skyeye-1.2.5_REL/0000755000175000001440000000000011023523237012234 5ustar kshusersskyeye-1.2.5_REL/LICENSE0000644000175000001440000000237210652645426013261 0ustar kshusersSkyEye in Linux or other NON-Windows Operating Systems uses GNU GENERAL PUBLIC LICENSE Version 2. The simulation code of ppc is originally developed by PearPC Project.Please see the license from header part of its source file .Its official website is http://pearpc.sourceforge.net/ The simulation code of coldfire under arch/coldfire is originally developed by David Grant. Please read its license from header of its source file. Its development site is http://www.slicer.ca/coldfire/index.php. All other part of SkyEye is developed by SkyEye Development Team. Copyright (C) 2003-2007 SkyEye Development Team. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission. skyeye-1.2.5_REL/depcomp0000644000175000001440000004224611006120657013616 0ustar kshusers#! /bin/sh # depcomp - compile a program generating dependencies as side-effects scriptversion=2006-10-15.18 # Copyright (C) 1999, 2000, 2003, 2004, 2005, 2006 Free Software # Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2, or (at your option) # any later version. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA # 02110-1301, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Alexandre Oliva . case $1 in '') echo "$0: No command. Try \`$0 --help' for more information." 1>&2 exit 1; ;; -h | --h*) cat <<\EOF Usage: depcomp [--help] [--version] PROGRAM [ARGS] Run PROGRAMS ARGS to compile a file, generating dependencies as side-effects. Environment variables: depmode Dependency tracking mode. source Source file read by `PROGRAMS ARGS'. object Object file output by `PROGRAMS ARGS'. DEPDIR directory where to store dependencies. depfile Dependency file to output. tmpdepfile Temporary file to use when outputing dependencies. libtool Whether libtool is used (yes/no). Report bugs to . EOF exit $? ;; -v | --v*) echo "depcomp $scriptversion" exit $? ;; esac if test -z "$depmode" || test -z "$source" || test -z "$object"; then echo "depcomp: Variables source, object and depmode must be set" 1>&2 exit 1 fi # Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. depfile=${depfile-`echo "$object" | sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} rm -f "$tmpdepfile" # Some modes work just like other modes, but use different flags. We # parameterize here, but still list the modes in the big case below, # to make depend.m4 easier to write. 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grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_gdi32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_gdi32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_gdi32_main" >&5 echo "${ECHO_T}$ac_cv_lib_gdi32_main" >&6; } if test $ac_cv_lib_gdi32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBGDI32 1 _ACEOF LIBS="-lgdi32 $LIBS" fi # FIXME: Replace `main' with a function in `-liberty': { echo "$as_me:$LINENO: checking for main in -liberty" >&5 echo $ECHO_N "checking for main in -liberty... $ECHO_C" >&6; } if test "${ac_cv_lib_iberty_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-liberty $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_iberty_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_iberty_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_iberty_main" >&5 echo "${ECHO_T}$ac_cv_lib_iberty_main" >&6; } if test $ac_cv_lib_iberty_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBIBERTY 1 _ACEOF LIBS="-liberty $LIBS" fi # FIXME: Replace `main' with a function in `-lintl': { echo "$as_me:$LINENO: checking for main in -lintl" >&5 echo $ECHO_N "checking for main in -lintl... $ECHO_C" >&6; } if test "${ac_cv_lib_intl_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lintl $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_intl_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_intl_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_intl_main" >&5 echo "${ECHO_T}$ac_cv_lib_intl_main" >&6; } if test $ac_cv_lib_intl_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBINTL 1 _ACEOF LIBS="-lintl $LIBS" fi # FIXME: Replace `main' with a function in `-lkernel32': { echo "$as_me:$LINENO: checking for main in -lkernel32" >&5 echo $ECHO_N "checking for main in -lkernel32... $ECHO_C" >&6; } if test "${ac_cv_lib_kernel32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lkernel32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_kernel32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_kernel32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_kernel32_main" >&5 echo "${ECHO_T}$ac_cv_lib_kernel32_main" >&6; } if test $ac_cv_lib_kernel32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBKERNEL32 1 _ACEOF LIBS="-lkernel32 $LIBS" fi # FIXME: Replace `main' with a function in `-lm': { echo "$as_me:$LINENO: checking for main in -lm" >&5 echo $ECHO_N "checking for main in -lm... $ECHO_C" >&6; } if test "${ac_cv_lib_m_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lm $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_m_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_m_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_m_main" >&5 echo "${ECHO_T}$ac_cv_lib_m_main" >&6; } if test $ac_cv_lib_m_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBM 1 _ACEOF LIBS="-lm $LIBS" fi # FIXME: Replace `main' with a function in `-lmsvcrt': { echo "$as_me:$LINENO: checking for main in -lmsvcrt" >&5 echo $ECHO_N "checking for main in -lmsvcrt... $ECHO_C" >&6; } if test "${ac_cv_lib_msvcrt_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lmsvcrt $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_msvcrt_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_msvcrt_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_msvcrt_main" >&5 echo "${ECHO_T}$ac_cv_lib_msvcrt_main" >&6; } if test $ac_cv_lib_msvcrt_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBMSVCRT 1 _ACEOF LIBS="-lmsvcrt $LIBS" fi # FIXME: Replace `main' with a function in `-ln': { echo "$as_me:$LINENO: checking for main in -ln" >&5 echo $ECHO_N "checking for main in -ln... $ECHO_C" >&6; } if test "${ac_cv_lib_n_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ln $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_n_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_n_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_n_main" >&5 echo "${ECHO_T}$ac_cv_lib_n_main" >&6; } if test $ac_cv_lib_n_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBN 1 _ACEOF LIBS="-ln $LIBS" fi # FIXME: Replace `main' with a function in `-lnet': { echo "$as_me:$LINENO: checking for main in -lnet" >&5 echo $ECHO_N "checking for main in -lnet... $ECHO_C" >&6; } if test "${ac_cv_lib_net_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lnet $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_net_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_net_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_net_main" >&5 echo "${ECHO_T}$ac_cv_lib_net_main" >&6; } if test $ac_cv_lib_net_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBNET 1 _ACEOF LIBS="-lnet $LIBS" fi # FIXME: Replace `main' with a function in `-lroot': { echo "$as_me:$LINENO: checking for main in -lroot" >&5 echo $ECHO_N "checking for main in -lroot... $ECHO_C" >&6; } if test "${ac_cv_lib_root_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lroot $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_root_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_root_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_root_main" >&5 echo "${ECHO_T}$ac_cv_lib_root_main" >&6; } if test $ac_cv_lib_root_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBROOT 1 _ACEOF LIBS="-lroot $LIBS" fi # FIXME: Replace `main' with a function in `-lsocket': { echo "$as_me:$LINENO: checking for main in -lsocket" >&5 echo $ECHO_N "checking for main in -lsocket... $ECHO_C" >&6; } if test "${ac_cv_lib_socket_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_socket_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_socket_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_socket_main" >&5 echo "${ECHO_T}$ac_cv_lib_socket_main" >&6; } if test $ac_cv_lib_socket_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBSOCKET 1 _ACEOF LIBS="-lsocket $LIBS" fi # FIXME: Replace `main' with a function in `-luser32': { echo "$as_me:$LINENO: checking for main in -luser32" >&5 echo $ECHO_N "checking for main in -luser32... $ECHO_C" >&6; } if test "${ac_cv_lib_user32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-luser32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_user32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_user32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_user32_main" >&5 echo "${ECHO_T}$ac_cv_lib_user32_main" >&6; } if test $ac_cv_lib_user32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBUSER32 1 _ACEOF LIBS="-luser32 $LIBS" fi # FIXME: Replace `main' with a function in `-lwinmm': { echo "$as_me:$LINENO: checking for main in -lwinmm" >&5 echo $ECHO_N "checking for main in -lwinmm... $ECHO_C" >&6; } if test "${ac_cv_lib_winmm_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lwinmm $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_winmm_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_winmm_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_winmm_main" >&5 echo "${ECHO_T}$ac_cv_lib_winmm_main" >&6; } if test $ac_cv_lib_winmm_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBWINMM 1 _ACEOF LIBS="-lwinmm $LIBS" fi # FIXME: Replace `main' with a function in `-lws2_32': { echo "$as_me:$LINENO: checking for main in -lws2_32" >&5 echo $ECHO_N "checking for main in -lws2_32... $ECHO_C" >&6; } if test "${ac_cv_lib_ws2_32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lws2_32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_ws2_32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_ws2_32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_ws2_32_main" >&5 echo "${ECHO_T}$ac_cv_lib_ws2_32_main" >&6; } if test $ac_cv_lib_ws2_32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBWS2_32 1 _ACEOF LIBS="-lws2_32 $LIBS" fi { echo "$as_me:$LINENO: checking for bfd_openr in -lbfd" >&5 echo $ECHO_N "checking for bfd_openr in -lbfd... $ECHO_C" >&6; } if test "${ac_cv_lib_bfd_bfd_openr+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lbfd $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char bfd_openr (); int main () { return bfd_openr (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_bfd_bfd_openr=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_bfd_bfd_openr=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_bfd_bfd_openr" >&5 echo "${ECHO_T}$ac_cv_lib_bfd_bfd_openr" >&6; } if test $ac_cv_lib_bfd_bfd_openr = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBBFD 1 _ACEOF LIBS="-lbfd $LIBS" fi # Checks for header files. { echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5 echo $ECHO_N "checking for grep that handles long lines and -e... $ECHO_C" >&6; } if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # Extract the first word of "grep ggrep" to use in msg output if test -z "$GREP"; then set dummy grep ggrep; ac_prog_name=$2 if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_GREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in grep ggrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue # Check for GNU ac_path_GREP and select it if it is found. # Check for GNU $ac_path_GREP case `"$ac_path_GREP" --version 2>&1` in *GNU*) ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'GREP' >> "conftest.nl" "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_GREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_GREP_found && break 3 done done done IFS=$as_save_IFS fi GREP="$ac_cv_path_GREP" if test -z "$GREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_GREP=$GREP fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5 echo "${ECHO_T}$ac_cv_path_GREP" >&6; } GREP="$ac_cv_path_GREP" { echo "$as_me:$LINENO: checking for egrep" >&5 echo $ECHO_N "checking for egrep... $ECHO_C" >&6; } if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 then ac_cv_path_EGREP="$GREP -E" else # Extract the first word of "egrep" to use in msg output if test -z "$EGREP"; then set dummy egrep; ac_prog_name=$2 if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_EGREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in egrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue # Check for GNU ac_path_EGREP and select it if it is found. # Check for GNU $ac_path_EGREP case `"$ac_path_EGREP" --version 2>&1` in *GNU*) ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'EGREP' >> "conftest.nl" "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_EGREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_EGREP_found && break 3 done done done IFS=$as_save_IFS fi EGREP="$ac_cv_path_EGREP" if test -z "$EGREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_EGREP=$EGREP fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5 echo "${ECHO_T}$ac_cv_path_EGREP" >&6; } EGREP="$ac_cv_path_EGREP" { echo "$as_me:$LINENO: checking for ANSI C header files" >&5 echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6; } if test "${ac_cv_header_stdc+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include #include int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdc=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "memchr" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "free" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. if test "$cross_compiling" = yes; then : else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #if ((' ' & 0x0FF) == 0x020) # define ISLOWER(c) ('a' <= (c) && (c) <= 'z') # define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) #else # define ISLOWER(c) \ (('a' <= (c) && (c) <= 'i') \ || ('j' <= (c) && (c) <= 'r') \ || ('s' <= (c) && (c) <= 'z')) # define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) #endif #define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) int main () { int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) return 2; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then : else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_header_stdc=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 echo "${ECHO_T}$ac_cv_header_stdc" >&6; } if test $ac_cv_header_stdc = yes; then cat >>confdefs.h <<\_ACEOF @%:@define STDC_HEADERS 1 _ACEOF fi # On IRIX 5.3, sys/types and inttypes.h are conflicting. for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ inttypes.h stdint.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then eval "$as_ac_Header=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_Header=no" fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_header in fcntl.h inttypes.h limits.h locale.h netdb.h netinet/in.h stddef.h stdint.h stdlib.h string.h sys/file.h sys/ioctl.h sys/socket.h sys/time.h termios.h unistd.h gtk/gtk.h bfd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done # Checks for typedefs, structures, and compiler characteristics. { echo "$as_me:$LINENO: checking for stdbool.h that conforms to C99" >&5 echo $ECHO_N "checking for stdbool.h that conforms to C99... $ECHO_C" >&6; } if test "${ac_cv_header_stdbool_h+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #ifndef bool "error: bool is not defined" #endif #ifndef false "error: false is not defined" #endif #if false "error: false is not 0" #endif #ifndef true "error: true is not defined" #endif #if true != 1 "error: true is not 1" #endif #ifndef __bool_true_false_are_defined "error: __bool_true_false_are_defined is not defined" #endif struct s { _Bool s: 1; _Bool t; } s; char a[true == 1 ? 1 : -1]; char b[false == 0 ? 1 : -1]; char c[__bool_true_false_are_defined == 1 ? 1 : -1]; char d[(bool) 0.5 == true ? 1 : -1]; bool e = &s; char f[(_Bool) 0.0 == false ? 1 : -1]; char g[true]; char h[sizeof (_Bool)]; char i[sizeof s.t]; enum { j = false, k = true, l = false * true, m = true * 256 }; _Bool n[m]; char o[sizeof n == m * sizeof n[0] ? 1 : -1]; char p[-1 - (_Bool) 0 < 0 && -1 - (bool) 0 < 0 ? 1 : -1]; # if defined __xlc__ || defined __GNUC__ /* Catch a bug in IBM AIX xlc compiler version 6.0.0.0 reported by James Lemley on 2005-10-05; see http://lists.gnu.org/archive/html/bug-coreutils/2005-10/msg00086.html This test is not quite right, since xlc is allowed to reject this program, as the initializer for xlcbug is not one of the forms that C requires support for. However, doing the test right would require a runtime test, and that would make cross-compilation harder. Let us hope that IBM fixes the xlc bug, and also adds support for this kind of constant expression. In the meantime, this test will reject xlc, which is OK, since our stdbool.h substitute should suffice. We also test this with GCC, where it should work, to detect more quickly whether someone messes up the test in the future. */ char digs[] = "0123456789"; int xlcbug = 1 / (&(digs + 5)[-2 + (bool) 1] == &digs[4] ? 1 : -1); # endif /* Catch a bug in an HP-UX C compiler. See http://gcc.gnu.org/ml/gcc-patches/2003-12/msg02303.html http://lists.gnu.org/archive/html/bug-coreutils/2005-11/msg00161.html */ _Bool q = true; _Bool *pq = &q; int main () { *pq |= q; *pq |= ! q; /* Refer to every declared value, to avoid compiler optimizations. */ return (!a + !b + !c + !d + !e + !f + !g + !h + !i + !!j + !k + !!l + !m + !n + !o + !p + !q + !pq); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdbool_h=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdbool_h=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdbool_h" >&5 echo "${ECHO_T}$ac_cv_header_stdbool_h" >&6; } { echo "$as_me:$LINENO: checking for _Bool" >&5 echo $ECHO_N "checking for _Bool... $ECHO_C" >&6; } if test "${ac_cv_type__Bool+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef _Bool ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type__Bool=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type__Bool=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type__Bool" >&5 echo "${ECHO_T}$ac_cv_type__Bool" >&6; } if test $ac_cv_type__Bool = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE__BOOL 1 _ACEOF fi if test $ac_cv_header_stdbool_h = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_STDBOOL_H 1 _ACEOF fi { echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6; } if test "${ac_cv_c_const+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { /* FIXME: Include the comments suggested by Paul. */ #ifndef __cplusplus /* Ultrix mips cc rejects this. */ typedef int charset[2]; const charset cs; /* SunOS 4.1.1 cc rejects this. */ char const *const *pcpcc; char **ppc; /* NEC SVR4.0.2 mips cc rejects this. */ struct point {int x, y;}; static struct point const zero = {0,0}; /* AIX XL C 1.02.0.0 rejects this. It does not let you subtract one const X* pointer from another in an arm of an if-expression whose if-part is not a constant expression */ const char *g = "string"; pcpcc = &g + (g ? g-g : 0); /* HPUX 7.0 cc rejects these. */ ++pcpcc; ppc = (char**) pcpcc; pcpcc = (char const *const *) ppc; { /* SCO 3.2v4 cc rejects this. */ char *t; char const *s = 0 ? (char *) 0 : (char const *) 0; *t++ = 0; if (s) return 0; } { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ int x[] = {25, 17}; const int *foo = &x[0]; ++foo; } { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ typedef const int *iptr; iptr p = 0; ++p; } { /* AIX XL C 1.02.0.0 rejects this saying "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ struct s { int j; const int *ap[3]; }; struct s *b; b->j = 5; } { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ const int foo = 10; if (!foo) return 0; } return !cs[0] && !zero.x; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_const=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_const=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 echo "${ECHO_T}$ac_cv_c_const" >&6; } if test $ac_cv_c_const = no; then cat >>confdefs.h <<\_ACEOF @%:@define const _ACEOF fi { echo "$as_me:$LINENO: checking for inline" >&5 echo $ECHO_N "checking for inline... $ECHO_C" >&6; } if test "${ac_cv_c_inline+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #ifndef __cplusplus typedef int foo_t; static $ac_kw foo_t static_foo () {return 0; } $ac_kw foo_t foo () {return 0; } #endif _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_inline=$ac_kw else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_inline" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5 echo "${ECHO_T}$ac_cv_c_inline" >&6; } case $ac_cv_c_inline in inline | yes) ;; *) case $ac_cv_c_inline in no) ac_val=;; *) ac_val=$ac_cv_c_inline;; esac cat >>confdefs.h <<_ACEOF #ifndef __cplusplus #define inline $ac_val #endif _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int16_t" >&5 echo $ECHO_N "checking for int16_t... $ECHO_C" >&6; } if test "${ac_cv_c_int16_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int16_t=no for ac_type in 'int16_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int16_t) ac_cv_c_int16_t=yes ;; *) ac_cv_c_int16_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int16_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int16_t" >&5 echo "${ECHO_T}$ac_cv_c_int16_t" >&6; } case $ac_cv_c_int16_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int16_t $ac_cv_c_int16_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int32_t" >&5 echo $ECHO_N "checking for int32_t... $ECHO_C" >&6; } if test "${ac_cv_c_int32_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int32_t=no for ac_type in 'int32_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int32_t) ac_cv_c_int32_t=yes ;; *) ac_cv_c_int32_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int32_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int32_t" >&5 echo "${ECHO_T}$ac_cv_c_int32_t" >&6; } case $ac_cv_c_int32_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int32_t $ac_cv_c_int32_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int64_t" >&5 echo $ECHO_N "checking for int64_t... $ECHO_C" >&6; } if test "${ac_cv_c_int64_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int64_t=no for ac_type in 'int64_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int64_t) ac_cv_c_int64_t=yes ;; *) ac_cv_c_int64_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int64_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int64_t" >&5 echo "${ECHO_T}$ac_cv_c_int64_t" >&6; } case $ac_cv_c_int64_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int64_t $ac_cv_c_int64_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int8_t" >&5 echo $ECHO_N "checking for int8_t... $ECHO_C" >&6; } if test "${ac_cv_c_int8_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int8_t=no for ac_type in 'int8_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int8_t) ac_cv_c_int8_t=yes ;; *) ac_cv_c_int8_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int8_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int8_t" >&5 echo "${ECHO_T}$ac_cv_c_int8_t" >&6; } case $ac_cv_c_int8_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int8_t $ac_cv_c_int8_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for off_t" >&5 echo $ECHO_N "checking for off_t... $ECHO_C" >&6; } if test "${ac_cv_type_off_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef off_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_off_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_off_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5 echo "${ECHO_T}$ac_cv_type_off_t" >&6; } if test $ac_cv_type_off_t = yes; then : else cat >>confdefs.h <<_ACEOF @%:@define off_t long int _ACEOF fi { echo "$as_me:$LINENO: checking for size_t" >&5 echo $ECHO_N "checking for size_t... $ECHO_C" >&6; } if test "${ac_cv_type_size_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef size_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_size_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_size_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5 echo "${ECHO_T}$ac_cv_type_size_t" >&6; } if test $ac_cv_type_size_t = yes; then : else cat >>confdefs.h <<_ACEOF @%:@define size_t unsigned int _ACEOF fi { echo "$as_me:$LINENO: checking for ssize_t" >&5 echo $ECHO_N "checking for ssize_t... $ECHO_C" >&6; } if test "${ac_cv_type_ssize_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef ssize_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_ssize_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_ssize_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_ssize_t" >&5 echo "${ECHO_T}$ac_cv_type_ssize_t" >&6; } if test $ac_cv_type_ssize_t = yes; then : else cat >>confdefs.h <<_ACEOF @%:@define ssize_t int _ACEOF fi { echo "$as_me:$LINENO: checking whether time.h and sys/time.h may both be included" >&5 echo $ECHO_N "checking whether time.h and sys/time.h may both be included... $ECHO_C" >&6; } if test "${ac_cv_header_time+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include int main () { if ((struct tm *) 0) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_time=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_time=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_time" >&5 echo "${ECHO_T}$ac_cv_header_time" >&6; } if test $ac_cv_header_time = yes; then cat >>confdefs.h <<\_ACEOF @%:@define TIME_WITH_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking whether struct tm is in sys/time.h or time.h" >&5 echo $ECHO_N "checking whether struct tm is in sys/time.h or time.h... $ECHO_C" >&6; } if test "${ac_cv_struct_tm+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include int main () { struct tm tm; int *p = &tm.tm_sec; return !p; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_struct_tm=time.h else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_struct_tm=sys/time.h fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_struct_tm" >&5 echo "${ECHO_T}$ac_cv_struct_tm" >&6; } if test $ac_cv_struct_tm = sys/time.h; then cat >>confdefs.h <<\_ACEOF @%:@define TM_IN_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking for uid_t in sys/types.h" >&5 echo $ECHO_N "checking for uid_t in sys/types.h... $ECHO_C" >&6; } if test "${ac_cv_type_uid_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "uid_t" >/dev/null 2>&1; then ac_cv_type_uid_t=yes else ac_cv_type_uid_t=no fi rm -f conftest* fi { echo "$as_me:$LINENO: result: $ac_cv_type_uid_t" >&5 echo "${ECHO_T}$ac_cv_type_uid_t" >&6; } if test $ac_cv_type_uid_t = no; then cat >>confdefs.h <<\_ACEOF @%:@define uid_t int _ACEOF cat >>confdefs.h <<\_ACEOF @%:@define gid_t int _ACEOF fi { echo "$as_me:$LINENO: checking for uint16_t" >&5 echo $ECHO_N "checking for uint16_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint16_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint16_t=no for ac_type in 'uint16_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) -1 >> (16 - 1) == 1)@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? 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{ echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for GNU libc compatible malloc" >&5 echo $ECHO_N "checking for GNU libc compatible malloc... $ECHO_C" >&6; } if test "${ac_cv_func_malloc_0_nonnull+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_malloc_0_nonnull=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined STDC_HEADERS || defined HAVE_STDLIB_H # include #else char *malloc (); #endif int main () { return ! malloc (0); ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_malloc_0_nonnull=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_malloc_0_nonnull=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_malloc_0_nonnull" >&5 echo "${ECHO_T}$ac_cv_func_malloc_0_nonnull" >&6; } if test $ac_cv_func_malloc_0_nonnull = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_MALLOC 1 _ACEOF else cat >>confdefs.h <<\_ACEOF @%:@define HAVE_MALLOC 0 _ACEOF case " $LIB@&t@OBJS " in *" malloc.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS malloc.$ac_objext" ;; esac cat >>confdefs.h <<\_ACEOF @%:@define malloc rpl_malloc _ACEOF fi { echo "$as_me:$LINENO: checking for working memcmp" >&5 echo $ECHO_N "checking for working memcmp... $ECHO_C" >&6; } if test "${ac_cv_func_memcmp_working+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_memcmp_working=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { /* Some versions of memcmp are not 8-bit clean. */ char c0 = '\100', c1 = '\200', c2 = '\201'; if (memcmp(&c0, &c2, 1) >= 0 || memcmp(&c1, &c2, 1) >= 0) return 1; /* The Next x86 OpenStep bug shows up only when comparing 16 bytes or more and with at least one buffer not starting on a 4-byte boundary. William Lewis provided this test program. */ { char foo[21]; char bar[21]; int i; for (i = 0; i < 4; i++) { char *a = foo + i; char *b = bar + i; strcpy (a, "--------01111111"); strcpy (b, "--------10000000"); if (memcmp (a, b, 16) >= 0) return 1; } return 0; } ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_memcmp_working=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_memcmp_working=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_memcmp_working" >&5 echo "${ECHO_T}$ac_cv_func_memcmp_working" >&6; } test $ac_cv_func_memcmp_working = no && case " $LIB@&t@OBJS " in *" memcmp.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS memcmp.$ac_objext" ;; esac for ac_header in $ac_header_list do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_func in $ac_func_list do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. For example, HP-UX 11i declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for working mktime" >&5 echo $ECHO_N "checking for working mktime... $ECHO_C" >&6; } if test "${ac_cv_func_working_mktime+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_working_mktime=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Test program from Paul Eggert and Tony Leneis. */ #ifdef TIME_WITH_SYS_TIME # include # include #else # ifdef HAVE_SYS_TIME_H # include # else # include # endif #endif #include #ifdef HAVE_UNISTD_H # include #endif #ifndef HAVE_ALARM # define alarm(X) /* empty */ #endif /* Work around redefinition to rpl_putenv by other config tests. */ #undef putenv static time_t time_t_max; static time_t time_t_min; /* Values we'll use to set the TZ environment variable. */ static char *tz_strings[] = { (char *) 0, "TZ=GMT0", "TZ=JST-9", "TZ=EST+3EDT+2,M10.1.0/00:00:00,M2.3.0/00:00:00" }; #define N_STRINGS (sizeof (tz_strings) / sizeof (tz_strings[0])) /* Return 0 if mktime fails to convert a date in the spring-forward gap. Based on a problem report from Andreas Jaeger. */ static int spring_forward_gap () { /* glibc (up to about 1998-10-07) failed this test. */ struct tm tm; /* Use the portable POSIX.1 specification "TZ=PST8PDT,M4.1.0,M10.5.0" instead of "TZ=America/Vancouver" in order to detect the bug even on systems that don't support the Olson extension, or don't have the full zoneinfo tables installed. */ putenv ("TZ=PST8PDT,M4.1.0,M10.5.0"); tm.tm_year = 98; tm.tm_mon = 3; tm.tm_mday = 5; tm.tm_hour = 2; tm.tm_min = 0; tm.tm_sec = 0; tm.tm_isdst = -1; return mktime (&tm) != (time_t) -1; } static int mktime_test1 (now) time_t now; { struct tm *lt; return ! (lt = localtime (&now)) || mktime (lt) == now; } static int mktime_test (now) time_t now; { return (mktime_test1 (now) && mktime_test1 ((time_t) (time_t_max - now)) && mktime_test1 ((time_t) (time_t_min + now))); } static int irix_6_4_bug () { /* Based on code from Ariel Faigon. */ struct tm tm; tm.tm_year = 96; tm.tm_mon = 3; tm.tm_mday = 0; tm.tm_hour = 0; tm.tm_min = 0; tm.tm_sec = 0; tm.tm_isdst = -1; mktime (&tm); return tm.tm_mon == 2 && tm.tm_mday == 31; } static int bigtime_test (j) int j; { struct tm tm; time_t now; tm.tm_year = tm.tm_mon = tm.tm_mday = tm.tm_hour = tm.tm_min = tm.tm_sec = j; now = mktime (&tm); if (now != (time_t) -1) { struct tm *lt = localtime (&now); if (! (lt && lt->tm_year == tm.tm_year && lt->tm_mon == tm.tm_mon && lt->tm_mday == tm.tm_mday && lt->tm_hour == tm.tm_hour && lt->tm_min == tm.tm_min && lt->tm_sec == tm.tm_sec && lt->tm_yday == tm.tm_yday && lt->tm_wday == tm.tm_wday && ((lt->tm_isdst < 0 ? -1 : 0 < lt->tm_isdst) == (tm.tm_isdst < 0 ? -1 : 0 < tm.tm_isdst)))) return 0; } return 1; } static int year_2050_test () { /* The correct answer for 2050-02-01 00:00:00 in Pacific time, ignoring leap seconds. */ unsigned long int answer = 2527315200UL; struct tm tm; time_t t; tm.tm_year = 2050 - 1900; tm.tm_mon = 2 - 1; tm.tm_mday = 1; tm.tm_hour = tm.tm_min = tm.tm_sec = 0; tm.tm_isdst = -1; /* Use the portable POSIX.1 specification "TZ=PST8PDT,M4.1.0,M10.5.0" instead of "TZ=America/Vancouver" in order to detect the bug even on systems that don't support the Olson extension, or don't have the full zoneinfo tables installed. */ putenv ("TZ=PST8PDT,M4.1.0,M10.5.0"); t = mktime (&tm); /* Check that the result is either a failure, or close enough to the correct answer that we can assume the discrepancy is due to leap seconds. */ return (t == (time_t) -1 || (0 < t && answer - 120 <= t && t <= answer + 120)); } int main () { time_t t, delta; int i, j; /* This test makes some buggy mktime implementations loop. Give up after 60 seconds; a mktime slower than that isn't worth using anyway. */ alarm (60); for (time_t_max = 1; 0 < time_t_max; time_t_max *= 2) continue; time_t_max--; if ((time_t) -1 < 0) for (time_t_min = -1; (time_t) (time_t_min * 2) < 0; time_t_min *= 2) continue; delta = time_t_max / 997; /* a suitable prime number */ for (i = 0; i < N_STRINGS; i++) { if (tz_strings[i]) putenv (tz_strings[i]); for (t = 0; t <= time_t_max - delta; t += delta) if (! mktime_test (t)) return 1; if (! (mktime_test ((time_t) 1) && mktime_test ((time_t) (60 * 60)) && mktime_test ((time_t) (60 * 60 * 24)))) return 1; for (j = 1; 0 < j; j *= 2) if (! bigtime_test (j)) return 1; if (! bigtime_test (j - 1)) return 1; } return ! (irix_6_4_bug () && spring_forward_gap () && year_2050_test ()); } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_working_mktime=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_working_mktime=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_working_mktime" >&5 echo "${ECHO_T}$ac_cv_func_working_mktime" >&6; } if test $ac_cv_func_working_mktime = no; then case " $LIB@&t@OBJS " in *" mktime.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS mktime.$ac_objext" ;; esac fi for ac_header in stdlib.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_func in getpagesize do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. For example, HP-UX 11i declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for working mmap" >&5 echo $ECHO_N "checking for working mmap... $ECHO_C" >&6; } if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_mmap_fixed_mapped=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default /* malloc might have been renamed as rpl_malloc. */ #undef malloc /* Thanks to Mike Haertel and Jim Avera for this test. Here is a matrix of mmap possibilities: mmap private not fixed mmap private fixed at somewhere currently unmapped mmap private fixed at somewhere already mapped mmap shared not fixed mmap shared fixed at somewhere currently unmapped mmap shared fixed at somewhere already mapped For private mappings, we should verify that changes cannot be read() back from the file, nor mmap's back from the file at a different address. (There have been systems where private was not correctly implemented like the infamous i386 svr4.0, and systems where the VM page cache was not coherent with the file system buffer cache like early versions of FreeBSD and possibly contemporary NetBSD.) For shared mappings, we should conversely verify that changes get propagated back to all the places they're supposed to be. Grep wants private fixed already mapped. The main things grep needs to know about mmap are: * does it exist and is it safe to write into the mmap'd area * how to use it (BSD variants) */ #include #include #if !defined STDC_HEADERS && !defined HAVE_STDLIB_H char *malloc (); #endif /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H # define HAVE_SYS_PARAM_H 1 # endif # ifdef _SC_PAGESIZE # define getpagesize() sysconf(_SC_PAGESIZE) # else /* no _SC_PAGESIZE */ # ifdef HAVE_SYS_PARAM_H # include # ifdef EXEC_PAGESIZE # define getpagesize() EXEC_PAGESIZE # else /* no EXEC_PAGESIZE */ # ifdef NBPG # define getpagesize() NBPG * CLSIZE # ifndef CLSIZE # define CLSIZE 1 # endif /* no CLSIZE */ # else /* no NBPG */ # ifdef NBPC # define getpagesize() NBPC # else /* no NBPC */ # ifdef PAGESIZE # define getpagesize() PAGESIZE # endif /* PAGESIZE */ # endif /* no NBPC */ # endif /* no NBPG */ # endif /* no EXEC_PAGESIZE */ # else /* no HAVE_SYS_PARAM_H */ # define getpagesize() 8192 /* punt totally */ # endif /* no HAVE_SYS_PARAM_H */ # endif /* no _SC_PAGESIZE */ #endif /* no HAVE_GETPAGESIZE */ int main () { char *data, *data2, *data3; int i, pagesize; int fd; pagesize = getpagesize (); /* First, make a file with some known garbage in it. */ data = (char *) malloc (pagesize); if (!data) return 1; for (i = 0; i < pagesize; ++i) *(data + i) = rand (); umask (0); fd = creat ("conftest.mmap", 0600); if (fd < 0) return 1; if (write (fd, data, pagesize) != pagesize) return 1; close (fd); /* Next, try to mmap the file at a fixed address which already has something else allocated at it. If we can, also make sure that we see the same garbage. */ fd = open ("conftest.mmap", O_RDWR); if (fd < 0) return 1; data2 = (char *) malloc (2 * pagesize); if (!data2) return 1; data2 += (pagesize - ((long int) data2 & (pagesize - 1))) & (pagesize - 1); if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_FIXED, fd, 0L)) return 1; for (i = 0; i < pagesize; ++i) if (*(data + i) != *(data2 + i)) return 1; /* Finally, make sure that changes to the mapped area do not percolate back to the file as seen by read(). (This is a bug on some variants of i386 svr4.0.) */ for (i = 0; i < pagesize; ++i) *(data2 + i) = *(data2 + i) + 1; data3 = (char *) malloc (pagesize); if (!data3) return 1; if (read (fd, data3, pagesize) != pagesize) return 1; for (i = 0; i < pagesize; ++i) if (*(data + i) != *(data3 + i)) return 1; close (fd); return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_mmap_fixed_mapped=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_mmap_fixed_mapped=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5 echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6; } if test $ac_cv_func_mmap_fixed_mapped = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_MMAP 1 _ACEOF fi rm -f conftest.mmap for ac_header in stdlib.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for GNU libc compatible realloc" >&5 echo $ECHO_N "checking for GNU libc compatible realloc... $ECHO_C" >&6; } if test "${ac_cv_func_realloc_0_nonnull+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_realloc_0_nonnull=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined STDC_HEADERS || defined HAVE_STDLIB_H # include #else char *realloc (); #endif int main () { return ! realloc (0, 0); ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_realloc_0_nonnull=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_realloc_0_nonnull=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_realloc_0_nonnull" >&5 echo "${ECHO_T}$ac_cv_func_realloc_0_nonnull" >&6; } if test $ac_cv_func_realloc_0_nonnull = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_REALLOC 1 _ACEOF else cat >>confdefs.h <<\_ACEOF @%:@define HAVE_REALLOC 0 _ACEOF case " $LIB@&t@OBJS " in *" realloc.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS realloc.$ac_objext" ;; esac cat >>confdefs.h <<\_ACEOF @%:@define realloc rpl_realloc _ACEOF fi for ac_header in sys/select.h sys/socket.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking types of arguments for select" >&5 echo $ECHO_N "checking types of arguments for select... $ECHO_C" >&6; } if test "${ac_cv_func_select_args+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else for ac_arg234 in 'fd_set *' 'int *' 'void *'; do for ac_arg1 in 'int' 'size_t' 'unsigned long int' 'unsigned int'; do for ac_arg5 in 'struct timeval *' 'const struct timeval *'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #ifdef HAVE_SYS_SELECT_H # include #endif #ifdef HAVE_SYS_SOCKET_H # include #endif int main () { extern int select ($ac_arg1, $ac_arg234, $ac_arg234, $ac_arg234, $ac_arg5); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? 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m4_pattern_allow([^LCD_TRUE$]) m4trace:configure.in:62: -1- AC_SUBST([LCD_FALSE]) m4trace:configure.in:62: -1- AC_SUBST_TRACE([LCD_FALSE]) m4trace:configure.in:62: -1- m4_pattern_allow([^LCD_FALSE$]) m4trace:configure.in:62: -1- _AM_SUBST_NOTMAKE([LCD_TRUE]) m4trace:configure.in:62: -1- _AM_SUBST_NOTMAKE([LCD_FALSE]) m4trace:configure.in:66: -1- AH_OUTPUT([HAVE_LIBADVAPI32], [/* Define to 1 if you have the `advapi32\' library (-ladvapi32). */ #undef HAVE_LIBADVAPI32]) m4trace:configure.in:66: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBADVAPI32]) m4trace:configure.in:66: -1- m4_pattern_allow([^HAVE_LIBADVAPI32$]) m4trace:configure.in:68: -1- AH_OUTPUT([HAVE_LIBBE], [/* Define to 1 if you have the `be\' library (-lbe). */ #undef HAVE_LIBBE]) m4trace:configure.in:68: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBBE]) m4trace:configure.in:68: -1- m4_pattern_allow([^HAVE_LIBBE$]) m4trace:configure.in:70: -1- AH_OUTPUT([HAVE_LIBC], [/* Define to 1 if you have the `c\' library (-lc). */ #undef HAVE_LIBC]) m4trace:configure.in:70: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBC]) m4trace:configure.in:70: -1- m4_pattern_allow([^HAVE_LIBC$]) m4trace:configure.in:72: -1- AH_OUTPUT([HAVE_LIBGDI32], [/* Define to 1 if you have the `gdi32\' library (-lgdi32). */ #undef HAVE_LIBGDI32]) m4trace:configure.in:72: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBGDI32]) m4trace:configure.in:72: -1- m4_pattern_allow([^HAVE_LIBGDI32$]) m4trace:configure.in:74: -1- AH_OUTPUT([HAVE_LIBIBERTY], [/* Define to 1 if you have the `iberty\' library (-liberty). */ #undef HAVE_LIBIBERTY]) m4trace:configure.in:74: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBIBERTY]) m4trace:configure.in:74: -1- m4_pattern_allow([^HAVE_LIBIBERTY$]) m4trace:configure.in:76: -1- AH_OUTPUT([HAVE_LIBINTL], [/* Define to 1 if you have the `intl\' library (-lintl). */ #undef HAVE_LIBINTL]) m4trace:configure.in:76: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBINTL]) m4trace:configure.in:76: -1- m4_pattern_allow([^HAVE_LIBINTL$]) m4trace:configure.in:78: -1- AH_OUTPUT([HAVE_LIBKERNEL32], [/* Define to 1 if you have the `kernel32\' library (-lkernel32). */ #undef HAVE_LIBKERNEL32]) m4trace:configure.in:78: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBKERNEL32]) m4trace:configure.in:78: -1- m4_pattern_allow([^HAVE_LIBKERNEL32$]) m4trace:configure.in:80: -1- AH_OUTPUT([HAVE_LIBM], [/* Define to 1 if you have the `m\' library (-lm). */ #undef HAVE_LIBM]) m4trace:configure.in:80: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBM]) m4trace:configure.in:80: -1- m4_pattern_allow([^HAVE_LIBM$]) m4trace:configure.in:82: -1- AH_OUTPUT([HAVE_LIBMSVCRT], [/* Define to 1 if you have the `msvcrt\' library (-lmsvcrt). */ #undef HAVE_LIBMSVCRT]) m4trace:configure.in:82: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBMSVCRT]) m4trace:configure.in:82: -1- m4_pattern_allow([^HAVE_LIBMSVCRT$]) m4trace:configure.in:84: -1- AH_OUTPUT([HAVE_LIBN], [/* Define to 1 if you have the `n\' library (-ln). */ #undef HAVE_LIBN]) m4trace:configure.in:84: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBN]) m4trace:configure.in:84: -1- m4_pattern_allow([^HAVE_LIBN$]) m4trace:configure.in:86: -1- AH_OUTPUT([HAVE_LIBNET], [/* Define to 1 if you have the `net\' library (-lnet). */ #undef HAVE_LIBNET]) m4trace:configure.in:86: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBNET]) m4trace:configure.in:86: -1- m4_pattern_allow([^HAVE_LIBNET$]) m4trace:configure.in:88: -1- AH_OUTPUT([HAVE_LIBROOT], [/* Define to 1 if you have the `root\' library (-lroot). */ #undef HAVE_LIBROOT]) m4trace:configure.in:88: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBROOT]) m4trace:configure.in:88: -1- m4_pattern_allow([^HAVE_LIBROOT$]) m4trace:configure.in:90: -1- AH_OUTPUT([HAVE_LIBSOCKET], [/* Define to 1 if you have the `socket\' library (-lsocket). */ #undef HAVE_LIBSOCKET]) m4trace:configure.in:90: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBSOCKET]) m4trace:configure.in:90: -1- m4_pattern_allow([^HAVE_LIBSOCKET$]) m4trace:configure.in:92: -1- AH_OUTPUT([HAVE_LIBUSER32], [/* Define to 1 if you have the `user32\' library (-luser32). */ #undef HAVE_LIBUSER32]) m4trace:configure.in:92: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBUSER32]) m4trace:configure.in:92: -1- m4_pattern_allow([^HAVE_LIBUSER32$]) m4trace:configure.in:94: -1- AH_OUTPUT([HAVE_LIBWINMM], [/* Define to 1 if you have the `winmm\' library (-lwinmm). */ #undef HAVE_LIBWINMM]) m4trace:configure.in:94: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBWINMM]) m4trace:configure.in:94: -1- m4_pattern_allow([^HAVE_LIBWINMM$]) m4trace:configure.in:96: -1- AH_OUTPUT([HAVE_LIBWS2_32], [/* Define to 1 if you have the `ws2_32\' library (-lws2_32). */ #undef HAVE_LIBWS2_32]) m4trace:configure.in:96: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBWS2_32]) m4trace:configure.in:96: -1- m4_pattern_allow([^HAVE_LIBWS2_32$]) m4trace:configure.in:98: -1- AH_OUTPUT([HAVE_LIBBFD], [/* Define to 1 if you have the `bfd\' library (-lbfd). */ #undef HAVE_LIBBFD]) m4trace:configure.in:98: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBBFD]) m4trace:configure.in:98: -1- m4_pattern_allow([^HAVE_LIBBFD$]) m4trace:configure.in:101: -1- AC_SUBST([GREP]) m4trace:configure.in:101: -1- AC_SUBST_TRACE([GREP]) m4trace:configure.in:101: -1- m4_pattern_allow([^GREP$]) m4trace:configure.in:101: -1- AC_SUBST([GREP]) m4trace:configure.in:101: -1- AC_SUBST_TRACE([GREP]) m4trace:configure.in:101: -1- m4_pattern_allow([^GREP$]) m4trace:configure.in:101: -1- AC_SUBST([EGREP]) m4trace:configure.in:101: -1- AC_SUBST_TRACE([EGREP]) m4trace:configure.in:101: -1- m4_pattern_allow([^EGREP$]) m4trace:configure.in:101: -1- AC_SUBST([EGREP]) m4trace:configure.in:101: -1- AC_SUBST_TRACE([EGREP]) m4trace:configure.in:101: -1- m4_pattern_allow([^EGREP$]) m4trace:configure.in:101: -1- AC_DEFINE_TRACE_LITERAL([STDC_HEADERS]) m4trace:configure.in:101: -1- m4_pattern_allow([^STDC_HEADERS$]) m4trace:configure.in:101: -1- AH_OUTPUT([STDC_HEADERS], [/* Define to 1 if you have the ANSI C header files. */ #undef STDC_HEADERS]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_FCNTL_H], [/* Define to 1 if you have the header file. */ #undef HAVE_FCNTL_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_INTTYPES_H], [/* Define to 1 if you have the header file. */ #undef HAVE_INTTYPES_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_LIMITS_H], [/* Define to 1 if you have the header file. */ #undef HAVE_LIMITS_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_LOCALE_H], [/* Define to 1 if you have the header file. */ #undef HAVE_LOCALE_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_NETDB_H], [/* Define to 1 if you have the header file. */ #undef HAVE_NETDB_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_NETINET_IN_H], [/* Define to 1 if you have the header file. */ #undef HAVE_NETINET_IN_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STDDEF_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STDDEF_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STDINT_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STDINT_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STDLIB_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STDLIB_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STRING_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STRING_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_SYS_FILE_H], [/* Define to 1 if you have the header file. */ #undef HAVE_SYS_FILE_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_SYS_IOCTL_H], [/* Define to 1 if you have the header file. */ #undef HAVE_SYS_IOCTL_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_SYS_SOCKET_H], [/* Define to 1 if you have the header file. */ #undef HAVE_SYS_SOCKET_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_SYS_TIME_H], [/* Define to 1 if you have the header file. */ #undef HAVE_SYS_TIME_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_TERMIOS_H], [/* Define to 1 if you have the header file. */ #undef HAVE_TERMIOS_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_UNISTD_H], [/* Define to 1 if you have the header file. */ #undef HAVE_UNISTD_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_GTK_GTK_H], [/* Define to 1 if you have the header file. */ #undef HAVE_GTK_GTK_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_BFD_H], [/* Define to 1 if you have the header file. */ #undef HAVE_BFD_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_SYS_TYPES_H], [/* Define to 1 if you have the header file. */ #undef HAVE_SYS_TYPES_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_SYS_STAT_H], [/* Define to 1 if you have the header file. */ #undef HAVE_SYS_STAT_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STDLIB_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STDLIB_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STRING_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STRING_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_MEMORY_H], [/* Define to 1 if you have the header file. */ #undef HAVE_MEMORY_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STRINGS_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STRINGS_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_INTTYPES_H], [/* Define to 1 if you have the header file. */ #undef HAVE_INTTYPES_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_STDINT_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STDINT_H]) m4trace:configure.in:102: -1- AH_OUTPUT([HAVE_UNISTD_H], [/* Define to 1 if you have the header file. */ #undef HAVE_UNISTD_H]) m4trace:configure.in:105: -1- AC_DEFINE_TRACE_LITERAL([HAVE__BOOL]) m4trace:configure.in:105: -1- m4_pattern_allow([^HAVE__BOOL$]) m4trace:configure.in:105: -1- AH_OUTPUT([HAVE__BOOL], [/* Define to 1 if the system has the type `_Bool\'. */ #undef HAVE__BOOL]) m4trace:configure.in:105: -1- AC_DEFINE_TRACE_LITERAL([HAVE_STDBOOL_H]) m4trace:configure.in:105: -1- m4_pattern_allow([^HAVE_STDBOOL_H$]) m4trace:configure.in:105: -1- AH_OUTPUT([HAVE_STDBOOL_H], [/* Define to 1 if stdbool.h conforms to C99. */ #undef HAVE_STDBOOL_H]) m4trace:configure.in:106: -1- AC_DEFINE_TRACE_LITERAL([const]) m4trace:configure.in:106: -1- m4_pattern_allow([^const$]) m4trace:configure.in:106: -1- AH_OUTPUT([const], [/* Define to empty if `const\' does not conform to ANSI C. */ #undef const]) m4trace:configure.in:107: -1- AH_OUTPUT([inline], [/* Define to `__inline__\' or `__inline\' if that\'s what the C compiler calls it, or to nothing if \'inline\' is not supported under any name. */ #ifndef __cplusplus #undef inline #endif]) m4trace:configure.in:108: -1- AC_DEFINE_TRACE_LITERAL([int16_t]) m4trace:configure.in:108: -1- m4_pattern_allow([^int16_t$]) m4trace:configure.in:108: -1- AH_OUTPUT([int16_t], [/* Define to the type of a signed integer type of width exactly 16 bits if such a type exists and the standard includes do not define it. */ #undef int16_t]) m4trace:configure.in:109: -1- AC_DEFINE_TRACE_LITERAL([int32_t]) m4trace:configure.in:109: -1- m4_pattern_allow([^int32_t$]) m4trace:configure.in:109: -1- AH_OUTPUT([int32_t], [/* Define to the type of a signed integer type of width exactly 32 bits if such a type exists and the standard includes do not define it. */ #undef int32_t]) m4trace:configure.in:110: -1- AC_DEFINE_TRACE_LITERAL([int64_t]) m4trace:configure.in:110: -1- m4_pattern_allow([^int64_t$]) m4trace:configure.in:110: -1- AH_OUTPUT([int64_t], [/* Define to the type of a signed integer type of width exactly 64 bits if such a type exists and the standard includes do not define it. */ #undef int64_t]) m4trace:configure.in:111: -1- AC_DEFINE_TRACE_LITERAL([int8_t]) m4trace:configure.in:111: -1- m4_pattern_allow([^int8_t$]) m4trace:configure.in:111: -1- AH_OUTPUT([int8_t], [/* Define to the type of a signed integer type of width exactly 8 bits if such a type exists and the standard includes do not define it. */ #undef int8_t]) m4trace:configure.in:112: -1- AC_DEFINE_TRACE_LITERAL([off_t]) m4trace:configure.in:112: -1- m4_pattern_allow([^off_t$]) m4trace:configure.in:112: -1- AH_OUTPUT([off_t], [/* Define to `long int\' if does not define. */ #undef off_t]) m4trace:configure.in:113: -1- AC_DEFINE_TRACE_LITERAL([size_t]) m4trace:configure.in:113: -1- m4_pattern_allow([^size_t$]) m4trace:configure.in:113: -1- AH_OUTPUT([size_t], [/* Define to `unsigned int\' if does not define. */ #undef size_t]) m4trace:configure.in:114: -1- AC_DEFINE_TRACE_LITERAL([ssize_t]) m4trace:configure.in:114: -1- m4_pattern_allow([^ssize_t$]) m4trace:configure.in:114: -1- AH_OUTPUT([ssize_t], [/* Define to `int\' if does not define. */ #undef ssize_t]) m4trace:configure.in:115: -1- AC_DEFINE_TRACE_LITERAL([TIME_WITH_SYS_TIME]) m4trace:configure.in:115: -1- m4_pattern_allow([^TIME_WITH_SYS_TIME$]) m4trace:configure.in:115: -1- AH_OUTPUT([TIME_WITH_SYS_TIME], [/* Define to 1 if you can safely include both and . */ #undef TIME_WITH_SYS_TIME]) m4trace:configure.in:116: -1- AC_DEFINE_TRACE_LITERAL([TM_IN_SYS_TIME]) m4trace:configure.in:116: -1- m4_pattern_allow([^TM_IN_SYS_TIME$]) m4trace:configure.in:116: -1- AH_OUTPUT([TM_IN_SYS_TIME], [/* Define to 1 if your declares `struct tm\'. */ #undef TM_IN_SYS_TIME]) m4trace:configure.in:117: -1- AC_DEFINE_TRACE_LITERAL([uid_t]) m4trace:configure.in:117: -1- m4_pattern_allow([^uid_t$]) m4trace:configure.in:117: -1- AH_OUTPUT([uid_t], [/* Define to `int\' if doesn\'t define. */ #undef uid_t]) m4trace:configure.in:117: -1- AC_DEFINE_TRACE_LITERAL([gid_t]) m4trace:configure.in:117: -1- m4_pattern_allow([^gid_t$]) m4trace:configure.in:117: -1- AH_OUTPUT([gid_t], [/* Define to `int\' if doesn\'t define. */ #undef gid_t]) m4trace:configure.in:118: -1- AC_DEFINE_TRACE_LITERAL([uint16_t]) m4trace:configure.in:118: -1- m4_pattern_allow([^uint16_t$]) m4trace:configure.in:118: -1- AH_OUTPUT([uint16_t], [/* Define to the type of an unsigned integer type of width exactly 16 bits if such a type exists and the standard includes do not define it. */ #undef uint16_t]) m4trace:configure.in:119: -1- AC_DEFINE_TRACE_LITERAL([_UINT32_T]) m4trace:configure.in:119: -1- m4_pattern_allow([^_UINT32_T$]) m4trace:configure.in:119: -1- AH_OUTPUT([_UINT32_T], [/* Define for Solaris 2.5.1 so the uint32_t typedef from , , or is not used. If the typedef was allowed, the #define below would cause a syntax error. */ #undef _UINT32_T]) m4trace:configure.in:119: -1- AC_DEFINE_TRACE_LITERAL([uint32_t]) m4trace:configure.in:119: -1- m4_pattern_allow([^uint32_t$]) m4trace:configure.in:119: -1- AH_OUTPUT([uint32_t], [/* Define to the type of an unsigned integer type of width exactly 32 bits if such a type exists and the standard includes do not define it. */ #undef uint32_t]) m4trace:configure.in:120: -1- AC_DEFINE_TRACE_LITERAL([_UINT64_T]) m4trace:configure.in:120: -1- m4_pattern_allow([^_UINT64_T$]) m4trace:configure.in:120: -1- AH_OUTPUT([_UINT64_T], [/* Define for Solaris 2.5.1 so the uint64_t typedef from , , or is not used. If the typedef was allowed, the #define below would cause a syntax error. */ #undef _UINT64_T]) m4trace:configure.in:120: -1- AC_DEFINE_TRACE_LITERAL([uint64_t]) m4trace:configure.in:120: -1- m4_pattern_allow([^uint64_t$]) m4trace:configure.in:120: -1- AH_OUTPUT([uint64_t], [/* Define to the type of an unsigned integer type of width exactly 64 bits if such a type exists and the standard includes do not define it. */ #undef uint64_t]) m4trace:configure.in:121: -1- AC_DEFINE_TRACE_LITERAL([_UINT8_T]) m4trace:configure.in:121: -1- m4_pattern_allow([^_UINT8_T$]) m4trace:configure.in:121: -1- AH_OUTPUT([_UINT8_T], [/* Define for Solaris 2.5.1 so the uint8_t typedef from , , or is not used. If the typedef was allowed, the #define below would cause a syntax error. */ #undef _UINT8_T]) m4trace:configure.in:121: -1- AC_DEFINE_TRACE_LITERAL([uint8_t]) m4trace:configure.in:121: -1- m4_pattern_allow([^uint8_t$]) m4trace:configure.in:121: -1- AH_OUTPUT([uint8_t], [/* Define to the type of an unsigned integer type of width exactly 8 bits if such a type exists and the standard includes do not define it. */ #undef uint8_t]) m4trace:configure.in:122: -1- AC_DEFINE_TRACE_LITERAL([volatile]) m4trace:configure.in:122: -1- m4_pattern_allow([^volatile$]) m4trace:configure.in:122: -1- AH_OUTPUT([volatile], [/* Define to empty if the keyword `volatile\' does not work. Warning: valid code using `volatile\' can become incorrect without. Disable with care. */ #undef volatile]) m4trace:configure.in:125: -1- AC_LIBSOURCE([error.h]) m4trace:configure.in:125: -1- AC_LIBSOURCE([error.c]) m4trace:configure.in:125: -1- AC_LIBSOURCE([error.c]) m4trace:configure.in:125: -1- AC_SUBST([LIB@&t@OBJS], ["$LIB@&t@OBJS error.$ac_objext"]) m4trace:configure.in:125: -1- AC_SUBST_TRACE([LIB@&t@OBJS]) m4trace:configure.in:125: -1- m4_pattern_allow([^LIB@&t@OBJS$]) m4trace:configure.in:127: -1- AH_OUTPUT([HAVE_STDLIB_H], [/* Define to 1 if you have the header file. */ #undef HAVE_STDLIB_H]) m4trace:configure.in:127: -1- AC_DEFINE_TRACE_LITERAL([HAVE_MALLOC]) m4trace:configure.in:127: -1- m4_pattern_allow([^HAVE_MALLOC$]) m4trace:configure.in:127: -1- AH_OUTPUT([HAVE_MALLOC], [/* Define to 1 if your system has a GNU libc compatible `malloc\' function, and to 0 otherwise. */ #undef HAVE_MALLOC]) m4trace:configure.in:127: -1- AC_DEFINE_TRACE_LITERAL([HAVE_MALLOC]) m4trace:configure.in:127: -1- m4_pattern_allow([^HAVE_MALLOC$]) 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grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_be_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_be_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_be_main" >&5 echo "${ECHO_T}$ac_cv_lib_be_main" >&6; } if test $ac_cv_lib_be_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBBE 1 _ACEOF LIBS="-lbe $LIBS" fi # FIXME: Replace `main' with a function in `-lc': { echo "$as_me:$LINENO: checking for main in -lc" >&5 echo $ECHO_N "checking for main in -lc... $ECHO_C" >&6; } if test "${ac_cv_lib_c_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lc $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_c_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_c_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_c_main" >&5 echo "${ECHO_T}$ac_cv_lib_c_main" >&6; } if test $ac_cv_lib_c_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBC 1 _ACEOF LIBS="-lc $LIBS" fi # FIXME: Replace `main' with a function in `-lgdi32': { echo "$as_me:$LINENO: checking for main in -lgdi32" >&5 echo $ECHO_N "checking for main in -lgdi32... $ECHO_C" >&6; } if test "${ac_cv_lib_gdi32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lgdi32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_gdi32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_gdi32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_gdi32_main" >&5 echo "${ECHO_T}$ac_cv_lib_gdi32_main" >&6; } if test $ac_cv_lib_gdi32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBGDI32 1 _ACEOF LIBS="-lgdi32 $LIBS" fi # FIXME: Replace `main' with a function in `-liberty': { echo "$as_me:$LINENO: checking for main in -liberty" >&5 echo $ECHO_N "checking for main in -liberty... $ECHO_C" >&6; } if test "${ac_cv_lib_iberty_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-liberty $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_iberty_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_iberty_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_iberty_main" >&5 echo "${ECHO_T}$ac_cv_lib_iberty_main" >&6; } if test $ac_cv_lib_iberty_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBIBERTY 1 _ACEOF LIBS="-liberty $LIBS" fi # FIXME: Replace `main' with a function in `-lintl': { echo "$as_me:$LINENO: checking for main in -lintl" >&5 echo $ECHO_N "checking for main in -lintl... $ECHO_C" >&6; } if test "${ac_cv_lib_intl_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lintl $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_intl_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_intl_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_intl_main" >&5 echo "${ECHO_T}$ac_cv_lib_intl_main" >&6; } if test $ac_cv_lib_intl_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBINTL 1 _ACEOF LIBS="-lintl $LIBS" fi # FIXME: Replace `main' with a function in `-lkernel32': { echo "$as_me:$LINENO: checking for main in -lkernel32" >&5 echo $ECHO_N "checking for main in -lkernel32... $ECHO_C" >&6; } if test "${ac_cv_lib_kernel32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lkernel32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_kernel32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_kernel32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_kernel32_main" >&5 echo "${ECHO_T}$ac_cv_lib_kernel32_main" >&6; } if test $ac_cv_lib_kernel32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBKERNEL32 1 _ACEOF LIBS="-lkernel32 $LIBS" fi # FIXME: Replace `main' with a function in `-lm': { echo "$as_me:$LINENO: checking for main in -lm" >&5 echo $ECHO_N "checking for main in -lm... $ECHO_C" >&6; } if test "${ac_cv_lib_m_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lm $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_m_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_m_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_m_main" >&5 echo "${ECHO_T}$ac_cv_lib_m_main" >&6; } if test $ac_cv_lib_m_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBM 1 _ACEOF LIBS="-lm $LIBS" fi # FIXME: Replace `main' with a function in `-lmsvcrt': { echo "$as_me:$LINENO: checking for main in -lmsvcrt" >&5 echo $ECHO_N "checking for main in -lmsvcrt... $ECHO_C" >&6; } if test "${ac_cv_lib_msvcrt_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lmsvcrt $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_msvcrt_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_msvcrt_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_msvcrt_main" >&5 echo "${ECHO_T}$ac_cv_lib_msvcrt_main" >&6; } if test $ac_cv_lib_msvcrt_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBMSVCRT 1 _ACEOF LIBS="-lmsvcrt $LIBS" fi # FIXME: Replace `main' with a function in `-ln': { echo "$as_me:$LINENO: checking for main in -ln" >&5 echo $ECHO_N "checking for main in -ln... $ECHO_C" >&6; } if test "${ac_cv_lib_n_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ln $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_n_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_n_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_n_main" >&5 echo "${ECHO_T}$ac_cv_lib_n_main" >&6; } if test $ac_cv_lib_n_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBN 1 _ACEOF LIBS="-ln $LIBS" fi # FIXME: Replace `main' with a function in `-lnet': { echo "$as_me:$LINENO: checking for main in -lnet" >&5 echo $ECHO_N "checking for main in -lnet... $ECHO_C" >&6; } if test "${ac_cv_lib_net_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lnet $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_net_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_net_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_net_main" >&5 echo "${ECHO_T}$ac_cv_lib_net_main" >&6; } if test $ac_cv_lib_net_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBNET 1 _ACEOF LIBS="-lnet $LIBS" fi # FIXME: Replace `main' with a function in `-lroot': { echo "$as_me:$LINENO: checking for main in -lroot" >&5 echo $ECHO_N "checking for main in -lroot... $ECHO_C" >&6; } if test "${ac_cv_lib_root_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lroot $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_root_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_root_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_root_main" >&5 echo "${ECHO_T}$ac_cv_lib_root_main" >&6; } if test $ac_cv_lib_root_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBROOT 1 _ACEOF LIBS="-lroot $LIBS" fi # FIXME: Replace `main' with a function in `-lsocket': { echo "$as_me:$LINENO: checking for main in -lsocket" >&5 echo $ECHO_N "checking for main in -lsocket... $ECHO_C" >&6; } if test "${ac_cv_lib_socket_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_socket_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_socket_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_socket_main" >&5 echo "${ECHO_T}$ac_cv_lib_socket_main" >&6; } if test $ac_cv_lib_socket_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBSOCKET 1 _ACEOF LIBS="-lsocket $LIBS" fi # FIXME: Replace `main' with a function in `-luser32': { echo "$as_me:$LINENO: checking for main in -luser32" >&5 echo $ECHO_N "checking for main in -luser32... $ECHO_C" >&6; } if test "${ac_cv_lib_user32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-luser32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_user32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_user32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_user32_main" >&5 echo "${ECHO_T}$ac_cv_lib_user32_main" >&6; } if test $ac_cv_lib_user32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBUSER32 1 _ACEOF LIBS="-luser32 $LIBS" fi # FIXME: Replace `main' with a function in `-lwinmm': { echo "$as_me:$LINENO: checking for main in -lwinmm" >&5 echo $ECHO_N "checking for main in -lwinmm... $ECHO_C" >&6; } if test "${ac_cv_lib_winmm_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lwinmm $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_winmm_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_winmm_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_winmm_main" >&5 echo "${ECHO_T}$ac_cv_lib_winmm_main" >&6; } if test $ac_cv_lib_winmm_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBWINMM 1 _ACEOF LIBS="-lwinmm $LIBS" fi # FIXME: Replace `main' with a function in `-lws2_32': { echo "$as_me:$LINENO: checking for main in -lws2_32" >&5 echo $ECHO_N "checking for main in -lws2_32... $ECHO_C" >&6; } if test "${ac_cv_lib_ws2_32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lws2_32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_ws2_32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_ws2_32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_ws2_32_main" >&5 echo "${ECHO_T}$ac_cv_lib_ws2_32_main" >&6; } if test $ac_cv_lib_ws2_32_main = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBWS2_32 1 _ACEOF LIBS="-lws2_32 $LIBS" fi { echo "$as_me:$LINENO: checking for bfd_openr in -lbfd" >&5 echo $ECHO_N "checking for bfd_openr in -lbfd... $ECHO_C" >&6; } if test "${ac_cv_lib_bfd_bfd_openr+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lbfd $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char bfd_openr (); int main () { return bfd_openr (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_bfd_bfd_openr=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_bfd_bfd_openr=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_bfd_bfd_openr" >&5 echo "${ECHO_T}$ac_cv_lib_bfd_bfd_openr" >&6; } if test $ac_cv_lib_bfd_bfd_openr = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBBFD 1 _ACEOF LIBS="-lbfd $LIBS" fi # Checks for header files. { echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5 echo $ECHO_N "checking for grep that handles long lines and -e... $ECHO_C" >&6; } if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # Extract the first word of "grep ggrep" to use in msg output if test -z "$GREP"; then set dummy grep ggrep; ac_prog_name=$2 if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_GREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in grep ggrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue # Check for GNU ac_path_GREP and select it if it is found. # Check for GNU $ac_path_GREP case `"$ac_path_GREP" --version 2>&1` in *GNU*) ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'GREP' >> "conftest.nl" "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_GREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_GREP_found && break 3 done done done IFS=$as_save_IFS fi GREP="$ac_cv_path_GREP" if test -z "$GREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_GREP=$GREP fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5 echo "${ECHO_T}$ac_cv_path_GREP" >&6; } GREP="$ac_cv_path_GREP" { echo "$as_me:$LINENO: checking for egrep" >&5 echo $ECHO_N "checking for egrep... $ECHO_C" >&6; } if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 then ac_cv_path_EGREP="$GREP -E" else # Extract the first word of "egrep" to use in msg output if test -z "$EGREP"; then set dummy egrep; ac_prog_name=$2 if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_EGREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in egrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue # Check for GNU ac_path_EGREP and select it if it is found. # Check for GNU $ac_path_EGREP case `"$ac_path_EGREP" --version 2>&1` in *GNU*) ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'EGREP' >> "conftest.nl" "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_EGREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_EGREP_found && break 3 done done done IFS=$as_save_IFS fi EGREP="$ac_cv_path_EGREP" if test -z "$EGREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_EGREP=$EGREP fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5 echo "${ECHO_T}$ac_cv_path_EGREP" >&6; } EGREP="$ac_cv_path_EGREP" { echo "$as_me:$LINENO: checking for ANSI C header files" >&5 echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6; } if test "${ac_cv_header_stdc+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include #include int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdc=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "memchr" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "free" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. if test "$cross_compiling" = yes; then : else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #if ((' ' & 0x0FF) == 0x020) # define ISLOWER(c) ('a' <= (c) && (c) <= 'z') # define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) #else # define ISLOWER(c) \ (('a' <= (c) && (c) <= 'i') \ || ('j' <= (c) && (c) <= 'r') \ || ('s' <= (c) && (c) <= 'z')) # define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) #endif #define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) int main () { int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) return 2; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then : else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_header_stdc=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 echo "${ECHO_T}$ac_cv_header_stdc" >&6; } if test $ac_cv_header_stdc = yes; then cat >>confdefs.h <<\_ACEOF @%:@define STDC_HEADERS 1 _ACEOF fi # On IRIX 5.3, sys/types and inttypes.h are conflicting. for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ inttypes.h stdint.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then eval "$as_ac_Header=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_Header=no" fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_header in fcntl.h inttypes.h limits.h locale.h netdb.h netinet/in.h stddef.h stdint.h stdlib.h string.h sys/file.h sys/ioctl.h sys/socket.h sys/time.h termios.h unistd.h gtk/gtk.h bfd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done # Checks for typedefs, structures, and compiler characteristics. { echo "$as_me:$LINENO: checking for stdbool.h that conforms to C99" >&5 echo $ECHO_N "checking for stdbool.h that conforms to C99... $ECHO_C" >&6; } if test "${ac_cv_header_stdbool_h+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #ifndef bool "error: bool is not defined" #endif #ifndef false "error: false is not defined" #endif #if false "error: false is not 0" #endif #ifndef true "error: true is not defined" #endif #if true != 1 "error: true is not 1" #endif #ifndef __bool_true_false_are_defined "error: __bool_true_false_are_defined is not defined" #endif struct s { _Bool s: 1; _Bool t; } s; char a[true == 1 ? 1 : -1]; char b[false == 0 ? 1 : -1]; char c[__bool_true_false_are_defined == 1 ? 1 : -1]; char d[(bool) 0.5 == true ? 1 : -1]; bool e = &s; char f[(_Bool) 0.0 == false ? 1 : -1]; char g[true]; char h[sizeof (_Bool)]; char i[sizeof s.t]; enum { j = false, k = true, l = false * true, m = true * 256 }; _Bool n[m]; char o[sizeof n == m * sizeof n[0] ? 1 : -1]; char p[-1 - (_Bool) 0 < 0 && -1 - (bool) 0 < 0 ? 1 : -1]; # if defined __xlc__ || defined __GNUC__ /* Catch a bug in IBM AIX xlc compiler version 6.0.0.0 reported by James Lemley on 2005-10-05; see http://lists.gnu.org/archive/html/bug-coreutils/2005-10/msg00086.html This test is not quite right, since xlc is allowed to reject this program, as the initializer for xlcbug is not one of the forms that C requires support for. However, doing the test right would require a runtime test, and that would make cross-compilation harder. Let us hope that IBM fixes the xlc bug, and also adds support for this kind of constant expression. In the meantime, this test will reject xlc, which is OK, since our stdbool.h substitute should suffice. We also test this with GCC, where it should work, to detect more quickly whether someone messes up the test in the future. */ char digs[] = "0123456789"; int xlcbug = 1 / (&(digs + 5)[-2 + (bool) 1] == &digs[4] ? 1 : -1); # endif /* Catch a bug in an HP-UX C compiler. See http://gcc.gnu.org/ml/gcc-patches/2003-12/msg02303.html http://lists.gnu.org/archive/html/bug-coreutils/2005-11/msg00161.html */ _Bool q = true; _Bool *pq = &q; int main () { *pq |= q; *pq |= ! q; /* Refer to every declared value, to avoid compiler optimizations. */ return (!a + !b + !c + !d + !e + !f + !g + !h + !i + !!j + !k + !!l + !m + !n + !o + !p + !q + !pq); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdbool_h=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdbool_h=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdbool_h" >&5 echo "${ECHO_T}$ac_cv_header_stdbool_h" >&6; } { echo "$as_me:$LINENO: checking for _Bool" >&5 echo $ECHO_N "checking for _Bool... $ECHO_C" >&6; } if test "${ac_cv_type__Bool+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef _Bool ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type__Bool=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type__Bool=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type__Bool" >&5 echo "${ECHO_T}$ac_cv_type__Bool" >&6; } if test $ac_cv_type__Bool = yes; then cat >>confdefs.h <<_ACEOF @%:@define HAVE__BOOL 1 _ACEOF fi if test $ac_cv_header_stdbool_h = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_STDBOOL_H 1 _ACEOF fi { echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6; } if test "${ac_cv_c_const+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { /* FIXME: Include the comments suggested by Paul. */ #ifndef __cplusplus /* Ultrix mips cc rejects this. */ typedef int charset[2]; const charset cs; /* SunOS 4.1.1 cc rejects this. */ char const *const *pcpcc; char **ppc; /* NEC SVR4.0.2 mips cc rejects this. */ struct point {int x, y;}; static struct point const zero = {0,0}; /* AIX XL C 1.02.0.0 rejects this. It does not let you subtract one const X* pointer from another in an arm of an if-expression whose if-part is not a constant expression */ const char *g = "string"; pcpcc = &g + (g ? g-g : 0); /* HPUX 7.0 cc rejects these. */ ++pcpcc; ppc = (char**) pcpcc; pcpcc = (char const *const *) ppc; { /* SCO 3.2v4 cc rejects this. */ char *t; char const *s = 0 ? (char *) 0 : (char const *) 0; *t++ = 0; if (s) return 0; } { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ int x[] = {25, 17}; const int *foo = &x[0]; ++foo; } { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ typedef const int *iptr; iptr p = 0; ++p; } { /* AIX XL C 1.02.0.0 rejects this saying "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ struct s { int j; const int *ap[3]; }; struct s *b; b->j = 5; } { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ const int foo = 10; if (!foo) return 0; } return !cs[0] && !zero.x; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_const=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_const=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 echo "${ECHO_T}$ac_cv_c_const" >&6; } if test $ac_cv_c_const = no; then cat >>confdefs.h <<\_ACEOF @%:@define const _ACEOF fi { echo "$as_me:$LINENO: checking for inline" >&5 echo $ECHO_N "checking for inline... $ECHO_C" >&6; } if test "${ac_cv_c_inline+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #ifndef __cplusplus typedef int foo_t; static $ac_kw foo_t static_foo () {return 0; } $ac_kw foo_t foo () {return 0; } #endif _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_inline=$ac_kw else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_inline" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5 echo "${ECHO_T}$ac_cv_c_inline" >&6; } case $ac_cv_c_inline in inline | yes) ;; *) case $ac_cv_c_inline in no) ac_val=;; *) ac_val=$ac_cv_c_inline;; esac cat >>confdefs.h <<_ACEOF #ifndef __cplusplus #define inline $ac_val #endif _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int16_t" >&5 echo $ECHO_N "checking for int16_t... $ECHO_C" >&6; } if test "${ac_cv_c_int16_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int16_t=no for ac_type in 'int16_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int16_t) ac_cv_c_int16_t=yes ;; *) ac_cv_c_int16_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int16_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int16_t" >&5 echo "${ECHO_T}$ac_cv_c_int16_t" >&6; } case $ac_cv_c_int16_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int16_t $ac_cv_c_int16_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int32_t" >&5 echo $ECHO_N "checking for int32_t... $ECHO_C" >&6; } if test "${ac_cv_c_int32_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int32_t=no for ac_type in 'int32_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int32_t) ac_cv_c_int32_t=yes ;; *) ac_cv_c_int32_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int32_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int32_t" >&5 echo "${ECHO_T}$ac_cv_c_int32_t" >&6; } case $ac_cv_c_int32_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int32_t $ac_cv_c_int32_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int64_t" >&5 echo $ECHO_N "checking for int64_t... $ECHO_C" >&6; } if test "${ac_cv_c_int64_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int64_t=no for ac_type in 'int64_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int64_t) ac_cv_c_int64_t=yes ;; *) ac_cv_c_int64_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int64_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int64_t" >&5 echo "${ECHO_T}$ac_cv_c_int64_t" >&6; } case $ac_cv_c_int64_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int64_t $ac_cv_c_int64_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int8_t" >&5 echo $ECHO_N "checking for int8_t... $ECHO_C" >&6; } if test "${ac_cv_c_int8_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int8_t=no for ac_type in 'int8_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 1))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 2))@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int8_t) ac_cv_c_int8_t=yes ;; *) ac_cv_c_int8_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int8_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int8_t" >&5 echo "${ECHO_T}$ac_cv_c_int8_t" >&6; } case $ac_cv_c_int8_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define int8_t $ac_cv_c_int8_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for off_t" >&5 echo $ECHO_N "checking for off_t... $ECHO_C" >&6; } if test "${ac_cv_type_off_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef off_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_off_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_off_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5 echo "${ECHO_T}$ac_cv_type_off_t" >&6; } if test $ac_cv_type_off_t = yes; then : else cat >>confdefs.h <<_ACEOF @%:@define off_t long int _ACEOF fi { echo "$as_me:$LINENO: checking for size_t" >&5 echo $ECHO_N "checking for size_t... $ECHO_C" >&6; } if test "${ac_cv_type_size_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef size_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_size_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_size_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5 echo "${ECHO_T}$ac_cv_type_size_t" >&6; } if test $ac_cv_type_size_t = yes; then : else cat >>confdefs.h <<_ACEOF @%:@define size_t unsigned int _ACEOF fi { echo "$as_me:$LINENO: checking for ssize_t" >&5 echo $ECHO_N "checking for ssize_t... $ECHO_C" >&6; } if test "${ac_cv_type_ssize_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef ssize_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_ssize_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_ssize_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_ssize_t" >&5 echo "${ECHO_T}$ac_cv_type_ssize_t" >&6; } if test $ac_cv_type_ssize_t = yes; then : else cat >>confdefs.h <<_ACEOF @%:@define ssize_t int _ACEOF fi { echo "$as_me:$LINENO: checking whether time.h and sys/time.h may both be included" >&5 echo $ECHO_N "checking whether time.h and sys/time.h may both be included... $ECHO_C" >&6; } if test "${ac_cv_header_time+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include int main () { if ((struct tm *) 0) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_time=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_time=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_time" >&5 echo "${ECHO_T}$ac_cv_header_time" >&6; } if test $ac_cv_header_time = yes; then cat >>confdefs.h <<\_ACEOF @%:@define TIME_WITH_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking whether struct tm is in sys/time.h or time.h" >&5 echo $ECHO_N "checking whether struct tm is in sys/time.h or time.h... $ECHO_C" >&6; } if test "${ac_cv_struct_tm+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include int main () { struct tm tm; int *p = &tm.tm_sec; return !p; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_struct_tm=time.h else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_struct_tm=sys/time.h fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_struct_tm" >&5 echo "${ECHO_T}$ac_cv_struct_tm" >&6; } if test $ac_cv_struct_tm = sys/time.h; then cat >>confdefs.h <<\_ACEOF @%:@define TM_IN_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking for uid_t in sys/types.h" >&5 echo $ECHO_N "checking for uid_t in sys/types.h... $ECHO_C" >&6; } if test "${ac_cv_type_uid_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "uid_t" >/dev/null 2>&1; then ac_cv_type_uid_t=yes else ac_cv_type_uid_t=no fi rm -f conftest* fi { echo "$as_me:$LINENO: result: $ac_cv_type_uid_t" >&5 echo "${ECHO_T}$ac_cv_type_uid_t" >&6; } if test $ac_cv_type_uid_t = no; then cat >>confdefs.h <<\_ACEOF @%:@define uid_t int _ACEOF cat >>confdefs.h <<\_ACEOF @%:@define gid_t int _ACEOF fi { echo "$as_me:$LINENO: checking for uint16_t" >&5 echo $ECHO_N "checking for uint16_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint16_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint16_t=no for ac_type in 'uint16_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) -1 >> (16 - 1) == 1)@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint16_t) ac_cv_c_uint16_t=yes ;; *) ac_cv_c_uint16_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint16_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint16_t" >&5 echo "${ECHO_T}$ac_cv_c_uint16_t" >&6; } case $ac_cv_c_uint16_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF @%:@define uint16_t $ac_cv_c_uint16_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for uint32_t" >&5 echo $ECHO_N "checking for uint32_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint32_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint32_t=no for ac_type in 'uint32_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) -1 >> (32 - 1) == 1)@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint32_t) ac_cv_c_uint32_t=yes ;; *) ac_cv_c_uint32_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint32_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint32_t" >&5 echo "${ECHO_T}$ac_cv_c_uint32_t" >&6; } case $ac_cv_c_uint32_t in #( no|yes) ;; #( *) cat >>confdefs.h <<\_ACEOF @%:@define _UINT32_T 1 _ACEOF cat >>confdefs.h <<_ACEOF @%:@define uint32_t $ac_cv_c_uint32_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for uint64_t" >&5 echo $ECHO_N "checking for uint64_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint64_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint64_t=no for ac_type in 'uint64_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) -1 >> (64 - 1) == 1)@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint64_t) ac_cv_c_uint64_t=yes ;; *) ac_cv_c_uint64_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint64_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint64_t" >&5 echo "${ECHO_T}$ac_cv_c_uint64_t" >&6; } case $ac_cv_c_uint64_t in #( no|yes) ;; #( *) cat >>confdefs.h <<\_ACEOF @%:@define _UINT64_T 1 _ACEOF cat >>confdefs.h <<_ACEOF @%:@define uint64_t $ac_cv_c_uint64_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for uint8_t" >&5 echo $ECHO_N "checking for uint8_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint8_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint8_t=no for ac_type in 'uint8_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array @<:@1 - 2 * !(($ac_type) -1 >> (8 - 1) == 1)@:>@; test_array @<:@0@:>@ = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint8_t) ac_cv_c_uint8_t=yes ;; *) ac_cv_c_uint8_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint8_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint8_t" >&5 echo "${ECHO_T}$ac_cv_c_uint8_t" >&6; } case $ac_cv_c_uint8_t in #( no|yes) ;; #( *) cat >>confdefs.h <<\_ACEOF @%:@define _UINT8_T 1 _ACEOF cat >>confdefs.h <<_ACEOF @%:@define uint8_t $ac_cv_c_uint8_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for working volatile" >&5 echo $ECHO_N "checking for working volatile... $ECHO_C" >&6; } if test "${ac_cv_c_volatile+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { volatile int x; int * volatile y = (int *) 0; return !x && !y; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_volatile=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_volatile=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_c_volatile" >&5 echo "${ECHO_T}$ac_cv_c_volatile" >&6; } if test $ac_cv_c_volatile = no; then cat >>confdefs.h <<\_ACEOF @%:@define volatile _ACEOF fi # Checks for library functions. { echo "$as_me:$LINENO: checking for error_at_line" >&5 echo $ECHO_N "checking for error_at_line... $ECHO_C" >&6; } if test "${ac_cv_lib_error_at_line+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include int main () { error_at_line (0, 0, "", 0, "an error occurred"); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_error_at_line=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_error_at_line=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_lib_error_at_line" >&5 echo "${ECHO_T}$ac_cv_lib_error_at_line" >&6; } if test $ac_cv_lib_error_at_line = no; then case " $LIB@&t@OBJS " in *" error.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS error.$ac_objext" ;; esac fi if test $ac_cv_c_compiler_gnu = yes; then { echo "$as_me:$LINENO: checking whether $CC needs -traditional" >&5 echo $ECHO_N "checking whether $CC needs -traditional... $ECHO_C" >&6; } if test "${ac_cv_prog_gcc_traditional+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_pattern="Autoconf.*'x'" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include Autoconf TIOCGETP _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "$ac_pattern" >/dev/null 2>&1; then ac_cv_prog_gcc_traditional=yes else ac_cv_prog_gcc_traditional=no fi rm -f conftest* if test $ac_cv_prog_gcc_traditional = no; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include Autoconf TCGETA _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "$ac_pattern" >/dev/null 2>&1; then ac_cv_prog_gcc_traditional=yes fi rm -f conftest* fi fi { echo "$as_me:$LINENO: result: $ac_cv_prog_gcc_traditional" >&5 echo "${ECHO_T}$ac_cv_prog_gcc_traditional" >&6; } if test $ac_cv_prog_gcc_traditional = yes; then CC="$CC -traditional" fi fi for ac_header in stdlib.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for GNU libc compatible malloc" >&5 echo $ECHO_N "checking for GNU libc compatible malloc... $ECHO_C" >&6; } if test "${ac_cv_func_malloc_0_nonnull+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_malloc_0_nonnull=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined STDC_HEADERS || defined HAVE_STDLIB_H # include #else char *malloc (); #endif int main () { return ! malloc (0); ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_malloc_0_nonnull=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_malloc_0_nonnull=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_malloc_0_nonnull" >&5 echo "${ECHO_T}$ac_cv_func_malloc_0_nonnull" >&6; } if test $ac_cv_func_malloc_0_nonnull = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_MALLOC 1 _ACEOF else cat >>confdefs.h <<\_ACEOF @%:@define HAVE_MALLOC 0 _ACEOF case " $LIB@&t@OBJS " in *" malloc.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS malloc.$ac_objext" ;; esac cat >>confdefs.h <<\_ACEOF @%:@define malloc rpl_malloc _ACEOF fi { echo "$as_me:$LINENO: checking for working memcmp" >&5 echo $ECHO_N "checking for working memcmp... $ECHO_C" >&6; } if test "${ac_cv_func_memcmp_working+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_memcmp_working=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { /* Some versions of memcmp are not 8-bit clean. */ char c0 = '\100', c1 = '\200', c2 = '\201'; if (memcmp(&c0, &c2, 1) >= 0 || memcmp(&c1, &c2, 1) >= 0) return 1; /* The Next x86 OpenStep bug shows up only when comparing 16 bytes or more and with at least one buffer not starting on a 4-byte boundary. William Lewis provided this test program. */ { char foo[21]; char bar[21]; int i; for (i = 0; i < 4; i++) { char *a = foo + i; char *b = bar + i; strcpy (a, "--------01111111"); strcpy (b, "--------10000000"); if (memcmp (a, b, 16) >= 0) return 1; } return 0; } ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_memcmp_working=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_memcmp_working=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_memcmp_working" >&5 echo "${ECHO_T}$ac_cv_func_memcmp_working" >&6; } test $ac_cv_func_memcmp_working = no && case " $LIB@&t@OBJS " in *" memcmp.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS memcmp.$ac_objext" ;; esac for ac_header in $ac_header_list do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_func in $ac_func_list do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. For example, HP-UX 11i declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for working mktime" >&5 echo $ECHO_N "checking for working mktime... $ECHO_C" >&6; } if test "${ac_cv_func_working_mktime+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_working_mktime=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Test program from Paul Eggert and Tony Leneis. */ #ifdef TIME_WITH_SYS_TIME # include # include #else # ifdef HAVE_SYS_TIME_H # include # else # include # endif #endif #include #ifdef HAVE_UNISTD_H # include #endif #ifndef HAVE_ALARM # define alarm(X) /* empty */ #endif /* Work around redefinition to rpl_putenv by other config tests. */ #undef putenv static time_t time_t_max; static time_t time_t_min; /* Values we'll use to set the TZ environment variable. */ static char *tz_strings[] = { (char *) 0, "TZ=GMT0", "TZ=JST-9", "TZ=EST+3EDT+2,M10.1.0/00:00:00,M2.3.0/00:00:00" }; #define N_STRINGS (sizeof (tz_strings) / sizeof (tz_strings[0])) /* Return 0 if mktime fails to convert a date in the spring-forward gap. Based on a problem report from Andreas Jaeger. */ static int spring_forward_gap () { /* glibc (up to about 1998-10-07) failed this test. */ struct tm tm; /* Use the portable POSIX.1 specification "TZ=PST8PDT,M4.1.0,M10.5.0" instead of "TZ=America/Vancouver" in order to detect the bug even on systems that don't support the Olson extension, or don't have the full zoneinfo tables installed. */ putenv ("TZ=PST8PDT,M4.1.0,M10.5.0"); tm.tm_year = 98; tm.tm_mon = 3; tm.tm_mday = 5; tm.tm_hour = 2; tm.tm_min = 0; tm.tm_sec = 0; tm.tm_isdst = -1; return mktime (&tm) != (time_t) -1; } static int mktime_test1 (now) time_t now; { struct tm *lt; return ! (lt = localtime (&now)) || mktime (lt) == now; } static int mktime_test (now) time_t now; { return (mktime_test1 (now) && mktime_test1 ((time_t) (time_t_max - now)) && mktime_test1 ((time_t) (time_t_min + now))); } static int irix_6_4_bug () { /* Based on code from Ariel Faigon. */ struct tm tm; tm.tm_year = 96; tm.tm_mon = 3; tm.tm_mday = 0; tm.tm_hour = 0; tm.tm_min = 0; tm.tm_sec = 0; tm.tm_isdst = -1; mktime (&tm); return tm.tm_mon == 2 && tm.tm_mday == 31; } static int bigtime_test (j) int j; { struct tm tm; time_t now; tm.tm_year = tm.tm_mon = tm.tm_mday = tm.tm_hour = tm.tm_min = tm.tm_sec = j; now = mktime (&tm); if (now != (time_t) -1) { struct tm *lt = localtime (&now); if (! (lt && lt->tm_year == tm.tm_year && lt->tm_mon == tm.tm_mon && lt->tm_mday == tm.tm_mday && lt->tm_hour == tm.tm_hour && lt->tm_min == tm.tm_min && lt->tm_sec == tm.tm_sec && lt->tm_yday == tm.tm_yday && lt->tm_wday == tm.tm_wday && ((lt->tm_isdst < 0 ? -1 : 0 < lt->tm_isdst) == (tm.tm_isdst < 0 ? -1 : 0 < tm.tm_isdst)))) return 0; } return 1; } static int year_2050_test () { /* The correct answer for 2050-02-01 00:00:00 in Pacific time, ignoring leap seconds. */ unsigned long int answer = 2527315200UL; struct tm tm; time_t t; tm.tm_year = 2050 - 1900; tm.tm_mon = 2 - 1; tm.tm_mday = 1; tm.tm_hour = tm.tm_min = tm.tm_sec = 0; tm.tm_isdst = -1; /* Use the portable POSIX.1 specification "TZ=PST8PDT,M4.1.0,M10.5.0" instead of "TZ=America/Vancouver" in order to detect the bug even on systems that don't support the Olson extension, or don't have the full zoneinfo tables installed. */ putenv ("TZ=PST8PDT,M4.1.0,M10.5.0"); t = mktime (&tm); /* Check that the result is either a failure, or close enough to the correct answer that we can assume the discrepancy is due to leap seconds. */ return (t == (time_t) -1 || (0 < t && answer - 120 <= t && t <= answer + 120)); } int main () { time_t t, delta; int i, j; /* This test makes some buggy mktime implementations loop. Give up after 60 seconds; a mktime slower than that isn't worth using anyway. */ alarm (60); for (time_t_max = 1; 0 < time_t_max; time_t_max *= 2) continue; time_t_max--; if ((time_t) -1 < 0) for (time_t_min = -1; (time_t) (time_t_min * 2) < 0; time_t_min *= 2) continue; delta = time_t_max / 997; /* a suitable prime number */ for (i = 0; i < N_STRINGS; i++) { if (tz_strings[i]) putenv (tz_strings[i]); for (t = 0; t <= time_t_max - delta; t += delta) if (! mktime_test (t)) return 1; if (! (mktime_test ((time_t) 1) && mktime_test ((time_t) (60 * 60)) && mktime_test ((time_t) (60 * 60 * 24)))) return 1; for (j = 1; 0 < j; j *= 2) if (! bigtime_test (j)) return 1; if (! bigtime_test (j - 1)) return 1; } return ! (irix_6_4_bug () && spring_forward_gap () && year_2050_test ()); } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_working_mktime=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_working_mktime=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_working_mktime" >&5 echo "${ECHO_T}$ac_cv_func_working_mktime" >&6; } if test $ac_cv_func_working_mktime = no; then case " $LIB@&t@OBJS " in *" mktime.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS mktime.$ac_objext" ;; esac fi for ac_header in stdlib.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_func in getpagesize do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. For example, HP-UX 11i declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for working mmap" >&5 echo $ECHO_N "checking for working mmap... $ECHO_C" >&6; } if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_mmap_fixed_mapped=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default /* malloc might have been renamed as rpl_malloc. */ #undef malloc /* Thanks to Mike Haertel and Jim Avera for this test. Here is a matrix of mmap possibilities: mmap private not fixed mmap private fixed at somewhere currently unmapped mmap private fixed at somewhere already mapped mmap shared not fixed mmap shared fixed at somewhere currently unmapped mmap shared fixed at somewhere already mapped For private mappings, we should verify that changes cannot be read() back from the file, nor mmap's back from the file at a different address. (There have been systems where private was not correctly implemented like the infamous i386 svr4.0, and systems where the VM page cache was not coherent with the file system buffer cache like early versions of FreeBSD and possibly contemporary NetBSD.) For shared mappings, we should conversely verify that changes get propagated back to all the places they're supposed to be. Grep wants private fixed already mapped. The main things grep needs to know about mmap are: * does it exist and is it safe to write into the mmap'd area * how to use it (BSD variants) */ #include #include #if !defined STDC_HEADERS && !defined HAVE_STDLIB_H char *malloc (); #endif /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H # define HAVE_SYS_PARAM_H 1 # endif # ifdef _SC_PAGESIZE # define getpagesize() sysconf(_SC_PAGESIZE) # else /* no _SC_PAGESIZE */ # ifdef HAVE_SYS_PARAM_H # include # ifdef EXEC_PAGESIZE # define getpagesize() EXEC_PAGESIZE # else /* no EXEC_PAGESIZE */ # ifdef NBPG # define getpagesize() NBPG * CLSIZE # ifndef CLSIZE # define CLSIZE 1 # endif /* no CLSIZE */ # else /* no NBPG */ # ifdef NBPC # define getpagesize() NBPC # else /* no NBPC */ # ifdef PAGESIZE # define getpagesize() PAGESIZE # endif /* PAGESIZE */ # endif /* no NBPC */ # endif /* no NBPG */ # endif /* no EXEC_PAGESIZE */ # else /* no HAVE_SYS_PARAM_H */ # define getpagesize() 8192 /* punt totally */ # endif /* no HAVE_SYS_PARAM_H */ # endif /* no _SC_PAGESIZE */ #endif /* no HAVE_GETPAGESIZE */ int main () { char *data, *data2, *data3; int i, pagesize; int fd; pagesize = getpagesize (); /* First, make a file with some known garbage in it. */ data = (char *) malloc (pagesize); if (!data) return 1; for (i = 0; i < pagesize; ++i) *(data + i) = rand (); umask (0); fd = creat ("conftest.mmap", 0600); if (fd < 0) return 1; if (write (fd, data, pagesize) != pagesize) return 1; close (fd); /* Next, try to mmap the file at a fixed address which already has something else allocated at it. If we can, also make sure that we see the same garbage. */ fd = open ("conftest.mmap", O_RDWR); if (fd < 0) return 1; data2 = (char *) malloc (2 * pagesize); if (!data2) return 1; data2 += (pagesize - ((long int) data2 & (pagesize - 1))) & (pagesize - 1); if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_FIXED, fd, 0L)) return 1; for (i = 0; i < pagesize; ++i) if (*(data + i) != *(data2 + i)) return 1; /* Finally, make sure that changes to the mapped area do not percolate back to the file as seen by read(). (This is a bug on some variants of i386 svr4.0.) */ for (i = 0; i < pagesize; ++i) *(data2 + i) = *(data2 + i) + 1; data3 = (char *) malloc (pagesize); if (!data3) return 1; if (read (fd, data3, pagesize) != pagesize) return 1; for (i = 0; i < pagesize; ++i) if (*(data + i) != *(data3 + i)) return 1; close (fd); return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_mmap_fixed_mapped=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_mmap_fixed_mapped=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5 echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6; } if test $ac_cv_func_mmap_fixed_mapped = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_MMAP 1 _ACEOF fi rm -f conftest.mmap for ac_header in stdlib.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for GNU libc compatible realloc" >&5 echo $ECHO_N "checking for GNU libc compatible realloc... $ECHO_C" >&6; } if test "${ac_cv_func_realloc_0_nonnull+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_realloc_0_nonnull=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined STDC_HEADERS || defined HAVE_STDLIB_H # include #else char *realloc (); #endif int main () { return ! realloc (0, 0); ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_realloc_0_nonnull=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_realloc_0_nonnull=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_realloc_0_nonnull" >&5 echo "${ECHO_T}$ac_cv_func_realloc_0_nonnull" >&6; } if test $ac_cv_func_realloc_0_nonnull = yes; then cat >>confdefs.h <<\_ACEOF @%:@define HAVE_REALLOC 1 _ACEOF else cat >>confdefs.h <<\_ACEOF @%:@define HAVE_REALLOC 0 _ACEOF case " $LIB@&t@OBJS " in *" realloc.$ac_objext "* ) ;; *) LIB@&t@OBJS="$LIB@&t@OBJS realloc.$ac_objext" ;; esac cat >>confdefs.h <<\_ACEOF @%:@define realloc rpl_realloc _ACEOF fi for ac_header in sys/select.h sys/socket.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default @%:@include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ @%:@include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX @%:@@%:@ ---------------------------------------------------- @%:@@%:@ @%:@@%:@ Report this to skyeye-developer@lists.gro.clinux.org @%:@@%:@ @%:@@%:@ ---------------------------------------------------- @%:@@%:@ _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF @%:@define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking types of arguments for select" >&5 echo $ECHO_N "checking types of arguments for select... $ECHO_C" >&6; } if test "${ac_cv_func_select_args+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else for ac_arg234 in 'fd_set *' 'int *' 'void *'; do for ac_arg1 in 'int' 'size_t' 'unsigned long int' 'unsigned int'; do for ac_arg5 in 'struct timeval *' 'const struct timeval *'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #ifdef HAVE_SYS_SELECT_H # include #endif #ifdef HAVE_SYS_SOCKET_H # include #endif int main () { extern int select ($ac_arg1, $ac_arg234, $ac_arg234, $ac_arg234, $ac_arg5); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? 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See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA # 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Please send patches to . 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# Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) basic_machine=i386-unknown os=-bsd ;; 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) basic_machine=m68000-att ;; 3b*) basic_machine=we32k-att ;; a29khif) basic_machine=a29k-amd os=-udi ;; abacus) basic_machine=abacus-unknown ;; adobe68k) basic_machine=m68010-adobe os=-scout ;; alliant | fx80) basic_machine=fx80-alliant ;; altos | altos3068) basic_machine=m68k-altos ;; am29k) basic_machine=a29k-none os=-bsd ;; amd64) basic_machine=x86_64-pc ;; amd64-*) basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; amdahl) basic_machine=580-amdahl os=-sysv ;; amiga | amiga-*) basic_machine=m68k-unknown ;; amigaos | amigados) basic_machine=m68k-unknown os=-amigaos ;; amigaunix | amix) basic_machine=m68k-unknown os=-sysv4 ;; apollo68) basic_machine=m68k-apollo os=-sysv ;; apollo68bsd) basic_machine=m68k-apollo os=-bsd ;; aux) basic_machine=m68k-apple os=-aux ;; balance) basic_machine=ns32k-sequent os=-dynix ;; c90) basic_machine=c90-cray os=-unicos ;; convex-c1) basic_machine=c1-convex os=-bsd ;; convex-c2) basic_machine=c2-convex os=-bsd ;; convex-c32) basic_machine=c32-convex os=-bsd ;; convex-c34) basic_machine=c34-convex os=-bsd ;; convex-c38) basic_machine=c38-convex os=-bsd ;; cray | j90) basic_machine=j90-cray os=-unicos ;; craynv) basic_machine=craynv-cray os=-unicosmp ;; cr16c) basic_machine=cr16c-unknown os=-elf ;; crds | unos) basic_machine=m68k-crds ;; crisv32 | crisv32-* | etraxfs*) basic_machine=crisv32-axis ;; cris | cris-* | etrax*) basic_machine=cris-axis ;; crx) basic_machine=crx-unknown os=-elf ;; da30 | da30-*) basic_machine=m68k-da30 ;; decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) basic_machine=mips-dec ;; decsystem10* | dec10*) basic_machine=pdp10-dec os=-tops10 ;; decsystem20* | dec20*) basic_machine=pdp10-dec os=-tops20 ;; delta | 3300 | motorola-3300 | motorola-delta \ | 3300-motorola | delta-motorola) basic_machine=m68k-motorola ;; delta88) basic_machine=m88k-motorola os=-sysv3 ;; djgpp) basic_machine=i586-pc os=-msdosdjgpp ;; dpx20 | dpx20-*) basic_machine=rs6000-bull os=-bosx ;; dpx2* | dpx2*-bull) basic_machine=m68k-bull os=-sysv3 ;; ebmon29k) basic_machine=a29k-amd os=-ebmon ;; elxsi) basic_machine=elxsi-elxsi os=-bsd ;; encore | umax | mmax) basic_machine=ns32k-encore ;; es1800 | OSE68k | ose68k | ose | OSE) basic_machine=m68k-ericsson os=-ose ;; fx2800) basic_machine=i860-alliant ;; genix) basic_machine=ns32k-ns ;; gmicro) basic_machine=tron-gmicro os=-sysv ;; go32) basic_machine=i386-pc os=-go32 ;; h3050r* | hiux*) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; h8300hms) basic_machine=h8300-hitachi os=-hms ;; h8300xray) basic_machine=h8300-hitachi os=-xray ;; h8500hms) basic_machine=h8500-hitachi os=-hms ;; harris) basic_machine=m88k-harris os=-sysv3 ;; hp300-*) basic_machine=m68k-hp ;; hp300bsd) basic_machine=m68k-hp os=-bsd ;; hp300hpux) basic_machine=m68k-hp os=-hpux ;; hp3k9[0-9][0-9] | hp9[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k2[0-9][0-9] | hp9k31[0-9]) basic_machine=m68000-hp ;; hp9k3[2-9][0-9]) basic_machine=m68k-hp ;; hp9k6[0-9][0-9] | hp6[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k7[0-79][0-9] | hp7[0-79][0-9]) basic_machine=hppa1.1-hp ;; hp9k78[0-9] | hp78[0-9]) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[0-9][13679] | hp8[0-9][13679]) basic_machine=hppa1.1-hp ;; hp9k8[0-9][0-9] | hp8[0-9][0-9]) basic_machine=hppa1.0-hp ;; hppa-next) os=-nextstep3 ;; hppaosf) basic_machine=hppa1.1-hp os=-osf ;; hppro) basic_machine=hppa1.1-hp os=-proelf ;; i370-ibm* | ibm*) basic_machine=i370-ibm ;; # I'm not sure what "Sysv32" means. Should this be sysv3.2? i*86v32) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv32 ;; i*86v4*) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv4 ;; i*86v) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv ;; i*86sol2) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-solaris2 ;; i386mach) basic_machine=i386-mach os=-mach ;; i386-vsta | vsta) basic_machine=i386-unknown os=-vsta ;; iris | iris4d) basic_machine=mips-sgi case $os in -irix*) ;; *) os=-irix4 ;; esac ;; isi68 | isi) basic_machine=m68k-isi os=-sysv ;; m88k-omron*) basic_machine=m88k-omron ;; magnum | m3230) basic_machine=mips-mips os=-sysv ;; merlin) basic_machine=ns32k-utek os=-sysv ;; mingw32) basic_machine=i386-pc os=-mingw32 ;; miniframe) basic_machine=m68000-convergent ;; *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) basic_machine=m68k-atari os=-mint ;; mips3*-*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` ;; mips3*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown ;; monitor) basic_machine=m68k-rom68k os=-coff ;; morphos) basic_machine=powerpc-unknown os=-morphos ;; msdos) basic_machine=i386-pc os=-msdos ;; ms1-*) basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` ;; mvs) basic_machine=i370-ibm os=-mvs ;; ncr3000) basic_machine=i486-ncr os=-sysv4 ;; netbsd386) basic_machine=i386-unknown os=-netbsd ;; netwinder) basic_machine=armv4l-rebel os=-linux ;; news | news700 | news800 | news900) basic_machine=m68k-sony os=-newsos ;; news1000) basic_machine=m68030-sony os=-newsos ;; news-3600 | risc-news) basic_machine=mips-sony os=-newsos ;; necv70) basic_machine=v70-nec os=-sysv ;; next | m*-next ) basic_machine=m68k-next case $os in -nextstep* ) ;; -ns2*) os=-nextstep2 ;; *) os=-nextstep3 ;; esac ;; nh3000) basic_machine=m68k-harris os=-cxux ;; nh[45]000) basic_machine=m88k-harris os=-cxux ;; nindy960) basic_machine=i960-intel os=-nindy ;; mon960) basic_machine=i960-intel os=-mon960 ;; nonstopux) basic_machine=mips-compaq os=-nonstopux ;; np1) basic_machine=np1-gould ;; nsr-tandem) basic_machine=nsr-tandem ;; op50n-* | op60c-*) basic_machine=hppa1.1-oki os=-proelf ;; openrisc | openrisc-*) basic_machine=or32-unknown ;; os400) basic_machine=powerpc-ibm os=-os400 ;; OSE68000 | ose68000) basic_machine=m68000-ericsson os=-ose ;; os68k) basic_machine=m68k-none os=-os68k ;; pa-hitachi) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; paragon) basic_machine=i860-intel os=-osf ;; pbd) basic_machine=sparc-tti ;; pbb) basic_machine=m68k-tti ;; pc532 | pc532-*) basic_machine=ns32k-pc532 ;; pc98) basic_machine=i386-pc ;; pc98-*) basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium | p5 | k5 | k6 | nexgen | viac3) basic_machine=i586-pc ;; pentiumpro | p6 | 6x86 | athlon | athlon_*) basic_machine=i686-pc ;; pentiumii | pentium2 | pentiumiii | pentium3) basic_machine=i686-pc ;; pentium4) basic_machine=i786-pc ;; pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumpro-* | p6-* | 6x86-* | athlon-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium4-*) basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pn) basic_machine=pn-gould ;; power) basic_machine=power-ibm ;; ppc) basic_machine=powerpc-unknown ;; ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64) basic_machine=powerpc64-unknown ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64le | powerpc64little | ppc64-le | powerpc64-little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ps2) basic_machine=i386-ibm ;; pw32) basic_machine=i586-unknown os=-pw32 ;; rdos) basic_machine=i386-pc os=-rdos ;; rom68k) basic_machine=m68k-rom68k os=-coff ;; rm[46]00) basic_machine=mips-siemens ;; rtpc | rtpc-*) basic_machine=romp-ibm ;; s390 | s390-*) basic_machine=s390-ibm ;; s390x | s390x-*) basic_machine=s390x-ibm ;; sa29200) basic_machine=a29k-amd os=-udi ;; sb1) basic_machine=mipsisa64sb1-unknown ;; sb1el) basic_machine=mipsisa64sb1el-unknown ;; sde) basic_machine=mipsisa32-sde os=-elf ;; sei) basic_machine=mips-sei os=-seiux ;; sequent) basic_machine=i386-sequent ;; sh) basic_machine=sh-hitachi os=-hms ;; sh64) basic_machine=sh64-unknown ;; sparclite-wrs | simso-wrs) basic_machine=sparclite-wrs os=-vxworks ;; sps7) basic_machine=m68k-bull os=-sysv2 ;; spur) basic_machine=spur-unknown ;; st2000) basic_machine=m68k-tandem ;; stratus) basic_machine=i860-stratus os=-sysv4 ;; sun2) basic_machine=m68000-sun ;; sun2os3) basic_machine=m68000-sun os=-sunos3 ;; sun2os4) basic_machine=m68000-sun os=-sunos4 ;; sun3os3) basic_machine=m68k-sun os=-sunos3 ;; sun3os4) basic_machine=m68k-sun os=-sunos4 ;; sun4os3) basic_machine=sparc-sun os=-sunos3 ;; sun4os4) basic_machine=sparc-sun os=-sunos4 ;; sun4sol2) basic_machine=sparc-sun os=-solaris2 ;; sun3 | sun3-*) basic_machine=m68k-sun ;; sun4) basic_machine=sparc-sun ;; sun386 | sun386i | roadrunner) basic_machine=i386-sun ;; sv1) basic_machine=sv1-cray os=-unicos ;; symmetry) basic_machine=i386-sequent os=-dynix ;; t3e) basic_machine=alphaev5-cray os=-unicos ;; t90) basic_machine=t90-cray os=-unicos ;; tic54x | c54x*) basic_machine=tic54x-unknown os=-coff ;; tic55x | c55x*) basic_machine=tic55x-unknown os=-coff ;; tic6x | c6x*) basic_machine=tic6x-unknown os=-coff ;; tx39) basic_machine=mipstx39-unknown ;; tx39el) basic_machine=mipstx39el-unknown ;; toad1) basic_machine=pdp10-xkl os=-tops20 ;; tower | tower-32) basic_machine=m68k-ncr ;; tpf) basic_machine=s390x-ibm os=-tpf ;; udi29k) basic_machine=a29k-amd os=-udi ;; ultra3) basic_machine=a29k-nyu os=-sym1 ;; v810 | necv810) basic_machine=v810-nec os=-none ;; vaxv) basic_machine=vax-dec os=-sysv ;; vms) basic_machine=vax-dec os=-vms ;; vpp*|vx|vx-*) basic_machine=f301-fujitsu ;; vxworks960) basic_machine=i960-wrs os=-vxworks ;; vxworks68) basic_machine=m68k-wrs os=-vxworks ;; vxworks29k) basic_machine=a29k-wrs os=-vxworks ;; w65*) basic_machine=w65-wdc os=-none ;; w89k-*) basic_machine=hppa1.1-winbond os=-proelf ;; xbox) basic_machine=i686-pc os=-mingw32 ;; xps | xps100) basic_machine=xps100-honeywell ;; ymp) basic_machine=ymp-cray os=-unicos ;; z8k-*-coff) basic_machine=z8k-unknown os=-sim ;; none) basic_machine=none-none os=-none ;; # Here we handle the default manufacturer of certain CPU types. It is in # some cases the only manufacturer, in others, it is the most popular. w89k) basic_machine=hppa1.1-winbond ;; op50n) basic_machine=hppa1.1-oki ;; op60c) basic_machine=hppa1.1-oki ;; romp) basic_machine=romp-ibm ;; mmix) basic_machine=mmix-knuth ;; rs6000) basic_machine=rs6000-ibm ;; vax) basic_machine=vax-dec ;; pdp10) # there are many clones, so DEC is not a safe bet basic_machine=pdp10-unknown ;; pdp11) basic_machine=pdp11-dec ;; we32k) basic_machine=we32k-att ;; sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele) basic_machine=sh-unknown ;; sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) basic_machine=sparc-sun ;; cydra) basic_machine=cydra-cydrome ;; orion) basic_machine=orion-highlevel ;; orion105) basic_machine=clipper-highlevel ;; mac | mpw | mac-mpw) basic_machine=m68k-apple ;; pmac | pmac-mpw) basic_machine=powerpc-apple ;; *-unknown) # Make sure to match an already-canonicalized machine name. ;; *) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; esac # Here we canonicalize certain aliases for manufacturers. case $basic_machine in *-digital*) basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` ;; *-commodore*) basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` ;; *) ;; esac # Decode manufacturer-specific aliases for certain operating systems. if [ x"$os" != x"" ] then case $os in # First match some system type aliases # that might get confused with valid system types. # -solaris* is a basic system type, with this one exception. -solaris1 | -solaris1.*) os=`echo $os | sed -e 's|solaris1|sunos4|'` ;; -solaris) os=-solaris2 ;; -svr4*) os=-sysv4 ;; -unixware*) os=-sysv4.2uw ;; -gnu/linux*) os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` ;; # First accept the basic system types. # The portable systems comes first. # Each alternative MUST END IN A *, to match a version number. # -sysv* is not here because it comes later, after sysvr4. -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ | -aos* \ | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ | -openbsd* | -solidbsd* \ | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ | -chorusos* | -chorusrdb* \ | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \ | -uxpv* | -beos* | -mpeix* | -udk* \ | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ | -skyos* | -haiku* | -rdos* | -toppers*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) case $basic_machine in x86-* | i*86-*) ;; *) os=-nto$os ;; esac ;; -nto-qnx*) ;; -nto*) os=`echo $os | sed -e 's|nto|nto-qnx|'` ;; -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \ | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) ;; -mac*) os=`echo $os | sed -e 's|mac|macos|'` ;; -linux-dietlibc) os=-linux-dietlibc ;; -linux*) os=`echo $os | sed -e 's|linux|linux-gnu|'` ;; -sunos5*) os=`echo $os | sed -e 's|sunos5|solaris2|'` ;; -sunos6*) os=`echo $os | sed -e 's|sunos6|solaris3|'` ;; -opened*) os=-openedition ;; -os400*) os=-os400 ;; -wince*) os=-wince ;; -osfrose*) os=-osfrose ;; -osf*) os=-osf ;; -utek*) os=-bsd ;; -dynix*) os=-bsd ;; -acis*) os=-aos ;; -atheos*) os=-atheos ;; -syllable*) os=-syllable ;; -386bsd) os=-bsd ;; -ctix* | -uts*) os=-sysv ;; -nova*) os=-rtmk-nova ;; -ns2 ) os=-nextstep2 ;; -nsk*) os=-nsk ;; # Preserve the version number of sinix5. -sinix5.*) os=`echo $os | sed -e 's|sinix|sysv|'` ;; -sinix*) os=-sysv4 ;; -tpf*) os=-tpf ;; -triton*) os=-sysv3 ;; -oss*) os=-sysv3 ;; -svr4) os=-sysv4 ;; -svr3) os=-sysv3 ;; -sysvr4) os=-sysv4 ;; # This must come after -sysvr4. -sysv*) ;; -ose*) os=-ose ;; -es1800*) os=-ose ;; -xenix) os=-xenix ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) os=-mint ;; -aros*) os=-aros ;; -kaos*) os=-kaos ;; -zvmoe) os=-zvmoe ;; -none) ;; *) # Get rid of the `-' at the beginning of $os. os=`echo $os | sed 's/[^-]*-//'` echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 exit 1 ;; esac else # Here we handle the default operating systems that come with various machines. # The value should be what the vendor currently ships out the door with their # machine or put another way, the most popular os provided with the machine. # Note that if you're going to try to match "-MANUFACTURER" here (say, # "-sun"), then you have to tell the case statement up towards the top # that MANUFACTURER isn't an operating system. Otherwise, code above # will signal an error saying that MANUFACTURER isn't an operating # system, and we'll never get to this point. case $basic_machine in score-*) os=-elf ;; spu-*) os=-elf ;; *-acorn) os=-riscix1.2 ;; arm*-rebel) os=-linux ;; arm*-semi) os=-aout ;; c4x-* | tic4x-*) os=-coff ;; # This must come before the *-dec entry. pdp10-*) os=-tops20 ;; pdp11-*) os=-none ;; *-dec | vax-*) os=-ultrix4.2 ;; m68*-apollo) os=-domain ;; i386-sun) os=-sunos4.0.2 ;; m68000-sun) os=-sunos3 # This also exists in the configure program, but was not the # default. # os=-sunos4 ;; m68*-cisco) os=-aout ;; mips*-cisco) os=-elf ;; mips*-*) os=-elf ;; or32-*) os=-coff ;; *-tti) # must be before sparc entry or we get the wrong os. os=-sysv3 ;; sparc-* | *-sun) os=-sunos4.1.1 ;; *-be) os=-beos ;; *-haiku) os=-haiku ;; *-ibm) os=-aix ;; *-knuth) os=-mmixware ;; *-wec) os=-proelf ;; *-winbond) os=-proelf ;; *-oki) os=-proelf ;; *-hp) os=-hpux ;; *-hitachi) os=-hiux ;; i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) os=-sysv ;; *-cbm) os=-amigaos ;; *-dg) os=-dgux ;; *-dolphin) os=-sysv3 ;; m68k-ccur) os=-rtu ;; m88k-omron*) os=-luna ;; *-next ) os=-nextstep ;; *-sequent) os=-ptx ;; *-crds) os=-unos ;; *-ns) os=-genix ;; i370-*) os=-mvs ;; *-next) os=-nextstep3 ;; *-gould) os=-sysv ;; *-highlevel) os=-bsd ;; *-encore) os=-bsd ;; *-sgi) os=-irix ;; *-siemens) os=-sysv4 ;; *-masscomp) os=-rtu ;; f30[01]-fujitsu | f700-fujitsu) os=-uxpv ;; *-rom68k) os=-coff ;; *-*bug) os=-coff ;; *-apple) os=-macos ;; *-atari*) os=-mint ;; *) os=-none ;; esac fi # Here we handle the case where we know the os, and the CPU type, but not the # manufacturer. We pick the logical manufacturer. vendor=unknown case $basic_machine in *-unknown) case $os in -riscix*) vendor=acorn ;; -sunos*) vendor=sun ;; -aix*) vendor=ibm ;; -beos*) vendor=be ;; -hpux*) vendor=hp ;; -mpeix*) vendor=hp ;; -hiux*) vendor=hitachi ;; -unos*) vendor=crds ;; -dgux*) vendor=dg ;; -luna*) vendor=omron ;; -genix*) vendor=ns ;; -mvs* | -opened*) vendor=ibm ;; -os400*) vendor=ibm ;; -ptx*) vendor=sequent ;; -tpf*) vendor=ibm ;; -vxsim* | -vxworks* | -windiss*) vendor=wrs ;; -aux*) vendor=apple ;; -hms*) vendor=hitachi ;; -mpw* | -macos*) vendor=apple ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) vendor=atari ;; -vos*) vendor=stratus ;; esac basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` ;; esac echo $basic_machine$os exit # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: skyeye-1.2.5_REL/device/0000755000175000001440000000000011023523234013470 5ustar kshusersskyeye-1.2.5_REL/device/touchscreen/0000755000175000001440000000000011023514411016007 5ustar kshusersskyeye-1.2.5_REL/device/touchscreen/skyeye_touchscreen.c0000644000175000001440000000435010600516406022076 0ustar kshusers/* skyeye_touchscreen.c - skyeye general touchscreen device support functions Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/19/2007 initial version by Anthony Lee */ #include "skyeye_device.h" #include "skyeye_options.h" #include "skyeye.h" #include "skyeye_touchscreen.h" unsigned int Pen_buffer[8]; /* * touchscreen_init() : Initialize the touchscreen module set. * If you want to add a new touchscreen simulation, * just add a "touchscreen_*_init" function to it. */ static void touchscreen_init (struct device_module_set *mod_set) { memset(&Pen_buffer[0], 0, sizeof(Pen_buffer)); touchscreen_skyeye_init (mod_set); } static int touchscreen_setup(struct device_desc *dev, void *option) { struct touchscreen_device *ts_dev; struct touchscreen_option *ts_opt = (struct touchscreen_option*)option; int ret = 0; ts_dev = (struct touchscreen_device*)malloc(sizeof(struct touchscreen_device)); if (ts_dev == NULL) return 1; memset(ts_dev, 0, sizeof(struct touchscreen_device)); /* TODO */ dev->dev = (void*)ts_dev; return ret; } static struct device_module_set ts_mod_set = { .name = "touchscreen", .count = 0, .count_max = 0, .init = touchscreen_init, .initialized = 0, .setup_module = touchscreen_setup, }; /* * touchscreen_register() : Used by global device initialize function. */ void touchscreen_register(void) { if (register_device_module_set(&ts_mod_set)) { SKYEYE_ERR("\"%s\" module set register error!\n", ts_mod_set.name); } } /* help functions. */ skyeye-1.2.5_REL/device/touchscreen/dev_touchscreen_skyeye.c0000644000175000001440000001012710600516406022733 0ustar kshusers/* dev_touchscreen_skyeye.c - skyeye custom touchscreen simulation Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/19/2007 initial version, most from skyeye_mach_ep7312.c by ywc. * Anthony Lee */ #include #include "skyeye_config.h" #include "skyeye_device.h" /* Pen_buffer: defined in skyeye_touchscreen.c */ extern unsigned int Pen_buffer[8]; struct ts_skyeye_io { uint32_t ts_buffer[8]; }; static struct device_default_value skyeye_ts_def[] = { /* name base size interrupt array */ #if 0 {"at91", 0xff00b000, 0x20, {17, 0, 0, 0}}, {"ep7312", 0x8000b000, 0x20, {6, 0, 0, 0}}, {"pxa_lubbock", 0x40000300, 0x20, {15, 0, 0, 0}}, {"pxa_mainstone", 0x40000300, 0x20, {15, 0, 0, 0}}, #endif {NULL}, }; static void ts_skyeye_set_update_intr(struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct machine_config *mc = (struct machine_config*)dev->mach; struct ts_skyeye_io *io = (struct ts_skyeye_io*)dev->data; if (mc->mach_set_intr == NULL) return; mc->mach_set_intr(intr->interrupts[0]); if (mc->mach_update_intr != NULL) mc->mach_update_intr(mc); } static void ts_skyeye_fini(struct device_desc *dev) { struct ts_skyeye_io *io = (struct ts_skyeye_io*)dev->data; free(dev->dev); free(io); } static void ts_skyeye_reset(struct device_desc *dev) { struct touchscreen_device *ts_dev = (struct touchscreen_device*)dev->dev; struct ts_skyeye_io *io = (struct ts_skyeye_io*) dev->data; memset(io, 0, sizeof(struct ts_skyeye_io)); } static void ts_skyeye_update(struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct touchscreen_device *ts_dev = (struct touchscreen_device*)dev->dev; struct ts_skyeye_io *io = (struct ts_skyeye_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; if (mc->mach_pending_intr == NULL) return; if ((!mc->mach_pending_intr(intr->interrupts[0]))) { /* if now has no ts interrupt, then query */ if (Pen_buffer[6] == 1) { /* interrupt */ *(io->ts_buffer + 0) = Pen_buffer[0]; *(io->ts_buffer + 1) = Pen_buffer[1]; *(io->ts_buffer + 4) = Pen_buffer[4]; *(io->ts_buffer + 6) = Pen_buffer[6]; ts_skyeye_set_update_intr(dev); /* update interrupt, ts driver will clear it */ Pen_buffer[6] = 0; } } } static int ts_skyeye_read_word(struct device_desc *dev, uint32_t addr, uint32_t *data) { struct touchscreen_device *ts_dev = (struct touchscreen_device*) dev->dev; struct ts_skyeye_io *io = (struct ts_skyeye_io*)dev->data; int offset = (addr & ~3) - dev->base; *data = io->ts_buffer[offset / 4]; return ADDR_HIT; } static int ts_skyeye_write_word(struct device_desc *dev, uint32_t addr, uint32_t data) { return ADDR_NOHIT; } static int ts_skyeye_setup(struct device_desc *dev) { struct ts_skyeye_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = ts_skyeye_fini; dev->reset = ts_skyeye_reset; dev->update = ts_skyeye_update; dev->read_word = ts_skyeye_read_word; dev->write_word = ts_skyeye_write_word; io = (struct ts_skyeye_io*)malloc(sizeof(struct ts_skyeye_io)); if (io == NULL) return 1; dev->data = (void*)io; ts_skyeye_reset(dev); /* see if we need to set default values. */ set_device_default(dev, skyeye_ts_def); return 0; } void touchscreen_skyeye_init(struct device_module_set *mod_set) { register_device_module("skyeye", mod_set, &ts_skyeye_setup); } skyeye-1.2.5_REL/device/touchscreen/skyeye_touchscreen.h0000644000175000001440000000234710600516406022107 0ustar kshusers/* skyeye_touchscreen.h - skyeye general touchscreen device support functions Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/19/2007 initial version by Anthony Lee */ #ifndef __SKYEYE_TOUCHSCREEN_H_ #define __SKYEYE_TOUCHSCREEN_H_ #include "skyeye_device.h" struct touchscreen_device { }; /* touchscreen controller initialize functions*/ extern void touchscreen_skyeye_init(struct device_module_set *mod_set); /* help function*/ #endif /* __SKYEYE_TOUCHSCREEN_H_ */ skyeye-1.2.5_REL/device/lcd/0000755000175000001440000000000011023514411014227 5ustar kshusersskyeye-1.2.5_REL/device/lcd/dev_lcd_s3c2410.h0000644000175000001440000000361410541455476017106 0ustar kshusers/* dev_lcd_s3c2410.h - skyeye S3C2410 lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 07/25/2005 initial version * walimis * */ #ifndef __DEV_LCD_S3C2410_H_ #define __DEV_LCD_S3C2410_H_ #define VBUFSIZ 0x00001fff /* Video buffer size (bits/128-1) */ #define LINELEN 0x0007e000 /* Line length (pix/16-1) */ #define LINELEN_SHIFT 13 #define PIXPSC 0x01f80000 /* Pixel prescale (526628/pixels-1) */ #define PIXPSC_SHIFT 19 #define ACPSC 0x3e000000 /* AC prescale */ #define ACPSC_SHIFT 25 #define GSEN 0x40000000 /* Grayscale enable (0: monochrome) */ #define GSMD 0x80000000 /* Grayscale mode (0: 2 bit, 1: 4 bit) */ #define LCDCON1 (0x0) #define LCDCON2 (0x4 * 1) #define LCDCON3 (0x4 * 2) #define LCDCON4 (0x4 * 3) #define LCDCON5 (0x4 * 4) #define LCDSADDR1 (0x4 * 5) #define LCDSADDR2 (0x4 * 6) #define LCDSADDR3 (0x4 * 7) typedef struct lcd_s3c2410_io { u32 lcdcon1; u32 lcdcon2; u32 lcdcon3; u32 lcdcon4; u32 lcdcon5; u32 lcdsaddr1; u32 lcdsaddr2; u32 lcdsaddr3; u32 lcdintpnd; u32 lcdsrcpnd; u32 lcdintmsk; } lcd_s3c2410_io_t; #endif //_DEV_LCD_S3C2410_H_ skyeye-1.2.5_REL/device/lcd/dev_lcd_au1100.h0000644000175000001440000000505310577550314017011 0ustar kshusers/* dev_lcd_au1100.h - skyeye Alchemy Au1100TM lcd controllor simulation Copyright (C) 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/19/2007 written by Anthony Lee */ #ifndef __DEV_LCD_AU1100_H_ #define __DEV_LCD_AU1100_H_ #include #define AU1100_LCD_CONTROL (0x0000) #define AU1100_LCD_INT_STATUS (0x0004) #define AU1100_LCD_INT_ENABLE (0x0008) #define AU1100_LCD_HORZ_TIMING (0x000c) #define AU1100_LCD_VERT_TIMING (0x0010) #define AU1100_LCD_CLK_CONTROL (0x0014) #define AU1100_LCD_DMA_ADDR0 (0x0018) #define AU1100_LCD_DMA_ADDR1 (0x001c) #define AU1100_LCD_WORDS (0x0020) #define AU1100_LCD_PWM_DIV (0x0024) #define AU1100_LCD_PWM_HI (0x0028) #define AU1100_LCD_PALLETTE_BASE (0x0400) typedef struct lcd_au1100_io { uint32_t control; uint32_t int_status; uint32_t int_enable; uint32_t horz_timing; uint32_t vert_timing; uint32_t clk_control; uint32_t dma_addr0; uint32_t dma_addr1; uint32_t words; uint32_t pwm_div; uint32_t pwm_hi; uint8_t pallette[256]; } lcd_au1100_io_t; #define AU1100_LCD_6BITS_DATA_FORMAT(io) ((io->control >> 18) & 0x7) #define AU1100_LCD_ROTATE_DEGREE(io) ((io->control >> 13) & 0x3) #define AU1100_LCD_IS_BGR_ELSE_RGB(io) ((io->control >> 11) & 0x1) #define AU1100_LCD_IS_DUAL_PANEL(io) ((io->control >> 10) & 0x1) #define AU1100_LCD_PIXEL_ORDER(io) ((io->control >> 8) & 0x3) #define AU1100_LCD_MONO_IS_8BITS_ELSE_4BITS(io) ((io->control >> 7) & 0x1) #define AU1100_LCD_IS_COLOR_ELSE_MONO(io) ((io->control >> 5) & 0x1) #define AU1100_LCD_BITS_PER_PIXEL(io) ((io->control >> 1) & 0x7) #define AU1100_LCD_GO(io) (io->control & 0x1) #define AU1100_LCD_WIDTH(io) ((io->horz_timing & 0x3ff) + 1) #define AU1100_LCD_HEIGHT(io) ((io->vert_timing & 0x3ff) + 1) #define AU1100_LCD_FRAMEBUFFER_ADDR(io) (io->dma_addr0 >> 5) #endif /* __DEV_LCD_AU1100_H_ */ skyeye-1.2.5_REL/device/lcd/skyeye_lcd_beos.cpp0000644000175000001440000002452210610103373020105 0ustar kshusers/* skyeye_lcd_beos.cpp - LCD display emulation on BeOS' BWindow. Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/31/2007 written by Anthony Lee */ #include #include #include #include "skyeye_lcd_beos.h" extern "C" { extern void beos_lcd_skPenEvent(unsigned int *buffer, int eventType, int stateType, int x, int y); /* defined in skyeye_lcd.c, but we don't include the "skyeye_lcd.h" */ extern void skyeye_convert_color_from_lcd_dma(void *lcd_dev, int x, int y, int w, int h, void (*func)(uint32_t color, void *user_data1, void *user_data2), void *user_data, void *user_data2); void* SkyEyeLCD_Be_new(int width, int virtual_width, int height, int depth, const uint32_t *colormap, const void *bufferFB, unsigned int *bufferPen, lcd_lookup_color_func func, void *lcd_dev) { SkyEyeLCD_Be *lcd = new SkyEyeLCD_Be(width, virtual_width, height, depth, colormap, bufferFB, bufferPen, func, lcd_dev); if(lcd->InitCheck() == B_OK) return (void*)lcd; delete lcd; return NULL; } void SkyEyeLCD_Be_delete(void *_lcd) { SkyEyeLCD_Be *lcd = (SkyEyeLCD_Be*)_lcd; if(lcd) delete lcd; } void SkyEyeLCD_Be_Update(void *_lcd) { SkyEyeLCD_Be *lcd = (SkyEyeLCD_Be*)_lcd; if(lcd) lcd->Update(); } void SkyEyeLCD_Be_DMAChanged(void *_lcd, int l, int t, int r, int b) { SkyEyeLCD_Be *lcd = (SkyEyeLCD_Be*)_lcd; if(lcd) lcd->DMAChanged(l, t, r, b); } } // extern "C" static void SkyEyeLCD_Be_At_Exit_Callback() { while(be_app_messenger.SendMessage(B_QUIT_REQUESTED) == B_OK) snooze(500000); } static int32 SkyEyeLCD_Be_Thread_App(void *data) { new BApplication("application/x-vnd.skyeye-lcd-app"); atexit(SkyEyeLCD_Be_At_Exit_Callback); be_app->Run(); delete be_app; return 0; } bool SkyEyeLCD_Be::InitApplication() { if(be_app_messenger.IsValid()) return true; thread_id tid = spawn_thread(SkyEyeLCD_Be_Thread_App, NULL, B_URGENT_DISPLAY_PRIORITY, NULL); if(tid < 0 || resume_thread(tid) != B_OK) return false; while(be_app_messenger.IsValid() == false) snooze(100000); return true; } bool SkyEyeLCD_Be::IsDepthSupported(int depth) const { switch(depth) { case 1: case 8: case 16: case 24: case 32: return true; case 2: return(fLookupColorFunc != NULL); case 4: return(fLookupColorFunc != NULL || fColormap != NULL); default: return false; } } status_t SkyEyeLCD_Be::InitCheck() const { if(fWidth <= 0 || fVirtualWidth < fWidth || fHeight <= 0 || !IsDepthSupported(fDepth) || fBufferFB == NULL || (fLookupColorFunc != NULL && fDevice == NULL)) return B_ERROR; if(!fMsgr.IsValid() || fBitmap == NULL) return B_NO_INIT; return B_OK; } SkyEyeLCD_Be::SkyEyeLCD_Be(int width, int virtual_width, int height, int depth, const uint32_t *colormap, const void *bufferFB, unsigned int *bufferPen, lcd_lookup_color_func func, void *lcd_dev) : fWidth(width), fVirtualWidth(virtual_width), fHeight(height), fDepth(depth), fColormap(colormap), fUpdateAll(true), fBufferFB(bufferFB), fBufferPen(bufferPen), fLookupColorFunc(func), fDevice(lcd_dev), fBitmap(NULL), fTimestamp(0) { if(InitApplication() == false || InitCheck() == B_ERROR) return; fBufferPenTmp = (unsigned int*)malloc(sizeof(unsigned int) * 8); fBitmap = new BBitmap(BRect(0, 0, (fLookupColorFunc == NULL ? fVirtualWidth : fWidth) - 1, fHeight - 1), (fDepth == 1 && fLookupColorFunc == NULL ? B_GRAY1 : B_RGB32), false); if(fBufferPenTmp == NULL || fBitmap->InitCheck() != B_OK) { if(fBufferPenTmp != NULL) free(fBufferPenTmp); if(fBitmap != NULL) delete fBitmap; fBufferPenTmp = NULL; fBitmap = NULL; return; } memcpy(fBufferPenTmp, fBufferPen, sizeof(unsigned int) * 8); BString title; title << width << "x" << height << "x" << depth << " SkyEye LCD & Touch Screen (BeOS)"; BWindow *win = new BWindow(BRect(100, 100, 100 + fWidth - 1, 100 + fHeight - 1), title.String(), B_TITLED_WINDOW, B_NOT_CLOSABLE | B_NOT_ZOOMABLE | B_NOT_RESIZABLE); BView *view = new SkyEyeLCD_Be_View(this); /* for B_GRAY1 */ view->SetHighColor(255, 255, 255); view->SetLowColor(0, 0, 0); win->Lock(); win->AddChild(view); win->Show(); fMsgr = BMessenger(view, NULL); win->Unlock(); } SkyEyeLCD_Be::~SkyEyeLCD_Be() { if(fMsgr.IsValid()) { while(fMsgr.LockTarget() == false) snooze(100000); BLooper *looper; BView *view = (BView*)fMsgr.Target(&looper); view->RemoveSelf(); looper->PostMessage(B_QUIT_REQUESTED); looper->Unlock(); delete view; } if(fBufferPenTmp != NULL) free(fBufferPenTmp); if(fBitmap != NULL) delete fBitmap; } void SkyEyeLCD_Be::DMAChanged(int l, int t, int r, int b) { while(fBitmap->LockBits() != B_OK); if (fUpdateRect.IsValid() == false) fUpdateRect = BRect(l, t, r, b); else fUpdateRect = (fUpdateRect | BRect(l, t, r, b)); fUpdateAll = false; fBitmap->UnlockBits(); } void SkyEyeLCD_Be::DMAConvertCallback(uint32_t c, uint8 **buf_addr, void *noused) { *(*buf_addr) = (c >> 16) & 0xff; *((*buf_addr) + 1)= (c >> 8) & 0xff; *((*buf_addr) + 2) = c & 0xff; *buf_addr = (*buf_addr) + 3; } void SkyEyeLCD_Be::Update() { while(fBitmap->LockBits() != B_OK); if(real_time_clock_usecs() - fTimestamp >= (bigtime_t)200000UL && (fUpdateAll || fUpdateRect.IsValid())) { void *data = NULL; int32 length, offset; color_space cs; BRect rect; if(fUpdateAll == false) { rect = fUpdateRect; rect.right += 1; rect.bottom += 1; fUpdateRect = BRect(); } else { rect = BRect(0, 0, fWidth, fHeight); } if(fLookupColorFunc != NULL) { offset = fWidth * (int)rect.top * 4; length = fWidth * rect.IntegerHeight() * 3; cs = B_RGB32; if((data = malloc(length)) != NULL) { uint8 *tmp = (uint8*)data; skyeye_convert_color_from_lcd_dma(fDevice, 0, (int)rect.top, fWidth, rect.IntegerHeight(), (void (*)(uint32_t, void*, void*))DMAConvertCallback, &tmp, NULL); } } else switch(fDepth) { case 1: data = (void*)fBufferFB; offset = fVirtualWidth * (int)rect.top / 8; length = fVirtualWidth * rect.IntegerHeight() / 8; cs = B_GRAY1; break; case 24: data = (void*)fBufferFB; offset = fVirtualWidth * (int)rect.top * 4; length = fVirtualWidth * rect.IntegerHeight() * 3; cs = B_RGB32; break; case 4: /* index */ case 8: /* 3-3-2 */ case 16: /* 5-6-5 */ case 32: offset = fVirtualWidth * (int)rect.top * 4; length = fVirtualWidth * rect.IntegerHeight() * 3; cs = B_RGB32; if((data = malloc(length)) != NULL) { uint8 *tmp = (uint8*)data; uint8 *buf = (uint8*)fBufferFB + fVirtualWidth * (int)rect.top * fDepth / 8; int32 count = fWidth * rect.IntegerHeight(); int32 i = 0; while(count-- > 0) { if(fDepth == 4) { uint32 c = *(fColormap + (count % 2 == 0 ? (*buf & 0xf) : (*buf >> 4))); *tmp++ = (c >> 16) & 0xff; // red *tmp++ = (c >> 8) & 0xff; // green *tmp++ = c & 0xff; // blue if(count % 2 == 0) buf++; } if(fDepth == 8) { *tmp++ = (*buf & 0xe0) | 0x1f; // red *tmp++ = ((*buf & 0x1c) << 3) | 0x1f; // green *tmp++ = ((*buf++ & 0x03) << 6) | 0x3f; // blue } else if(fDepth == 16) { *tmp++ = ((*((uint16*)buf) & 0xf800) >> 8) | 0x0007; // red *tmp++ = ((*((uint16*)buf) & 0x07e0) >> 3) | 0x0003; // green *tmp++ = ((*((uint16*)buf) & 0x001f) << 3) | 0x0007; // blue buf += 2; } else { uint32 c = *((uint32*)buf); *tmp++ = (c >> 16) & 0xff; // red *tmp++ = (c >> 8) & 0xff; // green *tmp++ = c & 0xff; // blue buf += 4; } if(++i == fWidth) { tmp += (fVirtualWidth - fWidth) * 3; buf += (fVirtualWidth - fWidth) * fDepth / 8; i = 0; } } } break; default: break; } if(data != NULL) { BMessage aMsg('slcd'); fBitmap->SetBits(data, length, offset, cs); if(data != fBufferFB) free(data); rect.right -= 1; rect.bottom -= 1; aMsg.AddRect("frame", rect); fMsgr.SendMessage(&aMsg); } fTimestamp = real_time_clock_usecs(); } memcpy(fBufferPen, fBufferPenTmp, sizeof(unsigned int) * 8); fBitmap->UnlockBits(); } SkyEyeLCD_Be_View::SkyEyeLCD_Be_View(SkyEyeLCD_Be *lcd) : BView(BRect(0, 0, lcd->fWidth - 1, lcd->fHeight - 1), NULL, B_FOLLOW_NONE, 0), fLCD(lcd) { } SkyEyeLCD_Be_View::~SkyEyeLCD_Be_View() { } void SkyEyeLCD_Be_View::MessageReceived(BMessage *msg) { BRect rect; switch(msg->what) { case 'slcd': if(msg->FindRect("frame", &rect) != B_OK) break; Draw(rect); break; default: BView::MessageReceived(msg); } } void SkyEyeLCD_Be_View::Draw(BRect updateRect) { while(fLCD->fBitmap->LockBits() != B_OK); DrawBitmap(fLCD->fBitmap, updateRect, updateRect); fLCD->fBitmap->UnlockBits(); } void SkyEyeLCD_Be_View::MouseDown(BPoint where) { while(fLCD->fBitmap->LockBits() != B_OK); beos_lcd_skPenEvent(fLCD->fBufferPenTmp, 0, 1, (int)where.x, (int)where.y); fLCD->fBitmap->UnlockBits(); } void SkyEyeLCD_Be_View::MouseUp(BPoint where) { while(fLCD->fBitmap->LockBits() != B_OK); beos_lcd_skPenEvent(fLCD->fBufferPenTmp, 1, 0, (int)where.x, (int)where.y); fLCD->fBitmap->UnlockBits(); } void SkyEyeLCD_Be_View::MouseMoved(BPoint where, uint32 code, const BMessage *a_message) { while(fLCD->fBitmap->LockBits() != B_OK); if(*(fLCD->fBufferPenTmp + 5) == 1) beos_lcd_skPenEvent(fLCD->fBufferPenTmp, 2, 1, (int)where.x, (int)where.y); fLCD->fBitmap->UnlockBits(); } skyeye-1.2.5_REL/device/lcd/dev_lcd_ep7312.c0000644000175000001440000001107010557466770017024 0ustar kshusers/* dev_lcd_ep7312.c - skyeye EP7312 serial lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/17/2005 initial verion for ep7312 */ #include "armdefs.h" #include "skyeye_device.h" #include "dev_lcd_ep7312.h" static struct device_default_value ep7312_lcd_def[] = { /* name base size interrupt array */ {"ep7312", 0x800002c0, 0x4, {0, 0, 0, 0}}, {"at91", 0xffc002c0, 0x4, {0, 0, 0, 0}}, {NULL}, }; static void ep7312_changed (struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_ep7312_io *io = (struct lcd_ep7312_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; u32 lcdcon = io->lcdcon; u32 vbufsiz = lcdcon & VBUFSIZ; u32 linelen = (lcdcon & LINELEN) >> LINELEN_SHIFT; lcd_dev->state = mc->state; lcd_dev->lcd_close (lcd_dev); lcd_dev->depth = 8; //test by ywc 2004-07-24 lcd_dev->width = (linelen + 1) * 16; if (linelen == 0x3b) { lcd_dev->depth = 12; //test by ywc 2004-10-14 lcd_dev->width = (linelen + 1) * 16 / 3; } lcd_dev->height = (vbufsiz + 1) * 128 / (lcd_dev->depth) / (lcd_dev->width); /* 2007-01-29 added by anthonylee */ lcd_dev->lcd_addr_begin = 0xc0000000; lcd_dev->lcd_open (lcd_dev); } static void lcd_ep7312_fini (struct device_desc *dev) { struct lcd_ep7312_io *io = (struct lcd_ep7312_io *) dev->data; if (!dev->dev) free (dev->dev); if (!io) free (io); } static void lcd_ep7312_reset (struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_ep7312_io *io = (struct lcd_ep7312_io *) dev->data; //io->lcdcon = GSEN|GSMD | 0x12bf | (0x27<<13); io->lcdcon = GSEN | GSMD | 0x95f | (0x13 << 13); /* 2007-01-29 removed by anthonylee */ #if 0 lcd_dev->lcd_addr_begin = 0xc0000000; lcd_dev->lcd_addr_end = 0xc0000000; #endif } static void lcd_ep7312_update (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_ep7312_io *io = (struct lcd_ep7312_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; if(lcd_dev->lcd_update) lcd_dev->lcd_update (lcd_dev); } int lcd_ep7312_read_word (struct device_desc *dev, u32 addr, u32 * data) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_ep7312_io *io = (struct lcd_ep7312_io *) dev->data; int offset = (addr - dev->base); int ret = ADDR_HIT; //printf("%s:addr %x, %x\n", __FUNCTION__, addr, MACON); *data = 0; switch (offset) { case 0: *data = io->lcdcon; break; default: break; } return ret; } int lcd_ep7312_write_word (struct device_desc *dev, u32 addr, u32 data) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_ep7312_io *io = (struct lcd_ep7312_io *) dev->data; int offset = (addr - dev->base); int ret = ADDR_HIT; //printf("%s:mach:%x\n", __FUNCTION__, dev->mach); switch (offset) { case 0: if (io->lcdcon != data) { io->lcdcon = data; ep7312_changed (dev); } break; default: ret = ADDR_NOHIT; break; } return ret; } static int lcd_ep7312_setup (struct device_desc *dev) { int i; struct lcd_ep7312_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = lcd_ep7312_fini; dev->reset = lcd_ep7312_reset; dev->update = lcd_ep7312_update; dev->read_word = lcd_ep7312_read_word; dev->write_word = lcd_ep7312_write_word; io = (struct lcd_ep7312_io *) malloc (sizeof (struct lcd_ep7312_io)); memset (io, 0, sizeof (struct lcd_ep7312_io)); if (io == NULL) return 1; dev->data = (void *) io; lcd_ep7312_reset (dev); /* see if we need to set default values. * */ set_device_default (dev, ep7312_lcd_def); return 0; } void lcd_ep7312_init (struct device_module_set *mod_set) { int i; register_device_module ("ep7312", mod_set, &lcd_ep7312_setup); } skyeye-1.2.5_REL/device/lcd/skyeye_lcd_gtk.c0000644000175000001440000003353311006356577017424 0ustar kshusers/* skyeye_lcd_gtk.c - LCD display emulation in an X window. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 1999 Written by Ben Williamson * 2004 - 2007 Modified by chy, zy, ywc, etc. * 04/13/2007 Modified for multi-devs by Anthony Lee */ #include "skyeye_lcd.h" #include #include extern unsigned int Pen_buffer[8]; typedef struct SkyEyeLCD_GTK { int width; int virtual_width; int height; int depth; GdkRectangle update_rect; gboolean update_all; guchar *rgbbuf; guint32 *fbmem; GdkRgbCmap *colormap; guint timer; GtkWidget *window; GtkWidget *drawing; struct lcd_device *dev; } SkyEyeLCD_GTK; static guint32 colors1b[2] = { 0x000000, 0xffffff }; static guint32 colors4b[16] = { 0x000000, 0x000080, 0x008000, 0x008080, 0x800000, 0x800080, 0x808000, 0x808080, 0xc0c0c0, 0x0000ff, 0x00ff00, 0x00ffff, 0xff0000, 0xff00ff, 0xffff00, 0xffffff }; static guint32 colors8b[256]; static void lcd_convert_callback(u32 c, u32 **buf_addr, void *noused) { /* the gtk's 32 bits rgb buffer : X-B-G-R */ *(*buf_addr) = ((c >> 16) | (c & 0xff00) | ((c & 0xff) << 16)); *buf_addr = ++(*buf_addr); } /* use rgbbuf */ static gint callback_expose_event(GtkWidget *widget, GdkEventExpose *event, SkyEyeLCD_GTK *lcd) { int i, j, x, y, pix, bit; int wordnum; //for lcd_depth==16 , 1 word contain 2 pixel guint32 fbdata; // |R1,G1,B1,R0,G0,B0| int tribytenum; //for lcd_depth==12, 3 byte contain 2 pixel guchar fbdata8_0; // |G0,R0| guchar fbdata8_1; // |R1,B0| guchar fbdata8_2; // |B1,G1| GdkRectangle rect; if (lcd == NULL || lcd->dev == NULL) return FALSE; if (lcd->update_all == FALSE) { if (lcd->update_rect.width < 0 || lcd->update_rect.height < 0) return TRUE; rect = lcd->update_rect; rect.width += 1; rect.height += 1; lcd->update_rect.x = 0; lcd->update_rect.y = 0; lcd->update_rect.width = -1; lcd->update_rect.height = -1; } else { rect.x = 0; rect.y = 0; rect.width = lcd->width; rect.height = lcd->height; } wordnum = lcd->virtual_width * rect.height * lcd->depth / 32; tribytenum = lcd->virtual_width * rect.height * lcd->depth / 24; // anthonylee 2007-01-29 : for lcd_lookup_color if (lcd->dev->lcd_lookup_color != NULL) { u32 *tmp = (u32*)lcd->rgbbuf + rect.y * lcd->width; skyeye_convert_color_from_lcd_dma(lcd->dev, 0, rect.y, lcd->width, rect.height, (void (*)(u32, void*, void*))lcd_convert_callback, &tmp, NULL); gdk_draw_rgb_32_image(widget->window, widget->style->fg_gc[GTK_STATE_NORMAL], 0, rect.y, lcd->width, rect.height, GDK_RGB_DITHER_NORMAL, (guchar*)((u32*)lcd->rgbbuf + rect.y * lcd->width), lcd->width * 4); } else switch (lcd->depth) { case 1: // case 2: case 4: // anthonylee 2007-01-28 for (j = rect.y; j < lcd->height; j++) { guchar *buf = (guchar*)lcd->fbmem + j * lcd->virtual_width * lcd->depth / 8; for (i = 0; i < lcd->width;) { int k; guchar c = *buf++; guchar *tmp = (guchar*)lcd->rgbbuf + j * lcd->virtual_width + i; for (k = 0; k < 8 / lcd->depth; k++, i++, tmp++) *tmp = (c >> (8 - ((k + 1) << (lcd->depth - 1)))) & ((1 << lcd->depth) - 1); } } gdk_draw_indexed_image(widget->window, widget->style->fg_gc[GTK_STATE_NORMAL], 0, rect.y, lcd->width, rect.height, GDK_RGB_DITHER_NORMAL, (guchar*)lcd->rgbbuf + rect.y * lcd->virtual_width * lcd->depth / 8, lcd->virtual_width, lcd->colormap); break; case 8: gdk_draw_indexed_image(widget->window, widget->style->fg_gc[GTK_STATE_NORMAL], 0, rect.y, lcd->width, rect.height, GDK_RGB_DITHER_NORMAL, (guchar*)lcd->rgbbuf + rect.y * lcd->virtual_width, lcd->virtual_width, lcd->colormap); break; case 12: for (i = lcd->virtual_width * rect.y / 2; i < tribytenum; i++) { fbdata8_0 = *((guchar*)lcd->fbmem + i * 3); fbdata8_1 = *((guchar*)lcd->fbmem + i * 3 + 1); fbdata8_2 = *((guchar*)lcd->fbmem + i * 3 + 2); *(lcd->rgbbuf + i * 6 + 0) = (fbdata8_0 & 0x0f) << 4; *(lcd->rgbbuf + i * 6 + 1) = (fbdata8_0 & 0xf0); *(lcd->rgbbuf + i * 6 + 2) = (fbdata8_1 & 0x0f) << 4; *(lcd->rgbbuf + i * 6 + 3) = (fbdata8_1 & 0xf0); *(lcd->rgbbuf + i * 6 + 4) = (fbdata8_2 & 0x0f) << 4; *(lcd->rgbbuf + i * 6 + 5) = (fbdata8_2 & 0xf0); } gdk_draw_rgb_image(widget->window, widget->style->fg_gc[GTK_STATE_NORMAL], 0, rect.y, lcd->width, rect.height, GDK_RGB_DITHER_MAX, (guchar*)lcd->rgbbuf + rect.y * lcd->virtual_width * 3, lcd->virtual_width * 3); break; case 16: for (i = lcd->virtual_width * rect.y / 2; i < wordnum; i++) { fbdata = *((guint32*)lcd->fbmem + i); *(lcd->rgbbuf + i * 6 + 0) = (guchar)((fbdata & 0x0000f800) >> 8); *(lcd->rgbbuf + i * 6 + 1) = (guchar)((fbdata & 0x000007e0) >> 3); *(lcd->rgbbuf + i * 6 + 2) = (guchar)((fbdata & 0x0000001f) << 3); *(lcd->rgbbuf + i * 6 + 3) = (guchar)((fbdata & 0xf8000000) >> 24); *(lcd->rgbbuf + i * 6 + 4) = (guchar)((fbdata & 0x07e00000) >> 19); *(lcd->rgbbuf + i * 6 + 5) = (guchar)((fbdata & 0x001f0000) >> 13); } gdk_draw_rgb_image(widget->window, widget->style->fg_gc[GTK_STATE_NORMAL], 0, rect.y, lcd->width, rect.height, GDK_RGB_DITHER_MAX, (guchar*)lcd->rgbbuf + rect.y * lcd->virtual_width * 3, lcd->virtual_width * 3); break; case 24: gdk_draw_rgb_image(widget->window, widget->style->fg_gc[GTK_STATE_NORMAL], 0, rect.y, lcd->width, rect.height, GDK_RGB_DITHER_NORMAL, (guchar*)lcd->rgbbuf + rect.y * lcd->virtual_width * 3, lcd->virtual_width * 3); break; case 32: gdk_draw_rgb_32_image(widget->window, widget->style->fg_gc[GTK_STATE_NORMAL], 0, rect.y, lcd->width, rect.height, GDK_RGB_DITHER_NORMAL, (guchar*)((u32*)lcd->rgbbuf + rect.y * lcd->virtual_width), lcd->virtual_width * 4); break; default: break; } return TRUE; } //********** touch srceen event callback funtion by ywc ************ static void skPenEvent(int *buffer, int eventType, int stateType, int x, int y) { // printf("\nSkyEye: skPenEvent():event type=%d\n(x=%d,y=%d)\n",down,x,y); buffer[0] = x; buffer[1] = y; buffer[2] = 0; // dx buffer[3] = 0; // dy buffer[4] = eventType; // event from pen (DOWN,UP,CLICK,MOVE) buffer[5] = stateType; // state of pen (DOWN,UP,ERROR) buffer[6] = 1; // no of the event buffer[7] = 0; // time of the event (ms) since ts_open } static void callback_button_press(GtkWidget *w, GdkEventButton *event) { skPenEvent(Pen_buffer, 0, 1, event->x, event->y); // g_print("button pressed , Skyeye get it !!!\n"); } static void callback_button_release(GtkWidget *w, GdkEventButton *event) { skPenEvent(Pen_buffer, 1, 0, event->x, event->y); // g_print("button released , Skyeye get it !!!\n\n"); } static void callback_motion_notify(GtkWidget *w, GdkEventMotion *event) { /* * when mouse is moving, generate an skyeye pen motion event * should changed to "when mouse is pressed and moving" */ if (Pen_buffer[5] == 1) skPenEvent(Pen_buffer, 2, 1, event->x, event->y); // g_print("and moving , Skyeye get it !!!\n"); } static gint callback_redraw(GtkWidget *window) { gtk_widget_queue_draw(window); return TRUE; } static int gtk_lcd_open(struct lcd_device *lcd_dev) { SkyEyeLCD_GTK *lcd; guint32 *fbmem; char *title; GtkWidget *touch_screen; if (lcd_dev == NULL || lcd_dev->priv != NULL || lcd_dev->width <= 0 || lcd_dev->height <= 0) return -1; if ((fbmem = (guint32*)skyeye_find_lcd_dma(lcd_dev)) == NULL) { fprintf(stderr, "[GTK_LCD]: Can't find LCD DMA from address 0x%x\n", lcd_dev->lcd_addr_begin); return -1; } if ((lcd = (SkyEyeLCD_GTK*)malloc(sizeof(SkyEyeLCD_GTK))) == NULL) return -1; memset(lcd, 0, sizeof(SkyEyeLCD_GTK)); lcd->width = lcd_dev->width; lcd->virtual_width = lcd_dev->width + (int)lcd_dev->lcd_line_offset; lcd->height = lcd_dev->height; lcd->depth = lcd_dev->depth; lcd->update_rect.width = -1; lcd->update_rect.height = -1; lcd->update_all = TRUE; lcd->fbmem = fbmem; lcd->dev = lcd_dev; if(lcd_dev->lcd_lookup_color != NULL) { lcd->rgbbuf = (guchar*)malloc(lcd->width * lcd->height * 4); } else switch (lcd->depth) { case 1: case 2: case 4: lcd->rgbbuf = (guchar*)malloc(lcd->virtual_width * lcd->height); break; case 12: case 16: lcd->rgbbuf = (guchar*)malloc(lcd->virtual_width * lcd->height * 3); break; case 8: case 24: case 32: lcd->rgbbuf = (guchar*)fbmem; break; default: break; } lcd->window = gtk_window_new(GTK_WINDOW_TOPLEVEL); gtk_signal_connect(GTK_OBJECT(lcd->window), "delete-event", GTK_SIGNAL_FUNC(gtk_true), NULL); if ((title = g_strdup_printf("%dx%dx%d SkyEye LCD & Touch Screen (GTK+)", lcd->width, lcd->height, lcd->depth)) != NULL) { gtk_window_set_title(GTK_WINDOW(lcd->window), title); g_free(title); } gtk_widget_set_usize(lcd->window, lcd->width, lcd->height); gtk_widget_set_events(lcd->window, GDK_EXPOSURE_MASK); touch_screen = gtk_event_box_new(); gtk_container_add(GTK_CONTAINER(lcd->window), touch_screen); gtk_widget_set_events(touch_screen, GDK_BUTTON_PRESS_MASK | GDK_BUTTON_RELEASE_MASK | GDK_POINTER_MOTION_MASK); gtk_signal_connect(GTK_OBJECT(touch_screen), "button-press-event", GTK_SIGNAL_FUNC(callback_button_press), NULL); gtk_signal_connect(GTK_OBJECT(touch_screen), "button-release-event", GTK_SIGNAL_FUNC(callback_button_release), NULL); gtk_signal_connect(GTK_OBJECT(touch_screen), "motion-notify-event", GTK_SIGNAL_FUNC(callback_motion_notify), NULL); gtk_widget_realize(touch_screen); gdk_window_set_cursor(touch_screen->window, gdk_cursor_new(GDK_HAND2)); //zy 2004-4-02 Add Drawing area lcd->drawing = gtk_drawing_area_new(); gtk_container_add(GTK_CONTAINER(touch_screen), lcd->drawing); gtk_signal_connect(GTK_OBJECT(lcd->drawing), "expose-event", GTK_SIGNAL_FUNC(callback_expose_event), lcd); gtk_widget_show_all(lcd->window); if (lcd_dev->lcd_lookup_color == NULL) switch (lcd->depth) { case 1: lcd->colormap = gdk_rgb_cmap_new(colors1b, 2); break; case 2: break; case 4: lcd->colormap = gdk_rgb_cmap_new(colors4b, 16); break; case 8: lcd->colormap = gdk_rgb_cmap_new(colors8b, 256); break; default: break; } lcd->timer = gtk_timeout_add(200, (GtkFunction)callback_redraw, lcd->window); lcd_dev->priv = (void*)lcd; return 0; } static int gtk_lcd_close(struct lcd_device *lcd_dev) { SkyEyeLCD_GTK *lcd = lcd_dev ? (SkyEyeLCD_GTK*)lcd_dev->priv : NULL; if(lcd == NULL) return -1; if (lcd->rgbbuf != NULL && lcd->rgbbuf != (void*)lcd->fbmem) free(lcd->rgbbuf); gtk_timeout_remove(lcd->timer); gtk_widget_destroy(lcd->window); if (lcd->colormap) gdk_rgb_cmap_free(lcd->colormap); free(lcd); lcd_dev->priv = NULL; lcd_dev->lcd_addr_end = lcd_dev->lcd_addr_begin = 0; return 0; } static int gtk_lcd_filter_write(struct lcd_device *lcd_dev, u32 addr, u32 data, size_t count) { int offsetADDR1, offsetADDR2; int w, x1, y1, x2, y2; SkyEyeLCD_GTK *lcd = lcd_dev ? (SkyEyeLCD_GTK*)(lcd_dev->priv) : NULL; if (lcd == NULL || addr < lcd_dev->lcd_addr_begin || addr > lcd_dev->lcd_addr_end) return 0; offsetADDR1 = (int)(addr - lcd_dev->lcd_addr_begin) * 8 / lcd->depth; offsetADDR2 = offsetADDR1 + (int)count * 8 / lcd->depth; w = lcd->virtual_width; x1 = MIN(offsetADDR1 % w, w - 1); y1 = MIN(offsetADDR1 / w, lcd->height - 1); x2 = MIN(offsetADDR2 % w, w - 1); y2 = MIN(offsetADDR2 / w, lcd->height - 1); if (lcd->update_rect.width < 0 || lcd->update_rect.height < 0) { lcd->update_rect.x = min(x1, x2); lcd->update_rect.y = min(y1, y2); lcd->update_rect.width = max(x1, x2) - lcd->update_rect.x; lcd->update_rect.height = max(y1, y2) - lcd->update_rect.y; } else { int l = min(min(x1, x2), lcd->update_rect.x); int t = min(min(y1, y2), lcd->update_rect.y); int r = max(max(x1, x2), lcd->update_rect.x + lcd->update_rect.width); int b = max(max(y1, y2), lcd->update_rect.y + lcd->update_rect.height); lcd->update_rect.x = l; lcd->update_rect.y = t; lcd->update_rect.width = r - l; lcd->update_rect.height = b - t; } lcd->update_all = FALSE; return 0; } static int gtk_lcd_update(struct lcd_device *lcd_dev) { if (lcd_dev == NULL || lcd_dev->priv == NULL) return -1; gtk_main_iteration_do(FALSE); return 0; } int gtk_lcd_init(struct lcd_device *lcd_dev) { static int tmp_argc = 0; static gboolean once = FALSE; guint32 i; if (lcd_dev == NULL) return -1; if (once == FALSE) { if (gtk_init_check(&tmp_argc, NULL) == FALSE) { fprintf(stderr, "[GTK_LCD]: Can't initalize GTK+\n"); return -1; } gdk_rgb_init(); // ywc 2004-07-24 creat the 256 colormap from 8 TRUE_COLOR-8-332 // should add PSEUDOCOLOR palette for depth==8 for (i = 0; i < 256; i++) { colors8b[i] = ((i & 0x000000e0) << 16) + ((i & 0x0000001c) << 11) + ((i & 0x00000003) << 6); } once = TRUE; } lcd_dev->lcd_open = gtk_lcd_open; lcd_dev->lcd_close = gtk_lcd_close; lcd_dev->lcd_update = gtk_lcd_update; lcd_dev->lcd_filter_read = NULL; lcd_dev->lcd_filter_write = gtk_lcd_filter_write; return 0; } skyeye-1.2.5_REL/device/lcd/dev_lcd_au1100.c0000644000175000001440000001500310577661541017005 0ustar kshusers/* dev_lcd_au1100.c - skyeye Alchemy Au1100TM lcd controllor simulation Copyright (C) 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/19/2007 written by Anthony Lee */ /* * WARNING: uncompleted yet !!! */ #include "skyeye_config.h" #include "skyeye_lcd.h" #include "dev_lcd_au1100.h" #define LCD_AU1100_DEBUG 1 #define PRINT(x...) printf("[LCD_AU1100]: " x) #if LCD_AU1100_DEBUG #define DEBUG(x...) printf("[LCD_AU1100]: " x) #else #define DEBUG(x...) (void)0 #endif static struct device_default_value au1100_lcd_def[] = { /* name base size interrupt array */ {"au1100", 0x15000000, 0x500, {0, 0, 0, 0}}, {NULL}, }; static void lcd_au1100_changed(struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device*)dev->dev; struct lcd_au1100_io *io = (struct lcd_au1100_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; int depth = 1, width, height; /* TODO: not test yet!!! */ if (AU1100_LCD_IS_COLOR_ELSE_MONO(io)) { depth = AU1100_LCD_BITS_PER_PIXEL(io); if (depth < 4) { depth = (1 << depth); } else if (depth < 6) { depth = (12 + (depth - 4) << 2); } else { PRINT(" *** WARNING: unsupported depth !!!\n"); return; } } width = AU1100_LCD_WIDTH(io); height = AU1100_LCD_HEIGHT(io); lcd_dev->state = mc->state; lcd_dev->lcd_close(lcd_dev); if (AU1100_LCD_GO(io)) { /* start sending framebuffer to LCD */ lcd_dev->lcd_line_offset = 0; lcd_dev->lcd_addr_begin = AU1100_LCD_FRAMEBUFFER_ADDR(io); lcd_dev->lcd_addr_end = lcd_dev->lcd_addr_begin + width * height * depth / 8 - 1; DEBUG("depth: %d, width: %d, height: %d\n", depth, width, height); DEBUG("control: 0x%x\n", io->control); DEBUG("horz_timing: 0x%x\n", io->horz_timing); DEBUG("vert_timing: 0x%x\n", io->vert_timing); DEBUG("dma_addr0: 0x%x\n", io->dma_addr0); DEBUG("dma_addr1: 0x%x\n", io->dma_addr1); DEBUG("words: 0x%x\n", io->words); DEBUG("lcd_addr_begin: 0x%x\n", lcd_dev->lcd_addr_begin); if (AU1100_LCD_IS_DUAL_PANEL(io)) PRINT(" *** WARNING: Dual scan mode unsupported !!!\n"); lcd_dev->depth = depth; lcd_dev->width = width; lcd_dev->height = height; lcd_dev->device_priv = (void*)io; lcd_dev->lcd_open(lcd_dev); } } static void lcd_au1100_fini(struct device_desc *dev) { struct lcd_au1100_io *io = (struct lcd_au1100_io*)dev->data; if(dev->dev != NULL) free(dev->dev); /* lcd_device from "lcd_setup()", so we free it. */ if(io != NULL) free(io); } static void lcd_au1100_reset(struct device_desc *dev) { struct lcd_au1100_io *io = (struct lcd_au1100_io*)dev->data; memset(io, 0, sizeof(struct lcd_au1100_io)); } static void lcd_au1100_update(struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device*)dev->dev; lcd_dev->lcd_update(lcd_dev); } int lcd_au1100_read_word(struct device_desc *dev, uint32_t addr, uint32_t *data) { struct lcd_au1100_io *io = (struct lcd_au1100_io*)dev->data; int offset = addr - dev->base; int ret = ADDR_HIT; *data = 0; if (offset >= AU1100_LCD_PALLETTE_BASE && offset < AU1100_LCD_PALLETTE_BASE + 0xff) { offset -= AU1100_LCD_PALLETTE_BASE; memcpy(data, &io->pallette[offset], (offset < 0xfb ? 4 : (0xff - offset))); return ret; } switch(offset) { case AU1100_LCD_CONTROL: *data = io->control; break; case AU1100_LCD_INT_STATUS: *data = io->int_status; break; case AU1100_LCD_INT_ENABLE: *data = io->int_enable; break; case AU1100_LCD_HORZ_TIMING: *data = io->horz_timing; break; case AU1100_LCD_VERT_TIMING: *data = io->vert_timing; break; case AU1100_LCD_CLK_CONTROL: *data = io->clk_control; break; case AU1100_LCD_DMA_ADDR0: *data = io->dma_addr0; break; case AU1100_LCD_DMA_ADDR1: *data = io->dma_addr1; break; case AU1100_LCD_WORDS: *data = io->words; break; case AU1100_LCD_PWM_DIV: *data = io->pwm_div; break; case AU1100_LCD_PWM_HI: *data = io->pwm_hi; break; default: break; } return ret; } int lcd_au1100_write_word(struct device_desc *dev, uint32_t addr, uint32_t data) { struct lcd_au1100_io *io = (struct lcd_au1100_io*)dev->data; int offset = addr - dev->base; int ret = ADDR_HIT; if (offset >= AU1100_LCD_PALLETTE_BASE && offset < AU1100_LCD_PALLETTE_BASE + 0xff) { offset -= AU1100_LCD_PALLETTE_BASE; memcpy(&io->pallette[offset], &data, (offset < 0xfb ? 4 : (0xff - offset))); return ret; } switch (offset) { case AU1100_LCD_CONTROL: if (io->control != data) { io->control = data; lcd_au1100_changed(dev); } break; case AU1100_LCD_INT_STATUS: io->int_status = data; break; case AU1100_LCD_INT_ENABLE: io->int_enable = data; break; case AU1100_LCD_HORZ_TIMING: io->horz_timing = data; break; case AU1100_LCD_VERT_TIMING: io->vert_timing = data; break; case AU1100_LCD_CLK_CONTROL: io->clk_control = data; break; case AU1100_LCD_DMA_ADDR0: io->dma_addr0 = data; break; case AU1100_LCD_DMA_ADDR1: io->dma_addr1 = data; break; case AU1100_LCD_WORDS: io->words = data; break; case AU1100_LCD_PWM_DIV: io->pwm_div = data; break; case AU1100_LCD_PWM_HI: io->pwm_hi = data; break; default: ret = ADDR_NOHIT; break; } return ret; } static int lcd_au1100_setup(struct device_desc *dev) { struct lcd_au1100_io *io; dev->fini = lcd_au1100_fini; dev->reset = lcd_au1100_reset; dev->update = lcd_au1100_update; dev->read_word = lcd_au1100_read_word; dev->write_word = lcd_au1100_write_word; if((io = (struct lcd_au1100_io*)malloc(sizeof(struct lcd_au1100_io))) == NULL) return -1; dev->data = (void*)io; lcd_au1100_reset(dev); /* see if we need to set default values. */ set_device_default(dev, au1100_lcd_def); return 0; } void lcd_au1100_init(struct device_module_set *mod_set) { register_device_module("au1100", mod_set, &lcd_au1100_setup); } skyeye-1.2.5_REL/device/lcd/dev_lcd_pxa.h0000644000175000001440000000314610541455476016677 0ustar kshusers/* dev_lcd_pxa.h - skyeye PXA25x lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/23/2005 initial version * walimis * */ #ifndef __DEV_LCD_PXA_H_ #define __DEV_LCD_PXA_H_ /* registers */ #define LCCR0 0x000000 #define LCCR1 0x000004 #define LCCR2 0x000008 #define LCCR3 0x00000C #define FDADR0 0x000200 #define FSADR0 0x000204 #define FIDR0 0x000208 #define LDCMD0 0x00020C #define FDADR1 0x000210 #define FSADR1 0x000214 #define FIDR1 0x000218 #define LDCMD1 0x00021C #define LCCR0_ENB 0x00000001 #define LCCR1_PPL 0x000003FF #define LCCR2_LPP 0x000003FF #define LCCR3_BPP 0x07000000 typedef struct lcd_pxa_io { u32 lccr0; u32 lccr1; u32 lccr2; u32 lccr3; u32 fdadr0; u32 fdadr1; u32 fsadr0; u32 fsadr1; } lcd_pxa_io_t; #endif //_DEV_LCD_PXA_H_ skyeye-1.2.5_REL/device/lcd/skyeye_lcd_beos.h0000644000175000001440000000605510610103373017553 0ustar kshusers/* skyeye_lcd_beos.h - LCD display emulation on BeOS' BWindow. Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/31/2007 written by Anthony Lee */ #ifndef __SKYEYE_LCD_BEOS_H__ #define __SKYEYE_LCD_BEOS_H__ #include typedef uint32_t (*lcd_lookup_color_func)(void *lcd_dev, uint32_t color); #ifdef __cplusplus /* Just for C++ */ #include #include #include #include #include class SkyEyeLCD_Be { public: SkyEyeLCD_Be(int width, int virtual_width, int height, int depth, const uint32_t *colormap, const void *bufferFB, unsigned int *bufferPen, lcd_lookup_color_func func, void *lcd_dev); ~SkyEyeLCD_Be(); status_t InitCheck() const; void Update(); void DMAChanged(int l, int t, int r, int b); private: friend class SkyEyeLCD_Be_View; int fWidth; int fVirtualWidth; int fHeight; int fDepth; const uint32_t *fColormap; BRect fUpdateRect; bool fUpdateAll; const void *fBufferFB; unsigned int *fBufferPen; unsigned int *fBufferPenTmp; void *fDevice; lcd_lookup_color_func fLookupColorFunc; BMessenger fMsgr; BBitmap *fBitmap; bigtime_t fTimestamp; bool IsDepthSupported(int depth) const; bool InitApplication(); static void DMAConvertCallback(uint32_t c, uint8 **buf_addr, void *noused); }; class SkyEyeLCD_Be_View : public BView { public: SkyEyeLCD_Be_View(SkyEyeLCD_Be *lcd); virtual ~SkyEyeLCD_Be_View(); virtual void MessageReceived(BMessage *msg); virtual void Draw(BRect updateRect); virtual void MouseDown(BPoint where); virtual void MouseUp(BPoint where); virtual void MouseMoved(BPoint where, uint32 code, const BMessage *a_message); private: SkyEyeLCD_Be *fLCD; }; extern "C" { #endif /* __cplusplus */ /* C functions called from C */ void* SkyEyeLCD_Be_new(int width, int virtual_width, int height, int depth, const uint32_t *colormap, const void *bufferFB, unsigned int *bufferPen, lcd_lookup_color_func func, void *lcd_dev); void SkyEyeLCD_Be_delete(void *lcd); void SkyEyeLCD_Be_Update(void *lcd); void SkyEyeLCD_Be_DMAChanged(void *lcd, int l, int t, int r, int b); #ifdef __cplusplus /* Just for C++ */ } // extern "C" #endif /* __cplusplus */ #endif /* __SKYEYE_LCD_BEOS_H__ */ skyeye-1.2.5_REL/device/lcd/dev_lcd_s3c44b0x.h0000644000175000001440000000336010556455515017357 0ustar kshusers/* dev_lcd_s3c44b0x.h - skyeye S3C44B0X lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/27/2007 initial version by Anthony Lee */ #ifndef __DEV_LCD_S3C44B0X_H_ #define __DEV_LCD_S3C44B0X_H_ #define LCDCON1 (0x0) #define LCDCON2 (0x4) #define LCDCON3 (0x40) #define LCDSADDR1 (0x8) #define LCDSADDR2 (0xc) #define LCDSADDR3 (0x10) #define REDLUT (0x14) #define GREENLUT (0x18) #define BLUELUT (0x1c) #define DP1_2 (0x20) #define DP4_7 (0x24) #define DP3_5 (0x28) #define DP2_3 (0x2c) #define DP5_7 (0x30) #define DP3_4 (0x34) #define DP4_5 (0x38) #define DP6_7 (0x3c) #define DITHMODE (0x44) typedef struct lcd_s3c44b0x_io { u32 lcdcon1; u32 lcdcon2; u32 lcdcon3; u32 lcdsaddr1; u32 lcdsaddr2; u32 lcdsaddr3; u32 lcdredlut; u32 lcdgreenlut; u32 lcdbluelut; u32 lcddp12; u32 lcddp47; u32 lcddp35; u32 lcddp23; u32 lcddp57; u32 lcddp34; u32 lcddp45; u32 lcddp67; u32 lcddithmode; } lcd_s3c44b0x_io_t; #endif /* _DEV_LCD_S3C44B0X_H_ */ skyeye-1.2.5_REL/device/lcd/skyeye_lcd.h0000644000175000001440000000506410607777061016563 0ustar kshusers/* skyeye_lcd.h - skyeye general lcd device file support functions Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __SKYEYE_LCD_H_ #define __SKYEYE_LCD_H_ #include "skyeye_device.h" #define LCD_MOD_NONE 0 #define LCD_MOD_GTK 1 #define LCD_MOD_QT 2 #define LCD_MOD_X 3 #define LCD_MOD_SDL 4 #define LCD_MOD_WIN32 5 #define LCD_MOD_BEOS 6 struct lcd_device { int mod; int width; int height; int depth; void *state; u32 lcd_addr_begin; u32 lcd_addr_end; /* private data. */ void *priv; int (*lcd_open) (struct lcd_device *lcd_dev); int (*lcd_close) (struct lcd_device *lcd_dev); int (*lcd_update) (struct lcd_device *lcd_dev); int (*lcd_filter_read) (struct lcd_device *lcd_dev, u32 addr, u32 *data, size_t count); int (*lcd_filter_write) (struct lcd_device *lcd_dev, u32 addr, u32 data, size_t count); /* below is customed by device */ void *device_priv; /* private data for device. */ u32 lcd_line_offset; /* pixels from the line's ending to the next line's starting. */ u32 (*lcd_lookup_color) (struct lcd_device *lcd_dev, u32 color); /* return RGB32 color. */ int lcd_color_right_to_left; /* whether color from right to left when depth < 32 */ int lcd_dma_swap_word; /* whether to swap word from dma, usually for big endian */ }; /* help functions. */ unsigned char* skyeye_find_lcd_dma (struct lcd_device *lcd_dev); void skyeye_convert_color_from_lcd_dma (struct lcd_device *lcd_dev, int x, int y, int w, int h, void (*func)(u32 color, void *user_data1, void *user_data2), void *user_data, void *user_data2); /* modules */ #ifdef GTK_LCD int gtk_lcd_init (struct lcd_device *lcd_dev); #endif #ifdef WIN32_LCD int win32_lcd_init (struct lcd_device *lcd_dev); #endif #ifdef BEOS_LCD int beos_lcd_init (struct lcd_device *lcd_dev); #endif #endif /*__SKYEYE_LCD_H_*/ skyeye-1.2.5_REL/device/lcd/dev_lcd_s3c2410.c0000644000175000001440000001204510552270410017060 0ustar kshusers/* dev_lcd_s3c2410.c - skyeye SAMSUNG s3c2410 lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/17/2005 initial verion for s3c2410 */ #include "armdefs.h" #include "skyeye_device.h" #include "dev_lcd_s3c2410.h" static struct device_default_value s3c2410_lcd_def[] = { /* name base size interrupt array */ {"s3c2410x", 0x4d000000, 0x60, {0, 0, 0, 0}}, {"s3c2440", 0x4d000000, 0x60, {0, 0, 0, 0}}, {NULL}, }; static void s3c2410_changed (struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_s3c2410_io *io = (struct lcd_s3c2410_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; int bppmode = ((io->lcdcon1 >> 1) & 0xF); int depth = 16; lcd_dev->state = mc->state; lcd_dev->lcd_close (lcd_dev); /* if ((bppmode <= 4)) { if (bppmode == 4) depth = 12; else depth = 2^bppmode; } else { if (bppmode == 0xd) depth = 24; else depth = 2^(bppmode - 8); } */ //printf("lcdsaddr1:%x\n", io->lcdsaddr1<<1); /* we here use lcdsaddr1 as lcd_addr_begin */ lcd_dev->lcd_addr_begin = io->lcdsaddr1 << 1; lcd_dev->depth = depth; lcd_dev->height = ((io->lcdcon2 >> 14) & 0x3ff) + 1; lcd_dev->width = ((io->lcdcon3 >> 8) & 0x7ff) + 1; lcd_dev->lcd_open (lcd_dev); } static void lcd_s3c2410_fini (struct device_desc *dev) { struct lcd_s3c2410_io *io = (struct lcd_s3c2410_io *) dev->data; if (!dev->dev) free (dev->dev); if (!io) free (io); } static void lcd_s3c2410_reset (struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_s3c2410_io *io = (struct lcd_s3c2410_io *) dev->data; //lcd_dev->lcd_addr_begin = 0xc0141000; //lcd_dev->lcd_addr_end = 0xc0141000; } static void lcd_s3c2410_update (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_s3c2410_io *io = (struct lcd_s3c2410_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; lcd_dev->lcd_update (lcd_dev); } int lcd_s3c2410_read_word (struct device_desc *dev, u32 addr, u32 * data) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_s3c2410_io *io = (struct lcd_s3c2410_io *) dev->data; int offset = (addr - dev->base); int ret = ADDR_HIT; //printf("%s:addr %x, %x\n", __FUNCTION__, addr, MACON); *data = 0; switch (offset) { case LCDCON1: *data = io->lcdcon1; break; case LCDCON2: *data = io->lcdcon2; break; case LCDCON3: *data = io->lcdcon3; break; case LCDCON4: *data = io->lcdcon4; break; case LCDCON5: *data = io->lcdcon5; break; default: break; } return ret; } int lcd_s3c2410_write_word (struct device_desc *dev, u32 addr, u32 data) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_s3c2410_io *io = (struct lcd_s3c2410_io *) dev->data; int offset = (addr - dev->base); int ret = ADDR_HIT; //printf("%s:mach:%x\n", __FUNCTION__, dev->mach); switch (offset) { case LCDCON1: if ((io->lcdcon1 != data) && (data & 0x1)) { io->lcdcon1 = data; s3c2410_changed (dev); } break; case LCDCON2: io->lcdcon2 = data; break; case LCDCON3: io->lcdcon3 = data; break; case LCDCON4: io->lcdcon4 = data; break; case LCDCON5: io->lcdcon5 = data; break; case LCDSADDR1: io->lcdsaddr1 = data; break; case LCDSADDR2: io->lcdsaddr2 = data; break; case LCDSADDR3: io->lcdsaddr3 = data; break; default: ret = ADDR_NOHIT; break; } return ret; } static int lcd_s3c2410_setup (struct device_desc *dev) { int i; struct lcd_s3c2410_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = lcd_s3c2410_fini; dev->reset = lcd_s3c2410_reset; dev->update = lcd_s3c2410_update; dev->read_word = lcd_s3c2410_read_word; dev->write_word = lcd_s3c2410_write_word; io = (struct lcd_s3c2410_io *) malloc (sizeof (struct lcd_s3c2410_io)); memset (io, 0, sizeof (struct lcd_s3c2410_io)); if (io == NULL) return 1; dev->data = (void *) io; lcd_s3c2410_reset (dev); /* see if we need to set default values. * */ set_device_default (dev, s3c2410_lcd_def); return 0; } void lcd_s3c2410_init (struct device_module_set *mod_set) { int i; register_device_module ("s3c2410x", mod_set, &lcd_s3c2410_setup); } skyeye-1.2.5_REL/device/lcd/skyeye_lcd_beos.c0000644000175000001440000000721510610103373017545 0ustar kshusers/* skyeye_lcd_beos.c - LCD display emulation on BeOS' BWindow. Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/31/2007 written by Anthony Lee */ #include "skyeye_lcd.h" #include "skyeye_lcd_beos.h" extern unsigned int Pen_buffer[8]; static u32 colors4b[16] = { 0x000000,0x000080,0x008000,0x008080,0x800000,0x800080,0x808000,0x808080, 0xc0c0c0,0x0000ff,0x00ff00,0x00ffff,0xff0000,0xff00ff,0xffff00,0xffffff }; void beos_lcd_skPenEvent(unsigned int *buffer, int eventType, int stateType, int x, int y) { buffer[0] = x; buffer[1] = y; buffer[2] = 0; // dx buffer[3] = 0; // dy buffer[4] = eventType; // event from pen (DOWN,UP,CLICK,MOVE) buffer[5] = stateType; // state of pen (DOWN,UP,ERROR) buffer[6] = 1; // no of the event buffer[7] = 0; // time of the event (ms) since ts_open } static int beos_lcd_update(struct lcd_device *lcd_dev) { if(lcd_dev == NULL || lcd_dev->priv == NULL) return -1; SkyEyeLCD_Be_Update(lcd_dev->priv); return 0; } static int beos_lcd_open(struct lcd_device *lcd_dev) { unsigned char *fbSkyeyeADDR; if(lcd_dev == NULL || lcd_dev->priv != NULL) return -1; if((fbSkyeyeADDR = skyeye_find_lcd_dma(lcd_dev)) == NULL) { fprintf(stderr, "[BEOS_LCD]: Can't find LCD DMA from address 0x%x\n", lcd_dev->lcd_addr_begin); return -1; } lcd_dev->priv = SkyEyeLCD_Be_new(lcd_dev->width, lcd_dev->width + (int)lcd_dev->lcd_line_offset, lcd_dev->height, lcd_dev->depth, lcd_dev->depth == 4 ? &colors4b[0] : NULL, fbSkyeyeADDR, &Pen_buffer[0], (lcd_lookup_color_func)lcd_dev->lcd_lookup_color, (void*)lcd_dev); return(lcd_dev->priv == NULL ? -1 : 0); } static int beos_lcd_close(struct lcd_device *lcd_dev) { if(lcd_dev == NULL || lcd_dev->priv == NULL) return -1; SkyEyeLCD_Be_delete(lcd_dev->priv); lcd_dev->priv = NULL; lcd_dev->lcd_addr_end = lcd_dev->lcd_addr_begin = 0; return 0; } static int beos_lcd_filter_write(struct lcd_device *lcd_dev, u32 addr, u32 data, size_t count) { int offsetADDR1, offsetADDR2; int w, x1, y1, x2, y2; if(lcd_dev == NULL || lcd_dev->priv == NULL || addr < lcd_dev->lcd_addr_begin || addr > lcd_dev->lcd_addr_end) return 0; offsetADDR1 = (int)(addr - lcd_dev->lcd_addr_begin) * 8 / lcd_dev->depth; offsetADDR2 = offsetADDR1 + (int)count * 8 / lcd_dev->depth; w = lcd_dev->width + (int)lcd_dev->lcd_line_offset; x1 = min(offsetADDR1 % w, w - 1); y1 = min(offsetADDR1 / w, lcd_dev->height - 1); x2 = min(offsetADDR2 % w, w - 1); y2 = min(offsetADDR2 / w, lcd_dev->height - 1); SkyEyeLCD_Be_DMAChanged(lcd_dev->priv, min(x1, x2), min(y1, y2), max(x1, x2), max(y1, y2)); return 0; } int beos_lcd_init(struct lcd_device *lcd_dev) { if (lcd_dev == NULL) return -1; lcd_dev->lcd_open = beos_lcd_open; lcd_dev->lcd_close = beos_lcd_close; lcd_dev->lcd_update = beos_lcd_update; lcd_dev->lcd_filter_read = NULL; lcd_dev->lcd_filter_write = beos_lcd_filter_write; return 0; } skyeye-1.2.5_REL/device/lcd/dev_lcd_s3c44b0x.c0000644000175000001440000002304410607777061017353 0ustar kshusers/* dev_lcd_s3c44b0x.c - skyeye S3C44B0X lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/27/2007 written by Anthony Lee */ #include "armdefs.h" #include "skyeye_device.h" #include "dev_lcd_s3c44b0x.h" #define LCD_S3C44B0X_DEBUG 0 #define PRINT(x...) printf("[LCD_S3C44B0X]: " x) #if LCD_S3C44B0X_DEBUG #define DEBUG(x...) printf("[LCD_S3C44B0X]: " x) #else #define DEBUG(x...) (void)0 #endif static struct device_default_value s3c44b0x_lcd_def[] = { /* name base size interrupt array */ {"s3c44b0", 0x1f00000, 0x48, {0, 0, 0, 0}}, {"s3c44b0x", 0x1f00000, 0x48, {0, 0, 0, 0}}, {NULL}, }; static u32 s3c44b0x_lookup_color_MONO(struct lcd_device *lcd_dev, u32 color) { return (color ? 0xffffff : 0x000000); } static u32 s3c44b0x_lookup_color_G4(struct lcd_device *lcd_dev, u32 color) { struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)lcd_dev->device_priv; u8 gray = (io->lcdbluelut >> ((color & 0x3) << 2)) & 0xf; return (((u32)((gray << 4) | 0xf) << 16) | ((u32)((gray << 4) | 0xf) << 8) | (u32)((gray << 4) | 0xf)); } static u32 s3c44b0x_lookup_color_G16(struct lcd_device *lcd_dev, u32 color) { u8 gray = color & 0xf; return (((u32)((gray << 4) | 0xf) << 16) | ((u32)((gray << 4) | 0xf) << 8) | (u32)((gray << 4) | 0xf)); } static u32 s3c44b0x_lookup_color_C256(struct lcd_device *lcd_dev, u32 color) { struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)lcd_dev->device_priv; u8 c = color & 0xff; u8 r = (io->lcdredlut >> ((c >> 5) << 2)) & 0xf; u8 g = (io->lcdgreenlut >> (((c >> 2) & 0x7) << 2)) & 0xf; u8 b = (io->lcdbluelut >> ((c & 0x3) << 2)) & 0xf; return (((u32)((r << 4) | 0xf) << 16) | ((u32)((g << 4) | 0xf) << 8) | (u32)((b << 4) | 0xf)); } static void lcd_s3c44b0x_changed(struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device*)dev->dev; struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; int DISMOD = (io->lcdcon1 >> 5) & 0x3; int HOZVAL = (io->lcdcon2 >> 10) & 0x7ff; int LINEVAL = io->lcdcon2 & 0x3ff; int MODESEL = (io->lcdsaddr1 >> 27) & 0x3; int OFFSIZE = (io->lcdsaddr3 >> 9) & 0x7ff; int PAGEWIDTH = io->lcdsaddr3 & 0x1ff; int BSWP = (io->lcdsaddr2 >> 29) & 0x1; int depth, width, height; if (state == NULL) return; lcd_dev->state = (void*)state; lcd_dev->lcd_color_right_to_left = 0; lcd_dev->lcd_lookup_color = NULL; lcd_dev->lcd_color_right_to_left = 0; /* In big endian mode, the dma also be big endian per 4 bytes. */ lcd_dev->lcd_dma_swap_word = (BSWP ? (!state->bigendSig) : state->bigendSig); if (MODESEL == 0) { /* monochrome mode */ depth = 1; lcd_dev->lcd_lookup_color = s3c44b0x_lookup_color_MONO; } else if (MODESEL == 1) { /* 4-level gray mode */ depth = 2; lcd_dev->lcd_lookup_color = s3c44b0x_lookup_color_G4; } else if (MODESEL == 2) { /* 16-level gray mode */ depth = 4; lcd_dev->lcd_lookup_color = s3c44b0x_lookup_color_G16; } else if (MODESEL == 3) { /* 8 bits color mode */ depth = 8; lcd_dev->lcd_lookup_color = s3c44b0x_lookup_color_C256; } width = (HOZVAL + 1) * (DISMOD == 1 ? 4 : 8); if (depth == 8) width /= 3; if (DISMOD == 0) height = (LINEVAL + 1) >> 1; /* dual scan */ else height = LINEVAL + 1; /* single scan */ lcd_dev->lcd_close(lcd_dev); if (io->lcdcon1 & 0x1) { /* ENVID = 1 */ lcd_dev->lcd_line_offset = OFFSIZE << (4 - MODESEL); lcd_dev->lcd_addr_end = lcd_dev->lcd_addr_begin = (io->lcdsaddr1 & 0x7ffffff) << 1; lcd_dev->lcd_addr_end += (width + PAGEWIDTH << (4 - MODESEL)) * height * depth / 8 - 1; DEBUG("DISMOD: 0x%x, HOZVAL: 0x%x, LINEVAL: 0x%x, MODESEL: 0x%x, BSWP: %d\n", DISMOD, HOZVAL, LINEVAL, MODESEL, BSWP); DEBUG("OFFSIZE: 0x%x, PAGEWIDTH: 0x%x\n", OFFSIZE, PAGEWIDTH); DEBUG("depth: %d, width: %d, height: %d\n", depth, width, height); DEBUG("lcdsaddr1: 0x%x\n", io->lcdsaddr1); DEBUG("lcd_addr_begin: 0x%x\n", lcd_dev->lcd_addr_begin); if (DISMOD == 0) PRINT(" *** WARNING: Dual scan mode unsupported !!!\n"); lcd_dev->depth = depth; lcd_dev->width = width; lcd_dev->height = height; lcd_dev->device_priv = (void*)io; lcd_dev->lcd_open(lcd_dev); } } static void lcd_s3c44b0x_fini(struct device_desc *dev) { struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)dev->data; if (dev->dev != NULL) free(dev->dev); /* lcd_device from "lcd_setup()", so we free it. */ if (io != NULL) free(io); } static void lcd_s3c44b0x_reset(struct device_desc *dev) { struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)dev->data; io->lcddp12 = 0xa5a5; io->lcddp47 = 0xba5da65; io->lcddp35 = 0xa5a5f; io->lcddp23 = 0xd6b; io->lcddp57 = 0xeb7b5ed; io->lcddp34 = 0x7dbe; io->lcddp45 = 0x7ebdf; io->lcddp67 = 0x7fdfbfe; io->lcddithmode = 0x0; } static void lcd_s3c44b0x_update(struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device*)dev->dev; lcd_dev->lcd_update(lcd_dev); } int lcd_s3c44b0x_read_word(struct device_desc *dev, u32 addr, u32 *data) { struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)dev->data; int offset = addr - dev->base; int ret = ADDR_HIT; *data = 0; switch (offset) { case LCDCON1: *data = io->lcdcon1; break; case LCDCON2: *data = io->lcdcon2; break; case LCDCON3: *data = io->lcdcon3; break; case LCDSADDR1: *data = io->lcdsaddr1; break; case LCDSADDR2: *data = io->lcdsaddr2; break; case LCDSADDR3: *data = io->lcdsaddr3; break; case REDLUT: *data = io->lcdredlut; break; case GREENLUT: *data = io->lcdgreenlut; break; case BLUELUT: *data = io->lcdbluelut; break; case DP1_2: *data = io->lcddp12; break; case DP4_7: *data = io->lcddp47; break; case DP3_5: *data = io->lcddp35; break; case DP2_3: *data = io->lcddp23; break; case DP5_7: *data = io->lcddp57; break; case DP3_4: *data = io->lcddp34; break; case DP4_5: *data = io->lcddp45; break; case DP6_7: *data = io->lcddp67; break; case DITHMODE: *data = io->lcddithmode; break; } return ret; } int lcd_s3c44b0x_write_word(struct device_desc *dev, u32 addr, u32 data) { struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)dev->data; int offset = addr - dev->base; int ret = ADDR_HIT; switch(offset) { case LCDCON1: if (io->lcdcon1 != data) { io->lcdcon1 = data; lcd_s3c44b0x_changed(dev); } break; case LCDCON2: io->lcdcon2 = data; break; case LCDCON3: io->lcdcon3 = data; break; case LCDSADDR1: io->lcdsaddr1 = data; break; case LCDSADDR2: io->lcdsaddr2 = data; break; case LCDSADDR3: io->lcdsaddr3 = data; break; case REDLUT: io->lcdredlut = data; break; case GREENLUT: io->lcdgreenlut = data; break; case BLUELUT: io->lcdbluelut = data; break; case DP1_2: io->lcddp12 = data; break; case DP4_7: io->lcddp47 = data; break; case DP3_5: io->lcddp35 = data; break; case DP2_3: io->lcddp23 = data; break; case DP5_7: io->lcddp57 = data; break; case DP3_4: io->lcddp34 = data; break; case DP4_5: io->lcddp45 = data; break; case DP6_7: io->lcddp67 = data; break; case DITHMODE: io->lcddithmode = data; break; default: ret = ADDR_NOHIT; break; } return ret; } static int lcd_s3c44b0x_filter_read(struct device_desc *dev, u32 addr, u32 *data, size_t count) { struct lcd_device *lcd_dev = (struct lcd_device*)dev->dev; struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)dev->data; if (lcd_dev->lcd_filter_read == NULL) return 0; if ((io->lcdcon1 & 0x1) == 0) return 0; return lcd_dev->lcd_filter_read(lcd_dev, addr, data, count); } static int lcd_s3c44b0x_filter_write(struct device_desc *dev, u32 addr, u32 data, size_t count) { struct lcd_device *lcd_dev = (struct lcd_device*)dev->dev; struct lcd_s3c44b0x_io *io = (struct lcd_s3c44b0x_io*)dev->data; if (lcd_dev->lcd_filter_write == NULL) return 0; if ((io->lcdcon1 & 0x1) == 0) return 0; return lcd_dev->lcd_filter_write(lcd_dev, addr, data, count); } static int lcd_s3c44b0x_setup(struct device_desc *dev) { struct lcd_s3c44b0x_io *io; dev->fini = lcd_s3c44b0x_fini; dev->reset = lcd_s3c44b0x_reset; dev->update = lcd_s3c44b0x_update; dev->filter_read = lcd_s3c44b0x_filter_read; dev->filter_write = lcd_s3c44b0x_filter_write; dev->read_word = lcd_s3c44b0x_read_word; dev->write_word = lcd_s3c44b0x_write_word; if ((io = (struct lcd_s3c44b0x_io*)malloc(sizeof(struct lcd_s3c44b0x_io))) == NULL) return -1; memset(io, 0, sizeof(struct lcd_s3c44b0x_io)); dev->data = (void*)io; lcd_s3c44b0x_reset(dev); /* see if we need to set default values. */ set_device_default(dev, s3c44b0x_lcd_def); return 0; } void lcd_s3c44b0x_init(struct device_module_set *mod_set) { register_device_module("s3c44b0x", mod_set, &lcd_s3c44b0x_setup); } skyeye-1.2.5_REL/device/lcd/dev_lcd_pxa.c0000644000175000001440000001165510552270410016657 0ustar kshusers/* dev_lcd_pxa.c - skyeye PXA25x serial lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/17/2005 initial verion for pxa */ #include "armdefs.h" #include "skyeye_device.h" #include "dev_lcd_pxa.h" static struct device_default_value pxa_lcd_def[] = { /* name base size interrupt array */ {"pxa_lubbock", 0x44000000, 0x220, {0, 0, 0, 0}}, {"pxa_mainstone", 0x44000000, 0x220, {0, 0, 0, 0}}, {NULL}, }; static void pxa_changed (struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_pxa_io *io = (struct lcd_pxa_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; lcd_dev->state = mc->state; //width = (pxa_io.lccr1 & LCCR1_PPL) + 1; //height = ((pxa_io.lccr2 & LCCR2_LPP) + 1)*2; //depth = 1 << ((pxa_io.lccr3 & LCCR3_BPP)>>24); //printf("io->fdadr0:%x, io->fdadr1:%x\n", io->fdadr0, io->fdadr1); lcd_dev->lcd_addr_begin = ((io->fdadr0 + 0x1000) & 0xffff1000); lcd_dev->depth = 1 << ((io->lccr3 & LCCR3_BPP) >> 24); lcd_dev->width = (io->lccr1 & LCCR1_PPL) + 1; lcd_dev->height = ((io->lccr2 & LCCR2_LPP) + 1) * 2; lcd_dev->lcd_open (lcd_dev); } static void lcd_pxa_fini (struct device_desc *dev) { struct lcd_pxa_io *io = (struct lcd_pxa_io *) dev->data; if (!dev->dev) free (dev->dev); if (!io) free (io); } static void lcd_pxa_reset (struct device_desc *dev) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_pxa_io *io = (struct lcd_pxa_io *) dev->data; // lcd_dev->lcd_addr_begin = 0xc0e01000; // lcd_dev->lcd_addr_end = 0xc0e01000; } static void lcd_pxa_update (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_pxa_io *io = (struct lcd_pxa_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; lcd_dev->lcd_update (lcd_dev); } int lcd_pxa_read_word (struct device_desc *dev, u32 addr, u32 * data) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_pxa_io *io = (struct lcd_pxa_io *) dev->data; int offset = (addr - dev->base); int ret = ADDR_HIT; //printf("%s:addr %x, %x\n", __FUNCTION__, addr, MACON); *data = 0; switch (offset) { case LCCR0: *data = io->lccr0; break; case LCCR1: *data = io->lccr1; break; case LCCR2: *data = io->lccr2; break; case LCCR3: *data = io->lccr3; break; case FDADR0: *data = io->fdadr0; break; case FDADR1: *data = io->fdadr1; break; case FSADR0: *data = io->fsadr0; break; case FSADR1: *data = io->fsadr1; break; default: break; } return ret; } int lcd_pxa_write_word (struct device_desc *dev, u32 addr, u32 data) { struct lcd_device *lcd_dev = (struct lcd_device *) dev->dev; struct lcd_pxa_io *io = (struct lcd_pxa_io *) dev->data; int offset = (addr - dev->base); int ret = ADDR_HIT; static int once = 0; //printf("%s:mach:%x\n", __FUNCTION__, dev->mach); switch (offset) { case LCCR0: if ((!(io->lccr0 & LCCR0_ENB)) && (data & LCCR0_ENB)) { if (!once) { once++; pxa_changed (dev); } } io->lccr0 = data; break; case LCCR1: io->lccr1 = data; break; case LCCR2: io->lccr2 = data; break; case LCCR3: io->lccr3 = data; break; case FDADR0: io->fdadr0 = data; break; case FDADR1: io->fdadr1 = data; break; case FSADR0: io->fsadr0 = data; break; case FSADR1: io->fsadr1 = data; break; default: ret = ADDR_NOHIT; break; } return ret; } static int lcd_pxa_setup (struct device_desc *dev) { int i; struct lcd_pxa_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = lcd_pxa_fini; dev->reset = lcd_pxa_reset; dev->update = lcd_pxa_update; dev->read_word = lcd_pxa_read_word; dev->write_word = lcd_pxa_write_word; io = (struct lcd_pxa_io *) malloc (sizeof (struct lcd_pxa_io)); memset (io, 0, sizeof (struct lcd_pxa_io)); if (io == NULL) return 1; dev->data = (void *) io; lcd_pxa_reset (dev); /* see if we need to set default values. * */ set_device_default (dev, pxa_lcd_def); return 0; } void lcd_pxa_init (struct device_module_set *mod_set) { int i; register_device_module ("pxa", mod_set, &lcd_pxa_setup); } skyeye-1.2.5_REL/device/lcd/skyeye_lcd.c0000644000175000001440000001437010607617433016552 0ustar kshusers/* skyeye_lcd.c - skyeye general lcd device file support functions Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/22/2005 initial version * walimis */ #include #include #include #include "armdefs.h" #include "arch/mips/common/mipsdef.h" #include "skyeye_device.h" #include "skyeye_options.h" #include "skyeye.h" #include "skyeye_lcd.h" /* initialize the lcd module set. * If you want to add a new lcd simulation, just add a "lcd_*_init" function to it. * */ static void lcd_init (struct device_module_set *mod_set) { lcd_ep7312_init (mod_set); lcd_pxa_init (mod_set); lcd_s3c2410_init (mod_set); lcd_s3c44b0x_init (mod_set); lcd_au1100_init (mod_set); } static int lcd_setup (struct device_desc *dev, void *option) { struct lcd_device *lcd_dev; struct lcd_option *lcd_opt = (struct lcd_option *) option; int ret = 0; lcd_dev = (struct lcd_device *) malloc (sizeof (struct lcd_device)); if (lcd_dev == NULL) return -1; memset (lcd_dev, 0, sizeof (struct lcd_device)); lcd_dev->mod = lcd_opt->mod; printf ("lcd_mod:%d\n", lcd_dev->mod); switch (lcd_dev->mod) { #ifdef GTK_LCD case LCD_MOD_GTK: ret = gtk_lcd_init(lcd_dev); break; #endif #ifdef WIN32_LCD case LCD_MOD_WIN32: ret = win32_lcd_init(lcd_dev); break; #endif #ifdef BEOS_LCD case LCD_MOD_BEOS: ret = beos_lcd_init(lcd_dev); break; #endif default: ret = -1; break; } if (ret != 0) { free(lcd_dev); lcd_dev = NULL; } dev->dev = (void *) lcd_dev; return ret; } static struct device_module_set lcd_mod_set = { .name = "lcd", .count = 0, .count_max = 0, .init = lcd_init, .initialized = 0, .setup_module = lcd_setup, }; /* used by global device initialize function. * */ void lcd_register () { if (register_device_module_set (&lcd_mod_set)) SKYEYE_ERR ("\"%s\" module set register error!\n", lcd_mod_set.name); } /* help functions. */ unsigned char* skyeye_find_lcd_dma (struct lcd_device *lcd_dev) { unsigned char *dma = NULL; if (lcd_dev == NULL || skyeye_config.arch == NULL || skyeye_config.arch->arch_name == NULL) return NULL; if (strcmp(skyeye_config.arch->arch_name, "arm") == 0) { /* arm */ extern mem_bank_t *bank_ptr(ARMword addr); mem_bank_t *mbp; ARMul_State *state = (ARMul_State*)lcd_dev->state; if(!(state == NULL || (mbp = bank_ptr(lcd_dev->lcd_addr_begin)) == NULL)) { dma = (unsigned char*)(&state->mem.rom[(mbp - state->mem_bank->mem_banks)] [(lcd_dev->lcd_addr_begin - mbp->addr) >> 2]); } } if (strcmp(skyeye_config.arch->arch_name, "mips") == 0) { /* mips */ extern mips_mem_state_t mips_mem; extern mips_mem_bank_t *mips_global_mbp; extern mips_mem_config_t mips_mem_config; int i; unsigned long addr, len; for (i = 0; i < mips_mem_config.bank_num; i++) { addr = mips_mem_config.mem_banks[i].addr; len = mips_mem_config.mem_banks[i].len; if (addr <= lcd_dev->lcd_addr_begin && addr + len > lcd_dev->lcd_addr_begin) break; } if (i != mips_mem_config.bank_num) { dma = (unsigned char*)&(mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks] [(lcd_dev->lcd_addr_begin - mips_global_mbp->addr) >> 2]); } } /* TODO: blackfin, coldfire, etc. */ return dma; } void skyeye_convert_color_from_lcd_dma (struct lcd_device *lcd, int x, int y, int w, int h, void (*func)(u32, void*, void*), void *user_data1, void *user_data2) { const u8 *dma = skyeye_find_lcd_dma(lcd); const u32 *buf; const u16 *buf16; const u8 *buf8; u32 block, color, c; int dx, dy, exw, exb, line_width; int i, k; if (dma == NULL || lcd->lcd_lookup_color == NULL || func == NULL) return; if (!(lcd->depth == 1 || lcd->depth == 2 || lcd->depth == 4 || lcd->depth == 8 || lcd->depth == 16 || lcd->depth == 32)) return; if (lcd->width <= 0 || x < 0 || w <= 0 || x + w > lcd->width) return; if (lcd->height <= 0 || y < 0 || h <= 0 || y + h > lcd->height) return; line_width = (lcd->width + (int)lcd->lcd_line_offset); for (dy = y; dy < y + h; dy++) { exw = (((line_width * dy + x) * lcd->depth) % 32) / 8; exb = ((line_width * dy + x) * lcd->depth) % 8; buf = (const u32*)(dma + 4 * (((line_width * dy + x) * lcd->depth) / 32)); for (dx = x; dx < x + w; buf++) { block = *buf; #ifndef HOST_IS_BIG_ENDIAN if (lcd->lcd_dma_swap_word == 1) { #else if (lcd->lcd_dma_swap_word == 0) { #endif block = (((block & 0xff) << 24) | ((block & 0xff00) << 8) | ((block & 0xff0000) >> 8) | (block >> 24)); } buf8 = (u8*)█ buf16 = (u16*)█ for (i = exw; i < 4 && dx < x + w; exw = 0) { if (lcd->depth < 16) { /* lcd->depth: 1, 2, 4, 8 */ color = (u32)(*(buf8 + (lcd->lcd_color_right_to_left == 0 ? i : 3 - i))); for (k = exb; k < 8 && dx < x + w; k += lcd->depth, exb = 0) { if (lcd->lcd_color_right_to_left == 0) c = ((color >> (8 - (k + lcd->depth))) & ((1 << lcd->depth) - 1)); else c = ((color >> k) & ((1 << lcd->depth) - 1)); (*func)(lcd->lcd_lookup_color(lcd, c), user_data1, user_data2); dx++; } i += 1; } else if (lcd->depth == 16) { if (lcd->lcd_color_right_to_left == 0) color = (u32)(*(buf16 + (i == 0 ? 0 : 1))); else color = (u32)(*(buf16 + (i == 0 ? 1 : 0))); (*func)(lcd->lcd_lookup_color(lcd, color), user_data1, user_data2); dx++; i += 2; } else { /* lcd->depth: 32 */ color = block; (*func)(lcd->lcd_lookup_color(lcd, color), user_data1, user_data2); dx++; break; } } } } } skyeye-1.2.5_REL/device/lcd/skyeye_lcd_win32.c0000644000175000001440000003645210607777061017605 0ustar kshusers/* skyeye_lcd_win32.c - LCD display emulation in a GDI32 window. Copyright (C) 2006 Anthony Lee This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * NOTE: only for little endian. */ #include "skyeye_lcd.h" #undef WORD #include extern unsigned int Pen_buffer[8]; typedef struct SkyEyeLCD { int fWidth; int fHeight; int fDepth; RECT fUpdateRect; BOOL fUpdateAll; HINSTANCE fHinstance; ATOM fAppClass; HDC fScreenHDC; HDC fHDC; HBITMAP fBitmap; HWND fWindow; DWORD fTimestamp; DWORD fInterval; void *fADDR; void *fPrivateADDR; struct lcd_device *fDevice; } SkyEyeLCD; static SkyEyeLCD* SkyEyeLCD_new(struct lcd_device *lcd_dev, unsigned char *addr); static void SkyEyeLCD_delete(SkyEyeLCD *lcd); static void SkyEyeLCD_UpdateFromSkyEye(SkyEyeLCD *lcd); static BOOL SkyEyeLCD_ProcessEvent(SkyEyeLCD *lcd, MSG *msg, LRESULT *reslut); static void SkyEyeLCD_DoUpdate(SkyEyeLCD *lcd, RECT r); #ifndef GET_X_LPARAM #define GET_X_LPARAM(a) ((int)((short)LOWORD(a))) #endif #ifndef GET_Y_LPARAM #define GET_Y_LPARAM(a) ((int)((short)HIWORD(a))) #endif #ifndef MIN #define MIN(a, b) ((a) > (b) ? (b) : (a)) #endif #ifndef MAX #define MAX(a, b) ((a) > (b) ? (a) : (b)) #endif static void skPenEvent(int *buffer, int eventType, int stateType, int x, int y) { buffer[0] = x; buffer[1] = y; buffer[2] = 0; // dx buffer[3] = 0; // dy buffer[4] = eventType; // event from pen (DOWN,UP,CLICK,MOVE) buffer[5] = stateType; // state of pen (DOWN,UP,ERROR) buffer[6] = 1; // no of the event buffer[7] = 0; // time of the event (ms) since ts_open } BOOL SkyEyeLCD_ProcessEvent(SkyEyeLCD *lcd, MSG *msg, LRESULT *result) { BOOL handled = TRUE; RECT r = {0, 0, -1, -1}; if(lcd == NULL || msg == NULL || result == NULL) { handled = FALSE; } else switch(msg->message) { case WM_CLOSE: *result = 0; break; case WM_PAINT: GetUpdateRect(msg->hwnd, &r, FALSE); SkyEyeLCD_DoUpdate(lcd, r); ValidateRect(msg->hwnd, NULL); *result = 0; break; case WM_MOUSEMOVE: if(Pen_buffer[5] == 1) skPenEvent(Pen_buffer, 2, 1, GET_X_LPARAM(msg->lParam), GET_Y_LPARAM(msg->lParam)); break; case WM_LBUTTONDOWN: skPenEvent(Pen_buffer, 0, 1, GET_X_LPARAM(msg->lParam), GET_Y_LPARAM(msg->lParam)); break; case WM_LBUTTONUP: skPenEvent(Pen_buffer, 1, 0, GET_X_LPARAM(msg->lParam), GET_Y_LPARAM(msg->lParam)); break; case WM_KEYDOWN: /* write to stdin */ { BYTE keyState[256]; DWORD keybuffer[3]; DWORD nWrote; if(GetKeyboardState(keyState) == 0) break; UINT scanCode = (UINT)((msg->lParam >> 16) & 0xff); if(ToAscii(msg->wParam, scanCode, keyState, (LPWORD)keybuffer, 0) != 1) break; INPUT_RECORD input; input.EventType = KEY_EVENT; input.Event.KeyEvent.bKeyDown = TRUE; input.Event.KeyEvent.wRepeatCount = msg->lParam & 0xff; input.Event.KeyEvent.wVirtualKeyCode = msg->wParam; input.Event.KeyEvent.wVirtualScanCode = scanCode; input.Event.KeyEvent.uChar.AsciiChar = keybuffer[0]; input.Event.KeyEvent.dwControlKeyState = 0; WriteConsoleInput(GetStdHandle(STD_INPUT_HANDLE), &input, 1, &nWrote); } break; default: handled = FALSE; } return handled; } static LRESULT CALLBACK _lcd_win32_WndProc_(HWND hWnd, UINT umsg, WPARAM wParam, LPARAM lParam) { BOOL handled = FALSE; LRESULT result = 0; MSG winMsg; SkyEyeLCD *lcd = (SkyEyeLCD*)GetWindowLong(hWnd, 0); if(lcd != NULL) { winMsg.hwnd = hWnd; winMsg.message = umsg; winMsg.wParam = wParam; winMsg.lParam = lParam; handled = SkyEyeLCD_ProcessEvent(lcd, &winMsg, &result); } if(!handled) result = DefWindowProc(hWnd, umsg, wParam, lParam); return result; } static int SkyEyeLCD_Initalize(SkyEyeLCD *self) { RECT r; char mode[100]; WNDCLASSEX wcApp; if(self == NULL || (self->fHinstance = (HINSTANCE)GetModuleHandle(NULL)) == NULL) return -1; wcApp.lpszClassName = "skyeye_lcd_win32"; wcApp.hInstance = self->fHinstance; wcApp.lpfnWndProc = _lcd_win32_WndProc_; wcApp.hCursor = LoadCursor(NULL, IDC_HAND); wcApp.hIcon = 0; wcApp.hIconSm = 0; wcApp.lpszMenuName = 0; wcApp.hbrBackground = (HBRUSH)GetStockObject(WHITE_BRUSH); wcApp.style = CS_CLASSDC; wcApp.cbClsExtra = 0; wcApp.cbWndExtra = 4; wcApp.cbSize = sizeof(wcApp); self->fAppClass = RegisterClassEx(&wcApp); self->fScreenHDC = CreateDC("DISPLAY", NULL, NULL, NULL); self->fHDC = CreateCompatibleDC(self->fScreenHDC); self->fBitmap = CreateCompatibleBitmap(self->fScreenHDC, self->fWidth, self->fHeight); SelectObject(self->fHDC, self->fBitmap); Rectangle(self->fHDC, 0, 0, self->fWidth, self->fHeight); snprintf(mode, 100, "If you always see this,"); TextOut(self->fHDC, 10, 10, mode, strlen(mode)); snprintf(mode, 100, "thus means that depth %d unsupported!!!", self->fDepth); TextOut(self->fHDC, 10, 30, mode, strlen(mode)); r.left = 100; r.top = 100; r.right = r.left + self->fWidth; r.bottom = r.top + self->fHeight; AdjustWindowRectEx(&r, WS_CAPTION | WS_MINIMIZEBOX | WS_SYSMENU, FALSE, WS_EX_DLGMODALFRAME); self->fWindow = CreateWindowEx(WS_EX_DLGMODALFRAME, MAKEINTATOM(self->fAppClass), "", WS_CAPTION | WS_MINIMIZEBOX | WS_SYSMENU, r.left, r.top, r.right - r.left + 1, r.bottom - r.top + 1, NULL, NULL, self->fHinstance, NULL); SetWindowLong(self->fWindow, 0, (LONG)self); snprintf(mode, 100, "%dx%dx%d %s", self->fWidth, self->fHeight, self->fDepth, "SkyEye LCD & Touch Screen (Win32)"); SetWindowText(self->fWindow, mode); ShowWindow(self->fWindow, SW_SHOWNORMAL); return 0; } static int SkyEyeLCD_Destroy(SkyEyeLCD *self) { if(self == NULL || self->fHinstance == NULL) return -1; DestroyWindow(self->fWindow); DeleteObject(self->fBitmap); DeleteDC(self->fHDC); DeleteDC(self->fScreenHDC); UnregisterClass(MAKEINTATOM(self->fAppClass), self->fHinstance); return 0; } static void SkyEyeLCD_Cycle(SkyEyeLCD *self) { MSG winMsg; while(PeekMessage(&winMsg, NULL, 0, 0, PM_REMOVE)) DispatchMessage(&winMsg); if(GetTickCount() - self->fTimestamp > self->fInterval) { SkyEyeLCD_UpdateFromSkyEye(self); self->fTimestamp = GetTickCount(); } } static u32 colors1b[2] = { 0x000000,0xffffff }; static u32 colors4b[16] = { 0x000000,0x000080,0x008000,0x008080,0x800000,0x800080,0x808000,0x808080, 0xc0c0c0,0x0000ff,0x00ff00,0x00ffff,0xff0000,0xff00ff,0xffff00,0xffffff }; SkyEyeLCD* SkyEyeLCD_new(struct lcd_device *lcd_dev, unsigned char *addr) { SkyEyeLCD *lcd; size_t sizePrivateADDR = 0; int width = lcd_dev->width; int height = lcd_dev->height; int depth = lcd_dev->depth; if(width <= 0 || height <= 0 || addr == NULL) return NULL; if((lcd = (SkyEyeLCD*)malloc(sizeof(SkyEyeLCD))) == NULL) return NULL; lcd->fWidth = width; lcd->fHeight = height; lcd->fDepth = depth; lcd->fADDR = (void*)addr; lcd->fInterval = 200; lcd->fTimestamp = 0; lcd->fPrivateADDR = NULL; lcd->fUpdateRect.left = 0; lcd->fUpdateRect.top = 0; lcd->fUpdateRect.right = -1; lcd->fUpdateRect.bottom = -1; lcd->fUpdateAll = TRUE; lcd->fDevice = lcd_dev; if(SkyEyeLCD_Initalize(lcd) != 0) { free(lcd); return NULL; } if(lcd->fDevice->lcd_lookup_color != NULL || lcd->fDepth == 8) /* turn to RGB32 */ sizePrivateADDR = (size_t)(lcd->fWidth * lcd->fHeight * 4); else if(lcd->fDepth == 1) sizePrivateADDR = sizeof(BITMAPINFO) + sizeof(RGBQUAD); else if(lcd->fDepth == 4) sizePrivateADDR = sizeof(BITMAPINFO) + 15 * sizeof(RGBQUAD); if(sizePrivateADDR > 0) { if((lcd->fPrivateADDR = malloc(sizePrivateADDR)) != NULL) { bzero(lcd->fPrivateADDR, sizePrivateADDR); if(lcd->fDevice->lcd_lookup_color == NULL && (lcd->fDepth == 4 || lcd->fDepth == 1)) { BITMAPINFO *bitsInfo = (BITMAPINFO*)lcd->fPrivateADDR; int w = lcd->fWidth + (int)lcd->fDevice->lcd_line_offset; memcpy(&bitsInfo->bmiColors[0], lcd->fDepth == 1 ? colors1b : colors4b, lcd->fDepth == 1 ? 8 : 64); bitsInfo->bmiHeader.biSize = sizeof(BITMAPINFOHEADER); bitsInfo->bmiHeader.biWidth = (LONG)w; bitsInfo->bmiHeader.biHeight = -((LONG)lcd->fHeight); bitsInfo->bmiHeader.biPlanes = 1; bitsInfo->bmiHeader.biBitCount = lcd->fDepth; bitsInfo->bmiHeader.biSizeImage = (DWORD)((w * lcd->fHeight * lcd->fDepth + 7) & ~7) / 8; } } } return lcd; } void SkyEyeLCD_delete(SkyEyeLCD *lcd) { if(lcd == NULL) return; SkyEyeLCD_Destroy(lcd); if(lcd->fPrivateADDR) free(lcd->fPrivateADDR); free(lcd); } void SkyEyeLCD_DoUpdate(SkyEyeLCD *lcd, RECT r) { HDC hdc; if(lcd == NULL || lcd->fBitmap == NULL || lcd->fWindow == NULL || (hdc = GetDC(lcd->fWindow)) == NULL) { fprintf(stderr, "%s: lcd == NULL || lcd->fBitmap == NULL || lcd->fWindow == NULL || (hdc = GetDC(lcd->fWindow)) == NULL\n", __FUNCTION__); return; } if(r.right < r.left || r.bottom < r.top) { r.left = 0; r.top = 0; r.right = lcd->fWidth - 1; r.bottom = lcd->fHeight - 1; } BitBlt(hdc, r.left, r.top, r.right - r.left + 1, r.bottom - r.top + 1, lcd->fHDC, r.left, r.top, SRCCOPY); ReleaseDC(lcd->fWindow, hdc); } typedef struct _BITMAPINFO_LARGE { BITMAPINFO bitsInfo; DWORD reserved[3]; // enough to contain 16 bits RGB mask } _BITMAPINFO_LARGE; static void SkyEyeLCD_DMAConvertCallback(u32 c, u32 **buf_addr, void *noused) { *(*buf_addr) = c; *buf_addr = ++(*buf_addr); } void SkyEyeLCD_UpdateFromSkyEye(SkyEyeLCD *lcd) { RECT r; _BITMAPINFO_LARGE _bitsInfo; BITMAPINFO *bitsInfo = (BITMAPINFO*)&_bitsInfo; if(lcd == NULL || lcd->fBitmap == NULL || lcd->fWindow == NULL) return; if(lcd->fUpdateAll == FALSE) { if(lcd->fUpdateRect.left > lcd->fUpdateRect.right || lcd->fUpdateRect.top > lcd->fUpdateRect.bottom) return; r = lcd->fUpdateRect; lcd->fUpdateRect.left = 0; lcd->fUpdateRect.top = 0; lcd->fUpdateRect.right = -1; lcd->fUpdateRect.bottom = -1; } else { r.left = 0; r.top = 0; r.right = lcd->fWidth - 1; r.bottom = lcd->fHeight - 1; } bzero(bitsInfo, sizeof(BITMAPINFO)); bitsInfo->bmiHeader.biSize = sizeof(BITMAPINFOHEADER); bitsInfo->bmiHeader.biWidth = (LONG)lcd->fWidth; bitsInfo->bmiHeader.biHeight = -((LONG)lcd->fHeight); bitsInfo->bmiHeader.biPlanes = 1; if(lcd->fDevice->lcd_lookup_color != NULL) { u32 *tmp = (u32*)(lcd->fPrivateADDR) + r.top * lcd->fWidth; if(lcd->fPrivateADDR == NULL) return; skyeye_convert_color_from_lcd_dma(lcd->fDevice, 0, r.top, lcd->fWidth, r.bottom - r.top + 1, (void (*)(u32, void*, void*))SkyEyeLCD_DMAConvertCallback, &tmp, NULL); bitsInfo->bmiHeader.biBitCount = 32; bitsInfo->bmiHeader.biCompression = BI_RGB; bitsInfo->bmiHeader.biSizeImage = 0; } else switch(lcd->fDepth) { case 1: case 4: if(lcd->fPrivateADDR == NULL) return; break; case 16: bitsInfo->bmiHeader.biBitCount = 16; bitsInfo->bmiHeader.biSizeImage = (DWORD)((lcd->fWidth + (int)lcd->fDevice->lcd_line_offset) * lcd->fHeight * 2); bitsInfo->bmiHeader.biCompression = BI_BITFIELDS; ((DWORD*)(&bitsInfo->bmiColors[0]))[0] = 0xf800; ((DWORD*)(&bitsInfo->bmiColors[0]))[1] = 0x07e0; ((DWORD*)(&bitsInfo->bmiColors[0]))[2] = 0x001f; break; case 24: bitsInfo->bmiHeader.biBitCount = 24; bitsInfo->bmiHeader.biSizeImage = (DWORD)((lcd->fWidth + (int)lcd->fDevice->lcd_line_offset) * lcd->fHeight * 3); break; case 8: /* 3-3-2 */ if(lcd->fPrivateADDR == NULL) return; else { int count = lcd->fWidth * (r.bottom - r.top + 1); const unsigned char *buf = (const unsigned char*)lcd->fADDR + r.top * lcd->fWidth; u32 *tmp = (u32*)(lcd->fPrivateADDR) + r.top * lcd->fWidth; int i; while(count-- > 0) { *tmp++ = (((*buf & 0xe0) | 0x1f) << 16) | // red ((((*buf & 0x1c) << 3) | 0x1f) << 8) | // green (((*buf++ & 0x03) << 6) | 0x3f); // blue if(++i == lcd->fWidth) {buf += lcd->fDevice->lcd_line_offset; i = 0;} } } case 32: if(lcd->fDepth == 32) bitsInfo->bmiHeader.biWidth += (LONG)lcd->fDevice->lcd_line_offset; bitsInfo->bmiHeader.biBitCount = 32; bitsInfo->bmiHeader.biCompression = BI_RGB; bitsInfo->bmiHeader.biSizeImage = 0; break; default: return; } StretchDIBits(lcd->fHDC, r.left, r.top, r.right - r.left + 1, r.bottom - r.top + 1, r.left, r.top, r.right - r.left + 1, r.bottom - r.top + 1, (lcd->fDevice->lcd_lookup_color != NULL || lcd->fDepth == 8 ? lcd->fPrivateADDR : lcd->fADDR), (lcd->fDevice->lcd_lookup_color == NULL && (lcd->fDepth == 1 || lcd->fDepth == 4) ? (BITMAPINFO*)lcd->fPrivateADDR : bitsInfo), DIB_RGB_COLORS, SRCCOPY); SkyEyeLCD_DoUpdate(lcd, r); } static int win32_lcd_update(struct lcd_device *lcd_dev) { if(lcd_dev == NULL || lcd_dev->priv == NULL) return -1; SkyEyeLCD_Cycle((SkyEyeLCD*)(lcd_dev->priv)); return 0; } static int win32_lcd_open(struct lcd_device *lcd_dev) { unsigned char *fbSkyeyeADDR; if(lcd_dev == NULL || lcd_dev->priv != NULL) return -1; if((fbSkyeyeADDR = skyeye_find_lcd_dma(lcd_dev)) == NULL) { fprintf(stderr, "[WIN32_LCD]: Can't find LCD DMA from address 0x%x\n", lcd_dev->lcd_addr_begin); return -1; } if((lcd_dev->priv = (void*)SkyEyeLCD_new(lcd_dev, fbSkyeyeADDR)) == NULL) return -1; return 0; } static int win32_lcd_close(struct lcd_device *lcd_dev) { if(lcd_dev == NULL || lcd_dev->priv == NULL) return -1; SkyEyeLCD_delete((SkyEyeLCD*)(lcd_dev->priv)); lcd_dev->priv = NULL; lcd_dev->lcd_addr_end = lcd_dev->lcd_addr_begin = 0; return 0; } static int win32_lcd_filter_write(struct lcd_device *lcd_dev, u32 addr, u32 data, size_t count) { int offsetADDR1, offsetADDR2; int w, x1, y1, x2, y2; SkyEyeLCD *lcd = lcd_dev ? (SkyEyeLCD*)(lcd_dev->priv) : NULL; if (lcd == NULL || addr < lcd_dev->lcd_addr_begin || addr > lcd_dev->lcd_addr_end) return 0; offsetADDR1 = (int)(addr - lcd_dev->lcd_addr_begin) * 8 / lcd->fDepth; offsetADDR2 = offsetADDR1 + (int)count * 8 / lcd->fDepth; w = lcd->fWidth + (int)lcd->fDevice->lcd_line_offset; x1 = MIN(offsetADDR1 % w, w - 1); y1 = MIN(offsetADDR1 / w, lcd->fHeight - 1); x2 = MIN(offsetADDR2 % w, w - 1); y2 = MIN(offsetADDR2 / w, lcd->fHeight - 1); if(lcd->fUpdateRect.left > lcd->fUpdateRect.right || lcd->fUpdateRect.top > lcd->fUpdateRect.bottom) { lcd->fUpdateRect.left = MIN(x1, x2); lcd->fUpdateRect.right = MAX(x1, x2); lcd->fUpdateRect.top = MIN(y1, y2); lcd->fUpdateRect.bottom = MAX(y1, y2); } else { lcd->fUpdateRect.left = MIN(MIN(lcd->fUpdateRect.left, x1), x2); lcd->fUpdateRect.top = MIN(MIN(lcd->fUpdateRect.top, y1), y2); lcd->fUpdateRect.right = MAX(MAX(lcd->fUpdateRect.right, x1), x2); lcd->fUpdateRect.bottom = MAX(MAX(lcd->fUpdateRect.bottom, y1), y2); } lcd->fUpdateAll = FALSE; return 0; } int win32_lcd_init(struct lcd_device *lcd_dev) { if (lcd_dev == NULL) return -1; lcd_dev->lcd_open = win32_lcd_open; lcd_dev->lcd_close = win32_lcd_close; lcd_dev->lcd_update = win32_lcd_update; lcd_dev->lcd_filter_read = NULL; lcd_dev->lcd_filter_write = win32_lcd_filter_write; return 0; } skyeye-1.2.5_REL/device/lcd/dev_lcd_ep7312.h0000644000175000001440000000302310541455476017022 0ustar kshusers/* dev_lcd_ep7312.h - skyeye EP7312 lcd controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/23/2005 initial version * walimis * */ #ifndef __DEV_LCD_EP7312_H_ #define __DEV_LCD_EP7312_H_ #define VBUFSIZ 0x00001fff /* Video buffer size (bits/128-1) */ #define LINELEN 0x0007e000 /* Line length (pix/16-1) */ #define LINELEN_SHIFT 13 #define PIXPSC 0x01f80000 /* Pixel prescale (526628/pixels-1) */ #define PIXPSC_SHIFT 19 #define ACPSC 0x3e000000 /* AC prescale */ #define ACPSC_SHIFT 25 #define GSEN 0x40000000 /* Grayscale enable (0: monochrome) */ #define GSMD 0x80000000 /* Grayscale mode (0: 2 bit, 1: 4 bit) */ typedef struct lcd_ep7312_io { u32 lcdcon; } lcd_ep7312_io_t; #endif //_DEV_LCD_EP7312_H_ skyeye-1.2.5_REL/device/sound/0000755000175000001440000000000011023514411014615 5ustar kshusersskyeye-1.2.5_REL/device/sound/dev_sound_s3c44b0x.c0000644000175000001440000001035410602016004020301 0ustar kshusers/* dev_sound_s3c44b0x.c - SAMSUNG's S3C44B0X sound simulation for skyeye Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/25/2007 Written by Anthony Lee */ #include "arch/arm/common/armdefs.h" #include "arch/arm/mach/s3c44b0.h" #include "skyeye_config.h" #include "skyeye_sound.h" extern ARMhword *s3c44b0x_iisfifo_tx; /* defined in "skyeye_mach_s3c44b0x.c" */ struct snd_s3c44b0x_io { int count; }; static struct device_default_value skyeye_snd_def[] = { /* name base size interrupt array */ {"s3c44b0", IISFIF_RX_CONTROL, 0x08, {0, 0, 0, 0}}, {"s3c44b0x", IISFIF_RX_CONTROL, 0x08, {0, 0, 0, 0}}, {NULL}, }; static void snd_s3c44b0x_fini(struct device_desc *dev) { struct sound_device *snd_dev = (struct sound_device*)dev->dev; struct snd_s3c44b0x_io *io = (struct snd_s3c44b0x_io*)dev->data; if (snd_dev->sound_close != NULL) (*(snd_dev->sound_close))(snd_dev); free(dev->dev); free(io); } static void snd_s3c44b0x_reset(struct device_desc *dev) { struct sound_device *snd_dev = (struct sound_device*)dev->dev; struct snd_s3c44b0x_io *io = (struct snd_s3c44b0x_io*)dev->data; memset(io, 0, sizeof(struct snd_s3c44b0x_io)); if (snd_dev->sound_close != NULL) (*(snd_dev->sound_close))(snd_dev); if (snd_dev->sound_open != NULL) (*(snd_dev->sound_open))(snd_dev); } static void snd_s3c44b0x_update(struct device_desc *dev) { struct sound_device *snd_dev = (struct sound_device*)dev->dev; if (snd_dev->sound_update != NULL) (*(snd_dev->sound_update))(snd_dev); } static int snd_s3c44b0x_read_word(struct device_desc *dev, uint32_t addr, uint32_t *data) { struct sound_device *snd_dev = (struct sound_device*)dev->dev; struct snd_s3c44b0x_io *io = (struct snd_s3c44b0x_io*)dev->data; uint32_t offset = addr - dev->base; uint16_t tmp; switch (offset) { case 0: /* IISFIF_RX_CONTROL */ *data = 0x1400; if (snd_dev->sound_read == NULL) break; if ((*(snd_dev->sound_read))(snd_dev, &tmp, 2) <= 0) break; *data = (0x1500 | tmp); break; case 4: /* IISFIF_TX_CONTROL */ *data = (0xa20 | io->count); break; default: break; } return ADDR_HIT; } static int snd_s3c44b0x_write_word(struct device_desc *dev, uint32_t addr, uint32_t data) { struct sound_device *snd_dev = (struct sound_device*)dev->dev; struct snd_s3c44b0x_io *io = (struct snd_s3c44b0x_io*)dev->data; int count, ret = ADDR_HIT; uint32_t offset = addr - dev->base; switch (offset) { case 4: /* IISFIF_TX_CONTROL */ io->count = 0; if (snd_dev->sound_write == NULL) break; if ((data & 0xa10) == 0xa10 && s3c44b0x_iisfifo_tx != NULL) { if ((count = (data & 0xf)) == 0) break; if (count > 8) count = 8; count = (*(snd_dev->sound_write))(snd_dev, (void*)s3c44b0x_iisfifo_tx, count * 2); if (count <= 0) break; count /= 2; io->count = count; } break; default: ret = ADDR_NOHIT; break; } return ret; } static int snd_s3c44b0x_setup(struct device_desc *dev) { struct snd_s3c44b0x_io *io; dev->fini = snd_s3c44b0x_fini; dev->reset = snd_s3c44b0x_reset; dev->update = snd_s3c44b0x_update; dev->read_word = snd_s3c44b0x_read_word; dev->write_word = snd_s3c44b0x_write_word; io = (struct snd_s3c44b0x_io*)malloc(sizeof(struct snd_s3c44b0x_io)); if (io == NULL) return -1; dev->data = (void*)io; snd_s3c44b0x_reset(dev); /* see if we need to set default values. */ set_device_default(dev, skyeye_snd_def); return 0; } void sound_s3c44b0x_init(struct device_module_set *mod_set) { register_device_module("s3c44b0x", mod_set, &snd_s3c44b0x_setup); } skyeye-1.2.5_REL/device/sound/skyeye_sound_pcm.c0000644000175000001440000001273510602016004020346 0ustar kshusers/* skyeye_sound_pcm.c - pcm module of sound simulation for skyeye Copyright (C) 2007 Anthony Lee This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/25/2007 Written by Anthony Lee */ /* * WARNING: uncompleted yet !!! */ #include "skyeye_sound.h" #if (defined(__MINGW32__) || defined(__CYGWIN__)) #undef WORD #include struct pcm_sound_t { CRITICAL_SECTION locker; HWAVEIN handle_in; HWAVEOUT handle_out; WAVEHDR header; unsigned char *buf; DWORD buf_playing_cnt; DWORD buf_pending_cnt; DWORD buf_size; }; static CALLBACK void pcm_sound_callback(HWAVEOUT hwo, UINT uMsg, DWORD dwInstance, DWORD dwParma1, DWORD dwParam2) { struct pcm_sound_t *snd = (struct pcm_sound_t*)dwInstance; if (uMsg == WOM_DONE && snd != NULL) { EnterCriticalSection(&snd->locker); if (snd->buf_pending_cnt > 0) { memmove(snd->buf, snd->buf + snd->buf_playing_cnt, snd->buf_pending_cnt); snd->header.dwBufferLength = snd->buf_playing_cnt = snd->buf_pending_cnt; snd->buf_pending_cnt = 0; LeaveCriticalSection(&snd->locker); waveOutWrite(snd->handle_out, &snd->header, sizeof(WAVEHDR)); return; } else { snd->buf_playing_cnt = 0; } LeaveCriticalSection(&snd->locker); } } int pcm_sound_open(struct sound_device *snd_dev) { WAVEFORMATEX wfx; struct pcm_sound_t *snd; if (snd_dev->priv != NULL || waveOutGetNumDevs() == 0 || snd_dev->channels <= 0 || snd_dev->bits_per_sample <= 0 || snd_dev->bits_per_sample % 8 != 0 || snd_dev->samples_per_sec <= 0) return -1; snd = (struct pcm_sound_t*)malloc(sizeof(struct pcm_sound_t)); if (snd == NULL) return -1; memset(snd, 0, sizeof(struct pcm_sound_t)); wfx.wFormatTag = WAVE_FORMAT_PCM; wfx.nChannels = snd_dev->channels; wfx.wBitsPerSample = snd_dev->bits_per_sample; wfx.nBlockAlign = ((wfx.nChannels * wfx.wBitsPerSample) >> 3); wfx.nSamplesPerSec = snd_dev->samples_per_sec; wfx.nAvgBytesPerSec = wfx.nSamplesPerSec * wfx.nBlockAlign; if (waveOutOpen(&snd->handle_out, WAVE_MAPPER, &wfx, (DWORD_PTR)pcm_sound_callback, (DWORD_PTR)snd, CALLBACK_FUNCTION) != MMSYSERR_NOERROR) { printf("%s: waveOutOpen() failed.\n", __FUNCTION__); snd->handle_out = NULL; goto error; } snd->buf_size = 0x100000; if ((snd->buf = (unsigned char*)malloc((size_t)snd->buf_size)) == NULL) { printf("%s: allocate memory failed.\n", __FUNCTION__); goto error; } snd->buf_playing_cnt = 0; snd->buf_pending_cnt = 0; snd->header.lpData = snd->buf; snd->header.dwBufferLength = 0; snd->header.dwFlags = 0; snd->header.dwLoops = 0; if (waveOutPrepareHeader(snd->handle_out, &snd->header, sizeof(WAVEHDR)) != MMSYSERR_NOERROR) { printf("%s: waveOutPrepareHeader() failed.\n", __FUNCTION__); goto error; } InitializeCriticalSection(&snd->locker); goto exit; error: if (snd->handle_out != NULL) waveOutClose(snd->handle_out); if (snd->buf != NULL) free(snd->buf); free(snd); return -1; exit: snd_dev->priv = (void*)snd; return 0; } int pcm_sound_close(struct sound_device *snd_dev) { struct pcm_sound_t *snd = (struct pcm_sound_t*)snd_dev->priv; if (snd == NULL) return -1; waveOutReset(snd->handle_out); waveOutUnprepareHeader(snd->handle_out, &snd->header, sizeof(WAVEHDR)); waveOutClose(snd->handle_out); free(snd->buf); DeleteCriticalSection(&snd->locker); free(snd); snd_dev->priv = NULL; return 0; } int pcm_sound_update(struct sound_device *snd_dev) { /* TODO */ return 0; } int pcm_sound_read(struct sound_device *snd_dev, void *buf, size_t count) { /* TODO */ return -1; } int pcm_sound_write(struct sound_device *snd_dev, void *buf, size_t count) { struct pcm_sound_t *snd = (struct pcm_sound_t*)snd_dev->priv; if (snd == NULL || buf == NULL || count <= 0) return -1; EnterCriticalSection(&snd->locker); count = (size_t)min(snd->buf_size - snd->buf_playing_cnt - snd->buf_pending_cnt, (int)count); if (count > 0) { unsigned char *tmp = snd->buf + snd->buf_playing_cnt + snd->buf_pending_cnt; memcpy(tmp, buf, count); snd->buf_pending_cnt += ((int)count); if (snd->buf_playing_cnt == 0) { snd->header.dwBufferLength = snd->buf_playing_cnt = snd->buf_pending_cnt; snd->buf_pending_cnt = 0; LeaveCriticalSection(&snd->locker); waveOutWrite(snd->handle_out, &snd->header, sizeof(WAVEHDR)); return ((int)count); } } LeaveCriticalSection(&snd->locker); return ((int)count); } #else /* !(defined(__MINGW32__) || defined(__CYGWIN__)) */ /* TODO */ int pcm_sound_open(struct sound_device *snd_dev) { return -1; } int pcm_sound_close(struct sound_device *snd_dev) { return 0; } int pcm_sound_update(struct sound_device *snd_dev) { return 0; } int pcm_sound_read(struct sound_device *snd_dev, void *buf, size_t count) { return -1; } int pcm_sound_write(struct sound_device *snd_dev, void *buf, size_t count) { return -1; } #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ skyeye-1.2.5_REL/device/sound/skyeye_sound.c0000644000175000001440000000475710604002410017512 0ustar kshusers/* skyeye_sound.c - skyeye sound device support functions Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/25/2007 initial version by Anthony Lee */ #include "skyeye_device.h" #include "skyeye_options.h" #include "skyeye.h" #include "skyeye_sound.h" /* * sound_init() : Initialize the sound module set. * If you want to add a new sound simulation, * just add a "sound_*_init" function to it. */ static void sound_init(struct device_module_set *mod_set) { sound_s3c44b0x_init(mod_set); } static int sound_setup(struct device_desc *dev, void *option) { struct sound_device *snd_dev; struct sound_option *snd_opt = (struct sound_option*)option; int ret = 0; snd_dev = (struct sound_device*)malloc(sizeof(struct sound_device)); if (snd_dev == NULL) return -1; memset(snd_dev, 0, sizeof(struct sound_device)); snd_dev->mod = snd_opt->mod; snd_dev->channels = snd_opt->channels; snd_dev->bits_per_sample = snd_opt->bits_per_sample; snd_dev->samples_per_sec = snd_opt->samples_per_sec; switch (snd_opt->mod) { case SOUND_SIM_PCM: snd_dev->sound_open = pcm_sound_open; snd_dev->sound_close = pcm_sound_close; snd_dev->sound_update = pcm_sound_update; snd_dev->sound_read = pcm_sound_read; snd_dev->sound_write = pcm_sound_write; break; default: break; } dev->dev = (void*)snd_dev; return ret; } static struct device_module_set snd_mod_set = { .name = "sound", .count = 0, .count_max = 0, .init = sound_init, .initialized = 0, .setup_module = sound_setup, }; /* * sound_register() : Used by global device initialize function. */ void sound_register(void) { if (register_device_module_set(&snd_mod_set)) { SKYEYE_ERR("\"%s\" module set register error!\n", snd_mod_set.name); } } /* help functions. */ skyeye-1.2.5_REL/device/sound/skyeye_sound.h0000644000175000001440000000375410602016004017515 0ustar kshusers/* skyeye_sound.h - skyeye sound device support functions Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/25/2007 initial version by Anthony Lee */ #ifndef __SKYEYE_SOUND_H_ #define __SKYEYE_SOUND_H_ #include "skyeye_device.h" /* sound simulation type */ #define SOUND_SIM_PCM 1 /* pcm data write to device directly */ struct sound_device { int mod; int channels; int bits_per_sample; int samples_per_sec; /* private data. */ void *priv; int (*sound_open)(struct sound_device *snd_dev); int (*sound_close)(struct sound_device *snd_dev); int (*sound_update)(struct sound_device *snd_dev); int (*sound_read)(struct sound_device *snd_dev, void *buf, size_t count); int (*sound_write)(struct sound_device *snd_dev, void *buf, size_t count); }; /* sound controller initialize functions */ extern void sound_s3c44b0x_init(struct device_module_set *mod_set); /* modules */ int pcm_sound_open(struct sound_device *snd_dev); int pcm_sound_close(struct sound_device *snd_dev); int pcm_sound_update(struct sound_device *snd_dev); int pcm_sound_read(struct sound_device *snd_dev, void *buf, size_t count); int pcm_sound_write(struct sound_device *snd_dev, void *buf, size_t count); /* help function*/ #endif /* __SKYEYE_SOUND_H_ */ skyeye-1.2.5_REL/device/skyeye_device.h0000644000175000001440000001236610607777061016521 0ustar kshusers/* skyeye_device.h - definitions of the device framework for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 05/04/2004 initial version * desgin a generic device framework for skyeye to providing good exetension of device simulations * * walimis * */ /* Important notice: * We just want to design an "independent" device framework that hasn't any * relationships with any specific device simulation. So don't put any specific * device simulation data here. * */ #ifndef __SKYEYE_DEVICE_H_ #define __SKYEYE_DEVICE_H_ #include "skyeye.h" #define MAX_STR_NAME 32 #define MAX_INTERRUPT 4 struct device_interrupt { /* interrupts of device. * some devices may have multi interrupts, so we define a array of interrupts. * The meanings of every interrupt must be exactly known by device simulations.*/ u32 interrupts[MAX_INTERRUPT]; /* set interrupt bit. * */ void (*set_interrupt) (u32 interrupt); /* see if interrupt bit is pending * return value: * 1: pending. * 0: not pending * */ int (*pending_interrupt) (u32 interrupt); /* update interrupt state. * */ void (*update_interrupt) (void *mach); }; struct device_mem_op { int (*read_byte) (void *mach, u32 addr, u32 * data); int (*write_byte) (void *mach, u32 addr, u32 data); }; /* many devices have default value. * */ struct device_default_value { char *name; /*I/O or memory base address and size */ u32 base; u32 size; u32 interrupts[MAX_INTERRUPT]; }; typedef struct device_desc { /* device type name. * if inexistance, can be gotten from "mach name" * e.g. ep7312, at91. * */ char type[MAX_STR_NAME]; /* device instance name. * The same type of device may have two or more instances, but they * have different name. "name" can identify different instances. * e.g. the "s3c4510b" uart has two instances: uart1 and uart2. * */ char name[MAX_STR_NAME]; /*I/O or memory base address and size */ u32 base; u32 size; /* interrupt of device. * */ struct device_interrupt intr; /* mem operation * */ struct device_mem_op mem_op; void (*fini) (struct device_desc * dev); /*finish routine */ void (*reset) (struct device_desc * dev); /*reset device. */ void (*update) (struct device_desc * dev); /*called by io_do_cycle */ int (*filter_read) (struct device_desc *dev, u32 addr, u32 *data, size_t count); int (*filter_write) (struct device_desc *dev, u32 addr, u32 data, size_t count); int (*read_byte) (struct device_desc * dev, u32 addr, u8 * result); int (*read_halfword) (struct device_desc * dev, u32 addr, u16 * result); int (*read_word) (struct device_desc * dev, u32 addr, u32 * result); int (*write_byte) (struct device_desc * dev, u32 addr, u8 data); int (*write_halfword) (struct device_desc * dev, u32 addr, u16 data); int (*write_word) (struct device_desc * dev, u32 addr, u32 data); /* refer the "mach" that the device belongs to. * */ void *mach; /* specific common data for a type of device * */ void *dev; /* device specific data * usually be an "io" struct. * */ void *data; } device_desc_t; struct device_module { char *type_name; int (*setup) (struct device_desc * dev); }; struct device_module_set { char *name; /*module set name. e.g. uart, net, lcd */ struct device_module **mod; /*pointer of array of device_module */ int count; /*current count of device_module */ int count_max; /*max count of device_module */ /* initialize this module set. */ void (*init) (struct device_module_set * mod_set); int initialized; /* * setup "device module" data * */ int (*setup_module) (struct device_desc * dev, void *option); }; extern int register_device_module (char *name, struct device_module_set *mod_set, int (*setup) (struct device_desc * dev)); extern int register_device_module_set (struct device_module_set *mod_set); extern void initialize_all_devices (); extern void set_device_default (struct device_desc *dev, struct device_default_value *def); /* register funtions of all kinds of device module set. * */ //extern void uart_register(); //extern void timer_register(); extern void net_register(); extern void lcd_register(); extern void flash_register(); extern void touchscreen_register(); extern void sound_register(); #define ADDR_NOHIT 0 /* address no hit */ #define ADDR_HIT 1 /* address hit */ #define ADDR_HITNOAVAIL 2 /* address hit but no available */ #define ACTION_EQUAL 0 #define ACTION_AND 1 #define ACTION_AND_NOT 2 #define ACTION_OR 3 #define ACTION_OR_NOT 4 #endif /*__SKYEYE_DEVICE_H_ */ skyeye-1.2.5_REL/device/nandflash/0000755000175000001440000000000011023514411015423 5ustar kshusersskyeye-1.2.5_REL/device/nandflash/dev_nandflash_s3c2410.h0000644000175000001440000000333410673446633021476 0ustar kshusers/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author gbf0871 */ #ifndef __DEV_NANDFLASH_S3C2410_H_ #define __DEV_NANDFLASH_S3C2410_H_ #define S3C2410_NFCONF_EN (1<<15) #define S3C2410_NFCONF_512BYTE (1<<14) #define S3C2410_NFCONF_4STEP (1<<13) #define S3C2410_NFCONF_INITECC (1<<12) #define S3C2410_NFCONF_nFCE (1<<11) #define S3C2410_NFCONF_TACLS(x) ((x)<<8) #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) #define NFCONF 0x4E000000 /* NAND flash configuration */ #define NFCMD 0x4E000004 /* NAND flash command set register */ #define NFADDR 0x4E000008 /*NAND flash address set register*/ #define NFDATA 0x4E00000C /* NAND flash data register */ #define NFSTAT 0x4E000010 /*NAND flash operation status*/ #define NFECC1 0x4E000014 /* NAND flash ECC (Error Correction Code) register */ #define NFECC2 0x4E000015 #define NFECC3 0x4E000016 typedef struct nandflash_s3c2410_io { u32 nfconf; u32 nfcmd; u32 nfaddr; u32 nfdata; u32 nfstat; u32 nfecc; } nandflash_s3c2410_io_t; #endif //_DEV_NANDFLASH_S3C2410_H_ skyeye-1.2.5_REL/device/nandflash/dev_nandflash_s3c2410.c0000644000175000001440000001366510673446633021501 0ustar kshusers/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author gbf0871 */ #include "armdefs.h" #include "skyeye_device.h" #include "skyeye_nandflash.h" #include "dev_nandflash_s3c2410.h" #include "nandflash_smallblock.h" static void nandflash_s3c2410_fini (struct device_desc *dev) { struct nandflash_device *nandflashdev=(struct nandflash_device*)dev->dev; struct nandflash_s3c2410_io *io = (struct nandflash_s3c2410_io *) dev->data; //nandflash_sb_uninstall(nandflashdev); nandflashdev->uinstall(nandflashdev); if (!dev->dev) free (dev->dev); if (!io) free (io); } static void nandflash_s3c2410_reset (struct device_desc *dev) { struct nandflash_device *nandflash_dev = (struct nandflash_device *) dev->dev; struct nandflash_s3c2410_io *io = (struct nandflash_s3c2410_io *) dev->data; //struct nandflash_sb_status *nf = (struct nandflash_sb_status*)nandflash_dev->priv; io->nfaddr=0; io->nfcmd=0; io->nfconf=0; io->nfdata=0; io->nfecc=0; io->nfstat=0; nandflash_dev->setCE(nandflash_dev,NF_HIGH); //nandflash_sb_setCE(NF_HIGH,nf); } static void nandflash_s3c2410_update (struct device_desc *dev) { struct nandflash_device *nandflash_dev = (struct nandflash_device *) dev->dev; struct nandflash_s3c2410_io *io = (struct nandflash_s3c2410_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; } int iomach(u32 addr) { if((addr>=NFCONF)&&(addr<=NFECC3)) return 1; else return 0; } int nandflash_s3c2410_read_word (struct device_desc *dev, u32 addr, u32 * data) { struct nandflash_device *nandflash_dev = (struct nandflash_device *) dev->dev; struct nandflash_s3c2410_io *io = (struct nandflash_s3c2410_io *) dev->data; //struct nandflash_sb_status *nf = (struct nandflash_sb_status*)nandflash_dev->priv; int ret = ADDR_HIT; int ctrenable=io->nfconf&S3C2410_NFCONF_EN; //if (iomach(addr)) // NANDFLASH_DBG("%s:addr %x\n", __FUNCTION__, addr); *data = 0; switch (addr) { case NFCONF: *data = io->nfconf; break; case NFCMD: *data = io->nfcmd; break; case NFADDR: *data = io->nfaddr; break; case NFDATA: if(ctrenable) //*data=(u32)nandflash_sb_readdata(nf); *data=(u32)nandflash_dev->readdata(nandflash_dev); break; case NFSTAT: if(ctrenable) *data=nandflash_dev->readRB(nandflash_dev); //*data = nandflash_sb_readRB(nf); break; case NFECC1: *data = 0xFF; break; case NFECC2: *data = 0xFF; break; case NFECC3: *data = 0xFF; break; default: ret= ADDR_NOHIT; break; } //if (iomach(addr)) // NANDFLASH_DBG("%s:readdata: %x\n", __FUNCTION__, *data); return ret; } int nandflash_s3c2410_read_byte(struct device_desc *dev, u32 addr, u8 * data) { nandflash_s3c2410_read_word(dev,addr,(u32*)data); } int nandflash_s3c2410_write_word (struct device_desc *dev, u32 addr, u32 data) { struct nandflash_device *nandflash_dev = (struct nandflash_device *) dev->dev; struct nandflash_s3c2410_io *io = (struct nandflash_s3c2410_io *) dev->data; //struct nandflash_sb_status *nf = (struct nandflash_sb_status*)nandflash_dev->priv; int ret = ADDR_HIT; int ctrenable=io->nfconf&S3C2410_NFCONF_EN; //if (iomach(addr)) switch (addr) { case NFCONF: //NANDFLASH_DBG("%s:mach:%x,data:%x\n", __FUNCTION__, addr,data); io->nfconf=data; ctrenable=io->nfconf&S3C2410_NFCONF_EN; if ((data&S3C2410_NFCONF_nFCE)&&(ctrenable)) { //NANDFLASH_DBG("%d\n",data&S3C2410_NFCONF_nFCE); //nandflash_sb_setCE(NF_HIGH,nf); nandflash_dev->setCE(nandflash_dev,NF_HIGH); } else { //nandflash_sb_setCE(NF_LOW,nf); nandflash_dev->setCE(nandflash_dev,NF_LOW); } break; case NFCMD: if(ctrenable) { //NANDFLASH_DBG("%s:mach:%x,data:%x\n", __FUNCTION__, addr,data); //nandflash_sb_sendcmd((u8)data,nf); nandflash_dev->sendcmd(nandflash_dev,(u8)data); } break; case NFADDR: if(ctrenable) nandflash_dev->sendaddr(nandflash_dev,(u8)data); //nandflash_sb_sendaddr((u8)data,nf); break; case NFDATA: if(ctrenable) nandflash_dev->senddata(nandflash_dev,(u8)data); //nandflash_sb_senddata((u8)data,nf); break; case NFSTAT: break; case NFECC1: break; case NFECC2: break; case NFECC3: break; default: ret = ADDR_NOHIT; break; } return ret; } int nandflash_s3c2410_write_byte (struct device_desc *dev, u32 addr, u8 data) { nandflash_s3c2410_write_word(dev,addr,(u32)data); } static int nandflash_s3c2410_setup (struct device_desc *dev) { int i; struct nandflash_s3c2410_io *io; struct device_interrupt *intr = &dev->intr; struct nandflash_device *nandflashdev=(struct nandflash_device*)dev->dev; dev->fini = nandflash_s3c2410_fini; dev->reset = nandflash_s3c2410_reset; dev->update = nandflash_s3c2410_update; dev->read_word = nandflash_s3c2410_read_word; dev->write_word = nandflash_s3c2410_write_word; dev->read_byte= nandflash_s3c2410_read_byte; dev->write_byte= nandflash_s3c2410_write_byte; //nandflash_sb_setup(nandflashdev); if (nandflash_module_setup(nandflashdev,dev->name)==-1) return 1; nandflashdev->install(nandflashdev); io = (struct nandflash_s3c2410_io *) malloc (sizeof (struct nandflash_s3c2410_io)); if (io == NULL) return 1; memset (io, 0, sizeof (struct nandflash_s3c2410_io)); dev->data = (void *) io; nandflash_s3c2410_reset (dev); return 0; } void nandflash_s3c2410_init (struct device_module_set *mod_set) { int i; register_device_module ("s3c2410x", mod_set, &nandflash_s3c2410_setup); } skyeye-1.2.5_REL/device/nandflash/nandflash_smallblock.h0000644000175000001440000000363710704350434021756 0ustar kshusers/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author gbf0871 */ #ifndef _NANDFLASH_SMALLBLOCK_H_ #define _NANDFLASH_SMALLBLOCK_H_ #include #include "skyeye_nandflash.h" #ifdef __MINGW32__ #define FILE_FLAG (O_RDWR | O_CREAT | O_BINARY) #else #define FILE_FLAG (O_RDWR | O_CREAT) #endif #if (defined(__MINGW32__) || defined(__BEOS__)) #define POSIX_SHARE_MEMORY_BROKEN #endif //nandflash cmd status typedef enum { NF_NOSTATUS, NF_addr_1st, NF_addr_2nd, NF_addr_3rd, NF_addr_4th, NF_addr_finish, NF_status, NF_readID_1st, NF_readID_2nd, NF_readID_3rd, NF_readID_4th, NF_readID_addr } cmdstatustype; typedef enum { NF_CMD, NF_ADDR, NF_DATAREAD, NF_DATAWRITE, NF_STATUSREAD, NF_IDREAD, NF_NONE } iostatustype; struct nandflash_sb_status { u8 IOPIN; u8 status; NFCE_STATE CLE; NFCE_STATE ALE; NFCE_STATE CE; NFCE_STATE WE; NFCE_STATE RE; NFCE_STATE WP; NFCE_STATE RB; u8 cmd; cmdstatustype cmdstatus; iostatustype iostatus; u32 address; //u32 memsize; int fdump; u8 *writebuffer; u16 pageoffset; #ifdef POSIX_SHARE_MEMORY_BROKEN u8 *readbuffer; u32 curblock; FILE *fd; #else u8* addrspace; #endif }; #endif //_NANDFLASH_SMALLBLOCK_H_ skyeye-1.2.5_REL/device/nandflash/nandflash_smallblock.c0000644000175000001440000003727510704350434021756 0ustar kshusers/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author gbf0871 */ #include #include #include //#include #include "portable/mman.h" #include "skyeye_nandflash.h" #include "nandflash_smallblock.h" void nandflash_sb_reset(struct nandflash_device *dev); static void nandflash_sb_doerase(struct nandflash_device *dev,struct nandflash_sb_status *nf) { u32 blocks,len,base,i; if(nf->WP==NF_HIGH) { len=dev->erasesize; base=nf->address-nf->address%len; #ifndef POSIX_SHARE_MEMORY_BROKEN for (i=0;iaddrspace+base+i)=0xFF; #else lseek(nf->fdump,base,SEEK_SET); memset(nf->readbuffer,0xff,dev->pagedumpsize); nf->curblock=-1; for(i=0;ipagenum;i++) write(nf->fdump,nf->readbuffer,dev->pagedumpsize); #endif //msync(nf->addrspace+base,len,MS_ASYNC); } } static void nandflash_sb_dodatawrite(struct nandflash_device *dev,struct nandflash_sb_status *nf) { u32 offset; if(nf->WP==NF_HIGH) { //offset=nf->address%528; if (nf->pageoffset>dev->pagedumpsize-1) NANDFLASH_DBG("nandflash write cycle out bound\n"); nf->writebuffer[nf->pageoffset]=nf->IOPIN; nf->pageoffset++; } } static void nandflash_sb_finishwrite(struct nandflash_device *dev,struct nandflash_sb_status *nf) { u32 i,base; if(nf->WP==NF_HIGH) { base=nf->address-nf->address%dev->pagedumpsize; #ifndef POSIX_SHARE_MEMORY_BROKEN for (i=0;ipagedumpsize;i++) { *(nf->addrspace+base+i)&=nf->writebuffer[i]; } #else //printf("DEBUG:nand flash write\n"); lseek(nf->fdump,base,SEEK_SET); if(write(nf->fdump,nf->writebuffer,dev->pagedumpsize)!=dev->pagedumpsize) printf("nand flash write error\n"); //fsync(nf->fdump); #endif //msync(nf->addrspace+base,528,MS_ASYNC); } } static void nandflash_sb_doread(struct nandflash_device *dev,struct nandflash_sb_status *nf) { if(nf->addressdevicesize) { #ifndef POSIX_SHARE_MEMORY_BROKEN nf->IOPIN=*(nf->addrspace+nf->address); #else int blockoff=nf->address%dev->pagedumpsize; nf->IOPIN=nf->readbuffer[blockoff]; #endif nf->address++; #ifdef POSIX_SHARE_MEMORY_BROKEN if((nf->address%dev->pagedumpsize)==0) { nf->curblock=-1; } #endif if((nf->address%dev->pagedumpsize==0)&&(nf->cmd==NAND_CMD_READOOB)) { nf->address+=dev->pagesize; } //NANDFLASH_DBG("%s:mach:%x,data:%x\n", __FUNCTION__, nf->address,nf->IOPIN); } else { NANDFLASH_DBG("nandflash read outof bound!\n"); } } static void nandflash_sb_doreadid(struct nandflash_device *dev,struct nandflash_sb_status *nf) { switch(nf->cmdstatus){ case NF_readID_1st: nf->IOPIN=dev->ID[0]; nf->cmdstatus=NF_readID_2nd; break; case NF_readID_2nd: nf->IOPIN=dev->ID[1]; nf->cmdstatus=NF_readID_3rd; break; case NF_readID_3rd: nf->IOPIN=dev->ID[2]; nf->cmdstatus=NF_readID_4th; break; case NF_readID_4th: nf->IOPIN=dev->ID[3]; nf->cmdstatus=NF_NOSTATUS; nf->iostatus=NF_NONE; break; default: NANDFLASH_DBG("Nandflash readID Error!"); break; } } static void nandflash_sb_docmd(struct nandflash_device *dev,struct nandflash_sb_status *nf) { //printf("commd:%x\n",nf->IOPIN); switch(nf->IOPIN) { case NAND_CMD_READ0: nf->cmd=NAND_CMD_READ0; nf->cmdstatus=NF_addr_1st; nf->address=0; nf->iostatus=NF_ADDR; nf->pageoffset=0; break; case NAND_CMD_READ1: nf->cmd=NAND_CMD_READ1; nf->cmdstatus=NF_addr_1st; nf->pageoffset=256; nf->address=0; nf->iostatus=NF_ADDR;; break; case NAND_CMD_READOOB: nf->cmd=NAND_CMD_READOOB; nf->cmdstatus=NF_addr_1st; nf->address=0; nf->pageoffset=512; nf->iostatus=NF_ADDR; break; case NAND_CMD_RESET: nf->cmd=NAND_CMD_RESET; nandflash_sb_reset(dev); break; case NAND_CMD_SEQIN: nf->cmd=NAND_CMD_SEQIN; nf->cmdstatus=NF_addr_1st; memset(nf->writebuffer,0xFF,dev->pagedumpsize); nf->address=0; nf->iostatus=NF_ADDR; break; case NAND_CMD_ERASE1: nf->cmd=NAND_CMD_ERASE1; nf->cmdstatus=NF_addr_2nd; nf->iostatus=NF_ADDR; nf->pageoffset=0; nf->address=0; break; case NAND_CMD_ERASE2: if ((nf->cmd==NAND_CMD_ERASE1)&&(nf->cmdstatus==NF_addr_finish)) { nandflash_sb_doerase(dev,nf); } else { NANDFLASH_DBG("invalid ERASE2 commond,command:%x,status:%x\n",nf->cmd,nf->cmdstatus); } nf->cmd=NAND_CMD_NONE; break; case NAND_CMD_STATUS: nf->cmd=NAND_CMD_STATUS; nf->cmdstatus=NF_status; nf->iostatus=NF_STATUSREAD; break; case NAND_CMD_READID: nf->cmd=NAND_CMD_READID; nf->cmdstatus=NF_addr_4th; nf->pageoffset=0; nf->address=0; nf->iostatus=NF_ADDR; break; case NAND_CMD_PAGEPROG: if ((nf->cmd==NAND_CMD_SEQIN)&&(nf->cmdstatus==NF_addr_finish)) { nf->cmd=NAND_CMD_PAGEPROG; nandflash_sb_finishwrite(dev,nf); } else { NANDFLASH_DBG("invalid PAGEPROG commond,command:%x,status:%x\n",nf->cmd,nf->cmdstatus); } break; default: NANDFLASH_DBG("Unknow nandflash command:%x\n",nf->IOPIN); break; } } static void nandflash_sb_doaddr(struct nandflash_device *dev,struct nandflash_sb_status *nf) { u32 offset,rows,tmp; tmp=nf->IOPIN; //printf("tmp:%02x\n",tmp); switch (nf->cmdstatus) { case NF_addr_1st: nf->address=0; nf->pageoffset=nf->IOPIN+nf->pageoffset; nf->cmdstatus=NF_addr_2nd; break; case NF_addr_2nd: nf->address=(nf->address |(tmp<<9)); nf->cmdstatus=NF_addr_3rd; break; case NF_addr_3rd: nf->address=(nf->address |(tmp<<17)); nf->cmdstatus=NF_addr_4th; break; case NF_addr_4th: nf->address=(nf->address |(tmp<<25)); rows=nf->address>>9; nf->address=rows*528+nf->pageoffset; //NANDFLASH_DBG("set addr:%08x\n",nf->address); if ((nf->cmd==NAND_CMD_READ0)||(nf->cmd==NAND_CMD_READ1)||(nf->cmd==NAND_CMD_READOOB)) { nf->iostatus=NF_DATAREAD; #ifdef POSIX_SHARE_MEMORY_BROKEN int block=nf->address/dev->pagedumpsize; int tmp; //if(block!=nf->curblock) //{ //printf("nand read address:%08x\n",nf->address); if (nf->addressdevicesize) { memset(nf->readbuffer,0xff,dev->pagedumpsize); if(lseek(nf->fdump,block*dev->pagedumpsize,SEEK_SET)==-1) printf("lseek error\n"); //printf("offset:%d\n",block); tmp=read(nf->fdump,nf->readbuffer,dev->pagedumpsize); if (tmp!=dev->pagedumpsize) printf("read error address:%08x,readsize:%d,block:%d\n",nf->address,tmp,block); } else { printf("read outof bound\n"); } //} #endif } else if (nf->cmd==NAND_CMD_SEQIN) { nf->iostatus=NF_DATAWRITE; nf->cmdstatus=NF_addr_finish; //if (nf->pageoffset!=0) NANDFLASH_DBG("when page program offset is not 0 maybe this is error!\n"); } else if (nf->cmd==NAND_CMD_READID) { nf->iostatus=NF_IDREAD; nf->cmdstatus=NF_readID_1st; } else if (nf->cmd==NAND_CMD_ERASE1) { nf->iostatus=NF_CMD; nf->cmdstatus=NF_addr_finish; } else { NANDFLASH_DBG("Error address input\n"); } break; case NF_readID_addr: nf->cmdstatus=NF_readID_1st; nf->iostatus=NF_addr_finish; break; case NF_addr_finish: NANDFLASH_DBG("nandflash write address 4 cycle has already finish,but addr write however!\n"); break; default: NANDFLASH_DBG("nandflash write address error!\n"); break; } } u8 nandflash_sb_readio(struct nandflash_device *dev) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; if (nf->CE==NF_LOW) { return nf->IOPIN; } } void nandflash_sb_writeio(struct nandflash_device *dev,u8 iodata) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; if (nf->CE==NF_LOW) { nf->IOPIN=iodata; } } void nandflash_sb_setCE(struct nandflash_device *dev,NFCE_STATE state) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; nf->CE=state; if ((state==NF_HIGH) &(nf->iostatus==NF_DATAREAD)) { nf->iostatus=NF_NONE; } } void nandflash_sb_setCLE(struct nandflash_device *dev,NFCE_STATE state) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; if (nf->ALE==NF_HIGH) { NANDFLASH_DBG("warning the ALE is high,but CLE also set high\n");//maybe this warning is wrong,i don't know } nf->CLE=state; if ((state==NF_HIGH)&&(nf->CE==NF_LOW)) { nf->iostatus=NF_CMD; } } void nandflash_sb_setALE(struct nandflash_device *dev,NFCE_STATE state) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; if (nf->CLE==NF_HIGH) { NANDFLASH_DBG("warning the CLE is high,but ALE also set high\n"); //maybe this warning is wrong,i don't know } nf->ALE=state; if ((state==NF_HIGH)&&(nf->CE==NF_LOW)) { nf->iostatus=NF_ADDR; } } void nandflash_sb_setWE(struct nandflash_device *dev,NFCE_STATE state) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; if ((nf->WE==NF_LOW)&&(state==NF_HIGH)&&(nf->CE==NF_LOW)) //latched on the rising edge { switch(nf->iostatus) { case NF_CMD: nandflash_sb_docmd(dev,nf); break; case NF_ADDR: nandflash_sb_doaddr(dev,nf); break; case NF_DATAWRITE: nandflash_sb_dodatawrite(dev,nf); //nf->iostatus=NF_NONE; break; default: NANDFLASH_DBG("warning when WE raising,do nothing\n "); break; } } nf->WE=state; } void nandflash_sb_setRE(struct nandflash_device *dev,NFCE_STATE state) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; if ((nf->RE==NF_HIGH)&&(state==NF_LOW)&&(nf->CE==NF_LOW)) { switch(nf->iostatus) { case NF_DATAREAD: nandflash_sb_doread(dev,nf); break; case NF_IDREAD: nandflash_sb_doreadid(dev,nf); break; case NF_STATUSREAD: //printf("read status:0x%x\n",nf->status); nf->IOPIN=nf->status; nf->iostatus=NF_NONE; break; default: NANDFLASH_DBG("warning when RE falling,do nothing\n "); break; } } nf->RE=state; } void nandflash_sb_setWP(struct nandflash_device *dev,NFCE_STATE state) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; nf->WP=state; if (state==NF_LOW){ nf->status=nf->status & 127; printf("WP set LOW\n"); } else { nf->status=nf->status | 128; printf("WP set HIGH\n"); } } u32 nandflash_sb_readRB(struct nandflash_device *dev) //the rb { return 1; } void nandflash_sb_sendcmd(struct nandflash_device *dev,u8 cmd) //send a commond { nandflash_sb_setCLE(dev,NF_HIGH); nandflash_sb_setWE(dev,NF_LOW); nandflash_sb_writeio(dev,cmd); nandflash_sb_setWE(dev,NF_HIGH); nandflash_sb_setCLE(dev,NF_LOW); } void nandflash_sb_senddata(struct nandflash_device *dev,u8 data) { nandflash_sb_setWE(dev,NF_LOW); nandflash_sb_writeio(dev,data); nandflash_sb_setWE(dev,NF_HIGH); } void nandflash_sb_sendaddr(struct nandflash_device *dev,u8 data) { nandflash_sb_setALE(dev,NF_HIGH); nandflash_sb_setWE(dev,NF_LOW); nandflash_sb_writeio(dev,data); nandflash_sb_setWE(dev,NF_HIGH); nandflash_sb_setALE(dev,NF_LOW); } u8 nandflash_sb_readdata(struct nandflash_device *dev) { u8 data; nandflash_sb_setRE(dev,NF_LOW); data=nandflash_sb_readio(dev); nandflash_sb_setRE(dev,NF_HIGH); return data; } void nandflash_sb_poweron(struct nandflash_device *dev) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; nf->ALE=NF_LOW; nf->CLE=NF_LOW; nf->CE=NF_HIGH; nf->iostatus=NF_NONE; nf->IOPIN=0; nf->RB=1; nf->RE=NF_HIGH; nf->WE=NF_HIGH; nf->WP=NF_HIGH; nf->status=192; nf->pageoffset=0; nf->cmd=NAND_CMD_READ0; nf->cmdstatus=NF_NOSTATUS; nf->iostatus=NF_NONE; memset(nf->writebuffer,0xFF,dev->pagedumpsize); } void nandflash_sb_reset(struct nandflash_device *dev) { struct nandflash_sb_status *nf=(struct nandflash_sb_status*)dev->priv; nf->ALE=NF_LOW; nf->CLE=NF_LOW; //nf->CE=NF_HIGH; nf->iostatus=NF_NONE; nf->IOPIN=0; nf->RB=1; nf->RE=NF_HIGH; nf->WE=NF_HIGH; nf->WP=NF_HIGH; nf->status=192; nf->pageoffset=0; nf->cmd=NF_NOSTATUS; nf->cmdstatus=NF_NOSTATUS; nf->iostatus=NF_NONE; memset(nf->writebuffer,0xFF,dev->pagedumpsize); } void nandflash_sb_setup(struct nandflash_device* dev) { u8 flag=0xFF; int len,start,needinit=0; struct stat statbuf; struct nandflash_sb_status *nf; int i; nf=(struct nandflash_sb_status *)malloc(sizeof(struct nandflash_sb_status)); if (nf==NULL) { printf("error malloc nandflash_sb_status!\n"); skyeye_exit(-1); } dev->poweron=nandflash_sb_poweron; dev->readdata=nandflash_sb_readdata; dev->readio=nandflash_sb_readio; dev->readRB=nandflash_sb_readRB; dev->reset=nandflash_sb_reset; dev->sendaddr=nandflash_sb_sendaddr; dev->sendcmd=nandflash_sb_sendcmd; dev->senddata=nandflash_sb_senddata; dev->setALE=nandflash_sb_setALE; dev->setCE=nandflash_sb_setCE; dev->setCLE=nandflash_sb_setCLE; dev->setRE=nandflash_sb_setRE; dev->setWE=nandflash_sb_setWE; dev->setWP=nandflash_sb_setWP; memset(nf,0,sizeof(struct nandflash_sb_status)); #ifdef POSIX_SHARE_MEMORY_BROKEN nf->readbuffer=(u8*)malloc(dev->pagedumpsize); #endif nf->writebuffer=(u8*)malloc(dev->pagedumpsize); //nf->memsize=528*32*4096; if ((nf->fdump= open(dev->dump, FILE_FLAG)) < 0) { free(nf); printf("error open nandflash dump!\n"); skyeye_exit(-1); } if (fstat(nf->fdump, &statbuf) < 0) /* need size of input file */ { free(nf); printf("error fstat function\n"); skyeye_exit(-1); } if (statbuf.st_sizedevicesize) { printf("\nInit nandflash dump file.\n"); needinit=1; start=statbuf.st_size; len=dev->devicesize-start; lseek(nf->fdump,dev->devicesize-1,SEEK_SET); write(nf->fdump,&flag,1); #ifndef __MINGW32__ fsync(nf->fdump); #else _flushall(); #endif } #ifndef POSIX_SHARE_MEMORY_BROKEN if (fstat(nf->fdump, &statbuf) < 0) /* need size of input file */ { free(nf); printf("error fstat function\n"); skyeye_exit(-1); } printf("file size:%d\n",statbuf.st_size); if ((nf->addrspace= mmap(0, statbuf.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, nf->fdump, 0)) == MAP_FAILED) { free(nf); printf("error mmap nandflash file\n"); skyeye_exit(-1); } if (needinit) { for(i=start;idevicesize;i++) { *(nf->addrspace+i)=flag; } if (!msync(nf->addrspace,dev->devicesize,MS_SYNC)) printf("finish init nandflash dump\n"); } #else nf->curblock=-1; if (needinit) { memset(nf->readbuffer,0xff,dev->pagedumpsize); lseek(nf->fdump,start,SEEK_SET); while((dev->devicesize-start)>=dev->pagesize) { write(nf->fdump,nf->readbuffer,dev->pagesize); start=start+dev->pagesize; } for (i=start;idevicesize;i++) write(nf->fdump,&flag,1); } #endif dev->priv=nf; nandflash_sb_poweron(dev); } void nandflash_sb_uninstall(struct nandflash_device* dev) { struct nandflash_sb_status *nf; if(!dev->priv) { nf=(struct nandflash_sb_status*)dev->priv; if (!nf->fdump) { //msync(nf->addrspace,nf->memsize,MS_SYNC); #ifndef POSIX_SHARE_MEMORY_BROKEN munmap(nf->addrspace,dev->devicesize); #endif close(nf->fdump); NANDFLASH_DBG("Unistall nandflash\n"); } #ifdef POSIX_SHARE_MEMORY_BROKEN if(!nf->readbuffer) free(nf->readbuffer); #endif if(!nf->writebuffer) free(nf->writebuffer); free(nf); } } skyeye-1.2.5_REL/device/nandflash/skyeye_nandflash.h0000644000175000001440000000661610673446633021160 0ustar kshusers/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author gbf0871 */ #ifndef __SKYEYE_NANDFLASH_H_ #define __SKYEYE_NANDFLASH_H_ #include "skyeye_device.h" #define NANDFLASH_DEBUG 1 #if NANDFLASH_DEBUG #define NANDFLASH_DBG(msg...) fprintf(stderr, ##msg) #else #define NANDFLASH_DBG(msg...) #endif /* * Standard NAND flash commands */ #define NAND_CMD_NONE -1 #define NAND_CMD_READ0 0 #define NAND_CMD_READ1 1 #define NAND_CMD_PAGEPROG 0x10 #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 #define NAND_CMD_STATUS_MULTI 0x71 #define NAND_CMD_SEQIN 0x80 #define NAND_CMD_READID 0x90 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff typedef enum { NF_LOW, NF_HIGH } NFCE_STATE; struct nandflash_device { int mod; void *state; /* private data. */ void *priv; char dump[MAX_STR_NAME]; u32 pagesize,obbsize; u32 pagenum; /* page numbers per block*/ u32 blocknum; /* block numbers per device*/ u32 pagedumpsize,erasesize; u32 devicesize; u8 ID[5]; u8 (*readio)(struct nandflash_device * flash_dev); void (*writeio) (struct nandflash_device * flash_dev,u8 iodata); void (*setCE) (struct nandflash_device * flash_dev,NFCE_STATE state); void (*setCLE) (struct nandflash_device * flash_dev,NFCE_STATE state); void (*setALE) (struct nandflash_device * flash_dev,NFCE_STATE state); void (*setRE) (struct nandflash_device * flash_dev,NFCE_STATE state); void (*setWE) (struct nandflash_device * flash_dev,NFCE_STATE state); void (*setWP) (struct nandflash_device * flash_dev,NFCE_STATE state); u32 (*readRB)(struct nandflash_device * flash_dev); void (*sendcmd)(struct nandflash_device * flash_dev,u8 cmd); void (*sendaddr)(struct nandflash_device * flash_dev,u8 addr); void (*senddata)(struct nandflash_device * flash_dev,u8 data); u8 (*readdata)(struct nandflash_device * flash_dev); void (*poweron)(struct nandflash_device * flash_dev); void (*reset)(struct nandflash_device * flash_dev); void (*install)(struct nandflash_device *flash_dev); void (*uinstall)(struct nandflash_device *flash_dev); }; typedef struct nandflash_module_option { char *name; u32 pagesize,obbsize; u32 pagenum; /* page numbers per block*/ u32 blocknum; /* block numbers per device*/ u8 ID[5]; void (*install_dev) (struct nandflash_device *dev); void (*uinstall_dev)(struct nandflash_device *dev); } nandflash_module_option; int nandflash_module_setup(struct nandflash_device *dev,char *name); void nandflash_sb_uninstall(struct nandflash_device* dev); void nandflash_sb_setup(struct nandflash_device* dev); static nandflash_module_option nandflash_module_data[]={ {"K9F1208U0B",512,16,32,4096,{0xEC,0x76,0xA5,0xC0,0x0},nandflash_sb_setup,nandflash_sb_uninstall}, }; #endif /*__SKYEYE_NANDFLASH_H_*/ skyeye-1.2.5_REL/device/nandflash/tools/0000755000175000001440000000000011023514411016563 5ustar kshusersskyeye-1.2.5_REL/device/nandflash/tools/mknandflashdump.c0000644000175000001440000000365410673446633022137 0ustar kshusers#include #include #include #include #include #include #include #include #define FILE_MODE (S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH) int main(int argc, char *argv[]) { int fdin, fdout; unsigned char *src, *dst; struct stat statbuf; int i,j,size,offset,pos; if (argc != 4) { printf("usage: %s \n", argv[0]); exit(1); } if ((fdin = open(argv[1], O_RDONLY)) < 0) { printf("can't open %s for reading", argv[1]); exit(1); } if ((fdout = open(argv[2], O_RDWR | O_CREAT, FILE_MODE)) < 0) { printf("can't creat %s for writing", argv[2]); exit(1); } if (fstat(fdin, &statbuf) < 0) /* need size of input file */ { printf("fstat error"); exit(1); } offset=strtoul(argv[3],NULL,0); if(offset %512) { printf("offset not a multiple of 512 bytes\n"); exit(1); } size=((statbuf.st_size+offset+511)/512)*528; /* set size of output file */ if (lseek(fdout, size - 1, SEEK_SET) == -1) { printf("lseek error"); exit(1); } if (write(fdout, "", 1) != 1) { printf("write error"); exit(1); } if ((src = mmap(0, statbuf.st_size, PROT_READ, MAP_SHARED, fdin, 0)) == MAP_FAILED) { printf("mmap error for input"); exit(1); } if ((dst = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fdout, 0)) == MAP_FAILED) { printf("mmap error for output"); exit(1); } //memset(dst+offset,0xFF,size-offset); //printf("%x\n",offset); for(i=0,pos=(offset*528/512);i */ #include #include #include #include "armdefs.h" #include "skyeye_device.h" #include "skyeye_options.h" #include "skyeye.h" #include "skyeye_nandflash.h" extern void nandflash_s3c2410_init(struct device_module_set *mod_set); /* initialize the nandflash module set. * If you want to add a new nandflash simulation, just add a "flash_*_init" function to it. * */ static void nandflash_init (struct device_module_set *mod_set) { nandflash_s3c2410_init (mod_set); } nandflash_module_option * get_nandflashmd(char *name) { nandflash_module_option * md=nandflash_module_data; int i; for(i=0;iname)) return md; } return NULL; } int nandflash_module_setup(struct nandflash_device *dev,char *name) { nandflash_module_option * md; int ret=-1; int i; md=get_nandflashmd(name); if(md!=NULL){ dev->install=md->install_dev; dev->uinstall=md->uinstall_dev; dev->pagesize=md->pagesize; dev->obbsize=md->obbsize; dev->pagenum=md->pagenum; dev->blocknum=md->blocknum; dev->pagedumpsize=dev->pagesize+dev->obbsize; dev->erasesize=dev->pagedumpsize*dev->pagenum; dev->devicesize=dev->erasesize*dev->blocknum; for(i=0;i<5;i++) dev->ID[i]=md->ID[i]; //md->install_dev(dev); ret=0; } else { printf("nandflash not support this:%s\n",name); exit(1); } } static int nandflash_setup (struct device_desc *dev, void *option) { struct nandflash_device *nandflash_dev; struct flash_option *nandflash_opt = (struct flash_option *) option; int ret = 0; nandflash_dev = (struct nandflash_device *) malloc (sizeof (struct nandflash_device)); if (nandflash_dev == NULL) return 1; memset (nandflash_dev, 0, sizeof (struct nandflash_device)); memcpy (&nandflash_dev->dump[0], &nandflash_opt->dump[0], MAX_STR_NAME); dev->dev = (void *) nandflash_dev; return ret; } static struct device_module_set nandflash_mod_set = { .name = "nandflash", .count = 0, .count_max = 0, .init = nandflash_init, .initialized = 0, .setup_module = nandflash_setup, }; /* used by global device initialize function. * */ void nandflash_register () { if (register_device_module_set (&nandflash_mod_set)) SKYEYE_ERR ("\"%s\" module set register error!\n", nandflash_mod_set.name); } skyeye-1.2.5_REL/device/Makefile.in0000644000175000001440000022200411023514464015542 0ustar kshusers# Makefile.in generated by automake 1.10 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or 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install-exec-am install-html install-html-am install-info \ install-info-am install-man install-pdf install-pdf-am \ install-ps install-ps-am install-strip installcheck \ installcheck-am installdirs maintainer-clean \ maintainer-clean-generic mostlyclean mostlyclean-compile \ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \ uninstall-am # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: skyeye-1.2.5_REL/device/uart/0000755000175000001440000000000011023514411014440 5ustar kshusersskyeye-1.2.5_REL/device/uart/skyeye_uart_pipe.c0000644000175000001440000002266211006120657020203 0ustar kshusers/* skyeye_uart_pipe.c - skyeye uart device from pipe or device Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 2007.01.18 by Anthony Lee : initial version */ #include "skyeye_uart.h" #ifdef __BEOS__ #include #endif #if (defined(__MINGW32__) || (defined(__BEOS__) && B_BEOS_VERSION < 0x510)) #define SKYEYE_UART_PIPE_POSIX_SUPPORTED 0 #else #define SKYEYE_UART_PIPE_POSIX_SUPPORTED 1 #endif #if SKYEYE_UART_PIPE_POSIX_SUPPORTED #include #include #include #include typedef struct uart_pipe_t { int fd_in; int fd_out; } uart_pipe_t; int uart_pipe_open(struct uart_device *uart_dev) { uart_pipe_t *dev = malloc(sizeof(uart_pipe_t)); int ret = 0; if(dev == NULL) return -1; if(uart_dev->desc_in[0] == '\0') { ret = -1; } else if(uart_dev->desc_out[0] == '\0' || strcmp(uart_dev->desc_in, uart_dev->desc_out) == 0) { dev->fd_out = -1; if((dev->fd_in = open(uart_dev->desc_in, O_RDWR)) == -1) { ret = -1; fprintf(stderr, "Error when open device \"%s\" !!!", uart_dev->desc_in); } } else { if((dev->fd_in = open(uart_dev->desc_in, O_RDONLY)) == -1) { ret = -1; fprintf(stderr, "Error when open device \"%s\" for input !!!", uart_dev->desc_in); } else if((dev->fd_out = open(uart_dev->desc_out, O_WRONLY)) == -1) { close(dev->fd_in); ret = -1; fprintf(stderr, "Error when open device \"%s\" for output !!!", uart_dev->desc_out); } } if(ret == 0) uart_dev->priv = (void*)dev; else free(dev); return ret; } int uart_pipe_close(struct uart_device *uart_dev) { uart_pipe_t *dev = (uart_pipe_t*)uart_dev->priv; if(dev == NULL) return -1; if(dev->fd_in != -1) close(dev->fd_in); if(dev->fd_out != -1) close(dev->fd_out); free(dev); uart_dev->priv = NULL; return 0; } int uart_pipe_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout) { fd_set rfds; uart_pipe_t *dev = (uart_pipe_t*)uart_dev->priv; if(dev == NULL) return -1; FD_ZERO(&rfds); FD_SET(dev->fd_in, &rfds); if(select(dev->fd_in + 1, &rfds, NULL, NULL, timeout) != 1 || !FD_ISSET(dev->fd_in, &rfds)) return 0; return read(dev->fd_in, buf, count); } int uart_pipe_write(struct uart_device *uart_dev, void *buf, size_t count) { uart_pipe_t *dev = (uart_pipe_t*)uart_dev->priv; if(dev == NULL) return -1; return write((dev->fd_out != -1 ? dev->fd_out : dev->fd_in), buf, count); } #else /* !SKYEYE_UART_PIPE_POSIX_SUPPORTED */ #if (defined(__MINGW32__) || defined(__CYGWIN__)) #undef WORD #undef byte #include #define PIPE_BUFFER_SIZE 1 typedef struct uart_pipe_win32 { HANDLE fHandle; HANDLE fHandleOut; HANDLE fEvent; HANDLE fEventOut; unsigned char fBuffer[PIPE_BUFFER_SIZE]; DWORD fBufferLen; CRITICAL_SECTION fLocker; BOOL fReading; OVERLAPPED fOverlapped; OVERLAPPED fOverlappedOut; DWORD fWritten; } uart_pipe_win32; int uart_pipe_open(struct uart_device *uart_dev) { uart_pipe_win32 *dev = malloc(sizeof(uart_pipe_win32)); int ret = 0; if(dev == NULL) return -1; bzero(dev, sizeof(uart_pipe_win32)); if(strncmp(&uart_dev->desc_in[0], "/dev/ttyS", 9) == 0 && uart_dev->desc_in[9] >= '0' && uart_dev->desc_in[9] <= '8' && uart_dev->desc_in[10] == 0) { memcpy(&uart_dev->desc_in[0], "COM\0", 5); uart_dev->desc_in[3] = uart_dev->desc_in[9] + 1; } if(strncmp(&uart_dev->desc_out[0], "/dev/ttyS", 9) == 0 && uart_dev->desc_out[9] >= '0' && uart_dev->desc_out[9] <= '8' && uart_dev->desc_out[10] == 0) { memcpy(&uart_dev->desc_out[0], "COM\0", 5); uart_dev->desc_out[3] = uart_dev->desc_out[9] + 1; } if(uart_dev->desc_in[0] == '\0') { ret = -1; } else if(uart_dev->desc_out[0] == '\0' || strcmp(uart_dev->desc_in, uart_dev->desc_out) == 0) { if((dev->fHandle = CreateFile(uart_dev->desc_in, GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_FLAG_OVERLAPPED, NULL)) == INVALID_HANDLE_VALUE) { ret = -1; fprintf(stderr, "Error when open device \"%s\" !!!\n", uart_dev->desc_in); } } else { if((dev->fHandle = CreateFile(uart_dev->desc_in, GENERIC_READ, FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_FLAG_OVERLAPPED, NULL)) == INVALID_HANDLE_VALUE) { ret = -1; fprintf(stderr, "Error when open device \"%s\" for input !!!\n", uart_dev->desc_in); } else if((dev->fHandleOut = CreateFile(uart_dev->desc_out, GENERIC_WRITE, FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_FLAG_OVERLAPPED, NULL)) == INVALID_HANDLE_VALUE) { CloseHandle(dev->fHandle); ret = -1; fprintf(stderr, "Error when open device \"%s\" for output !!!\n", uart_dev->desc_out); } } if(ret != 0) { free(dev); return ret; } InitializeCriticalSection(&dev->fLocker); dev->fEvent = CreateEvent(NULL, TRUE, FALSE, NULL); dev->fEventOut = CreateEvent(NULL, FALSE, FALSE, NULL); uart_dev->priv = (void*)dev; return 0; } int uart_pipe_close(struct uart_device *uart_dev) { uart_pipe_win32 *dev = (uart_dev ? (uart_pipe_win32*)(uart_dev->priv) : NULL); if(dev == NULL) return -1; CloseHandle(dev->fHandle); if(dev->fHandleOut) CloseHandle(dev->fHandleOut); CloseHandle(dev->fEvent); CloseHandle(dev->fEventOut); DeleteCriticalSection(&dev->fLocker); uart_dev->priv = NULL; return 0; } static void CALLBACK uart_pipe_read_callback(DWORD dwErrorCode, DWORD dwNumberOfBytesTransfered, LPOVERLAPPED lpOverlapped) { uart_pipe_win32 *dev = (uart_pipe_win32*)lpOverlapped->hEvent; if(dev == NULL) return; EnterCriticalSection(&dev->fLocker); dev->fReading = FALSE; dev->fBufferLen = (dwErrorCode == 0 ? dwNumberOfBytesTransfered : 0); SetEvent(dev->fEvent); LeaveCriticalSection(&dev->fLocker); } static void CALLBACK uart_pipe_write_callback(DWORD dwErrorCode, DWORD dwNumberOfBytesTransfered, LPOVERLAPPED lpOverlapped) { uart_pipe_win32 *dev = (uart_pipe_win32*)lpOverlapped->hEvent; if(dev == NULL) return; dev->fWritten = (dwErrorCode == 0 ? dwNumberOfBytesTransfered : 0); SetEvent(dev->fEventOut); } int uart_pipe_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *tv) { uart_pipe_win32 *dev = (uart_dev ? (uart_pipe_win32*)(uart_dev->priv) : NULL); int retVal = 0, flags = 1; DWORD status; if(dev == NULL) return -1; restart: EnterCriticalSection(&dev->fLocker); if(dev->fReading) { retVal = 0; } else if(dev->fBufferLen == 0) { retVal = 0; dev->fReading = TRUE; dev->fOverlapped.Internal = 0; dev->fOverlapped.InternalHigh = 0; dev->fOverlapped.Offset = 0; dev->fOverlapped.OffsetHigh = 0; dev->fOverlapped.hEvent = dev; ResetEvent(dev->fEvent); if(ReadFileEx(dev->fHandle, &dev->fBuffer[0], PIPE_BUFFER_SIZE, &dev->fOverlapped, uart_pipe_read_callback) == 0) { dev->fReading = FALSE; retVal = -1; } } else { retVal = min((int)dev->fBufferLen, count); memcpy(buf, &dev->fBuffer[0], (size_t)retVal); if(count < dev->fBufferLen) memmove(&dev->fBuffer[0], &dev->fBuffer[count], dev->fBufferLen - count); dev->fBufferLen -= retVal; } LeaveCriticalSection(&dev->fLocker); if(retVal == 0 && flags == 1) { DWORD timeout = (tv == NULL ? INFINITE : (DWORD)(tv->tv_sec * 1000UL + tv->tv_usec / 1000UL)); while(TRUE) { status = WaitForSingleObjectEx(dev->fEvent, timeout, TRUE); if(status == WAIT_IO_COMPLETION && tv == NULL) continue; if(status == WAIT_OBJECT_0) { flags = 0; goto restart; } break; } } return retVal; } int uart_pipe_write(struct uart_device *uart_dev, void *buf, size_t count) { uart_pipe_win32 *dev = (uart_dev ? (uart_pipe_win32*)(uart_dev->priv) : NULL); DWORD written = 0, status; HANDLE handle; if(dev == NULL) return -1; handle = (dev->fHandleOut == NULL ? dev->fHandle : dev->fHandleOut); dev->fOverlappedOut.Internal = 0; dev->fOverlappedOut.InternalHigh = 0; dev->fOverlappedOut.Offset = 0; dev->fOverlappedOut.OffsetHigh = 0; dev->fOverlappedOut.hEvent = dev; dev->fWritten = 0; if(WriteFileEx(handle, buf, (DWORD)count, &dev->fOverlappedOut, uart_pipe_write_callback) != 0) { while(TRUE) { status = WaitForSingleObjectEx(dev->fEventOut, INFINITE, TRUE); if(status == WAIT_IO_COMPLETION) continue; if(status == WAIT_OBJECT_0) written = dev->fWritten; break; } } return (int)written; } #else /* other system */ int uart_pipe_open(struct uart_device *uart_dev) { return -1; } int uart_pipe_close(struct uart_device *uart_dev) { return -1; } int uart_pipe_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout) { return -1; } int uart_pipe_write(struct uart_device *uart_dev, void *buf, size_t count) { return -1; } #endif #endif /* SKYEYE_UART_PIPE_POSIX_SUPPORTED */ skyeye-1.2.5_REL/device/uart/skyeye_uart_net.c0000644000175000001440000000241110555732132020027 0ustar kshusers/* skyeye_uart_net.c - skyeye uart device from tcp port Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 2007.01.18 by Anthony Lee : initial version */ #include "skyeye_uart.h" int uart_net_open(struct uart_device *uart_dev) { return -1; } int uart_net_close(struct uart_device *uart_dev) { return -1; } int uart_net_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout) { return -1; } int uart_net_write(struct uart_device *uart_dev, void *buf, size_t count) { return -1; } skyeye-1.2.5_REL/device/uart/skyeye_uart_stdio.c0000644000175000001440000001406510704350434020370 0ustar kshusers/* skyeye_uart_stdio.c - skyeye uart device from standard input/output Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 2007.01.18 by Anthony Lee : initial version */ #include "skyeye_uart.h" #ifndef __MINGW32__ #ifdef __BEOS__ #include #if (B_BEOS_VERSION >= 0x510) #include #else /* B_BEOS_VERSION < 0x510 */ #define SELECT_UNSUPPORTED #endif /* B_BEOS_VERSION >= 0x510 */ #else /* !__BEOS__ */ #include #endif /* __BEOS__ */ #ifdef SELECT_UNSUPPORTED #include #include "portable/usleep.h" #endif /* SELECT_UNSUPPORTED */ #include #include int uart_stdio_open(struct uart_device *uart_dev) { struct termios tmp; if((uart_dev->priv = malloc(sizeof(struct termios))) == NULL) return -1; tcgetattr(0, &tmp); memcpy(uart_dev->priv, &tmp, sizeof(struct termios)); /* Set the terminal for non-blocking per-character (not per-line) input, no echo */ tmp.c_lflag &= ~ICANON; tmp.c_lflag |= ISIG; tmp.c_lflag &= ~ECHO; tmp.c_cc[VMIN] = 0; tmp.c_cc[VTIME] = 0; tcsetattr(0, TCSANOW, &tmp); return 0; } int uart_stdio_close(struct uart_device *uart_dev) { if(uart_dev->priv != NULL) { /* Restore the original terminal settings */ tcsetattr(0, TCSANOW, (struct termios*)uart_dev->priv); free(uart_dev->priv); uart_dev->priv = NULL; } return 0; } int uart_stdio_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout) { /* * 2007-03-03 by Anthony Lee : for the system that don't support select(). * WHY: maybe useful for real-time improvement. */ #ifndef SELECT_UNSUPPORTED fd_set rfds; FD_ZERO(&rfds); FD_SET(0, &rfds); if(select(1, &rfds, NULL, NULL, timeout) != 1 || !FD_ISSET(0, &rfds)) return 0; return read(0, buf, count); #else /* SELECT_UNSUPPORTED */ int retVal; int64_t time_left; if(timeout != NULL) time_left = (int64_t)timeout->tv_sec * (int64_t)1000000 + (int64_t)timeout->tv_usec; while(1) { /* for non-blocking input, instead of polling. */ if((retVal = read(0, buf, count)) != 0) break; if(timeout == NULL) continue; if(time_left <= 0) break; usleep(1000); time_left -= (int64_t)1000; } return retVal; #endif /* !SELECT_UNSUPPORTED */ } int uart_stdio_write(struct uart_device *uart_dev, void *buf, size_t count) { return write(1, buf, count); } #else /* __MINGW32__ */ #undef WORD #undef byte #include int uart_stdio_open(struct uart_device *uart_dev) { char *term = getenv("TERM"); DWORD console_mode = 0; if(term ? (strcmp(term, "xterm") == 0 || strcmp(term, "msys") == 0) : 0) /* rxvt shell */ { /* TODO */ fprintf(stderr, "\x1b[31m***\n" "*** [UART_STDIO_WIN32]: unsupported for rxvt shell !!!\n" "***\tyou should add \"GOTO: startsh\" to the target of\n" "***\tthe link pointed to \"msys.bat\".\n" "***\n\x1b[0m"); skyeye_exit(-1); } if(GetStdHandle(STD_INPUT_HANDLE) == NULL || GetStdHandle(STD_INPUT_HANDLE) == INVALID_HANDLE_VALUE) { AllocConsole(); Sleep(500); } GetConsoleMode(GetStdHandle(STD_INPUT_HANDLE), &console_mode); /* Set the terminal for non-blocking per-character (not per-line) input, no echo */ SetConsoleMode(GetStdHandle(STD_INPUT_HANDLE), console_mode & ~(ENABLE_LINE_INPUT | ENABLE_ECHO_INPUT)); uart_dev->priv = (void*)console_mode; return 0; } int uart_stdio_close(struct uart_device *uart_dev) { /* Restore the original terminal settings */ SetConsoleMode(GetStdHandle(STD_INPUT_HANDLE), (DWORD)uart_dev->priv); return 0; } int uart_stdio_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout) { int flags = -1; DWORD status; HANDLE handle = NULL; DWORD nRead = 0; INPUT_RECORD input; DWORD nEvents = 0; /* 2007-01-24 modified by Anthony Lee : for working on Windows 9x */ DWORD msec = (timeout == NULL ? INFINITE : (DWORD)(timeout->tv_sec * 1000UL + timeout->tv_usec / 1000UL)); handle = GetStdHandle(STD_INPUT_HANDLE); if(handle == NULL || handle == INVALID_HANDLE_VALUE) { fprintf(stderr, "%s: Unable to get handle.\n", __FUNCTION__); return -1; } status = WaitForSingleObject(handle, msec); if(status == WAIT_TIMEOUT) flags = 0; /* timeout */ else if(status == WAIT_OBJECT_0) flags = 1; /* got something */ if(flags <= 0) return flags; /* non-blocking stardand input */ /* FIXME: IT IS NOT GOOD */ while(!(GetNumberOfConsoleInputEvents(handle, &nEvents) == 0 || nEvents == 0) && nRead < count) { DWORD code; if(ReadConsoleInput(handle, &input, 1, &nEvents) == 0 || nEvents != 1) break; if(input.EventType != KEY_EVENT) continue; if(input.Event.KeyEvent.bKeyDown == FALSE) continue; code = input.Event.KeyEvent.wVirtualKeyCode; if(code == VK_SHIFT || code == VK_MENU || code == VK_CONTROL || code == VK_LWIN || code == VK_RWIN || code == VK_APPS || code == VK_CAPITAL || code == VK_SCROLL || code == VK_NUMLOCK) continue; *(((char*)buf) + (nRead++)) = input.Event.KeyEvent.uChar.AsciiChar; } return (int)nRead; } int uart_stdio_write(struct uart_device *uart_dev, void *buf, size_t count) { HANDLE handle = NULL; DWORD nWritten = 0; handle = GetStdHandle(STD_OUTPUT_HANDLE); if(handle == NULL || handle == INVALID_HANDLE_VALUE) { fprintf(stderr, "%s: Unable to get handle.\n", __FUNCTION__); return -1; } if(!WriteFile(handle, buf, count, &nWritten, NULL)) return -1; return (int)nWritten; } #endif /* !__MINGW32__ */ skyeye-1.2.5_REL/device/uart/skyeye_uart.c0000644000175000001440000001441410604241721017161 0ustar kshusers/* skyeye_uart.c - skyeye uart device support functions Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 2007.01.18 by Anthony Lee : initial version */ #include "skyeye_config.h" #include "skyeye_uart.h" #include "portable/gettimeofday.h" #include "portable/usleep.h" struct uart_converter { char name[MAX_STR_NAME]; void (*setup)(struct uart_device *uart_dev); }; static struct uart_converter uart_cvts[] = { /* name setup */ { "dcc", skyeye_uart_converter_dcc_setup }, { "", NULL }, }; static int skyeye_uart_stdio_once_flag = 0; static int skyeye_uart_check_timeout(struct timeval *tv) { struct timeval cur_time; if (tv == NULL) return 1; if (gettimeofday(&cur_time, NULL) != 0) return -1; if (cur_time.tv_sec > tv->tv_sec) return 0; if (cur_time.tv_sec == tv->tv_sec && cur_time.tv_usec >= tv->tv_usec) return 0; return 1; } int skyeye_uart_read(int devIndex, void *buf, size_t count, struct timeval *timeout, int *retDevIndex) { int retVal = -1; struct uart_device *uart_dev; if (retDevIndex != NULL) *retDevIndex = -1; if (devIndex >= skyeye_config.uart.count || buf == NULL || count == 0) { /* invalid */ } else if(devIndex >= 0) { /* single device */ uart_dev = skyeye_config.uart.devs[devIndex]; retVal = uart_dev->uart_read(uart_dev, buf, count, timeout); } else { /* all devices */ int i, stop_flags = 0; struct timeval tv, zero_tv; if (!(timeout == NULL || gettimeofday(&tv, NULL) == 0)) { /* something error */ } else { if (timeout != NULL) { tv.tv_sec += (timeout->tv_sec + (timeout->tv_usec + tv.tv_usec) / 1000000UL); tv.tv_usec = (timeout->tv_usec + tv.tv_usec) % 1000000UL; } zero_tv.tv_sec = 0; zero_tv.tv_usec = 0; do { for (i = 0; i < skyeye_config.uart.count; i++) { uart_dev = skyeye_config.uart.devs[i]; retVal = uart_dev->uart_read(uart_dev, buf, count, &zero_tv); if(retVal > 0) { /* got something */ devIndex = i; break; } if(retVal == 0) continue; stop_flags |= (1 << i); /* failed */ } if (stop_flags == (1 << skyeye_config.uart.count) - 1) { /* all failed */ retVal = -1; } else if (retVal > 0) { stop_flags = 1; } else { retVal = 0; if (skyeye_uart_check_timeout(timeout != NULL ? &tv : NULL) == 1) { /* polling */ stop_flags = 0; usleep(500); } else { /* timeout */ stop_flags = 1; } } } while (stop_flags == 0); } } if (retVal > 0 && retDevIndex != NULL) *retDevIndex = devIndex; return retVal; } int skyeye_uart_write(int devIndex, void *buf, size_t count, int *wroteBytes[MAX_UART_DEVICE_NUM]) { int i = (devIndex < 0 ? skyeye_config.uart.count - 1 : devIndex); int retVal = -1; int nWrote = 0; if (i < 0 || i >= skyeye_config.uart.count) return -1; do { nWrote = skyeye_config.uart.devs[i]->uart_write(skyeye_config.uart.devs[i], buf, count); if (wroteBytes != NULL) (*wroteBytes)[i] = nWrote; retVal = max(retVal, nWrote); } while (--i >= 0 && devIndex < 0); return retVal; } /* skyeye_uart_cleanup(): for cleanup stack on exit */ void skyeye_uart_cleanup() { int i = skyeye_config.uart.count; struct uart_device *dev; skyeye_config.uart.count = 0; while (--i >= 0) { dev = skyeye_config.uart.devs[i]; dev->uart_close(dev); free(dev); } } /* skyeye_uart_setup(): setup device when analyzing uart options */ int skyeye_uart_setup(struct uart_option *uart_opt) { struct uart_device *uart_dev; int ret = -1; if (skyeye_config.uart.count >= MAX_UART_DEVICE_NUM) return -1; uart_dev = (struct uart_device *)malloc(sizeof(struct uart_device)); if (uart_dev == NULL) return -1; memset(uart_dev, 0, sizeof(struct uart_device)); uart_dev->mod = uart_opt->mod; memcpy(&uart_dev->desc_in[0], &uart_opt->desc_in[0], MAX_STR_NAME); memcpy(&uart_dev->desc_out[0], &uart_opt->desc_out[0], MAX_STR_NAME); memcpy(&uart_dev->converter[0], &uart_opt->converter[0], MAX_STR_NAME); printf("uart_mod:%d, desc_in:%s, desc_out:%s, converter:%s\n", uart_dev->mod, uart_dev->desc_in, uart_dev->desc_out, uart_dev->converter); switch (uart_dev->mod) { case UART_SIM_STDIO: if (skyeye_uart_stdio_once_flag != 0) break; uart_dev->uart_open = uart_stdio_open; uart_dev->uart_close = uart_stdio_close; uart_dev->uart_read = uart_stdio_read; uart_dev->uart_write = uart_stdio_write; ret = 0; break; case UART_SIM_PIPE: uart_dev->uart_open = uart_pipe_open; uart_dev->uart_close = uart_pipe_close; uart_dev->uart_read = uart_pipe_read; uart_dev->uart_write = uart_pipe_write; ret = 0; break; case UART_SIM_NET: uart_dev->uart_open = uart_net_open; uart_dev->uart_close = uart_net_close; uart_dev->uart_read = uart_net_read; uart_dev->uart_write = uart_net_write; ret = 0; break; default: break; } if (ret == 0) { if(uart_dev->uart_open(uart_dev) == 0) { skyeye_config.uart.devs[skyeye_config.uart.count++] = uart_dev; if(uart_dev->mod == UART_SIM_STDIO) skyeye_uart_stdio_once_flag = 1; } else { ret = -1; } } if (ret != 0) { free(uart_dev); uart_dev = NULL; } return ret; } /* skyeye_uart_converter_setup(): setup converter of uart devices after machine initalized */ void skyeye_uart_converter_setup(void) { struct uart_device *uart_dev; int i, k; for (i = 0; i < skyeye_config.uart.count; i++) { uart_dev = skyeye_config.uart.devs[i]; if (uart_dev->converter[0] == 0) continue; for (k = 0; uart_cvts[k].setup != NULL; k++) { if (strncmp(&uart_dev->converter[0], &uart_cvts[k].name[0], MAX_STR_NAME) == 0) { (*(uart_cvts[k].setup))(uart_dev); } } } } skyeye-1.2.5_REL/device/uart/skyeye_uart_cvt_dcc.c0000644000175000001440000001102710604241721020643 0ustar kshusers/* skyeye_uart_cvt_dcc.c - skyeye JTAG Debug Communication Channel simulation Copyright (C) 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 2007.03.31 Written by Anthony Lee */ /* * NOTE: * THE CODES JUST BASED ON linux-2.6.x source * "linux-2.6.x/drivers/serial/dcc.c" by Hyok S. Choi (hyok.choi@samsung.com) */ #include "armdefs.h" #include "skyeye_uart.h" #define PRINT(x...) printf("[JTAG_DCC]: " x) struct uart_dcc_device { unsigned flags; struct uart_device *dev; int (*uart_close)(struct uart_device *uart_dev); int (*uart_read)(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout); int (*uart_write)(struct uart_device *uart_dev, void *buf, size_t count); }; static struct uart_dcc_device dcc = {0, NULL, NULL, NULL, NULL}; static unsigned uart_dcc_cp14_mrc(ARMul_State *state, unsigned type, ARMword instr, ARMword *value) { unsigned opcode_1 = BITS(21, 23); unsigned CRn = BITS(16, 19); unsigned CRm = BITS(0, 3); unsigned opcode_2 = BITS(5, 7); if (!(opcode_1 == 0 && opcode_2 == 0 && CRn < 2 && CRm == 0)) return ARMul_CANT; if ((dcc.flags & 0x1) && dcc.dev != NULL) { switch (CRn) { case 0: /* returns the Debug Comms Control Register into Rd */ if ((dcc.flags & 0x2) == 0 && dcc.uart_read != NULL) { unsigned char c; struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; if (dcc.uart_read(dcc.dev, &c, 1, &tv) > 0) { dcc.flags = 0x3 | (c << 2); } } *value = (dcc.flags & 0x2) == 0 ? 0 : 1; /* W bit always be 0 */ break; case 1: /* returns the Debug data read register into Rd */ *value = 0; if ((dcc.flags & 0x2) != 0) { *value = (dcc.flags >> 2) & 0xff; dcc.flags = 0x1; } break; default: break; } } return ARMul_DONE; } static unsigned uart_dcc_cp14_mcr(ARMul_State *state, unsigned type, ARMword instr, ARMword value) { unsigned opcode_1 = BITS(21, 23); unsigned CRn = BITS(16, 19); unsigned CRm = BITS(0, 3); unsigned opcode_2 = BITS(5, 7); if (!(opcode_1 == 0 && opcode_2 == 0 && CRn == 1 && CRm == 0)) return ARMul_CANT; /* writes the value in Rn to the Comms Write Register */ if ((dcc.flags & 0x1) && dcc.dev != NULL && dcc.uart_write != NULL) { unsigned char c = value & 0xff; dcc.uart_write(dcc.dev, &c, 1); } return ARMul_DONE; } static int uart_dcc_close(struct uart_device *uart_dev) { if (dcc.flags != 0) { ARMul_CoProDetach((ARMul_State*)skyeye_config.mach->state, 14); dcc.dev->uart_close = dcc.uart_close; dcc.dev->uart_read = dcc.uart_read; dcc.dev->uart_write = dcc.uart_write; dcc.dev = NULL; dcc.flags = 0; if (uart_dev->uart_close != NULL) uart_dev->uart_close(uart_dev); } return 0; } static int uart_dcc_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout) { return -1; } static int uart_dcc_write(struct uart_device *uart_dev, void *buf, size_t count) { return -1; } void skyeye_uart_converter_dcc_setup(struct uart_device *uart_dev) { ARMul_State *state; if (skyeye_config.arch == NULL || skyeye_config.arch->arch_name == NULL || strcmp(skyeye_config.arch->arch_name, "arm") != 0 || skyeye_config.mach == NULL || (state = (ARMul_State*)skyeye_config.mach->state) == NULL || state->is_XScale != 0) { PRINT("*** ERROR: Unsupported architecture !!!\n"); return; } if (dcc.flags != 0) { PRINT("*** ERROR: JTAG DCC has been installed !!!\n"); return; } dcc.flags = 0x1; dcc.dev = uart_dev; dcc.uart_close = uart_dev->uart_close; dcc.uart_read = uart_dev->uart_read; dcc.uart_write= uart_dev->uart_write; uart_dev->uart_close = uart_dcc_close; uart_dev->uart_read = uart_dcc_read; uart_dev->uart_write = uart_dcc_write; ARMul_CoProAttach(state, 14, NULL, NULL, NULL, NULL, uart_dcc_cp14_mrc, uart_dcc_cp14_mcr, NULL, NULL, NULL); } skyeye-1.2.5_REL/device/uart/skyeye_uart.h0000644000175000001440000000675210604002410017162 0ustar kshusers/* skyeye_uart.h - skyeye uart device support functions Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __SKYEYE_UART_H_ #define __SKYEYE_UART_H_ #include #include "skyeye_device.h" #include "skyeye_config.h" /* uart simulation type */ #define UART_SIM_STDIO 0 /* use stdin and stdout as fd */ #define UART_SIM_PIPE 1 /* use file (pipe file) or device(/dev/ttyS1) as fd */ #define UART_SIM_NET 2 /* use tcp port as fd */ struct uart_device { int mod; char desc_in[MAX_STR_NAME]; /* description of device, such as path etc. */ char desc_out[MAX_STR_NAME]; /* description of device, such as path etc. */ /* private data. */ void *priv; int (*uart_open)(struct uart_device *uart_dev); int (*uart_close)(struct uart_device *uart_dev); int (*uart_read)(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout); int (*uart_write)(struct uart_device *uart_dev, void *buf, size_t count); char converter[MAX_STR_NAME]; void *converter_priv; /* converter private data. */ }; void skyeye_uart_cleanup(); int skyeye_uart_setup(struct uart_option *uart_opt); /* converter */ void skyeye_uart_converter_setup(void); void skyeye_uart_converter_dcc_setup(struct uart_device *uart_dev); /* modules */ int uart_stdio_open(struct uart_device *uart_dev); int uart_stdio_close(struct uart_device *uart_dev); int uart_stdio_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout); int uart_stdio_write(struct uart_device *uart_dev, void *buf, size_t count); int uart_pipe_open(struct uart_device *uart_dev); int uart_pipe_close(struct uart_device *uart_dev); int uart_pipe_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout); int uart_pipe_write(struct uart_device *uart_dev, void *buf, size_t count); int uart_net_open(struct uart_device *uart_dev); int uart_net_close(struct uart_device *uart_dev); int uart_net_read(struct uart_device *uart_dev, void *buf, size_t count, struct timeval *timeout); int uart_net_write(struct uart_device *uart_dev, void *buf, size_t count); /* helper functions */ /* skyeye_uart_read(), skyeye_uart_write(): * devIndex: * >= 0 --- the index of device * < 0 --- all devices, skyeye_uart_write() return the maximum bytes of the actions * retDevIndex: * if you don't pass NULL to it, skyeye_uart_read() replace the value of it be the index of device that got something. * wroteBytes: * if you don't pass NULL to it, skyeye_uart_write() replace the value of it be the bytes of each action of devices. */ int skyeye_uart_read(int devIndex, void *buf, size_t count, struct timeval *timeout, int *retDevIndex); int skyeye_uart_write(int devIndex, void *buf, size_t count, int *wroteBytes[MAX_UART_DEVICE_NUM]); #endif /* __SKYEYE_UART_H_ */ skyeye-1.2.5_REL/device/net/0000755000175000001440000000000011023514411014253 5ustar kshusersskyeye-1.2.5_REL/device/net/dev_net_rtl8019.h0000644000175000001440000002234510604132031017257 0ustar kshusers/* dev_net_rtl8019.h - skyeye realtek 8019 ethernet controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 05/25/2005 modified for rtl8019 * walimis * * 02/25/2003 initial version * yangye * chenyu */ #ifndef _DEV_NET_RTL8019_H_ #define _DEV_NET_RTL8019_H_ #define NE_CR 0x0 //R/W£¬¶Ô²»Í¬µÄÒ³£¬CR¶¼ÊÇͬһ¸ö //page0 registers #define NE_PSTART 0x01 //W£¬½ÓÊÕ»º³å»·Æðʼҳ #define NE_PSTOP 0x02 //W£¬½ÓÊÕ»º³å»·ÖÕÖ¹Ò³£¨²»°üÀ¨´ËÒ³£© #define NE_BNRY 0x03 //R/W£¬½ÓÊÕ»º³å»·¶ÁÖ¸Õ룬ָÏòÏÂÒ»¸ö°üµ½À´Ê±µÄÆðʼҳ,Ó¦³õʼ»¯³É£½CURR£½PSTART #define NE_TPSR 0x04 //W£¬Local DMA·¢ËÍ»º³åÆðʼҳ¼Ä´æÆ÷ #define NE_TBCR0 0x05 //W£¬Local DMA·¢Ëͳ¤¶ÈµÍλ #define NE_TBCR1 0x06 //W£¬Local DMA·¢Ëͳ¤¶È¸ßλ #define NE_ISR 0x07 //R/W£¬ÖжÏ״̬¼Ä´æÆ÷ #define NE_RSAR0 0x08 //W£¬Remote DMAÄ¿µÄÆðʼµØÖ·µÍλ #define NE_RSAR1 0x09 //W£¬Remote DMAÄ¿µÄÆðʼµØÖ·¸ßλ //ÕâÁ½¸öÊÇCPUÏòÍø¿¨Ð´Èë»ò¶Á³öÊý¾Ý°üµÄʵ¼Ê³¤¶È£¬Ö´ÐÐRemote DMAÃüÁîǰÉèÖà #define NE_RBCR0 0x0a //W£¬Remote DMAÊý¾Ý³¤¶ÈµÍλ #define NE_RBCR1 0x0b //W£¬Remote DMAÊý¾Ý³¤¶È¸ßλ #define NE_RCR 0x0c //W£¬½ÓÊÕÅäÖüĴæÆ÷,³õʼ»¯Ê±Ð´Èë0x04,±íʾֻ½ÓÊÕ·¢¸ø±¾Íø¿¨MACµØÖ·µÄ,´óÓÚ64×Ö½ÚµÄÒÔÌ«Íø°ü»ò¹ã²¥°ü #define NE_TCR 0x0d //·¢ËÍÅäÖüĴæÆ÷,³õʼ»¯¿ªÊ¼Ê±Ð´Èë0x02£¬ÖÃÍø¿¨ÎªLoop Backģʽ£¬Í£Ö¹·¢ËÍÊý¾Ý°ü,³õʼ»¯½áÊøÐ´Èë0x00¡£Õý³£·¢ËÍÊý¾Ý°ü²¢¼ÓÉÏCRC #define NE_DCR 0x0e //W£¬Êý¾ÝÅäÖüĴæÆ÷,³õʼ»¯Ê±Ð´Èë0x48£¬8λģʽ£¬FIFOÉî¶È8×Ö½Ú£¬DMA·½Ê½ #define NE_IMR 0x0f //W£¬ÖÐ¶ÏÆÁ±Î¼Ä´æÆ÷ËüµÄ¸÷λºÍISRÖеĸ÷λÏà¶ÔÓ¦£¬ÏòIMRдÈëÖµ¼´Îª´ò¿ªÏàÓ¦ÖÐ¶Ï //page1 registers #define NE_PAR0 0x01 //R/W£¬Íø¿¨MACµØÖ·×î¸ßλ #define NE_PAR1 0x02 //R/W£¬Íø¿¨MACµØÖ· #define NE_PAR2 0x03 //R/W£¬Íø¿¨MACµØÖ· #define NE_PAR3 0x04 //R/W£¬Íø¿¨MACµØÖ· #define NE_PAR4 0x05 //R/W£¬Íø¿¨MACµØÖ· #define NE_PAR5 0x06 //R/W£¬Íø¿¨MACµØÖ·×îµÍλ #define NE_CURR 0x07 //R/W£¬½ÓÊÕ»º³å»·Ð´Ö¸Õë #define NE_MAR0 0x08 //R/W£¬×é²¥¼Ä´æÆ÷ #define NE_MAR1 0x09 //R/W£¬×é²¥¼Ä´æÆ÷ #define NE_MAR2 0x0a //R/W£¬×é²¥¼Ä´æÆ÷ #define NE_MAR3 0x0b //R/W£¬×é²¥¼Ä´æÆ÷ #define NE_MAR4 0x0c //R/W£¬×é²¥¼Ä´æÆ÷ #define NE_MAR5 0x0d //R/W£¬×é²¥¼Ä´æÆ÷ #define NE_MAR6 0x0e //R/W£¬×é²¥¼Ä´æÆ÷ #define NE_MAR7 0x0f //R/W£¬×é²¥¼Ä´æÆ÷ //page2 registers //#define NE_PSTART 0x01 //R£¬½ÓÊÕ»º³å»·Æðʼҳ //#define NE_PSTOP 0x02 //R£¬½ÓÊÕ»º³å»·ÖÕÖ¹Ò³£¨²»°üÀ¨´ËÒ³£© //#define NE_TPSR 0x04 //R£¬Local DMA·¢ËÍ»º³åÆðʼҳ¼Ä´æÆ÷ //#define NE_RCR 0x0c //R£¬½ÓÊÕÅäÖüĴæÆ÷ //#define NE_TCR 0x0d //R,·¢ËÍÅäÖüĴæÆ÷ //#define NE_DCR 0x0e //R£¬Êý¾ÝÅäÖüĴæÆ÷ //#define NE_IMR 0x0f //R£¬ÓÃÀ´¶ÁÖÐ¶ÏÆÁ±Î¼Ä´æÆ÷IMR״̬ //CRÃüÁî¼Ä´æÆ÷µÄÃüÁî #define CMD_STOP 0x01 //Íø¿¨Í£Ö¹ÊÕ·¢Êý¾Ý #define CMD_RUN 0x02 //Íø¿¨Ö´ÐÐÃüÁî²¢¿ªÊ¼ÊÕ·¢Êý¾Ý°ü£¨ÃüÁîΪÏÂÃæËÄÖÖ£© #define CMD_XMIT 0x04 //Local DMA SEND£¨Íø¿¨¨D¨D>ÒÔÌ«Íø £© #define CMD_READ 0x08 //Remote DMA READ£¬ÓÃÓÚÊÖ¶¯½ÓÊÕÊý¾Ý£¨Íø¿¨¨D¨D>CPU£© #define CMD_WRITE 0x10 //Remote DMA WRITE £¨Íø¿¨<¨D¨DCPU£© #define CMD_SEND 0x18 //SEND COMMANDÃüÁÓÃÓÚ×Ô¶¯½ÓÊÕÊý¾Ý°ü £¨Íø¿¨¨D¨D>CPU£© #define CMD_NODMA 0x20 //Í£Ö¹DMA²Ù×÷ #define CMD_PAGE0 0x00 // Ñ¡ÔñµÚ0Ò³£¨ÒªÏÈѡҳ£¬ÔÙ¶Áд¸ÃÒ³¼Ä´æÆ÷£© #define CMD_PAGE1 0x40 // Ñ¡ÔñµÚ1Ò³ #define CMD_PAGE2 0x80 // Ñ¡ÔñµÚ2Ò³ //дÈëTPSRµÄÖµ #define XMIT_START 0x4000 //·¢ËÍ»º³åÆðʼµØÖ·£¨Ð´ÈëʱҪÓÒÒÆ8λµÃµ½Ò³ºÅ£© //дÈëPSTARTµÄÖµ #define RECV_START 0x4600 //½ÓÊÕ»º³åÆðʼµØÖ·£¨Ð´ÈëʱҪÓÒÒÆ8λµÃµ½Ò³ºÅ£© //дÈëPSTOPµÄÖµ #define RECV_STOP 0x6000 //½ÓÊÕ»º³å½áÊøµØÖ·£¨Ð´ÈëʱҪÓÒÒÆ8λµÃµ½Ò³ºÅ£© //ÖжÏ״̬¼Ä´æÆ÷µÄÖµ #define ISR_PRX 0x01 //ÕýÈ·½ÓÊÕÊý¾Ý°üÖжϡ£×ö½ÓÊÕ´¦Àí #define ISR_PTX 0x02 //ÕýÈ··¢ËÍÊý¾Ý°üÖжϡ£×ö²»×ö´¦ÀíÒª¿´ÉϲãÈí¼þÁË¡£ #define ISR_RXE 0x04 //½ÓÊÕÊý¾Ý°ü³ö´í¡£×öÖØÐÂÉèÖÃBNRY£½CURR´¦Àí¡£ #define ISR_TXE 0x08 //ÓÉÓÚ³åÍ»´ÎÊý¹ý¶à£¬·¢Ëͳö´í¡£×öÖØ·¢´¦Àí #define ISR_OVW 0x10 //Íø¿¨ÄÚ´æÒç³ö¡£×öÈí¼þÖØÆôÍø¿¨´¦Àí¡£¼ûÊֲᡣ #define ISR_CNT 0x20 //³ö´í¼ÆÊýÆ÷Öжϣ¬ÆÁ±Îµô£¨ÆÁ±ÎÓÃIMR¼Ä´æÆ÷£©¡£ #define ISR_RDC 0x40 //Remote DMA½áÊø ¡£ÆÁ±Îµô¡£ÂÖѯµÈ´ýDMA½áÊø¡£ #define ISR_RST 0x80 //Íø¿¨Reset£¬ÆÁ±Îµô¡£ //ÖÐ¶ÏÆÁ±Î¼Ä´æÆ÷µÄÖµ #define ISR_PRX 0x01 #define ISR_PTX 0x02 #define ISR_RXE 0x04 #define ISR_TXE 0x08 #define ISR_OVW 0x10 #define ISR_CNT 0x20 #define ISR_RDC 0x40 #define ISR_RST 0x80 //Êý¾Ý¿ØÖƼĴæÆ÷ //³õʼ»¯Ê±Ð´Èë0x48£¬8λģʽ£¬FIFOÉî¶È8×Ö½Ú£¬DMA·½Ê½¡£ #define DCR_WTS 0x01 #define DCR_BOS 0x02 #define DCR_LAS 0x04 #define DCR_LS 0x08 #define DCR_ARM 0x10 #define DCR_FIFO2 0x00 #define DCR_FIFO4 0x20 #define DCR_FIFO8 0x40 #define DCR_FIFO12 0x60 //TCR·¢ËÍÅäÖüĴæÆ÷ //³õʼ»¯¿ªÊ¼Ê±Ð´Èë0x02£¬ÖÃÍø¿¨ÎªLoop Backģʽ£¬Í£Ö¹·¢ËÍÊý¾Ý°ü£¬ //³õʼ»¯½áÊøÐ´Èë0x00¡£Õý³£·¢ËÍÊý¾Ý°ü²¢¼ÓÉÏCRC¡£ #define TCR_CRC 0x01 #define TCR_LOOP_NONE 0x00 #define TCR_LOOP_INT 0x02 #define TCR_LOOP_EXT 0x06 #define TCR_ATD 0x08 #define TCR_OFST 0x10 //RCR½ÓÊÕÅäÖüĴæÆ÷ //³õʼ»¯Ê±Ð´Èë0x04¡£Ö»½ÓÊÕ·¢¸ø±¾Íø¿¨MACµØÖ·´óÓÚ64×Ö½ÚµÄÒÔÌ«Íø°ü»ò¹ã²¥°ü #define RCR_SEP 0x01 #define RCR_AR 0x02 #define RCR_AB 0x04 #define RCR_AM 0x08 #define RCR_PRO 0x10 #define RCR_MON 0x20 /* Bits in received packet status byte and EN0_RSR*/ #define RSR_RXOK 0x01 /* Received a good packet */ #define RSR_CRC 0x02 /* CRC error */ #define RSR_FAE 0x04 /* frame alignment error */ #define RSR_FO 0x08 /* FIFO overrun */ #define RSR_MPA 0x10 /* missed pkt */ #define RSR_PHY 0x20 /* physical/multicast address */ #define RSR_DIS 0x40 /* receiver disable. set in monitor mode */ #define RSR_DEF 0x80 /* deferring */ /* Transmitted packet status, EN0_TSR. */ #define TSR_PTX 0x01 /* Packet transmitted without error */ #define TSR_ND 0x02 /* The transmit wasn't deferred. */ #define TSR_COL 0x04 /* The transmit collided at least once. */ #define TSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ #define TSR_CRS 0x10 /* The carrier sense was lost. */ #define TSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ #define TSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ #define TSR_OWC 0x80 /* There was an out-of-window collision. */ /* walimis */ #define START_PAGE 0x40 #define END_PAGE 0x80 #define PAGE_SIZE 0x100 #define PAGE_NUM (END_PAGE - START_PAGE) /* 16Kbytes */ #define INT_RTL8019 0 //the structure typedef struct net_rtl8019_io { // Page 0 // Command Register - 00h read/write u8 CR; //01h write ; page start register u8 PSTART; //02h write ; page stop register u8 PSTOP; //03h read/write ; boundary pointer u8 BNRY; //04h write ; transmit page start register u8 TSR; u8 TPSR; //05,06h write ; transmit byte-count register u8 TBCR0; u8 TBCR1; // Interrupt Status Register - 07h read/write u8 ISR; //08,09h write ; remote start address register u8 RSAR0; u8 RSAR1; //0a,0bh write ; remote byte-count register u8 RBCR0; u8 RBCR1; // Receive Configuration Register - 0ch write u8 RSR; u8 RCR; // Transmit Configuration Register - 0dh write u8 CNTR0; u8 TCR; // Data Configuration Register - 0eh write u8 CNTR1; u8 DCR; // Interrupt Mask Register - 0fh write u8 CNTR2; u8 IMR; // Page 1 // // Command Register 00h (repeated) //01-06h read/write ; MAC address u8 PAR0; u8 PAR1; u8 PAR2; u8 PAR3; u8 PAR4; u8 PAR5; // 07h read/write ; current page register u8 CURR; // 08-0fh read/write ; multicast hash array //Bit8u MAR[8]; // // Page 2 - diagnostic use only // // Command Register 00h (repeated) // // Page Start Register 01h read (repeated) PSTART // Page Stop Register 02h read (repeated) PSTOP // Transmit Page start address 04h read (repeated) TPSR // Receive Configuration Register 0ch read (repeated) RCR // Transmit Configuration Register 0dh read (repeated)TCR // Data Configuration Register 0eh read (repeated) DCR // Interrupt Mask Register 0fh read (repeated) IMR // u8 PROM[12]; // 12 bytes in Prom for MAC addr. u8 *sram; u32 remote_read_offset; u32 remote_write_offset; u32 remote_read_count; u32 remote_write_count; int need_update; int index; int op_16; } net_rtl8019_io_t; static u8 rtl8019_output (struct device_desc *dev, u8 * buf, u16 packet_len); static void rtl8019_input (struct device_desc *dev); #endif //_DEV_NET_RTL8019_H_ skyeye-1.2.5_REL/device/net/dev_net_cs8900a.h0000644000175000001440000002260510673435452017245 0ustar kshusers /* dev_net_cs8900a.h - skyeye Cirrus Logic CS8900A ethernet controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/04/2005 initial version * walimis */ #ifndef _DEV_NET_CS8900A_H_ #define _DEV_NET_CS8900A_H_ /* * take from linux/drivers/net/cirrus.h * * Author: Abraham van der Merwe * * A Cirrus Logic CS8900A driver for Linux * based on the cs89x0 driver written by Russell Nelson, * Donald Becker, and others. * * This source code is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. */ /* * Ports */ #define Rx_Frame_Port 0x00 /* Receive Data (Section 4.10.10) */ #define Tx_Frame_Port Rx_Frame_Port /* Transmit Data Port (Section 4.10.10) */ #define IO_TxCMD 0x04 /* Transmit Command see P75. (Section 4.10) */ #define IO_TxLength 0x06 /* Transmit Length see P75. (Section 4.10) */ #define IO_ISQ 0x08 /* Transmit Length see P75. (Section 4.10) */ #define PP_Address 0x0a /* PacketPage Pointer Port (Section 4.10.10) */ #define PP_Data 0x0c /* PacketPage Data Port (Section 4.10.10) */ /* * Registers */ #define PP_ProductID 0x0000 /* Section 4.3.1 Product Identification Code */ #define PP_MemBase 0x002c /* Section 4.9.2 Memory Base Address Register */ #define PP_IntNum 0x0022 /* Section 3.2.3 Interrupt Number */ #define PP_EEPROMCommand 0x0040 /* Section 4.3.11 EEPROM Command */ #define PP_EEPROMData 0x0042 /* Section 4.3.12 EEPROM Data */ #define PP_RxCFG 0x0102 /* Section 4.4.6 Receiver Configuration */ #define PP_RxCTL 0x0104 /* Section 4.4.8 Receiver Control */ #define PP_TxCFG 0x0106 /* Section 4.4.9 Transmit Configuration */ #define PP_BufCFG 0x010a /* Section 4.4.12 Buffer Configuration */ #define PP_LineCTL 0x0112 /* Section 4.4.16 Line Control */ #define PP_SelfCTL 0x0114 /* Section 4.4.18 Self Control */ #define PP_BusCTL 0x0116 /* Section 4.4.20 Bus Control */ #define PP_TestCTL 0x0118 /* Section 4.4.22 Test Control */ #define PP_ISQ 0x0120 /* Section 4.4.5 Interrupt Status Queue */ #define PP_RxEvent 0x0124 /* Section 4.4.7 Receiver Event */ #define PP_RxEventalt 0x0124 /* Section 4.4.7 Receiver Event */ #define PP_TxEvent 0x0128 /* Section 4.4.10 Transmitter Event */ #define PP_BufEvent 0x012c /* Section 4.4.13 Buffer Event */ #define PP_RxMISS 0x0130 /* Section 4.4.14 Receiver Miss Counter */ #define PP_TxCOL 0x0132 /* Section 4.4.15 Transmit Collision Counter */ #define PP_LineST 0x0134 /* Section 4.4.17 Line Status */ #define PP_SelfST 0x0136 /* Section 4.4.19 Self Status */ #define PP_BusST 0x0138 /* Section 4.4.21 Bus Status */ #define PP_TxCMD 0x0144 /* Section 4.4.11 Transmit Command */ #define PP_TxLength 0x0146 /* Section 4.5.2 Transmit Length */ #define PP_IA 0x0158 /* Section 4.6.2 Individual Address (IEEE Address) */ #define PP_RxStatus 0x0400 /* Section 4.7.1 Receive Status */ #define PP_RxLength 0x0402 /* Section 4.7.1 Receive Length (in bytes) */ #define PP_RxFrame 0x0404 /* Section 4.7.2 Receive Frame Location */ #define PP_TxFrame 0x0a00 /* Section 4.7.2 Transmit Frame Location */ /* * Values */ /* PP_IntNum */ #define INTRQ0 0x0000 #define INTRQ1 0x0001 #define INTRQ2 0x0002 #define INTRQ3 0x0003 /* PP_ProductID */ #define EISA_REG_CODE 0x630e #define REVISION(x) (((x) & 0x1f00) >> 8) #define VERSION(x) ((x) & ~0x1f00) #define CS8900A 0x0000 #define REV_B 7 #define REV_C 8 #define REV_D 9 /* PP_RxCFG */ #define Skip_1 0x0040 #define StreamE 0x0080 #define RxOKiE 0x0100 #define RxDMAonly 0x0200 #define AutoRxDMAE 0x0400 #define BufferCRC 0x0800 #define CRCerroriE 0x1000 #define RuntiE 0x2000 #define ExtradataiE 0x4000 /* PP_RxCTL */ #define IAHashA 0x0040 #define PromiscuousA 0x0080 #define RxOKA 0x0100 #define MulticastA 0x0200 #define IndividualA 0x0400 #define BroadcastA 0x0800 #define CRCerrorA 0x1000 #define RuntA 0x2000 #define ExtradataA 0x4000 /* PP_TxCFG */ #define Loss_of_CRSiE 0x0040 #define SQErroriE 0x0080 #define TxOKiE 0x0100 #define Out_of_windowiE 0x0200 #define JabberiE 0x0400 #define AnycolliE 0x0800 #define T16colliE 0x8000 /* PP_BufCFG */ #define SWint_X 0x0040 #define RxDMAiE 0x0080 #define Rdy4TxiE 0x0100 #define TxUnderruniE 0x0200 #define RxMissiE 0x0400 #define Rx128iE 0x0800 #define TxColOvfiE 0x1000 #define MissOvfloiE 0x2000 #define RxDestiE 0x8000 /* PP_LineCTL */ #define SerRxON 0x0040 #define SerTxON 0x0080 #define AUIonly 0x0100 #define AutoAUI_10BT 0x0200 #define ModBackoffE 0x0800 #define PolarityDis 0x1000 #define L2_partDefDis 0x2000 #define LoRxSquelch 0x4000 /* PP_SelfCTL */ #define RESET 0x0040 #define SWSuspend 0x0100 #define HWSleepE 0x0200 #define HWStandbyE 0x0400 #define HC0E 0x1000 #define HC1E 0x2000 #define HCB0 0x4000 #define HCB1 0x8000 /* PP_BusCTL */ #define ResetRxDMA 0x0040 #define DMAextend 0x0100 #define UseSA 0x0200 #define MemoryE 0x0400 #define DMABurst 0x0800 #define IOCHRDYE 0x1000 #define RxDMAsize 0x2000 #define EnableRQ 0x8000 /* PP_TestCTL */ #define DisableLT 0x0080 #define ENDECloop 0x0200 #define AUIloop 0x0400 #define DisableBackoff 0x0800 #define FDX 0x4000 /* PP_ISQ */ #define RegNum(x) ((x) & 0x3f) #define RegContent(x) ((x) & ~0x3d) #define RxEvent 0x0004 #define TxEvent 0x0008 #define BufEvent 0x000c #define RxMISS 0x0010 #define TxCOL 0x0012 /* PP_RxStatus */ #define IAHash 0x0040 #define Dribblebits 0x0080 #define RxOK 0x0100 #define Hashed 0x0200 #define IndividualAdr 0x0400 #define Broadcast 0x0800 #define CRCerror 0x1000 #define Runt 0x2000 #define Extradata 0x4000 #define HashTableIndex(x) ((x) >> 0xa) /* PP_TxCMD */ #define After5 0 #define After381 1 #define After1021 2 #define AfterAll 3 #define TxStart(x) ((x) << 6) #define Force 0x0100 #define Onecoll 0x0200 #define InhibitCRC 0x1000 #define TxPadDis 0x2000 /* PP_BusST */ #define TxBidErr 0x0080 #define Rdy4TxNOW 0x0100 /* PP_TxEvent */ #define Loss_of_CRS 0x0040 #define SQEerror 0x0080 #define TxOK 0x0100 #define Out_of_window 0x0200 #define Jabber 0x0400 #define T16coll 0x8000 #define TX_collisions(x) (((x) >> 0xb) & ~0x8000) /* PP_BufEvent */ #define SWint 0x0040 #define RxDMAFrame 0x0080 #define Rdy4Tx 0x0100 #define TxUnderrun 0x0200 #define RxMiss 0x0400 #define Rx128 0x0800 #define RxDest 0x8000 /* PP_RxMISS */ #define MissCount(x) ((x) >> 6) /* PP_TxCOL */ #define ColCount(x) ((x) >> 6) /* PP_SelfST */ #define T3VActive 0x0040 #define INITD 0x0080 #define SIBUSY 0x0100 #define EEPROMpresent 0x0200 #define EEPROMOK 0x0400 #define ELpresent 0x0800 #define EEsize 0x1000 /* PP_LineST - Ethernet Line Status bit definition - Read-only */ #define LINK_OK 0x0080 #define AUI_ON 0x0100 #define TENBASET_ON 0x0200 #define POLARITY_OK 0x1000 #define CRS_OK 0x4000 /* PP_EEPROMCommand */ #define EEWriteEnable 0x00F0 #define EEWriteDis 0x0000 #define EEWriteRegister 0x0100 #define EEReadRegister 0x0200 #define EEEraseRegister 0x0300 #define ELSEL 0x0400 /* walimis */ #define CtrlStNum(x) (((x & 0xfff) - 0x100)/2) #define Rx_Frame_Count 2048 #define Tx_Frame_Count 1024 #define Rx_Max_Count 1514 /* */ #define INT_CS8900A 0 //the structure typedef struct net_cs8900a_io { u16 pp_address; u16 pp_data; /* Bus Interface Registers */ u16 product_id[2]; u16 iobas_num; u16 int_num; u16 dma_channel_num; u16 dma_start_frame; u16 dma_frame_count; u16 rxdma_byte_count; u16 mem_base[2]; u16 boot_prom_base[2]; u16 boot_prom_mask[2]; u16 eeprom_cmd; u16 eeprom_data; u16 eeprom[64]; // 64 (16 bits word) in Prom. int eeprom_writable; /* Status and Control Registers */ u16 ctrl_st[32]; /* u16 sc_isq; u16 sc_rx_cfg; u16 sc_rx_event; u16 sc_rx_ctrl; u16 sc_tx_cfg; u16 sc_tx_event; u16 sc_tx_cmd_status; u16 sc_buf_cfg; u16 sc_buf_event; u16 sc_rx_miss_count; u16 sc_tx_col_count; u16 sc_line_ctrl; u16 sc_line_status; u16 sc_self_ctrl; u16 sc_self_status; u16 sc_bus_ctrl; u16 sc_bus_status; u16 sc_test_ctrl; */ /* Initiat Transmit Registers */ u16 tx_cmd; u16 tx_length; /* Address Filter Registers */ u8 hash_table[8]; u8 ieee_addr[6]; /* Frame Location Registers */ u16 *rx_status_p; u16 *rx_length_p; u16 *rx_frame; u16 rx_head; u16 rx_tail; u16 *tx_frame; u16 tx_head; u16 tx_tail; int need_update; int index; } net_cs8900a_io_t; static u8 cs8900a_output (struct device_desc *dev, u8 * buf, u16 packet_len); static void cs8900a_input (struct device_desc *dev); #endif //_DEV_NET_CS8900A_H_ skyeye-1.2.5_REL/device/net/skyeye_net_vnet.c0000644000175000001440000001307411012326044017640 0ustar kshusers/* skyeye_net_vnet.c - vnet net device file support functions Copyright (C) 2003 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/15/2005 modified for new net simulation framework * walimis * * 04/27/2003 initial version * chenyu */ #include "armdefs.h" #if !(defined(__MINGW32__) || defined(__CYGWIN__) || defined(__BEOS__) || defined(__svr4__)) #if defined( __FreeBSD__) || defined(__APPLE__) #include #endif #include #include #include //chy: make sure that if_vnet.h is as same as vnet/if_vnet.h #include "if_vnet.h" #define DEBUG 1 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr, ##a) #else #define DBG_PRINT(a...) #endif #define DEFAULT_VNET_IF_NAME "tap" static name_index = 0; //chy:2003-04-26 open&ioctl net dev file, and return file handler // set ne2k mac addr is in nic_reset function // no use hostip int vnet_open (struct net_device *net_dev) { int vnetif_fd, vnet_fd; static int firsttime = 0; struct ifreq ifr; int flag; unsigned char maddr[6]; char buf[128]; char if_name[10]; firsttime++; //chy: should change !!! will support more virtual hubs in the future if (firsttime == 1) { if (net_dev->hostip[0] == 0) //means don't do hostif ...... goto vnet_done; /* if(vnet_fd=open("/var/vnet_lock",O_CREAT|O_EXCL|O_RDONLY)<0) goto vnet_done; if(unlink("/var/vnet_lock")<0){ perror("vnet_open: unlink error"); exit(-1); } */ vnetif_fd = open ("/dev/net/vnet", O_RDWR); DBG_PRINT ("vnet_open:for hostif fd %d\n", vnetif_fd); if (vnetif_fd == -1) { perror ("vnet_open:for hostif open"); printf ("-----------------------------------------------------------\n"); printf ("NOTICE: Now the net simulation function is disable!!!\n"); printf ("NOTICE: 1. you should be root at first !!!\n"); printf ("NOTICE: 2. if you don't make device node, you should do commands:\n"); printf ("NOTICE: mkdir /dev/net; mknod /dev/net/vnet c 10 201\n"); printf ("NOTICE: 3. you should inmod linux kernel net driver vnet.o!!!\n"); printf ("NOTICE: Please read README in SkyEye package and try again!!!\n"); printf ("-----------------------------------------------------------\n"); skyeye_exit (-1); } snprintf (if_name, sizeof (if_name), "%s%d", DEFAULT_VNET_IF_NAME, name_index); memset (&ifr, 0, sizeof (ifr)); //If you don't set name, then it will be set in vnet_hostif_create //If you want more vnet, then you should set in here //maybe should be defineed in skyeye.conf //now, I only use vnet0. chy //IFNAMSIZ=16 strncpy (ifr.ifr_name, if_name, IFNAMSIZ); ifr.ifr_flags = IFF_VNET; if (ioctl (vnetif_fd, VNETSETIFF, (void *) &ifr) < 0) { perror ("ioctl VNETSETIFF error"); skyeye_exit (-1); } DBG_PRINT ("ioctl VNETSETIFF ok\n"); snprintf (buf, sizeof (buf), "ifconfig %s inet %d.%d.%d.%d", if_name, net_dev->hostip[0], net_dev->hostip[1], net_dev->hostip[2], net_dev->hostip[3]); DBG_PRINT ("tapif_init: system(\"%s\");\n", buf); system (buf); } vnet_done: //the scond time, open dev file for guestif vnetif_fd = open ("/dev/net/vnet", 2); DBG_PRINT ("vnet_open:for guestif fd %d\n", vnetif_fd); if (vnetif_fd == -1) { perror ("vnet_open:for guestif open"); skyeye_exit (-1); } //set mac addr for vnet memcpy (maddr, net_dev->macaddr, 6); if (ioctl (vnetif_fd, SIOCSIFADDR, (void *) maddr) < 0) { printf ("vnet_open: set mac addr error\n"); skyeye_exit (-1); } DBG_PRINT ("vnet_open: vnet_open: set mac addr ok\n"); //set ifflag for vnet flag = IFF_UP | IFF_RUNNING | IFF_BROADCAST; if (ioctl (vnetif_fd, SIOCSIFFLAGS, (void *) &flag) < 0) { printf ("vnet_open: ioctl vnet set ifflag error\n"); skyeye_exit (-1); } DBG_PRINT ("vnet_open: ioctl vnet set ifflag ok.\n"); DBG_PRINT ("vnet_open end\n"); return vnetif_fd; } int vnet_close (struct net_device *net_dev) { close (net_dev->net_fd); return 0; } int vnet_read (struct net_device *net_dev, void *buf, size_t count) { return read (net_dev->net_fd, buf, count); } int vnet_write (struct net_device *net_dev, void *buf, size_t count) { return write (net_dev->net_fd, buf, count); } int vnet_wait_packet (struct net_device *net_dev, struct timeval *tv) { fd_set frds; int ret; FD_ZERO(&frds); FD_SET(net_dev->net_fd, &frds); if((ret = select(net_dev->net_fd + 1, &frds, NULL, NULL, tv)) <= 0) return -1; if(!FD_ISSET(net_dev->net_fd, &frds)) return -1; return 0; } #else /* unsupported */ int vnet_open (struct net_device *net_dev) { return -1; } int vnet_close (struct net_device *net_dev) { return 0; } int vnet_read (struct net_device *net_dev, void *buf, size_t count) { return 0; } int vnet_write (struct net_device *net_dev, void *buf, size_t count) { return 0; } int vnet_wait_packet (struct net_device *net_dev, struct timeval *tv) { return -1; } #endif skyeye-1.2.5_REL/device/net/dev_net_s3c4510b.c0000644000175000001440000002204210577433673017316 0ustar kshusers/* dev_net_s3c4510b.c - skyeye S3C4510B ethernet controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/19/2007 cleanup the useless codes. * Anthony Lee * 06/17/2005 initial verion for s3c4510b * walimis */ #include "armdefs.h" #include "skyeye_device.h" #include "dev_net_s3c4510b.h" static struct device_default_value s3c4510b_net_def[] = { /* name base size interrupt array */ {"s3c4510b", 0x3FF9000, 0x2000, {16, 17, 18, 19}}, {NULL}, }; #define MAX_DEVICE_NUM 10 static struct device_desc *s3c4510b_devs[MAX_DEVICE_NUM]; static void mac_write (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct net_device *net_dev = (struct net_device *) dev->dev; struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; ARMul_State *state = (ARMul_State *) mc->state; fault_t fault; u32 ptr, status, len; int i; fault = mmu_read_word (state, io->bdmatxptr, &ptr); /* if( fault ) { *addr = io->bdmatxptr; return fault; } */ if (!(ptr & BDMA_owner)) return; ptr &= ~BDMA_owner; fault = mmu_read_word (state, io->bdmatxptr + 8, &len); /* if( fault ) { *addr = io->bdmatxptr + 8; return fault; } */ len &= 0xffff; if (len > sizeof (io->mac_buf)) return; for (i = 0; i < len; i++) { fault = mmu_read_byte (state, ptr + i, io->mac_buf + i); /* if( fault ) { *addr = ptr + i; return fault; } */ } //Update TXstatus status = len | (Comp << 16); fault = mmu_write_word (state, io->bdmatxptr + 8, status); //print_packet(io->mac_buf, len); /* if( fault ) { *addr = io->bdmatxptr + 8; return fault; } */ //set owner bit of desc to CPU fault = mmu_write_word (state, io->bdmatxptr, ptr); /* if( fault ) { *addr = io->bdmatxptr; return fault; } */ //get next desc fault = mmu_read_word (state, io->bdmatxptr + 12, &io->bdmatxptr); /* if( fault ) { *addr = io->bdmatxptr + 12; */ net_dev->net_write (net_dev, io->mac_buf, len); //write( skyeye_config.net[0].fd, io->mac_buf, len ); //trigger interrupt if (io->mactxcon & EnComp) { mc->mach_set_intr (intr->interrupts[INT_S3C4510B_MACTX]); mc->mach_update_intr (mc); //s3c4510b_set_interrupt(INT_MACTX); //s3c4510b_update_int(state); } } static void mac_read (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct net_device *net_dev = (struct net_device *) dev->dev; struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; ARMul_State *state = (ARMul_State *) mc->state; int packet_len, s3c4510b_len; fault_t fault; u32 ptr, status_len; int n, i; //*addr = 0; packet_len = net_dev->net_read (net_dev, io->mac_buf, sizeof (io->mac_buf)); //n = read(skyeye_config.net[0].fd, mac_buf, sizeof(mac_buf)); if (packet_len <= 0) return; fault = mmu_read_word (state, io->bdmarxptr, &ptr); //print_packet(io->mac_buf, packet_len); /* if( fault ) { *addr = io->bdmarxptr; return fault; } */ if (!(ptr & BDMA_owner)) return; ptr &= ~BDMA_owner; //if( len + 2 > sizeof(mac_buf) ) return 0; /* FIXME:for s3c4510b frame, ptr offset is 2 */ for (i = 0; i < packet_len; i++) { fault = mmu_write_byte (state, ptr + 2 + i, *(io->mac_buf + i)); /* if(fault) { *addr = ptr + 2 + i; return fault; } */ } //in desc, set Good bit for RX status , and set len status_len = (Good << 16) | (packet_len + 4); //printf("status_len:%x\n",status_len); fault = mmu_write_word (state, io->bdmarxptr + 8, status_len); /* if(fault) { *addr = io->bdmarxptr+8; return fault; } */ //set owner bit of desc to CPU fault = mmu_write_word (state, io->bdmarxptr, ptr); /* if(fault) { *addr = io->bdmarxptr; return fault; } */ //get next desc fault = mmu_read_word (state, io->bdmarxptr + 12, &io->bdmarxptr); /* if(fault) { *addr = io->bdmarxptr + 12; return fault; } */ /* update bdmastat register */ io->bdmastat |= S_BRxRDF; mc->mach_set_intr (intr->interrupts[INT_S3C4510B_BDMARX]); mc->mach_update_intr (mc); } static void net_s3c4510b_fini (struct device_desc *dev) { struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; free (dev->dev); free (io); } static void net_s3c4510b_reset (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; int i; io->bdmatxptr = 0xFFFFFFFF; io->bdmarxptr = 0xFFFFFFFF; } static void net_s3c4510b_update (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct net_device *net_dev = (struct net_device *) dev->dev; struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; if ((io->bdmarxcon & RxEn)) { struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; if(net_dev->net_wait_packet (net_dev, &tv) == 0) mac_read (dev); } } int net_s3c4510b_read_word (struct device_desc *dev, u32 addr, u32 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; int offset = (u16) (addr - dev->base + 0x9000); int ret = ADDR_HIT; //printf("%s:addr %x, %x\n", __FUNCTION__, addr, MACON); *data = 0; switch (offset) { case MACON: *data = io->macon; break; case CAMCON: *data = io->camcon; break; case MACTXCON: *data = io->mactxcon; break; case MACTXSTAT: *data = io->mactxstat; break; case MACRXCON: *data = io->macrxcon; break; case MACRXSTAT: *data = io->macrxstat; break; case STADATA: *data = io->stadata; break; case STACON: *data = io->stacon; break; case CAMEN: *data = io->camen; break; case BDMATXPTR: *data = io->bdmatxptr; break; case BDMARXPTR: *data = io->bdmarxptr; break; case BDMASTAT: *data = io->bdmastat; break; case BDMARXCON: *data = io->bdmarxcon; break; case BDMATXCON: *data = io->bdmatxcon; break; case BDMARXLSZ: *data = io->bdmarxlsz; break; default: break; } return ret; } int net_s3c4510b_write_word (struct device_desc *dev, u32 addr, u32 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; int offset = (u16) (addr - dev->base + 0x9000); int ret = ADDR_HIT; //printf("%s\n", __FUNCTION__); switch (offset) { case MACTXCON: if (data & TxEn == TxEn) { /* u32 addr; fault_t fault; fault = mac_write(dev); if( fault ) { mmu_data_abort(state, fault, addr); return; } */ mac_write (dev); } io->mactxcon = data; break; case BDMATXPTR: io->bdmatxptr = data; break; case BDMARXPTR: io->bdmarxptr = data; break; case BDMASTAT: io->bdmastat &= (~data); break; case MACON: io->macon = data; break; case MACRXCON: io->macrxcon = data; break; case BDMARXCON: io->bdmarxcon = data; break; case BDMATXCON: io->bdmatxcon = data; break; case BDMARXLSZ: io->bdmarxlsz = data; break; case CAMEN: io->camen = data; break; default: break; } return ret; } static int net_s3c4510b_setup (struct device_desc *dev) { int i; int enough = 0; struct net_s3c4510b_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = net_s3c4510b_fini; dev->reset = net_s3c4510b_reset; dev->update = net_s3c4510b_update; dev->read_word = net_s3c4510b_read_word; dev->write_word = net_s3c4510b_write_word; io = (struct net_s3c4510b_io *) malloc (sizeof (struct net_s3c4510b_io)); memset (io, 0, sizeof (struct net_s3c4510b_io)); if (io == NULL) return 1; dev->data = (void *) io; net_s3c4510b_reset (dev); /* see if we need to set default values. * */ set_device_default (dev, s3c4510b_net_def); for (i = 0; i < MAX_DEVICE_NUM; i++) { if (s3c4510b_devs[i] == NULL) { s3c4510b_devs[i] = dev; enough = 1; break; } } if (enough == 0) return 1; return 0; } void net_s3c4510b_init (struct device_module_set *mod_set) { int i; register_device_module ("s3c4510b", mod_set, &net_s3c4510b_setup); for (i = 0; i < MAX_DEVICE_NUM; i++) s3c4510b_devs[i] = NULL; } skyeye-1.2.5_REL/device/net/skyeye_net_tap_win32.c0000644000175000001440000003002710704350434020476 0ustar kshusers/* * TAP-Win32 -- A kernel driver to provide virtual tap device functionality * on Windows. Originally derived from the CIPE-Win32 * project by Damion K. Wilson, with extensive modifications by * James Yonan. * * All source code which derives from the CIPE-Win32 project is * Copyright (C) Damion K. Wilson, 2003, and is released under the * GPL version 2 (see below). * * All other source code is Copyright (C) James Yonan, 2003-2004, * and is released under the GPL version 2 (see below). * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program (see the file COPYING included with this * distribution); if not, write to the Free Software Foundation, Inc., * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* modified by Anthony Lee 2007.1.6 : for SkyEye to work on MinGW/CygWin */ #include "skyeye_net.h" #undef WORD #undef byte #include #include #include #include #include #define TAP_CONTROL_CODE(request,method) CTL_CODE(FILE_DEVICE_UNKNOWN, request, method, FILE_ANY_ACCESS) #define TAP_IOCTL_GET_MAC TAP_CONTROL_CODE(1, METHOD_BUFFERED) #define TAP_IOCTL_GET_VERSION TAP_CONTROL_CODE(2, METHOD_BUFFERED) #define TAP_IOCTL_GET_MTU TAP_CONTROL_CODE(3, METHOD_BUFFERED) #define TAP_IOCTL_GET_INFO TAP_CONTROL_CODE(4, METHOD_BUFFERED) #define TAP_IOCTL_CONFIG_POINT_TO_POINT TAP_CONTROL_CODE(5, METHOD_BUFFERED) #define TAP_IOCTL_SET_MEDIA_STATUS TAP_CONTROL_CODE(6, METHOD_BUFFERED) #define TAP_IOCTL_CONFIG_DHCP_MASQ TAP_CONTROL_CODE(7, METHOD_BUFFERED) #define TAP_IOCTL_GET_LOG_LINE TAP_CONTROL_CODE(8, METHOD_BUFFERED) #define TAP_IOCTL_CONFIG_DHCP_SET_OPT TAP_CONTROL_CODE(9, METHOD_BUFFERED) #define ADAPTER_KEY "SYSTEM\\CurrentControlSet\\Control\\Class\\{4D36E972-E325-11CE-BFC1-08002BE10318}" #define NETWORK_CONNECTIONS_KEY "SYSTEM\\CurrentControlSet\\Control\\Network\\{4D36E972-E325-11CE-BFC1-08002BE10318}" #define USERMODEDEVICEDIR "\\\\.\\Global\\" #define TAPSUFFIX ".tap" #define TAP_WIN32_MIN_MAJOR 7 #define TAP_WIN32_MIN_MINOR 1 #define TAP_BUFFER_SIZE 1560 #define printm(s...) fprintf(stderr, "[TAP-WIN32]: "s) typedef struct tap_win32 { HANDLE fHandle; HANDLE fEvent; unsigned char fBuffer[TAP_BUFFER_SIZE]; DWORD fBufferLen; CRITICAL_SECTION fLocker; BOOL fReading; OVERLAPPED fOverlapped; OVERLAPPED fOverlappedOut; } tap_win32; static void ShowErrorMsg(const char *prefix) { char errmsg[1024] = "\0"; if(prefix == NULL) prefix = ""; FormatMessage(FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS, NULL, GetLastError(), MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), errmsg, 1024, NULL); printm("%s --- %s\n", prefix, errmsg); } static int is_tap_win32_dev(const char *guid) { HKEY netcard_key; LONG status; DWORD len; int i, found = -1; char enum_name[256]; char unit_string[256]; HKEY unit_key; char component_id_string[] = "ComponentId"; char component_id[256]; char net_cfg_instance_id_string[] = "NetCfgInstanceId"; char net_cfg_instance_id[256]; DWORD data_type; if(RegOpenKeyEx(HKEY_LOCAL_MACHINE, ADAPTER_KEY, 0, KEY_READ, &netcard_key) != ERROR_SUCCESS) return -1; for(i = 0; found < 0; i++) { len = sizeof(enum_name); if(RegEnumKeyEx(netcard_key, i, enum_name, &len, NULL, NULL, NULL, NULL) != ERROR_SUCCESS) break; snprintf(unit_string, sizeof(unit_string), "%s\\%s", ADAPTER_KEY, enum_name); if(RegOpenKeyEx(HKEY_LOCAL_MACHINE, unit_string, 0, KEY_READ, &unit_key) != ERROR_SUCCESS) break; len = sizeof(component_id); if(RegQueryValueEx(unit_key, component_id_string, NULL, &data_type, component_id, &len) == ERROR_SUCCESS && data_type == REG_SZ) { len = sizeof(net_cfg_instance_id); if(RegQueryValueEx(unit_key, net_cfg_instance_id_string, NULL, &data_type, net_cfg_instance_id, &len) == ERROR_SUCCESS && data_type == REG_SZ) { if(strncmp(component_id, "tap", 3) == 0 && strcmp(net_cfg_instance_id, guid) == 0) found = i; } } RegCloseKey(unit_key); } RegCloseKey(netcard_key); return(found < 0 ? -1 : 0); } static int get_device_guid(char *name, int name_size, char *actual_name, int actual_name_size) { HKEY control_net_key; DWORD len; int i, found = -1; char enum_name[256]; char connection_string[256]; HKEY connection_key; char name_data[256]; DWORD name_type; const char name_string[] = "Name"; if(RegOpenKeyEx(HKEY_LOCAL_MACHINE, NETWORK_CONNECTIONS_KEY, 0, KEY_READ, &control_net_key) != ERROR_SUCCESS) { printm("Error opening registry key: %s\n", NETWORK_CONNECTIONS_KEY); return -1; } for(i = 0; found < 0; i++) { len = sizeof(enum_name); if(RegEnumKeyEx(control_net_key, i, enum_name, &len, NULL, NULL, NULL, NULL) != ERROR_SUCCESS) { printm("Error enumerating registry subkeys of key: %s\n", NETWORK_CONNECTIONS_KEY); break; } snprintf(connection_string, sizeof(connection_string), "%s\\%s\\Connection", NETWORK_CONNECTIONS_KEY, enum_name); if(RegOpenKeyEx(HKEY_LOCAL_MACHINE, connection_string, 0, KEY_READ, &connection_key) != ERROR_SUCCESS) continue; len = sizeof(name_data); if(!(RegQueryValueEx(connection_key, name_string, NULL, &name_type, (BYTE *)name_data, &len) != ERROR_SUCCESS || name_type != REG_SZ || is_tap_win32_dev(enum_name) != 0)) { printm("Found TAP device named '%s'\n", name_data); snprintf(name, name_size, "%s", enum_name); if(actual_name) snprintf(actual_name, actual_name_size, "\"%s\"", name_data); found = i; } RegCloseKey(connection_key); } RegCloseKey(control_net_key); return(found < 0 ? -1 : 0); } static int initDevice(struct net_device *net_dev) { char device_path[256]; char device_guid[0x100]; char device_name[1024]; ULONG tapVer[3]; ULONG len = 0; tap_win32 *dev = (net_dev ? (tap_win32*)(net_dev->priv) : NULL); if(dev == NULL) return -1; bzero(dev, sizeof(tap_win32)); if(get_device_guid(device_guid, sizeof(device_guid), device_name, sizeof(device_name)) != 0) { printm("ERROR: SkyEye requires a TAP-Win32 driver that is at least version %d.%d\n" "Please install from http://prdownloads.sourceforge.net/openvpn/openvpn-2.0_beta2-install.exe\n", TAP_WIN32_MIN_MAJOR, TAP_WIN32_MIN_MINOR); return -1; } if(GetVersion() < 0x80000000) { char hostip[16]; sprintf(hostip, "%d.%d.%d.%d", net_dev->hostip[0], net_dev->hostip[1], net_dev->hostip[2], net_dev->hostip[3]); if(_spawnlp(_P_DETACH, "netsh.exe", "netsh.exe", "interface", "ip", "set", "address", device_name, "static", hostip, "255.255.255.0", NULL) == -1) { printm("WARNING: Failed to Change IP Address/Mask.\n"); } } snprintf(device_path, sizeof(device_path), "%s%s%s", USERMODEDEVICEDIR, device_guid, TAPSUFFIX); dev->fHandle = CreateFile(device_path, GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_SYSTEM | FILE_FLAG_OVERLAPPED, NULL); if(dev->fHandle == INVALID_HANDLE_VALUE) { printm("Opening TAP connection failed\n"); return -1; } bzero(&tapVer[0], sizeof(tapVer)); if(!DeviceIoControl(dev->fHandle, TAP_IOCTL_GET_VERSION, &tapVer[0], sizeof(tapVer), &tapVer[0], sizeof(tapVer), &len, NULL)) { ShowErrorMsg("Could not get driver version info"); CloseHandle(dev->fHandle); return -1; } if(!(tapVer[0] > TAP_WIN32_MIN_MAJOR || (tapVer[0] == TAP_WIN32_MIN_MAJOR && tapVer[1] >= TAP_WIN32_MIN_MINOR))) { printm("ERROR: SkyEye requires a TAP-Win32 driver that is at least version %d.%d\n" "Please install an updated version from http://prdownloads.sourceforge.net/openvpn/openvpn-2.0_beta2-install.exe\n", TAP_WIN32_MIN_MAJOR, TAP_WIN32_MIN_MINOR); CloseHandle(dev->fHandle); return -1; } tapVer[0] = 1; if(!DeviceIoControl(dev->fHandle, TAP_IOCTL_SET_MEDIA_STATUS, &tapVer[0], sizeof(ULONG), &tapVer[0], sizeof(ULONG), &len, NULL)) { ShowErrorMsg("Setting Media Status to connected failed"); CloseHandle(dev->fHandle); return -1; } InitializeCriticalSection(&dev->fLocker); dev->fEvent = CreateEvent(NULL, TRUE, FALSE, NULL); return 0; } static int shutdownDevice(struct net_device *net_dev) { tap_win32 *dev = (net_dev ? (tap_win32*)(net_dev->priv) : NULL); if(dev == NULL) return -1; printm("Closing TAP-WIN32 handle.\n"); CloseHandle(dev->fHandle); CloseHandle(dev->fEvent); DeleteCriticalSection(&dev->fLocker); net_dev->priv = NULL; return 0; } static int recvPacket(tap_win32 *dev, void *buf, int size) { int retVal = 0; if(size < 0) return -1; EnterCriticalSection(&dev->fLocker); if(dev->fReading == FALSE) { if(dev->fBufferLen > (DWORD)size) { /* no partial packets. drop it. */ retVal = 0; } else if(dev->fBufferLen > 0) { memcpy(buf, &dev->fBuffer[0], (size_t)dev->fBufferLen); retVal = (int)dev->fBufferLen; } dev->fBufferLen = 0; } LeaveCriticalSection(&dev->fLocker); return retVal; } static void CALLBACK waitRecvPacket_callback(DWORD dwErrorCode, DWORD dwNumberOfBytesTransfered, LPOVERLAPPED lpOverlapped) { tap_win32 *dev = (tap_win32*)lpOverlapped->hEvent; if(dev == NULL) return; EnterCriticalSection(&dev->fLocker); dev->fReading = FALSE; dev->fBufferLen = (dwErrorCode == 0 ? dwNumberOfBytesTransfered : 0); SetEvent(dev->fEvent); LeaveCriticalSection(&dev->fLocker); } static int waitRecvPacket(tap_win32 *dev, struct timeval *tv) { int retVal = 0; DWORD status; EnterCriticalSection(&dev->fLocker); if(dev->fReading) { retVal = -1; } else if(dev->fBufferLen == 0) { retVal = -1; dev->fReading = TRUE; dev->fOverlapped.Internal = 0; dev->fOverlapped.InternalHigh = 0; dev->fOverlapped.Offset = 0; dev->fOverlapped.OffsetHigh = 0; dev->fOverlapped.hEvent = dev; ResetEvent(dev->fEvent); if(ReadFileEx(dev->fHandle, &dev->fBuffer[0], TAP_BUFFER_SIZE, &dev->fOverlapped, waitRecvPacket_callback) == 0) { ShowErrorMsg("ReadFileEx error"); dev->fReading = FALSE; retVal = -2; } } LeaveCriticalSection(&dev->fLocker); if(retVal == -1) { DWORD timeout = (tv == NULL ? INFINITE : (DWORD)(tv->tv_sec * 1000UL + tv->tv_usec / 1000UL)); while(TRUE) { status = WaitForSingleObjectEx(dev->fEvent, timeout, TRUE); if(status == WAIT_IO_COMPLETION && tv == NULL) continue; if(status == WAIT_OBJECT_0) retVal = 0; break; } } return retVal; } static int sendPacket(tap_win32 *dev, void *buf, int size) { DWORD written = 0; if(WriteFile(dev->fHandle, buf, (DWORD)size, &written, &dev->fOverlappedOut) == 0) { char errmsg[1024]; DWORD errCode = GetLastError(); snprintf(errmsg, sizeof(errmsg), "Sending of %d bytes failed (%u bytes sent)", size, written); ShowErrorMsg(errmsg); } return (int)written; } int tuntap_open(struct net_device *net_dev) { net_dev->priv = LocalAlloc(LMEM_ZEROINIT, sizeof(tap_win32)); if(initDevice(net_dev) != 0) { if(net_dev->priv) LocalFree(net_dev->priv); net_dev->priv = NULL; return -1; } return 0; } int tuntap_close(struct net_device *net_dev) { shutdownDevice(net_dev); if(net_dev->priv) LocalFree(net_dev->priv); net_dev->priv = NULL; return 0; } int tuntap_read(struct net_device *net_dev, void *buf, size_t count) { if(net_dev->priv == NULL) return -1; return recvPacket((tap_win32*)net_dev->priv, buf, count); } int tuntap_write(struct net_device *net_dev, void *buf, size_t count) { if(net_dev->priv == NULL) return -1; return sendPacket((tap_win32*)net_dev->priv, buf, count); } int tuntap_wait_packet(struct net_device *net_dev, struct timeval *tv) { if(net_dev->priv == NULL) return -1; return waitRecvPacket((tap_win32*)net_dev->priv, tv); } skyeye-1.2.5_REL/device/net/skyeye_net.h0000644000175000001440000000534110552270410016612 0ustar kshusers/* skyeye_net.h - skyeye general net device file support functions Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 04/27/2003 initial version * chenyu */ #ifndef __SKYEYE_NET_H_ #define __SKYEYE_NET_H_ #include #include "skyeye_device.h" #define NET_MOD_LINUX 0 #define NET_MOD_TUNTAP 1 #define NET_MOD_VNET 2 struct net_device { int net_fd; unsigned char macaddr[6]; unsigned char hostip[4]; int ethmod; /* private data */ void *priv; int (*net_open) (struct net_device * net_dev); int (*net_close) (struct net_device * net_dev); int (*net_read) (struct net_device * net_dev, void *buf, size_t count); int (*net_write) (struct net_device * net_dev, void *buf, size_t count); int (*net_wait_packet) (struct net_device * net_dev, struct timeval *tv); }; /* TUNTAP */ extern int tuntap_open (struct net_device *net_dev); extern int tuntap_close (struct net_device *net_dev); extern int tuntap_read (struct net_device *net_dev, void *buf, size_t count); extern int tuntap_write (struct net_device *net_dev, void *buf, size_t count); extern int tuntap_wait_packet (struct net_device *net_dev, struct timeval *tv); /* VNEt */ extern int vnet_open (struct net_device *net_dev); extern int vnet_close (struct net_device *net_dev); extern int vnet_read (struct net_device *net_dev, void *buf, size_t count); extern int vnet_write (struct net_device *net_dev, void *buf, size_t count); extern int vnet_wait_packet (struct net_device *net_dev, struct timeval *tv); /* ethernet controller initialize functions*/ extern void net_rtl8019_init (struct device_module_set *mod_set); extern void net_cs8900a_init (struct device_module_set *mod_set); extern void net_s3c4510b_init (struct device_module_set *mod_set); /* help function*/ extern inline int is_broadcast (char *mac); extern inline int is_nulladdr (char *mac); extern inline int is_multicast (char *mac); extern void print_packet (u8 * buf, int len); #endif /*__SKYEYE_NET_H_*/ skyeye-1.2.5_REL/device/net/skyeye_net.c0000644000175000001440000000740510577446117016630 0ustar kshusers/* skyeye_net.c - skyeye general net device file support functions Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 05/01/2005 initial version * walimis */ #include #include #include #include "armdefs.h" #include "skyeye_device.h" #include "skyeye_options.h" #include "skyeye.h" #include "skyeye_net.h" #define MAC_ADDR "\0skyey" static nic_num = 0; /* initialize the net module set. * If you want to add a new ethernet nic simulation, just add a "net_*_init" function to it. * */ static void net_init (struct device_module_set *mod_set) { net_rtl8019_init (mod_set); net_cs8900a_init (mod_set); net_s3c4510b_init (mod_set); } static int net_setup (struct device_desc *dev, void *option) { struct net_device *net_dev; struct net_option *net_opt = (struct net_option *) option; int ret = 0; net_dev = (struct net_device *) malloc (sizeof (struct net_device)); if (net_dev == NULL) return 1; memset (net_dev, 0, sizeof (struct net_device)); /* if we don't config mac addr in config file, we set it here. */ if (is_nulladdr (net_opt->macaddr)) { memcpy (net_dev->macaddr, MAC_ADDR, 6); net_dev->macaddr[5] += nic_num; nic_num++; } else { memcpy (net_dev->macaddr, net_opt->macaddr, 6); } memcpy (net_dev->hostip, net_opt->hostip, 4); net_dev->ethmod = net_opt->ethmod; switch (net_dev->ethmod) { case NET_MOD_TUNTAP: net_dev->net_open = tuntap_open; net_dev->net_close = tuntap_close; net_dev->net_read = tuntap_read; net_dev->net_write = tuntap_write; net_dev->net_wait_packet = tuntap_wait_packet; break; case NET_MOD_VNET: net_dev->net_open = vnet_open; net_dev->net_close = vnet_close; net_dev->net_read = vnet_read; net_dev->net_write = vnet_write; net_dev->net_wait_packet = vnet_wait_packet; break; } ret = net_dev->net_open (net_dev); dev->dev = (void *) net_dev; return ret; } static struct device_module_set net_mod_set = { .name = "net", .count = 0, .count_max = 0, .init = net_init, .initialized = 0, .setup_module = net_setup, }; /* used by global device initialize function. * */ void net_register () { if (register_device_module_set (&net_mod_set)) SKYEYE_ERR ("\"%s\" module set register error!\n", net_mod_set.name); } /* help functions. */ inline int is_broadcast (char *mac) { static unsigned char bcast_addr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; return (!memcmp (mac, bcast_addr, 6)); } inline int is_nulladdr (char *mac) { static unsigned char null_addr[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; return (!memcmp (mac, null_addr, 6)); } inline int is_multicast (char *mac) { return (mac[0] & 0x01); } void print_packet (u8 * buf, int len) { int i = 0, j = 0, k = 0; fprintf (stderr, "\n"); while (i < len) { if (buf[i] < 16) fprintf (stderr, "0%x", buf[i]); else fprintf (stderr, "%2x", buf[i]); k++; if (k >= 2) { fprintf (stderr, " "); k = 0; } i++; j++; if (j >= 16) { fprintf (stderr, "\n"); j = 0; } } fprintf (stderr, "\n\n"); } skyeye-1.2.5_REL/device/net/dev_net_s3c4510b.h0000644000175000001440000002030110541455476017313 0ustar kshusers/* dev_net_s3c4510b.h - skyeye S3C4510B ethernet controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/04/2005 modify to fit in dev_net_s3c4510b.c * walimis * * 09/05/2004 initial version * * telpro2003@yahoo.com.cn, * walimis * */ #ifndef __DEV_NET_S3C4510B_H_ #define __DEV_NET_S3C4510B_H_ #define RX_FRAME_SIZE 64 #define TX_FRAME_SIZE 16 struct frame_desc_struct { unsigned int frame_data_ptr; // [31] Ownership 0=CPU, 1=BDMA unsigned int reserved; unsigned int status_and_frame_length; // [31:16] Rx Status, [15:0] Frame Length unsigned int next_frame_desc; }; /* struct frame_buf_struct { unsigned char dst[ETH_ALEN]; unsigned char src[ETH_ALEN]; unsigned short proto; unsigned char data[ETH_DATA_LEN + 22]; }; */ /* ----------------------------------------- * * Definitions of Samsung 4510 MAC registers * * ----------------------------------------- */ #define MaxRxFrameSize (1520) /* -------------------------------------- * * Buffered DMA Transmit Control Register * * -------------------------------------- */ #define BTxBRST (0x0000F) /* [4:0] */ #define BTxSTSKO (0x00020) #define BTxCCPIE (0x00080) #define BTxNLIE (0x00100) #define BTxNOIE (0x00200) #define BTxEmpty (0x00400) //#define BTxMSL /* [13:11] */ #define BTxMSL000 (0x00000) #define BTxMSL001 (0x00800) #define BTxMSL010 (0x01000) #define BTxMSL011 (0x01800) #define BTxMSL100 (0x02000) #define BTxMSL101 (0x02800) #define BTxMSL110 (0x03000) #define BTxMSL111 (0x03800) #define BTxEn (0x04000) #define BTxRS (0x08000) /* ------------------------------------- * * Buffered DMA Receive Control Register * * ------------------------------------- */ #define BRxBRST (0x0000F) /* [4:0] */ #define BRxSTSKO (0x00020) #define BRxMAINC (0x00040) #define BRxDIE (0x00080) #define BRxNLIE (0x00100) #define BRxNOIE (0x00200) #define BRxMSOIE (0x00400) #define BRxLittle (0x00800) //#define BRxWA /* [13:12] */ #define BRxWA01 (0x01000) #define BRxWA10 (0x02000) #define BRxWA11 (0x03000) #define BRxEn (0x04000) #define BRxRS (0x08000) #define BRxEmpty (0x10000) #define BRxEarly (0x20000) /* -------------------- * * BDMA Status Register * * -------------------- */ #define S_BRxRDF (0x00001) #define S_BRxNL (0x00002) #define S_BRxNO (0x00004) #define S_BRxMSO (0x00008) #define S_BRxEmpty (0x00010) #define S_BRxSEarly (0x00020) #define S_BRxFRF (0x00080) #define S_BRxNFR (0x00080) #define S_BTxCCP (0x10000) #define S_BTxNL (0x20000) #define S_BTxNO (0x40000) #define S_BTxEmpty (0x100000) /* -------------------- * * MAC Control Register * * -------------------- */ #define HaltReq (0x00001) #define HaltImm (0x00002) #define Reset (0x00004) #define FullDup (0x00008) #define MACLoop (0x00010) #define MIIOFF (0x00040) #define Loop10 (0x00080) #define MissRoll (0x00400) #define MDCOFF (0x01000) #define EnMissRoll (0x02000) #define Link10 (0x08000) /* ----------------------------- * * MAC Transmit Control Register * * ----------------------------- */ #define TxEn (0x0001) #define TxHalt (0x0002) #define NoPad (0x0004) #define NoCRC (0x0008) #define FBack (0x0010) #define NoDef (0x0020) #define SdPause (0x0040) #define SQEn (0x0080) #define EnUnder (0x0100) #define EnDefer (0x0200) #define EnNCarr (0x0400) #define EnExColl (0x0800) #define EnLateColl (0x1000) #define EnTxPar (0x2000) #define EnComp (0x4000) /* ---------------------------- * * MAC Receive Control Register * * ---------------------------- */ #define RxEn (0x0001) #define RxHalt (0x0002) #define LongEn (0x0004) #define ShortEn (0x0008) #define StripCRC (0x0010) #define PassCtl (0x0020) #define IgnoreCRC (0x0040) //#define (0x0080) #define EnAlign (0x0100) #define EnCRCErr (0x0200) #define EnOver (0x0400) #define EnLongErr (0x0800) //#define (0x1000) #define EnRxPar (0x2000) #define EnGood (0x4000) /* -------------------- * * CAM Control Register * * -------------------- */ #define StationAcc (0x0001) #define GroupAcc (0x0002) #define BroadAcc (0x0004) #define NegCAM (0x0008) #define CompEn (0x0010) /* Tx & Rx Frame Descriptor Ownership bit[31](O) */ #define BDMA_owner 0x80000000 /* BDMA */ #define CPU_owner 0x7fffffff /* CPU */ /* ------------------------------- * * Tx Frame Descriptor Description * * ------------------------------- */ #define Padding (0x00) #define NoPadding (0x01) #define CRCMode (0x00) #define NoCRCMode (0x02) #define MACTxIntEn (0x04) #define MACTxIntDis (0x00) #define LittleEndian (0x08) #define BigEndian (0x00) #define FrameDataPtrInc (0x10) #define FrameDataPtrDec (0x00) #define WA00 (0x00) #define WA01 (0x20) #define WA10 (0x40) #define WA11 (0x60) /* --------- * * Tx Status * * --------- */ #define TxCollCntMask (0x000F) #define ExColl (0x0010) #define TxDefer (0x0020) #define Paused (0x0040) #define IntTx (0x0080) #define Under (0x0100) #define Defer (0x0200) #define NCarr (0x0400) #define SQErr (0x0800) #define LateColl (0x1000) #define TxPar (0x2000) #define Comp (0x4000) #define TxHalted (0x8000) /* --------- * * Rx Status * * --------- */ #define OvMax (0x0004) #define CtlRcv (0x0020) #define IntRx (0x0040) #define Rx10stat (0x0080) #define AlignErr (0x0100) #define CRCErr (0x0200) #define Overflow (0x0400) #define LongErr (0x0800) #define RxPar (0x2000) #define Good (0x4000) #define RxHalted (0x8000) /* ------------- * * MII Registers * * ------------- */ #define PHYHWADDR 0x3E0 #define MiiBusy (1<<11) #define PHYREGWRITE (1<<10) enum { gMACCON = FullDup, gMACTXCON = EnComp | TxEn, gMACRXCON = RxEn, gBDMATXCON = BTxBRST | BTxMSL110 | BTxSTSKO | BTxEn, gBDMARXCON = BRxDIE | BRxEn | BRxLittle | BRxMAINC | BRxBRST | BRxNLIE | BRxNOIE | BRxSTSKO | BRxWA10, gCAMCON = CompEn | BroadAcc }; /* *********************** */ /* Ethernet BDMA Registers */ /* *********************** */ #define BDMATXCON (0x9000) #define BDMARXCON (0x9004) #define BDMATXPTR (0x9008) #define BDMARXPTR (0x900C) #define BDMARXLSZ (0x9010) #define BDMASTAT (0x9014) #define CAMBASE (0x9100) /* * CAM 0x9100 ~ 0x917C * BDMATXBUF 0x9200 ~ 0x92FC * BDMARXBUF 0x9800 ~ 0x99FC */ /* ********************** */ /* Ethernet MAC Registers */ /* ********************** */ #define MACON (0xA000) #define CAMCON (0xA004) #define MACTXCON (0xA008) #define MACTXSTAT (0xA00C) #define MACRXCON (0xA010) #define MACRXSTAT (0xA014) #define STADATA (0xA018) #define STACON (0xA01C) #define CAMEN (0xA028) #define EMISSCNT (0xA03C) #define EPZCNT (0xA040) #define ERMPZCNT (0xA044) #define EXTSTAT (0x9040) /* walimis */ #define INT_S3C4510B_BDMATX 0 #define INT_S3C4510B_BDMARX 1 #define INT_S3C4510B_MACTX 2 #define INT_S3C4510B_MACRX 3 typedef struct net_s3c4510b_io { /*Ethernet BDMA Registers */ u32 bdmatxcon; u32 bdmarxcon; u32 bdmatxptr; u32 bdmarxptr; u32 bdmarxlsz; u32 bdmastat; u32 cam[32]; /*Ethernet MAC Registers */ u32 macon; u32 camcon; u32 mactxcon; u32 mactxstat; u32 macrxcon; u32 macrxstat; u32 stadata; u32 stacon; u32 camen; u32 emisscnt; u32 epzcnt; u32 ermpzcnt; u32 extstat; u8 mac_buf[4096]; int need_update; } net_s3c4510b_io_t; static u8 s3c4510b_output (struct device_desc *dev, u8 * buf, u16 packet_len); static void s3c4510b_input (struct device_desc *dev); #endif //_DEV_NET_S3C4510B_H_ skyeye-1.2.5_REL/device/net/if_vnet.h0000644000175000001440000001233210555732132016072 0ustar kshusers/* * Universal Virtual Net Switch device driver. * Copyright (C) 1999-2003 Chen Yu * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * $Id: if_vnet.h,v 1.3 2006/08/04 16:40:41 chenyu Exp $ */ #ifndef __IF_VNET_H #define __IF_VNET_H /* Uncomment to enable debugging */ /* #define VNET_DEBUG 1 */ #ifdef __KERNEL__ #define VNET_DEBUG #ifdef VNET_DEBUG #define DBG if(1)printk #define DBG1 if(1)printk #else #define DBG( a... ) #define DBG1( a... ) #endif #define VNET_MAJOR 11 #define VNET_MINOR 201 struct vnet_struct { char *name; unsigned int flags; int attached; uid_t owner; wait_queue_head_t read_wait; struct sk_buff_head readq; struct net_device dev; struct net_device_stats stats; struct fasync_struct *fasync; #ifdef VNET_DEBUG int debug; #endif }; #ifndef MIN #define MIN(a,b) ( (a)<(b) ? (a):(b) ) #endif #endif /* __KERNEL__ */ /* Read queue size */ #define VNET_READQ_SIZE 10 /* VNET device flags */ #define VNET_VNET_DEV 0x0001 #define VNET_TAP_DEV 0x0002 #define VNET_TYPE_MASK 0x000f #define VNET_FASYNC 0x0010 #define VNET_NOCHECKSUM 0x0020 #define VNET_NO_PI 0x0040 #define VNET_ONE_QUEUE 0x0080 #define VNET_PERSIST 0x0100 /* Ioctl defines */ #define VNETSETNOCSUM _IOW('T', 200, int) #define VNETSETDEBUG _IOW('T', 201, int) #define VNETSETIFF _IOW('T', 202, int) #define VNETSETPERSIST _IOW('T', 203, int) #define VNETSETOWNER _IOW('T', 204, int) #define VNETSHOWINFO _IOW('T', 205, int) #define VNETUNSETIFF _IOW('T', 206, int) /* VNETSETIFF ifr flags */ #define IFF_VNET 0x0001 #define IFF_TAP 0x0002 #define IFF_NO_PI 0x1000 #define IFF_ONE_QUEUE 0x2000 #define VNET_PKT_STRIP 0x0001 #define VNET_NUM_HUBS 8 #define NUM_NUTS_PER_HUB 32 #define VNET_MAX_NUT_NAME_LEN 16 #define VNET_MAX_QLEN 128 typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned uint32; typedef int int32; typedef char Bool; #define VNET_MAC_EQ(_a, _b) !memcmp((_a), (_b), ETH_ALEN) #define VNET_SKB_2_DESTMAC(_skb) (((struct ethhdr *)(_skb)->data)->h_dest) #define VNET_SKB_2_SRCMAC(_skb) (((struct ethhdr *)(_skb)->data)->h_source) #define VNET_UP_AND_RUNNING(_flags) (((_flags) & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) #define TRUE 1 #define FALSE 0 typedef enum { VNET_GUESTIF_NUT, VNET_HOSTIF_NUT, VNET_HUB_NUT } vnet_nuttype; typedef enum { VNET_HUB, VNET_SWITCH } vnet_hubtype; struct vnet_pi { unsigned short flags; unsigned short proto; }; #ifdef __KERNEL__ /* * The net is the basic mechanism for connecting to objects * that send packet between them. */ struct vnet_nut { struct vnet_nut *peer; vnet_nuttype type; //maybe guestif or hostif or hub int numbolts; char name[VNET_MAX_NUT_NAME_LEN]; int refCount; Bool connected; // could be a generic state variable if needed void *private; // private field for containing object int index; // private field for containing object struct proc_dir_entry *procEntry; // private field for containing object wait_queue_head_t waitQueue; // used to wait for other threads to release the jack void (*free) (struct vnet_nut * this); void (*rcv) (struct vnet_nut * this, struct sk_buff * skb); Bool (*cycleDetect) (struct vnet_nut * this, int generation); void (*boltsChanged) (struct vnet_nut * this); int (*isBridged) (struct vnet_nut * this); }; struct vnet_bolt { struct vnet_nut nut; // must be first unsigned id; uint32 flags; struct vnet_bolt *next; uint8 paddr[ETH_ALEN]; uint8 ladrf[8]; int (*fileOpRead) (struct vnet_bolt * this, struct file * filp, char *buf, size_t count); int (*fileOpWrite) (struct vnet_bolt * this, struct file * filp, const char *buf, size_t count); int (*fileOpIoctl) (struct vnet_bolt * this, struct file * filp, unsigned int iocmd, unsigned int ioarg); int (*fileOpSelect) (struct vnet_bolt * this, struct file * filp, poll_table * wait); }; struct vnet_hub { int num; vnet_hubtype type; //hub or switch struct vnet_nut nut[NUM_NUTS_PER_HUB]; int stats[NUM_NUTS_PER_HUB]; int totalbolts; int mygeneration; }; struct vnet_guestif_stats { unsigned read; unsigned written; unsigned queued; unsigned droppedDown; unsigned droppedMismatch; unsigned droppedOverflow; }; struct vnet_guestif { struct vnet_bolt bolt; struct sk_buff_head packetQueue; uint32 *pollPtr; struct page *pollPage; uint32 pollMask; uint32 clusterCount; wait_queue_head_t waitQueue; struct vnet_guestif_stats stats; }; struct vnet_hostif { struct vnet_bolt bolt; unsigned int flags; int attached; uid_t owner; wait_queue_head_t read_wait; struct sk_buff_head readq; struct net_device dev; //char devName[8]; struct net_device_stats stats; struct fasync_struct *fasync; }; #endif /*__KERNEL__*/ #endif /* __IF_VNET_H */ skyeye-1.2.5_REL/device/net/skyeye_net_tap_beos.c0000644000175000001440000001000710572524543020467 0ustar kshusers/* skyeye_net_tap_beos.c - tuntap net device file support functions on BeOS Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/31/2007 written by Anthony Lee */ /* * TODO: To be sure that just one process read/write the tap. */ #include #include #include #include #include "skyeye_net.h" #include "portable/beos/tap_driver/skyeye_tap.h" #define TAP_BEOS_DEBUG 0 #define PRINT(x...) printf("[TAP_BEOS]: " x) #if TAP_BEOS_DEBUG #define DEBUG(x...) printf("[TAP_BEOS]: " x) #else #define DEBUG(x...) (void)0 #endif typedef struct tap_beos { port_id rxPort; port_id txPort; } tap_beos; int tuntap_open(struct net_device *net_dev) { char buf[1024]; tap_beos *dev = (tap_beos*)malloc(sizeof(tap_beos)); net_dev->priv = NULL; if(dev == NULL) return -1; #if (B_BEOS_VERSION >= 0x510) /* on BONE, the if_name is same as device. */ snprintf(buf, sizeof(buf), "ifconfig %s %d.%d.%d.%d 255.255.255.0 up > /dev/null 2>&1", SKYEYE_TAP_DEVICE, net_dev->hostip[0], net_dev->hostip[1], net_dev->hostip[2], net_dev->hostip[3]); DEBUG("system(\"%s\")\n", buf); system(buf); snooze(1000000); #endif if((dev->rxPort = find_port(SKYEYE_TAP_RX_PORT_FOR_USER)) < 0 || (dev->txPort = find_port(SKYEYE_TAP_TX_PORT_FOR_USER)) < 0) { PRINT("\x1b[31m******************************************************************\x1b[0m\n"); PRINT("\x1b[31m*** You should install the skyeye_tap driver,\x1b[0m\n"); PRINT("\x1b[31m*** see \"utils/portable/beos/tap_driver/README\" for more detail.\x1b[0m\n"); PRINT("\x1b[31m******************************************************************\x1b[0m\n"); free(dev); return -1; } net_dev->priv = (void*)dev; return 0; } int tuntap_close(struct net_device *net_dev) { if(net_dev->priv != NULL) { free(net_dev->priv); net_dev->priv = NULL; } return 0; } int tuntap_read(struct net_device *net_dev, void *buf, size_t count) { tap_beos *dev = (tap_beos*)net_dev->priv; ssize_t nBytes = 0; int32 code; if(dev == NULL) return -1; nBytes = read_port_etc(dev->rxPort, &code, buf, count, B_TIMEOUT, 1000); if(nBytes < 0 || code != SKYEYE_TAP_PORT_MSG_CODE) nBytes = -1; #if TAP_BEOS_DEBUG if(nBytes > 0) { DEBUG("*********** READ ***********\n"); print_packet(buf, nBytes); DEBUG("*****************************\n"); } else { DEBUG("read failed(%d).\n", nBytes); } #endif return (int)nBytes; } int tuntap_write(struct net_device *net_dev, void *buf, size_t count) { tap_beos *dev = (tap_beos*)net_dev->priv; ssize_t nBytes = 0; if(dev == NULL) return -1; if(write_port_etc(dev->txPort, SKYEYE_TAP_PORT_MSG_CODE, buf, count, B_TIMEOUT, 1000) == B_OK) nBytes = (ssize_t)count; #if TAP_BEOS_DEBUG if(nBytes > 0) { DEBUG("*********** WRITE ***********\n"); print_packet(buf, nBytes); DEBUG("*****************************\n"); } else { DEBUG("write failed(%d).\n", nBytes); } #endif return (int)nBytes; } int tuntap_wait_packet(struct net_device *net_dev, struct timeval *tv) { tap_beos *dev = (tap_beos*)net_dev->priv; bigtime_t timeout = (tv == NULL ? B_INFINITE_TIMEOUT : (bigtime_t)tv->tv_sec * (bigtime_t)1000000UL + (bigtime_t)tv->tv_usec); if(dev == NULL) return -1; if(port_buffer_size_etc(dev->rxPort, B_TIMEOUT, timeout) >= 0) return 0; return -1; } skyeye-1.2.5_REL/device/net/dev_net_rtl8019.c0000644000175000001440000005464510665426010017274 0ustar kshusers/* dev_net_rtl8019.c - skyeye realtek 8019 ethernet controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 04/01/2007 added 16-bits mode. * Anthony Lee * 03/19/2007 fixed writing CR directly when page over 2, * fixed for running on Windows, * replaced the codes based on sigaction with portable function. * Anthony Lee * 05/25/2005 modified for rtl8019 * walimis * 04/27/2003 add net option support * chenyu * 02/25/2003 initial version * yangye */ #include "armdefs.h" #include "skyeye_device.h" #include "dev_net_rtl8019.h" #include "portable/gettimeofday.h" //if you don't want to the debug info,just commit below two line //#define DEBUG 1 #undef DEBUG #if DEBUG #define DBG_PRINT(a...) fprintf(stderr, ##a) #else #define DBG_PRINT(a...) #endif static struct device_default_value rtl8019_net_def[] = { /* name base size interrupt array */ {"at91", 0xfffa0000, 0xff, {16, 0, 0, 0}}, {"s3c44b0x", 0x06000000, 0xff, {22, 0, 0, 0}}, {NULL}, }; #define MAX_DEVICE_NUM 10 static struct device_desc *rtl8019_devs[MAX_DEVICE_NUM]; static struct timeval eth_timeout[MAX_DEVICE_NUM]; static int eth_timeout_flags[MAX_DEVICE_NUM] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; #define TIMEVAL_ADD_USEC(tv, usec) \ do { \ tv.tv_sec += ((tv.tv_usec + usec) / (1000000UL)); \ tv.tv_usec = ((tv.tv_usec + usec) % (1000000UL)); \ } while (0) #define TIMEVAL_CMP(tv1, tv2) \ (memcmp(&tv1, &tv2, sizeof(struct timeval)) == 0 ? \ 0 : ( \ tv1.tv_sec < tv2.tv_sec ? -1 : ( \ (tv1.tv_sec == tv2.tv_sec && tv1.tv_usec < tv2.tv_usec) ? -1 : 1 \ ))) static void set_time(int index, int packets) { eth_timeout_flags[index] = 0; if (packets <= 0) return; if (gettimeofday(ð_timeout[index], NULL) != 0) return; #if 0 TIMEVAL_ADD_USEC(eth_timeout[index], (unsigned int)packets * 100UL); #else /* * NOTE by Stano: * In 10 ms - no reason to wait 1 second for a big packet * * NOTE by Lee: * Though the timeout just for generating interrupt, * but please increase the timeout microseconds to decrease * the loading of CPU when connecting to an external network. */ TIMEVAL_ADD_USEC(eth_timeout[index], 10000UL); #endif eth_timeout_flags[index] = 1; } static inline void net_rtl8019_set_update_intr (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct machine_config *mc = (struct machine_config *) dev->mach; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; mc->mach_set_intr (intr->interrupts[INT_RTL8019]); mc->mach_update_intr (mc); } static void send_interrupt(int index) { struct device_desc *dev; if ((dev = rtl8019_devs[index]) != NULL) { struct net_device *net_dev = (struct net_device *) dev->dev; struct machine_config *mc = (struct machine_config *) dev->mach; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; if ((io->need_update) && (io->IMR & io->ISR)) { net_rtl8019_set_update_intr(dev); io->need_update = 0; set_time(index, 0); } } } static void check_timeout(int index) { struct timeval tv; if (!eth_timeout_flags[index]) return; if (gettimeofday(&tv, NULL) != 0) return; if (TIMEVAL_CMP(tv, eth_timeout[index]) < 1) return; send_interrupt(index); eth_timeout_flags[index] = 0; } static void write_cr (struct device_desc *dev, u8 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; u8 startpage; u16 packet_len; u16 rtl8019_len; DBG_PRINT ("write_cr begin: data 0x%x\n", data); // Validate remote-DMA (RD2,RD1,RD0 not allowed to be 000) if (((data & 0x38) == 0x00)) { //wrong command DBG_PRINT ("write_cr: wrong command\n"); return; } // XMIT command if (data & CMD_XMIT) { DBG_PRINT ("write_cr: xmit command\n"); startpage = (io->TPSR - START_PAGE); //tpsr - 0x40 packet_len = (((u16) io->TBCR1 << 8) | (io->TBCR0)); packet_len &= 0xffff; io->TSR = 0; if (!rtl8019_output (dev, (io->sram + startpage * PAGE_SIZE), packet_len)) { io->TSR |= TSR_PTX; } else { io->TSR |= TSR_COL; } /**** send a interrupt to CPU here! ****/ io->ISR |= ISR_PTX; set_time (io->index, packet_len); io->need_update = 1; //net_rtl8019_set_update_intr(dev); } //remote dma write if ((data & CMD_READ) && (data & CMD_RUN)) { rtl8019_len = (((u16) io->RBCR1 << 8) | io->RBCR0); io->remote_read_offset = (u16) (io->RSAR1 << 8 | io->RSAR0) - (u16) (START_PAGE * PAGE_SIZE); io->remote_read_offset &= 0xffff; io->remote_read_count = rtl8019_len; //printf("io->remote_read_count:%d,io->remote_read_offset:%x\n", io->remote_read_count, io->remote_read_offset); } //remote dma write if ((data & CMD_WRITE) && (data & CMD_RUN) && ((data & CMD_NODMA) == 0)) { io->remote_write_offset = (io->RSAR1 << 8 | io->RSAR0) - START_PAGE * PAGE_SIZE; io->remote_write_count = (((u16) io->RBCR1 << 8) | io->RBCR0); io->remote_write_count &= 0xffff; //printf("rtl8019 rw:count:%d,offset:%x\n", io->remote_write_count, io->remote_write_offset); } io->CR = data; DBG_PRINT ("write_cr: end\n"); } static void remote_write_word (struct device_desc *dev, u16 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; DBG_PRINT ("remote_write begin: data 0x%x\n", data); if (io->CR & CMD_WRITE) { //in remote write mode if (io->remote_write_offset + 1 >= PAGE_NUM * PAGE_SIZE) { io->ISR |= ISR_OVW; if ((ISR_OVW & io->IMR)) { net_rtl8019_set_update_intr (dev); } DBG_PRINT ("%s: write data overflow!\n", __FUNCTION__); return; } io->sram[io->remote_write_offset] = data & 0xff; io->sram[io->remote_write_offset + 1] = data >> 8; io->remote_write_offset += 2; io->remote_write_count -= 2; if (io->remote_write_count <= 0) { io->CR &= (~CMD_WRITE); //clear dma command in CR io->CR |= CMD_NODMA; io->ISR |= ISR_RDC; // remote write finished int if ((ISR_RDC & io->IMR)) { net_rtl8019_set_update_intr (dev); } } DBG_PRINT ("remote write end\n"); return; } } static void remote_write_byte (struct device_desc *dev, u8 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; DBG_PRINT ("remote_write begin: data 0x%x\n", data); if (io->CR & CMD_WRITE) { //in remote write mode if (io->remote_write_offset >= PAGE_NUM * PAGE_SIZE) { io->ISR |= ISR_OVW; if ((ISR_OVW & io->IMR)) { net_rtl8019_set_update_intr (dev); } DBG_PRINT ("%s: write data overflow!\n", __FUNCTION__); return; } io->sram[io->remote_write_offset] = data; io->remote_write_offset++; io->remote_write_count--; if (io->remote_write_count == 0) { io->CR &= (~CMD_WRITE); //clear dma command in CR io->CR |= CMD_NODMA; io->ISR |= ISR_RDC; // remote write finished int if ((ISR_RDC & io->IMR)) { net_rtl8019_set_update_intr (dev); } } DBG_PRINT ("remote write end\n"); return; } } static u16 remote_read_halfword (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; u16 data; DBG_PRINT ("remote read begin\n"); if (io->CR & CMD_READ) { data = io->sram[io->remote_read_offset]; data |= io->sram[io->remote_read_offset + 1] << 8; io->remote_read_offset += 2; io->remote_read_count -= 2; if (io->remote_read_count <= 0) { io->CR &= (~CMD_READ); io->CR |= CMD_NODMA; io->ISR |= ISR_RDC; if ((ISR_RDC & io->IMR)) { net_rtl8019_set_update_intr (dev); } } DBG_PRINT ("remote read end:data %d\n", data); return data; } return 0; } static u8 remote_read_byte (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; u8 data; DBG_PRINT ("remote read begin\n"); if (io->CR & CMD_READ) { data = io->sram[io->remote_read_offset]; io->remote_read_offset++; if (--io->remote_read_count == 0) { io->CR &= (~CMD_READ); io->CR |= CMD_NODMA; io->ISR |= ISR_RDC; if ((ISR_RDC & io->IMR)) { net_rtl8019_set_update_intr (dev); } } DBG_PRINT ("remote read end:data %d\n", data); return data; } return 0; } static void net_rtl8019_fini (struct device_desc *dev) { struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; free (dev->dev); free (io); } static void net_rtl8019_reset (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; /*init PROM */ io->PROM[0] = (u8) net_dev->macaddr[0]; //MACADDR0; io->PROM[1] = (u8) net_dev->macaddr[0]; //MACADDR0; io->PROM[2] = (u8) net_dev->macaddr[1]; //MACADDR1; io->PROM[3] = (u8) net_dev->macaddr[1]; //MACADDR1; io->PROM[4] = (u8) net_dev->macaddr[2]; //MACADDR2; io->PROM[5] = (u8) net_dev->macaddr[2]; //MACADDR2; io->PROM[6] = (u8) net_dev->macaddr[3]; //MACADDR3; io->PROM[7] = (u8) net_dev->macaddr[3]; //MACADDR3; io->PROM[8] = (u8) net_dev->macaddr[4]; //MACADDR4; io->PROM[9] = (u8) net_dev->macaddr[4]; //MACADDR4; io->PROM[10] = (u8) net_dev->macaddr[5]; //MACADDR5; io->PROM[11] = (u8) net_dev->macaddr[5]; //MACADDR5; io->PAR0 = io->PROM[0]; io->PAR1 = io->PROM[2]; io->PAR2 = io->PROM[4]; io->PAR3 = io->PROM[6]; io->PAR4 = io->PROM[8]; io->PAR5 = io->PROM[10]; //init Registers io->CR = 0x21; //nic Stopped io->PSTART = 0; io->PSTOP = 0; io->BNRY = 0; io->TPSR = 0; io->TBCR0 = 0; io->TBCR1 = 0; io->ISR = 0; io->RSAR0 = 0; io->RSAR1 = 0; io->RBCR0 = 0; io->RBCR1 = 0; io->RCR = 0; io->TCR = 0; io->DCR = 0x84; //set long addr bit io->IMR = 0; io->CURR = 0; /* raise reset interrupt */ io->ISR = io->ISR | ISR_RST; /* init nic RAM */ if (io->sram != NULL) { memset (io->sram, 0, PAGE_NUM * PAGE_SIZE); } else { io->sram = (u8 *) malloc (PAGE_NUM * PAGE_SIZE); } io->remote_read_offset = 0; io->remote_write_offset = 0; io->remote_read_count = 0; io->remote_write_count = 0; io->need_update = 0; } static void net_rtl8019_update (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; #if 0 /* disabled: ISR_OVW instead of this */ if ((!mc->mach_pending_intr (intr->interrupts[INT_RTL8019]))) #else if (!(io->ISR & ISR_OVW)) #endif if(net_dev->net_wait_packet (net_dev, &tv) == 0) rtl8019_input (dev); check_timeout(io->index); } static int net_rtl8019_read_halfword (struct device_desc *dev, u32 addr, u16 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; int offset = (u8) (addr - dev->base); int ret = ADDR_HIT; offset >>= io->op_16; //DBG_PRINT("nic read begin: offset %x, io->ISR %x\n",offset,io->ISR); if (offset == 0x10) { //remote read if (io->DCR & 0x1) { *data = remote_read_halfword (dev); } } return ret; } static int net_rtl8019_read_byte (struct device_desc *dev, u32 addr, u8 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; int offset = (u8) (addr - dev->base); int ret = ADDR_HIT; offset >>= io->op_16; DBG_PRINT ("nic read begin: offset %x, io->ISR %x\n", offset, io->ISR); *data = 0; if (offset == 0x10) { //remote read /* FIXME: don't use DCR here. */ *data = remote_read_byte (dev); return ret; } if (offset == 0x1f) { //reset net_rtl8019_reset (dev); return ret; } if ((io->CR >> 6) == 0) { //read page0 switch (offset) { case 0x00: //CR *data = io->CR; break; case 0x03: //BNRY *data = io->BNRY; break; case 0x04: // ISR *data = io->TSR; break; case 0x07: // ISR *data = io->ISR; break; case 0x0c: // ISR *data = io->RSR; break; case 0x0d: // ISR io->CNTR0 = 0; *data = io->CNTR0; break; } } //end if page0 if ((io->CR >> 6) == 1) { //read page1 switch (offset) { case 0x00: //CR *data = io->CR;; break; case 0x01: //PAR0 - PAR5 ,MAC addr *data = io->PAR0; break; case 0x02: *data = io->PAR1; break; case 0x03: *data = io->PAR2; break; case 0x04: *data = io->PAR3; break; case 0x05: *data = io->PAR4; break; case 0x06: *data = io->PAR5; break; case 0x07: //CURR *data = io->CURR; break; } } //end if PAGE1 if ((io->CR >> 6) == 2) { //read page2 switch (offset) { case 0x00: //CR *data = io->CR; break; case 0x01: //PSTART *data = io->PSTART; break; case 0x02: //PSTOP *data = io->PSTOP; break; case 0x04: //TPSR *data = io->TPSR; break; case 0x0C: //RCR *data = io->RCR; break; case 0x0D: //TCR *data = io->TCR; break; case 0x0E: //DCR *data = io->DCR; break; case 0x0F: //IMR *data = io->IMR; break; } } //end if page2 return ret; } static int net_rtl8019_write_halfword (struct device_desc *dev, u32 addr, u16 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; int offset = (u8) (addr - dev->base); int ret = ADDR_HIT; offset >>= io->op_16; if (offset == 0x10) { //remote write if (io->DCR & 0x1) { remote_write_word (dev, (u16) data); } } return ret; //DBG_PRINT("nic write begin: offset %x, data %x\n",offset,data); } //offset should be 00-0f, 10 or 1f static int net_rtl8019_write_byte (struct device_desc *dev, u32 addr, u8 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; int offset = (u8) (addr - dev->base); int ret = ADDR_HIT; offset >>= io->op_16; if (offset == 0x10) { //remote write /* FIXME: don't use DCR here. */ //if (io->DCR & 0x2) { remote_write_byte (dev, (u8) data); //} return ret; } if (offset == 0x1f) { //reset net_rtl8019_reset (dev); return ret; } if (offset == 0x00) { // 2007-03-14 by Anthony Lee : here we should set the CR directly. write_cr (dev, data); return ret; } if ((io->CR >> 6) == 0) { //write page0 switch (offset) { #if 0 case 0x00: //CR write_cr (dev, data); break; #endif case 0x01: //PSTART io->PSTART = data; break; case 0x02: //PSTOP io->PSTOP = data; break; case 0x03: //BNRY io->BNRY = data; break; case 0x04: //TPSR io->TPSR = data; break; case 0x05: //TBCR0 io->TBCR0 = data; break; case 0x06: //TBCR1 io->TBCR1 = data; break; case 0x07: //ISR (write means clear) io->ISR = (io->ISR & (~data)); /* if (io->IMR & io->ISR) { } */ //UNSET_NET_INT (); break; case 0x08: //RSAR0 io->RSAR0 = data; break; case 0x09: //RSAR1 io->RSAR1 = data; break; case 0x0a: //RBCR0 io->RBCR0 = data; break; case 0x0b: //RBCR1 io->RBCR1 = data; break; case 0x0c: //RCR io->RCR = data; break; case 0x0d: //TCR io->TCR = data; break; case 0x0e: //DCR io->DCR = data; break; case 0x0f: //IMR //printf("IMR:%x -> %x. ISR:%x\n", io->IMR, data, io->ISR); io->IMR = data; /* if (io->IMR & io->ISR) { net_rtl8019_set_update_intr(dev); } */ break; } return ret; } //end if page0 if ((io->CR >> 6) == 1) { //write page1 switch (offset) { #if 0 case 0x00: //CR write_cr (dev, data); break; #endif case 0x01: //PAR0 - PAR5 ,MAC addr io->PAR0 = data; break; case 0x02: io->PAR1 = data; break; case 0x03: io->PAR2 = data; break; case 0x04: io->PAR3 = data; break; case 0x05: io->PAR4 = data; break; case 0x06: io->PAR5 = data; break; case 0x07: //CURR io->CURR = data; break; } return ret; } //end if page1 #if 0 //yangye 2003-1-21 //add write page2 ,only CR if ((io->CR >> 6) == 2) { //write page2 if (offset == 0x00) { write_cr (dev, data); return ret; } } //end if page2 #endif DBG_PRINT ("error write page or error write register\n"); return ret; } static void rtl8019_input (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; int packet_len, rtl8019_len; u8 buf[1600]; u8 frame_header[4]; u8 *bufptr; u8 *sramptr; u16 i, j, len; u32 free_pages, occupy_pages, next_page; if ((io->CR & CMD_STOP) || (io->TCR & TCR_LOOP_EXT)) { return; } if (io->CURR < io->BNRY) { free_pages = io->BNRY - io->CURR; } else { free_pages = (io->PSTOP - io->PSTART) - (io->CURR - io->BNRY); } packet_len = net_dev->net_read (net_dev, buf, sizeof (buf)); if (packet_len < 0) return; /* if packet_len < 60, pad zero to 60 bytes length. */ if (packet_len < 60) { memset (buf + packet_len, 0, 60 - packet_len); packet_len = 60; } rtl8019_len = packet_len + 4; occupy_pages = (rtl8019_len + 255) / PAGE_SIZE; /* check if we have available space to receive packet */ if (occupy_pages > free_pages) { io->ISR |= ISR_OVW; if ((ISR_OVW & io->IMR)) { net_rtl8019_set_update_intr (dev); } DBG_PRINT ("%s: read data overflow!\n", __FUNCTION__); return; } next_page = io->CURR + occupy_pages; if (next_page >= io->PSTOP) { next_page -= io->PSTOP - io->PSTART; } //add 8019 frame header frame_header[0] = RSR_RXOK; frame_header[1] = next_page; frame_header[2] = (rtl8019_len & 0xFF); //low 8 bit frame_header[3] = (rtl8019_len >> 8); //high 8 bit /* check if we are in in promiscuous mode */ /** * The tuntap does sometimes match the multicast address and * we _want_ to get broadcasts. Ignore this all and play * promisc. */ #if 0 if (!(io->RCR & RCR_PRO)) { /* not in promiscuous mode */ if (!is_broadcast (buf)) { DBG_PRINT (" destination address is a broadcast address!!!\n"); if (!(io->RCR & RCR_AB)) { /* reject broadcast destination address */ return; } } else if (is_multicast (buf)) { DBG_PRINT ("destination address is a multicast address!!!\n"); if (!(io->RCR & RCR_AM)) { /* reject multicast destination address */ return; } } else if ((io->PAR0 != buf[0]) || (io->PAR1 != buf[1]) || (io->PAR2 != buf[2]) || (io->PAR3 != buf[3]) || (io->PAR4 != buf[4]) || (io->PAR5 != buf[5])) { return; } } #endif sramptr = &io->sram[(io->CURR - START_PAGE) * PAGE_SIZE]; if (next_page > io->CURR || ((io->CURR + occupy_pages) == io->PSTOP)) { memcpy (sramptr, frame_header, 4); memcpy (sramptr + 4, buf, packet_len); } else { int copy_bytes = (io->PSTOP - io->CURR) * PAGE_SIZE; memcpy (sramptr, frame_header, 4); memcpy (sramptr + 4, buf, copy_bytes - 4); sramptr = &io->sram[(io->PSTART - START_PAGE) * PAGE_SIZE]; memcpy (sramptr, (void *) (buf + copy_bytes - 4), (packet_len - copy_bytes + 4)); } io->CURR = next_page; io->RSR |= RSR_RXOK; #if 0 fprintf(stderr, "\n----(%s)(packet_len:%d)----", __FUNCTION__, packet_len); print_packet (sramptr + 4, packet_len); #endif /*** send CPU a rx interrupt here! *****/ io->ISR |= ISR_PRX; //got packet int if ((ISR_PRX & io->IMR)) { //printf ("+++%s: raise RX interrupt, ISR:%x, IMR:%x\n", __FUNCTION__, io->ISR, io->IMR); set_time (io->index, rtl8019_len); io->need_update = 1; net_rtl8019_set_update_intr (dev); } } static u8 rtl8019_output (struct device_desc *dev, u8 * buf, u16 packet_len) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_rtl8019_io *io = (struct net_rtl8019_io *) dev->data; int len; if (io->CR & CMD_STOP) { //nic in stop mode return 0; } #if 0 fprintf(stderr, "\n----(%s)(packet_len:%d)----", __FUNCTION__, packet_len); print_packet (buf, packet_len); #endif if ((len = net_dev->net_write (net_dev, buf, packet_len)) == -1) { fprintf (stderr, "write to tapif error in skyeye-ne2k.c\n"); return -1; } //printf ("+++%s: trans\n", __FUNCTION__); return 0; } static int net_rtl8019_setup(struct device_desc *dev) { int i; int enough = 0; struct net_rtl8019_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = net_rtl8019_fini; dev->reset = net_rtl8019_reset; dev->update = net_rtl8019_update; dev->read_byte = net_rtl8019_read_byte; dev->write_byte = net_rtl8019_write_byte; dev->read_halfword = net_rtl8019_read_halfword; dev->write_halfword = net_rtl8019_write_halfword; io = (struct net_rtl8019_io*)malloc(sizeof(struct net_rtl8019_io)); if (io == NULL) return 1; memset(io, 0, sizeof (struct net_rtl8019_io)); dev->data = (void*)io; net_rtl8019_reset(dev); /* see if we need to set default values. */ set_device_default(dev, rtl8019_net_def); for (i = 0; i < MAX_DEVICE_NUM; i++) { if (rtl8019_devs[i] == NULL) { rtl8019_devs[i] = dev; io->index = i; enough = 1; break; } } if (enough == 0) return 1; return 0; } static int net_rtl8019_8bits_setup(struct device_desc *dev) { int ret = net_rtl8019_setup(dev); if (ret != 0) return ret; ((struct net_rtl8019_io*)dev->data)->op_16 = 8; return 0; } static int net_rtl8019_16bits_setup(struct device_desc *dev) { int ret = net_rtl8019_setup(dev); if (ret != 0) return ret; ((struct net_rtl8019_io*)dev->data)->op_16 = 1; return 0; } void net_rtl8019_init (struct device_module_set *mod_set) { int i; register_device_module("rtl8019", mod_set, &net_rtl8019_setup); register_device_module("rtl8019_8", mod_set, &net_rtl8019_8bits_setup); register_device_module("rtl8019_16", mod_set, &net_rtl8019_16bits_setup); for (i = 0; i < MAX_DEVICE_NUM; i++) rtl8019_devs[i] = NULL; } skyeye-1.2.5_REL/device/net/dev_net_cs8900a.c0000644000175000001440000003604310750371246017235 0ustar kshusers/* dev_net_cs8900a.c - skyeye Cirrus Logic CS8900A ethernet controllor simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/19/2007 replaced the codes based on sigaction with portable function. * Anthony Lee * 06/04/2005 initial verion for cs8900a * walimis */ #include "armdefs.h" #include "skyeye_device.h" #include "dev_net_cs8900a.h" #include "portable/gettimeofday.h" static struct device_default_value cs8900a_net_def[] = { /* name base size interrupt array */ {"at91", 0xfffa0000, 0x20, {16, 0, 0, 0}}, {"s3c2410x", 0x19000300, 0x20, {9, 0, 0, 0}}, {NULL}, }; #define MAX_DEVICE_NUM 10 static struct device_desc *cs8900a_devs[MAX_DEVICE_NUM]; static struct timeval eth_timeout[MAX_DEVICE_NUM]; static int eth_timeout_flags[MAX_DEVICE_NUM] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static void net_cs8900a_reset (struct device_desc *dev); #define TIMEVAL_ADD_USEC(tv, usec) \ do { \ tv.tv_sec += ((tv.tv_usec + usec) / (1000000UL)); \ tv.tv_usec = ((tv.tv_usec + usec) % (1000000UL)); \ } while (0) #define TIMEVAL_CMP(tv1, tv2) \ (memcmp(&tv1, &tv2, sizeof(struct timeval)) == 0 ? \ 0 : ( \ tv1.tv_sec < tv2.tv_sec ? -1 : ( \ (tv1.tv_sec == tv2.tv_sec && tv1.tv_usec < tv2.tv_usec) ? -1 : 1 \ ))) static void set_time(int index, int packets) { eth_timeout_flags[index] = 0; if (packets <= 0) return; if (gettimeofday(ð_timeout[index], NULL) != 0) return; #if 0 TIMEVAL_ADD_USEC(eth_timeout[index], (unsigned int)packets * 100UL); #else /* * NOTE by Stano: * In 10 ms - no reason to wait 1 second for a big packet * * NOTE by Lee: * Though the timeout just for generating interrupt, * but please increase the timeout microseconds to decrease * the loading of CPU when connecting to an external network. */ TIMEVAL_ADD_USEC(eth_timeout[index], 10000UL); #endif eth_timeout_flags[index] = 1; } void net_cs8900a_set_update_intr (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct machine_config *mc = (struct machine_config *) dev->mach; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; mc->mach_set_intr (intr->interrupts[INT_CS8900A]); mc->mach_update_intr (mc); } static void send_interrupt(int index) { struct device_desc *dev; if ((dev = cs8900a_devs[index]) != NULL) { struct net_device *net_dev = (struct net_device *) dev->dev; struct machine_config *mc = (struct machine_config *) dev->mach; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; if ((io->need_update)) { /* only update once. */ net_cs8900a_set_update_intr (dev); io->need_update = 0; set_time (index, 0); } } } static void check_timeout(int index) { struct timeval tv; if (!eth_timeout_flags[index]) return; if (gettimeofday(&tv, NULL) != 0) return; if (TIMEVAL_CMP(tv, eth_timeout[index]) < 1) return; send_interrupt(index); eth_timeout_flags[index] = 0; } /* ISQ read*/ static void isq_read (struct device_desc *dev, u16 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; io->ctrl_st[CtrlStNum (PP_ISQ)] = 0x0; if (io->ctrl_st[CtrlStNum (PP_RxEvent)] & 0xffc0) { io->ctrl_st[CtrlStNum (PP_ISQ)] = io->ctrl_st[CtrlStNum (PP_RxEvent)]; //io->ctrl_st[CtrlStNum (PP_RxEvent)] &= 0x3f; } else if (io->ctrl_st[CtrlStNum (PP_TxEvent)] & 0xffc0) { io->ctrl_st[CtrlStNum (PP_ISQ)] = io->ctrl_st[CtrlStNum (PP_TxEvent)]; io->ctrl_st[CtrlStNum (PP_TxEvent)] &= 0x3f; } *data = io->ctrl_st[CtrlStNum (PP_ISQ)]; } static void frame_write (struct device_desc *dev, u16 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; io->tx_frame[io->tx_tail] = data; io->tx_tail++; if ((io->tx_tail * 2) >= io->tx_length) { cs8900a_output (dev, (u8 *) io->tx_frame, (io->tx_tail * 2)); io->tx_tail = 0; } } static void frame_read (struct device_desc *dev, u16 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; if (io->rx_tail > io->rx_head) { io->rx_head = io->rx_tail = 0; return; } *data = io->rx_frame[io->rx_tail]; if (io->rx_tail==io->rx_head) { io->ctrl_st[CtrlStNum (PP_RxEvent)] &= ~0x100; } io->rx_tail++; } static void eeprom_reset (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; u8 offset, checksum = 0, *buf; u16 eeprom_val[17] = { 0xa120, 0x2020, 0x0300, 0x0003, 0x0001, 0x502c, 0xe000, 0x000f, 0x0, 0xd, 0xc000, 0xf, 0x2158, 0x0010, 0x0, 0x0, 0x2800 }; /* set eeprom mac address */ eeprom_val[13] = net_dev->macaddr[0] | (net_dev->macaddr[1] << 8); eeprom_val[14] = net_dev->macaddr[2] | (net_dev->macaddr[3] << 8); eeprom_val[15] = net_dev->macaddr[4] | (net_dev->macaddr[5] << 8); /* re-compute checksum. */ buf = (u8 *) eeprom_val; for (offset = 0; offset < (sizeof (eeprom_val) - 2); offset++) checksum += buf[offset]; eeprom_val[16] = ((u8) (0x100 - checksum)) << 8; /* fill eeprom. */ memcpy (io->eeprom, eeprom_val, sizeof (eeprom_val)); /* others */ io->eeprom_writable = 0; io->ctrl_st[CtrlStNum (PP_SelfST)] |= EEPROMpresent | EEPROMOK; memcpy (io->ieee_addr, net_dev->macaddr, 6); } static void ctrl_status_write (struct device_desc *dev, u16 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; io->ctrl_st[CtrlStNum (io->pp_address)] = data; if (io->pp_address==PP_SelfCTL) { if (data&RESET) net_cs8900a_reset(dev); } //printf("%s: addr %x, data %x\n", __FUNCTION__, io->pp_address, data); } static void ctrl_status_read (struct device_desc *dev, u16 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; *data = io->ctrl_st[CtrlStNum (io->pp_address)]; //printf("%s: addr %x, data %x\n", __FUNCTION__, io->pp_address, *data); } /* FIXME: now it doesn't support erase-all/write-all commands */ static void eeprom_write (struct device_desc *dev, u16 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; if ((io->eeprom_cmd & EEWriteRegister) && io->eeprom_writable == 1) { io->eeprom[io->eeprom_cmd & 0xff] = io->eeprom_data; } else if ((io->eeprom_cmd & EEEraseRegister) && io->eeprom_writable == 1) { io->eeprom[io->eeprom_cmd & 0xff] = 0xffff; } else { if (io->eeprom_cmd & EEWriteEnable) { io->eeprom_writable = 1; } else if (io->eeprom_cmd & EEWriteDis) { io->eeprom_writable = 0; } } } static void eeprom_read (struct device_desc *dev, u16 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; if (!(io->eeprom_cmd & EEReadRegister)) return; *data = io->eeprom[io->eeprom_cmd & 0xff]; } static void net_cs8900a_fini (struct device_desc *dev) { struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; free (dev->dev); free (io); } static void net_cs8900a_reset (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; int i; /* set ProductID: rev_d */ io->product_id[0] = EISA_REG_CODE; io->product_id[1] = CS8900A | (REV_D << 8); /* see section 4.10.5 */ io->pp_address |= 0x3000; /* set control and status registers low 6 bits. see P49. */ for (i = 0; i < 16; i++) { io->ctrl_st[i] |= i * 2 + 1; io->ctrl_st[i + 16] |= i * 2; } io->ctrl_st[CtrlStNum (PP_BusST)] |= Rdy4TxNOW; eeprom_reset (dev); /* init tx/rx buffer */ if (!io->rx_frame) io->rx_frame = (u16 *) malloc (Rx_Frame_Count); memset (io->rx_frame, 0, Rx_Frame_Count); io->rx_status_p = &(io->rx_frame[0]); io->rx_length_p = &(io->rx_frame[1]); io->rx_head = io->rx_tail = 0; if (!io->tx_frame) io->tx_frame = (u16 *) malloc (Tx_Frame_Count); memset (io->tx_frame, 0, Tx_Frame_Count); io->tx_head = io->tx_tail = 0; io->ctrl_st[CtrlStNum (PP_SelfST)] |= INITD; io->ctrl_st[CtrlStNum (PP_LineST)] |= LINK_OK; io->ctrl_st[CtrlStNum (PP_TxEvent)] &= 0x3f; } static void net_cs8900a_update (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; if ((!mc->mach_pending_intr (intr->interrupts[INT_CS8900A]))) { struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; if(net_dev->net_wait_packet (net_dev, &tv) == 0) cs8900a_input (dev); } } int net_cs8900a_read_halfword (struct device_desc *dev, u32 addr, u16 * data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; int offset = (u16) (addr - dev->base); int ret = ADDR_HIT; *data = 0; switch (offset) { case Rx_Frame_Port: frame_read (dev, data); break; case IO_ISQ: isq_read (dev, data); break; case PP_Address: *data = io->pp_address | 0x3000; break; case PP_Data: if (io->pp_address >= 0x100 && io->pp_address < 0x140) { ctrl_status_read (dev, data); } switch (io->pp_address) { case PP_ProductID: *data = io->product_id[0]; break; case PP_ProductID + 2: *data = io->product_id[1]; break; case PP_IntNum: *data = io->int_num; break; case PP_EEPROMCommand: *data = io->eeprom_cmd; break; case PP_EEPROMData: eeprom_read (dev, data); break; case PP_IA: case PP_IA + 2: case PP_IA + 4: *data = io->ieee_addr[io->pp_address - PP_IA] | (io-> ieee_addr[io->pp_address - PP_IA + 1] << 8); break; case PP_ISQ: isq_read (dev, data); break; case PP_RxStatus: *data = *(io->rx_status_p); *(io->rx_status_p) = 0; io->rx_tail++; break; case PP_RxLength: *data = *(io->rx_length_p); *(io->rx_length_p) = 0; io->rx_tail++; break; } //printf("addr:%x, data:%x\n", io->pp_address, *data); break; default: break; } return ret; } int net_cs8900a_write_halfword (struct device_desc *dev, u32 addr, u16 data) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; int offset = (u16) (addr - dev->base); int ret = ADDR_HIT; switch (offset) { case Tx_Frame_Port: frame_write (dev, data); break; case IO_TxCMD: io->tx_cmd = data; break; case IO_TxLength: io->tx_length = data; break; case PP_Address: io->pp_address = data; break; case PP_Data: if (io->pp_address >= 0x100 && io->pp_address < 0x140) { ctrl_status_write (dev, data); } switch (io->pp_address) { case PP_IntNum: io->int_num = data; break; case PP_EEPROMCommand: io->eeprom_cmd = data; eeprom_write (dev, data); break; case PP_EEPROMData: if (io->eeprom_writable == 1) io->eeprom_data = data; break; case PP_IA: case PP_IA + 2: case PP_IA + 4: io->ieee_addr[io->pp_address - PP_IA] = data & 0xff; io->ieee_addr[io->pp_address - PP_IA + 1] = (data >> 8) & 0xff; break; case PP_TxCMD: io->tx_cmd = data; break; case PP_TxLength: io->tx_length = data; break; } break; default: break; } return ret; } static void cs8900a_input (struct device_desc *dev) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; int packet_len, cs8900a_len; u8 *bufptr; /*When the CS8900A commits buffer space to a par- ticular held receive frame ,data from subsequent frames can be written P85*/ if (io->ctrl_st[CtrlStNum (PP_RxEvent)] & 0x100) return; bufptr = (u8 *) & (io->rx_frame[2]); packet_len = net_dev->net_read (net_dev, bufptr, Rx_Max_Count); if (packet_len < 0) return; *(io->rx_status_p) |= RxOK; *(io->rx_length_p) = packet_len; io->rx_head = 2; io->rx_head = io->rx_head + ((packet_len + 1) / 2) - 1; io->rx_tail = 0; //printf("io->rx_head:%d, io->rx_tail:%d, packet_len:%d\n", io->rx_head, io->rx_tail, packet_len); #if 0 print_packet (bufptr, packet_len); #endif io->ctrl_st[CtrlStNum (PP_RxEvent)] |= 0x100; //TxOK if (io->ctrl_st[CtrlStNum (PP_BusCTL)] & EnableRQ) { //printf("%s:%x, packet_len:%d\n", __FUNCTION__, io->ctrl_st[CtrlStNum(PP_RxEvent)], packet_len); set_time (io->index, packet_len); io->need_update = 1; net_cs8900a_set_update_intr (dev); } } static u8 cs8900a_output (struct device_desc *dev, u8 * buf, u16 packet_len) { struct net_device *net_dev = (struct net_device *) dev->dev; struct net_cs8900a_io *io = (struct net_cs8900a_io *) dev->data; int len; //printf("%s: packet_len:%d\n", __FUNCTION__, packet_len); #if 0 print_packet (buf, packet_len); #endif if ((len = net_dev->net_write (net_dev, buf, packet_len)) == -1) { fprintf (stderr, "write to tapif error in skyeye-ne2k.c\n"); return -1; } io->ctrl_st[CtrlStNum (PP_TxEvent)] |= 0x100; io->ctrl_st[CtrlStNum (PP_BusST)] |= Rdy4TxNOW; if (io->ctrl_st[CtrlStNum (PP_BusCTL)] & EnableRQ) { set_time (io->index, packet_len); io->need_update = 1; net_cs8900a_set_update_intr (dev); } return 0; } static int net_cs8900a_setup (struct device_desc *dev) { int i; int enough = 0; struct net_cs8900a_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = net_cs8900a_fini; dev->reset = net_cs8900a_reset; dev->update = net_cs8900a_update; dev->read_halfword = net_cs8900a_read_halfword; dev->write_halfword = net_cs8900a_write_halfword; io = (struct net_cs8900a_io *) malloc (sizeof (struct net_cs8900a_io)); memset (io, 0, sizeof (struct net_cs8900a_io)); if (io == NULL) return 1; dev->data = (void *) io; net_cs8900a_reset (dev); /* see if we need to set default values. * */ set_device_default (dev, cs8900a_net_def); for (i = 0; i < MAX_DEVICE_NUM; i++) { if (cs8900a_devs[i] == NULL) { cs8900a_devs[i] = dev; io->index = i; enough = 1; break; } } if (enough == 0) return 1; return 0; } void net_cs8900a_init (struct device_module_set *mod_set) { int i; register_device_module ("cs8900a", mod_set, &net_cs8900a_setup); for (i = 0; i < MAX_DEVICE_NUM; i++) cs8900a_devs[i] = NULL; } skyeye-1.2.5_REL/device/net/skyeye_net_tuntap.c0000644000175000001440000001252411012326044020176 0ustar kshusers/* skyeye_net_tuntap.c - tuntap net device file support functions Copyright (C) 2003 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 04/27/2003 initial version * chenyu */ #include "armdefs.h" #if !(defined(__MINGW32__) || defined(__CYGWIN__) || defined(__BEOS__)) #ifdef __linux__ #include #include #include #endif #ifdef __svr4__ #include #include #include #include #include #endif #ifdef __FreeBSD__ #include #include #include #include #include #endif #ifdef __APPLE__ #include #include #include #include #include #endif #define DEBUG 0 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr, ##a) #else #define DBG_PRINT(a...) #endif #define DEFAULT_TUNTAP_IF_NAME "tap" static name_index = 0; int tuntap_open (struct net_device *net_dev) { int tapif_fd; struct ifreq ifr; char buf[128]; char if_name[10]; DBG_PRINT ("tapif_init begin\n"); #ifdef __linux__ tapif_fd = open ("/dev/net/tun", O_RDWR); DBG_PRINT ("tapif_init: fd %d\n", tapif_fd); if (tapif_fd < 0) { perror ("tapif_init:open"); printf ("-----------------------------------------------------------\n"); printf ("NOTICE: you should be root at first !!!\n"); printf ("NOTICE: you should inmod linux kernel net driver tun.o!!!\n"); printf ("NOTICE: if you don't make device node, you should do commands:\n"); printf ("NOTICE: mkdir /dev/net; mknod /dev/net/tun c 10 200\n"); printf ("NOTICE: now the net simulation function can not support!!!\n"); printf ("NOTICE: Please read SkyEye.README and try again!!!\n"); printf ("-----------------------------------------------------------\n"); return 1; } #endif #ifdef __FreeBSD__ tapif_fd = open ("/dev/tap", O_RDWR); DBG_PRINT ("tapif_init: fd %d\n", tapif_fd); if (tapif_fd == -1) { perror ("tapif_init:open"); printf ("-----------------------------------------------------------\n"); printf ("NOTICE: You should run as root if you require network\n"); printf ("NOTICE: load the kernel tap module with 'kldload if_tap'\n"); printf ("NOTICE: and execute 'cat /dev/tap'. there should be a \n"); printf ("NOTICE: device node under /dev/ (e.g. /dev/tap0).\n"); printf ("-----------------------------------------------------------\n"); return 1; } #endif #if !defined(__FreeBSD__)&&!defined(__linux__) printf ("NOTICE: No network support for your OS(yet). Bugging out!\n"); return 1; #endif snprintf (if_name, sizeof (if_name), "%s%d", DEFAULT_TUNTAP_IF_NAME, name_index); #ifdef __linux__ memset (&ifr, 0, sizeof (ifr)); ifr.ifr_flags = IFF_TAP | IFF_NO_PI; strncpy (ifr.ifr_name, if_name, IFNAMSIZ); if (ioctl (tapif_fd, TUNSETIFF, (void *) &ifr) < 0) { printf ("tapif_init: icotl TUNSETIFF error"); return 1; } #endif snprintf (buf, sizeof (buf), "ifconfig %s inet %d.%d.%d.%d", if_name, net_dev->hostip[0], net_dev->hostip[1], net_dev->hostip[2], net_dev->hostip[3]); DBG_PRINT ("tapif_init: system(\"%s\");\n", buf); system (buf); net_dev->net_fd = tapif_fd; name_index++; DBG_PRINT ("tapif_init end\n"); return 0; } int tuntap_close (struct net_device *net_dev) { close (net_dev->net_fd); return 0; } int tuntap_read (struct net_device *net_dev, void *buf, size_t count) { return read (net_dev->net_fd, buf, count); } int tuntap_write (struct net_device *net_dev, void *buf, size_t count) { return write (net_dev->net_fd, buf, count); } int tuntap_wait_packet (struct net_device *net_dev, struct timeval *tv) { fd_set frds; int ret; FD_ZERO(&frds); FD_SET(net_dev->net_fd, &frds); if((ret = select(net_dev->net_fd + 1, &frds, NULL, NULL, tv)) <= 0) return -1; if(!FD_ISSET(net_dev->net_fd, &frds)) return -1; return 0; } #else /* other systems */ #if (defined(__MINGW32__) || defined(__CYGWIN__)) #define SKYEYE_NET_TUNTAP_SUPPORT #include "./skyeye_net_tap_win32.c" #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ #ifdef __BEOS__ #define SKYEYE_NET_TUNTAP_SUPPORT #include "./skyeye_net_tap_beos.c" #endif /* __BEOS__ */ #ifndef SKYEYE_NET_TUNTAP_SUPPORT int tuntap_open (struct net_device *net_dev)s { return -1; } int tuntap_close (struct net_device *net_dev) { return 0; } int tuntap_read (struct net_device *net_dev, void *buf, size_t count) { return 0; } int tuntap_write (struct net_device *net_dev, void *buf, size_t count) { return 0; } int tuntap_wait_packet (struct net_device *net_dev, struct timeval *tv) { return -1; } #endif /* SKYEYE_NET_TUNTAP_SUPPORT */ #endif skyeye-1.2.5_REL/device/skyeye_device.c0000644000175000001440000001375511006120657016502 0ustar kshusers/* skyeye_device.c - implement the device framework for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 05/04/2004 initial version * desgin a device framework for skyeye to providing good exetension of device simulations * * walimis * */ #include "skyeye_device.h" #include "skyeye_config.h" static struct device_module_set **global_mod_set; static int mod_set_count = 0, mod_set_count_max = 0; void initialize_all_devices () { //uart_register(); //timer_register(); #ifndef NO_NET net_register (); #endif #ifdef LCD lcd_register (); #endif flash_register (); touchscreen_register (); sound_register (); nandflash_register(); } void set_device_default (struct device_desc *dev, struct device_default_value *def) { struct device_default_value *def_p = def; struct machine_config *mc = (struct machine_config *) dev->mach; while (def_p->name != NULL) { if ((strcasecmp (dev->name, def_p->name) == 0) || (strcasecmp (mc->machine_name, def_p->name) == 0)) { if (dev->base == 0) dev->base = def_p->base; if (dev->size == 0) dev->size = def_p->size; if (dev->intr.interrupts[0] == 0) memcpy (dev->intr.interrupts, def_p->interrupts, sizeof (def_p->interrupts)); return; } def_p++; } } /* find a module from mod_set * */ static struct device_module * find_module (const char *name, struct device_module_set *mod_set) { int i; struct device_module *dev_mod = NULL; if (!name || *name == '\0') return NULL; for (i = 0; i < mod_set->count; i++) { dev_mod = mod_set->mod[i]; if (strcmp (dev_mod->type_name, name) == 0) break; } return dev_mod; } static struct device_module_set * find_module_set (const char *name) { int i; struct device_module_set *mod_set = NULL; for (i = 0; i < mod_set_count; i++) { mod_set = global_mod_set[i]; if (strcmp (mod_set->name, name) == 0) break; } return mod_set; } int setup_device (char *dev_name, struct common_config *conf, void *option, machine_config_t * mc) { struct device_module_set *mod_set = NULL; struct device_module *dev_mod = NULL; struct device_desc *dev; if ((mod_set = find_module_set (dev_name)) == NULL) { SKYEYE_ERR ("can't find module set: %s\n", dev_name); return 1; } if (mod_set->initialized == 0) { mod_set->init (mod_set); mod_set->initialized = 1; } if ((dev_mod = find_module (conf->type, mod_set)) == NULL) { SKYEYE_ERR ("can't find device module: (name:%s, type:%s)\n", mod_set->name, conf->type); return 1; } mc->devices = realloc (mc->devices, sizeof (struct device_desc *) * (mc->dev_count + 1)); if (mc->devices == NULL) { SKYEYE_ERR ("can't alloc memory for devices pionter: (name:%s, type:%s)\n", mod_set->name, conf->type); return 1; } dev = malloc (sizeof (struct device_desc)); if (dev == NULL) { SKYEYE_ERR ("can't alloc memory for new device: (name:%s, type:%s)\n", mod_set->name, conf->type); return 1; } /* init device * */ memset (dev, 0, sizeof (struct device_desc)); strncpy (dev->type, conf->type, MAX_STR_NAME); dev->type[MAX_STR_NAME - 1] = '\0'; if (conf->name && *(conf->name) != '\0') { strncpy (dev->name, conf->name, MAX_STR_NAME); dev->name[MAX_STR_NAME - 1] = '\0'; } dev->base = conf->base; dev->size = conf->size; memcpy (dev->intr.interrupts, conf->interrupts, sizeof (conf->interrupts)); dev->intr.set_interrupt = mc->mach_set_intr; dev->intr.pending_interrupt = mc->mach_pending_intr; dev->intr.update_interrupt = mc->mach_update_intr; dev->mem_op.write_byte = mc->mach_mem_write_byte; dev->mem_op.read_byte = mc->mach_mem_read_byte; dev->mach = (void *) mc; /* setup device module data * */ if (mod_set->setup_module) { if (mod_set->setup_module (dev, option) != 0) { free(dev); SKYEYE_ERR ("failed to setup_module (name:%s, type:%s)\n", mod_set->name, conf->type); return 1; } } mc->devices[mc->dev_count] = dev; mc->dev_count++; /* setup device data itself. * */ dev_mod->setup (dev); return 0; } /* register a "device module set" to the global module set "global_mod_set". * called by the device register funtions. e.g. uart_register. * */ int register_device_module_set (struct device_module_set *mod_set) { if (mod_set_count == mod_set_count_max) { mod_set_count_max += 4; global_mod_set = realloc (global_mod_set, sizeof (struct device_module_set *) * mod_set_count_max); if (global_mod_set == NULL) return 1; } global_mod_set[mod_set_count] = mod_set; mod_set_count++; return 0; } /* register a "device module" to a specific "device module set", * e.g. uart or net module set * called by device module initialize funtions. e.g. uart_s3c4510b_init. * */ int register_device_module (char *name, struct device_module_set *mod_set, int (*setup) (struct device_desc * dev)) { struct device_module *dev_mod; if (mod_set->count == mod_set->count_max) { mod_set->count_max += 4; mod_set->mod = realloc (mod_set->mod, sizeof (struct device_module *) * mod_set->count_max); if (mod_set->mod == NULL) return 1; } dev_mod = malloc (sizeof (struct device_module)); if (dev_mod == NULL) return 1; dev_mod->type_name = strdup (name); dev_mod->setup = setup; mod_set->mod[mod_set->count] = dev_mod; mod_set->count++; return 0; } skyeye-1.2.5_REL/device/Makefile.am0000644000175000001440000000245411006120402015520 0ustar kshusers# # top level directory for RTEMS build tree # ## ## $Id: Makefile.am,v 1.39.2.3 2007/02/22 12:13:33 ralf Exp $ ## dev_uart = uart/skyeye_uart.c uart/skyeye_uart_net.c uart/skyeye_uart_stdio.c \ uart/skyeye_uart_cvt_dcc.c uart/skyeye_uart_pipe.c dev_flash = flash/armflash.c flash/dev_flash_sst39lvf160.c \ flash/dev_flash_am29.c flash/dev_flash_intel.c flash/skyeye_flash.c dev_nandflash = nandflash/dev_nandflash_s3c2410.c nandflash/nandflash_smallblock.c nandflash/skyeye_nandflash.c dev_sound = sound/dev_sound_s3c44b0x.c sound/skyeye_sound.c sound/skyeye_sound_pcm.c dev_lcd = lcd/dev_lcd_au1100.c lcd/dev_lcd_s3c2410.c lcd/skyeye_lcd.c \ lcd/dev_lcd_ep7312.c lcd/dev_lcd_s3c44b0x.c lcd/skyeye_lcd_gtk.c \ lcd/dev_lcd_pxa.c dev_net = net/dev_net_cs8900a.c net/dev_net_s3c4510b.c net/skyeye_net_tuntap.c \ net/dev_net_rtl8019.c net/skyeye_net.c net/skyeye_net_vnet.c dev_ts = touchscreen/dev_touchscreen_skyeye.c touchscreen/skyeye_touchscreen.c libdev_a_SOURCES = skyeye_device.c $(dev_uart) $(dev_flash) $(dev_nandflash) $(dev_sound) $(dev_net) $(dev_ts) if LCD libdev_a_SOURCES += $(dev_lcd) endif noinst_LIBRARIES = libdev.a INCLUDES = -I./ -I$(top_srcdir)/arch/arm -I$(top_srcdir)/arch/arm/common @COMMON_INCLUDES@ if LCD INCLUDES += `pkg-config gtk+-2.0 --cflags` endif skyeye-1.2.5_REL/device/flash/0000755000175000001440000000000011023514411014562 5ustar kshusersskyeye-1.2.5_REL/device/flash/dev_flash_sst39lvf160.c0000644000175000001440000002314010606502134020672 0ustar kshusers/* dev_flash_sst39lvf160.c - skyeye SST39LF/VF160 flash simulation Copyright (C) 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 2007.04.03 Written by Anthony Lee */ #include #include #include "armdefs.h" #include "skyeye_device.h" #include "skyeye_flash.h" #include "dev_flash_sst39lvf160.h" #define FLASH_SST39LVF160_DEBUG 0 #define PRINT(x...) printf("[FLASH_SST39LVF160]: " x) #if FLASH_SST39LVF160_DEBUG #define DEBUG(x...) printf("[FLASH_SST39LVF160]: " x) #else #define DEBUG(x...) (void)0 #endif extern mem_bank_t *global_mbp; extern mem_bank_t *bank_ptr(ARMword addr); extern ARMword real_read_byte(ARMul_State*, ARMword); extern ARMword real_read_halfword(ARMul_State*, ARMword); extern ARMword real_read_word(ARMul_State*, ARMword); extern void real_write_byte(ARMul_State*, ARMword, ARMword); extern void real_write_halfword(ARMul_State*, ARMword, ARMword); extern void real_write_word(ARMul_State*, ARMword, ARMword); static void flash_sst39lvf160_fini(struct device_desc *dev) { struct flash_sst39lvf160_io *io = (struct flash_sst39lvf160_io*)dev->data; free(dev->dev); free(io); } static void flash_sst39lvf160_reset(struct device_desc *dev) { struct flash_sst39lvf160_io *io = (struct flash_sst39lvf160_io*)dev->data; memset(io, 0, sizeof(struct flash_sst39lvf160_io)); io->dump_cnt = 0xffff; } static void flash_sst39lvf160_update(struct device_desc *dev) { struct flash_device *flash_dev = (struct flash_device*)dev->dev; struct flash_sst39lvf160_io *io = (struct flash_sst39lvf160_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; uint32_t addr, data; int fd; if (flash_dev->dump[0] == 0) return; if (io->dump_flags == 0 || (io->dump_flags & 0x2) != 0) return; io->dump_cnt -= 1; if (io->dump_cnt == 0) { if (skyeye_flash_dump(flash_dev->dump, dev->base, 0x200000) != 0) { io->dump_flags |= 0x2; printf("\n"); PRINT("*** FAILED: Can't dump to %s\n", flash_dev->dump); return; } io->dump_cnt = 0xffff; io->dump_flags = 0; printf("\n"); PRINT("Dumped to %s\n", flash_dev->dump); } } static int flash_sst39lvf160_read_byte(struct device_desc *dev, uint32_t addr, uint8_t *data) { struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; global_mbp = bank_ptr(addr); *data = real_read_byte(state, addr); DEBUG("read_byte(addr:0x%08x, data:0x%x)\n", addr, *data); return ADDR_HIT; } static int flash_sst39lvf160_write_byte(struct device_desc *dev, uint32_t addr, uint8_t data) { #if 0 struct flash_sst39lvf160_io *io = (struct flash_sst39lvf160_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; global_mbp = bank_ptr(addr); real_write_byte(state, addr, data); io->dump_flags |= 0x1; DEBUG("write_byte(addr:0x%08x, data:0x%x)\n", addr, data); return ADDR_HIT; #else PRINT("write_byte: Unsupported !!!\n"); return ADDR_NOHIT; #endif } static int flash_sst39lvf160_read_halfword(struct device_desc *dev, uint32_t addr, uint16_t *data) { struct flash_sst39lvf160_io *io = (struct flash_sst39lvf160_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; uint32_t offset = (addr - dev->base) >> 1; if (CMD_SOFTWARE_ID_ENTRY(io)) { switch (offset) { case 0: *data = 0xbf; break; case 1: *data = 0x2782; break; default: *data = 0x0; break; } } if (CMD_CFI_QUERY_ENTRY(io)) { switch (offset) { /* CFI QUERY IDENTIFICATION STRING */ case 0x10: *data= 0x51; break; case 0x11: *data= 0x52; break; case 0x12: *data= 0x59; break; case 0x13: *data= 0x1; break; case 0x14: *data= 0x7; break; case 0x15: *data= 0x0; break; case 0x16: *data= 0x0; break; case 0x17: *data= 0x0; break; case 0x18: *data= 0x0; break; case 0x19: *data= 0x0; break; case 0x1a: *data= 0x0; break; /* SYSTEM INTERFACE INFORMATION */ case 0x1b: *data= strcmp(dev->type, "SST39LF160") == 0 ? 0x30 : 0x27; break; case 0x1c: *data= 0x36; break; case 0x1d: *data= 0x0; break; case 0x1e: *data= 0x0; break; case 0x1f: *data= 0x4; break; case 0x20: *data= 0x0; break; case 0x21: *data= 0x4; break; case 0x22: *data= 0x6; break; case 0x23: *data= 0x1; break; case 0x24: *data= 0x0; break; case 0x25: *data= 0x1; break; case 0x26: *data= 0x1; break; /* DEVICE GEOMETRY INFORMATION */ case 0x27: *data= 0x15; break; case 0x28: *data= 0x1; break; case 0x29: *data= 0x0; break; case 0x2a: *data= 0x0; break; case 0x2b: *data= 0x0; break; case 0x2c: *data= 0x2; break; case 0x2d: *data= 0xff; break; case 0x2e: *data= 0x1; break; case 0x2f: *data= 0x10; break; case 0x30: *data= 0x0; break; case 0x31: *data= 0x1f; break; case 0x32: *data= 0x0; break; case 0x33: *data= 0x0; break; case 0x34: *data= 0x1; break; default: *data = 0x0; break; } } if (io->cnt == 0) { /* read data from addr */ global_mbp = bank_ptr(addr); *data = real_read_halfword(state, addr); } io->n_bus = 0; DEBUG("read_halfword(offset:0x%08x, data:0x%x)\n", offset, *data); return ADDR_HIT; } static int flash_sst39lvf160_write_halfword(struct device_desc *dev, uint32_t addr, uint16_t data) { struct flash_sst39lvf160_io *io = (struct flash_sst39lvf160_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; uint32_t offset = (addr - dev->base) >> 1; uint32_t start, end; DEBUG("write_halfword(%dst Bus, offset:0x%08x, data:0x%x)\n", io->n_bus + 1, offset, data); if (CMD_WORD_PROGRAM(io)) { /* write data to addr */ global_mbp = bank_ptr(addr); real_write_halfword(state, addr, data); io->dump_flags |= 0x1; goto reset; } if (CMD_ERASE(io)) { switch (data) { case 0x10: /* Chip-Erase */ start = dev->base; end = start + 0x200000; break; case 0x30: /* Sector-Erase: 4KBytes/sector */ start = addr; end = start + 0x1000; break; case 0x50: /* Block-Erase: 64KBytes/block */ start = addr; end = start + 0x10000; break; default: start = end = 0x0; break; } if (end > start && end <= dev->base + 0x200000) { for (addr = start; addr < end; addr += 4) { global_mbp = bank_ptr(addr); real_write_word(state, addr, 0xffffffff); } DEBUG("*** Erase(start:0x%08x, end:0x%08x)\n", start, end); } else { PRINT("*** ERROR: Erase(start:0x%08x, end:0x%08x)\n", start, end); } goto reset; } if (io->n_bus < 6) { io->bus[io->n_bus].addr = offset; io->bus[io->n_bus].data = data; io->n_bus += 1; io->cnt = io->n_bus; if (CMD_QUERY_EXIT(io)) goto reset; } goto exit; reset: io->cnt = io->n_bus = 0; memset(&io->bus[0], 0, sizeof(io->bus[0]) * 6); exit: return ADDR_HIT; } static int flash_sst39lvf160_read_word(struct device_desc *dev, uint32_t addr, uint32_t *data) { struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; global_mbp = bank_ptr(addr); *data = real_read_word(state, addr); DEBUG("read_word(addr:0x%08x, data:0x%x)\n", addr, *data); return ADDR_HIT; } static int flash_sst39lvf160_write_word(struct device_desc *dev, uint32_t addr, uint32_t data) { #if 0 struct flash_sst39lvf160_io *io = (struct flash_sst39lvf160_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; global_mbp = bank_ptr(addr); real_write_word(state, addr, data); io->dump_flags |= 0x1; DEBUG("write_word(addr:0x%08x, data:0x%x)\n", addr, data); return ADDR_HIT; #else PRINT("write_word: Unsupported !!!\n"); return ADDR_NOHIT; #endif } static int flash_sst39lvf160_setup(struct device_desc *dev) { struct flash_sst39lvf160_io *io; if (skyeye_config.arch == NULL || skyeye_config.arch->arch_name == NULL || strcmp(skyeye_config.arch->arch_name, "arm") != 0) { PRINT("*** ERROR: Unsupported architecture !!!\n"); return -1; } if (dev->size != 0x200000) { PRINT("*** ERROR: Only support 2M flash !!!\n"); return -1; } io = (struct flash_sst39lvf160_io*)malloc(sizeof(struct flash_sst39lvf160_io)); if (io == NULL) return -1; dev->fini = flash_sst39lvf160_fini; dev->reset = flash_sst39lvf160_reset; dev->update = flash_sst39lvf160_update; dev->read_byte = flash_sst39lvf160_read_byte; dev->write_byte = flash_sst39lvf160_write_byte; dev->read_halfword = flash_sst39lvf160_read_halfword; dev->write_halfword = flash_sst39lvf160_write_halfword; dev->read_word = flash_sst39lvf160_read_word; dev->write_word = flash_sst39lvf160_write_word; dev->data = (void*)io; flash_sst39lvf160_reset(dev); return 0; } void flash_sst39lvf160_init(struct device_module_set *mod_set) { register_device_module("SST39LF160", mod_set, &flash_sst39lvf160_setup); register_device_module("SST39VF160", mod_set, &flash_sst39lvf160_setup); } skyeye-1.2.5_REL/device/flash/dev_flash_am29.h0000644000175000001440000000727110605111734017533 0ustar kshusers/* dev_flash_am29.h - skyeye AMD Am29LV160B flash simulation Copyright (C) 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __DEV_FLASH_AM29_H_ #define __DEV_FLASH_AM29_H_ #include struct flash_am29_bus { uint32_t addr; uint32_t data; }; struct flash_am29_io; typedef void (*flash_am29_bautoselect_func)(struct flash_am29_io*, uint32_t, uint8_t*); typedef void (*flash_am29_wautoselect_func)(struct flash_am29_io*, uint32_t, uint16_t*); struct flash_am29_io { char type[MAX_STR_NAME]; int bcnt; int n_bbus; struct flash_am29_bus bbus[6]; int wcnt; int n_wbus; struct flash_am29_bus wbus[6]; uint16_t *query; int max_query; flash_am29_bautoselect_func bautoselect; flash_am29_wautoselect_func wautoselect; uint32_t chip_size; uint32_t sector_size; int dump_cnt; int dump_flags; }; #define CMD_BCHECK(io, n, o, v) \ (io->bbus[n].addr == o && io->bbus[n].data == v) #define CMD_WCHECK(io, n, o, v) \ (io->wbus[n].addr == o && io->wbus[n].data == v) #define CMD_BYTE_PROGRAM(io) \ (io->bcnt == 3 && \ CMD_BCHECK(io, 0, 0xaaa, 0xaa) && \ CMD_BCHECK(io, 1, 0x555, 0x55) && \ CMD_BCHECK(io, 2, 0xaaa, 0xa0)) #define CMD_WORD_PROGRAM(io) \ (io->wcnt == 3 && \ CMD_WCHECK(io, 0, 0x555, 0xaa) && \ CMD_WCHECK(io, 1, 0x2aa, 0x55) && \ CMD_WCHECK(io, 2, 0x555, 0xa0)) #define CMD_BYTE_ERASE(io) \ (io->bcnt == 5 && \ CMD_BCHECK(io, 0, 0xaaa, 0xaa) && \ CMD_BCHECK(io, 1, 0x555, 0x55) && \ CMD_BCHECK(io, 2, 0xaaa, 0x80) && \ CMD_BCHECK(io, 3, 0xaaa, 0xaa) && \ CMD_BCHECK(io, 4, 0x555, 0x55)) #define CMD_WORD_ERASE(io) \ (io->wcnt == 5 && \ CMD_WCHECK(io, 0, 0x555, 0xaa) && \ CMD_WCHECK(io, 1, 0x2aa, 0x55) && \ CMD_WCHECK(io, 2, 0x555, 0x80) && \ CMD_WCHECK(io, 3, 0x555, 0xaa) && \ CMD_WCHECK(io, 4, 0x2aa, 0x55)) #define CMD_BYTE_AUTOSELCT(io) \ (io->bcnt == 3 && \ CMD_BCHECK(io, 0, 0xaaa, 0xaa) && \ CMD_BCHECK(io, 1, 0x555, 0x55) && \ CMD_BCHECK(io, 2, 0xaaa, 0x90)) #define CMD_WORD_AUTOSELCT(io) \ (io->wcnt == 3 && \ CMD_WCHECK(io, 0, 0x555, 0xaa) && \ CMD_WCHECK(io, 1, 0x2aa, 0x55) && \ CMD_WCHECK(io, 2, 0x555, 0x90)) #define CMD_BYTE_QUERY(io) \ (io->bcnt == 1 && \ CMD_BCHECK(io, 0, 0xaa, 0x98)) #define CMD_WORD_QUERY(io) \ (io->wcnt == 1 && \ CMD_WCHECK(io, 0, 0x55, 0x98)) #define CMD_BYTE_UNLOCK_BYPASS(io) \ (io->bcnt == 3 && \ CMD_BCHECK(io, 0, 0xaaa, 0xaa) && \ CMD_BCHECK(io, 1, 0x555, 0x55) && \ CMD_BCHECK(io, 2, 0xaaa, 0x20)) #define CMD_WORD_UNLOCK_BYPASS(io) \ (io->wcnt == 3 && \ CMD_WCHECK(io, 0, 0x555, 0xaa) && \ CMD_WCHECK(io, 1, 0x2aa, 0x55) && \ CMD_WCHECK(io, 2, 0x555, 0x20)) #define CMD_BYTE_UNLOCK_BYPASS_PROGRAM_RESET(io) \ (io->bcnt == 2 && \ io->bbus[0].data == 0xa0 || \ io->bbus[0].data == 0x90) #define CMD_WORD_UNLOCK_BYPASS_PROGRAM_RESET(io) \ (io->wcnt == 2 && \ io->wbus[0].data == 0xa0 || \ io->wbus[0].data == 0x90) #endif /* __DEV_FLASH_AM29_H_ */ skyeye-1.2.5_REL/device/flash/skyeye_flash.c0000644000175000001440000001054310606502134017424 0ustar kshusers/* skyeye_flash.c - skyeye general flash device file support functions Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 09/22/2005 initial version * walimis */ #include #include #include #include "armdefs.h" #include "skyeye_device.h" #include "skyeye_options.h" #include "skyeye.h" #include "skyeye_flash.h" extern void flash_intel_init(struct device_module_set *mod_set); extern void flash_sst39lvf160_init(struct device_module_set *mod_set); extern void flash_am29_init(struct device_module_set *mod_set); /* initialize the flash module set. * If you want to add a new flash simulation, just add a "flash_*_init" function to it. * */ static void flash_init (struct device_module_set *mod_set) { flash_intel_init (mod_set); flash_sst39lvf160_init (mod_set); flash_am29_init (mod_set); } static int flash_setup (struct device_desc *dev, void *option) { struct flash_device *flash_dev; struct flash_option *flash_opt = (struct flash_option *) option; int ret = 0; flash_dev = (struct flash_device *) malloc (sizeof (struct flash_device)); if (flash_dev == NULL) return 1; memset (flash_dev, 0, sizeof (struct flash_device)); memcpy (&flash_dev->dump[0], &flash_opt->dump[0], MAX_STR_NAME); dev->dev = (void *) flash_dev; return ret; } static struct device_module_set flash_mod_set = { .name = "flash", .count = 0, .count_max = 0, .init = flash_init, .initialized = 0, .setup_module = flash_setup, }; /* used by global device initialize function. * */ void flash_register () { if (register_device_module_set (&flash_mod_set)) SKYEYE_ERR ("\"%s\" module set register error!\n", flash_mod_set.name); } /* helper functions */ #ifdef __MINGW32__ #include #undef S_IREAD #undef S_IWRITE #undef O_CREAT #undef O_TRUNC #undef O_WRONLY #define S_IREAD _S_IREAD #define S_IWRITE _S_IWRITE #define O_CREAT _O_CREAT #define O_TRUNC _O_TRUNC #define O_WRONLY (_O_WRONLY | _O_BINARY) #define open(file, flags, mode) _open(file, flags, mode) #define close(fd) _close(fd) #define write(fd, buf, count) _write(fd, buf, count) #else #include #include #include #ifndef S_IREAD #define S_IREAD S_IRUSR #endif #ifndef S_IWRITE #define S_IWRITE S_IWUSR #endif #endif static int skyeye_flash_arm_read_word (uint32_t addr, uint32_t *data) { extern mem_bank_t *global_mbp; extern mem_bank_t *bank_ptr(ARMword addr); ARMul_State *state = (ARMul_State*)skyeye_config.mach->state; if (data == NULL || state == NULL || (global_mbp = bank_ptr(addr)) == NULL ) return -1; *data = real_read_word(state, addr); #ifndef HOST_IS_BIG_ENDIAN if (state->bigendSig == HIGH) #else if (state->bigendSig != HIGH) #endif *data = ((*data & 0xff) << 24) | (((*data >> 8) & 0xff) << 16) | (((*data >> 16) & 0xff) << 8) | (((*data >> 24) & 0xff)); return 0; } int skyeye_flash_dump (const char *filename, uint32_t base, uint32_t size) { uint32_t addr, data; int fd; int (*read_word_func)(uint32_t, uint32_t*) = NULL; if (filename == NULL || *filename == 0 || skyeye_config.arch == NULL || skyeye_config.arch->arch_name == NULL) return -1; if (strcmp(skyeye_config.arch->arch_name, "arm") == 0) /* arm */ read_word_func = skyeye_flash_arm_read_word; else /* TODO */ return -1; fd = open(filename, O_CREAT | O_TRUNC | O_WRONLY, S_IREAD | S_IWRITE); if (fd == -1) return -1; for (addr = base; addr < base + size; addr += 4) { if ((*read_word_func)(base, &data) != 0) { close(fd); return -1; } write(fd, &data, 4); } close(fd); return 0; } skyeye-1.2.5_REL/device/flash/armflash.h0000644000175000001440000000067710541455476016565 0ustar kshusers//ywc 2005-1-21 for flash simulation ARMword flash_read_byte (ARMul_State * state, ARMword addr); void flash_write_byte (ARMul_State * state, ARMword addr, ARMword data); ARMword flash_read_halfword (ARMul_State * state, ARMword addr); void flash_write_halfword (ARMul_State * state, ARMword addr, ARMword data); ARMword flash_read_word (ARMul_State * state, ARMword addr); void flash_write_word (ARMul_State * state, ARMword addr, ARMword data); skyeye-1.2.5_REL/device/flash/armflash.c0000644000175000001440000000755710555732132016554 0ustar kshusers#include #include #include #include "armdefs.h" ARMword flash_read_byte (ARMul_State * state, ARMword addr) { struct device_desc *dev; ARMword data; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->read_byte) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->read_byte (dev, addr, (u8 *) & data) != ADDR_NOHIT) return data & 0xff; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->read_byte (dev, addr, (u8 *) & data) != ADDR_NOHIT) return data & 0xff; } } } ARMword flash_read_halfword (ARMul_State * state, ARMword addr) { struct device_desc *dev; ARMword data; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->read_halfword) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->read_halfword (dev, addr, (u16 *) & data) != ADDR_NOHIT) return data & 0xffff; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->read_halfword (dev, addr, (u16 *) & data) != ADDR_NOHIT) return data & 0xffff; } } } ARMword flash_read_word (ARMul_State * state, ARMword addr) { struct device_desc *dev; ARMword data; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->read_word) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->read_word (dev, addr, (u32 *) & data) != ADDR_NOHIT) return data; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->read_word (dev, addr, (u32 *) & data) != ADDR_NOHIT) return data; } } } void flash_write_byte (ARMul_State * state, ARMword addr, ARMword data) { struct device_desc *dev; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->write_byte) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->write_byte (dev, addr, (u8) data) != ADDR_NOHIT) return; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->write_byte (dev, addr, (u8) data) != ADDR_NOHIT) return; } } } void flash_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { struct device_desc *dev; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->write_halfword) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->write_halfword (dev, addr, (u16) data) != ADDR_NOHIT) return; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->write_halfword (dev, addr, (u16) data) != ADDR_NOHIT) return; } } } void flash_write_word (ARMul_State * state, ARMword addr, ARMword data) { struct device_desc *dev; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->write_word) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->write_word (dev, addr, data) != ADDR_NOHIT) return; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->write_word (dev, addr, data) != ADDR_NOHIT) return; } } } skyeye-1.2.5_REL/device/flash/dev_flash_sst39lvf160.h0000644000175000001440000000433110604543121020677 0ustar kshusers/* dev_flash_sst39lvf160.h - skyeye SST39LF/VF160 flash simulation Copyright (C) 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __DEV_FLASH_SST39LVF160_H_ #define __DEV_FLASH_SST39LVF160_H_ #include struct flash_sst39lvf160_bus { uint32_t addr; uint32_t data; }; struct flash_sst39lvf160_io { int cnt; int n_bus; struct flash_sst39lvf160_bus bus[6]; int dump_cnt; int dump_flags; }; #define CMD_CHECK(io, n, o, v) \ (io->bus[n].addr == o && io->bus[n].data == v) #define CMD_WORD_PROGRAM(io) \ (io->cnt == 3 && \ CMD_CHECK(io, 0, 0x5555, 0xaa) && \ CMD_CHECK(io, 1, 0x2aaa, 0x55) && \ CMD_CHECK(io, 2, 0x5555, 0xa0)) #define CMD_ERASE(io) \ (io->cnt == 5 && \ CMD_CHECK(io, 0, 0x5555, 0xaa) && \ CMD_CHECK(io, 1, 0x2aaa, 0x55) && \ CMD_CHECK(io, 2, 0x5555, 0x80) && \ CMD_CHECK(io, 3, 0x5555, 0xaa) && \ CMD_CHECK(io, 4, 0x2aaa, 0x55)) #define CMD_SOFTWARE_ID_ENTRY(io) \ (io->cnt == 3 && \ CMD_CHECK(io, 0, 0x5555, 0xaa) && \ CMD_CHECK(io, 1, 0x2aaa, 0x55) && \ CMD_CHECK(io, 2, 0x5555, 0x90)) #define CMD_CFI_QUERY_ENTRY(io) \ (io->cnt == 3 && \ CMD_CHECK(io, 0, 0x5555, 0xaa) && \ CMD_CHECK(io, 1, 0x2aaa, 0x55) && \ CMD_CHECK(io, 2, 0x5555, 0x98)) #define CMD_QUERY_EXIT(io) \ ((io->cnt == 1 && io->bus[0].data == 0xf0) || \ (io->cnt == 3 && \ CMD_CHECK(io, 0, 0x5555, 0xaa) && \ CMD_CHECK(io, 1, 0x2aaa, 0x55) && \ CMD_CHECK(io, 2, 0x5555, 0xf0))) #endif /* __DEV_FLASH_SST39LVF160_H_ */ skyeye-1.2.5_REL/device/flash/dev_flash_am29.c0000644000175000001440000003627110606502134017527 0ustar kshusers/* dev_flash_am29.c - skyeye AMD Am29xxxxxx flash simulation Copyright (C) 2007 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 2007.04.05 Written by Anthony Lee */ #include #include #include "armdefs.h" #include "skyeye_device.h" #include "skyeye_flash.h" #include "dev_flash_am29.h" #define FLASH_AM29_DEBUG 0 #define PRINT(x...) printf("[FLASH_AM29]: " x) #if FLASH_AM29_DEBUG #define DEBUG(x...) printf("[FLASH_AM29]: " x) #else #define DEBUG(x...) (void)0 #endif extern mem_bank_t *global_mbp; extern mem_bank_t *bank_ptr(ARMword addr); extern ARMword real_read_byte(ARMul_State*, ARMword); extern ARMword real_read_halfword(ARMul_State*, ARMword); extern ARMword real_read_word(ARMul_State*, ARMword); extern void real_write_byte(ARMul_State*, ARMword, ARMword); extern void real_write_halfword(ARMul_State*, ARMword, ARMword); extern void real_write_word(ARMul_State*, ARMword, ARMword); static void flash_am29_fini(struct device_desc *dev) { struct flash_am29_io *io = (struct flash_am29_io*)dev->data; free(dev->dev); free(io); } static void flash_am29_reset(struct device_desc *dev) { struct flash_am29_io *io = (struct flash_am29_io*)dev->data; io->bcnt = io->n_bbus = 0; memset(&io->bbus[0], 0, sizeof(io->bbus[0]) * 6); io->wcnt = io->n_wbus = 0; memset(&io->wbus[0], 0, sizeof(io->wbus[0]) * 6); io->dump_cnt = 0xffff; io->dump_flags = 0; } static void flash_am29_update(struct device_desc *dev) { struct flash_device *flash_dev = (struct flash_device*)dev->dev; struct flash_am29_io *io = (struct flash_am29_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; if (flash_dev->dump[0] == 0) return; if (io->dump_flags == 0 || (io->dump_flags & 0x2) != 0) return; io->dump_cnt -= 1; if (io->dump_cnt == 0) { if (skyeye_flash_dump(flash_dev->dump, dev->base, io->chip_size) != 0) { io->dump_flags |= 0x2; printf("\n"); PRINT("*** FAILED: Can't dump to %s\n", flash_dev->dump); return; } io->dump_cnt = 0xffff; io->dump_flags = 0; printf("\n"); PRINT("Dumped to %s\n", flash_dev->dump); } } static int flash_am29_read_byte(struct device_desc *dev, uint32_t addr, uint8_t *data) { struct flash_am29_io *io = (struct flash_am29_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; uint32_t offset = addr - dev->base; if (io->bautoselect != NULL && io->bcnt > 0) { if (io->query != NULL && CMD_BYTE_QUERY(io)) { *data = ((offset >> 1) < io->max_query ? *(io->query + (offset >> 1)) : 0x0); } if (CMD_BYTE_AUTOSELCT(io)) { io->bautoselect(io, offset, data); } DEBUG("read_byte(offset:0x%08x, data:0x%x)\n", offset, *data); } if (io->bcnt == 0) { /* read data from addr */ global_mbp = bank_ptr(addr); *data = real_read_byte(state, addr); } io->n_bbus = 0; return ADDR_HIT; } static int flash_am29_write_byte(struct device_desc *dev, uint32_t addr, uint8_t data) { struct flash_am29_io *io = (struct flash_am29_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; uint32_t offset = addr - dev->base; uint32_t start, end; if (io->bautoselect == NULL) { PRINT("write_byte: Unsupported !!!\n"); return ADDR_NOHIT; } DEBUG("write_byte(%dst Bus, offset:0x%08x, data:0x%x)\n", io->n_bbus + 1, offset, data); if (io->n_bbus == 0 && (data == 0xb0 || data == 0x30)) { DEBUG("Erase Suspend/Resume.\n"); return ADDR_NOHIT; } if (CMD_BYTE_PROGRAM(io)) { /* write data to addr */ global_mbp = bank_ptr(addr); real_write_byte(state, addr, data); io->dump_flags |= 0x1; goto reset; } if (CMD_BYTE_ERASE(io)) { switch (data) { case 0x10: /* Chip-Erase */ start = dev->base; end = start + io->chip_size; break; case 0x30: /* Sector-Erase */ start = addr; end = start + io->sector_size; break; default: start = end = 0x0; break; } if (end > start && end <= dev->base + io->chip_size) { for (addr = start; addr < end; addr += 4) { global_mbp = bank_ptr(addr); real_write_word(state, addr, 0xffffffff); } DEBUG("*** Erase(start:0x%08x, end:0x%08x)\n", start, end); } else { PRINT("*** ERROR: Erase(start:0x%08x, end:0x%08x)\n", start, end); } goto reset; } if (io->n_bbus < 6) { io->bbus[io->n_bbus].addr = offset; io->bbus[io->n_bbus].data = data; io->n_bbus += 1; io->bcnt = io->n_bbus; if (data == 0xf0) goto reset; /* CMD_RESET */ } if (CMD_BYTE_UNLOCK_BYPASS(io) || CMD_BYTE_UNLOCK_BYPASS_PROGRAM_RESET(io)) { DEBUG("*** WARNING: Unlock Bypass.\n"); goto reset; } goto exit; reset: io->bcnt = io->n_bbus = 0; memset(&io->bbus[0], 0, sizeof(io->bbus[0]) * 6); exit: return ADDR_HIT; } static int flash_am29_read_halfword(struct device_desc *dev, uint32_t addr, uint16_t *data) { struct flash_am29_io *io = (struct flash_am29_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; uint32_t offset = (addr - dev->base) >> 1; if (io->wautoselect != NULL && io->wcnt > 0) { if (io->query != NULL && CMD_WORD_QUERY(io)) { *data = (offset < io->max_query ? *(io->query + offset) : 0x0); } if (CMD_WORD_AUTOSELCT(io)) { io->wautoselect(io, offset, data); } DEBUG("read_halfword(offset:0x%08x, data:0x%x)\n", offset, *data); } if (io->wcnt == 0) { /* read data from addr */ global_mbp = bank_ptr(addr); *data = real_read_halfword(state, addr); } io->n_wbus = 0; return ADDR_HIT; } static int flash_am29_write_halfword(struct device_desc *dev, uint32_t addr, uint16_t data) { struct flash_am29_io *io = (struct flash_am29_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; uint32_t offset = (addr - dev->base) >> 1; uint32_t start, end; if (io->wautoselect == NULL) { PRINT("write_halfword: Unsupported !!!\n"); return ADDR_NOHIT; } DEBUG("write_halfword(%dst Bus, offset:0x%08x, data:0x%x)\n", io->n_wbus + 1, offset, data); if (io->n_wbus == 0 && (data == 0xb0 || data == 0x30)) { DEBUG("Erase Suspend/Resume.\n"); return ADDR_NOHIT; } if (CMD_WORD_PROGRAM(io)) { /* write data to addr */ global_mbp = bank_ptr(addr); real_write_halfword(state, addr, data); io->dump_flags |= 0x1; goto reset; } if (CMD_WORD_ERASE(io)) { switch (data) { case 0x10: /* Chip-Erase */ start = dev->base; end = start + io->chip_size; break; case 0x30: /* Sector-Erase */ start = addr; end = start + io->sector_size; break; default: start = end = 0x0; break; } if (end > start && end <= dev->base + io->chip_size) { for (addr = start; addr < end; addr += 4) { global_mbp = bank_ptr(addr); real_write_word(state, addr, 0xffffffff); } DEBUG("*** Erase(start:0x%08x, end:0x%08x)\n", start, end); } else { PRINT("*** ERROR: Erase(start:0x%08x, end:0x%08x)\n", start, end); } goto reset; } if (io->n_wbus < 6) { io->wbus[io->n_wbus].addr = offset; io->wbus[io->n_wbus].data = data; io->n_wbus += 1; io->wcnt = io->n_wbus; if (data == 0xf0) goto reset; /* CMD_RESET */ } if (CMD_WORD_UNLOCK_BYPASS(io) || CMD_WORD_UNLOCK_BYPASS_PROGRAM_RESET(io)) { DEBUG("*** WARNING: Unlock Bypass.\n"); goto reset; } goto exit; reset: io->wcnt = io->n_wbus = 0; memset(&io->wbus[0], 0, sizeof(io->wbus[0]) * 6); exit: return ADDR_HIT; } static int flash_am29_read_word(struct device_desc *dev, uint32_t addr, uint32_t *data) { struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; global_mbp = bank_ptr(addr); *data = real_read_word(state, addr); DEBUG("read_word(addr:0x%08x, data:0x%x)\n", addr, *data); return ADDR_HIT; } static int flash_am29_write_word(struct device_desc *dev, uint32_t addr, uint32_t data) { #if 0 struct flash_am29_io *io = (struct flash_am29_io*)dev->data; struct machine_config *mc = (struct machine_config*)dev->mach; ARMul_State *state = (ARMul_State*)mc->state; global_mbp = bank_ptr(addr); real_write_word(state, addr, data); io->dump_flags |= 0x1; DEBUG("write_word(addr:0x%08x, data:0x%x)\n", addr, data); return ADDR_HIT; #else PRINT("write_word: Unsupported !!!\n"); return ADDR_NOHIT; #endif } static int flash_am29_setup(struct device_desc *dev, uint16_t *query, int max_query, flash_am29_bautoselect_func bautoselect, flash_am29_wautoselect_func wautoselect, uint32_t chip_size, uint32_t sector_size) { struct flash_am29_io *io; if (skyeye_config.arch == NULL || skyeye_config.arch->arch_name == NULL || strcmp(skyeye_config.arch->arch_name, "arm") != 0 || (query != NULL && max_query < 0x35) || (bautoselect == NULL && wautoselect == NULL)) { PRINT("*** ERROR: Unsupported architecture !!!\n"); return -1; } io = (struct flash_am29_io*)malloc(sizeof(struct flash_am29_io)); if (io == NULL) return -1; io->query = query; io->max_query = max_query; io->bautoselect = bautoselect; io->wautoselect = wautoselect; if (chip_size == 0 && query != NULL) io->chip_size = (0x1 << query[0x27]); else io->chip_size = chip_size; if (sector_size == 0 && query != NULL) io->sector_size = io->chip_size / max(((uint32_t)query[0x34] << 8) | (uint32_t)query[0x33], 1); else io->sector_size = sector_size; DEBUG("chip_size:%dM, sector_size:%dK\n", io->chip_size >> 20, io->sector_size >> 10); if (dev->size != io->chip_size) { PRINT("*** ERROR: Only support %dM flash !!!\n", io->chip_size >> 20); free(io); return -1; } dev->fini = flash_am29_fini; dev->reset = flash_am29_reset; dev->update = flash_am29_update; dev->read_byte = flash_am29_read_byte; dev->write_byte = flash_am29_write_byte; dev->read_halfword = flash_am29_read_halfword; dev->write_halfword = flash_am29_write_halfword; dev->read_word = flash_am29_read_word; dev->write_word = flash_am29_write_word; dev->data = (void*)io; flash_am29_reset(dev); return 0; } static uint16_t am29lv160_query[0x4d] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 0 - 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 5 - 9 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* a - e */ 0x0000, /* f */ 0x0051, 0x0052, 0x0059, /* 10 - 12 : QRY*/ 0x0002, 0x0000, /* 13 - 14 */ 0x0040, 0x0000, /* 15 - 16 */ 0x0000, 0x0000, /* 17 - 18 */ 0x0000, 0x0000, /* 19 - 1a */ 0x0027, /* 1b */ 0x0036, /* 1c */ 0x0000, /* 1d */ 0x0000, /* 1e */ 0x0004, /* 1f */ 0x0000, /* 20 */ 0x000a, /* 21 */ 0x0000, /* 22 */ 0x0005, /* 23 */ 0x0000, /* 24 */ 0x0004, /* 25 */ 0x0000, /* 26 */ 0x0015, /* 27 : Device Size = 2^N Bytes */ 0x0002, 0x0000, /* 28 - 29 */ 0x0000, 0x0000, /* 2a - 2b */ 0x0004, /* 2c */ 0x0000, 0x0000, 0x0040, 0x0000, /* 2d - 30 */ 0x0001, 0x0000, 0x0020, 0x0000, /* 31 - 34 */ 0x0000, 0x0000, 0x0080, 0x0000, /* 35 - 38 */ 0x001e, 0x0000, 0x0000, 0x0001, /* 39 - 3c */ 0x0000, 0x0000, 0x0000, /* 3d - 3f */ 0x0050, 0x0052, 0x0049, /* 40 - 42 : PRI */ 0x0031, /* 43 */ 0x0030, /* 44 */ 0x0000, /* 45 */ 0x0002, /* 46 */ 0x0001, /* 47 */ 0x0001, /* 48 */ 0x0004, /* 49 */ 0x0000, /* 4a */ 0x0000, /* 4b */ 0x0000, /* 4c */ }; static void flash_am29lv160_bautoselect(struct flash_am29_io *io, uint32_t offset, uint8_t *data) { switch (offset & 0xff) { case 0: *data = 0x1; break; case 2: *data = (strncmp(io->type, "Am29LV160T", 10) == 0 ? 0xc4 : 0x49); break; // case 4: *data = 0x1; break; /* write-protected */ default: *data = 0x0; break; } } static void flash_am29lv160_wautoselect(struct flash_am29_io *io, uint32_t offset, uint16_t *data) { switch (offset & 0xff) { case 0: *data = 0x1; break; case 1: *data = (strncmp(io->type, "Am29LV160T", 10) == 0 ? 0x22c4 : 0x2249); break; // case 2: *data = 0x1; break; /* write-protected */ default: *data = 0x0; break; } } static void flash_am29lv800_bautoselect(struct flash_am29_io *io, uint32_t offset, uint8_t *data) { switch (offset & 0xff) { case 0: *data = 0x1; break; case 2: *data = (strncmp(io->type, "Am29LV800T", 10) == 0 ? 0xda : 0x5b); break; // case 4: *data = 0x1; break; /* write-protected */ default: *data = 0x0; break; } } static void flash_am29lv800_wautoselect(struct flash_am29_io *io, uint32_t offset, uint16_t *data) { switch (offset & 0xff) { case 0: *data = 0x1; break; case 1: *data = (strncmp(io->type, "Am29LV800T", 10) == 0 ? 0x22da : 0x225b); break; // case 2: *data = 0x1; break; /* write-protected */ default: *data = 0x0; break; } } static int flash_am29lv160_setup(struct device_desc *dev) { int ret = -1; if (strlen(dev->type) >= 12) { if (strcmp(&dev->type[strlen(dev->type) - 2], "-8") == 0) ret = flash_am29_setup(dev, am29lv160_query, 0x4d, flash_am29lv160_bautoselect, NULL, 0, 0); else if (strcmp(&dev->type[strlen(dev->type) - 3], "-16") == 0) ret = flash_am29_setup(dev, am29lv160_query, 0x4d, NULL, flash_am29lv160_wautoselect, 0, 0); } if (ret == 0) memcpy(&((struct flash_am29_io*)(dev->data))->type[0], &dev->type[0], MAX_STR_NAME); DEBUG("Setup %s, ret:%d\n", dev->type, ret); return ret; } static int flash_am29lv800_setup(struct device_desc *dev) { int ret = -1; if (strlen(dev->type) >= 12) { if (strcmp(&dev->type[strlen(dev->type) - 2], "-8") == 0) ret = flash_am29_setup(dev, NULL, 0, flash_am29lv800_bautoselect, NULL, 0x100000, 0x10000); else if (strcmp(&dev->type[strlen(dev->type) - 3], "-16") == 0) ret = flash_am29_setup(dev, NULL, 0, NULL, flash_am29lv800_wautoselect, 0x100000, 0x10000); } if (ret == 0) memcpy(&((struct flash_am29_io*)(dev->data))->type[0], &dev->type[0], MAX_STR_NAME); DEBUG("Setup %s, ret:%d\n", dev->type, ret); return ret; } void flash_am29_init(struct device_module_set *mod_set) { register_device_module("Am29LV160T-8", mod_set, &flash_am29lv160_setup); register_device_module("Am29LV160B-8", mod_set, &flash_am29lv160_setup); register_device_module("Am29LV160T-16", mod_set, &flash_am29lv160_setup); register_device_module("Am29LV160B-16", mod_set, &flash_am29lv160_setup); register_device_module("Am29LV800T-8", mod_set, &flash_am29lv800_setup); register_device_module("Am29LV800B-8", mod_set, &flash_am29lv800_setup); register_device_module("Am29LV800T-16", mod_set, &flash_am29lv800_setup); register_device_module("Am29LV800B-16", mod_set, &flash_am29lv800_setup); } skyeye-1.2.5_REL/device/flash/dev_flash_intel.c0000644000175000001440000004311110555732132020067 0ustar kshusers/* dev_flash_intel.c - skyeye intel flash simulation Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 09/22/2005 rewrite for new framework * walimis * * ywc 2005-01-21 add for flash simulation * core flash simulation source code from ipaqsim * Thanks to ipaqsim's AUTHOR(s): Ye Wen (wenye@cs.ucsb.edu) */ #include #include "armdefs.h" #include "armmem.h" #include "dev_flash_intel.h" //chy 2006-08-12 extern mem_bank_t *global_mbp; extern mem_bank_t * bank_ptr (ARMword addr); /*ywc 2005-04-01*/ void init_querytable (); static u32 query[INTEL_QUERYTABLE_SIZE]; /* query table */ /* return the lock bit */ #define ISLOCKED(x) (io->lock[(x)>>FLASH_SECTOR_SHIFT]) #define ADDR_SUSPENDED(x) \ ((io->program_suspended && ((x) == io->program_latch_addr)) || \ (io->progbuf_suspended && (((x) >= io->pb_start) && ((x) < (io->pb_start+io->pb_count)))) || \ (io->erase_suspended && (((x) & FLASH_SECTOR_MASK) == (io->erase_latch_addr & FLASH_SECTOR_MASK))) ) #define DEVICE_SUSPENDED (io->program_suspended || io->progbuf_suspended || io->erase_suspended) void flash_intel_reset (struct device_desc *dev) { struct flash_device *flash_dev = (struct flash_device *) dev->dev; struct flash_intel_io *io = (struct flash_intel_io *) dev->data; unsigned int i; io->size = INTEL28F128J3A_SIZE; io->lock = malloc (io->size / FLASH_SECTOR_SIZE); if (io->lock == NULL) { printf ("\nflash memory lock allocation failed"); /* exit */ } for (i = 0; i < io->size / FLASH_SECTOR_SIZE; i++) { io->lock[i] = 0; } io->read_mode = WSM_READ_ARRAY; io->wsm_mode = WSM_READY; io->program_busy = io->progbuf_busy = io->erase_busy = io->lock_busy = 0; io->program_suspended = io->progbuf_suspended = io->erase_suspended = 0; io->protection_error = io->program_setlb_error = io->erase_clearlb_error = io->program_volt_error = 0; //io->vpen = 0; /* disable program/erase */ io->vpen = 1; /* enable program/erase */ io->pb_count = io->pb_loaded = 0; init_querytable (); } static void flash_intel_fini (struct device_desc *dev) { struct flash_intel_io *io = (struct flash_intel_io *) dev->data; if (!dev->dev) free (dev->dev); if (!io) free (io); } int flash_intel_read_byte (struct device_desc *dev, u32 addr, u8 * data) { struct machine_config *mc = (struct machine_config *) dev->mach; ARMul_State *state = (ARMul_State *) mc->state; u32 temp, offset; int ret = ADDR_HIT; flash_intel_read_word (dev, addr, &temp); offset = (((u32) state->bigendSig * 3) ^ (addr & 3)) << 3; *data = (temp >> offset & 0xffL); return ret; } int flash_intel_read_halfword (struct device_desc *dev, u32 addr, u16 * data) { struct machine_config *mc = (struct machine_config *) dev->mach; ARMul_State *state = (ARMul_State *) mc->state; u32 temp, offset; int ret = ADDR_HIT; flash_intel_read_word (dev, addr, &temp); offset = (((u32) state->bigendSig * 2) ^ (addr & 2)) << 3; *data = (temp >> offset & 0xffffL); return ret; } int flash_intel_read_word (struct device_desc *dev, u32 addr, u32 * data) { struct flash_device *flash_dev = (struct flash_device *) dev->dev; struct flash_intel_io *io = (struct flash_intel_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; ARMul_State *state = (ARMul_State *) mc->state; int ret = ADDR_HIT; u32 temp; switch (io->read_mode) { case WSM_READ_ARRAY: /* read flash */ //data = mem[WORD_ADDR(addr)]; //chy 2006-08-12 fig bug: not set global_mbp before real_read/write_byte/word. global_mbp = bank_ptr (addr); *data = real_read_word (state, addr); //data = state->mem.rom[mbp - skyeye_config.mem.mem_banks][(addr- mbp->addr)>>2]; break; case WSM_READ_ID: //read IDs temp = WORD_ADDR (addr) & 0x00000001; if (temp == 0) { *data = BOTHCHIP (INTEL_MANUFACTURER_CODE); } //manu. ID else if (temp == 1) { *data = BOTHCHIP (INTEL_28F128J3A_DEVICE_CODE); } // device ID else if (((addr & FLASH_SECTOR_OFF) >> WORD_SHIFT) == 2) //read lock state *data = BOTHCHIP (ISLOCKED (addr) & 0x1); else { *data = 0; printf ("\nFlash: read ID error: unknown address 0x%x\n", addr); } break; case WSM_READ_STATUS: /* read status register */ /* first get the WSM busy/ready state */ temp = !io->program_busy && !io->progbuf_busy && !io->lock_busy && !io->erase_busy; /* suppose no voltage error */ *data = BOTHCHIP ((temp << 7) | (io->erase_suspended << 6) | (io->erase_clearlb_error << 5) | (io->program_setlb_error << 4) | (io->program_volt_error << 3) | (io->program_suspended << 2) | (io-> protection_error) << 1); break; case WSM_READ_QUERY: // read query table //temp = WORD_ADDR(addr); temp = WORD_ADDR (addr & 0x0000ffff); *data = (temp < INTEL_QUERYTABLE_SIZE) ? query[temp] : 0; break; default: printf ("\nFlash: invalid read mode: %d", io->read_mode); *data = 0; break; } return ret; } int flash_intel_write_byte (struct device_desc *dev, u32 addr, u8 data) { int ret = ADDR_HIT; printf ("\nFlash in current config does not support halfword write at 0x%x", addr); return ret; } int flash_intel_write_halfword (struct device_desc *dev, u32 addr, u16 data) { int ret = ADDR_HIT; printf ("\nFlash in current config does not support byte write at 0x%x", addr); return ret; } /* initialize a new WSM command sequence */ void init_wsm (struct device_desc *dev, u32 addr, u32 data) { struct flash_intel_io *io = (struct flash_intel_io *) dev->data; /* maybe we don't need to care the data symmetry */ //CHECK_DATA_VALID(data); /* * No timing support now, so Suspend/Resume has no effect * July 1st, 2004 Ye Wen */ int i; u32 cmd = data & 0xff; switch (cmd) { case WSM_READ_ARRAY: io->read_mode = WSM_READ_ARRAY; break; case WSM_READ_ID: io->read_mode = WSM_READ_ID; break; case WSM_READ_STATUS: io->read_mode = WSM_READ_STATUS; break; case WSM_READ_QUERY: io->read_mode = WSM_READ_QUERY; break; case WSM_CLEAR_STATUS: io->protection_error = io->program_setlb_error = io->erase_clearlb_error = io->program_volt_error = 0; // is this right? I can't see it from spec. // but the bootldr code implies this. Check // program_flash_region in bootldr.c // -July 28, 2004 Ye Wen io->read_mode = WSM_READ_ARRAY; break; case WSM_PROGRAM: case WSM_PROGRAM2: io->wsm_mode = WSM_PROGRAM; break; case WSM_WRITE_BUFFER: io->wsm_mode = WSM_WRITE_BUFFER; io->read_mode = WSM_READ_STATUS; io->pb_count = io->pb_loaded = 0; for (i = 0; i < INTEL_WRITEBUFFER_SIZE; i++) io->pb_buf[i] = 0xffffffff; break; case WSM_BLOCK_ERASE: io->wsm_mode = WSM_BLOCK_ERASE; break; case WSM_SUSPEND: if (io->program_busy) io->program_suspended = 1; else if (io->progbuf_busy) io->progbuf_suspended = 1; else if (io->erase_busy) io->erase_suspended = 1; else { //ywc //printf("\nFlash: nothing busy for suspending"); } break; case WSM_RESUME: if (io->program_suspended) io->program_suspended = 0; else if (io->progbuf_suspended) io->progbuf_suspended = 0; else if (io->erase_suspended) io->erase_suspended = 0; else { //ywc //printf("\nFlash: nothing to resume"); } break; case WSM_LOCK_ACCESS: io->wsm_mode = WSM_LOCK_ACCESS; break; case WSM_CONFIG: case WSM_PROTECT: printf ("\nFlash: command 0x%x not supported yet", cmd); break; default: //ywc //printf("\nFlash: command 0x%x unrecognized", cmd); break; } } int flash_intel_write_word (struct device_desc *dev, u32 addr, u32 data) { struct machine_config *mc = (struct machine_config *) dev->mach; struct flash_intel_io *io = (struct flash_intel_io *) dev->data; ARMul_State *state = (ARMul_State *) mc->state; unsigned int i; int ret = ADDR_HIT; u32 j; //CHECK_ADDR_RANGE(addr); //fprintf(stderr,"SKYEYE flash write begin: addr %x data %x\n", addr,data); switch (io->wsm_mode) { case WSM_READY: init_wsm (dev, addr, data); break; case WSM_WRITE_BUFFER: if (io->pb_count == 0) { /* step 1: get count */ io->pb_count = (data & 0xff) + 1; io->progbuf_latch_addr = addr; //fprintf(stderr,"SKYEYE flash write step 1: count %x addr %x\n",io->pb_count, addr); if (io->pb_count > INTEL_WRITEBUFFER_SIZE) { io->program_setlb_error = io->erase_clearlb_error = 1; io->wsm_mode = WSM_READY; printf ("\nFlash: buffer program count too large: %d", io->pb_count); break; } if (SECTOR_ADDR (addr) != SECTOR_ADDR (addr + io->pb_count - 1)) { io->program_setlb_error = io->erase_clearlb_error = 1; io->wsm_mode = WSM_READY; printf ("\nFlash: buffer program address range across sectors: 0x%x-0x%x", addr, addr + io->pb_count - 1); break; } break; } if (io->pb_loaded < io->pb_count) { /* step 2: load data */ if (SECTOR_ADDR (addr) != SECTOR_ADDR (io->progbuf_latch_addr)) { io->program_setlb_error = io->erase_clearlb_error = 1; io->wsm_mode = WSM_READY; printf ("\nFlash: buffer program address across sectors: 0x%x", addr); break; } if (io->pb_loaded == 0) io->pb_start = addr; io->pb_buf[WORD_ADDR (addr) & INTEL_WRITEBUFFER_MASK] = data; io->pb_loaded++; break; } //fprintf(stderr,"SKYEYE flash write step 2: load data: start_addr %x, count %x\n",io->pb_start, io->pb_loaded); if ((data & 0xff) == WSM_CONFIRM) { /* step 3: confirm the program */ io->progbuf_busy = 1; io->read_mode = WSM_READ_STATUS; /* copy buffer to flash */ if (ISLOCKED (io->progbuf_latch_addr)) { printf ("\nFlash: buffer program locked address [0x%x]", io->progbuf_latch_addr); io->program_setlb_error = io->protection_error = 1; } else if (DEVICE_SUSPENDED) { printf ("\nFlash: buffer program suspended device"); io->program_setlb_error = 1; } else if (io->vpen != 1) { printf ("\nFlash: can't buffer program when VPEN low"); io->program_setlb_error = io->program_volt_error = 1; } else { //fprintf(stderr,"SKYEYE flash write step 3: confirm: \n"); for (j = WORD_ADDR (io->pb_start); j < WORD_ADDR (io->pb_start) + INTEL_WRITEBUFFER_SIZE; j++){ //mem[j] &= io->pb_buf[j & INTEL_WRITEBUFFER_MASK]; //chy 2006-08-12 fix bug: not set global_mbp before real_read/write_byte/word. //chy 2006-08-13 fix bug: j =real_addr >>2. should be j<<2 global_mbp = bank_ptr (j<pb_buf[j & INTEL_WRITEBUFFER_MASK]); } } io->wsm_mode = WSM_READY; io->progbuf_busy = 0; break; } else { printf ("\nFlash: buffer program with wrong cmd sequence: 0x%x", data); io->program_setlb_error = io->erase_clearlb_error = 1; io->wsm_mode = WSM_READY; break; } break; case WSM_PROGRAM: case WSM_PROGRAM2: io->program_busy = 1; io->program_latch_addr = addr; io->program_latch_data = data; io->read_mode = WSM_READ_STATUS; if (ISLOCKED (io->program_latch_addr)) { printf ("\nFlash: program locked address [0x%x]=0x%x", addr, data); io->program_setlb_error = io->protection_error = 1; } else if (ADDR_SUSPENDED (io->program_latch_addr)) { printf ("\nFlash: program suspended address [0x%x]=0x%x", addr, data); io->program_setlb_error = 1; } else if (io->vpen != 1) { printf ("\nFlash: can't program when VPEN low"); io->program_setlb_error = io->program_volt_error = 1; } else { //mem[WORD_ADDR(io->program_latch_addr)] &= data; //chy 2006-08-12 fig bug: not set global_mbp before real_read/write_byte/word. global_mbp = bank_ptr (io->program_latch_addr); real_write_word (state, io->program_latch_addr, real_read_word (state, io-> program_latch_addr) & data); } io->program_busy = 0; io->wsm_mode = WSM_READY; break; case WSM_BLOCK_ERASE: if ((data & 0xff) == WSM_CONFIRM) { io->erase_busy = 1; io->erase_latch_addr = addr & FLASH_SECTOR_MASK; io->read_mode = WSM_READ_STATUS; if (ISLOCKED (io->erase_latch_addr)) { printf ("\nFlash: erase locked address [0x%x]", io->erase_latch_addr); io->erase_clearlb_error = io->protection_error = 1; } else if (DEVICE_SUSPENDED) { printf ("\nFlash: erase suspended device"); io->erase_clearlb_error = 1; } else if (io->vpen != 1) { printf ("\nFlash: can't erase when VPEN low\n"); io->erase_clearlb_error = io->program_volt_error = 1; } else { for (i = 0; i < WORD_ADDR (FLASH_SECTOR_SIZE); i++) { //mem[WORD_ADDR(io->erase_latch_addr)+i] = 0xffffffff; //chy 2006-08-12 fig bug: not set global_mbp before real_read/write_byte/word. global_mbp = bank_ptr (io->erase_latch_addr +(i<erase_latch_addr +(i<erase_busy = 0; io->wsm_mode = WSM_READY; break; } else { printf ("\nFlash: erase with wrong cmd sequence: 0x%x", data); io->wsm_mode = WSM_READY; break; } break; case WSM_LOCK_ACCESS: if ((data & 0xff) == 0x01) { /* set lock bit */ io->lock_busy = 1; io->read_mode = WSM_READ_STATUS; if (DEVICE_SUSPENDED) { printf ("\nFlash: set lock on suspended device"); io->program_setlb_error = 1; } else if (io->vpen != 1) { printf ("\nFlash: can't set lock when VPEN low"); io->program_setlb_error = io->program_volt_error = 1; } else { io->lock[SECTOR_ADDR (addr)] = 1; } io->lock_busy = 0; io->wsm_mode = WSM_READY; break; } else if ((data & 0xff) == WSM_CONFIRM) { /* clear all lock bits */ io->lock_busy = 1; io->read_mode = WSM_READ_STATUS; if (DEVICE_SUSPENDED) { printf ("\nFlash: clear locks on suspended device"); io->erase_clearlb_error = 1; } else if (io->vpen != 1) { printf ("\nFlash: can't clear locks when VPEN low"); io->erase_clearlb_error = io->program_volt_error = 1; } else { for (i = 0; i < io->size / FLASH_SECTOR_SIZE; i++) io->lock[i] = 0; } io->lock_busy = 0; io->wsm_mode = WSM_READY; break; } else { printf ("\nFlash: lock access with wrong cmd sequence: 0x%x", data); io->wsm_mode = WSM_READY; break; } break; default: printf ("\nFlash: Can't recognize WSM mode: 0x%x", io->wsm_mode); break; } return ret; } void init_querytable () { int i; for (i = 0; i < INTEL_QUERYTABLE_SIZE; i++) { query[i] = 0; } /* * This is a dump of a real 28F128J3A flash query table * Lines with a "*": different from Verilog model (Ref.2) * Lines with a "+": different from the spec (Ref.1) */ query[0x00] = 0x00890089; //manu. ID //query[0x01] = 0x00170017; //device ID query[0x01] = 0x00180018; //device ID query[0x02] = 0x00010001; //? query[0x10] = 0x00510051; //"Q" query[0x11] = 0x00520052; //"R" query[0x12] = 0x00590059; //"Y" query[0x13] = 0x00010001; query[0x15] = 0x00310031; query[0x1b] = 0x00270027; query[0x1c] = 0x00360036; query[0x1f] = 0x00070007; query[0x20] = 0x00070007; query[0x21] = 0x000A000A; query[0x23] = 0x00040004; query[0x24] = 0x00040004; query[0x25] = 0x00040004; query[0x27] = 0x00180018; //2^(0x18) = 2^24 = 16MByte 28F128 flash chip size //query[0x27] = 0x00170017; query[0x28] = 0x00020002; query[0x2a] = 0x00050005; //2^5 = 32 write buffer size query[0x2c] = 0x00010001; //symmetrically-blocked query[0x2d] = 0x007F007F; //[31,16]=?(128KByte) ;[15,0]=block number query[0x30] = 0x00020002; query[0x31] = 0x00500050; //"P" query[0x32] = 0x00520052; //"R" query[0x33] = 0x00490049; //"I" query[0x34] = 0x00310031; query[0x35] = 0x00320032; // * query[0x36] = 0x00CE00CE; // * query[0x3a] = 0x00010001; query[0x3b] = 0x00010001; query[0x3c] = 0x00010001; query[0x3d] = 0x00330033; query[0x3f] = 0x00010001; query[0x40] = 0x00000000; // + query[0x41] = 0x00010001; // + query[0x42] = 0x00030003; query[0x43] = 0x00030003; query[0x44] = 0x00030003; } static int flash_intel_setup (struct device_desc *dev) { int i; struct flash_intel_io *io; struct device_interrupt *intr = &dev->intr; dev->fini = flash_intel_fini; dev->reset = flash_intel_reset; //dev->update = flash_intel_update; dev->read_byte = flash_intel_read_byte; dev->write_byte = flash_intel_write_byte; dev->read_halfword = flash_intel_read_halfword; dev->write_halfword = flash_intel_write_halfword; dev->read_word = flash_intel_read_word; dev->write_word = flash_intel_write_word; io = (struct flash_intel_io *) malloc (sizeof (struct flash_intel_io)); memset (io, 0, sizeof (struct flash_intel_io)); if (io == NULL) return 1; dev->data = (void *) io; flash_intel_reset (dev); /* see if we need to set default values. * */ //set_device_default (dev, intel_flash_def); return 0; } void flash_intel_init (struct device_module_set *mod_set) { int i; register_device_module ("28F128J3A", mod_set, &flash_intel_setup); } skyeye-1.2.5_REL/device/flash/dev_flash_intel.h0000644000175000001440000001216710541455476020113 0ustar kshusers//ywc 2005-1-21 for flash simulation //core flash simulation source code from ipaqsim //Thanks to ipaqsim's AUTHOR(s): Ye Wen (wenye@cs.ucsb.edu) #include //#include "sadefs.h" //#include "memory.h" //#define INTEL28F640J3A_SIZE (0x800000 * 2) /* 28F640J3A: 8M * 2 */ #define INTEL28F128J3A_SIZE (0x1000000 * 2) /* 28F128J3A: 16M * 2 */ #define INTEL_MANUFACTURER_CODE (0x0089) /* Intel flash */ //#define INTEL_28F640J3A_DEVICE_CODE (0x0017) /* for 28F640J3A */ #define INTEL_28F128J3A_DEVICE_CODE (0x0018) /* for 28F128J3A */ #define INTEL_WRITEBUFFER_SIZE (0x10) /* 16 words */ #define INTEL_WRITEBUFFER_MASK (0xf) /* apply to word address */ /* * It is not clear how large the query table is. * I choose the largest value from the spec (Ref.1). */ #define INTEL_QUERYTABLE_SIZE (0x47) /* query table size: word size */ /* 128KB x 2 */ #define FLASH_SECTOR_SIZE (0x40000) //#define FLASH_SECTOR_NUM (INTEL28F640J3A_SIZE/FLASH_SECTOR_SIZE) #define FLASH_SECTOR_NUM (INTEL28F128J3A_SIZE/FLASH_SECTOR_SIZE) #define FLASH_SECTOR_MASK (0xfffc0000) #define FLASH_SECTOR_OFF (0x3ffff) #define FLASH_SECTOR_SHIFT (18) #define SECTOR_ADDR(x) ((x) >> FLASH_SECTOR_SHIFT) /* get sector number */ /* command code is also used as the WSM state value */ #define WSM_READ_ARRAY (0xff) /* default mode: read array */ #define WSM_READ_ID (0x90) /* read ID codes */ #define WSM_READ_STATUS (0x70) /* read status register */ #define WSM_CLEAR_STATUS (0x50) /* clear status register */ #define WSM_READ_QUERY (0x98) /* read query */ #define WSM_WRITE_BUFFER (0xe8) /* write to buffer */ #define WSM_PROGRAM (0x40) /* word program */ #define WSM_PROGRAM2 (0x10) /* alternative of word program */ #define WSM_BLOCK_ERASE (0x20) /* block erase (0xd0) */ #define WSM_SUSPEND (0xB0) /* blcok erase/program suspend */ #define WSM_RESUME (0xD0) /* blcok erase/program resume */ #define WSM_CONFIG (0xB8) /* configuration */ #define WSM_LOCK_ACCESS (0x60) /* set(0x01)/clear(0xD0) block lock-bit */ #define WSM_PROTECT (0xC0) /* protection program */ #define WSM_CONFIRM (0xD0) /* buffer program/erase confirm */ #define WSM_READY (0x00) /* default state of WSM, ready for new command */ /* status bits */ #define FLASH_STATUS_WSMS (1 << 7) /* WSM ready */ #define FLASH_STATUS_ESS (1 << 6) /* erase suspended */ #define FLASH_STATUS_ECLBS (1 << 5) /* erase/clear lock-bit error */ #define FLASH_STATUS_PSLBS (1 << 4) /* program/set lock-bit error */ #define FLASH_STATUS_VPENS (1 << 3) /* programming voltage low */ #define FLASH_STATUS_PSS (1 << 2) /* program suspended */ #define FLASH_STATUS_DPS (1 << 1) /* block locked, operation aborted */ /* XSR bits */ #define FLASH_XSR_WBS (1 << 7) /* write buffer available */ /* * Since there are 2 chips of 16-bit flash, the data * sent to bus should be sth. like 0x00uv00uv. This * macro is used to check the validity of the data * to ensure same command is sent to the two chips. */ #define CHIP_DATA_VALID(x) ( ((x) & 0xffff) == (((x) >> 16) & 0xffff) ) /* #define CHECK_DATA_VALID(x) \ do { \ if (!CHIP_DATA_VALID(x)) { \ printf("\ndata commands sent to two chips are different: 0x%x", x); \ return SUCCESS; \ } \ }while (0) */ /* make 32-bit data output for both chips when ID or Query is read */ #define BOTHCHIP(x) ((((x)&0xffff)<<16)|((x)&0xffff)) /* return the lock bit */ //#define ISLOCKED(x) (this->lock[(x)>>FLASH_SECTOR_SHIFT]) /* #define ADDR_SUSPENDED(x) \ ((program_suspended && ((x) == program_latch_addr)) || \ (progbuf_suspended && (((x) >= pb_start) && ((x) < (pb_start+pb_count)))) || \ (erase_suspended && (((x) & FLASH_SECTOR_MASK) == (erase_latch_addr & FLASH_SECTOR_MASK))) ) #define DEVICE_SUSPENDED (program_suspended || progbuf_suspended || erase_suspended) */ #define SUCCESS ( 0) /* integer return values */ #define FAILURE (-1) #ifndef WORD_SIZE #define WORD_SIZE 4 #endif #define WORD_SHIFT 2 #define WORD_ADDR(x) ((x) >> WORD_SHIFT) #ifndef ARMWord typedef unsigned int ARMWord; #endif #ifndef ARMByte typedef unsigned char ARMByte; #endif #ifndef ARMAddr typedef ARMWord ARMAddr; #endif typedef struct flash_intel_io { u8 *lock; /* sector lock */ u32 size; /* byte size */ u32 read_mode; /* mode for read operation */ u32 wsm_mode; /* write state machine */ /* VPEN pin: should controlled by EGPIO ??? */ u8 vpen; /* latch address&data for each handlers */ u32 program_latch_addr; u32 program_latch_data; u32 progbuf_latch_addr; u32 erase_latch_addr; /* * stateful information for buffer program handler */ /* total count and number to be loaded/programmed */ u32 pb_count, pb_loaded; u32 pb_start; /* start address */ u32 pb_buf[INTEL_WRITEBUFFER_SIZE]; /* write buffer */ /* * state bits for handlers: program, buffer program, erase, lock * xxxx_busy: whether WSM is busy on the handler * xxxx_suspended: whether the handler is suspended * xxxx_error: operation errors */ u8 program_busy, progbuf_busy, erase_busy, lock_busy; u8 program_suspended, progbuf_suspended, erase_suspended; u8 protection_error, program_setlb_error, erase_clearlb_error, program_volt_error; } flash_intel_io_t; skyeye-1.2.5_REL/device/flash/skyeye_flash.h0000644000175000001440000000277610606502134017442 0ustar kshusers/* skyeye_flash.h - skyeye general flash device file support functions Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __SKYEYE_FLASH_H_ #define __SKYEYE_FLASH_H_ #include "skyeye_device.h" struct flash_device { int mod; char dump[MAX_STR_NAME]; void *state; void *priv; int (*flash_open) (struct flash_device * flash_dev); int (*flash_close) (struct flash_device * flash_dev); int (*flash_update) (struct flash_device * flash_dev); int (*flash_read) (struct flash_device * flash_dev, void *buf, size_t count); int (*flash_write) (struct flash_device * flash_dev, void *buf, size_t count); }; /* helper functions */ int skyeye_flash_dump (const char *filename, uint32_t base, uint32_t size); #endif /*__SKYEYE_FLASH_H_*/ skyeye-1.2.5_REL/REPORTING-BUGS0000644000175000001440000000020310651575124014271 0ustar kshusers Please report bug in the following URL: http://sourceforge.net/tracker/?group_id=85554&atid=576533 -- Thank you skyeye-1.2.5_REL/MAINTAINERS0000644000175000001440000000220310610155067013731 0ustar kshusers List of maintainers and how to submit your patch SUBMIT PATCH: For the developer of SkyEye(who has commit privilege of SkyEye cvs repository): If you just fix a bug or add some improvement based on the existed code of SkyEye. You can send your patch to skyeye developer maillist(Now it is skyeye-developer@lists.gro.clinux.org).If no one give different opinions for your patch, you can commit it by yourself. For the new bie of SkyEye(who have no privilege of SkyEye cvs repository): You can send your patch to the following MAINTAINERS list after you test your patch on the newest SkyEye version. Global MAINTAINERS: Chen Yu ( chyyuu@gmail.com ) Michael Kang ( blackfin.kang@gmail.com ) Key Developers: Wang Liming ( walimisdev@gmail.com ) Yang Ye Tea Water Kang Shuo Main Developer: Ying Wen Chao Yang Jian Liu Yuhong Trilok Soni Koodailar Zeng Yi Lu Zhe Tao Li Ming Ying Sou Yi Wang Yong Hao Zhang Zhi Chao Yang Ji Long Shi Yang Cai Qiang Luo Hui Song zhenyu Contributors: Wen Ye Benno Simone Zinanni Stefano Fedrigo Lian Zhu Lin Anthony Lee skyeye-1.2.5_REL/Makefile.in0000644000175000001440000006113611023514464014312 0ustar kshusers# Makefile.in generated by automake 1.10 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ target_triplet = @target@ bin_PROGRAMS = skyeye$(EXEEXT) subdir = . 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old/uClinux-dist/linux-2.4.x/arch/armnommu/config.in 2004-04-08 08:15:01.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/config.in 2005-01-06 09:12:11.000000000 +0800 @@ -56,6 +56,7 @@ Triscend-A7V CONFIG_ARCH_TA7V \ SWARM CONFIG_ARCH_SWARM \ Samsung CONFIG_ARCH_SAMSUNG \ + LPC CONFIG_ARCH_LPC \ Atmel CONFIG_ARCH_ATMEL" TI-DSC21 if [ "$CONFIG_ARCH_TA7V" = "y" ]; then @@ -225,6 +226,15 @@ define_hex FLASH_SIZE 0x00100000 fi +if [ "$CONFIG_ARCH_LPC" = "y" ]; then + define_bool CONFIG_NO_PGT_CACHE y + define_bool CONFIG_CPU_ARM710 y + define_bool CONFIG_CPU_32 y + define_bool CONFIG_CPU_32v4 y + define_bool CONFIG_CPU_WITH_CACHE n + define_bool CONFIG_CPU_WITH_MCR_INSTRUCTION n +fi + if [ "$CONFIG_ARCH_ATMEL" = "y" ]; then define_bool CONFIG_NO_PGT_CACHE y define_bool CONFIG_CPU_ARM710 y @@ -548,6 +558,7 @@ "$CONFIG_ARCH_PERSONAL_SERVER" = "y" -o \ "$CONFIG_ARCH_CATS" = "y" -o \ "$CONFIG_ARCH_ATMEL" = "y" -o \ + "$CONFIG_ARCH_LPC" = "y" -o \ "$CONFIG_ARCH_NETARM" = "y" -o \ "$CONFIG_ARCH_SAMSUNG" = "y" -o \ "$CONFIG_ARCH_TA7S" = "y" -o \ diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/defconfig uClinux-dist/linux-2.4.x/arch/armnommu/defconfig --- old/uClinux-dist/linux-2.4.x/arch/armnommu/defconfig 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/defconfig 2005-01-06 09:15:59.000000000 +0800 @@ -0,0 +1,320 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_ARM=y +# CONFIG_SBUS is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_UCLINUX=y +MAGIC_ROM_PTR=y + +# +# Code maturity level options +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# System Type +# +# CONFIG_ARCH_DSC21 is not set +# CONFIG_ARCH_C5471 is not set +# CONFIG_ARCH_CNXT is not set +# CONFIG_ARCH_NETARM is not set +# CONFIG_ARCH_TA7S is not set +# CONFIG_ARCH_TA7V is not set +# CONFIG_ARCH_SWARM is not set +# CONFIG_ARCH_SAMSUNG is not set +CONFIG_ARCH_LPC=y +# CONFIG_ARCH_ATMEL is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SET_MEM_PARAM=y +DRAM_BASE=81000000 +DRAM_SIZE=00800000 +FLASH_MEM_BASE=80000000 +FLASH_SIZE=00200000 +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_NO_PGT_CACHE=y +CONFIG_CPU_ARM710=y +CONFIG_CPU_32=y +CONFIG_CPU_32v4=y +# CONFIG_CPU_WITH_CACHE is not set +# CONFIG_CPU_WITH_MCR_INSTRUCTION is not set + +# +# General setup +# +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +# CONFIG_NET is not set +# CONFIG_SYSVIPC is not set +# CONFIG_REDUCED_MEMORY is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set +# CONFIG_NWFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_KERNEL_ELF=y +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="root=/dev/ram" +# CONFIG_ALIGNMENT_TRAP is not set +# CONFIG_RAM_ATTACHED_ROMFS is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_CISS_MONITOR_THREAD is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_RAMDISK_DATA is not set +# CONFIG_BLK_DEV_BLKMEM is not set +# CONFIG_BLK_STATS is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_QFMT_V2 is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +CONFIG_ROMFS_FS=y +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_SMB_FS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Character devices +# +# CONFIG_LEDMAN is not set +# CONFIG_DS1302 is not set +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_SERIAL_TA7=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set +# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set + +# +# Controller Area Network Cards/Chips +# +# CONFIG_CAN4LINUX is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set + +# +# Direct Rendering Manager (XFree86 DRI support) +# +# CONFIG_DRM is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Support for USB gadgets +# +# CONFIG_USB_GADGET is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +# CONFIG_REVISIT is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_INFO=y +# CONFIG_MAGIC_SYSRQ is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZLIB_DEFLATE is not set diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/def-configs/lpc2200 uClinux-dist/linux-2.4.x/arch/armnommu/def-configs/lpc2200 --- old/uClinux-dist/linux-2.4.x/arch/armnommu/def-configs/lpc2200 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/def-configs/lpc2200 2005-01-06 09:12:11.000000000 +0800 @@ -0,0 +1,320 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_ARM=y +# CONFIG_SBUS is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_UCLINUX=y +MAGIC_ROM_PTR=y + +# +# Code maturity level options +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# System Type +# +# CONFIG_ARCH_DSC21 is not set +# CONFIG_ARCH_C5471 is not set +# CONFIG_ARCH_CNXT is not set +# CONFIG_ARCH_NETARM is not set +# CONFIG_ARCH_TA7S is not set +# CONFIG_ARCH_TA7V is not set +# CONFIG_ARCH_SWARM is not set +# CONFIG_ARCH_SAMSUNG is not set +CONFIG_ARCH_LPC=y +# CONFIG_ARCH_ATMEL is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SET_MEM_PARAM=y +DRAM_BASE=81000000 +DRAM_SIZE=00800000 +FLASH_MEM_BASE=80000000 +FLASH_SIZE=00200000 +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_NO_PGT_CACHE=y +CONFIG_CPU_ARM710=y +CONFIG_CPU_32=y +CONFIG_CPU_32v4=y +# CONFIG_CPU_WITH_CACHE is not set +# CONFIG_CPU_WITH_MCR_INSTRUCTION is not set + +# +# General setup +# +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +# CONFIG_NET is not set +# CONFIG_SYSVIPC is not set +# CONFIG_REDUCED_MEMORY is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set +# CONFIG_NWFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_KERNEL_ELF=y +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="root=/dev/ram" +# CONFIG_ALIGNMENT_TRAP is not set +# CONFIG_RAM_ATTACHED_ROMFS is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_CISS_MONITOR_THREAD is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_RAMDISK_DATA is not set +# CONFIG_BLK_DEV_BLKMEM is not set +# CONFIG_BLK_STATS is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_QFMT_V2 is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +CONFIG_ROMFS_FS=y +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_SMB_FS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Character devices +# +# CONFIG_LEDMAN is not set +# CONFIG_DS1302 is not set +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_SERIAL_TA7=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set +# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set + +# +# Controller Area Network Cards/Chips +# +# CONFIG_CAN4LINUX is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set + +# +# Direct Rendering Manager (XFree86 DRI support) +# +# CONFIG_DRM is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Support for USB gadgets +# +# CONFIG_USB_GADGET is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +# CONFIG_REVISIT is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_INFO=y +# CONFIG_MAGIC_SYSRQ is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZLIB_DEFLATE is not set diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/debug-armv.S uClinux-dist/linux-2.4.x/arch/armnommu/kernel/debug-armv.S --- old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/debug-armv.S 2004-04-08 08:15:02.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/kernel/debug-armv.S 2005-01-06 09:12:11.000000000 +0800 @@ -44,6 +44,27 @@ beq 1001b .endm +#elif defined(CONFIG_ARCH_ARCH_LPC) + .macro addruart, rx + ldr \rx, =0xe000c000 + .endm + + .macro senduart,rd,rx + str \rd,[\rx] + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #0x18] + tst \rd, #0x00000001 + bne 1001b + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #0x14] + tst \rd, #0x00000020 + beq 1002b + .endm + #elif defined(CONFIG_ARCH_EBSA110) .macro addruart,rx mov \rx, #0xf0000000 diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.S uClinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.S --- old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.S 2004-04-08 08:15:02.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.S 2005-04-26 15:41:40.000000000 +0800 @@ -805,6 +805,152 @@ .macro irq_prio_table .endm +#elif defined(CONFIG_ARCH_LPC) + .macro disable_fiq + .endm + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +#if 0 + ldr r4, =VIC_AR + ldr \irqnr, [r4] + ldr r4, =VIC_ISR + ldr \irqstat, [r4] + teq \irqstat, #0 +#endif + ldr r4, =VIC_ISR + ldr r4, [r4] + mov \irqstat, r4 + + mov \irqnr, #0 + tst r4, #0x00000001 + BNE .+30*4*3+8 + + mov \irqnr, #1 + tst r4, #0x00000002 + BNE .+29*4*3+8 + + mov \irqnr, #2 + tst r4, #0x00000004 + BNE .+28*4*3+8 + + mov \irqnr, #3 + tst r4, #0x00000008 + BNE .+27*4*3+8 + + mov \irqnr, #4 + tst r4, #0x00000010 + BNE .+26*4*3+8 + + mov \irqnr, #5 + tst r4, #0x00000020 + BNE .+25*4*3+8 + + mov \irqnr, #6 + tst r4, #0x00000040 + BNE .+24*4*3+8 + + mov \irqnr, #7 + tst r4, #0x00000080 + BNE .+23*4*3+8 + + mov \irqnr, #8 + tst r4, #0x00000100 + BNE .+22*4*3+8 + + mov \irqnr, #9 + tst r4, #0x00000200 + BNE .+21*4*3+8 + + mov \irqnr, #10 + tst r4, #0x00000400 + BNE .+20*4*3+8 + + mov \irqnr, #11 + tst r4, #0x00000800 + BNE .+19*4*3+8 + + mov \irqnr, #12 + tst r4, #0x00001000 + BNE .+18*4*3+8 + + mov \irqnr, #13 + tst r4, #0x00002000 + BNE .+17*4*3+8 + + mov \irqnr, #14 + tst r4, #0x00004000 + BNE .+16*4*3+8 + + mov \irqnr, #15 + tst r4, #0x00008000 + BNE .+15*4*3+8 + + mov \irqnr, #16 + tst r4, #0x00010000 + BNE .+14*4*3+8 + + mov \irqnr, #17 + tst r4, #0x00020000 + BNE .+13*4*3+8 + + mov \irqnr, #18 + tst r4, #0x00040000 + BNE .+12*4*3+8 + + mov \irqnr, #19 + tst r4, #0x00080000 + BNE .+11*4*3+8 + + mov \irqnr, #20 + tst r4, #0x00100000 + BNE .+10*4*3+8 + + mov \irqnr, #21 + tst r4, #0x00200000 + BNE .+9*4*3+8 + + mov \irqnr, #22 + tst r4, #0x00400000 + BNE .+8*4*3+8 + + mov \irqnr, #23 + tst r4, #0x00800000 + BNE .+7*4*3+8 + + mov \irqnr, #24 + tst r4, #0x01000000 + BNE .+6*4*3+8 + + mov \irqnr, #25 + tst r4, #0x02000000 + BNE .+5*4*3+8 + + mov \irqnr, #26 + tst r4, #0x04000000 + BNE .+4*4*3+8 + + mov \irqnr, #27 + tst r4, #0x08000000 + BNE .+3*4*3+8 + + mov \irqnr, #28 + tst r4, #0x10000000 + BNE .+2*4*3+8 + + mov \irqnr, #29 + tst r4, #0x20000000 + BNE .+1*4*3+8 + + mov \irqnr, #30 + tst r4, #0x40000000 + BNE .+0*4*3+8 + + mov \irqnr, #31 + + + .endm + .macro irq_prio_table + .endm + #elif defined(CONFIG_ARCH_TA7S) || defined(CONFIG_ARCH_TA7V) #include @@ -1602,6 +1748,25 @@ ldmfd sp!, {r4 - r9, pc} #else /* Normal case: lower memory is writable. */ +#if defined(CONFIG_ARCH_LPC) + .equ __real_stubs_start, 0x200 + RAM_BASE +.LCvectors: + swi SYS_ERROR0 + ldr pc, .vector_undef + ldr pc, .vector_swi + ldr pc, .vector_prefetch + ldr pc, .vector_data + ldr pc, .vector_reserve + ldr pc, .vector_IRQ + ldr pc, .vector_FIQ +.vector_undef: .word (__real_stubs_start + (vector_undefinstr - __stubs_start)) +.vector_swi: .word vector_swi +.vector_prefetch: .word (__real_stubs_start + (vector_prefetch - __stubs_start)) +.vector_data: .word (__real_stubs_start + (vector_data - __stubs_start)) +.vector_reserve: .word (__real_stubs_start + (vector_addrexcptn - __stubs_start)) +.vector_IRQ: .word (__real_stubs_start + (vector_IRQ - __stubs_start)) +.vector_FIQ: .word (__real_stubs_start + (vector_FIQ - __stubs_start)) +#else .equ __real_stubs_start, .LCvectors + 0x200 .LCvectors: @@ -1654,6 +1819,7 @@ b __real_stubs_start + (vector_IRQ - __stubs_start) - 0x60 b __real_stubs_start + (vector_IRQ - __stubs_start) - 0x60 #endif +#endif /* CONFIG_ARCH_LPC */ ENTRY(__trap_init) stmfd sp!, {r4 - r9, lr} @@ -1687,10 +1853,21 @@ /* str r2, [r1] */ #endif /* CONFIG_CPU_S3C44B0X */ +#ifdef CONFIG_ARCH_LPC + mov r0, #RAM_BASE +#endif + adr r1, .LCvectors @ set up the vectors ldmia r1, {r2, r3, r4, r5, r6, r7, r8, r9} stmia r0, {r2, r3, r4, r5, r6, r7, r8, r9} +#ifdef CONFIG_ARCH_LPC + adr r1, .vector_undef + ldmia r1, {r2 - r9} + mov r0, #(RAM_BASE+32) + stmia r0, {r2 - r9} +#endif + #ifdef CONFIG_CPU_S3C3410 /* * Enable the vector table based interrupt mode @@ -1735,6 +1912,10 @@ mov r0, r4 #endif /* CONFIG_CPU_S3C44B0X */ +#ifdef CONFIG_ARCH_LPC + mov r0, #RAM_BASE +#endif + add r2, r0, #0x200 adr r0, __stubs_start @ copy stubs to 0x200 adr r1, __stubs_end diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/head-armv.S uClinux-dist/linux-2.4.x/arch/armnommu/kernel/head-armv.S --- old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/head-armv.S 2004-04-08 08:15:03.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/kernel/head-armv.S 2005-01-06 09:12:11.000000000 +0800 @@ -220,6 +220,33 @@ .long init_task_union+8192 #endif +#if defined(CONFIG_ARCH_LPC) + adr r5, LC0 + ldmia r5, {r5, r6, r8, r9, sp} @ Setup stack + + /* Clear BSS */ + mov r4, #0 +1: cmp r5, r8 + strcc r4, [r5], #4 + bcc 1b + + /* Pretend we know what our processor code is (for arm_id) */ + ldr r2, LPC_PROCESSOR_TYPE + str r2, [r6] + mov r2, #MACH_TYPE_LPC + str r2, [r9] + + mov fp, #0 + b start_kernel + +LC0: .long __bss_start + .long processor_id + .long _end + .long __machine_arch_type + .long init_task_union+8192 +LPC_PROCESSOR_TYPE: .long 0xfefefefe +#endif + #if defined(CONFIG_BOARD_SNDS100) adr r5, LC0 diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/ptrace.c uClinux-dist/linux-2.4.x/arch/armnommu/kernel/ptrace.c --- old/uClinux-dist/linux-2.4.x/arch/armnommu/kernel/ptrace.c 2004-04-08 08:15:03.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/kernel/ptrace.c 2005-06-06 09:51:12.000000000 +0800 @@ -23,6 +23,8 @@ #include "ptrace.h" + + #define REG_PC 15 #define REG_PSR 16 /* @@ -37,6 +39,44 @@ /* fill this in later */ #define BREAKINST_THUMB 0xdf00 +/*added by telpro*/ +static inline long get_stack_long(struct task_struct *task, int offset); +#define REG_SP 13 + +int in_arm26_mode(struct task_struct *child) +{ + long psr; + psr = get_stack_long(child, REG_PSR) ; + return ((psr & 0x1f) <= 3); +} + +#define FIXPC(child, x) \ + do { \ + if(in_arm26_mode(child)) x = x & 0x0ffffffc; \ + }while(0) + +//do as arch/armnommu/kernel/process.c +//a dirty version, FIXME...telpro +int is_addr_access( struct task_struct *child, + unsigned long addr ) +{ + unsigned long sp; + if ( addr >= child->mm->start_code && + addr < child->mm->end_code ) + return 1; + + if ( addr >= child->mm->start_data && + addr < child->mm->brk ) + return 1; + sp = get_stack_long(child, REG_SP) ; + //actually = sp && + addr < child->mm->start_stack ) + return 1; + return 0; +} + + /* * Get the address of the live pt_regs for the specified task. * These are saved onto the top kernel stack when the process @@ -57,6 +97,12 @@ */ static inline long get_stack_long(struct task_struct *task, int offset) { + unsigned long data; + data = get_user_regs(task)->uregs[offset]; + + if(offset == 14) { + data = data & 0x03fffffe; + } return get_user_regs(task)->uregs[offset]; } @@ -380,6 +426,8 @@ regs = get_user_regs(child); pc = instruction_pointer(regs); + //26bit , added by telpro + FIXPC(child, pc); res = read_tsk_long(child, pc, &insn); if (!res) { @@ -389,8 +437,10 @@ dbg->nsaved = 0; alt = get_branch_address(child, pc, insn); - if (alt) + if (alt) { + FIXPC(child, alt); res = add_breakpoint_arm(child, dbg, alt); + } /* * Note that we ignore the result of setting the above @@ -455,6 +505,11 @@ */ case PTRACE_PEEKTEXT: case PTRACE_PEEKDATA: + /*added by telpro*/ + if (!is_addr_access(child, addr) ) { + ret = -EIO; + break; + } ret = read_tsk_long(child, addr, &tmp); if (!ret) ret = put_user(tmp, (unsigned long *) data); @@ -471,15 +526,23 @@ tmp = 0; /* Default return condition */ if (addr < sizeof(struct pt_regs)) { tmp = get_stack_long(child, (int)addr >> 2); - } else if (addr == 4*49) { + //added by telpro, for at91 + if(addr == 14*4 || addr == 15*4 ) { + FIXPC(child, tmp); + } + } else if (addr == 49*4) { tmp = child->mm->start_code; - } else if (addr == 4*50) { + } else if (addr == 50*4) { tmp = child->mm->start_data; - } else if (addr == 4*51) { + } else if (addr == 51*4) { tmp = child->mm->end_code; - } else if (addr == 4*52) { + } else if (addr == 52*4) + { tmp = child->mm->end_data; - } + } else + break; + ret = put_user(tmp,(unsigned long *) data); + break; ret = put_user(tmp, (unsigned long *)data); break; @@ -488,6 +551,11 @@ */ case PTRACE_POKETEXT: case PTRACE_POKEDATA: + /*added by telpro*/ + if (!is_addr_access(child, addr) ) { + ret = -EIO; + break; + } ret = write_tsk_long(child, addr, data); break; diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/arch.c uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/arch.c --- old/uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/arch.c 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/arch.c 2005-03-30 13:53:38.000000000 +0800 @@ -0,0 +1,32 @@ +#include +#include +#include +#include + +#include +#include +#include +#include + +extern void genarch_init_irq(void); + +void fixup_lpc(struct machine_desc *desc, struct param_struct *params, char ** cmdline, struct meminfo * mi) +{ + mi->bank[0].start = 0x81000000; + mi->bank[0].size = 8 * 1024 * 1024; + mi->bank[0].node = 0; + mi->nr_banks = 1; + +#ifdef CONFIG_BLK_DEV_INITRD + setup_ramdisk(1, 0, 0, CONFIG_BLK_DEV_RAM_SIZE); + setup_initrd(__phys_to_virt(0x81700000), 1024 * 1024); + ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); +#endif +} + +MACHINE_START(LPC, "zlg-arm-linux") + MAINTAINER("Michael.Kang") + BOOT_MEM(0x81000000, 0xe0000000, 0xe0000000) + FIXUP(fixup_lpc) + INITIRQ(genarch_init_irq) +MACHINE_END diff -Naur old/uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/irq.c uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/irq.c --- old/uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/irq.c 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/arch/armnommu/mach-lpc/irq.c 2005-04-26 13:22:14.000000000 +0800 @@ -0,0 +1,56 @@ +#include + +#include +#include +#include +#include +#include + +extern struct irqdesc irq_desc[]; + +void lpc_mask_irq(unsigned int irq) +{ + __arch_putl(1< $@ qtronixmap.c: qtronixmap.map - set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@ + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@ \ No newline at end of file diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/dma.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/dma.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/dma.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/dma.h 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,8 @@ +#ifndef __ASM_ARCH_DAM_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 0 +#define arch_dma_init(dma_chan) + +#endif /* __ASM_ARCH_DMA_H */ diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/hardware.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/hardware.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/hardware.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/hardware.h 2005-05-19 15:57:52.000000000 +0800 @@ -0,0 +1,621 @@ +/* + * linux/include/asm-arm/arch-lpc/hardware.h + * for lpc + * 2004-06-19 added by Michael.Kang,tsinghua + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* 0=TC0, 1=TC1*/ +#define KERNEL_TIMER 0 + +#define LPC_TC_BASE 0xe0004000 +#define HARD_RESET_NOW() +/* +* add by lyh, use inner-ram for IRQ*/ +#define RAM_BASE 0x40000000 + +/*clocks*/ +#define Fosc 11059200 +#define Fcclk (Fosc * 4) +#define Fcco (Fcclk * 4) +#define Fpclk (Fcclk / 4) + +/* + * added by Michael.Kang,2004-06-18,defined interrupt register + */ +#define VIC_BASE 0xfffff000 +#define VIC_ISR (VIC_BASE+0x000) +#define VIC_FSR (VIC_BASE+0x004) +#define VIC_RISR (VIC_BASE+0x008) +#define VIC_ISLR (VIC_BASE+0x00c) //interrupt select register +#define VIC_IER (VIC_BASE+0x010) +#define VIC_IECR (VIC_BASE+0x014) +#define VIC_SIR (VIC_BASE+0x018) +#define VIC_SICR (VIC_BASE+0x01c) +#define VIC_PER (VIC_BASE+0x020) +#define VIC_AR (VIC_BASE+0x030) +#define VIC_DVAR (VIC_BASE+0x034) +#define VIC_VAR(i) (VIC_BASE+0x100+i*4) +#define VIC_VCR(i) (VIC_BASE+0x200+i*4) + +/* EXTERNAL MEMORY CONTROLLER (EMC) */ +#define BCFG0 0xFFE00000 /* lpc22xx only */ +#define BCFG1 0xFFE00004 /* lpc22xx only */ +#define BCFG2 0xFFE00008 /* lpc22xx only */ +#define BCFG3 0xFFE0000C /* lpc22xx only */ + +/* External Interrupts */ +#define EXTINT 0xE01FC140 +#define EXTWAKE 0xE01FC144 +#define EXTMODE 0xE01FC148 /* no in lpc210x*/ +#define EXTPOLAR 0xE01FC14C /* no in lpc210x*/ + +/* SMemory mapping control. */ +/* ÄÚ´æremap¿ØÖƼĴæÆ÷ */ +#define MEMMAP 0xE01FC040 + +/* Phase Locked Loop (PLL) */ +#define PLLCON 0xE01FC080 +#define PLLCFG 0xE01FC084 +#define PLLSTAT 0xE01FC088 +#define PLLFEED 0xE01FC08C + +/* Power Control */ +#define PCON 0xE01FC0C0 +#define PCONP 0xE01FC0C4 + +/* VPB Divider */ +#define VPBDIV 0xE01FC100 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR 0xE01FC000 +#define MAMTIM 0xE01FC004 + +/* Vectored Interrupt Controller (VIC) */ +#define VICIRQStatus 0xFFFFF000 +#define VICFIQStatus 0xFFFFF004 +#define VICRawIntr 0xFFFFF008 +#define VICIntSelect 0xFFFFF00C +#define VICIntEnable 0xFFFFF010 +#define VICIntEnClr 0xFFFFF014 +#define VICSoftInt 0xFFFFF018 +#define VICSoftIntClear 0xFFFFF01C +#define VICProtection 0xFFFFF020 +#define VICVectAddr 0xFFFFF030 +#define VICDefVectAddr 0xFFFFF034 +#define VICVectAddr0 0xFFFFF100 +#define VICVectAddr1 0xFFFFF104 +#define VICVectAddr2 0xFFFFF108 +#define VICVectAddr3 0xFFFFF10C +#define VICVectAddr4 0xFFFFF110 +#define VICVectAddr5 0xFFFFF114 +#define VICVectAddr6 0xFFFFF118 +#define VICVectAddr7 0xFFFFF11C +#define VICVectAddr8 0xFFFFF120 +#define VICVectAddr9 0xFFFFF124 +#define VICVectAddr10 0xFFFFF128 +#define VICVectAddr11 0xFFFFF12C +#define VICVectAddr12 0xFFFFF130 +#define VICVectAddr13 0xFFFFF134 +#define VICVectAddr14 0xFFFFF138 +#define VICVectAddr15 0xFFFFF13C +#define VICVectCntl0 0xFFFFF200 +#define VICVectCntl1 0xFFFFF204 +#define VICVectCntl2 0xFFFFF208 +#define VICVectCntl3 0xFFFFF20C +#define VICVectCntl4 0xFFFFF210 +#define VICVectCntl5 0xFFFFF214 +#define VICVectCntl6 0xFFFFF218 +#define VICVectCntl7 0xFFFFF21C +#define VICVectCntl8 0xFFFFF220 +#define VICVectCntl9 0xFFFFF224 +#define VICVectCntl10 0xFFFFF228 +#define VICVectCntl11 0xFFFFF22C +#define VICVectCntl12 0xFFFFF230 +#define VICVectCntl13 0xFFFFF234 +#define VICVectCntl14 0xFFFFF238 +#define VICVectCntl15 0xFFFFF23C + +/* Pin Connect Block */ +#define PINSEL0 0xE002C000 +#define PINSEL1 0xE002C004 +#define PINSEL2 0xE002C014 /* no in lpc210x*/ + +/* General Purpose Input/Output (GPIO) */ +#define IOPIN 0xE0028000 /* lpc210x only */ +#define IOSET 0xE0028004 /* lpc210x only */ +#define IODIR 0xE0028008 /* lpc210x only */ +#define IOCLR 0xE002800C /* lpc210x only */ + +#define IO0PIN 0xE0028000 /* no in lpc210x*/ +#define IO0SET 0xE0028004 /* no in lpc210x*/ +#define IO0DIR 0xE0028008 /* no in lpc210x*/ +#define IO0CLR 0xE002800C /* no in lpc210x*/ + +#define IO1PIN 0xE0028010 /* no in lpc210x*/ +#define IO1SET 0xE0028014 /* no in lpc210x*/ +#define IO1DIR 0xE0028018 /* no in lpc210x*/ +#define IO1CLR 0xE002801C /* no in lpc210x*/ + +#define IO2PIN 0xE0028020 /* lpc22xx only */ +#define IO2SET 0xE0028024 /* lpc22xx only */ +#define IO2DIR 0xE0028028 /* lpc22xx only */ +#define IO2CLR 0xE002802C /* lpc22xx only */ + +#define IO3PIN 0xE0028030 /* lpc22xx only */ +#define IO3SET 0xE0028034 /* lpc22xx only */ +#define IO3DIR 0xE0028038 /* lpc22xx only */ +#define IO3CLR 0xE002803C /* lpc22xx only */ + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define U0RBR 0xE000C000 +#define U0THR 0xE000C000 +#define U0IER 0xE000C004 +#define U0IIR 0xE000C008 +#define U0FCR 0xE000C008 +#define U0LCR 0xE000C00C +#define U0LSR 0xE000C014 +#define U0SCR 0xE000C01C +#define U0DLL 0xE000C000 +#define U0DLM 0xE000C004 + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define U1RBR 0xE0010000 +#define U1THR 0xE0010000 +#define U1IER 0xE0010004 +#define U1IIR 0xE0010008 +#define U1FCR 0xE0010008 +#define U1LCR 0xE001000C +#define U1MCR 0xE0010010 +#define U1LSR 0xE0010014 +#define U1MSR 0xE0010018 +#define U1SCR 0xE001001C +#define U1DLL 0xE0010000 +#define U1DLM 0xE0010004 + +/* I2C (8/16 bit data bus) */ +#define I2CONSET 0xE001C000 +#define I2STAT 0xE001C004 +#define I2DAT 0xE001C008 +#define I2ADR 0xE001C00C +#define I2SCLH 0xE001C010 +#define I2SCLL 0xE001C014 +#define I2CONCLR 0xE001C018 + +/* SPI (Serial Peripheral Interface) */ + /* only for lpc210x*/ +#define SPI_SPCR 0xE0020000 +#define SPI_SPSR 0xE0020004 +#define SPI_SPDR 0xE0020008 +#define SPI_SPCCR 0xE002000C +#define SPI_SPINT 0xE002001C + +#define S0PCR 0xE0020000 /* no in lpc210x*/ +#define S0PSR 0xE0020004 /* no in lpc210x*/ +#define S0PDR 0xE0020008 /* no in lpc210x*/ +#define S0PCCR 0xE002000C /* no in lpc210x*/ +#define S0PINT 0xE002001C /* no in lpc210x*/ + +#define S1PCR 0xE0030000 /* no in lpc210x*/ +#define S1PSR 0xE0030004 /* no in lpc210x*/ +#define S1PDR 0xE0030008 /* no in lpc210x*/ +#define S1PCCR 0xE003000C /* no in lpc210x*/ +#define S1PINT 0xE003001C /* no in lpc210x*/ + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN1MOD 0xE0044000 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1CMR 0xE0044004 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1GSR 0xE0044008 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1ICR 0xE004400C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1IER 0xE0044010 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1BTR 0xE0044014 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1EWL 0xE004401C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1SR 0xE0044020 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RFS 0xE0044024 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RDA 0xE0044028 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RDB 0xE004402C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI1 0xE0044030 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID1 0xE0044034 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA1 0xE0044038 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB1 0xE004403C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI2 0xE0044040 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID2 0xE0044044 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA2 0xE0044048 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB2 0xE004404C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI3 0xE0044050 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID3 0xE0044054 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA3 0xE0044058 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB3 0xE004405C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN2MOD 0xE0048000 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2CMR 0xE0048004 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2GSR 0xE0048008 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2ICR 0xE004800C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2IER 0xE0048010 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2BTR 0xE0048014 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2EWL 0xE004801C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2SR 0xE0048020 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RFS 0xE0048024 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RDA 0xE0048028 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RDB 0xE004802C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI1 0xE0048030 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID1 0xE0048034 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA1 0xE0048038 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB1 0xE004803C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI2 0xE0048040 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID2 0xE0048044 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA2 0xE0048048 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB2 0xE004804C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI3 0xE0048050 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID3 0xE0048054 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA3 0xE0048058 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB3 0xE004805C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN3MOD 0xE004C000 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3CMR 0xE004C004 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3GSR 0xE004C008 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3ICR 0xE004C00C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3IER 0xE004C010 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3BTR 0xE004C014 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3EWL 0xE004C01C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3SR 0xE004C020 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RFS 0xE004C024 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RDA 0xE004C028 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RDB 0xE004C02C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI1 0xE004C030 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID1 0xE004C034 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA1 0xE004C038 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB1 0xE004C03C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI2 0xE004C040 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID2 0xE004C044 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA2 0xE004C048 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB2 0xE004C04C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI3 0xE004C050 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID3 0xE004C054 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA3 0xE004C058 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB3 0xE004C05C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN4MOD 0xE0050000 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4CMR 0xE0050004 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4GSR 0xE0050008 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4ICR 0xE005000C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4IER 0xE0050010 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4BTR 0xE0050014 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4EWL 0xE005001C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4SR 0xE0050020 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RFS 0xE0050024 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RDA 0xE0050028 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RDB 0xE005002C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI1 0xE0050030 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID1 0xE0050034 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA1 0xE0050038 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB1 0xE005003C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI2 0xE0050040 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID2 0xE0050044 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA2 0xE0050048 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB2 0xE005004C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI3 0xE0050050 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID3 0xE0050054 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA3 0xE0050058 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB3 0xE005005C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN5MOD 0xE0054000 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5CMR 0xE0054004 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5GSR 0xE0054008 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5ICR 0xE005400C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5IER 0xE0054010 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5BTR 0xE0054014 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5EWL 0xE005401C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5SR 0xE0054020 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RFS 0xE0054024 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RDA 0xE0054028 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RDB 0xE005402C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI1 0xE0054030 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID1 0xE0054034 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA1 0xE0054038 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB1 0xE005403C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI2 0xE0054040 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID2 0xE0054044 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA2 0xE0054048 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB2 0xE005404C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI3 0xE0054050 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID3 0xE0054054 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA3 0xE0054058 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB3 0xE005405C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN6MOD 0xE0058000 /* lpc2292\lpc2294 only */ +#define CAN6CMR 0xE0058004 /* lpc2292\lpc2294 only */ +#define CAN6GSR 0xE0058008 /* lpc2292\lpc2294 only */ +#define CAN6ICR 0xE005800C /* lpc2292\lpc2294 only */ +#define CAN6IER 0xE0058010 /* lpc2292\lpc2294 only */ +#define CAN6BTR 0xE0058014 /* lpc2292\lpc2294 only */ +#define CAN6EWL 0xE005801C /* lpc2292\lpc2294 only */ +#define CAN6SR 0xE0058020 /* lpc2292\lpc2294 only */ +#define CAN6RFS 0xE0058024 /* lpc2292\lpc2294 only */ +#define CAN6RDA 0xE0058028 /* lpc2292\lpc2294 only */ +#define CAN6RDB 0xE005802C /* lpc2292\lpc2294 only */ +#define CAN6TFI1 0xE0058030 /* lpc2292\lpc2294 only */ +#define CAN6TID1 0xE0058034 /* lpc2292\lpc2294 only */ +#define CAN6TDA1 0xE0058038 /* lpc2292\lpc2294 only */ +#define CAN6TDB1 0xE005803C /* lpc2292\lpc2294 only */ +#define CAN6TFI2 0xE0058040 /* lpc2292\lpc2294 only */ +#define CAN6TID2 0xE0058044 /* lpc2292\lpc2294 only */ +#define CAN6TDA2 0xE0058048 /* lpc2292\lpc2294 only */ +#define CAN6TDB2 0xE005804C /* lpc2292\lpc2294 only */ +#define CAN6TFI3 0xE0058050 /* lpc2292\lpc2294 only */ +#define CAN6TID3 0xE0058054 /* lpc2292\lpc2294 only */ +#define CAN6TDA3 0xE0058058 /* lpc2292\lpc2294 only */ +#define CAN6TDB3 0xE005805C /* lpc2292\lpc2294 only */ + +#define CANTxSR 0xE0040000 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANRxSR 0xE0040004 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANMSR 0xE0040008 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CANAFMR 0xE003C000 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANSFF_sa 0xE003C004 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANSFF_GRP_sa 0xE003C008 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANEFF_sa 0xE003C00C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANEFF_GRP_sa 0xE003C010 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANENDofTable 0xE003C014 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANLUTerrAd 0xE003C018 /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANLUTerr 0xE003C01C /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + + +/* Timer 0 */ +#define T0IR 0xE0004000 +#define T0TCR 0xE0004004 +#define T0TC 0xE0004008 +#define T0PR 0xE000400C +#define T0PC 0xE0004010 +#define T0MCR 0xE0004014 +#define T0MR0 0xE0004018 +#define T0MR1 0xE000401C +#define T0MR2 0xE0004020 +#define T0MR3 0xE0004024 +#define T0CCR 0xE0004028 +#define T0CR0 0xE000402C +#define T0CR1 0xE0004030 +#define T0CR2 0xE0004034 +#define T0CR3 0xE0004038 +#define T0EMR 0xE000403C + +/* Timer 1 */ +#define T1IR 0xE0008000 +#define T1TCR 0xE0008004 +#define T1TC 0xE0008008 +#define T1PR 0xE000800C +#define T1PC 0xE0008010 +#define T1MCR 0xE0008014 +#define T1MR0 0xE0008018 +#define T1MR1 0xE000801C +#define T1MR2 0xE0008020 +#define T1MR3 0xE0008024 +#define T1CCR 0xE0008028 +#define T1CR0 0xE000802C +#define T1CR1 0xE0008030 +#define T1CR2 0xE0008034 +#define T1CR3 0xE0008038 +#define T1EMR 0xE000803C + +/* Pulse Width Modulator (PWM) */ +#define PWMIR 0xE0014000 +#define PWMTCR 0xE0014004 +#define PWMTC 0xE0014008 +#define PWMPR 0xE001400C +#define PWMPC 0xE0014010 +#define PWMMCR 0xE0014014 +#define PWMMR0 0xE0014018 +#define PWMMR1 0xE001401C +#define PWMMR2 0xE0014020 +#define PWMMR3 0xE0014024 +#define PWMMR4 0xE0014040 +#define PWMMR5 0xE0014044 +#define PWMMR6 0xE0014048 +#define PWMPCR 0xE001404C +#define PWMLER 0xE0014050 + +/* A/D CONVERTER */ +#define ADCR 0xE0034000 /* no in lpc210x*/ +#define ADDR 0xE0034004 /* no in lpc210x*/ + +/* Real Time Clock */ +#define ILR 0xE0024000 +#define CTC 0xE0024004 +#define CCR 0xE0024008 +#define CIIR 0xE002400C +#define AMR 0xE0024010 +#define CTIME0 0xE0024014 +#define CTIME1 0xE0024018 +#define CTIME2 0xE002401C +#define SEC 0xE0024020 +#define MIN 0xE0024024 +#define HOUR 0xE0024028 +#define DOM 0xE002402C +#define DOW 0xE0024030 +#define DOY 0xE0024034 +#define MONTH 0xE0024038 +#define YEAR 0xE002403C +#define ALSEC 0xE0024060 +#define ALMIN 0xE0024064 +#define ALHOUR 0xE0024068 +#define ALDOM 0xE002406C +#define ALDOW 0xE0024070 +#define ALDOY 0xE0024074 +#define ALMON 0xE0024078 +#define ALYEAR 0xE002407C +#define PREINT 0xE0024080 +#define PREFRAC 0xE0024084 + +/* Watchdog */ +#define WDMOD 0xE0000000 +#define WDTC 0xE0000004 +#define WDFEED 0xE0000008 +#define WDTV 0xE000000C + +/* Define firmware Functions */ +#define rm_init_entry() ((void (*)())(0x7fffff91))() +#define rm_undef_handler() ((void (*)())(0x7fffffa0))() +#define rm_prefetchabort_handler() ((void (*)())(0x7fffffb0))() +#define rm_dataabort_handler() ((void (*)())(0x7fffffc0))() +#define rm_irqhandler() ((void (*)())(0x7fffffd0))() +#define rm_irqhandler2() ((void (*)())(0x7fffffe0))() +#define iap_entry(a, b) ((void (*)())(0x7ffffff1))(a, b) + + +#ifndef __ASSEMBLER__ + + +struct lpc_timers +{ + + unsigned long ir; // + unsigned long tcr; // + unsigned long tc; // + unsigned long pr; // + unsigned long pc; // + unsigned long mcr; // + unsigned long mr0; // + unsigned long mr1; // + unsigned long mr2; // + unsigned long mr3; // + unsigned long ccr; // + unsigned long cr0; // + unsigned long cr1; // + unsigned long cr2; // + unsigned long cr3; // + unsigned long emr; // +}; +#endif + + +/* TC control register */ +#define TC_SYNC (1) + +/* TC mode register */ +#define TC2XC2S(x) (x & 0x3) +#define TC1XC1S(x) (x<<2 & 0xc) +#define TC0XC0S(x) (x<<4 & 0x30) +#define TCNXCNS(timer,v) ((v) << (timer<<1)) + +/* TC channel control */ +#define TC_CLKEN (1) +#define TC_CLKDIS (1<<1) +#define TC_SWTRG (1<<2) + +/* TC interrupts enable/disable/mask and status registers */ +#define TC_MTIOB (1<<18) +#define TC_MTIOA (1<<17) +#define TC_CLKSTA (1<<16) + +#define TC_ETRGS (1<<7) +#define TC_LDRBS (1<<6) +#define TC_LDRAS (1<<5) +#define TC_CPCS (1<<4) +#define TC_CPBS (1<<3) +#define TC_CPAS (1<<2) +#define TC_LOVRS (1<<1) +#define TC_COVFS (1) + +/* + * USART registers + */ + +#define LPC_UART_CNT 2 +#define LPC_UART0_BASE 0xe000c000 +#define LPC_UART1_BASE 0xe0010000 + +/* US control register */ +#define US_SENDA (1<<12) +#define US_STTO (1<<11) +#define US_STPBRK (1<<10) +#define US_STTBRK (1<<9) +#define US_RSTSTA (1<<8) +#define US_TXDIS (1<<7) +#define US_TXEN (1<<6) +#define US_RXDIS (1<<5) +#define US_RXEN (1<<4) +#define US_RSTTX (1<<3) +#define US_RSTRX (1<<2) + +/* US mode register */ +#define US_CLK0 (1<<18) +#define US_MODE9 (1<<17) +#define US_CHMODE(x)(x<<14 & 0xc000) +#define US_NBSTOP(x)(x<<12 & 0x3000) +#define US_PAR(x) (x<<9 & 0xe00) +#define US_SYNC (1<<8) +#define US_CHRL(x) (x<<6 & 0xc0) +#define US_USCLKS(x)(x<<4 & 0x30) + +/* US interrupts enable/disable/mask and status register */ +#define US_DMSI (1<<10) +#define US_TXEMPTY (1<<9) +#define US_TIMEOUT (1<<8) +#define US_PARE (1<<7) +#define US_FRAME (1<<6) +#define US_OVRE (1<<5) +#define US_ENDTX (1<<4) +#define US_ENDRX (1<<3) +#define US_RXBRK (1<<2) +#define US_TXRDY (1<<1) +#define US_RXRDY (1) + +#define US_ALL_INTS (US_DMSI|US_TXEMPTY|US_TIMEOUT|US_PARE|US_FRAME|US_OVRE|US_ENDTX|US_ENDRX|US_RXBRK|US_TXRDY|US_RXRDY) + +#ifndef __ASSEMBLER__ +#if 0 +static inline void lpc_uart_init(int baudrate) +{ + + //unsigned long reg = Fpclk / 16 /9600; /*9600*/ + unsigned int reg; + reg = 72; /*default 9600*/ + + + PINSEL0 |= 0x5; /*connect TXD0, RXD0*/ + U0LCR = 0x83; /*DLAB = 1, 8N1*/ + + U0DLL = reg; + U0DLM = 0; + + U0LCR = 0x3; /*DLAB = 0*/ +} + +static inline void lpc_uart_putc(unsigned char c) +{ + U0THR = c; + while((U0LSR & 0x40) == 0); + /* If \n, also do \r */ + if (c == '\n') + lpc_uart_putc ('\r'); +} +#endif +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ + + diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/ide.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/ide.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/ide.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/ide.h 2005-06-06 10:47:07.000000000 +0800 @@ -0,0 +1,45 @@ +/* + * linux/include/asm-arm/arch-sa1100/ide.h + * + * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre + * + * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * Get rid of the special ide_init_hwif_ports() functions + * and make a generalised function that can be used by all + * architectures. + */ + +#include +#include +#include +#include + + +/* + * Set up a hw structure for a specified data port, control port and IRQ. + * This should follow whatever the default interface uses. + */ +static __inline__ void +ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq) +{ +#ifdef CONFIG_REVISIT +#error Not sure what to do for ide_init_hwif_ports +#endif +} + + + + +/* + * This registers the standard ports for this architecture with the IDE + * driver. + */ +static __inline__ void +ide_init_default_hwifs(void) +{ +#ifdef CONFIG_REVISIT +#error Not sure what to do for ide_init_default_hwifs +#endif +} + + diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/io.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/io.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/io.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/io.h 2005-06-01 16:29:51.000000000 +0800 @@ -0,0 +1,48 @@ +/* + * linux/include/asm-armnommu/arch-atmel/io.h + * + * Copyright (C) 1997-1999 Russell King + * + * Modifications: + * 06-12-1997 RMK Created. + * 07-04-1999 RMK Major cleanup + * 02-19-2001 gjm Leveraged for armnommu/dsc21 + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H +#define CONFIG_IO16_BASE 0x00000000 + +/* + * kernel/resource.c uses this to initialize the global ioport_resource struct + * which is used in all calls to request_resource(), allocate_resource(), etc. + * --gmcnutt + */ +#define IO_SPACE_LIMIT 0xffffffff + +/* + * If we define __io then asm/io.h will take care of most of the inb & friends + * macros. It still leaves us some 16bit macros to deal with ourselves, though. + * We don't have PCI or ISA on the dsc21 so I dropped __mem_pci & __mem_isa. + * --gmcnutt + */ +#define __io(a) (CONFIG_IO16_BASE + (a)) +//#define __iob(a) (CONFIG_IO8_BASE + (a)) // byte io address +#define __iob(a) (a) +#define __mem_pci(a) ((unsigned long)(a)) + +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) + +/* + * Defining these two gives us ioremap for free. See asm/io.h. + * --gmcnutt + */ +#define iomem_valid_addr(iomem,sz) (1) +#define iomem_to_phys(iomem) (iomem) + +#ifdef CONFIG_CPU_BIG_ENDIAN +#define __io_noswap 1 +#endif + +#endif + diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irq.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irq.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irq.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irq.h 2005-06-01 16:35:16.000000000 +0800 @@ -0,0 +1,29 @@ +#ifndef __ASM_ARCH_IRQ_H +#define __ASM_ARCH_IRQ_H + +#include +#include +#include +#include + +#define fixup_irq(x) (x) + +extern void lpc_mask_irq(unsigned int irq); +extern void lpc_unmask_irq(unsigned int irq); +extern void lpc_mask_ack_irq(unsigned int irq); +extern void lpc_init_vic(void); + +static __inline__ void irq_init_irq(void) +{ + int irq; + lpc_init_vic(); + for(irq = 0; irq < NR_IRQS; irq++) { + if(!VALID_IRQ(irq)) continue; + irq_desc[irq].valid = 1; + irq_desc[irq].probe_ok = 1; + irq_desc[irq].mask_ack = lpc_mask_ack_irq; + irq_desc[irq].mask = lpc_mask_irq; + irq_desc[irq].unmask = lpc_unmask_irq; + } +} +#endif /* __ASM_ARCH_IRQ_H */ diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irqs.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irqs.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irqs.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/irqs.h 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,24 @@ +#ifndef __ASM_ARCH_IRQS_H__ +#define __ASM_ARCH_IRQS_H__ + +#define NR_IRQS 32 +#define VALID_IRQ(i) (i>=0 && i +#include + +#define RS_TABLE_SIZE 2 +#define BASE_BAUD 115200 +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +#define STD_SERIAL_PORT_DEFNS \ + { \ + type : PORT_16550A, \ + xmit_fifo_size : 16, \ + baud_base: BASE_BAUD, \ + irq: IRQ_UART0, \ + flags : STD_COM_FLAGS, \ + iomem_base : (u8*)LPC_UART0_BASE, \ + io_type : SERIAL_IO_MEM, \ + iomem_reg_shift: 2 \ + }, \ + { \ + type : PORT_16550A, \ + xmit_fifo_size : 16, \ + baud_base: BASE_BAUD, \ + irq: IRQ_UART1, \ + flags: STD_COM_FLAGS, \ + iomem_base : (u8*)LPC_UART1_BASE, \ + io_type : SERIAL_IO_MEM, \ + iomem_reg_shift: 2 \ + } + +unsigned int baudrate_div(unsigned int baudrate) +{ + return ((Fpclk / 16) / baudrate); +} + +#define EXTRA_SERIAL_PORT_DEFNS +#endif diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/shmparam.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/shmparam.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/shmparam.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/shmparam.h 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,5 @@ +/* + * linux/include/asm-arm/arch-a5k/shmparam.h + * + * Copyright (c) 1996 Russell King. + */ diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/system.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/system.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/system.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/system.h 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,17 @@ +/* + * linux/include/asm-armnommu/arch-p52/system.h + * 2001 Mindspeed + */ + +static inline void arch_idle(void) +{ + while (!current->need_resched && !hlt_counter) + cpu_do_idle(IDLE_WAIT_SLOW); +} + +extern inline void arch_reset(char mode) +{ + /* tbd */ +} + + diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/time.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/time.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/time.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/time.h 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,41 @@ +#if (KERNEL_TIMER == 0) +# define KERNEL_TIMER_IRQ_NUM IRQ_TC0 +#elif (KERNEL_TIMER == 1) +# define KERNEL_TIMER_IRQ_NUM IRQ_TC1 + +#else +#error Wierd -- KERNEL_TIMER is not defined or something... +#endif + +static unsigned long lpc_gettimeoffset(void) +{ + /* volatile struct lpc_timers * tt = (struct lpc_timers*)(LPC_TC_BASE); */ + return 0; +} + +static void lpc_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + /* printk("lpc_timer_interrupt\n"); */ + __arch_putl(0x1, T0IR); + do_timer(regs); + do_profile(regs); +} + +extern void lpc_unmask_irq(int); + +extern inline void setup_timer(void) +{ + // init timer + __arch_putl(0x2, T0TCR); + __arch_putl(0xffffffff, T0IR); + __arch_putl(0x0, T0PR); + __arch_putl(0x3, T0MCR); + __arch_putl(Fpclk/HZ, T0MR0); + __arch_putl(0x1, T0TCR); + + lpc_unmask_irq(KERNEL_TIMER_IRQ_NUM); + + gettimeoffset = lpc_gettimeoffset; + timer_irq.handler = lpc_timer_interrupt; + setup_arm_irq(KERNEL_TIMER_IRQ_NUM, &timer_irq); +} diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/timex.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/timex.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/timex.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/timex.h 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_TIMEX_H__ +#define __ASM_ARCH_TIMEX_H__ + +#define CLOCK_TICK_RATE 1000/8 + +#endif /* __ASM_ARCH_TIMEX_H__ */ diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/vmalloc.h uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/vmalloc.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/vmalloc.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/arch-lpc/vmalloc.h 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,33 @@ +/* + * linux/include/asm-arm/arch-dsc21/vmalloc.h + * + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) + diff -Naur old/uClinux-dist/linux-2.4.x/include/asm-armnommu/mach-types.h uClinux-dist/linux-2.4.x/include/asm-armnommu/mach-types.h --- old/uClinux-dist/linux-2.4.x/include/asm-armnommu/mach-types.h 2004-04-08 08:17:11.000000000 +0800 +++ uClinux-dist/linux-2.4.x/include/asm-armnommu/mach-types.h 1970-01-01 08:00:00.000000000 +0800 @@ -1,1287 +0,0 @@ -/* - * This was automagically generated from mach-types! - * Do NOT edit - */ - -#ifndef __ASM_ARM_MACH_TYPE_H -#define __ASM_ARM_MACH_TYPE_H - -#include - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -/* see arch/arm/kernel/arch.c for a description of these */ -#define MACH_TYPE_EBSA110 0 -#define MACH_TYPE_RISCPC 1 -#define MACH_TYPE_NEXUSPCI 3 -#define MACH_TYPE_EBSA285 4 -#define MACH_TYPE_NETWINDER 5 -#define MACH_TYPE_CATS 6 -#define MACH_TYPE_TBOX 7 -#define MACH_TYPE_CO285 8 -#define MACH_TYPE_CLPS7110 9 -#define MACH_TYPE_ARCHIMEDES 10 -#define MACH_TYPE_A5K 11 -#define MACH_TYPE_ETOILE 12 -#define MACH_TYPE_LACIE_NAS 13 -#define MACH_TYPE_CLPS7500 14 -#define MACH_TYPE_SHARK 15 -#define MACH_TYPE_BRUTUS 16 -#define MACH_TYPE_PERSONAL_SERVER 17 -#define MACH_TYPE_ITSY 18 -#define MACH_TYPE_L7200 19 -#define MACH_TYPE_PLEB 20 -#define MACH_TYPE_INTEGRATOR 21 -#define MACH_TYPE_BITSY 22 -#define MACH_TYPE_IXP1200 23 -#define MACH_TYPE_P720T 24 -#define MACH_TYPE_ASSABET 25 -#define MACH_TYPE_VICTOR 26 -#define MACH_TYPE_LART 27 -#define MACH_TYPE_RANGER 28 -#define MACH_TYPE_GRAPHICSCLIENT 29 -#define MACH_TYPE_XP860 30 -#define MACH_TYPE_CERF 31 -#define MACH_TYPE_NANOENGINE 32 -#define MACH_TYPE_FPIC 33 -#define MACH_TYPE_EXTENEX1 34 -#define MACH_TYPE_SHERMAN 35 -#define MACH_TYPE_ACCELENT_SA 36 -#define MACH_TYPE_ACCELENT_L7200 37 -#define MACH_TYPE_NETPORT 38 -#define MACH_TYPE_PANGOLIN 39 -#define MACH_TYPE_YOPY 40 -#define MACH_TYPE_COOLIDGE 41 -#define MACH_TYPE_HUW_WEBPANEL 42 -#define MACH_TYPE_SPOTME 43 -#define MACH_TYPE_FREEBIRD 44 -#define MACH_TYPE_TI925 45 -#define MACH_TYPE_RISCSTATION 46 -#define MACH_TYPE_CAVY 47 -#define MACH_TYPE_JORNADA720 48 -#define MACH_TYPE_OMNIMETER 49 -#define MACH_TYPE_EDB7211 50 -#define MACH_TYPE_CITYGO 51 -#define MACH_TYPE_PFS168 52 -#define MACH_TYPE_SPOT 53 -#define MACH_TYPE_FLEXANET 54 -#define MACH_TYPE_WEBPAL 55 -#define MACH_TYPE_LINPDA 56 -#define MACH_TYPE_ANAKIN 57 -#define MACH_TYPE_MVI 58 -#define MACH_TYPE_JUPITER 59 -#define MACH_TYPE_PSIONW 60 -#define MACH_TYPE_ALN 61 -#define MACH_TYPE_CAMELOT 62 -#define MACH_TYPE_GDS2200 63 -#define MACH_TYPE_PSION_SERIES7 64 -#define MACH_TYPE_XFILE 65 -#define MACH_TYPE_ACCELENT_EP9312 66 -#define MACH_TYPE_IC200 67 -#define MACH_TYPE_CREDITLART 68 -#define MACH_TYPE_HTM 69 -#define MACH_TYPE_IQ80310 70 -#define MACH_TYPE_FREEBOT 71 -#define MACH_TYPE_ENTEL 72 -#define MACH_TYPE_ENP3510 73 -#define MACH_TYPE_TRIZEPS 74 -#define MACH_TYPE_NESA 75 -#define MACH_TYPE_VENUS 76 -#define MACH_TYPE_TARDIS 77 -#define MACH_TYPE_MERCURY 78 -#define MACH_TYPE_EMPEG 79 -#define MACH_TYPE_I80200FCC 80 -#define MACH_TYPE_ITT_CPB 81 -#define MACH_TYPE_SA1110_SVC 82 -#define MACH_TYPE_SA1100 83 -#define MACH_TYPE_ALPHA2 84 -#define MACH_TYPE_ALPHA1 85 -#define MACH_TYPE_NETARM 86 -#define MACH_TYPE_DSC21 115 -#define MACH_TYPE_CX821XX 130 -#define MACH_TYPE_ATMEL 224 -#define MACH_TYPE_TA7S 334 -#define MACH_TYPE_P52 87 -#define MACH_TYPE_SPIPE 88 -#define MACH_TYPE_SNDS100 90 -#define MACH_TYPE_EVS3C4530HEI 164 -#define MACH_TYPE_S3C3410 165 -#define MACH_TYPE_SMDK2500 166 -#define MACH_TYPE_S3C2500REFRGP 167 - -#ifdef CONFIG_ARCH_EBSA110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA110 -# endif -# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110) -#else -# define machine_is_ebsa110() (0) -#endif - -#ifdef CONFIG_ARCH_RPC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCPC -# endif -# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC) -#else -# define machine_is_riscpc() (0) -#endif - -#ifdef CONFIG_ARCH_NEXUSPCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXUSPCI -# endif -# define machine_is_nexuspci() (machine_arch_type == MACH_TYPE_NEXUSPCI) -#else -# define machine_is_nexuspci() (0) -#endif - -#ifdef CONFIG_ARCH_EBSA285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA285 -# endif -# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285) -#else -# define machine_is_ebsa285() (0) -#endif - -#ifdef CONFIG_ARCH_NETWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETWINDER -# endif -# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER) -#else -# define machine_is_netwinder() (0) -#endif - -#ifdef CONFIG_ARCH_CATS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATS -# endif -# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS) -#else -# define machine_is_cats() (0) -#endif - -#ifdef CONFIG_ARCH_TBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBOX -# endif -# define machine_is_tbox() (machine_arch_type == MACH_TYPE_TBOX) -#else -# define machine_is_tbox() (0) -#endif - -#ifdef CONFIG_ARCH_CO285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CO285 -# endif -# define machine_is_co285() (machine_arch_type == MACH_TYPE_CO285) -#else -# define machine_is_co285() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7110 -# endif -# define machine_is_clps7110() (machine_arch_type == MACH_TYPE_CLPS7110) -#else -# define machine_is_clps7110() (0) -#endif - -#ifdef CONFIG_ARCH_ARC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCHIMEDES -# endif -# define machine_is_archimedes() (machine_arch_type == MACH_TYPE_ARCHIMEDES) -#else -# define machine_is_archimedes() (0) -#endif - -#ifdef CONFIG_ARCH_A5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A5K -# endif -# define machine_is_a5k() (machine_arch_type == MACH_TYPE_A5K) -#else -# define machine_is_a5k() (0) -#endif - -#ifdef CONFIG_ARCH_ETOILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETOILE -# endif -# define machine_is_etoile() (machine_arch_type == MACH_TYPE_ETOILE) -#else -# define machine_is_etoile() (0) -#endif - -#ifdef CONFIG_ARCH_LACIE_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LACIE_NAS -# endif -# define machine_is_lacie_nas() (machine_arch_type == MACH_TYPE_LACIE_NAS) -#else -# define machine_is_lacie_nas() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7500 -# endif -# define machine_is_clps7500() (machine_arch_type == MACH_TYPE_CLPS7500) -#else -# define machine_is_clps7500() (0) -#endif - -#ifdef CONFIG_ARCH_SHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHARK -# endif -# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK) -#else -# define machine_is_shark() (0) -#endif - -#ifdef CONFIG_SA1100_BRUTUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRUTUS -# endif -# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS) -#else -# define machine_is_brutus() (0) -#endif - -#ifdef CONFIG_ARCH_PERSONAL_SERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSONAL_SERVER -# endif -# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER) -#else -# define machine_is_personal_server() (0) -#endif - -#ifdef CONFIG_SA1100_ITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITSY -# endif -# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) -#else -# define machine_is_itsy() (0) -#endif - -#ifdef CONFIG_ARCH_L7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L7200 -# endif -# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200) -#else -# define machine_is_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_PLEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB -# endif -# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB) -#else -# define machine_is_pleb() (0) -#endif - -#ifdef CONFIG_ARCH_INTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTEGRATOR -# endif -# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR) -#else -# define machine_is_integrator() (0) -#endif - -#ifdef CONFIG_SA1100_BITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BITSY -# endif -# define machine_is_bitsy() (machine_arch_type == MACH_TYPE_BITSY) -#else -# define machine_is_bitsy() (0) -#endif - -#ifdef CONFIG_ARCH_IXP1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP1200 -# endif -# define machine_is_ixp1200() (machine_arch_type == MACH_TYPE_IXP1200) -#else -# define machine_is_ixp1200() (0) -#endif - -#ifdef CONFIG_ARCH_P720T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P720T -# endif -# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T) -#else -# define machine_is_p720t() (0) -#endif - -#ifdef CONFIG_SA1100_ASSABET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASSABET -# endif -# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET) -#else -# define machine_is_assabet() (0) -#endif - -#ifdef CONFIG_SA1100_VICTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VICTOR -# endif -# define machine_is_victor() (machine_arch_type == MACH_TYPE_VICTOR) -#else -# define machine_is_victor() (0) -#endif - -#ifdef CONFIG_SA1100_LART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LART -# endif -# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART) -#else -# define machine_is_lart() (0) -#endif - -#ifdef CONFIG_SA1100_RANGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RANGER -# endif -# define machine_is_ranger() (machine_arch_type == MACH_TYPE_RANGER) -#else -# define machine_is_ranger() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT -# endif -# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT) -#else -# define machine_is_graphicsclient() (0) -#endif - -#ifdef CONFIG_SA1100_XP860 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP860 -# endif -# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860) -#else -# define machine_is_xp860() (0) -#endif - -#ifdef CONFIG_SA1100_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CERF -# endif -# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF) -#else -# define machine_is_cerf() (0) -#endif - -#ifdef CONFIG_SA1100_NANOENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANOENGINE -# endif -# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE) -#else -# define machine_is_nanoengine() (0) -#endif - -#ifdef CONFIG_SA1100_FPIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FPIC -# endif -# define machine_is_fpic() (machine_arch_type == MACH_TYPE_FPIC) -#else -# define machine_is_fpic() (0) -#endif - -#ifdef CONFIG_SA1100_EXTENEX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXTENEX1 -# endif -# define machine_is_extenex1() (machine_arch_type == MACH_TYPE_EXTENEX1) -#else -# define machine_is_extenex1() (0) -#endif - -#ifdef CONFIG_SA1100_SHERMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHERMAN -# endif -# define machine_is_sherman() (machine_arch_type == MACH_TYPE_SHERMAN) -#else -# define machine_is_sherman() (0) -#endif - -#ifdef CONFIG_SA1100_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_SA -# endif -# define machine_is_accelent_sa() (machine_arch_type == MACH_TYPE_ACCELENT_SA) -#else -# define machine_is_accelent_sa() (0) -#endif - -#ifdef CONFIG_ARCH_L7200_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_L7200 -# endif -# define machine_is_accelent_l7200() (machine_arch_type == MACH_TYPE_ACCELENT_L7200) -#else -# define machine_is_accelent_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_NETPORT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETPORT -# endif -# define machine_is_netport() (machine_arch_type == MACH_TYPE_NETPORT) -#else -# define machine_is_netport() (0) -#endif - -#ifdef CONFIG_SA1100_PANGOLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PANGOLIN -# endif -# define machine_is_pangolin() (machine_arch_type == MACH_TYPE_PANGOLIN) -#else -# define machine_is_pangolin() (0) -#endif - -#ifdef CONFIG_SA1100_YOPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOPY -# endif -# define machine_is_yopy() (machine_arch_type == MACH_TYPE_YOPY) -#else -# define machine_is_yopy() (0) -#endif - -#ifdef CONFIG_SA1100_COOLIDGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COOLIDGE -# endif -# define machine_is_coolidge() (machine_arch_type == MACH_TYPE_COOLIDGE) -#else -# define machine_is_coolidge() (0) -#endif - -#ifdef CONFIG_SA1100_HUW_WEBPANEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUW_WEBPANEL -# endif -# define machine_is_huw_webpanel() (machine_arch_type == MACH_TYPE_HUW_WEBPANEL) -#else -# define machine_is_huw_webpanel() (0) -#endif - -#ifdef CONFIG_ARCH_SPOTME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOTME -# endif -# define machine_is_spotme() (machine_arch_type == MACH_TYPE_SPOTME) -#else -# define machine_is_spotme() (0) -#endif - -#ifdef CONFIG_ARCH_FREEBIRD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBIRD -# endif -# define machine_is_freebird() (machine_arch_type == MACH_TYPE_FREEBIRD) -#else -# define machine_is_freebird() (0) -#endif - -#ifdef CONFIG_ARCH_TI925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI925 -# endif -# define machine_is_ti925() (machine_arch_type == MACH_TYPE_TI925) -#else -# define machine_is_ti925() (0) -#endif - -#ifdef CONFIG_ARCH_RISCSTATION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCSTATION -# endif -# define machine_is_riscstation() (machine_arch_type == MACH_TYPE_RISCSTATION) -#else -# define machine_is_riscstation() (0) -#endif - -#ifdef CONFIG_SA1100_CAVY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAVY -# endif -# define machine_is_cavy() (machine_arch_type == MACH_TYPE_CAVY) -#else -# define machine_is_cavy() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA720 -# endif -# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720) -#else -# define machine_is_jornada720() (0) -#endif - -#ifdef CONFIG_SA1100_OMNIMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMNIMETER -# endif -# define machine_is_omnimeter() (machine_arch_type == MACH_TYPE_OMNIMETER) -#else -# define machine_is_omnimeter() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7211 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7211 -# endif -# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211) -#else -# define machine_is_edb7211() (0) -#endif - -#ifdef CONFIG_SA1100_CITYGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CITYGO -# endif -# define machine_is_citygo() (machine_arch_type == MACH_TYPE_CITYGO) -#else -# define machine_is_citygo() (0) -#endif - -#ifdef CONFIG_SA1100_PFS168 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFS168 -# endif -# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168) -#else -# define machine_is_pfs168() (0) -#endif - -#ifdef CONFIG_SA1100_SPOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOT -# endif -# define machine_is_spot() (machine_arch_type == MACH_TYPE_SPOT) -#else -# define machine_is_spot() (0) -#endif - -#ifdef CONFIG_SA1100_FLEXANET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXANET -# endif -# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET) -#else -# define machine_is_flexanet() (0) -#endif - -#ifdef CONFIG_ARCH_WEBPAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBPAL -# endif -# define machine_is_webpal() (machine_arch_type == MACH_TYPE_WEBPAL) -#else -# define machine_is_webpal() (0) -#endif - -#ifdef CONFIG_SA1100_LINPDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINPDA -# endif -# define machine_is_linpda() (machine_arch_type == MACH_TYPE_LINPDA) -#else -# define machine_is_linpda() (0) -#endif - -#ifdef CONFIG_ARCH_ANAKIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANAKIN -# endif -# define machine_is_anakin() (machine_arch_type == MACH_TYPE_ANAKIN) -#else -# define machine_is_anakin() (0) -#endif - -#ifdef CONFIG_SA1100_MVI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVI -# endif -# define machine_is_mvi() (machine_arch_type == MACH_TYPE_MVI) -#else -# define machine_is_mvi() (0) -#endif - -#ifdef CONFIG_SA1100_JUPITER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JUPITER -# endif -# define machine_is_jupiter() (machine_arch_type == MACH_TYPE_JUPITER) -#else -# define machine_is_jupiter() (0) -#endif - -#ifdef CONFIG_ARCH_PSIONW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSIONW -# endif -# define machine_is_psionw() (machine_arch_type == MACH_TYPE_PSIONW) -#else -# define machine_is_psionw() (0) -#endif - -#ifdef CONFIG_SA1100_ALN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALN -# endif -# define machine_is_aln() (machine_arch_type == MACH_TYPE_ALN) -#else -# define machine_is_aln() (0) -#endif - -#ifdef CONFIG_ARCH_CAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMELOT -# endif -# define machine_is_camelot() (machine_arch_type == MACH_TYPE_CAMELOT) -#else -# define machine_is_camelot() (0) -#endif - -#ifdef CONFIG_SA1100_GDS2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GDS2200 -# endif -# define machine_is_gds2200() (machine_arch_type == MACH_TYPE_GDS2200) -#else -# define machine_is_gds2200() (0) -#endif - -#ifdef CONFIG_SA1100_PSION_SERIES7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSION_SERIES7 -# endif -# define machine_is_psion_series7() (machine_arch_type == MACH_TYPE_PSION_SERIES7) -#else -# define machine_is_psion_series7() (0) -#endif - -#ifdef CONFIG_SA1100_XFILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XFILE -# endif -# define machine_is_xfile() (machine_arch_type == MACH_TYPE_XFILE) -#else -# define machine_is_xfile() (0) -#endif - -#ifdef CONFIG_ARCH_ACCELENT_EP9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_EP9312 -# endif -# define machine_is_accelent_ep9312() (machine_arch_type == MACH_TYPE_ACCELENT_EP9312) -#else -# define machine_is_accelent_ep9312() (0) -#endif - -#ifdef CONFIG_ARCH_IC200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IC200 -# endif -# define machine_is_ic200() (machine_arch_type == MACH_TYPE_IC200) -#else -# define machine_is_ic200() (0) -#endif - -#ifdef CONFIG_SA1100_CREDITLART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CREDITLART -# endif -# define machine_is_creditlart() (machine_arch_type == MACH_TYPE_CREDITLART) -#else -# define machine_is_creditlart() (0) -#endif - -#ifdef CONFIG_SA1100_HTM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTM -# endif -# define machine_is_htm() (machine_arch_type == MACH_TYPE_HTM) -#else -# define machine_is_htm() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80310 -# endif -# define machine_is_iq80310() (machine_arch_type == MACH_TYPE_IQ80310) -#else -# define machine_is_iq80310() (0) -#endif - -#ifdef CONFIG_SA1100_FREEBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBOT -# endif -# define machine_is_freebot() (machine_arch_type == MACH_TYPE_FREEBOT) -#else -# define machine_is_freebot() (0) -#endif - -#ifdef CONFIG_ARCH_ENTEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENTEL -# endif -# define machine_is_entel() (machine_arch_type == MACH_TYPE_ENTEL) -#else -# define machine_is_entel() (0) -#endif - -#ifdef CONFIG_ARCH_ENP3510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP3510 -# endif -# define machine_is_enp3510() (machine_arch_type == MACH_TYPE_ENP3510) -#else -# define machine_is_enp3510() (0) -#endif - -#ifdef CONFIG_SA1100_TRIZEPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS -# endif -# define machine_is_trizeps() (machine_arch_type == MACH_TYPE_TRIZEPS) -#else -# define machine_is_trizeps() (0) -#endif - -#ifdef CONFIG_SA1100_NESA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NESA -# endif -# define machine_is_nesa() (machine_arch_type == MACH_TYPE_NESA) -#else -# define machine_is_nesa() (0) -#endif - -#ifdef CONFIG_ARCH_VENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENUS -# endif -# define machine_is_venus() (machine_arch_type == MACH_TYPE_VENUS) -#else -# define machine_is_venus() (0) -#endif - -#ifdef CONFIG_ARCH_TARDIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TARDIS -# endif -# define machine_is_tardis() (machine_arch_type == MACH_TYPE_TARDIS) -#else -# define machine_is_tardis() (0) -#endif - -#ifdef CONFIG_ARCH_MERCURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MERCURY -# endif -# define machine_is_mercury() (machine_arch_type == MACH_TYPE_MERCURY) -#else -# define machine_is_mercury() (0) -#endif - -#ifdef CONFIG_SA1100_EMPEG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPEG -# endif -# define machine_is_empeg() (machine_arch_type == MACH_TYPE_EMPEG) -#else -# define machine_is_empeg() (0) -#endif - -#ifdef CONFIG_ARCH_I80200FCC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I80200FCC -# endif -# define machine_is_i80200fcc() (machine_arch_type == MACH_TYPE_I80200FCC) -#else -# define machine_is_i80200fcc() (0) -#endif - -#ifdef CONFIG_SA1100_ITT_CPB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITT_CPB -# endif -# define machine_is_itt_cpb() (machine_arch_type == MACH_TYPE_ITT_CPB) -#else -# define machine_is_itt_cpb() (0) -#endif - -#ifdef CONFIG_ARCH_SA1110_SVC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SA1110_SVC -# endif -# define machine_is_sa1110_svc() (machine_arch_type == MACH_TYPE_SA1110_SVC) -#else -# define machine_is_sa1110_svc() (0) -#endif - -#ifdef CONFIG_SA1100_SA1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SA1100 -# endif -# define machine_is_sa1100() (machine_arch_type == MACH_TYPE_SA1100) -#else -# define machine_is_sa1100() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA2 -# endif -# define machine_is_alpha2() (machine_arch_type == MACH_TYPE_ALPHA2) -#else -# define machine_is_alpha2() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA1 -# endif -# define machine_is_alpha1() (machine_arch_type == MACH_TYPE_ALPHA1) -#else -# define machine_is_alpha1() (0) -#endif - -#ifdef CONFIG_ARCH_NETARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETARM -# endif -# define machine_is_netarm() (machine_arch_type == MACH_TYPE_NETARM) -#else -# define machine_is_netarm() (0) -#endif - -#ifdef CONFIG_ARCH_DSC21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC21 -# endif -# define machine_is_dsc21() (machine_arch_type == MACH_TYPE_DSC21) -#else -# define machine_is_dsc21() (0) -#endif - -#ifdef CONFIG_ARCH_CX821XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX821XX -# endif -# define machine_is_cx821xx() (machine_arch_type == MACH_TYPE_CX821XX) -#else -# define machine_is_cx821xx() (0) -#endif - -#ifdef CONFIG_ARCH_ATMEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATMEL -# endif -# define machine_is_atmel() (machine_arch_type == MACH_TYPE_ATMEL) -#else -# define machine_is_atmel() (0) -#endif - -#ifdef CONFIG_ARCH_TA7S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7S -# endif -# define machine_is_ta7s() (machine_arch_type == MACH_TYPE_TA7S) -#else -# define machine_is_ta7s() (0) -#endif - -#ifdef CONFIG_ARCH_P52 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P52 -# endif -# define machine_is_p52() (machine_arch_type == MACH_TYPE_P52) -#else -# define machine_is_p52() (0) -#endif - -#ifdef CONFIG_ARCH_SPIPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPIPE -# endif -# define machine_is_spipe() (machine_arch_type == MACH_TYPE_SPIPE) -#else -# define machine_is_spipe() (0) -#endif - -#ifdef CONFIG_BOARD_SNDS100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNDS100 -# endif -# define machine_is_snds100() (machine_arch_type == MACH_TYPE_SNDS100) -#else -# define machine_is_snds100() (0) -#endif - -#ifdef CONFIG_BOARD_EVS3C4530HEI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVS3C4530HEI -# endif -# define machine_is_evS3C4530HEI() (machine_arch_type == MACH_TYPE_EVS3C4530HEI) -#else -# define machine_is_evS3C4530HEI() (0) -#endif - -#ifdef CONFIG_BOARD_SMDK40100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C3410 -# endif -# define machine_is_S3C3410X() (machine_arch_type == MACH_TYPE_S3C3410) -#else -# define machine_is_S3C3410X() (0) -#endif - -#ifdef CONFIG_BOARD_SMDK2500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2500 -# endif -# define machine_is_smdk2500() (machine_arch_type == MACH_TYPE_SMDK2500) -#else -# define machine_is_smdk2500() (0) -#endif - -#ifdef CONFIG_BOARD_S3C2500REFRGP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2500REFRGP -# endif -# define machine_is_S3C2500REFRGP() (machine_arch_type == MACH_TYPE_S3C2500REFRGP) -#else -# define machine_is_S3C2500REFRGP() (0) -#endif - -/* - * These have not yet been registered - */ - -#ifndef machine_arch_type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff -Naur old/uClinux-dist/linux-2.4.x/Makefile uClinux-dist/linux-2.4.x/Makefile --- old/uClinux-dist/linux-2.4.x/Makefile 2004-04-08 08:14:46.000000000 +0800 +++ uClinux-dist/linux-2.4.x/Makefile 2005-01-06 09:12:12.000000000 +0800 @@ -5,7 +5,7 @@ KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) -# ARCH := armnommu +ARCH := armnommu # ARCH := m68knommu # ARCH := h8300 # ARCH := niosnommu @@ -40,7 +40,7 @@ HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer # CROSS_COMPILE = m68k-elf- -# CROSS_COMPILE = arm-elf- +CROSS_COMPILE = arm-elf- # CROSS_COMPILE = h8300-elf- # CROSS_COMPILE = nios-elf- # CROSS_COMPILE = e1-coff- diff -Naur old/uClinux-dist/user/gdbserver/config/arm/tm-arm.h uClinux-dist/user/gdbserver/config/arm/tm-arm.h --- old/uClinux-dist/user/gdbserver/config/arm/tm-arm.h 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/user/gdbserver/config/arm/tm-arm.h 2005-06-03 20:01:15.000000000 +0800 @@ -0,0 +1,24 @@ +#ifndef _TM_ARM_ +#define _TM_ARM_ + +#define TARGET_ARM 1 + +#define REGISTER_RAW_SIZE(x) 4 + +#define REGISTER_BYTES (17*4) + +#define REGISTER_BYTE(x) (4*x) + +#define NUM_REGS 17 + +#define MAX_REGISTER_RAW_SIZE 4 + +#define NUM_FREGS 0 + +#define PC_REGNUM 15 + +#define SP_REGNUM 13 + +#define FP_REGNUM 14 + +#endif diff -Naur old/uClinux-dist/user/gdbserver/low-linux.c uClinux-dist/user/gdbserver/low-linux.c --- old/uClinux-dist/user/gdbserver/low-linux.c 2004-04-08 08:23:37.000000000 +0800 +++ uClinux-dist/user/gdbserver/low-linux.c 2005-06-03 20:19:39.000000000 +0800 @@ -35,6 +35,10 @@ /* kwonsk */ #define TARGET_M68K + +#undef TARGET_M68K +#define TARGET_ARM + #define U_REGS_OFFSET 0 #define REGISTER_U_ADDR (addr, blockend, regno) \ @@ -58,10 +62,10 @@ #endif #endif -static unsigned int code_end; -static unsigned int code_start; -static unsigned int data_start; -static unsigned int bss_start; + unsigned int code_end; + unsigned int code_start; + unsigned int data_start; + unsigned int bss_start; extern char **environ; extern int errno; extern int inferior_pid; @@ -186,6 +190,7 @@ #endif #ifndef TARGET_M68K +#if 0 /* this table must line up with REGISTER_NAMES in tm-i386v.h */ /* symbols like 'EAX' come from */ static int regmap[] = @@ -219,6 +224,28 @@ return (blockend + 4 * regmap[regnum]); } +#endif + +#ifdef TARGET_ARM +static int regmap[] = + +{ + + 0, 1, 2, 3, + 4, 5, 6, 7, + 8, 9, 10, 11, + 12, 13, 14, 15, + 16, 17 +}; //p.357 + +int arm_linux_register_u_addr (blockend, regnum) + int blockend; + int regnum; +{ + return (blockend + 4 * regmap[regnum]); +} +#endif + #else /* TARGET_M68K */ /* This table must line up with REGISTER_NAMES in tm-m68k.h */ static int regmap[] = @@ -262,7 +289,11 @@ error ("Invalid register number %d.", regno); // REGISTER_U_ADDR (addr, blockend, regno); +#ifdef TARGET_ARM + addr = arm_linux_register_u_addr(blockend, regno); +#else addr = m68k_linux_register_u_addr (blockend, regno); +#endif return addr; } diff -Naur old/uClinux-dist/user/gdbserver/server.c uClinux-dist/user/gdbserver/server.c --- old/uClinux-dist/user/gdbserver/server.c 2004-04-08 08:23:37.000000000 +0800 +++ uClinux-dist/user/gdbserver/server.c 2005-06-03 23:56:53.000000000 +0800 @@ -58,6 +58,20 @@ extern int remote_debug; + +extern unsigned int code_end; +extern unsigned int code_start; +#define ARM_BREAKPOINT 0xe7ffdefe +#define ARM_LINUX_BREAKPOINT 0xef9f0001 + +void bp_opcode_conv(unsigned long addr, unsigned long *p_op) + +{ + if( addr < code_start || addr > code_end ) return ; + if( *p_op != ARM_BREAKPOINT) return ; + *p_op = ARM_LINUX_BREAKPOINT; +} + int main (argc, argv) int argc; @@ -141,7 +155,10 @@ convert_int_to_ascii (mem_buf, own_buf, len); break; case 'M': - decode_M_packet (&own_buf[1], &mem_addr, &len, mem_buf); + decode_M_packet (&own_buf[1], &mem_addr, &len, mem_buf); + bp_opcode_conv( (unsigned long) mem_addr, + (unsigned long*)mem_buf ); + //decode_M_packet (&own_buf[1], &mem_addr, &len, mem_buf); if (write_inferior_memory (mem_addr, mem_buf, len) == 0) write_ok (own_buf); else diff -Naur old/uClinux-dist/user/gdbserver/tm.h uClinux-dist/user/gdbserver/tm.h --- old/uClinux-dist/user/gdbserver/tm.h 2004-04-08 08:23:37.000000000 +0800 +++ uClinux-dist/user/gdbserver/tm.h 2005-06-03 20:00:49.000000000 +0800 @@ -34,7 +34,8 @@ /*#define NUM_REGS 18*/ -#include "m68k/tm-m68k.h" +//#include "m68k/tm-m68k.h" +#include "arm/tm-arm.h" /* Need to do this for ELF targets, where we can't figure out the boundaries of the entry file. This method stops the backtrace when we reach main. */ diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.arch uClinux-dist/vendors/PHILIPS/lpc2200/config.arch --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.arch 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.arch 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,15 @@ +.EXPORT_ALL_VARIABLES: +############################################################################ + +CPUFLAGS := +# VENDOR_CFLAGS # not required here +# DISABLE_XIP := 1 # XIP works fine +DISABLE_MOVE_RODATA := 1 # until we get a toolchain release +LOPT := -O2 # library is alway 02 +UOPT := -Os # user apps are always Os + +############################################################################ + +include $(ROOTDIR)/vendors/config/armnommu/config.arch + +############################################################################ diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.0.x uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.0.x --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.0.x 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.0.x 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,154 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_UCLINUX=y +MAGIC_ROM_PTR=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# General setup +# +# CONFIG_ARCH_TRIO is not set +CONFIG_ARCH_AT91=y +# CONFIG_ARCH_NETARM is not set +# CONFIG_ARCH_ARC is not set +# CONFIG_ARCH_A5K is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_NEXUSPCI is not set +# CONFIG_ARCH_GBA is not set +# CONFIG_ARCH_ACORN is not set +# CONFIG_PCI is not set +CONFIG_ARCH_ATMEL=y +CONFIG_CPU_ARM7=y +CONFIG_ARM_CLK=32768000 +DRAM_BASE=02000000 +DRAM_SIZE=00200000 +FLASH_MEM_BASE=01400000 +FLASH_SIZE=00200000 +# CONFIG_EBI is not set +# CONFIG_ARCH_ATMEL_EB55 is not set +# CONFIG_WILL_BOOT_FROM_FLASH is not set +CONFIG_FRAME_POINTER=y +CONFIG_BINUTILS_NEW=y +CONFIG_DEBUG_ERRORS=y +CONFIG_NET=y +# CONFIG_SYSVIPC is not set +CONFIG_REDUCED_MEMORY=y +CONFIG_BINFMT_FLAT=y +CONFIG_KERNEL_ELF=y +# CONFIG_BINFMT_JAVA is not set + +# +# Floppy, IDE, and other block devices +# +CONFIG_BLK_DEV_BLKMEM=y +# CONFIG_BLK_DEV_IDE is not set + +# +# Additional Block/FLASH Devices +# +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_RAM=y +# CONFIG_RD_RELEASE_BLOCKS is not set +# CONFIG_DEV_FLASH is not set + +# +# Character devices +# +CONFIG_SERIAL_ATMEL=y +CONFIG_CONSOLE_ON_ATMEL=y +# CONFIG_SWAP_ATMEL_PORTS is not set +USART0_BASE=FFFD0000 +USART1_BASE=FFFCC000 +# CONFIG_SC28L91 is not set +# CONFIG_SERIAL_ATMEL_BT is not set +# CONFIG_LED_ATMEL is not set + +# +# Networking options +# +# CONFIG_FIREWALL is not set +# CONFIG_NET_ALIAS is not set +CONFIG_INET=y +CONFIG_IP_FORWARD=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IP_ACCT is not set +CONFIG_IP_ROUTER=y +# CONFIG_NET_IPIP is not set + +# +# (it is safe to leave these untouched) +# +# CONFIG_INET_PCTCP is not set +# CONFIG_INET_RARP is not set +# CONFIG_NO_PATH_MTU_DISCOVERY is not set +# CONFIG_IP_NOSR is not set +# CONFIG_SKB_LARGE is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_AX25 is not set +# CONFIG_BRIDGE is not set +# CONFIG_NETLINK is not set +# CONFIG_IPSEC is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +CONFIG_SLIP=y +CONFIG_SLIP_COMPRESSED=y +# CONFIG_SLIP_SMART is not set +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_PPP=y + +# +# CCP compressors for PPP are only built as modules. +# +# CONFIG_EQUALIZER is not set +# CONFIG_UCCS8900 is not set +# CONFIG_SMC9194 is not set +# CONFIG_NE2000 is not set + +# +# Filesystems +# +# CONFIG_QUOTA is not set +# CONFIG_MINIX_FS is not set +# CONFIG_EXT_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_XIA_FS is not set +# CONFIG_NLS is not set +CONFIG_PROC_FS=y +CONFIG_NFS_FS=y +# CONFIG_ROOT_NFS is not set +# CONFIG_SMB_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AFFS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_JFFS_FS is not set +# CONFIG_UFS_FS is not set + +# +# Kernel hacking +# +# CONFIG_PROFILE is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x 2005-06-08 10:27:01.000000000 +0800 @@ -0,0 +1,466 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +# CONFIG_SBUS is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_UCLINUX=y +MAGIC_ROM_PTR=y + +# +# Code maturity level options +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_DSC21 is not set +# CONFIG_ARCH_C5471 is not set +# CONFIG_ARCH_CNXT is not set +# CONFIG_ARCH_NETARM is not set +# CONFIG_ARCH_TA7S is not set +# CONFIG_ARCH_TA7V is not set +# CONFIG_ARCH_SWARM is not set +# CONFIG_ARCH_SAMSUNG is not set +CONFIG_ARCH_LPC=y +# CONFIG_ARCH_ATMEL is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SET_MEM_PARAM=y +DRAM_BASE=81000000 +DRAM_SIZE=00800000 +FLASH_MEM_BASE=80000000 +FLASH_SIZE=00200000 +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_NO_PGT_CACHE=y +CONFIG_CPU_ARM710=y +CONFIG_CPU_32=y +CONFIG_CPU_32v4=y +# CONFIG_CPU_WITH_CACHE is not set +# CONFIG_CPU_WITH_MCR_INSTRUCTION is not set + +# +# General setup +# +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +CONFIG_NET=y +# CONFIG_SYSVIPC is not set +# CONFIG_REDUCED_MEMORY is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set +# CONFIG_NWFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_KERNEL_ELF=y +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="root=/dev/ram" +# CONFIG_ALIGNMENT_TRAP is not set +# CONFIG_RAM_ATTACHED_ROMFS is not set + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +# CONFIG_UNIX is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_ARP_LIMIT is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_VLAN_8021Q is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set + +# +# Appletalk devices +# +# CONFIG_DEV_APPLETALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_IPSEC is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set + +# +# Network device support +# +# CONFIG_NETDEVICES is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_CISS_MONITOR_THREAD is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_RAMDISK_DATA is not set +# CONFIG_BLK_DEV_BLKMEM is not set +# CONFIG_BLK_STATS is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_QFMT_V2 is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +CONFIG_VFAT_FS=y +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SMB_NLS is not set +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Character devices +# +# CONFIG_LEDMAN is not set +# CONFIG_DS1302 is not set +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_SERIAL_TA7=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set + +# +# Joysticks +# +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set +# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set + +# +# Controller Area Network Cards/Chips +# +# CONFIG_CAN4LINUX is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set + +# +# Direct Rendering Manager (XFree86 DRI support) +# +# CONFIG_DRM is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Support for USB gadgets +# +# CONFIG_USB_GADGET is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +# CONFIG_REVISIT is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_INFO=y +# CONFIG_MAGIC_SYSRQ is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZLIB_DEFLATE is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x.gdbarmulator uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x.gdbarmulator --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x.gdbarmulator 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.4.x.gdbarmulator 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,507 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +# CONFIG_SBUS is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_UCLINUX=y +MAGIC_ROM_PTR=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# System Type +# +# CONFIG_ARCH_DSC21 is not set +# CONFIG_ARCH_C5471 is not set +# CONFIG_ARCH_CNXT is not set +# CONFIG_ARCH_NETARM is not set +# CONFIG_ARCH_TA7S is not set +# CONFIG_ARCH_TA7V is not set +# CONFIG_ARCH_SWARM is not set +# CONFIG_ARCH_SAMSUNG is not set +CONFIG_ARCH_ATMEL=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SET_MEM_PARAM=y +DRAM_BASE=01000000 +DRAM_SIZE=00400000 +FLASH_MEM_BASE=01400000 +FLASH_SIZE=00400000 +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_NO_PGT_CACHE=y +CONFIG_CPU_ARM710=y +CONFIG_CPU_32=y +CONFIG_CPU_32v4=y +# CONFIG_CPU_WITH_CACHE is not set +# CONFIG_CPU_WITH_MCR_INSTRUCTION is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_ARM_CLK=40000000 +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_MEM16_BASE=03000000 +CONFIG_MEM8_BASE=03000000 +CONFIG_IO16_BASE=02000000 +CONFIG_IO8_BASE=02000000 +CONFIG_CPU_AT91X40=y +# CONFIG_CPU_AT91X63 is not set +# CONFIG_ATMEL_DEBUG is not set + +# +# General setup +# +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +CONFIG_NET=y +# CONFIG_SYSVIPC is not set +CONFIG_REDUCED_MEMORY=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set +# CONFIG_NWFPE is not set +# CONFIG_KCORE_ELF is not set +CONFIG_KCORE_AOUT=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_KERNEL_ELF=y +# CONFIG_PM is not set +# CONFIG_ARTHUR is not set +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_ALIGNMENT_TRAP is not set +# CONFIG_RAM_ATTACHED_ROMFS is not set + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_ARP_LIMIT is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set + +# +# Appletalk devices +# +# CONFIG_DEV_APPLETALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_IPSEC is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_ARM_AM79C961A is not set +# CONFIG_ARM_CIRRUS is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set +# CONFIG_FEC is not set +# CONFIG_CS89x0 is not set +# CONFIG_UCCS8900 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_CISS_MONITOR_THREAD is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_BLK_DEV_RAMDISK_DATA is not set +CONFIG_BLK_DEV_BLKMEM=y +CONFIG_NOFLASH=y +# CONFIG_AMDFLASH is not set +# CONFIG_INTELFLASH is not set +# CONFIG_BLK_STATS is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_QFMT_V2 is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +CONFIG_ROMFS_FS=y +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Character devices +# +# CONFIG_LEDMAN is not set +# CONFIG_DS1302 is not set +# CONFIG_VT is not set +# CONFIG_SERIAL is not set +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set + +# +# Joysticks +# +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set +# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set + +# +# Controller Area Network Cards/Chips +# +# CONFIG_CAN4LINUX is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set + +# +# Direct Rendering Manager (XFree86 DRI support) +# +# CONFIG_DRM is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Support for USB gadgets +# +# CONFIG_USB_GADGET is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +# CONFIG_REVISIT is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_INFO=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_CONTIGUOUS_PAGE_ALLOC is not set +# CONFIG_MEM_MAP is not set +# CONFIG_NO_MMU_LARGE_ALLOCS is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZLIB_DEFLATE is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.6.x uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.6.x --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.6.x 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.linux-2.6.x 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,525 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +# CONFIG_SBUS is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_UCLINUX=y +MAGIC_ROM_PTR=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# System Type +# +# CONFIG_ARCH_DSC21 is not set +# CONFIG_ARCH_CNXT is not set +# CONFIG_ARCH_NETARM is not set +# CONFIG_ARCH_SWARM is not set +# CONFIG_ARCH_SAMSUNG is not set +CONFIG_ARCH_ATMEL=y +CONFIG_SET_MEM_PARAM=y +DRAM_BASE=01000000 +DRAM_SIZE=00400000 +FLASH_MEM_BASE=04000000 +FLASH_SIZE=00400000 +CONFIG_NO_PGT_CACHE=y +CONFIG_CPU_ARM710=y +CONFIG_CPU_32=y +CONFIG_CPU_32v4=y +# CONFIG_CPU_WITH_CACHE is not set +# CONFIG_CPU_WITH_MCR_INSTRUCTION is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_MEM16_BASE=03000000 +CONFIG_MEM8_BASE=03000000 +CONFIG_IO16_BASE=02000000 +CONFIG_IO8_BASE=02000000 +CONFIG_CPU_AT91X40=y +# CONFIG_CPU_AT91X63 is not set +# CONFIG_ATMEL_DEBUG is not set + +# +# General setup +# +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +CONFIG_NET=y +# CONFIG_SYSVIPC is not set +CONFIG_REDUCED_MEMORY=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set +# CONFIG_NWFPE is not set +# CONFIG_KCORE_ELF is not set +CONFIG_KCORE_AOUT=y +CONFIG_BINFMT_FLAT=y +CONFIG_KERNEL_ELF=y +# CONFIG_PM is not set +# CONFIG_ARTHUR is not set +# CONFIG_ALIGNMENT_TRAP is not set + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_IPSEC is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_ARM_AM79C961A is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set +# CONFIG_FEC is not set +# CONFIG_CS89x0 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_BLK_DEV_RAMDISK_DATA is not set +CONFIG_BLK_DEV_BLKMEM=y +CONFIG_NOFLASH=y +# CONFIG_AMDFLASH is not set +# CONFIG_INTELFLASH is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +# CONFIG_RAMFS is not set +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +CONFIG_ROMFS_FS=y +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set +# CONFIG_ZLIB_FS_INFLATE is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Character devices +# +# CONFIG_LEDMAN is not set +# CONFIG_VT is not set +# CONFIG_SERIAL is not set +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set + +# +# Joysticks +# +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# USB Controllers +# +# CONFIG_USB_UHCI is not set +# CONFIG_USB_UHCI_ALT is not set +# CONFIG_USB_OHCI is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_BLUETOOTH is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_HP8200e is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# USB Human Interface Devices (HID) +# +# CONFIG_USB_HID is not set +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_WACOM is not set + +# +# USB Imaging devices +# +# CONFIG_USB_DC2XX is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_SCANNER is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_HPUSBSCSI is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DABUSB is not set + +# +# USB Network adaptors +# +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDCETHER is not set +# CONFIG_USB_USBNET is not set + +# +# USB port drivers +# +# CONFIG_USB_USS720 is not set + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OMNINET is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_RIO500 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +# CONFIG_REVISIT is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_INFO=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_CONTIGUOUS_PAGE_ALLOC is not set +# CONFIG_MEM_MAP is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.lpc2200 uClinux-dist/vendors/PHILIPS/lpc2200/config.lpc2200 --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.lpc2200 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.lpc2200 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,320 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_ARM=y +# CONFIG_SBUS is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_UCLINUX=y +MAGIC_ROM_PTR=y + +# +# Code maturity level options +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# System Type +# +# CONFIG_ARCH_DSC21 is not set +# CONFIG_ARCH_C5471 is not set +# CONFIG_ARCH_CNXT is not set +# CONFIG_ARCH_NETARM is not set +# CONFIG_ARCH_TA7S is not set +# CONFIG_ARCH_TA7V is not set +# CONFIG_ARCH_SWARM is not set +# CONFIG_ARCH_SAMSUNG is not set +CONFIG_ARCH_LPC=y +# CONFIG_ARCH_ATMEL is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SET_MEM_PARAM=y +DRAM_BASE=81000000 +DRAM_SIZE=00800000 +FLASH_MEM_BASE=80000000 +FLASH_SIZE=00200000 +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_NO_PGT_CACHE=y +CONFIG_CPU_ARM710=y +CONFIG_CPU_32=y +CONFIG_CPU_32v4=y +# CONFIG_CPU_WITH_CACHE is not set +# CONFIG_CPU_WITH_MCR_INSTRUCTION is not set + +# +# General setup +# +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +# CONFIG_NET is not set +# CONFIG_SYSVIPC is not set +# CONFIG_REDUCED_MEMORY is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set +# CONFIG_NWFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_KERNEL_ELF=y +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="root=/dev/ram" +# CONFIG_ALIGNMENT_TRAP is not set +# CONFIG_RAM_ATTACHED_ROMFS is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_CISS_MONITOR_THREAD is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_RAMDISK_DATA is not set +# CONFIG_BLK_DEV_BLKMEM is not set +# CONFIG_BLK_STATS is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_QFMT_V2 is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +CONFIG_ROMFS_FS=y +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_SMB_FS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Character devices +# +# CONFIG_LEDMAN is not set +# CONFIG_DS1302 is not set +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_SERIAL_TA7=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set +# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set + +# +# Controller Area Network Cards/Chips +# +# CONFIG_CAN4LINUX is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set + +# +# Direct Rendering Manager (XFree86 DRI support) +# +# CONFIG_DRM is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Support for USB gadgets +# +# CONFIG_USB_GADGET is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +# CONFIG_REVISIT is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_INFO=y +# CONFIG_MAGIC_SYSRQ is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZLIB_DEFLATE is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.uClibc uClinux-dist/vendors/PHILIPS/lpc2200/config.uClibc --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.uClibc 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.uClibc 2005-06-08 10:27:01.000000000 +0800 @@ -0,0 +1,142 @@ +# +# Automatically generated make config: don't edit +# +# TARGET_alpha is not set +TARGET_arm=y +# TARGET_cris is not set +# TARGET_e1 is not set +# TARGET_h8300 is not set +# TARGET_i386 is not set +# TARGET_i960 is not set +# TARGET_m68k is not set +# TARGET_microblaze is not set +# TARGET_mips is not set +# TARGET_powerpc is not set +# TARGET_sh is not set +# TARGET_sparc is not set +# TARGET_v850 is not set + +# +# Target Architecture Features and Options +# +HAVE_ELF=y +TARGET_ARCH="arm" +CONFIG_GENERIC_ARM=y +# CONFIG_ARM610 is not set +# CONFIG_ARM710 is not set +# CONFIG_ARM720T is not set +# CONFIG_ARM920T is not set +# CONFIG_ARM922T is not set +# CONFIG_ARM926T is not set +# CONFIG_ARM_SA110 is not set +# CONFIG_ARM_SA1100 is not set +# CONFIG_ARM_XSCALE is not set +UCLIBC_HAS_SOFT_FLOAT=y +ARCH_LITTLE_ENDIAN=y +# ARCH_BIG_ENDIAN is not set +# ARCH_HAS_NO_MMU is not set +# UCLIBC_HAS_MMU is not set +UCLIBC_HAS_FLOATS=y +# HAS_FPU is not set +DO_C99_MATH=y +WARNINGS="-Wall" +KERNEL_SOURCE="$(ROOTDIR)/$(LINUXDIR)/." +UCLIBC_UCLINUX_BROKEN_MUNMAP=y +EXCLUDE_BRK=y +C_SYMBOL_PREFIX="" +HAVE_DOT_CONFIG=y + +# +# General Library Settings +# +# HAVE_NO_PIC is not set +# DOPIC is not set +# HAVE_NO_SHARED is not set +# ARCH_HAS_NO_LDSO is not set +# UCLIBC_PIE_SUPPORT is not set +UCLIBC_CTOR_DTOR=y +# UCLIBC_PROPOLICE is not set +# UCLIBC_PROFILING is not set +# HAS_NO_THREADS is not set +UCLIBC_HAS_THREADS=y +# PTHREADS_DEBUG_SUPPORT is not set +UCLIBC_HAS_LFS=y +# MALLOC is not set +MALLOC_SIMPLE=y +# MALLOC_STANDARD is not set +# MALLOC_GLIBC_COMPAT is not set +UCLIBC_DYNAMIC_ATEXIT=y +# HAS_SHADOW is not set +# UNIX98PTY_ONLY is not set +ASSUME_DEVPTS=y +UCLIBC_HAS_TM_EXTENSIONS=y +# UCLIBC_HAS_TZ_CACHING is not set +UCLIBC_HAS_TZ_FILE=y +UCLIBC_HAS_TZ_FILE_READ_MANY=y +UCLIBC_TZ_FILE_PATH="/etc/TZ" + +# +# Networking Support +# +# UCLIBC_HAS_IPV6 is not set +UCLIBC_HAS_RPC=y +UCLIBC_HAS_FULL_RPC=y + +# +# String and Stdio Support +# +UCLIBC_HAS_CTYPE_TABLES=y +UCLIBC_HAS_CTYPE_SIGNED=y +UCLIBC_HAS_CTYPE_UNSAFE=y +# UCLIBC_HAS_CTYPE_CHECKED is not set +# UCLIBC_HAS_CTYPE_ENFORCED is not set +# UCLIBC_HAS_WCHAR is not set +# UCLIBC_HAS_LOCALE is not set +# UCLIBC_HAS_HEXADECIMAL_FLOATS is not set +# UCLIBC_HAS_GLIBC_CUSTOM_PRINTF is not set +# USE_OLD_VFPRINTF is not set +UCLIBC_PRINTF_SCANF_POSITIONAL_ARGS=9 +# UCLIBC_HAS_SCANF_GLIBC_A_FLAG is not set +# UCLIBC_HAS_STDIO_BUFSIZ_NONE is not set +UCLIBC_HAS_STDIO_BUFSIZ_256=y +# UCLIBC_HAS_STDIO_BUFSIZ_512 is not set +# UCLIBC_HAS_STDIO_BUFSIZ_1024 is not set +# UCLIBC_HAS_STDIO_BUFSIZ_2048 is not set +# UCLIBC_HAS_STDIO_BUFSIZ_4096 is not set +# UCLIBC_HAS_STDIO_BUFSIZ_8192 is not set +UCLIBC_HAS_STDIO_BUILTIN_BUFFER_NONE=y +# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_4 is not set +# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_8 is not set +UCLIBC_HAS_STDIO_GETC_MACRO=y +UCLIBC_HAS_STDIO_PUTC_MACRO=y +UCLIBC_HAS_STDIO_AUTO_RW_TRANSITION=y +# UCLIBC_HAS_FOPEN_LARGEFILE_MODE is not set +# UCLIBC_HAS_FOPEN_EXCLUSIVE_MODE is not set +# UCLIBC_HAS_GLIBC_CUSTOM_STREAMS is not set +UCLIBC_HAS_PRINTF_M_SPEC=y +UCLIBC_HAS_ERRNO_MESSAGES=y +UCLIBC_HAS_SYS_ERRLIST=y +UCLIBC_HAS_SIGNUM_MESSAGES=y +# UCLIBC_HAS_SYS_SIGLIST is not set +UCLIBC_HAS_GNU_GETOPT=y + +# +# Big and Tall +# +UCLIBC_HAS_REGEX=y +# UCLIBC_HAS_WORDEXP is not set +# UCLIBC_HAS_FTW is not set +UCLIBC_HAS_GLOB=y + +# +# Library Installation Options +# +RUNTIME_PREFIX="/usr/$(TARGET_ARCH)-linux-uclibc/" +DEVEL_PREFIX="/usr/$(TARGET_ARCH)-linux-uclibc" + +# +# uClibc development/debugging options +# +# DODEBUG is not set +# DOASSERTS is not set +# UCLIBC_MJN3_ONLY is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,514 @@ +# +# Automatically generated make config: don't edit +# + +# +# SnapGear Apps/Libs +# +# CONFIG_USER_CGI is not set +# CONFIG_USER_FIREWALL_TOOLS is not set +# CONFIG_USER_AES_PERF is not set +# CONFIG_USER_BR_BR is not set +# CONFIG_USER_CERBERIAN_CERBERIAN is not set +# CONFIG_USER_CERBERIAN_PROXYAUTH is not set +# CONFIG_USER_CERBERIAN_CERBTEST is not set +# CONFIG_USER_DESTEST_DESTEST is not set +# CONFIG_USER_DESTEST_DESPERF is not set +# CONFIG_USER_EMCTEST_EMCTEST is not set +# CONFIG_USER_FACTORY_FACTTEST is not set +# CONFIG_USER_GDSD_GDSD is not set +# CONFIG_USER_GDSD_GDSD_INET is not set +# CONFIG_USER_GRE_GRE is not set +# CONFIG_USER_IDB_IDB is not set +# CONFIG_USER_IPSEC_CONFIGURATOR is not set +# CONFIG_USER_REDIALER_REDIALER is not set +# CONFIG_USER_PKTDELAY_PKTDELAY is not set +# CONFIG_USER_PROTECT is not set +# CONFIG_USER_SETKEY_SETKEY is not set +# CONFIG_USER_IOD is not set +# CONFIG_USER_SWTEST_SWTEST is not set +# CONFIG_USER_MGMT_MGMT is not set +# CONFIG_USER_SGSNMPD_AGENT is not set +# CONFIG_USER_TQRECV_TQRECV is not set +# CONFIG_USER_UPNPD is not set +# CONFIG_USER_WINSD_WS is not set + +# +# Core Applications +# +CONFIG_USER_INIT_INIT=y +CONFIG_USER_INIT_CONSOLE_SH=y +# CONFIG_USER_INIT_RUN_FIREWALL is not set +CONFIG_USER_SASH_SH=y +# CONFIG_USER_SH_SH is not set +# CONFIG_USER_NWSH_SH is not set +# CONFIG_USER_BASH_BASH is not set +# CONFIG_USER_OTHER_SH is not set +# CONFIG_USER_SASH_HISTORY is not set +CONFIG_USER_SASH_REBOOT=y +# CONFIG_USER_SASH_SHUTDOWN is not set +CONFIG_USER_INIT_EXPAND=y +# CONFIG_USER_INIT_EXPAND_NOZEROES is not set +# CONFIG_USER_VERSION_VERSION is not set +CONFIG_USER_LOGIN_LOGIN=y +# CONFIG_USER_OLD_PASSWORDS is not set +# CONFIG_USER_ONLY_ROOT is not set +# CONFIG_USER_AGETTY_AGETTY is not set +# CONFIG_USER_GETTYD_GETTYD is not set +# CONFIG_USER_LOGIN_PASSWD is not set +# CONFIG_USER_CRON_CRON is not set + +# +# Real Time Clock +# +# CONFIG_USER_HWCLOCK_HWCLOCK is not set +# CONFIG_USER_RTC_M41T11 is not set +# CONFIG_USER_RTC_DS1302 is not set + +# +# Vixie-cron +# +# CONFIG_USER_VIXIECRON_CRON is not set +# CONFIG_USER_VIXIECRON_CRONTAB is not set + +# +# at +# +# CONFIG_USER_AT_AT is not set +# CONFIG_USER_AT_ATD is not set +# CONFIG_USER_AT_ATRUN is not set + +# +# Library Configuration +# + +# +# Force build (Normally built when required) +# +# CONFIG_LIB_LIBAES_FORCE is not set +# CONFIG_LIB_LIBDES_FORCE is not set +# CONFIG_LIB_LIBSSL_FORCE is not set +# CONFIG_LIB_LIBGMP_FORCE is not set +# CONFIG_LIB_LIBG_FORCE is not set +# CONFIG_LIB_LIBLDAP_FORCE is not set +# CONFIG_LIB_LIBPAM_FORCE is not set +# CONFIG_LIB_LIBPCAP_FORCE is not set +# CONFIG_LIB_ZLIB_FORCE is not set +# CONFIG_LIB_LIBATM_FORCE is not set +# CONFIG_LIB_LIBPNG_FORCE is not set +# CONFIG_LIB_LIBJPEG_FORCE is not set +# CONFIG_LIB_NCURSES_FORCE is not set + +# +# Library Configuration +# +# CONFIG_LIB_UC_LIBC_TIMEZONE is not set + +# +# Flash Tools +# +# CONFIG_USER_FLASHW_FLASHW is not set +# CONFIG_USER_NETFLASH_NETFLASH is not set +# CONFIG_USER_RECOVER_STATIC_TFTP is not set +# CONFIG_USER_RECOVER_RECOVER is not set +# CONFIG_USER_BOOTTOOLS_FLASHLOADER is not set +# CONFIG_USER_BOOTTOOLS_HIMEMLOADER is not set + +# +# MTD utils +# +# CONFIG_USER_MTDUTILS is not set +# CONFIG_USER_MTDUTILS_ERASE is not set +# CONFIG_USER_MTDUTILS_ERASEALL is not set +# CONFIG_USER_MTDUTILS_FTL_CHECK is not set +# CONFIG_USER_MTDUTILS_FTL_FORMAT is not set +# CONFIG_USER_MTDUTILS_MKFSJFFS is not set +# CONFIG_USER_MTDUTILS_MKFSJFFS2 is not set +# CONFIG_USER_MTDUTILS_NFTLDUMP is not set +# CONFIG_USER_MTDUTILS_NFTL_FORMAT is not set +# CONFIG_USER_MTDUTILS_NANDDUMP is not set +# CONFIG_USER_MTDUTILS_NANDTEST is not set +# CONFIG_USER_MTDUTILS_NANDWRITE is not set +# CONFIG_USER_MTDUTILS_DOC_LOADBIOS is not set +# CONFIG_USER_MTDUTILS_DOC_LOADIPL is not set + +# +# Filesystem Applications +# +# CONFIG_USER_FLATFSD_FLATFSD is not set +# CONFIG_USER_MOUNT_MOUNT is not set +# CONFIG_USER_MOUNT_UMOUNT is not set +# CONFIG_USER_FDISK_FDISK is not set +# CONFIG_USER_FDISK_SFDISK is not set + +# +# EXT2 +# +# CONFIG_USER_E2FSPROGS_E2FSCK_E2FSCK is not set +# CONFIG_USER_E2FSPROGS_MISC_MKE2FS is not set +# CONFIG_USER_E2FSPROGS_MISC_BADBLOCKS is not set +# CONFIG_USER_E2FSPROGS_MISC_CHATTR is not set +# CONFIG_USER_E2FSPROGS_MISC_DUMPE2FS is not set +# CONFIG_USER_E2FSPROGS_MISC_E2LABEL is not set +# CONFIG_USER_E2FSPROGS_MISC_FSCK is not set +# CONFIG_USER_E2FSPROGS_MISC_LSATTR is not set +# CONFIG_USER_E2FSPROGS_MISC_MKLOST_FOUND is not set +# CONFIG_USER_E2FSPROGS_MISC_TUNE2FS is not set +# CONFIG_USER_E2FSPROGS_MISC_UUIDGEN is not set + +# +# RESIERFS +# +# CONFIG_USER_REISERFSPROGS is not set +# CONFIG_USER_REISERFSPROGS_DEBUGRESIERFS is not set +# CONFIG_USER_REISERFSPROGS_MKREISERFS is not set +# CONFIG_USER_REISERFSPROGS_REISERFSCK is not set +# CONFIG_USER_REISERFSPROGS_RESIZE_REISERFS is not set +# CONFIG_USER_REISERFSPROGS_UNPACK is not set + +# +# SAMBA +# +# CONFIG_USER_SAMBA is not set +# CONFIG_USER_SAMBA_SMBD is not set +# CONFIG_USER_SAMBA_NMBD is not set +# CONFIG_USER_SAMBA_SMBMOUNT is not set +# CONFIG_USER_SAMBA_SMBUMOUNT is not set + +# +# SMBFS +# +# CONFIG_USER_SMBMOUNT_SMBMOUNT is not set +# CONFIG_USER_SMBMOUNT_SMBUMOUNT is not set + +# +# CRAMFS +# +# CONFIG_USER_CRAMFS_CRAMFSCK is not set +# CONFIG_USER_CRAMFS_MKCRAMFS is not set + +# +# Network Applications +# +# CONFIG_USER_ROUTE_ARP is not set +# CONFIG_USER_FNORD_HTTPD is not set +CONFIG_USER_BOA_SRC_BOA=y +# CONFIG_USER_BOA_WITH_SSL is not set +# CONFIG_USER_BPALOGIN_BPALOGIN is not set +# CONFIG_USER_BR2684CTL_BR2684CTL is not set +# CONFIG_USER_BRCFG_BRCFG is not set +# CONFIG_USER_BRCTL_BRCTL is not set +# CONFIG_USER_DHCPCD_DHCPCD is not set +CONFIG_USER_DHCPCD_NEW_DHCPCD=y +# CONFIG_USER_DHCPD_DHCPD is not set +# CONFIG_USER_DHCP_ISC_SERVER_DHCPD is not set +# CONFIG_USER_DHCP_ISC_CLIENT_DHCLIENT is not set +# CONFIG_USER_DHCP_ISC_RELAY_DHCRELAY is not set +# CONFIG_USER_DIALD_DIALD is not set +# CONFIG_USER_DISCARD_DISCARD is not set +# CONFIG_USER_DNSMASQ_DNSMASQ is not set +# CONFIG_USER_ETHATTACH_ETHATTACH is not set +# CONFIG_USER_EZIPUPDATE_EZIPUPDATE is not set +# CONFIG_USER_FTP_FTP_FTP is not set +# CONFIG_USER_FTPD_FTPD is not set +# CONFIG_USER_FREESWAN is not set +# CONFIG_USER_HTTPD_HTTPD is not set +# CONFIG_USER_IFATTACH_IFATTACH is not set +CONFIG_USER_ROUTE_IFCONFIG=y +CONFIG_USER_INETD_INETD=y +# CONFIG_USER_IPCHAINS_IPCHAINS is not set +# CONFIG_USER_IPFWADM_IPFWADM is not set +# CONFIG_USER_IPMASQADM_IPMASQADM is not set +# CONFIG_USER_IPPORTFW_IPPORTFW is not set +# CONFIG_USER_IPREDIR_IPREDIR is not set +# CONFIG_USER_IPROUTE2 is not set +# CONFIG_USER_IPTABLES_IPTABLES is not set +# CONFIG_USER_KENDIN_CONFIG is not set +# CONFIG_USER_KLAXON_KLAXON is not set +# CONFIG_USER_L2TPD_L2TPD is not set +# CONFIG_USER_LOATTACH_LOATTACH is not set +# CONFIG_USER_SMTP_SMTPCLIENT is not set +# CONFIG_USER_MAIL_MAIL_IP is not set +# CONFIG_USER_MARADNS_MARADNS is not set +# CONFIG_USER_MINI_HTTPD_MINI_HTTPD is not set +# CONFIG_USER_MSNTP_MSNTP is not set +# CONFIG_USER_NESSUS_NASL is not set +# CONFIG_USER_ROUTE_NETSTAT is not set +# CONFIG_USER_NETSTAT_NAT_NETSTAT_NAT is not set +# CONFIG_USER_MARADNS_ZONESERVER is not set +# CONFIG_USER_ROUTE_MIITOOL is not set +# CONFIG_USER_NTPD_NTPD is not set +# CONFIG_USER_NTPD_NTPDATE is not set +# CONFIG_USER_NTPD_NTPQ is not set +# CONFIG_USER_OPENSSL_APPS is not set +CONFIG_USER_PING_PING=y +CONFIG_USER_HELLO_HELLO=y +# CONFIG_USER_PLUG_PLUG is not set +# CONFIG_USER_PORTMAP_PORTMAP is not set +# CONFIG_USER_PPPD_PPPD_PPPD is not set +# CONFIG_USER_PPTPD_PPTPCTRL is not set +# CONFIG_USER_PPTPD_PPTPD is not set +# CONFIG_USER_PPTP_CLIENT_PPTP is not set +# CONFIG_USER_PPTP_CLIENT_PPTP_CALLMGR is not set +# CONFIG_USER_RDATE_RDATE is not set +CONFIG_USER_ROUTE_ROUTE=y +# CONFIG_USER_ROUTED_ROUTED is not set +# CONFIG_USER_RP_PPPOE_PPPOE is not set +# CONFIG_USER_RP_PPPOE_PPPOE_SERVER is not set +# CONFIG_USER_SETHDLC_SETHDLC is not set +# CONFIG_USER_SLATTACH_SLATTACH is not set +# CONFIG_USER_SNMPD_SNMPD is not set +# CONFIG_USER_SNORT_SNORT is not set +# CONFIG_USER_STUNNEL_STUNNEL is not set +# CONFIG_USER_SSLWRAP_SSLWRAP is not set +# CONFIG_USER_SQUID_SQUID is not set +# CONFIG_USER_SSH_SSH is not set +# CONFIG_USER_SSH_SSHD is not set +# CONFIG_USER_SSH_SSHKEYGEN is not set +# CONFIG_USER_STP_STP is not set +# CONFIG_USER_TCPWRAP_TCPD is not set +# CONFIG_USER_TCPBLAST_TCPBLAST is not set +# CONFIG_USER_TCPDUMP_TCPDUMP is not set +CONFIG_USER_TELNETD_TELNETD=y +# CONFIG_USER_TELNET_TELNET is not set +# CONFIG_USER_TFTP_TFTP is not set +# CONFIG_USER_TFTPD_TFTPD is not set +# CONFIG_USER_THTTPD_THTTPD is not set +# CONFIG_USER_TRACEROUTE_TRACEROUTE is not set +# CONFIG_USER_UCDSNMP_SNMPD is not set +# CONFIG_USER_VCONFIG_VCONFIG is not set +# CONFIG_USER_VPNLED_VPNLED is not set +# CONFIG_USER_WGET is not set +# CONFIG_USER_ZEBRA_ZEBRA_ZEBRA is not set + +# +# Net-tools +# +# CONFIG_USER_NET_TOOLS_ARP is not set +# CONFIG_USER_NET_TOOLS_HOSTNAME is not set +# CONFIG_USER_NET_TOOLS_IFCONFIG is not set +# CONFIG_USER_NET_TOOLS_NAMEIF is not set +# CONFIG_USER_NET_TOOLS_NETSTAT is not set +# CONFIG_USER_NET_TOOLS_PLIPCONFIG is not set +# CONFIG_USER_NET_TOOLS_RARP is not set +# CONFIG_USER_NET_TOOLS_ROUTE is not set +# CONFIG_USER_NET_TOOLS_SLATTACH is not set +# CONFIG_USER_NET_TOOLS_MII_TOOL is not set + +# +# Wireless-tools +# +# CONFIG_USER_WIRELESS_TOOLS is not set +# CONFIG_USER_HOSTAP_HOSTAP is not set +# CONFIG_USER_WLAN_NG is not set + +# +# Miscellaneous Applications +# +# CONFIG_USER_LANG_A60 is not set +# CONFIG_USER_CAL_CAL is not set +# CONFIG_USER_CHAT_CHAT is not set +# CONFIG_USER_CKSUM_CKSUM is not set +# CONFIG_USER_CLOCK_CLOCK is not set +# CONFIG_USER_CPU_CPU is not set +# CONFIG_USER_CAL_DATE is not set +# CONFIG_USER_DHRYSTONE_DHRYSTONE is not set +# CONFIG_USER_DE2TSCAL_DE2TSCAL is not set +# CONFIG_USER_FROB_LED_FROB_LED is not set +# CONFIG_USER_GDBSERVER_GDBREPLAY is not set +CONFIG_USER_GDBSERVER_GDBSERVER=y +# CONFIG_USER_HD_HD is not set +# CONFIG_USER_LCD_LCD is not set +# CONFIG_USER_LEDCON_LEDCON is not set +# CONFIG_USER_LILO_LILO is not set +# CONFIG_USER_LISSA_LISSA is not set +# CONFIG_USER_USBCBI_USBCBI is not set +# CONFIG_USER_USBISO_USBISO is not set +# CONFIG_USER_MATH_TEST is not set +# CONFIG_USER_MAWK_AWK is not set +# CONFIG_USER_MYSQL is not set +# CONFIG_USER_NULL_NULL is not set +# CONFIG_USER_PALMBOT_PALMBOT is not set +# CONFIG_USER_PCMCIA_CS is not set +# CONFIG_USER_PERL_PERL is not set +# CONFIG_USER_PYTHON_PYTHON is not set +# CONFIG_USER_READPROFILE_READPROFILE is not set +# CONFIG_USER_ROOTLOADER_ROOTLOADER is not set +# CONFIG_USER_SETSERIAL_SETSERIAL is not set +# CONFIG_USER_TRIPWIRE_SIGGEN is not set +# CONFIG_USER_STRACE_STRACE is not set +# CONFIG_USER_STTY_STTY is not set +# CONFIG_USER_TCSH_TCSH is not set +# CONFIG_USER_TINYTCL_TCLSH is not set +# CONFIG_USER_THREADDEMOS_THREADDEMOS is not set +# CONFIG_USER_TIP_TIP is not set +# CONFIG_USER_TRIPWIRE_TRIPWIRE is not set +# CONFIG_USER_LRZSZ_LRZSZ is not set + +# +# LIRC +# +# CONFIG_USER_LIRC is not set +# CONFIG_USER_LIRC_LIRCD is not set +# CONFIG_USER_LIRC_IRRECORD is not set +# CONFIG_USER_LIRC_LIRCMD is not set +# CONFIG_USER_LIRC_IREXEC is not set +# CONFIG_USER_LIRC_IRW is not set +# CONFIG_USER_LIRC_MODE2 is not set + +# +# Editors +# +# CONFIG_USER_LEVEE_VI is not set +# CONFIG_USER_ELVISTINY_VI is not set + +# +# Audio tools +# +# CONFIG_USER_MP3PLAY_MP3PLAY is not set +# CONFIG_USER_OGGPLAY_OGG123 is not set +# CONFIG_USER_OGGPLAY_EXAMPLE is not set +# CONFIG_USER_MUSICBOX_MUSICBOX is not set +# CONFIG_USER_PLAY_PLAY is not set +# CONFIG_USER_PLAY_TONE is not set +# CONFIG_USER_VPLAY_VPLAY is not set +# CONFIG_USER_VPLAY_VREC is not set +# CONFIG_USER_VPLAY_MIXER is not set +# CONFIG_USER_PLAYRT_PLAYRT is not set + +# +# Video tools +# +# CONFIG_USER_W3CAM_VIDCAT is not set +# CONFIG_USER_W3CAM_W3CAMD is not set + +# +# Fileutils tools +# +# CONFIG_USER_FILEUTILS_CAT is not set +# CONFIG_USER_FILEUTILS_CHGRP is not set +# CONFIG_USER_FILEUTILS_CHMOD is not set +# CONFIG_USER_FILEUTILS_CHOWN is not set +# CONFIG_USER_FILEUTILS_CMP is not set +# CONFIG_USER_FILEUTILS_CP is not set +# CONFIG_USER_FILEUTILS_DD is not set +# CONFIG_USER_FILEUTILS_GREP is not set +# CONFIG_USER_FILEUTILS_L is not set +# CONFIG_USER_FILEUTILS_LN is not set +# CONFIG_USER_FILEUTILS_LS is not set +# CONFIG_USER_FILEUTILS_MKDIR is not set +# CONFIG_USER_FILEUTILS_MKFIFO is not set +# CONFIG_USER_FILEUTILS_MKNOD is not set +# CONFIG_USER_FILEUTILS_MORE is not set +# CONFIG_USER_FILEUTILS_MV is not set +# CONFIG_USER_FILEUTILS_RM is not set +# CONFIG_USER_FILEUTILS_RMDIR is not set +# CONFIG_USER_FILEUTILS_SYNC is not set +# CONFIG_USER_FILEUTILS_TOUCH is not set + +# +# Shutils tools +# +# CONFIG_USER_SHUTILS_BASENAME is not set +# CONFIG_USER_SHUTILS_DATE is not set +# CONFIG_USER_SHUTILS_DIRNAME is not set +# CONFIG_USER_SHUTILS_ECHO is not set +# CONFIG_USER_SHUTILS_FALSE is not set +# CONFIG_USER_SHUTILS_LOGNAME is not set +# CONFIG_USER_SHUTILS_PRINTENV is not set +# CONFIG_USER_SHUTILS_PWD is not set +# CONFIG_USER_SHUTILS_TRUE is not set +# CONFIG_USER_SHUTILS_UNAME is not set +# CONFIG_USER_SHUTILS_WHICH is not set +# CONFIG_USER_SHUTILS_WHOAMI is not set +# CONFIG_USER_SHUTILS_YES is not set + +# +# Sysutils tools +# +# CONFIG_USER_SYSUTILS_REBOOT is not set +# CONFIG_USER_SYSUTILS_SHUTDOWN is not set +# CONFIG_USER_SYSUTILS_DF is not set +# CONFIG_USER_SYSUTILS_FREE is not set +# CONFIG_USER_SYSUTILS_HOSTNAME is not set +# CONFIG_USER_SYSUTILS_KILL is not set +# CONFIG_USER_SYSUTILS_PS is not set + +# +# Procps tools +# +# CONFIG_USER_PROCPS_FREE is not set +# CONFIG_USER_PROCPS_KILL is not set +# CONFIG_USER_PROCPS_PGREP is not set +# CONFIG_USER_PROCPS_PKILL is not set +# CONFIG_USER_PROCPS_PS is not set +# CONFIG_USER_PROCPS_SNICE is not set +# CONFIG_USER_PROCPS_SYSCTL is not set +# CONFIG_USER_PROCPS_TLOAD is not set +# CONFIG_USER_PROCPS_TOP is not set +# CONFIG_USER_PROCPS_UPTIME is not set +# CONFIG_USER_PROCPS_VMSTAT is not set +# CONFIG_USER_PROCPS_W is not set +# CONFIG_USER_PROCPS_WATCH is not set + +# +# PCI utilities +# +# CONFIG_USER_PCIUTILS_LSPCI is not set +# CONFIG_USER_PCIUTILS_SETPCI is not set + +# +# BusyBox +# +# CONFIG_USER_BUSYBOX_BUSYBOX is not set + +# +# Tinylogin +# +# CONFIG_USER_TINYLOGIN_TINYLOGIN is not set + +# +# MicroWindows +# +# CONFIG_USER_MICROWIN is not set + +# +# Games +# +# CONFIG_USER_GAMES_ADVENT4 is not set +# CONFIG_USER_GAMES_DUNGEON is not set +# CONFIG_USER_GAMES_RUBIK is not set + +# +# Miscellaneous Configuration +# +# CONFIG_USER_RAMIMAGE_NONE is not set +# CONFIG_USER_RAMIMAGE_RAMFS64 is not set +CONFIG_USER_RAMIMAGE_RAMFS128=y +# CONFIG_USER_RAMIMAGE_RAMFS256 is not set +# CONFIG_USER_RAMIMAGE_RAMFS512 is not set +# CONFIG_USER_RAMIMAGE_RAMFS1024 is not set +# CONFIG_USER_RAMIMAGE_RAMFS2048 is not set +# CONFIG_USER_RAMIMAGE_RAMFS8192 is not set +# CONFIG_USER_CGI_GENERIC is not set +# CONFIG_USER_CGIHTML is not set +# CONFIG_USER_DEMO_BUTTON is not set +# CONFIG_USER_DEMO_LATCH is not set +# CONFIG_USER_DEMO_MORSE is not set +# CONFIG_USER_DEMO_R2100 is not set + +# +# Debug Builds +# +CONFIG_LIB_DEBUG=y +CONFIG_USER_DEBUG=y + +# +# Debug tools +# +# CONFIG_USER_TIMEPEG_TPT is not set + +# +# Debug libraries +# +# CONFIG_LIB_LIBCCMALLOC is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor-2.4.x uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor-2.4.x --- old/uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor-2.4.x 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/config.vendor-2.4.x 2005-06-08 10:27:01.000000000 +0800 @@ -0,0 +1,519 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Core Applications +# +CONFIG_USER_INIT_INIT=y +CONFIG_USER_INIT_CONSOLE_SH=y +# CONFIG_USER_INIT_RUN_FIREWALL is not set +CONFIG_USER_SASH_SH=y +# CONFIG_USER_SH_SH is not set +# CONFIG_USER_NWSH_SH is not set +# CONFIG_USER_BASH_BASH is not set +# CONFIG_USER_OTHER_SH is not set +# CONFIG_USER_SASH_HISTORY is not set +CONFIG_USER_SASH_REBOOT=y +# CONFIG_USER_SASH_SHUTDOWN is not set +CONFIG_USER_INIT_EXPAND=y +# CONFIG_USER_INIT_EXPAND_NOZEROES is not set +# CONFIG_USER_VERSION_VERSION is not set +CONFIG_USER_LOGIN_LOGIN=y +# CONFIG_USER_OLD_PASSWORDS is not set +# CONFIG_USER_ONLY_ROOT is not set +# CONFIG_USER_AGETTY_AGETTY is not set +# CONFIG_USER_GETTYD_GETTYD is not set +# CONFIG_USER_LOGIN_PASSWD is not set +# CONFIG_USER_CRON_CRON is not set +# CONFIG_USER_HWCLOCK_HWCLOCK is not set +# CONFIG_USER_RTC_M41T11 is not set +# CONFIG_USER_RTC_DS1302 is not set +# CONFIG_USER_VIXIECRON_CRON is not set +# CONFIG_USER_VIXIECRON_CRONTAB is not set +# CONFIG_USER_AT_AT is not set +# CONFIG_USER_AT_ATD is not set +# CONFIG_USER_AT_ATRUN is not set + +# +# Library Configuration +# +# CONFIG_LIB_LIBAES_FORCE is not set +# CONFIG_LIB_LIBDES_FORCE is not set +# CONFIG_LIB_LIBSSL_FORCE is not set +# CONFIG_LIB_LIBGMP_FORCE is not set +# CONFIG_LIB_LIBG_FORCE is not set +# CONFIG_LIB_LIBLDAP_FORCE is not set +# CONFIG_LIB_LIBPAM_FORCE is not set +# CONFIG_LIB_LIBPCAP_FORCE is not set +# CONFIG_LIB_ZLIB_FORCE is not set +# CONFIG_LIB_LIBATM_FORCE is not set +# CONFIG_LIB_LIBPNG_FORCE is not set +# CONFIG_LIB_LIBJPEG_FORCE is not set +# CONFIG_LIB_NCURSES_FORCE is not set +# CONFIG_LIB_UC_LIBC_TIMEZONE is not set + +# +# Flash Tools +# +# CONFIG_USER_FLASHW_FLASHW is not set +# CONFIG_USER_NETFLASH_NETFLASH is not set +# CONFIG_USER_RECOVER_STATIC_TFTP is not set +# CONFIG_USER_RECOVER_RECOVER is not set +# CONFIG_USER_BOOTTOOLS_FLASHLOADER is not set +# CONFIG_USER_BOOTTOOLS_HIMEMLOADER is not set +# CONFIG_USER_MTDUTILS is not set +# CONFIG_USER_MTDUTILS_ERASE is not set +# CONFIG_USER_MTDUTILS_ERASEALL is not set +# CONFIG_USER_MTDUTILS_FTL_CHECK is not set +# CONFIG_USER_MTDUTILS_FTL_FORMAT is not set +# CONFIG_USER_MTDUTILS_MKFSJFFS is not set +# CONFIG_USER_MTDUTILS_MKFSJFFS2 is not set +# CONFIG_USER_MTDUTILS_NFTLDUMP is not set +# CONFIG_USER_MTDUTILS_NFTL_FORMAT is not set +# CONFIG_USER_MTDUTILS_NANDDUMP is not set +# CONFIG_USER_MTDUTILS_NANDTEST is not set +# CONFIG_USER_MTDUTILS_NANDWRITE is not set +# CONFIG_USER_MTDUTILS_DOC_LOADBIOS is not set +# CONFIG_USER_MTDUTILS_DOC_LOADIPL is not set + +# +# Filesystem Applications +# +# CONFIG_USER_FLATFSD_FLATFSD is not set +# CONFIG_USER_MOUNT_MOUNT is not set +# CONFIG_USER_MOUNT_UMOUNT is not set +# CONFIG_USER_FDISK_FDISK is not set +# CONFIG_USER_FDISK_SFDISK is not set +# CONFIG_USER_E2FSPROGS_E2FSCK_E2FSCK is not set +# CONFIG_USER_E2FSPROGS_MISC_MKE2FS is not set +# CONFIG_USER_E2FSPROGS_MISC_BADBLOCKS is not set +# CONFIG_USER_E2FSPROGS_MISC_CHATTR is not set +# CONFIG_USER_E2FSPROGS_MISC_DUMPE2FS is not set +# CONFIG_USER_E2FSPROGS_MISC_E2LABEL is not set +# CONFIG_USER_E2FSPROGS_MISC_FSCK is not set +# CONFIG_USER_E2FSPROGS_MISC_LSATTR is not set +# CONFIG_USER_E2FSPROGS_MISC_MKLOST_FOUND is not set +# CONFIG_USER_E2FSPROGS_MISC_TUNE2FS is not set +# CONFIG_USER_E2FSPROGS_MISC_UUIDGEN is not set +# CONFIG_USER_REISERFSPROGS is not set +# CONFIG_USER_REISERFSPROGS_DEBUGRESIERFS is not set +# CONFIG_USER_REISERFSPROGS_MKREISERFS is not set +# CONFIG_USER_REISERFSPROGS_REISERFSCK is not set +# CONFIG_USER_REISERFSPROGS_RESIZE_REISERFS is not set +# CONFIG_USER_REISERFSPROGS_UNPACK is not set +# CONFIG_USER_SAMBA is not set +# CONFIG_USER_SAMBA_SMBD is not set +# CONFIG_USER_SAMBA_NMBD is not set +# CONFIG_USER_SAMBA_SMBMOUNT is not set +# CONFIG_USER_SAMBA_SMBUMOUNT is not set +# CONFIG_USER_SMBMOUNT_SMBMOUNT is not set +# CONFIG_USER_SMBMOUNT_SMBUMOUNT is not set +# CONFIG_USER_CRAMFS_CRAMFSCK is not set +# CONFIG_USER_CRAMFS_MKCRAMFS is not set + +# +# Network Applications +# +# CONFIG_USER_ROUTE_ARP is not set +# CONFIG_USER_FNORD_HTTPD is not set +# CONFIG_USER_BOA_SRC_BOA is not set +# CONFIG_USER_BPALOGIN_BPALOGIN is not set +# CONFIG_USER_BR2684CTL_BR2684CTL is not set +# CONFIG_USER_BRCFG_BRCFG is not set +# CONFIG_USER_BRCTL_BRCTL is not set +# CONFIG_USER_DHCPCD_DHCPCD is not set +# CONFIG_USER_DHCPCD_NEW_DHCPCD is not set +# CONFIG_USER_DHCPD_DHCPD is not set +# CONFIG_USER_DHCP_ISC_SERVER_DHCPD is not set +# CONFIG_USER_DHCP_ISC_CLIENT_DHCLIENT is not set +# CONFIG_USER_DHCP_ISC_RELAY_DHCRELAY is not set +# CONFIG_USER_DIALD_DIALD is not set +# CONFIG_USER_DISCARD_DISCARD is not set +# CONFIG_USER_DNSMASQ_DNSMASQ is not set +# CONFIG_USER_ETHATTACH_ETHATTACH is not set +# CONFIG_USER_EZIPUPDATE_EZIPUPDATE is not set +# CONFIG_USER_FTP_FTP_FTP is not set +# CONFIG_USER_FTPD_FTPD is not set +# CONFIG_USER_FREESWAN is not set +# CONFIG_USER_HTTPD_HTTPD is not set +# CONFIG_USER_IFATTACH_IFATTACH is not set +# CONFIG_USER_ROUTE_IFCONFIG is not set +# CONFIG_USER_INETD_INETD is not set +# CONFIG_USER_IPCHAINS_IPCHAINS is not set +# CONFIG_USER_IPFWADM_IPFWADM is not set +# CONFIG_USER_IPMASQADM_IPMASQADM is not set +# CONFIG_USER_IPPORTFW_IPPORTFW is not set +# CONFIG_USER_IPREDIR_IPREDIR is not set +# CONFIG_USER_IPROUTE2 is not set +# CONFIG_USER_IPTABLES_IPTABLES is not set +# CONFIG_USER_KENDIN_CONFIG is not set +# CONFIG_USER_KLAXON_KLAXON is not set +# CONFIG_USER_L2TPD_L2TPD is not set +# CONFIG_USER_LOATTACH_LOATTACH is not set +# CONFIG_USER_SMTP_SMTPCLIENT is not set +# CONFIG_USER_MAIL_MAIL_IP is not set +# CONFIG_USER_MINI_HTTPD_MINI_HTTPD is not set +# CONFIG_USER_MSNTP_MSNTP is not set +# CONFIG_USER_NESSUS_NASL is not set +# CONFIG_USER_ROUTE_NETSTAT is not set +# CONFIG_USER_NETSTAT_NAT_NETSTAT_NAT is not set +# CONFIG_USER_ROUTE_MIITOOL is not set +# CONFIG_USER_NTPD_NTPD is not set +# CONFIG_USER_NTPD_NTPDATE is not set +# CONFIG_USER_NTPD_NTPQ is not set +# CONFIG_USER_OPENSSL_APPS is not set +# CONFIG_USER_PING_PING is not set +# CONFIG_USER_HELLO_HELLO is not set +# CONFIG_USER_PLUG_PLUG is not set +CONFIG_USER_PORTMAP_PORTMAP=y +# CONFIG_USER_PPPD_PPPD_PPPD is not set +# CONFIG_USER_PPTPD_PPTPCTRL is not set +# CONFIG_USER_PPTPD_PPTPD is not set +# CONFIG_USER_PPTP_CLIENT_PPTP is not set +# CONFIG_USER_PPTP_CLIENT_PPTP_CALLMGR is not set +# CONFIG_USER_RDATE_RDATE is not set +# CONFIG_USER_ROUTE_ROUTE is not set +# CONFIG_USER_ROUTED_ROUTED is not set +# CONFIG_USER_RP_PPPOE_PPPOE is not set +# CONFIG_USER_RP_PPPOE_PPPOE_SERVER is not set +# CONFIG_USER_SETHDLC_SETHDLC is not set +# CONFIG_USER_SLATTACH_SLATTACH is not set +# CONFIG_USER_SNMPD_SNMPD is not set +# CONFIG_USER_STUNNEL_STUNNEL is not set +# CONFIG_USER_SSLWRAP_SSLWRAP is not set +# CONFIG_USER_SQUID_SQUID is not set +# CONFIG_USER_SSH_SSH is not set +# CONFIG_USER_SSH_SSHD is not set +# CONFIG_USER_SSH_SSHKEYGEN is not set +# CONFIG_USER_STP_STP is not set +# CONFIG_USER_TCPWRAP_TCPD is not set +# CONFIG_USER_TCPBLAST_TCPBLAST is not set +# CONFIG_USER_TCPDUMP_TCPDUMP is not set +# CONFIG_USER_TELNETD_TELNETD is not set +# CONFIG_USER_TELNET_TELNET is not set +# CONFIG_USER_TFTP_TFTP is not set +# CONFIG_USER_TFTPD_TFTPD is not set +# CONFIG_USER_THTTPD_THTTPD is not set +# CONFIG_USER_TRACEROUTE_TRACEROUTE is not set +# CONFIG_USER_UCDSNMP_SNMPD is not set +# CONFIG_USER_VCONFIG_VCONFIG is not set +# CONFIG_USER_VPNLED_VPNLED is not set +# CONFIG_USER_WGET is not set +# CONFIG_USER_ZEBRA_ZEBRA_ZEBRA is not set +# CONFIG_USER_NET_TOOLS_ARP is not set +# CONFIG_USER_NET_TOOLS_HOSTNAME is not set +# CONFIG_USER_NET_TOOLS_IFCONFIG is not set +# CONFIG_USER_NET_TOOLS_NAMEIF is not set +# CONFIG_USER_NET_TOOLS_NETSTAT is not set +# CONFIG_USER_NET_TOOLS_PLIPCONFIG is not set +# CONFIG_USER_NET_TOOLS_RARP is not set +# CONFIG_USER_NET_TOOLS_ROUTE is not set +# CONFIG_USER_NET_TOOLS_SLATTACH is not set +# CONFIG_USER_NET_TOOLS_MII_TOOL is not set +# CONFIG_USER_WIRELESS_TOOLS is not set +# CONFIG_USER_HOSTAP_HOSTAP is not set +# CONFIG_USER_WLAN_NG is not set + +# +# Miscellaneous Applications +# +# CONFIG_USER_LANG_A60 is not set +# CONFIG_USER_CAL_CAL is not set +# CONFIG_USER_CHAT_CHAT is not set +# CONFIG_USER_CKSUM_CKSUM is not set +# CONFIG_USER_CLOCK_CLOCK is not set +# CONFIG_USER_CPU_CPU is not set +# CONFIG_USER_CAL_DATE is not set +# CONFIG_USER_DHRYSTONE_DHRYSTONE is not set +# CONFIG_USER_DE2TSCAL_DE2TSCAL is not set +# CONFIG_USER_FROB_LED_FROB_LED is not set +# CONFIG_USER_GDBSERVER_GDBREPLAY is not set +CONFIG_USER_GDBSERVER_GDBSERVER=y +# CONFIG_USER_HD_HD is not set +# CONFIG_USER_LCD_LCD is not set +# CONFIG_USER_LEDCON_LEDCON is not set +# CONFIG_USER_LILO_LILO is not set +# CONFIG_USER_LISSA_LISSA is not set +# CONFIG_USER_USBCBI_USBCBI is not set +# CONFIG_USER_USBISO_USBISO is not set +# CONFIG_USER_MATH_TEST is not set +# CONFIG_USER_MAWK_AWK is not set +# CONFIG_USER_MYSQL is not set +# CONFIG_USER_NULL_NULL is not set +# CONFIG_USER_PALMBOT_PALMBOT is not set +# CONFIG_USER_PCMCIA_CS is not set +# CONFIG_USER_PERL_PERL is not set +# CONFIG_USER_PYTHON_PYTHON is not set +# CONFIG_USER_READPROFILE_READPROFILE is not set +# CONFIG_USER_ROOTLOADER_ROOTLOADER is not set +# CONFIG_USER_SETSERIAL_SETSERIAL is not set +# CONFIG_USER_TRIPWIRE_SIGGEN is not set +# CONFIG_USER_STRACE_STRACE is not set +# CONFIG_USER_STTY_STTY is not set +# CONFIG_USER_TCSH_TCSH is not set +# CONFIG_USER_TINYTCL_TCLSH is not set +# CONFIG_USER_THREADDEMOS_THREADDEMOS is not set +# CONFIG_USER_TIP_TIP is not set +# CONFIG_USER_TRIPWIRE_TRIPWIRE is not set +# CONFIG_USER_LRZSZ_LRZSZ is not set +# CONFIG_USER_LIRC is not set +# CONFIG_USER_LIRC_LIRCD is not set +# CONFIG_USER_LIRC_IRRECORD is not set +# CONFIG_USER_LIRC_LIRCMD is not set +# CONFIG_USER_LIRC_IREXEC is not set +# CONFIG_USER_LIRC_IRW is not set +# CONFIG_USER_LIRC_MODE2 is not set +# CONFIG_USER_LEVEE_VI is not set +# CONFIG_USER_ELVISTINY_VI is not set +# CONFIG_USER_MP3PLAY_MP3PLAY is not set +# CONFIG_USER_OGGPLAY_OGG123 is not set +# CONFIG_USER_OGGPLAY_EXAMPLE is not set +# CONFIG_USER_MUSICBOX_MUSICBOX is not set +# CONFIG_USER_PLAY_PLAY is not set +# CONFIG_USER_PLAY_TONE is not set +# CONFIG_USER_VPLAY_VPLAY is not set +# CONFIG_USER_VPLAY_VREC is not set +# CONFIG_USER_VPLAY_MIXER is not set +# CONFIG_USER_PLAYRT_PLAYRT is not set +# CONFIG_USER_W3CAM_VIDCAT is not set +# CONFIG_USER_W3CAM_W3CAMD is not set +# CONFIG_USER_FILEUTILS_CAT is not set +# CONFIG_USER_FILEUTILS_CHGRP is not set +# CONFIG_USER_FILEUTILS_CHMOD is not set +# CONFIG_USER_FILEUTILS_CHOWN is not set +# CONFIG_USER_FILEUTILS_CMP is not set +# CONFIG_USER_FILEUTILS_CP is not set +# CONFIG_USER_FILEUTILS_DD is not set +# CONFIG_USER_FILEUTILS_GREP is not set +# CONFIG_USER_FILEUTILS_L is not set +# CONFIG_USER_FILEUTILS_LN is not set +# CONFIG_USER_FILEUTILS_LS is not set +# CONFIG_USER_FILEUTILS_MKDIR is not set +# CONFIG_USER_FILEUTILS_MKFIFO is not set +# CONFIG_USER_FILEUTILS_MKNOD is not set +# CONFIG_USER_FILEUTILS_MORE is not set +# CONFIG_USER_FILEUTILS_MV is not set +# CONFIG_USER_FILEUTILS_RM is not set +# CONFIG_USER_FILEUTILS_RMDIR is not set +# CONFIG_USER_FILEUTILS_SYNC is not set +# CONFIG_USER_FILEUTILS_TOUCH is not set +# CONFIG_USER_SHUTILS_BASENAME is not set +# CONFIG_USER_SHUTILS_DATE is not set +# CONFIG_USER_SHUTILS_DIRNAME is not set +# CONFIG_USER_SHUTILS_ECHO is not set +# CONFIG_USER_SHUTILS_FALSE is not set +# CONFIG_USER_SHUTILS_LOGNAME is not set +# CONFIG_USER_SHUTILS_PRINTENV is not set +# CONFIG_USER_SHUTILS_PWD is not set +# CONFIG_USER_SHUTILS_TRUE is not set +# CONFIG_USER_SHUTILS_UNAME is not set +# CONFIG_USER_SHUTILS_WHICH is not set +# CONFIG_USER_SHUTILS_WHOAMI is not set +# CONFIG_USER_SHUTILS_YES is not set +# CONFIG_USER_SYSUTILS_REBOOT is not set +# CONFIG_USER_SYSUTILS_SHUTDOWN is not set +# CONFIG_USER_SYSUTILS_DF is not set +# CONFIG_USER_SYSUTILS_FREE is not set +# CONFIG_USER_SYSUTILS_HOSTNAME is not set +# CONFIG_USER_SYSUTILS_KILL is not set +# CONFIG_USER_SYSUTILS_PS is not set +# CONFIG_USER_PROCPS_FREE is not set +# CONFIG_USER_PROCPS_KILL is not set +# CONFIG_USER_PROCPS_PGREP is not set +# CONFIG_USER_PROCPS_PKILL is not set +# CONFIG_USER_PROCPS_PS is not set +# CONFIG_USER_PROCPS_SNICE is not set +# CONFIG_USER_PROCPS_SYSCTL is not set +# CONFIG_USER_PROCPS_TLOAD is not set +# CONFIG_USER_PROCPS_TOP is not set +# CONFIG_USER_PROCPS_UPTIME is not set +# CONFIG_USER_PROCPS_VMSTAT is not set +# CONFIG_USER_PROCPS_W is not set +# CONFIG_USER_PROCPS_WATCH is not set +# CONFIG_USER_PCIUTILS_LSPCI is not set +# CONFIG_USER_PCIUTILS_SETPCI is not set + +# +# BusyBox +# +CONFIG_USER_BUSYBOX_BUSYBOX=y +# CONFIG_USER_BUSYBOX_ADJTIMEX is not set +# CONFIG_USER_BUSYBOX_AR is not set +# CONFIG_USER_BUSYBOX_BASENAME is not set +# CONFIG_USER_BUSYBOX_CAT is not set +# CONFIG_USER_BUSYBOX_CHGRP is not set +CONFIG_USER_BUSYBOX_CHMOD=y +# CONFIG_USER_BUSYBOX_CHOWN is not set +# CONFIG_USER_BUSYBOX_CHROOT is not set +# CONFIG_USER_BUSYBOX_CLEAR is not set +# CONFIG_USER_BUSYBOX_CMP is not set +# CONFIG_USER_BUSYBOX_CP is not set +# CONFIG_USER_BUSYBOX_CUT is not set +# CONFIG_USER_BUSYBOX_DATE is not set +# CONFIG_USER_BUSYBOX_DC is not set +# CONFIG_USER_BUSYBOX_DD is not set +# CONFIG_USER_BUSYBOX_DF is not set +# CONFIG_USER_BUSYBOX_DIRNAME is not set +# CONFIG_USER_BUSYBOX_DMESG is not set +# CONFIG_USER_BUSYBOX_DUTMP is not set +# CONFIG_USER_BUSYBOX_DU is not set +# CONFIG_USER_BUSYBOX_ECHO is not set +# CONFIG_USER_BUSYBOX_ENV is not set +# CONFIG_USER_BUSYBOX_EXPR is not set +# CONFIG_USER_BUSYBOX_FIND is not set +# CONFIG_USER_BUSYBOX_FREE is not set +# CONFIG_USER_BUSYBOX_FREERAMDISK is not set +# CONFIG_USER_BUSYBOX_FSCK_MINIX is not set +# CONFIG_USER_BUSYBOX_GETOPT is not set +# CONFIG_USER_BUSYBOX_GREP is not set +# CONFIG_USER_BUSYBOX_GUNZIP is not set +# CONFIG_USER_BUSYBOX_GZIP is not set +# CONFIG_USER_BUSYBOX_HALT is not set +# CONFIG_USER_BUSYBOX_HEAD is not set +# CONFIG_USER_BUSYBOX_HOSTNAME is not set +# CONFIG_USER_BUSYBOX_ID is not set +CONFIG_USER_BUSYBOX_IFCONFIG=y +CONFIG_USER_BUSYBOX_IFCONFIG_STATUS=y +CONFIG_USER_BUSYBOX_IFCONFIG_SLIP=y +CONFIG_USER_BUSYBOX_IFCONFIG_HW=y +CONFIG_USER_BUSYBOX_IFCONFIG_MEMSTART_IOADDR_IRQ=y +# CONFIG_USER_BUSYBOX_INIT is not set +CONFIG_USER_BUSYBOX_INSMOD=y +CONFIG_USER_BUSYBOX_INSMOD_LOADINKMEM=y +CONFIG_USER_BUSYBOX_KILL=y +CONFIG_USER_BUSYBOX_KILLALL=y +# CONFIG_USER_BUSYBOX_KLOGD is not set +# CONFIG_USER_BUSYBOX_LENGTH is not set +CONFIG_USER_BUSYBOX_LN=y +# CONFIG_USER_BUSYBOX_LOGGER is not set +# CONFIG_USER_BUSYBOX_LOGNAME is not set +# CONFIG_USER_BUSYBOX_LS is not set +CONFIG_USER_BUSYBOX_LSMOD=y +# CONFIG_USER_BUSYBOX_MAKEDEVS is not set +# CONFIG_USER_BUSYBOX_MD5SUM is not set +# CONFIG_USER_BUSYBOX_MKDIR is not set +# CONFIG_USER_BUSYBOX_MKFS_MINIX is not set +CONFIG_USER_BUSYBOX_MKNOD=y +CONFIG_USER_BUSYBOX_MKTEMP=y +# CONFIG_USER_BUSYBOX_MODPROBE is not set +CONFIG_USER_BUSYBOX_MORE=y +CONFIG_USER_BUSYBOX_MOUNT=y +CONFIG_USER_BUSYBOX_MOUNT_LOOP=y +CONFIG_USER_BUSYBOX_MTAB_SUPPORT=y +CONFIG_USER_BUSYBOX_NFSMOUNT=y +# CONFIG_USER_BUSYBOX_MV is not set +# CONFIG_USER_BUSYBOX_NC is not set +# CONFIG_USER_BUSYBOX_NSLOOKUP is not set +# CONFIG_USER_BUSYBOX_PIDOF is not set +CONFIG_USER_BUSYBOX_PING=y +CONFIG_USER_BUSYBOX_FANCY_PING=y +# CONFIG_USER_BUSYBOX_PIVOT_ROOT is not set +# CONFIG_USER_BUSYBOX_POWEROFF is not set +# CONFIG_USER_BUSYBOX_PRINTF is not set +# CONFIG_USER_BUSYBOX_PS is not set +# CONFIG_USER_BUSYBOX_PWD is not set +# CONFIG_USER_BUSYBOX_RDATE is not set +# CONFIG_USER_BUSYBOX_READLINK is not set +# CONFIG_USER_BUSYBOX_REBOOT is not set +# CONFIG_USER_BUSYBOX_RENICE is not set +# CONFIG_USER_BUSYBOX_RESET is not set +# CONFIG_USER_BUSYBOX_RM is not set +CONFIG_USER_BUSYBOX_RMDIR=y +CONFIG_USER_BUSYBOX_RMMOD=y +CONFIG_USER_BUSYBOX_ROUTE=y +# CONFIG_USER_BUSYBOX_RPM2CPIO is not set +# CONFIG_USER_BUSYBOX_SED is not set +# CONFIG_USER_BUSYBOX_SHELL is not set +# CONFIG_USER_BUSYBOX_SLEEP is not set +# CONFIG_USER_BUSYBOX_SORT is not set +# CONFIG_USER_BUSYBOX_STTY is not set +# CONFIG_USER_BUSYBOX_SYNC is not set +# CONFIG_USER_BUSYBOX_SYSLOGD is not set +# CONFIG_USER_BUSYBOX_TAIL is not set +# CONFIG_USER_BUSYBOX_TAR is not set +# CONFIG_USER_BUSYBOX_TEE is not set +CONFIG_USER_BUSYBOX_TELNET=y +CONFIG_USER_BUSYBOX_TELNET_TTYPE=y +# CONFIG_USER_BUSYBOX_TEST is not set +# CONFIG_USER_BUSYBOX_TFTP is not set +# CONFIG_USER_BUSYBOX_TOUCH is not set +# CONFIG_USER_BUSYBOX_TR is not set +# CONFIG_USER_BUSYBOX_TRACEROUTE is not set +# CONFIG_USER_BUSYBOX_TRUE_FALSE is not set +# CONFIG_USER_BUSYBOX_TTY is not set +CONFIG_USER_BUSYBOX_UMOUNT=y +CONFIG_USER_BUSYBOX_MOUNT_FORCE=y +# CONFIG_USER_BUSYBOX_UNAME is not set +# CONFIG_USER_BUSYBOX_UNIQ is not set +# CONFIG_USER_BUSYBOX_UNIX2DOS is not set +# CONFIG_USER_BUSYBOX_UPTIME is not set +# CONFIG_USER_BUSYBOX_USLEEP is not set +# CONFIG_USER_BUSYBOX_UUDECODE is not set +# CONFIG_USER_BUSYBOX_UUENCODE is not set +CONFIG_USER_BUSYBOX_VI=y +CONFIG_USER_BUSYBOX_VI_COLON=y +# CONFIG_USER_BUSYBOX_VI_YANKMARK is not set +# CONFIG_USER_BUSYBOX_VI_SEARCH is not set +# CONFIG_USER_BUSYBOX_VI_USE_SIGNALS is not set +# CONFIG_USER_BUSYBOX_VI_DOT_CMD is not set +# CONFIG_USER_BUSYBOX_VI_READONLY is not set +# CONFIG_USER_BUSYBOX_VI_SETOPTS is not set +# CONFIG_USER_BUSYBOX_VI_SET is not set +# CONFIG_USER_BUSYBOX_VI_WIN_RESIZE is not set +# CONFIG_USER_BUSYBOX_WATCHDOG is not set +# CONFIG_USER_BUSYBOX_WC is not set +# CONFIG_USER_BUSYBOX_WGET is not set +# CONFIG_USER_BUSYBOX_WHICH is not set +# CONFIG_USER_BUSYBOX_WHOAMI is not set +# CONFIG_USER_BUSYBOX_XARGS is not set +# CONFIG_USER_BUSYBOX_YES is not set +CONFIG_USER_BUSYBOX_VERBOSE_USAGE=y +# CONFIG_USER_BUSYBOX_AUTOWIDTH is not set +CONFIG_USER_BUSYBOX_NEW_MODULE_INTERFACE=y +# CONFIG_USER_BUSYBOX_OLD_MODULE_INTERFACE is not set +# CONFIG_USER_BUSYBOX_INSMOD_VERSION_CHECKING is not set +# CONFIG_USER_BUSYBOX_HUMAN_READABLE is not set + +# +# Tinylogin +# +# CONFIG_USER_TINYLOGIN_TINYLOGIN is not set + +# +# MicroWindows +# +# CONFIG_USER_MICROWIN is not set + +# +# Games +# +# CONFIG_USER_GAMES_ADVENT4 is not set +# CONFIG_USER_GAMES_DUNGEON is not set +# CONFIG_USER_GAMES_RUBIK is not set + +# +# Miscellaneous Configuration +# +# CONFIG_USER_RAMIMAGE_NONE is not set +# CONFIG_USER_RAMIMAGE_RAMFS64 is not set +CONFIG_USER_RAMIMAGE_RAMFS128=y +# CONFIG_USER_RAMIMAGE_RAMFS256 is not set +# CONFIG_USER_RAMIMAGE_RAMFS512 is not set +# CONFIG_USER_RAMIMAGE_RAMFS1024 is not set +# CONFIG_USER_RAMIMAGE_RAMFS2048 is not set +# CONFIG_USER_RAMIMAGE_RAMFS8192 is not set +# CONFIG_USER_CGI_GENERIC is not set +# CONFIG_USER_CGIHTML is not set +# CONFIG_USER_DEMO_BUTTON is not set +# CONFIG_USER_DEMO_LATCH is not set +# CONFIG_USER_DEMO_MORSE is not set +# CONFIG_USER_DEMO_R2100 is not set + +# +# Debug Builds +# +CONFIG_LIB_DEBUG=y +CONFIG_USER_DEBUG=y +# CONFIG_USER_TIMEPEG_TPT is not set +# CONFIG_LIB_LIBCCMALLOC is not set diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/inittab uClinux-dist/vendors/PHILIPS/lpc2200/inittab --- old/uClinux-dist/vendors/PHILIPS/lpc2200/inittab 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/inittab 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,2 @@ +# inet:unknown:/bin/inetd +# boa:unknown:/bin/boa diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/Makefile uClinux-dist/vendors/PHILIPS/lpc2200/Makefile --- old/uClinux-dist/vendors/PHILIPS/lpc2200/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/Makefile 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,75 @@ +# +# Makefile -- Build instructions for GDB/ARMulator +# + +ROMFSIMG = $(IMAGEDIR)/romfs.img +IMAGE = $(IMAGEDIR)/image.bin +ELFIMAGE = $(IMAGEDIR)/image.elf + + +ROMFS_DIRS = bin dev etc home lib mnt proc usr var + +DEVICES = \ + tty,c,5,0 console,c,5,1 cua0,c,5,64 cua1,c,5,65 \ + \ + mem,c,1,1 kmem,c,1,2 null,c,1,3 ram0,b,1,0 \ + ram1,b,1,1 \ + \ + ptyp0,c,2,0 ptyp1,c,2,1 ptyp2,c,2,2 ptyp3,c,2,3 \ + ptyp4,c,2,4 ptyp5,c,2,5 ptyp6,c,2,6 ptyp7,c,2,7 \ + ptyp8,c,2,8 ptyp9,c,2,9 ptypa,c,2,10 ptypb,c,2,11 \ + ptypc,c,2,12 ptypd,c,2,13 ptype,c,2,14 ptypf,c,2,15 \ + \ + rom0,b,31,0 rom1,b,31,1 rom2,b,31,2 rom3,b,31,3 \ + rom4,b,31,4 rom5,b,31,5 rom6,b,31,6 rom7,b,31,7 \ + rom8,b,31,8 rom9,b,31,9 \ + \ + tty0,c,4,0 tty1,c,4,1 tty2,c,4,2 tty3,c,4,3 \ + ttyS0,c,4,64 ttyS1,c,4,65 \ + \ + ttyp0,c,3,0 ttyp1,c,3,1 ttyp2,c,3,2 ttyp3,c,3,3 \ + ttyp4,c,3,4 ttyp5,c,3,5 ttyp6,c,3,6 ttyp7,c,3,7 \ + ttyp8,c,3,8 ttyp9,c,3,9 ttypa,c,3,10 ttypb,c,3,11 \ + ttypc,c,3,12 ttypd,c,3,13 ttype,c,3,14 ttypf,c,3,15 \ + \ + zero,c,1,5 random,c,1,8 urandom,c,1,9 + + +clean: + +romfs: + [ -d $(ROMFSDIR)/$$i ] || mkdir -p $(ROMFSDIR) + for i in $(ROMFS_DIRS); do \ + [ -d $(ROMFSDIR)/$$i ] || mkdir -p $(ROMFSDIR)/$$i; \ + done + for i in $(DEVICES); do \ + touch $(ROMFSDIR)/dev/@$$i; \ + done + $(ROMFSINST) -s /var/tmp /tmp + $(ROMFSINST) -s /bin /sbin + $(ROMFSINST) /etc/rc + $(ROMFSINST) /etc/inittab + $(ROMFSINST) ../../Generic/romfs/etc/services /etc/services + case "$(LINUXDIR)" in \ + *2.4.*) ;; \ + *) echo "ttyS0:linux:/bin/sh" >> $(ROMFSDIR)/etc/inittab ;; \ + esac + $(ROMFSINST) /etc/motd + $(ROMFSINST) /etc/passwd + echo "$(VERSIONSTR) -- " `date` > $(ROMFSDIR)/etc/version + +image: + [ -d $(IMAGEDIR) ] || mkdir -p $(IMAGEDIR) + genromfs -v -V "ROMdisk" -f $(ROMFSIMG) -d $(ROMFSDIR) + $(CROSS_COMPILE)objcopy -O binary --remove-section=.romvec \ + --remove-section=.text --remove-section=.ramvec \ + --remove-section=.init \ + --remove-section=.bss --remove-section=.eram \ + $(ROOTDIR)/$(LINUXDIR)/linux $(IMAGEDIR)/linux.data + $(CROSS_COMPILE)objcopy -O binary --remove-section=.ramvec \ + --remove-section=.bss --remove-section=.data \ + --remove-section=.eram \ + --set-section-flags=.romvec=CONTENTS,ALLOC,LOAD,READONLY,CODE \ + $(ROOTDIR)/$(LINUXDIR)/linux $(IMAGEDIR)/linux.text + cat $(IMAGEDIR)/linux.text $(IMAGEDIR)/linux.data $(ROMFSIMG) > $(IMAGE) + diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/motd uClinux-dist/vendors/PHILIPS/lpc2200/motd --- old/uClinux-dist/vendors/PHILIPS/lpc2200/motd 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/motd 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,14 @@ +Welcome to + ____ _ _ + / __| ||_| + _ _| | | | _ ____ _ _ _ _ + | | | | | | || | _ \| | | |\ \/ / + | |_| | |__| || | | | | |_| |/ \ + | ___\____|_||_|_| |_|\____|\_/\_/ + | | + |_| + +GDB/ARMulator support by +For further information check: +http://www.uclinux.org/ + diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/passwd uClinux-dist/vendors/PHILIPS/lpc2200/passwd --- old/uClinux-dist/vendors/PHILIPS/lpc2200/passwd 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/passwd 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1 @@ +passwd abvQyXa0CDjIA diff -Naur old/uClinux-dist/vendors/PHILIPS/lpc2200/rc uClinux-dist/vendors/PHILIPS/lpc2200/rc --- old/uClinux-dist/vendors/PHILIPS/lpc2200/rc 1970-01-01 08:00:00.000000000 +0800 +++ uClinux-dist/vendors/PHILIPS/lpc2200/rc 2005-01-06 09:12:12.000000000 +0800 @@ -0,0 +1,10 @@ +hostname GDB-ARMulator +/bin/expand /etc/ramfs.img /dev/ram0 +mount -t proc proc /proc +mount -t ext2 /dev/ram0 /var +mkdir /var/tmp +mkdir /var/log +mkdir /var/run +mkdir /var/lock +mkdir /var/empty +cat /etc/motd skyeye-1.2.5_REL/misc/auto_test/0000755000175000001440000000000011023514411015170 5ustar kshusersskyeye-1.2.5_REL/misc/auto_test/auto_test0000755000175000001440000000332110541455476017147 0ustar kshusers#!/usr/bin/expect # # Author: Michael Kang(blackfin.kang@gmail.com) # Purpose: autoTest all the testcases in the skyeye testsuite. # set TITLE "SkyEye Auto Test" puts "*********************************\r" puts "Start $TITLE\r" puts "*********************************\r" #set skyeye_penv(PWD) # add directory of all the test case set path { at91/uclinux_rtl8019/ at91/uclinux_cs8900a at91/at91_with_framebuffer_touchscreen at91rm9200/2.6.x ep7312/2.6.x ep7312/ep7312_with_framebuffer_touchscreen_minigui ep9312/2.6.x s3c2410/2.4.18 s3c4510/ pxa/2.6.x pxa/with_flash_net_lcd pxa/pxa27x cs89712/ strongarm/ blackfin/ } set timeout 180 set case_num 1 set failed_num 0 set pass_num 0 set report_date [exec date --iso-8601=date] # open a file as report set file [open test_report_$report_date w] puts $file " SkyEye test report" puts $file "Date : [exec date]" puts $file " " set skyeye_sh { ./exec_skyeye.sh ./exec_skyeye_dbct.sh } foreach skyeye_element $skyeye_sh { foreach element $path { spawn $skyeye_element $element $env(PWD) expect { # we think when appear "command shell" , testcase is passed "shell" { puts $file "Case $case_num: $skyeye_element $element ...PASSED\n" incr pass_num } timeout { puts $file "Case $case_num: $skyeye_element $element ...FAILED\n" incr failed_num } } incr case_num system "killall skyeye" } } set total_num [expr $case_num-1] puts " \r" puts "Total $total_num , failed $failed_num , pass $pass_num " puts "\r$TITLE ............\r" # write to a txt file as report puts $file "Total $total_num , failed $failed_num , pass $pass_num " skyeye-1.2.5_REL/misc/auto_test/README.daily0000644000175000001440000000013510541455476017173 0ustar kshusersset the two variables(TESTSUITE_PATH,DEVELOPER_NAME) to correct values and run daily_test.sh skyeye-1.2.5_REL/misc/auto_test/README0000644000175000001440000000107510541455476016076 0ustar kshusersautotest Version 0.2 Author: Kang Shuo, Chen Yu Description : AutoTest all the testcase in SkyEye testsuite. Usage: 0 get skyeye source, compile it and get skyeye binary code. 1 place daily_test.sh, auto_test, exec_skyeye.sh, exec_skyeye_dbct.sh, skyeye binary code into testsuite2 directoy 2 cd testsuite2 directory, run ./auto_test. You can select testcases by modify path variable in auto_test script. NOTE: if you can cvs co skyeye-v1, then just edit daily_test.sh and set the two variables(TESTSUITE_PATH,DEVELOPER_NAME) to fit your environment and run daily_test.sh skyeye-1.2.5_REL/misc/auto_test/exec_skyeye.sh0000755000175000001440000000064610560775671020100 0ustar kshusers#/bin/sh cd "$1" skyeye_path="$2" if test "x$OSTYPE" == "xmsys" || test "x$TERM" == "xcygwin"; then SKYEYE="${skyeye_path}/skyeye.exe" else SKYEYE="${skyeye_path}/skyeye" fi test -e linux && "$SKYEYE" -e linux -c skyeye.conf test -e vmlinux && "$SKYEYE" -e vmlinux -c skyeye.conf test -e vmlinux.large && "$SKYEYE" -e vmlinux.large -c skyeye.conf test -e vmlinux-8-332 && "$SKYEYE" -e vmlinux-8-332 -c skyeye.conf skyeye-1.2.5_REL/misc/auto_test/daily_test.sh0000644000175000001440000000172510541455476017715 0ustar kshusers#!/bin/bash TESTSUITE_PATH=/home/chy/develop/testsuite2 DEVELOPER_NAME=chenyu export CVSROOT=":ext:${DEVELOPER_NAME}@gro.clinux.org:/cvsroot/skyeye" export CVS_RSH="ssh" cd ${TESTSUITE_PATH}/ #Zero step: clean old files rm -rf ./skyeye-v1 rm -f ./skyeye ./auto_test ./exec_skyeye.sh ./exec_skyeye_dbct.sh #First step: check newest source from cvs cvs -z3 -d:ext:${DEVELOPER_NAME}@cvs.gro.clinux.org:/cvsroot/skyeye co skyeye-v1 #build skyeye with DBCT function #cp -f ${TESTSUITE_PATH}/Makefile_gcc-3.3_with_DBCT_X86_32 skyeye-v1/ #second step: build skyeye image cd skyeye-v1 #make CC=gcc-3.3 -C skyeye-v1 make -f Makefile_gcc-3.3_with_DBCT_X86_32 cd .. #third step: copy some files into testsuite path,and run cp skyeye-v1/binary/skyeye ${TESTSUITE_PATH}/ cp skyeye-v1/utils/tools/auto_test/auto_test ${TESTSUITE_PATH}/ cp skyeye-v1/utils/tools/auto_test/exec_skyeye.sh ${TESTSUITE_PATH}/ cp skyeye-v1/utils/tools/auto_test/exec_skyeye_dbct.sh ${TESTSUITE_PATH}/ ./auto_test skyeye-1.2.5_REL/misc/auto_test/another_auto_test0000644000175000001440000001054110561755240020660 0ustar kshusers#!/bin/sh # # Author: Anthony Lee # Purpose: # Test all the testcases automatically in the skyeye testsuite. # On MinGW/CygWin/BeOS, there are none "expect". # TITLE="SkyEye Auto Test" TEST_PATH=" at91/uclinux_rtl8019 \ at91/uclinux_cs8900a \ at91/at91_with_framebuffer_touchscreen \ at91rm9200/2.6.x \ ep7312/2.6.x \ ep7312/ep7312_with_framebuffer_touchscreen_minigui \ ep9312/2.6.x \ s3c2410/2.4.18 \ s3c4510 \ pxa/2.6.x \ pxa/with_flash_net_lcd pxa/pxa27x \ cs89712 \ strongarm \ blackfin" SKYEYE_SH="./exec_skyeye.sh" if test "x$NO_DBCT" == "x"; then SKYEYE_SH="$SKYEYE_SH ./exec_skyeye_dbct.sh" fi # wait 5 minutes, sometimes it spends more time by this script. TIMEOUT=300 CASE_NUM=1 FAILED_NUM=0 PASS_NUM=0 SKYEYE_RUNNING_STATE=0 REPORT_DATE=`date --iso-8601=date` PWD=`dirname "$0"` OUTPUT="${PWD}/test_report_${REPORT_DATE}" TMP="${PWD}/tmp1_${REPORT_DATE}" TIMEOUT_TMP="${PWD}/tmp2_${REPORT_DATE}" TIMEOUT_REQUESTED_TMP="${PWD}/tmp3_${REPORT_DATE}" # set title set_terminal_title () { printf "\033]0;$1\007" } # pause pause () { echo $1 read } # puts puts () { if test "x$2" == "x"; then echo "$1" else echo "$2" cat >> $1 <<_______EOF $2 _______EOF fi } # kill the running skyeye kill_skyeye () { if test "x$OSTYPE" == "xbeos"; then kill -9 skyeye > /dev/null 2>&1 else PID=`ps auwx | grep skyeye | awk '{print $1}'` if test "x$PID" != "x"; then kill -9 $PID > /dev/null 2>&1 fi fi } catch_pipe () { if read MESSAGE_FROM_PIPE; then echo "$MESSAGE_FROM_PIPE" >> "$TMP" IS_GET_SHELL=`echo "$MESSAGE_FROM_PIPE" | grep "shell"` if test "x$IS_GET_SHELL" != "x"; then # we think when appear "command shell" , testcase is passed SKYEYE_RUNNING_STATE=1 fi else # error SKYEYE_RUNNING_STATE=2 fi } # run single test run_test () { puts "$OUTPUT" " " puts "Running \"$1 $2\"..." rm -f "$TMP" if "$1" "$2" "$PWD" | "$0" --check; then puts "$OUTPUT" "Case $CASE_NUM: $1 $2 ...PASSED" PASS_NUM=`expr $PASS_NUM + 1` else puts "$OUTPUT" "Case $CASE_NUM: $1 $2 ...FAILED" FAILED_NUM=`expr $FAILED_NUM + 1` echo "####################################################" >> "$OUTPUT" if test -e "$TMP"; then cat "$TMP" >> "$OUTPUT" else echo "The file is inexistent" >> "$OUTPUT" fi echo "####################################################" >> "$OUTPUT" fi CASE_NUM=`expr $CASE_NUM + 1` } # run tests run_tests () { for element in $TEST_PATH; do \ run_test "$1" "$element"; \ done } # main process if test "x$OSTYPE" == "xbeos"; then if [ ! -t 1 ]; then # Launched from Tracker; open a shell window and run from there. export INWINDOW=1 Terminal /bin/sh "$0" unset INWINDOW exit 0 fi fi cd "$PWD" if test "x$1" == "x--check"; then SKYEYE_CHECK_RETVAL=0 rm -f "$TIMEOUT_TMP" rm -f "$TIMEOUT_REQUESTED_TMP" "$0" --timeout & while true; do catch_pipe if test $SKYEYE_RUNNING_STATE -ne 0; then if test $SKYEYE_RUNNING_STATE -ne 1; then SKYEYE_CHECK_RETVAL=1 fi break fi if test -e "$TIMEOUT_TMP"; then SKYEYE_CHECK_RETVAL=1 break fi done # wait for the timeout checking proccess to be quit if ! test -e "$TIMEOUT_TMP"; then echo " " > "$TIMEOUT_REQUESTED_TMP" while true; do if test -e "$TIMEOUT_TMP"; then break else sleep 1 fi done fi rm -f "$TIMEOUT_TMP" rm -f "$TIMEOUT_REQUESTED_TMP" exit $SKYEYE_CHECK_RETVAL elif test "x$1" == "x--timeout"; then ENDTIME=`date +%s` ENDTIME=`expr $ENDTIME + $TIMEOUT` while true; do sleep 2 CURTIME=`date +%s` if test -e "$TIMEOUT_REQUESTED_TMP"; then # maybe something error while catch_pipe break fi if test $CURTIME -gt $ENDTIME; then # timeout break fi done kill_skyeye echo " " > "$TIMEOUT_TMP" exit 0 fi set_terminal_title "$TITLE" puts "*********************************" puts "Start $TITLE" puts "*********************************" rm -f "$TMP" rm -f "$OUTPUT" puts "$OUTPUT" " SkyEye test report" puts "$OUTPUT" "Date : `date -R`" puts "$OUTPUT" " " for skyeye_element in $SKYEYE_SH; do \ run_tests "$skyeye_element"; \ done TOTAL_NUM=`expr $CASE_NUM - 1` puts "$OUTPUT" " " puts "$OUTPUT" "Total $TOTAL_NUM , failed $FAILED_NUM , pass $PASS_NUM " puts "$TITLE ............" rm -f "$TMP" rm -f "$TIMEOUT_TMP" rm -f "$TIMEOUT_REQUESTED_TMP" echo. pause "Press any key to quit ..." skyeye-1.2.5_REL/misc/auto_test/exec_skyeye_dbct.sh0000755000175000001440000000067210560775671021073 0ustar kshusers#/bin/sh cd "$1" skyeye_path="$2" if test "x$OSTYPE" == "xmsys" || test "x$TERM" == "xcygwin"; then SKYEYE="${skyeye_path}/skyeye.exe" else SKYEYE="${skyeye_path}/skyeye" fi test -e linux && "$SKYEYE" -e linux -c skyeye_dbct.conf test -e vmlinux && "$SKYEYE" -e vmlinux -c skyeye_dbct.conf test -e vmlinux.large && "$SKYEYE" -e vmlinux.large -c skyeye_dbct.conf test -e vmlinux-8-332 && "$SKYEYE" -e vmlinux-8-332 -c skyeye_dbct.conf skyeye-1.2.5_REL/misc/gdb/0000755000175000001440000000000011023514411013715 5ustar kshusersskyeye-1.2.5_REL/misc/gdb/skyeye_1.2_for_gdb_6.4.diff0000644000175000001440000010467010576117535020543 0ustar kshusersdiff -Nur skyeye-v1_Rel/gdb642skyeye.patch skyeye-v1_gdb/gdb642skyeye.patch --- skyeye-v1_Rel/gdb642skyeye.patch 1969-12-31 19:00:00.000000000 -0500 +++ skyeye-v1_gdb/gdb642skyeye.patch 2007-02-01 04:45:02.000000000 -0500 @@ -0,0 +1,879 @@ +diff -ruNa --exclude=CVS gdb-6.4-old/configure gdb-6.4/configure +--- gdb-6.4-old/configure 2005-10-17 20:54:34.000000000 +0800 ++++ gdb-6.4/configure 2007-02-01 17:42:52.000000000 +0800 +@@ -11,6 +11,10 @@ + ac_help= + ac_default_prefix=/usr/local + # Any additions from configure.in: ++#teawater SKYEYE go back to GDB 2006.09.29 begin-------------------------------- ++ac_help="$ac_help ++ --enable-skyeye Link gdb with SKYEYE" ++#teawater SKYEYE go back to GDB 2006.09.29 end---------------------------------- + ac_help="$ac_help + --enable-libada Builds libada directory" + ac_help="$ac_help +@@ -418,7 +422,6 @@ + + esac + done +- + if test -n "$ac_prev"; then + { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; } + fi +@@ -2570,6 +2573,13 @@ + fi + done + ++#teawater SKYEYE go back to GDB 2006.09.29 begin-------------------------------- ++# Check whether --enable-skyeye or --disable-skyeye was given. ++if ! test "${enable_skyeye}" = no; then ++ configdirs="$configdirs skyeye" ++fi ++#teawater SKYEYE go back to GDB 2006.09.29 end---------------------------------- ++ + target_configdirs_all="$target_configdirs" + target_configdirs= + for i in ${target_configdirs_all} ; do +@@ -3206,7 +3216,6 @@ + bootstrap_suffix=no-bootstrap ;; + esac + +- + for module in ${build_configdirs} ; do + if test -z "${no_recursion}" \ + && test -f ${build_subdir}/${module}/Makefile; then +diff -ruNa --exclude=CVS gdb-6.4-old/gdb/configure gdb-6.4/gdb/configure +--- gdb-6.4-old/gdb/configure 2005-07-25 23:08:40.000000000 +0800 ++++ gdb-6.4/gdb/configure 2007-02-01 17:42:52.000000000 +0800 +@@ -905,6 +905,7 @@ + it to find libraries and programs with nonstandard names/locations. + + _ACEOF ++ + fi + + if test "$ac_init_help" = "recursive"; then +@@ -21634,6 +21635,26 @@ + ignore_sim=true + fi + ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- ++SKYEYE_OBS="skyeye-target.o" ++LIBSKYEYE="../skyeye/libskyeye.a" ++LIBSKYEYEGTK="`pkg-config gtk+-2.0 --libs`" ++DIST="gdbskyeye" ++if test ! -f ${LIBSKYEYE} ++then ++ SKYEYE_OBS="" ++ LIBSKYEYE="" ++ LIBSKYEYEGTK="" ++ IGNORE_RDP="" ++ DIST="gdb" ++else ++ #remove sim because some functions names of skyeye is same with gdb sim ++ ignore_sim=true ++ #remove rdp because it need gdb/sim/common/callback.c ++ IGNORE_RDP="TDEPFILES= arm-tdep.o remote-rdi.o" ++fi ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- ++ + if test "${ignore_sim}" = "true"; then + IGNORE_SIM="SIM=" + IGNORE_SIM_OBS="SIM_OBS=" +@@ -22694,6 +22715,7 @@ + # No need to generate the scripts if there are no CONFIG_FILES. + # This happens for instance when ./config.status config.h + if test -n "\$CONFIG_FILES"; then ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- + # Protect against being on the right side of a sed subst in config.status. + sed 's/,@/@@/; s/@,/@@/; s/,;t t\$/@;t t/; /@;t t\$/s/[\\\\&,]/\\\\&/g; + s/@@/,@/; s/@@/@,/; s/@;t t\$/,;t t/' >\$tmp/subs.sed <<\\CEOF +@@ -22876,7 +22898,13 @@ + s,@host_makefile_frag@,,;t t + /@target_makefile_frag@/r $target_makefile_frag + s,@target_makefile_frag@,,;t t ++s,@SKYEYE_OBS@,$SKYEYE_OBS,;t t ++s,@LIBSKYEYE@,$LIBSKYEYE,;t t ++s,@LIBSKYEYEGTK@,$LIBSKYEYEGTK,;t t ++s,@IGNORE_RDP@,$IGNORE_RDP,;t t ++s,@DIST@,$DIST,;t t + CEOF ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + + _ACEOF + +diff -ruNa --exclude=CVS gdb-6.4-old/gdb/Makefile.in gdb-6.4/gdb/Makefile.in +--- gdb-6.4-old/gdb/Makefile.in 2005-11-16 20:44:10.000000000 +0800 ++++ gdb-6.4/gdb/Makefile.in 2007-02-01 17:42:52.000000000 +0800 +@@ -184,12 +184,18 @@ + SUBDIR_MI_CFLAGS= \ + -DMI_OUT=1 + ++#teawater SKYEYE go back to GDB 2006.10.20 begin-------------------------------- ++DIST=@DIST@ ++#teawater SKYEYE go back to GDB 2006.10.20 end---------------------------------- ++ + # + # TUI sub directory definitions + # + + # Name of the TUI program +-TUI=gdbtui ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- ++TUI=$(DIST)tui ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + + SUBDIR_TUI_OBS = \ + tui-command.o \ +@@ -361,6 +367,12 @@ + # PROFILE_CFLAGS is _not_ included, however, because we use monstartup. + INTERNAL_LDFLAGS = $(CFLAGS) $(GLOBAL_CFLAGS) $(MH_LDFLAGS) $(LDFLAGS) $(CONFIG_LDFLAGS) + ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- ++SKYEYE_OBS = @SKYEYE_OBS@ ++LIBSKYEYE = @LIBSKYEYE@ ++LIBSKYEYEGTK = @LIBSKYEYEGTK@ ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- ++ + # If your system is missing alloca(), or, more likely, it's there but + # it doesn't work, then refer to libiberty. + +@@ -372,17 +384,21 @@ + INSTALLED_LIBS=-lbfd -lreadline -lopcodes -liberty \ + $(XM_CLIBS) $(TM_CLIBS) $(NAT_CLIBS) $(GDBTKLIBS) @LIBS@ \ + -lintl -liberty ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- + CLIBS = $(SIM) $(READLINE) $(OPCODES) $(BFD) $(INTL) $(LIBIBERTY) \ + $(XM_CLIBS) $(TM_CLIBS) $(NAT_CLIBS) $(GDBTKLIBS) @LIBS@ \ + $(LIBICONV) \ +- $(LIBIBERTY) $(WIN32LIBS) ++ $(LIBIBERTY) $(WIN32LIBS) $(LIBSKYEYE) $(LIBSKYEYEGTK) + CDEPS = $(XM_CDEPS) $(TM_CDEPS) $(NAT_CDEPS) $(SIM) $(BFD) $(READLINE) \ +- $(OPCODES) $(INTL_DEPS) $(LIBIBERTY) $(CONFIG_DEPS) ++ $(OPCODES) $(INTL_DEPS) $(LIBIBERTY) $(CONFIG_DEPS) $(LIBSKYEYE) ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + + ADD_FILES = $(XM_ADD_FILES) $(TM_ADD_FILES) $(NAT_ADD_FILES) + ADD_DEPS = $(XM_ADD_FILES) $(TM_ADD_FILES) $(NAT_ADD_FILES) + +-DIST=gdb ++#teawater SKYEYE go back to GDB 2006.10.20 begin-------------------------------- ++#DIST=gdb ++#teawater SKYEYE go back to GDB 2006.10.20 end---------------------------------- + + LINT=/usr/5bin/lint + LINTFLAGS= $(GDB_CFLAGS) $(OPCODES_CFLAGS) $(READLINE_CFLAGS) \ +@@ -418,6 +434,9 @@ + # + @IGNORE_SIM@ + @IGNORE_SIM_OBS@ ++#teawater SKYEYE go back to GDB 2006.10.04 begin-------------------------------- ++@IGNORE_RDP@ ++#teawater SKYEYE go back to GDB 2006.10.04 end---------------------------------- + + FLAGS_TO_PASS = \ + "prefix=$(prefix)" \ +@@ -880,8 +899,10 @@ + # variables analogous to SER_HARDWIRE which get defaulted in this + # Makefile.in + ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- + DEPFILES = $(TDEPFILES) $(SER_HARDWIRE) $(NATDEPFILES) \ +- $(REMOTE_OBS) $(SIM_OBS) ++ $(REMOTE_OBS) $(SIM_OBS) $(SKYEYE_OBS) ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + + SOURCES = $(SFILES) $(ALLDEPFILES) $(YYFILES) $(CONFIG_SRCS) + # Don't include YYFILES (*.c) because we already include *.y in SFILES, +@@ -968,8 +989,10 @@ + .c.o: + $(CC) -c $(INTERNAL_CFLAGS) $< + +-all: gdb$(EXEEXT) $(CONFIG_ALL) ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- ++all: $(DIST)$(EXEEXT) $(CONFIG_ALL) + @$(MAKE) $(FLAGS_TO_PASS) DO=all "DODIRS=`echo $(SUBDIRS) | sed 's/testsuite//'`" subdir_do ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + .PHONY: all-tui + all-tui: $(TUI)$(EXEEXT) + +@@ -1027,22 +1050,24 @@ + # time it takes for make to check that all is up to date. + # install-only is intended to address that need. + install: all install-only ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- + install-only: $(CONFIG_INSTALL) + transformed_name=`t='$(program_transform_name)'; \ +- echo gdb | sed -e "$$t"` ; \ ++ echo $(DIST) | sed -e "$$t"` ; \ + if test "x$$transformed_name" = x; then \ +- transformed_name=gdb ; \ ++ transformed_name=$(DIST) ; \ + else \ + true ; \ + fi ; \ + $(SHELL) $(srcdir)/../mkinstalldirs $(DESTDIR)$(bindir) ; \ +- $(INSTALL_PROGRAM) gdb$(EXEEXT) \ ++ $(INSTALL_PROGRAM) $(DIST)$(EXEEXT) \ + $(DESTDIR)$(bindir)/$$transformed_name$(EXEEXT) ; \ + $(SHELL) $(srcdir)/../mkinstalldirs \ + $(DESTDIR)$(man1dir) ; \ + $(INSTALL_DATA) $(srcdir)/gdb.1 \ + $(DESTDIR)$(man1dir)/$$transformed_name.1 + @$(MAKE) DO=install "DODIRS=$(SUBDIRS)" $(FLAGS_TO_PASS) subdir_do ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + .PHONY: install-tui + install-tui: + transformed_name=`t='$(program_transform_name)'; \ +@@ -1181,11 +1206,13 @@ + init.o: init.c $(defs_h) $(call_cmds_h) + + # Removing the old gdb first works better if it is running, at least on SunOS. +-gdb$(EXEEXT): gdb.o libgdb.a $(ADD_DEPS) $(CDEPS) $(TDEPLIBS) +- rm -f gdb$(EXEEXT) ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- ++$(DIST)$(EXEEXT): gdb.o libgdb.a $(ADD_DEPS) $(CDEPS) $(TDEPLIBS) ++ rm -f $(DIST)$(EXEEXT) + $(CC_LD) $(INTERNAL_LDFLAGS) $(WIN32LDAPP) \ +- -o gdb$(EXEEXT) gdb.o libgdb.a \ ++ -o $(DIST)$(EXEEXT) gdb.o libgdb.a \ + $(TDEPLIBS) $(TUI_LIBRARY) $(CLIBS) $(LOADLIBES) ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + + $(TUI)$(EXEEXT): tui-main.o libgdb.a $(ADD_DEPS) $(CDEPS) $(TDEPLIBS) + rm -f $(TUI)$(EXEEXT) +@@ -1217,9 +1244,11 @@ + # gdb and put a copy in gdb1, and you can run it with "gdb gdb1". + # Removing gdb1 before the copy is the right thing if gdb1 is open + # in another process. +-gdb1$(EXEEXT): gdb$(EXEEXT) +- rm -f gdb1$(EXEEXT) +- cp gdb$(EXEEXT) gdb1$(EXEEXT) ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- ++$(DIST)1$(EXEEXT): $(DIST)$(EXEEXT) ++ rm -f $(DIST)1$(EXEEXT) ++ cp $(DIST)$(EXEEXT) $(DIST)1$(EXEEXT) ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + + # Put the proper machine-specific files first, so M-. on a machine + # specific routine gets the one for the correct machine. (FIXME: those +@@ -1246,8 +1275,10 @@ + @$(MAKE) $(FLAGS_TO_PASS) DO=clean "DODIRS=$(SUBDIRS)" subdir_do + rm -f *.o *.a $(ADD_FILES) *~ init.c-tmp init.l-tmp version.c-tmp + rm -f init.c version.c +- rm -f gdb$(EXEEXT) core make.log +- rm -f gdb[0-9]$(EXEEXT) ++#teawater SKYEYE go back to GDB 2006.10.03 begin-------------------------------- ++ rm -f $(DIST)$(EXEEXT) core make.log ++ rm -f $(DIST)[0-9]$(EXEEXT) ++#teawater SKYEYE go back to GDB 2006.10.03 end---------------------------------- + rm -f test-cp-name-parser$(EXEEXT) + + .PHONY: clean-tui +@@ -3142,4 +3173,8 @@ + $(gdb_curses_h) $(gdb_assert_h) + $(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-winsource.c + ++#teawater SKYEYE go back to GDB 2006.10.04 begin-------------------------------- ++skyeye-target.o: skyeye-target.c ++ $(CC) -c $(INTERNAL_CFLAGS) -DMODET -I $(srcdir)/../skyeye-v1/arch/arm -I $(srcdir)/../skyeye-v1/arch/arm/common/ -I $(srcdir)/../skyeye-v1/arch/arm/common/mmu/ -I $(srcdir)/../skyeye-v1/arch/arm/mach/ -I $(srcdir/..)/skyeye-v1/arch/bfin/common -I $(srcdir)/../skyeye-v1/arch/bfin/mach -I $(srcdir)/../skyeye-v1/arch/coldfire/common -I $(srcdir)/../skyeye-v1/device/ -I $(srcdir)/../skyeye-v1/device/net -I $(srcdir)/../skyeye-v1/device/lcd -I $(srcdir)/../skyeye-v1/device/flash -I $(srcdir)/../skyeye-v1/utils/share -I $(srcdir)/../skyeye-v1/utils/main -I $(srcdir)/../skyeye-v1/utils/config -I $(srcdir)/../skyeye-v1/utils/debugger $< ++#teawater SKYEYE go back to GDB 2006.10.04 end---------------------------------- + ### end of the gdb Makefile.in. +diff -ruNa --exclude=CVS gdb-6.4-old/gdb/skyeye-target.c gdb-6.4/gdb/skyeye-target.c +--- gdb-6.4-old/gdb/skyeye-target.c 1970-01-01 08:00:00.000000000 +0800 ++++ gdb-6.4/gdb/skyeye-target.c 2007-02-01 17:42:53.000000000 +0800 +@@ -0,0 +1,506 @@ ++/* Debugging interface for SKYEYE. ++ Written by teawater(teawater@gmail.com) ++ ++ This file is part of GDB and SKYEYE. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 59 Temple Place - Suite 330, ++ Boston, MA 02111-1307, USA. */ ++ ++#include "defs.h" ++#include "inferior.h" ++#include "bfd.h" ++#include "symfile.h" ++#include "gdbcmd.h" ++#include "gdbcore.h" ++#include "serial.h" ++#include "target.h" ++#include "exceptions.h" ++#include "remote-utils.h" ++#include "gdb_string.h" ++#include "gdb_stat.h" ++#include "regcache.h" ++#include ++#include ++#include "mips-tdep.h" ++#include ++#include ++#include ++ ++#include "skyeye_types.h" ++#include "skyeye_defs.h" ++#include "skyeye_config.h" ++#include "armemu.h" ++#include "armdefs.h" ++ ++#define MAGIC_NULL_PID 42000 ++ ++generic_arch_t * arch_instance; ++char * skyeye_config_filename; ++int global_argc = 1; ++char org_global_argv[1][7] = {"skyeye"}; ++char ** global_argv; ++int debugmode = 0; ++int stop_simulator = 0; ++#define MAX_BREAKPOINTS 16 ++struct SkyEye_ICE{ ++ unsigned int bps[MAX_BREAKPOINTS]; ++ int num_bps; ++}; ++struct SkyEye_ICE skyeye_ice; ++extern ARMul_State * state; ++extern void initialize_all_arch (); ++extern int skyeye_option_init (skyeye_config_t * config); ++extern int sim_fetch_inferior_registers (int rn, unsigned char *memory); ++extern int sim_store_inferior_registers (int rn, unsigned char *memory); ++extern void init_register_type(); ++extern int sim_read (ARMword addr, unsigned char *buffer, int size); ++extern int sim_write (ARMword addr, unsigned char *buffer, int size); ++ ++struct termios skyeye_termios_old; ++void ++skyeye_exit(int ret) ++{ ++ /* Restore the original terminal settings */ ++ tcsetattr (0, TCSANOW, &skyeye_termios_old); ++ exit( ret); ++} ++extern cpu_config_t bfin_cpu[]; ++extern machine_config_t arm_machines[]; ++void ++display_all_support() ++{ ++ int i; ++ fprintf (stderr, ++ "----------- Architectures and CPUs simulated by SkyEye-------------\n"); ++ fprintf (stderr, "-------- ARM architectures ---------\n"); ++ for(i = 0; arm_machines[i].machine_name!=NULL ; i++) ++ fprintf(stderr, "%s \n",arm_machines[i].machine_name); ++ fprintf (stderr, "-------- BlackFin architectures ----\n"); ++ for(i = 0; bfin_cpu[i].cpu_name!=NULL ; i++) ++ fprintf(stderr, "%s \n",bfin_cpu[i].cpu_name); ++} ++ ++ARMword ++ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr) ++{ ++ return (0); ++} ++void ++ARMul_ConsolePrint (ARMul_State * state, const char *format, ...) ++{ ++} ++ ++int ++remote_interrupt() ++{ ++ return (0); ++} ++void ++usage () ++{ ++} ++ ++ ++ ++static struct target_ops skyeye_ops; ++static enum target_signal resume_siggnal; ++static int resume_step; ++static sigset_t skyeye_maskall; ++ ++ ++ ++static void skyeye_open (char *name, int from_tty); ++static void skyeye_close (int quitting); ++static void skyeye_create_inferior (char *exec_file, char *args, char **env, int from_tty); ++static void skyeye_mourn_inferior (void); ++static void skyeye_resume (ptid_t ptid, int step, enum target_signal siggnal); ++static ptid_t skyeye_wait (ptid_t ptid, struct target_waitstatus *status); ++static void skyeye_stop (void); ++static void skyeye_kill (void); ++static void skyeye_prepare_to_store (void); ++static void skyeye_fetch_registers (int regnum); ++static void skyeye_store_registers (int regnum); ++static int skyeye_insert_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache); ++static int skyeye_remove_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache); ++#if 0 ++static int skyeye_check_watch_resources (int type, int cnt, int ot); ++static int skyeye_insert_hw_breakpoint (CORE_ADDR addr, gdb_byte *shadow); ++static int skyeye_remove_hw_breakpoint (CORE_ADDR addr, gdb_byte *shadow); ++#endif ++static int skyeye_xfer_memory (CORE_ADDR mem_addr, gdb_byte *buffer, int mem_len, int should_write, struct mem_attrib *attrib, struct target_ops *target); ++static void init_skyeye_ops (void); ++ ++static void ++skyeye_open (char *name, int from_tty) ++{ ++ static int done = 0; ++ ++ if (!done) { ++ //get skyeye_config_filename ++ if (name == NULL || strlen(name) == 0) { ++ skyeye_config_filename = DEFAULT_CONFIG_FILE; ++ } ++ else { ++ skyeye_config_filename = name; ++ } ++ initialize_all_devices (); ++ initialize_all_arch (); ++ init_register_type(); ++ skyeye_option_init (&skyeye_config); ++ if (skyeye_read_config() < 0) { ++ error ("SKYEYE: read config file \"%s\" error.\n", skyeye_config_filename); ++ } ++ arch_instance = (generic_arch_t *) malloc (sizeof (generic_arch_t)); ++ if (!arch_instance) { ++ error ("SKYEYE: allocate memeory error.\n"); ++ } ++ arch_instance->init = skyeye_config.arch->init; ++ arch_instance->reset = skyeye_config.arch->reset; ++ arch_instance->step_once = skyeye_config.arch->step_once; ++ arch_instance->set_pc = skyeye_config.arch->set_pc; ++ arch_instance->get_pc = skyeye_config.arch->get_pc; ++ arch_instance->ICE_write_byte = skyeye_config.arch->ICE_write_byte; ++ arch_instance->ICE_read_byte = skyeye_config.arch->ICE_read_byte; ++ ++ arch_instance->init (); ++ arch_instance->reset (); ++ ++ done = 1; ++ } ++ else { ++ unpush_target (&skyeye_ops); ++ } ++ //arch_instance->reset (); ++ ++ push_target (&skyeye_ops); ++} ++ ++static void ++skyeye_close (int quitting) ++{ ++ ++} ++ ++static void ++skyeye_create_inferior (char *exec_file, char *args, char **env, int from_tty) ++{ ++ if (exec_file == 0 || exec_bfd == 0) { ++ warning (_("No executable file specified.")); ++ } ++ ++ //arch_instance->reset (); ++ ++ inferior_ptid = pid_to_ptid (MAGIC_NULL_PID); ++ remove_breakpoints (); ++ init_wait_for_inferior (); ++ insert_breakpoints (); ++ clear_proceed_status (); ++ ++ if (skyeye_config.start_address != 0) { ++ proceed ((CORE_ADDR) skyeye_config.start_address, TARGET_SIGNAL_DEFAULT, 0); ++ } ++ else { ++ proceed ((CORE_ADDR) -1, TARGET_SIGNAL_DEFAULT, 0); ++ } ++} ++ ++static void ++skyeye_mourn_inferior (void) ++{ ++ generic_mourn_inferior (); ++} ++ ++static void ++skyeye_resume (ptid_t ptid, int step, enum target_signal siggnal) ++{ ++ if (PIDGET (inferior_ptid) != MAGIC_NULL_PID) { ++ error (_("The program is not being run.")); ++ } ++ ++ resume_siggnal = siggnal; ++ resume_step = step; ++} ++ ++static void ++skyeye_sig_handler (int signo) ++{ ++ target_stop (); ++} ++ ++static ptid_t ++skyeye_wait (ptid_t ptid, struct target_waitstatus *status) ++{ ++ int err = 0; ++ //sig init ++#if defined (HAVE_SIGACTION) && defined (SA_RESTART) ++ struct sigaction act, old_act; ++ ++ act.sa_handler = skyeye_sig_handler; ++ act.sa_mask = skyeye_maskall; ++ act.sa_flags = SA_RESTART; ++ if (sigaction (SIGINT, &act, &old_act)) { ++ error ("SKYEYE: sigaction."); ++ } ++#else ++ static RETSIGTYPE (*prev_sigint) (); ++ ++ prev_sigint = signal (SIGINT, skyeye_sig_handler); ++ if (prev_sigint == SIG_ERR) { ++ error ("SKYEYE: signal."); ++ } ++#endif ++ ++ //skyeye resume ++ if(!strcmp(skyeye_config.arch->arch_name, "arm")){ ++ state->EndCondition = 0; ++ stop_simulator = 0; ++ ++ if (resume_step) { ++ state->Reg[15] = ARMul_DoInstr (state); ++ ++ /* ++ if (state->EndCondition == 0) { ++ //chy 20050729 ???? ++ //printf ("error in sim_resume for state->EndCondition"); ++ //skyeye_exit (-1); ++ err = -1; ++ goto CLEAR_SIG; ++ } ++ */ ++ } ++ else { ++ state->NextInstr = RESUME; /* treat as PC change */ ++ state->Reg[15] = ARMul_DoProg (state); ++ } ++ ++ FLUSHPIPE; ++ } ++ else { ++ do { ++ arch_instance->step_once (); ++ }while(!resume_step); ++ } ++ ++//CLEAR_SIG: ++ //clear sig ++#if defined (HAVE_SIGACTION) && defined (SA_RESTART) ++ if (sigaction (SIGALRM, &old_act, NULL)) { ++ error ("SKYEYE: sigaction."); ++ } ++#else ++ if (signal (SIGINT, prev_sigint) == SIG_ERR) { ++ error ("SKYEYE: signal."); ++ } ++#endif ++/* ++ if (err) { ++ error ("SKYEYE: error in sim_resume for state->EndCondition"); ++ } ++*/ ++ status->kind = TARGET_WAITKIND_STOPPED; ++ status->value.sig = TARGET_SIGNAL_TRAP; ++ return (inferior_ptid); ++} ++ ++static void ++skyeye_stop (void) ++{ ++ resume_step = 1; ++ state->EndCondition = 0; ++ state->Emulate = STOP; ++} ++ ++static void ++skyeye_kill (void) ++{ ++ inferior_ptid = null_ptid; ++} ++ ++static void ++skyeye_prepare_to_store (void) ++{ ++ /* Do nothing, since we can store individual regs */ ++} ++ ++static void ++skyeye_fetch_registers (int regnum) ++{ ++ if (regnum >= 0) { ++ char reg[MAX_REGISTER_SIZE]; ++ ++ /* ++ if (sim_fetch_register (regnum, reg) == -1) { ++ regcache_raw_supply (current_regcache, regnum, NULL); ++ } ++ else { ++ regcache_raw_supply (current_regcache, regnum, reg); ++ } ++ */ ++ //sim_fetch_register always return -1(who wrote it?) ++ sim_fetch_inferior_registers (regnum, reg) ; ++ regcache_raw_supply (current_regcache, regnum, reg); ++ } ++ else { ++ int i; ++ ++ for (i = 0; i < NUM_REGS; i++) { ++ skyeye_fetch_registers (i); ++ } ++ } ++} ++ ++static void ++skyeye_store_registers (int regnum) ++{ ++ if (regnum >= 0) { ++ char reg[MAX_REGISTER_SIZE]; ++ ++ regcache_raw_collect (current_regcache, regnum, reg); ++ //sim_store_register always return -1(who wrote it?) ++ /* ++ if (sim_store_register (regnum, reg) == -1) { ++ error ("SKYEYE: set value to reg %d error", regnum); ++ } ++ */ ++ if (sim_store_inferior_registers (regnum, reg)) { ++ error ("SKYEYE: set value to reg %d error", regnum); ++ } ++ if (regnum == PC_REGNUM) { ++ arch_instance->set_pc ((uint32_t) read_register (PC_REGNUM)); ++ } ++ } ++ else { ++ int i; ++ ++ for (i = 0; i < NUM_REGS; i++) { ++ skyeye_store_registers (i); ++ } ++ } ++} ++ ++static int ++skyeye_insert_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache) ++{ ++ return (memory_insert_breakpoint (addr, contents_cache)); ++} ++ ++static int ++skyeye_remove_breakpoint (CORE_ADDR addr, bfd_byte *contents_cache) ++{ ++ return (memory_remove_breakpoint (addr, contents_cache)); ++} ++ ++ ++ ++#if 0 ++static int ++skyeye_check_watch_resources (int type, int cnt, int ot) ++{ ++ if (type == bp_hardware_breakpoint) { ++ if (cnt > MAX_BREAKPOINTS) { ++ return (-1); ++ } ++ return (1); ++ } ++ ++ return (0); ++} ++ ++static int ++skyeye_insert_hw_breakpoint (CORE_ADDR addr, gdb_byte *shadow) ++{ ++ if (sim_ice_breakpoint_insert (addr)) { ++ return (-1); ++ } ++ ++ return (0); ++} ++ ++static int ++skyeye_remove_hw_breakpoint (CORE_ADDR addr, gdb_byte *shadow) ++{ ++ if (sim_ice_breakpoint_remove (addr)) { ++ return (-1); ++ } ++ ++ return (0); ++} ++#endif ++ ++static int ++skyeye_xfer_memory (CORE_ADDR mem_addr, gdb_byte *buffer, int mem_len, int should_write, struct mem_attrib *attrib, struct target_ops *target) ++{ ++ if (should_write) { ++ return (sim_write (mem_addr, buffer, mem_len)); ++ } ++ else { ++ return (sim_read (mem_addr, buffer, mem_len)); ++ } ++} ++ ++static void ++init_skyeye_ops (void) ++{ ++ skyeye_ops.to_shortname = "skyeye"; ++ skyeye_ops.to_longname = "SKYEYE"; ++ skyeye_ops.to_doc = "Use the compiled-in SKYEYE simulator"; ++ skyeye_ops.to_open = skyeye_open; ++ skyeye_ops.to_close = skyeye_close; ++ skyeye_ops.to_load = generic_load; ++ skyeye_ops.to_resume = skyeye_resume; ++ skyeye_ops.to_wait = skyeye_wait; ++ skyeye_ops.to_stop = skyeye_stop; ++ skyeye_ops.to_kill = skyeye_kill; ++ skyeye_ops.to_create_inferior = skyeye_create_inferior; ++ skyeye_ops.to_mourn_inferior = skyeye_mourn_inferior; ++ skyeye_ops.to_prepare_to_store = skyeye_prepare_to_store; ++ skyeye_ops.to_fetch_registers = skyeye_fetch_registers; ++ skyeye_ops.to_store_registers = skyeye_store_registers; ++ skyeye_ops.to_insert_breakpoint = skyeye_insert_breakpoint; ++ skyeye_ops.to_remove_breakpoint = skyeye_remove_breakpoint; ++ skyeye_ops.deprecated_xfer_memory = skyeye_xfer_memory; ++ skyeye_ops.to_stratum = process_stratum; ++ skyeye_ops.to_has_all_memory = 1; ++ skyeye_ops.to_has_memory = 1; ++ skyeye_ops.to_has_stack = 1; ++ skyeye_ops.to_has_registers = 1; ++ skyeye_ops.to_has_execution = 1; ++ skyeye_ops.to_has_thread_control = tc_none; ++ skyeye_ops.to_magic = OPS_MAGIC; ++#if 0 ++ skyeye_ops.to_attach = skyeye_attach; ++ skyeye_ops.to_detach = skyeye_detach; ++ skyeye_ops.to_disconnect = skyeye_disconnect; ++ //skyeye_ops.to_xfer_partial = skyeye_xfer_partial; ++ skyeye_ops.to_can_use_hw_breakpoint = skyeye_check_watch_resources; ++ skyeye_ops.to_insert_hw_breakpoint = skyeye_insert_hw_breakpoint; ++ skyeye_ops.to_remove_hw_breakpoint = skyeye_remove_hw_breakpoint; ++#endif ++} ++ ++void ++_initialize_skyeye (void) ++{ ++ if (sigfillset (&skyeye_maskall) == -1) { ++ error ("SKYEYE: init sigal."); ++ } ++ ++ global_argv = (char **)org_global_argv; ++ skyeye_ice.num_bps = 0; ++ ++ init_skyeye_ops (); ++ add_target (&skyeye_ops); ++} ++ +diff -ruNa --exclude=CVS gdb-6.4-old/Makefile.in gdb-6.4/Makefile.in +--- gdb-6.4-old/Makefile.in 2005-12-02 13:29:54.000000000 +0800 ++++ gdb-6.4/Makefile.in 2007-02-01 17:42:53.000000000 +0800 +@@ -903,6 +903,7 @@ + maybe-all-build-texinfo \ + maybe-all-build-fixincludes + .PHONY: all-host ++#teawater SKYEYE go back to GDB 2006.09.30 begin-------------------------------- + all-host: \ + maybe-all-ash \ + maybe-all-autoconf \ +@@ -955,6 +956,7 @@ + maybe-all-send-pr \ + maybe-all-shellutils \ + maybe-all-sid \ ++ maybe-all-skyeye \ + maybe-all-sim \ + maybe-all-tar \ + maybe-all-texinfo \ +@@ -971,6 +973,7 @@ + maybe-all-libtermcap \ + maybe-all-utils \ + maybe-all-gnattools ++#teawater SKYEYE go back to GDB 2006.09.30 end---------------------------------- + .PHONY: all-target + all-target: \ + maybe-all-target-libstdc++-v3 \ +@@ -1723,6 +1726,7 @@ + + + .PHONY: clean-host ++#teawater SKYEYE go back to GDB 2006.09.30 begin-------------------------------- + clean-host: \ + maybe-clean-ash \ + maybe-clean-autoconf \ +@@ -1775,6 +1779,7 @@ + maybe-clean-send-pr \ + maybe-clean-shellutils \ + maybe-clean-sid \ ++ maybe-clean-skyeye \ + maybe-clean-sim \ + maybe-clean-tar \ + maybe-clean-texinfo \ +@@ -1791,6 +1796,7 @@ + maybe-clean-libtermcap \ + maybe-clean-utils \ + maybe-clean-gnattools ++#teawater SKYEYE go back to GDB 2006.09.30 begin-------------------------------- + + .PHONY: clean-target + clean-target: \ +@@ -22801,6 +22807,36 @@ + + + ++#teawater SKYEYE go back to GDB 2006.09.30 begin-------------------------------- ++.PHONY: all-skyeye maybe-all-skyeye ++maybe-all-skyeye: ++@if skyeye ++TARGET-skyeye=all ++maybe-all-skyeye: all-skyeye ++all-skyeye: $(HOST_SUBDIR)/skyeye/libskyeye.a ++ ++$(HOST_SUBDIR)/skyeye/libskyeye.a: $(srcdir)/skyeye-v1/binary/libskyeye.a ++ mkdir -p $(HOST_SUBDIR)/skyeye ++ cp -f $(srcdir)/skyeye-v1/binary/libskyeye.a $(HOST_SUBDIR)/skyeye/libskyeye.a ++ ++$(srcdir)/skyeye-v1/binary/libskyeye.a: ++ cd $(srcdir)/skyeye-v1 ; make libskyeye ++@endif skyeye ++ ++ ++ ++.PHONY: maybe-clean-skyeye clean-skyeye ++maybe-clean-skyeye: ++@if skyeye ++maybe-clean-skyeye: clean-skyeye ++ ++clean-skyeye: ++ cd $(HOST_SUBDIR)/skyeye-v1 ; make clean ++@endif skyeye ++#teawater SKYEYE go back to GDB 2006.09.30 end---------------------------------- ++ ++ ++ + .PHONY: configure-sim maybe-configure-sim + maybe-configure-sim: + @if sim diff -Nur skyeye-v1_Rel/Makefile skyeye-v1_gdb/Makefile --- skyeye-v1_Rel/Makefile 2006-12-16 12:12:09.000000000 -0500 +++ skyeye-v1_gdb/Makefile 2007-02-01 04:45:02.000000000 -0500 @@ -233,6 +233,13 @@ LIB_OBJS = $(SIM_OBJS) +#teawater SKYEYE go back to GDB 2007.01.22 begin-------------------------------- +SIM_CF_OBJS = binary/cf_arch_interface.o +CF_PATH = arch/coldfire/ +CF_COMMON_PATH = arch/coldfire/common/ +COLDFIRE_FLAG = -I arch/coldire/tracer +#teawater SKYEYE go back to GDB 2007.01.22 end---------------------------------- + all: binary/skyeye clean: $(SIM_EXTRA_CLEAN) rm -f binary/*.o @@ -240,6 +247,29 @@ rm -f binary/skyeye make -C arch/coldfire clean +#teawater SKYEYE go back to GDB 2007.01.22 begin-------------------------------- +#LIBSKYEYE_SIM_UTILS_OBJS = binary/arch_reg.o binary/skyeye_config.o binary/skyeye_options.o binary/skyeye_stub_win32.o binary/skyeye_arch.o +LIBSKYEYE_SIM_UTILS_OBJS = binary/skyeye2gdb.o binary/gdbserver.o binary/arch_regdefs.o binary/arm_regdefs.o binary/cf_regdefs.o binary/bfin_regdefs.o binary/skyeye_config.o binary/skyeye_options.o binary/skyeye_arch.o +ifeq ($(OSTYPE),msys) +LIBSKYEYE_SIM_UTILS_OBJS += binary/skyeye_win32_stdio.o +else +ifeq ($(TERM),cygwin) +LIBSKYEYE_SIM_UTILS_OBJS += binary/skyeye_stub_win32.o +endif +endif + +libskyeye: binary/libskyeye.a + +#binary/libarm.a binary/libmips.a binary/libbfin.a binary/libdev.a binary/libutils.a binary/libcoldfire.a +binary/libskyeye.a: binary/libarm.a binary/libmips.a binary/libbfin.a binary/libdev.a binary/libutils.a binary/libcoldfire.a $(SIM_ARM) $(SIM_BFIN_OBJS) $(SIM_DEV_OBJS) $(LIBSKYEYE_SIM_UTILS_OBJS) $(SIM_CF_OBJS) $(SIM_CF_OBJS) $(CF_PATH)/tracer/tracer.o $(CF_PATH)/i_5206/i.o + $(AR) $(AR_FLAGS) binary/libskyeye.a $(SIM_ARM) $(SIM_MIPS) $(SIM_BFIN_OBJS) $(SIM_DEV_OBJS) $(LIBSKYEYE_SIM_UTILS_OBJS) $(SIM_CF_OBJS) $(CF_COMMON_PATH)/*.o $(CF_PATH)/tracer/tracer.o $(CF_PATH)/i_5206/i.o + $(RANLIB) binary/libskyeye.a + + +patchgdb6.4: + cd ../..; patch -p0 < gdb-6.4/skyeye-v1/gdb642skyeye.patch +#teawater SKYEYE go back to GDB 2007.01.22 end---------------------------------- + distclean mostlyclean maintainer-clean realclean: clean rm -f TAGS tags rm -f binary/skyeye binary/*.o binary/*.a @@ -271,10 +301,12 @@ $(RANLIB) binary/libbfin.a #generate lib for coldfire architecture -SIM_CF_OBJS = binary/cf_arch_interface.o -CF_PATH = arch/coldfire/ -CF_COMMON_PATH = arch/coldfire/common/ -COLDFIRE_FLAG = -I arch/coldire/tracer +#teawater SKYEYE go back to GDB 2007.01.22 begin-------------------------------- +#SIM_CF_OBJS = binary/cf_arch_interface.o +#CF_PATH = arch/coldfire/ +#CF_COMMON_PATH = arch/coldfire/common/ +#COLDFIRE_FLAG = -I arch/coldire/tracer +#teawater SKYEYE go back to GDB 2007.01.22 end---------------------------------- binary/libcoldfire.a:$(SIM_CF_OBJS) make -C arch/coldfire $(AR) $(AR_FLAGS) binary/libcoldfire.a $(SIM_CF_OBJS) $(CF_COMMON_PATH)/*.o $(CF_PATH)/tracer/tracer.o $(CF_PATH)/i_5206/i.o diff -Nur skyeye-v1_Rel/utils/debugger/gdbserver.c skyeye-v1_gdb/utils/debugger/gdbserver.c --- skyeye-v1_Rel/utils/debugger/gdbserver.c 2006-12-16 11:35:35.000000000 -0500 +++ skyeye-v1_gdb/utils/debugger/gdbserver.c 2007-02-01 04:45:02.000000000 -0500 @@ -486,6 +486,8 @@ convert_ascii_to_int (&from[i++], to, *len_ptr); } +//teawater SKYEYE go back to GDB 2007.01.24 begin------------------------------- +#if 0 static void fetch_inferior_registers (int regno, unsigned char *memory) { @@ -507,6 +509,9 @@ else current_reg_type->store_register (regno, &(memory[current_reg_type->register_byte (regno)])); } +#endif +//teawater SKYEYE go back to GDB 2007.01.24 end--------------------------------- + int sim_debug () { @@ -579,15 +584,31 @@ break; #endif //chy 2005-07-30 case 'g': - fetch_inferior_registers (0, registers); - convert_int_to_ascii (registers, own_buf, - current_reg_type->register_bytes); +//teawater SKYEYE go back to GDB 2007.01.24 begin------------------------------- + if (sim_fetch_inferior_registers (-1, registers)) { + write_enn (own_buf); + } + else { + convert_int_to_ascii (registers, own_buf, current_reg_type->register_bytes); + } + //fetch_inferior_registers (0, registers); + //convert_int_to_ascii (registers, own_buf, + // current_reg_type->register_bytes); +//teawater SKYEYE go back to GDB 2007.01.24 end--------------------------------- break; case 'G': convert_ascii_to_int (&own_buf[1], registers, current_reg_type->register_bytes); - store_inferior_registers (-1, registers); - write_ok (own_buf); +//teawater SKYEYE go back to GDB 2007.01.24 begin------------------------------- + if (sim_store_inferior_registers (-1, registers)) { + write_enn (own_buf); + } + else { + write_ok (own_buf); + } +// store_inferior_registers (-1, registers); +// write_ok (own_buf); +//teawater SKYEYE go back to GDB 2007.01.24 end--------------------------------- break; case 'm': decode_m_packet (&own_buf[1], &mem_addr, diff -Nur skyeye-v1_Rel/utils/debugger/skyeye2gdb.c skyeye-v1_gdb/utils/debugger/skyeye2gdb.c --- skyeye-v1_Rel/utils/debugger/skyeye2gdb.c 2006-12-16 11:35:35.000000000 -0500 +++ skyeye-v1_gdb/utils/debugger/skyeye2gdb.c 2007-02-01 04:45:02.000000000 -0500 @@ -137,6 +137,58 @@ return size; } +//teawater SKYEYE go back to GDB 2007.01.24 begin------------------------------- +extern register_defs_t *current_reg_type; + +int +sim_fetch_inferior_registers (int regno, unsigned char *memory) +{ + if (regno < 0) { + for (regno = 0; regno < current_reg_type->num_regs; regno++) { + if (sim_fetch_inferior_registers (regno, &(memory[current_reg_type->register_byte (regno)]))) { + return (-1); + } + } + } + else { + if (current_reg_type->fetch_register) { + if (current_reg_type->fetch_register (regno, memory)) { + return (-1); + } + } + else { + return (-1); + } + } + + return (0); +} + +int +sim_store_inferior_registers (int regno, unsigned char *memory) +{ + if (regno < 0) { + for (regno = 0; regno < current_reg_type->num_regs; regno++) { + if (sim_store_inferior_registers (regno, &(memory[current_reg_type->register_byte (regno)]))) { + return (-1); + } + } + } + else { + if (current_reg_type->fetch_register) { + if (current_reg_type->store_register (regno, memory)) { + return (-1); + } + } + else { + return (-1); + } + } + + return (0); +} +//teawater SKYEYE go back to GDB 2007.01.24 end--------------------------------- + void gdbserver_cont(){ if(!strcmp(skyeye_config.arch->arch_name,"arm")){ //chy 2006-04-12 skyeye-1.2.5_REL/misc/gdb/README0000644000175000001440000000146010576117535014620 0ustar kshusers README for gdb with SkyEye (teawater@gmail.com) You can compile gdb-6.4 with skyeye-1.2 by the following command: tar vxjf gdb-6.4.tar.bz2 tar xjvf skyeye-v1.2_Rel.tar.bz2 cd SKYEYE_SOURCE_DIR cat SKYEYE_SOURCE_DIR/misc/gdb/skyeye_1.2_for_gdb_6.4.diff|patch -p1 cd.. cp SKYEYE_SOURCE_DIR gdb-6.4/ cd gdb-6.4 tar vxjf skyeye-v1.2_Rel_gdb.tar.bz2 cd skyeye-v1 make patchgdb6.4 cd .. ./configure --target=arm-elf make make install Then run it by the following command: gdbskyeye image_name (gdb)target skyeye (gdb)load (gdb)run skyeye-1.2.5_REL/misc/linux_driver/0000755000175000001440000000000011023514411015673 5ustar kshusersskyeye-1.2.5_REL/misc/linux_driver/rtl8019/0000755000175000001440000000000011023514411017016 5ustar kshusersskyeye-1.2.5_REL/misc/linux_driver/rtl8019/rtl8019.c0000644000175000001440000002477210665426153020341 0ustar kshusers/* * port to 16bit/8bit remote dma mode lq@cdgwbn.com.cn * linux/deriver/net/Rtl8019as.c * Ethernet driver for Samsung 44B0 * Copyright (C) 2003 antiscle * * Modified by Skyeye Develop Group 2007 * */ #include #include #include #include #include // kmalloc() #include // error codes #include // size_t #include // mark_bh #include #include // net_device #include #include #include #include #include #include #include "rtl8019.h" #undef DEBUG //#define DEBUG 1 #ifdef DEBUG #define TRACE(str, args...) printk(str, ## args) #else #define TRACE(str, args...) #endif #define outportb(port, data) *((volatile u8 *)(port)) = (u8)(data) #define inportb(port) *((volatile u8 *)(port)) #define outportw(port, data) *((volatile u16 *)(port)) = (u16)(data) #define inportw(port) *((volatile u16 *)(port)) #define ETH_FRAME_LEN 1514 #define RPSTART 0x4c #define RPSTOP 0x80 #define SPSTART 0x40 static int timeout = 100; // tx watchdog ticks 100 = 1s static char *version = "Samsung S3C44B0 Rtl8019as driver version 0.1 (2002-02-20) \n"; /* * This structure is private to each device. It is used to pass * packets in and out, so there is place for a packet */ struct nic_8019_priv { struct net_device_stats stats; spinlock_t lock; struct sk_buff *skb; }; /*****************************************************************************/ static u8 rBNRY; static u8 SrcMacID[ETH_ALEN] = {0x12,0x34,0x56,0x78,0x90,0xAB,}; static void SetRegPage( u8 PageIdx) { u8 temp; temp = inportb(BaseAddr); temp = (temp&0x3b)|(PageIdx<<6); outportb(BaseAddr, temp); } irqreturn_t nic_8019_rx(int irq, void *dev_id, struct pt_regs *regs) { u8 RxPageBeg, RxPageEnd; u8 RxNextPage; u8 RxStatus; #ifdef RTL8019_OP_16 u16 *data,temp; #else u8 *data; #endif u16 i, RxLength,RxLen; struct sk_buff *skb; struct net_device *dev = (struct net_device *) dev_id; struct nic_8019_priv *priv = (struct nic_8019_priv *) dev->priv; TRACE("TX/RX Interupt!\n"); spin_lock(&priv->lock); SetRegPage(0); outportb(BNRY, rBNRY); //??? RxStatus = inportb(ISR); if (RxStatus & 2) { outportb(ISR, 0x2); //clr TX interupt priv->stats.tx_packets++; TRACE("transmit one packet complete!\n"); } if (RxStatus & 1) { readpacket: TRACE("Receivex packet....\n"); outportb(ISR, 0x1); //clr Rx interupt SetRegPage(1); RxPageEnd = inportb(CURR); SetRegPage(0); RxPageBeg = rBNRY+1; if(RxPageBeg>=RPSTOP) RxPageBeg = RPSTART; outportb(BaseAddr, 0x22); // stop remote dma //outport(RSAR0, RxPageBeg<<8); //outport(RBCR0, 256); outportb(RSAR0, 0); outportb(RSAR1, RxPageBeg); outportb(RBCR0, 4); outportb(RBCR1, 0); outportb(BaseAddr, 0xa); #ifdef RTL8019_OP_16 temp = inportw(RWPORT); RxNextPage = temp>>8; RxStatus = temp&0xff; RxLength = inportw(RWPORT); #else RxStatus = inportb(RWPORT); RxNextPage = inportb(RWPORT); RxLength = inportb(RWPORT); RxLength |= inportb(RWPORT)<<8; #endif TRACE("\nRxBeg = %x, RxEnd = %x, nextpage = %x, size = %i\n", RxPageBeg, RxPageEnd, RxNextPage, RxLength); RxLength -= 4; if (RxLength>ETH_FRAME_LEN) { if (RxPageEnd==RPSTART) rBNRY = RPSTOP-1; else rBNRY = RxPageEnd-1; outportb(BNRY, rBNRY); TRACE("RxLength more long than %x\n", ETH_FRAME_LEN); return IRQ_HANDLED; } skb = dev_alloc_skb(RxLength+2); if (!skb) { TRACE("Rtl8019as eth: low on mem - packet dropped\n"); priv->stats.rx_dropped++; return IRQ_HANDLED; } skb->dev = dev; skb_reserve(skb, 2); skb_put(skb, RxLength); #ifdef RTL8019_OP_16 data = ( u16 *)skb->data; #else data = ( u8 *)skb->data; #endif // eth_copy_and_sum(skb, data, len, 0); outportb(RSAR0, 4); outportb(RSAR1, RxPageBeg); outportb(RBCR0, RxLength); outportb(RBCR1, RxLength>>8); outportb(BaseAddr, 0xa); #ifdef RTL8019_OP_16 i = 2; data -= 2; RxLen=(RxLength+1)/2; #else i = 4; data -= 4; RxLen=RxLength; #endif for(; RxLen--;) { #ifdef RTL8019_OP_16 static const int cmp_val = 0x7f; #else static const int cmp_val = 0xff; #endif if (!(i & cmp_val)) { outportb(BNRY, RxPageBeg); RxPageBeg++; if(RxPageBeg>=RPSTOP) RxPageBeg = RPSTART; } #ifdef RTL8019_OP_16 data[i++] = inportw(RWPORT); TRACE("%2X,%2X,", data[i-1]&0xff,data[i-1]>>8); #else data[i++] = inportb(RWPORT); TRACE("%2X,", data[i-1]); #endif } TRACE("\n"); outportb(BNRY, RxPageBeg); rBNRY = RxPageBeg; skb->protocol = eth_type_trans(skb, dev); TRACE("\nprotocol=%x\n", skb->protocol); priv->stats.rx_packets++; priv->stats.rx_bytes +=RxLength; netif_rx(skb); /* Process all unread data */ if (RxPageEnd != RxNextPage) goto readpacket; } else { outportb(ISR, 0xfe); } spin_unlock(&priv->lock); return IRQ_HANDLED; } /* * Open and Close */ static int nic_8019_open(struct net_device *dev) { int i,j; MOD_INC_USE_COUNT; TRACE("open\n"); // Disable irqs disable_irq(dev->irq); // register rx isr if (request_irq(dev->irq, &nic_8019_rx, SA_INTERRUPT, "eth rx isr", dev)) { printk(KERN_ERR "Rtl8019: Can't get irq %d\n", dev->irq); return -EAGAIN; } // wake up Rtl8019as SetRegPage(3); outportb(CR9346, 0xcf); //set eem1-0, 11 ,enable write config register outportb(CONFIG3, 0x60); //clear pwrdn, sleep mode, set led0 as led_col, led1 as led_crs outportb(CR9346, 0x3f); //disable write config register // initialize outportb(RstAddr, 0x5a); i = 20000; while(i--); SetRegPage(0); inportb(ISR); outportb(BaseAddr, 0x21); /* set page 0 and stop */ outportb(Pstart, RPSTART); /* set Pstart 0x4c */ outportb(Pstop, RPSTOP); /* set Pstop 0x80 */ outportb(BNRY, RPSTART); /* BNRY-> the last page has been read */ outportb(TPSR, SPSTART); /* SPSTART page start register, 0x40 */ outportb(RCR, 0xcc); /* set RCR 0xcc */ outportb(TCR, 0xe0); /* set TCR 0xe0 */ #ifdef RTL8019_OP_16 outportb(DCR, 0xc9); /* set DCR 0xc9, 16bit DMA */ #else outportb(DCR, 0xc8); /* set DCR 0xc8, 8bit DMA */ #endif outportb(IMR, 0x03); /* set IMR 0x03, enable tx rx int */ outportb(ISR, 0xff); /* clear ISR */ SetRegPage(1); for(i=0; i<6; i++) outportb(BaseAddr+(1+i)*2, dev->dev_addr[i]); // set mac id outportb(CURR, RPSTART+1); outportb(MAR0, 0x00); outportb(MAR1, 0x41); outportb(MAR2, 0x00); outportb(MAR3, 0x80); outportb(MAR4, 0x00); outportb(MAR5, 0x00); outportb(MAR6, 0x00); outportb(MAR7, 0x00); outportb(BaseAddr, 0x22); /* set page 0 and start */ rBNRY = RPSTART; enable_irq(dev->irq); // Start the transmit queue netif_start_queue(dev); return 0; } static int nic_8019_stop(struct net_device *dev) { TRACE("stop\n"); SetRegPage(3); outportb(CR9346, 0xcf); // set eem1-0, 11 ,enable write config register outportb(CONFIG3, 0x66); // enter pwrdn, sleep mode, set led0 as led_col, led1 as led_crs outportb(CR9346, 0x3f); // disable write config register free_irq(dev->irq, dev); netif_stop_queue(dev); MOD_DEC_USE_COUNT; return 0; } static int nic_8019_start_xmit(struct sk_buff *skb, struct net_device *dev) { int i; u16 len,TxLen; #ifdef RTL8019_OP_16 u16 *data; #else u8 *data; #endif struct nic_8019_priv *priv = (struct nic_8019_priv *) dev->priv; TRACE("start_xmit\n"); len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; TRACE("\nTx Length = %i,%x,%x\n", len, skb->data[12], skb->data[13]); #ifdef RTL8019_OP_16 data =(u16*) skb->data; #else data =(u8*) skb->data; #endif outportb(BaseAddr,0x22); //switch to page 0 and stop remote dma if (inportb(BaseAddr)&4) // last remote dma not complete,return 1 echo busy(error),retransmit next return 1; #ifdef bug_fix_for_write //read page 42,0,42,0 before write if you have problem #endif outportb(RSAR0, 0); outportb(RSAR1, SPSTART); outportb(RBCR0, len&0xff); outportb(RBCR1, len>>8); outportb(BaseAddr, 0x12); //begin remote write dev->trans_start = jiffies; #ifdef RTL8019_OP_16 TxLen=(len+1)/2; #else TxLen=len; #endif for(i=0; i>8); #else outportb(RWPORT, data[i]); // copy data to nic ram TRACE("%2X,",skb->data[i]); #endif } TRACE("\n"); outportb(TPSR, SPSTART); // transmit begin page 0x40 outportb(TBCR0, len&0xff); outportb(TBCR1, len>>8); outportb(BaseAddr, 0x1e); // begin to send packet dev_kfree_skb(skb); return 0; } static struct net_device_stats *nic_8019_get_stats(struct net_device *dev) { struct nic_8019_priv *priv = (struct nic_8019_priv *) dev->priv; TRACE("get_stats\n"); return &priv->stats; } /******************************************************************************/ static int nic_8019_init(struct net_device *dev) { int i; TRACE("init\n"); ether_setup(dev); // Assign some of the fields // set net_device methods dev->open = nic_8019_open; dev->stop = nic_8019_stop; dev->get_stats = nic_8019_get_stats; dev->hard_start_xmit = nic_8019_start_xmit; // set net_device data members dev->watchdog_timeo = timeout; dev->irq = IRQ_NUM; dev->dma = 0; // set MAC address manually printk(KERN_INFO "%s: ", dev->name); for(i=0; i<6; i++) { dev->dev_addr[i] = SrcMacID[i]; printk("%2.2x%c", dev->dev_addr[i], (i==5) ? ' ' : ':'); } printk("\n"); SET_MODULE_OWNER(dev); dev->priv = kmalloc(sizeof(struct nic_8019_priv), GFP_KERNEL); if(dev->priv == NULL) return -ENOMEM; memset(dev->priv, 0, sizeof(struct nic_8019_priv)); spin_lock_init(&((struct nic_8019_priv *) dev->priv)->lock); return 0; } static struct net_device nic_8019_netdevs = { init: nic_8019_init, }; /* * Finally, the module stuff */ int __init nic_8019_init_module(void) { int result; TRACE("init_module\n"); //Print version information printk(KERN_INFO "%s", version); //register_netdev will call nic_8019_init() if((result = register_netdev(&nic_8019_netdevs))) printk("Rtl8019as eth: Error %i registering device \"%s\"\n", result, nic_8019_netdevs.name); return result ? 0 : -ENODEV; } void __exit nic_8019_cleanup(void) { TRACE("cleanup\n"); kfree(nic_8019_netdevs.priv); unregister_netdev(&nic_8019_netdevs); return; } module_init(nic_8019_init_module); module_exit(nic_8019_cleanup); MODULE_DESCRIPTION("Rtl8019as ethernet driver"); MODULE_AUTHOR("antiscle "); MODULE_LICENSE("GPL"); skyeye-1.2.5_REL/misc/linux_driver/rtl8019/README0000644000175000001440000000015210664204362017707 0ustar kshusersThe patch is tested on linux-2.4.x source tree of uClinux-dist-2000408 and uClinux-dist-20070130 version. skyeye-1.2.5_REL/misc/linux_driver/rtl8019/rtl8019.h0000644000175000001440000000506710665426153020342 0ustar kshusers#ifndef __RTL8019_H__ #define __RTL8019_H__ #ifdef CONFIG_RTL8019_OP_8_EXTRA #define RTL8019_OP_8_EXTRA #elif defined(CONFIG_RTL8019_OP_8) #define RTL8019_OP_8 #else #define RTL8019_OP_16 #endif #ifdef RTL8019_OP_16 #define SHIFT(x) (x<<1) #elif defined(RTL8019_OP_8_EXTRA) #define SHIFT(x) (x<<8) #else /* RTL8019_OP_8 */ #define SHIFT(x) (x) #endif #ifdef CONFIG_ARCH_S3C44B0X #ifdef RTL8019_OP_16 #define BaseAddr 0x6000000 #elif defined(RTL8019_OP_8_EXTRA) #define BaseAddr 0x3000000 #else /* RTL8019_OP_8 */ #define BaseAddr 0x8000000 #endif #define IRQ_NUM 22 #else /* for AT91 or others */ #define BaseAddr 0xfffa0000 #define IRQ_NUM 16 #endif #ifdef CONFIG_RTL8019_BASE_ADDRESS #undef BaseAddr #define BaseAddr CONFIG_RTL8019_BASE_ADDRESS #endif #ifdef CONFIG_RTL8019_IRQ #undef IRQ_NUM #define IRQ_NUM CONFIG_RTL8019_IRQ #endif #define RWPORT (BaseAddr+SHIFT(0x10)) /* dma read write address, form 0x10 - 0x17 */ #define RstAddr (BaseAddr+SHIFT(0x18)) /* reset register, 0x18, 0x1a, 0x1c, 0x1e even address is recommanded */ /* page 0 */ #define Pstart (BaseAddr+SHIFT(1)) /* page start */ #define Pstop (BaseAddr+SHIFT(2)) /* page stop */ #define BNRY (BaseAddr+SHIFT(3)) #define TPSR (BaseAddr+SHIFT(4)) /* transmit page start */ #define TBCR0 (BaseAddr+SHIFT(5)) #define TBCR1 (BaseAddr+SHIFT(6)) #define ISR (BaseAddr+SHIFT(7)) /* interrupt status register */ #define RSAR0 (BaseAddr+SHIFT(8)) /* dma read address */ #define RSAR1 (BaseAddr+SHIFT(9)) #define RBCR0 (BaseAddr+SHIFT(10)) /* dma read byte count */ #define RBCR1 (BaseAddr+SHIFT(11)) #define RCR (BaseAddr+SHIFT(12)) /* receive config */ #define TCR (BaseAddr+SHIFT(13)) /* transmit config */ #define DCR (BaseAddr+SHIFT(14)) /* data config */ #define IMR (BaseAddr+SHIFT(15)) /* interrupt mask */ #define ID8019L (BaseAddr+SHIFT(10)) #define ID8019H (BaseAddr+SHIFT(11)) /* page 1 */ #define PAR0 (BaseAddr+SHIFT(1)) #define PAR1 (BaseAddr+SHIFT(2)) #define PAR2 (BaseAddr+SHIFT(3)) #define PAR3 (BaseAddr+SHIFT(4)) #define PAR4 (BaseAddr+SHIFT(5)) #define PAR6 (BaseAddr+SHIFT(6)) #define CURR (BaseAddr+SHIFT(7)) #define MAR0 (BaseAddr+SHIFT(8)) #define MAR1 (BaseAddr+SHIFT(9)) #define MAR2 (BaseAddr+SHIFT(10)) #define MAR3 (BaseAddr+SHIFT(11)) #define MAR4 (BaseAddr+SHIFT(12)) #define MAR5 (BaseAddr+SHIFT(13)) #define MAR6 (BaseAddr+SHIFT(14)) #define MAR7 (BaseAddr+SHIFT(15)) /* page 2 */ /* page 3 */ #define CR9346 (BaseAddr+SHIFT(1)) #define CONFIG0 (BaseAddr+SHIFT(3)) #define CONFIG1 (BaseAddr+SHIFT(4)) #define CONFIG2 (BaseAddr+SHIFT(5)) #define CONFIG3 (BaseAddr+SHIFT(6)) #endif skyeye-1.2.5_REL/misc/linux_driver/cs8900a/0000755000175000001440000000000011023514411016762 5ustar kshusersskyeye-1.2.5_REL/misc/linux_driver/cs8900a/linux_2_6_14_cs8900.diff0000644000175000001440000010152111006364735022750 0ustar kshusersdiff -Nur linux-2.6.14/arch/arm/mach-s3c2410/mach-smdk2410.c linux-2.6.14_cs8900/arch/arm/mach-s3c2410/mach-smdk2410.c --- linux-2.6.14/arch/arm/mach-s3c2410/mach-smdk2410.c 2005-10-28 08:02:08.000000000 +0800 +++ linux-2.6.14_cs8900/arch/arm/mach-s3c2410/mach-smdk2410.c 2008-02-03 23:08:55.000000000 +0800 @@ -52,9 +52,12 @@ #include "devs.h" #include "cpu.h" +#include static struct map_desc smdk2410_iodesc[] __initdata = { /* nothing here yet */ + /* Map the ethernet controller CS8900A */ +{vSMDK2410_ETH_IO,pSMDK2410_ETH_IO, SZ_1M, MT_DEVICE} }; #define UCON S3C2410_UCON_DEFAULT diff -Nur linux-2.6.14/drivers/net/arm/cs8900.c linux-2.6.14_cs8900/drivers/net/arm/cs8900.c --- linux-2.6.14/drivers/net/arm/cs8900.c 1970-01-01 08:00:00.000000000 +0800 +++ linux-2.6.14_cs8900/drivers/net/arm/cs8900.c 2008-02-03 23:15:49.000000000 +0800 @@ -0,0 +1,923 @@ + +/* + * linux/drivers/net/cs8900.c + * + * Author: Abraham van der Merwe + * + * A Cirrus Logic CS8900A driver for Linux + * based on the cs89x0 driver written by Russell Nelson, + * Donald Becker, and others. + * + * This source code is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * History: + * 22-May-2002 Initial version (Abraham vd Merwe) + * 30-May-2002 Added char device support for eeprom (Frank Becker) + * 24-Jan-2004 Fixups for 2.6 (Frank Becker) + * 15-July-2004 Modified for SMDK2410 (Roc Wu pwu at jadechip.com) + */ + +#define VERSION_STRING "Cirrus Logic CS8900A driver for Linux (Modified for SMDK2410)" + +/* + * At the moment the driver does not support memory mode operation. + * It is trivial to implement this, but not worth the effort. + */ + +/* + * TODO: + * + * 1. Sort out ethernet checksum + * 2. If !ready in send_start(), queue buffer and send it in interrupt handler + * when we receive a BufEvent with Rdy4Tx, send it again. dangerous! + * 3. how do we prevent interrupt handler destroying integrity of get_stats()? + * 4. Change reset code to check status. + * 5. Implement set_mac_address and remove fake mac address + * 7. Link status detection stuff + * 8. Write utility to write EEPROM, do self testing, etc. + * 9. Implement DMA routines (I need a board w/ DMA support for that) + * 10. Power management + * 11. Add support for multiple ethernet chips + */ + +// added BSt +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// Added BSt +#include + +#ifdef CONFIG_SA1100_CERF +#include "asm/arch/cerf.h" +#endif + +#ifdef CONFIG_ARCH_SMDK2410 +#include "asm/arch-s3c2410/smdk2410.h" +#endif + +#include "cs8900.h" + +//#define FULL_DUPLEX +//#define DEBUG + +typedef struct { + struct net_device_stats stats; + u16 txlen; + int char_devnum; + + spinlock_t lock; +} cs8900_t; + +int cs8900_probe (struct net_device *dev); +static struct net_device cs8900_dev = +{ + init: cs8900_probe +}; + +/* + * There seems to be no way to determine the exact size of the eeprom, + * so we use the largest size. + * FIXME: Verify it's safe to read/write past the end of a 64/128 + * byte eeprom. + * + * Possible eeprom sizes: + * Cx46 - 64 bytes + * Cx56 - 128 bytes + * Cx66 - 256 bytes + */ +#define MAX_EEPROM_SIZE 256 + +static int cs8900_eeprom_fopen(struct inode *inode, struct file *file); +static int cs8900_eeprom_frelease(struct inode *inode, struct file *file); +static loff_t cs8900_eeprom_fllseek(struct file * file,loff_t offset, int flags); +static ssize_t cs8900_eeprom_fread(struct file *file, char *buf, size_t count, loff_t *f_pos); +static ssize_t cs8900_eeprom_fwrite(struct file *file, const char *buf, size_t count, loff_t *f_pos); +static struct file_operations cs8900_eeprom_fops = { + owner: THIS_MODULE, + open: cs8900_eeprom_fopen, + release: cs8900_eeprom_frelease, + llseek: cs8900_eeprom_fllseek, + read: cs8900_eeprom_fread, + write: cs8900_eeprom_fwrite, +}; + +static u16 cs8900_eeprom_cache[MAX_EEPROM_SIZE/2]; + +/* + * I/O routines + */ + +static inline u16 cs8900_read (struct net_device *dev,u16 reg) +{ + outw (reg,dev->base_addr + PP_Address); + return (inw (dev->base_addr + PP_Data)); +} + +static inline void cs8900_write (struct net_device *dev,u16 reg,u16 value) +{ + outw (reg,dev->base_addr + PP_Address); + outw (value,dev->base_addr + PP_Data); +} + +static inline void cs8900_set (struct net_device *dev,u16 reg,u16 value) +{ + cs8900_write (dev,reg,cs8900_read (dev,reg) | value); +} + +static inline void cs8900_clear (struct net_device *dev,u16 reg,u16 value) +{ + cs8900_write (dev,reg,cs8900_read (dev,reg) & ~value); +} + +static inline void cs8900_frame_read (struct net_device *dev,struct sk_buff *skb,u16 length) +{ + insw (dev->base_addr,skb_put (skb,length),(length + 1) / 2); +} + +static inline void cs8900_frame_write (struct net_device *dev,struct sk_buff *skb) +{ + outsw (dev->base_addr,skb->data,(skb->len + 1) / 2); +} + +/* + * EEPROM I/O routines + */ + +static int cs8900_eeprom_wait (struct net_device *dev) +{ + int i; + + for (i = 0; i < 3000; i++) { + if (!(cs8900_read (dev,PP_SelfST) & SIBUSY)) + return (0); + udelay (1); + } + + return (-1); +} + +static int cs8900_eeprom_read (struct net_device *dev,u16 *value,u16 offset) +{ + if (cs8900_eeprom_wait (dev) < 0) + return (-1); + + cs8900_write (dev,PP_EEPROMCommand,offset | EEReadRegister); + + if (cs8900_eeprom_wait (dev) < 0) + return (-1); + + *value = cs8900_read (dev,PP_EEPROMData); + + return (0); +} + +static int cs8900_eeprom_write (struct net_device *dev,u16 *value,u16 offset) +{ + cs8900_eeprom_wait(dev); + cs8900_write(dev, PP_EEPROMCommand, (EEWriteEnable)); + cs8900_eeprom_wait(dev); + cs8900_write(dev, PP_EEPROMData, *value); + cs8900_eeprom_wait(dev); + cs8900_write(dev, PP_EEPROMCommand, (offset | EEWriteRegister)); + cs8900_eeprom_wait(dev); + cs8900_write(dev, PP_EEPROMCommand, (EEWriteDisable)); + cs8900_eeprom_wait(dev); + + return 0; +} + +/* + * Debugging functions + */ + +#ifdef DEBUG +static inline int printable (int c) +{ + return ((c >= 32 && c <= 126) || + (c >= 174 && c <= 223) || + (c >= 242 && c <= 243) || + (c >= 252 && c <= 253)); +} + +static void dump16 (struct net_device *dev,const u8 *s,size_t len) +{ + int i; + char str[128]; + + if (!len) return; + + *str = '\0'; + + for (i = 0; i < len; i++) { + if (i && !(i % 4)) strcat (str," "); + sprintf (str,"%s%.2x ",str,s[i]); + } + + for ( ; i < 16; i++) { + if (i && !(i % 4)) strcat (str," "); + strcat (str," "); + } + + strcat (str," "); + for (i = 0; i < len; i++) sprintf (str,"%s%c",str,printable (s[i]) ? s[i] : '.'); + + printk (KERN_DEBUG "%s: %s\n",dev->name,str); +} + +static void hexdump (struct net_device *dev,const void *ptr,size_t size) +{ + const u8 *s = (u8 *) ptr; + int i; + for (i = 0; i < size / 16; i++, s += 16) dump16 (dev,s,16); + dump16 (dev,s,size % 16); +} + +static void dump_packet (struct net_device *dev,struct sk_buff *skb,const char *type) +{ + printk (KERN_INFO "%s: %s %d byte frame %.2x:%.2x:%.2x:%.2x:%.2x:%.2x to %.2x:%.2x:%.2x:%.2x:%.2x:%.2x type %.4x\n", + dev->name, + type, + skb->len, + skb->data[0],skb->data[1],skb->data[2],skb->data[3],skb->data[4],skb->data[5], + skb->data[6],skb->data[7],skb->data[8],skb->data[9],skb->data[10],skb->data[11], + (skb->data[12] << 8) | skb->data[13]); + if (skb->len < 0x100) hexdump (dev,skb->data,skb->len); +} + +static void eepromdump( struct net_device *dev) +{ + u16 buf[0x80]; + u16 i; + int count; + int total; + + if( cs8900_read( dev, PP_SelfST) & EEPROMpresent) + { + printk (KERN_INFO "%s: EEPROM present\n",dev->name); + } + else + { + printk (KERN_INFO "%s: NO EEPROM present\n",dev->name); + return; + } + + if( cs8900_read( dev, PP_SelfST) & EEPROMOK) + { + printk (KERN_INFO "%s: EEPROM OK\n",dev->name); + } + else + { + printk (KERN_INFO "%s: EEPROM checksum mismatch - fixing...\n",dev->name); + } + + printk (KERN_INFO "%s: Hexdump\n",dev->name); + for( i=0; i<0x80; i++) + { + cs8900_eeprom_read( dev, &buf[i], i); + } + hexdump( dev, buf, 0x100); + + if( buf[0] & 0x0100) + { + printk (KERN_INFO "%s: non-sequential EEPROM\n",dev->name); + } + else + { + printk (KERN_INFO "%s: sequential EEPROM\n",dev->name); + } + + if( (buf[0] & 0xe000) == 0xa000) + { + printk (KERN_INFO "%s: Found reset configuration block\n",dev->name); + } + else + { + printk (KERN_INFO "%s: Reset configuration block not found\n",dev->name); + return; + } + + count = 2; + total = buf[0] & 0xff; + printk (KERN_INFO "%s: Reset configuration block size = %d bytes\n",dev->name, total); + + while( count < total) + { + int groupsize = (buf[count/2] >> 12) + 1; + int basereg = (buf[count/2] &0x1ff); + printk (KERN_INFO "%s: Group size = %d words\n",dev->name, groupsize); + printk (KERN_INFO "%s: Base register = %x\n",dev->name, basereg); + count += (groupsize + 1)*2; + } +} + +#endif /* #ifdef DEBUG */ + +/* + * Driver functions + */ + +static void cs8900_receive (struct net_device *dev) +{ + cs8900_t *priv = (cs8900_t *) dev->priv; + struct sk_buff *skb; + u16 status,length; + + status = cs8900_read (dev,PP_RxStatus); + length = cs8900_read (dev,PP_RxLength); + + if (!(status & RxOK)) { + priv->stats.rx_errors++; + if ((status & (Runt | Extradata))) priv->stats.rx_length_errors++; + if ((status & CRCerror)) priv->stats.rx_crc_errors++; + return; + } + + if ((skb = dev_alloc_skb (length + 4)) == NULL) { + priv->stats.rx_dropped++; + return; + } + + skb->dev = dev; + skb_reserve (skb,2); + + cs8900_frame_read (dev,skb,length); + +#ifdef FULL_DUPLEX + dump_packet (dev,skb,"recv"); +#endif /* #ifdef FULL_DUPLEX */ + + skb->protocol = eth_type_trans (skb,dev); + + netif_rx (skb); + dev->last_rx = jiffies; + + priv->stats.rx_packets++; + priv->stats.rx_bytes += length; +} + +static int cs8900_send_start (struct sk_buff *skb,struct net_device *dev) +{ + cs8900_t *priv = (cs8900_t *) dev->priv; + u16 status; + + spin_lock_irq(&priv->lock); + netif_stop_queue (dev); + + cs8900_write (dev,PP_TxCMD,TxStart (After5)); + cs8900_write (dev,PP_TxLength,skb->len); + + status = cs8900_read (dev,PP_BusST); + + if ((status & TxBidErr)) { + spin_unlock_irq(&priv->lock); + printk (KERN_WARNING "%s: Invalid frame size %d!\n",dev->name,skb->len); + priv->stats.tx_errors++; + priv->stats.tx_aborted_errors++; + priv->txlen = 0; + return (1); + } + + if (!(status & Rdy4TxNOW)) { + spin_unlock_irq(&priv->lock); + printk (KERN_WARNING "%s: Transmit buffer not free!\n",dev->name); + priv->stats.tx_errors++; + priv->txlen = 0; + /* FIXME: store skb and send it in interrupt handler */ + return (1); + } + + cs8900_frame_write (dev,skb); + spin_unlock_irq(&priv->lock); + +#ifdef DEBUG + dump_packet (dev,skb,"send"); +#endif /* #ifdef DEBUG */ + + dev->trans_start = jiffies; + + dev_kfree_skb (skb); + + priv->txlen = skb->len; + + return (0); +} + +static irqreturn_t cs8900_interrupt (int irq,void *id,struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) id; + cs8900_t *priv; + volatile u16 status; + irqreturn_t handled = 0; + + if (dev->priv == NULL) { + printk (KERN_WARNING "%s: irq %d for unknown device.\n",dev->name,irq); + return 0; + } + + priv = (cs8900_t *) dev->priv; + + while ((status = cs8900_read (dev, PP_ISQ))) { + handled = 1; + + switch (RegNum (status)) { + case RxEvent: + cs8900_receive (dev); + break; + + case TxEvent: + priv->stats.collisions += ColCount (cs8900_read (dev,PP_TxCOL)); + if (!(RegContent (status) & TxOK)) { + priv->stats.tx_errors++; + if ((RegContent (status) & Out_of_window)) priv->stats.tx_window_errors++; + if ((RegContent (status) & Jabber)) priv->stats.tx_aborted_errors++; + break; + } else if (priv->txlen) { + priv->stats.tx_packets++; + priv->stats.tx_bytes += priv->txlen; + } + priv->txlen = 0; + netif_wake_queue (dev); + break; + + case BufEvent: + if ((RegContent (status) & RxMiss)) { + u16 missed = MissCount (cs8900_read (dev,PP_RxMISS)); + priv->stats.rx_errors += missed; + priv->stats.rx_missed_errors += missed; + } + if ((RegContent (status) & TxUnderrun)) { + priv->stats.tx_errors++; + priv->stats.tx_fifo_errors++; + + priv->txlen = 0; + netif_wake_queue (dev); + } + /* FIXME: if Rdy4Tx, transmit last sent packet (if any) */ + break; + + case TxCOL: + priv->stats.collisions += ColCount (cs8900_read (dev,PP_TxCOL)); + break; + + case RxMISS: + status = MissCount (cs8900_read (dev,PP_RxMISS)); + priv->stats.rx_errors += status; + priv->stats.rx_missed_errors += status; + break; + } + } + return IRQ_RETVAL(handled); +} + +static void cs8900_transmit_timeout (struct net_device *dev) +{ + cs8900_t *priv = (cs8900_t *) dev->priv; + priv->stats.tx_errors++; + priv->stats.tx_heartbeat_errors++; + priv->txlen = 0; + netif_wake_queue (dev); +} + +static int cs8900_start (struct net_device *dev) +{ + int result; + +#if defined(CONFIG_ARCH_SMDK2410) + set_irq_type(dev->irq, IRQT_RISING); + + /* enable the ethernet controller */ + cs8900_set (dev,PP_RxCFG,RxOKiE | BufferCRC | CRCerroriE | RuntiE | ExtradataiE); + cs8900_set (dev,PP_RxCTL,RxOKA | IndividualA | BroadcastA); + cs8900_set (dev,PP_TxCFG,TxOKiE | Out_of_windowiE | JabberiE); + cs8900_set (dev,PP_BufCFG,Rdy4TxiE | RxMissiE | TxUnderruniE | TxColOvfiE | MissOvfloiE); + cs8900_set (dev,PP_LineCTL,SerRxON | SerTxON); + cs8900_set (dev,PP_BusCTL,EnableRQ); + +#ifdef FULL_DUPLEX + cs8900_set (dev,PP_TestCTL,FDX); +#endif /* #ifdef FULL_DUPLEX */ + udelay(200); + /* install interrupt handler */ + if ((result = request_irq (dev->irq, &cs8900_interrupt, 0, dev->name, dev)) < 0) { + printk ("%s: could not register interrupt %d\n",dev->name, dev->irq); + return (result); + } +#else + + /* install interrupt handler */ + if ((result = request_irq (dev->irq, &cs8900_interrupt, 0, dev->name, dev)) < 0) { + printk ("%s: could not register interrupt %d\n",dev->name, dev->irq); + return (result); + } + + set_irq_type(dev->irq, IRQT_RISING); + + /* enable the ethernet controller */ + cs8900_set (dev,PP_RxCFG,RxOKiE | BufferCRC | CRCerroriE | RuntiE | ExtradataiE); + cs8900_set (dev,PP_RxCTL,RxOKA | IndividualA | BroadcastA); + cs8900_set (dev,PP_TxCFG,TxOKiE | Out_of_windowiE | JabberiE); + cs8900_set (dev,PP_BufCFG,Rdy4TxiE | RxMissiE | TxUnderruniE | TxColOvfiE | MissOvfloiE); + cs8900_set (dev,PP_LineCTL,SerRxON | SerTxON); + cs8900_set (dev,PP_BusCTL,EnableRQ); + +#ifdef FULL_DUPLEX + cs8900_set (dev,PP_TestCTL,FDX); +#endif /* #ifdef FULL_DUPLEX */ + +#endif /* #if defined(CONFIG_ARCH_SMDK2410) */ + + /* start the queue */ + netif_start_queue (dev); + + return (0); +} + +static int cs8900_stop (struct net_device *dev) +{ + /* disable ethernet controller */ + cs8900_write (dev,PP_BusCTL,0); + cs8900_write (dev,PP_TestCTL,0); + cs8900_write (dev,PP_SelfCTL,0); + cs8900_write (dev,PP_LineCTL,0); + cs8900_write (dev,PP_BufCFG,0); + cs8900_write (dev,PP_TxCFG,0); + cs8900_write (dev,PP_RxCTL,0); + cs8900_write (dev,PP_RxCFG,0); + + /* uninstall interrupt handler */ + free_irq (dev->irq,dev); + + /* stop the queue */ + netif_stop_queue (dev); + + return (0); +} + +static struct net_device_stats *cs8900_get_stats (struct net_device *dev) +{ + cs8900_t *priv = (cs8900_t *) dev->priv; + return (&priv->stats); +} + +static void cs8900_set_receive_mode (struct net_device *dev) +{ + if ((dev->flags & IFF_PROMISC)) + cs8900_set (dev,PP_RxCTL,PromiscuousA); + else + cs8900_clear (dev,PP_RxCTL,PromiscuousA); + + if ((dev->flags & IFF_ALLMULTI) && dev->mc_list) + cs8900_set (dev,PP_RxCTL,MulticastA); + else + cs8900_clear (dev,PP_RxCTL,MulticastA); +} + +static int cs8900_eeprom (struct net_device *dev) +{ + cs8900_t *priv = (cs8900_t *) dev->priv; + int i; + + /* SMDK2410 CS8900A without EEPROM at all */ +#if defined(CONFIG_ARCH_SMDK2410) + return (-ENODEV); +#endif + +#ifdef DEBUG + eepromdump (dev); +#endif + + if( (cs8900_read( dev, PP_SelfST) & EEPROMpresent) == 0) + { + /* no eeprom */ + return (-ENODEV); + } + + /* add character device for easy eeprom programming */ + if( (priv->char_devnum=register_chrdev(0,"cs8900_eeprom",&cs8900_eeprom_fops)) != 0) + printk (KERN_INFO "%s: Registered cs8900_eeprom char device (major #%d)\n", + dev->name, priv->char_devnum); + else + printk (KERN_WARNING "%s: Failed to register char device cs8900_eeprom\n",dev->name); + + if( (cs8900_read( dev, PP_SelfST) & EEPROMOK) == 0) + { + /* bad checksum, invalid config block */ + return (-EFAULT); + } + + /* If we get here, the chip will have initialized the registers + * that were specified in the eeprom configuration block + * We assume this is at least the mac address. + */ + for (i = 0; i < ETH_ALEN; i += 2) + { + u16 mac = cs8900_read (dev,PP_IA + i); + dev->dev_addr[i] = mac & 0xff; + dev->dev_addr[i+1] = (mac>>8) & 0xff; + } + + return (0); +} + +/* + * EEPROM Charater device + */ + +static int cs8900_eeprom_fopen(struct inode *inode, struct file *file) +{ + u16 i; + for( i=0; if_pos + offset; + break; + case 2: /* SEEK_END */ + newpos = (MAX_EEPROM_SIZE-1) - offset; + break; + default: /* can't happen */ + return -EINVAL; + + } + + if( (newpos<0) || (newpos>=MAX_EEPROM_SIZE)) return -EINVAL; + + file->f_pos = newpos; + return newpos; +} + +static ssize_t cs8900_eeprom_fread(struct file *file, char *buf, size_t count, loff_t *f_pos) +{ + unsigned char *temp = (unsigned char *)cs8900_eeprom_cache; + + if (*f_pos >= MAX_EEPROM_SIZE) + return 0; + + if (*f_pos + count > MAX_EEPROM_SIZE) + count = MAX_EEPROM_SIZE - *f_pos; + + if (count<1) + return 0; + + if (copy_to_user(buf, &temp[*f_pos], count)){ + return -EFAULT; + } + *f_pos += count; + return count; +} + +static ssize_t cs8900_eeprom_fwrite(struct file *file, const char *buf, size_t count, loff_t *f_pos) +{ + u16 i; + unsigned char *temp = (unsigned char *)cs8900_eeprom_cache; + + if (*f_pos >= MAX_EEPROM_SIZE) + return 0; + + if (*f_pos + count > MAX_EEPROM_SIZE) + count = MAX_EEPROM_SIZE - *f_pos; + + if (count<1) + return 0; + + /* FIXME: lock critical section */ + + /* update the cache */ + if (copy_from_user(&temp[*f_pos], buf, count)){ + return -EFAULT; + } + + /* not concerned about performance, so write the entire thing */ + for( i=0; iopen = cs8900_start; + dev->stop = cs8900_stop; + dev->hard_start_xmit = cs8900_send_start; + dev->get_stats = cs8900_get_stats; + dev->set_multicast_list = cs8900_set_receive_mode; + dev->tx_timeout = cs8900_transmit_timeout; + dev->watchdog_timeo = HZ; + +#if defined(CONFIG_ARCH_SMDK2410) + dev->dev_addr[0] = 0x08; + dev->dev_addr[1] = 0x00; + dev->dev_addr[2] = 0x3e; + dev->dev_addr[3] = 0x26; + dev->dev_addr[4] = 0x0a; + dev->dev_addr[5] = 0x5b; +#else + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x12; + dev->dev_addr[2] = 0x34; + dev->dev_addr[3] = 0x56; + dev->dev_addr[4] = 0x78; + dev->dev_addr[5] = 0x9a; +#endif + + dev->if_port = IF_PORT_10BASET; + dev->priv = (void *) &priv; + + spin_lock_init(&priv.lock); + + SET_MODULE_OWNER (dev); + +#ifdef CONFIG_SA1100_FRODO + dev->base_addr = FRODO_ETH_IO + 0x300; + dev->irq = FRODO_ETH_IRQ; + frodo_reset (dev); +#endif /* #ifdef CONFIG_SA1100_FRODO */ + +#if defined(CONFIG_SA1100_CERF) + dev->base_addr = CERF_ETH_IO + 0x300; + dev->irq = CERF_ETH_IRQ; +#endif /* #if defined(CONFIG_SA1100_CERF) */ + +#if defined(CONFIG_ARCH_SMDK2410) + dev->base_addr = vSMDK2410_ETH_IO + 0x300; + dev->irq = SMDK2410_ETH_IRQ; +#endif /* #if defined(CONFIG_ARCH_SMDK2410) */ + + if ((result = check_mem_region (dev->base_addr, 16))) { + printk (KERN_ERR "%s: can't get I/O port address 0x%lx\n",dev->name,dev->base_addr); + return (result); + } + request_mem_region (dev->base_addr, 16, dev->name); + + /* verify EISA registration number for Cirrus Logic */ + if ((value = cs8900_read (dev,PP_ProductID)) != EISA_REG_CODE) { + printk (KERN_ERR "%s: incorrect signature 0x%.4x\n",dev->name,value); + return (-ENXIO); + } + + /* verify chip version */ + value = cs8900_read (dev,PP_ProductID + 2); + if (VERSION (value) != CS8900A) { + printk (KERN_ERR "%s: unknown chip version 0x%.8x\n",dev->name,VERSION (value)); + return (-ENXIO); + } + /* setup interrupt number */ + cs8900_write (dev,PP_IntNum,0); + + /* If an EEPROM is present, use it's MAC address. A valid EEPROM will + * initialize the registers automatically. + */ + result = cs8900_eeprom (dev); + + printk (KERN_INFO "%s: CS8900A rev %c at %#lx irq=%d", + dev->name,'B' + REVISION (value) - REV_B, dev->base_addr, dev->irq); + if (result == -ENODEV) { + /* no eeprom or invalid config block, configure MAC address by hand */ + for (i = 0; i < ETH_ALEN; i += 2) + cs8900_write (dev,PP_IA + i,dev->dev_addr[i] | (dev->dev_addr[i + 1] << 8)); + printk (", no eeprom "); + } + else if( result == -EFAULT) + { +#if defined(CONFIG_SA1100_CERF) + /* The default eeprom layout doesn't follow the cs8900 layout + * that enables automatic cs8900 initialization. Doh! + * Read the mac address manually. + */ + u16 MAC_addr[3] = {0, 0, 0}; + + if (cs8900_eeprom_read(dev, &MAC_addr[0], 0x1c) == -1) + printk("\ncs8900: [CERF] EEPROM[0] read failed\n"); + if (cs8900_eeprom_read(dev, &MAC_addr[1], 0x1d) == -1) + printk("\ncs8900: [CERF] EEPROM[1] read failed\n"); + if (cs8900_eeprom_read(dev, &MAC_addr[2], 0x1e) == -1) + printk("\ncs8900: [CERF] EEPROM[2] read failed\n"); + + for (i = 0; i < ETH_ALEN / 2; i++) + { + dev->dev_addr[i*2] = MAC_addr[i] & 0xff; + dev->dev_addr[i*2+1] = (MAC_addr[i] >> 8) & 0xff; + + cs8900_write (dev,PP_IA + i*2,dev->dev_addr[i*2] | (dev->dev_addr[i*2 + 1] << 8)); + } + printk (", eeprom (smdk2410 layout)"); +#else + printk (", eeprom (invalid config block)"); +#endif /* #if defined(CONFIG_SA1100_CERF) */ + } + else + { + printk (", eeprom ok"); + } + + printk (", addr:"); + for (i = 0; i < ETH_ALEN; i += 2) + { + u16 mac = cs8900_read (dev,PP_IA + i); + printk ("%c%02X:%2X", (i==0)?' ':':', mac & 0xff, (mac >> 8)); + } + printk ("\n"); + + return (0); +} + +static int __init cs8900_init (void) +{ + strcpy(cs8900_dev.name, "eth%d"); + + return (register_netdev (&cs8900_dev)); +} + +static void __exit cs8900_cleanup (void) +{ + cs8900_t *priv = (cs8900_t *) cs8900_dev.priv; + if( priv->char_devnum) + { + unregister_chrdev(priv->char_devnum,"cs8900_eeprom"); + } + release_mem_region (cs8900_dev.base_addr,16); + unregister_netdev (&cs8900_dev); +} + +MODULE_AUTHOR ("Abraham van der Merwe "); +MODULE_DESCRIPTION (VERSION_STRING); +MODULE_LICENSE ("GPL"); + +module_init (cs8900_init); +module_exit (cs8900_cleanup); diff -Nur linux-2.6.14/drivers/net/arm/cs8900.h linux-2.6.14_cs8900/drivers/net/arm/cs8900.h --- linux-2.6.14/drivers/net/arm/cs8900.h 1970-01-01 08:00:00.000000000 +0800 +++ linux-2.6.14_cs8900/drivers/net/arm/cs8900.h 2008-02-03 23:15:49.000000000 +0800 @@ -0,0 +1,237 @@ +#ifndef CS8900_H +#define CS8900_H + +/* + * linux/drivers/net/cs8900.h + * + * Author: Abraham van der Merwe + * + * A Cirrus Logic CS8900A driver for Linux + * based on the cs89x0 driver written by Russell Nelson, + * Donald Becker, and others. + * + * This source code is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +/* + * Ports + */ + +#define PP_Address 0x0a /* PacketPage Pointer Port (Section 4.10.10) */ +#define PP_Data 0x0c /* PacketPage Data Port (Section 4.10.10) */ + +/* + * Registers + */ + +#define PP_ProductID 0x0000 /* Section 4.3.1 Product Identification Code */ +#define PP_MemBase 0x002c /* Section 4.9.2 Memory Base Address Register */ +#define PP_IntNum 0x0022 /* Section 3.2.3 Interrupt Number */ +#define PP_EEPROMCommand 0x0040 /* Section 4.3.11 EEPROM Command */ +#define PP_EEPROMData 0x0042 /* Section 4.3.12 EEPROM Data */ +#define PP_RxCFG 0x0102 /* Section 4.4.6 Receiver Configuration */ +#define PP_RxCTL 0x0104 /* Section 4.4.8 Receiver Control */ +#define PP_TxCFG 0x0106 /* Section 4.4.9 Transmit Configuration */ +#define PP_BufCFG 0x010a /* Section 4.4.12 Buffer Configuration */ +#define PP_LineCTL 0x0112 /* Section 4.4.16 Line Control */ +#define PP_SelfCTL 0x0114 /* Section 4.4.18 Self Control */ +#define PP_BusCTL 0x0116 /* Section 4.4.20 Bus Control */ +#define PP_TestCTL 0x0118 /* Section 4.4.22 Test Control */ +#define PP_ISQ 0x0120 /* Section 4.4.5 Interrupt Status Queue */ +#define PP_TxEvent 0x0128 /* Section 4.4.10 Transmitter Event */ +#define PP_BufEvent 0x012c /* Section 4.4.13 Buffer Event */ +#define PP_RxMISS 0x0130 /* Section 4.4.14 Receiver Miss Counter */ +#define PP_TxCOL 0x0132 /* Section 4.4.15 Transmit Collision Counter */ +#define PP_SelfST 0x0136 /* Section 4.4.19 Self Status */ +#define PP_BusST 0x0138 /* Section 4.4.21 Bus Status */ +#define PP_TxCMD 0x0144 /* Section 4.4.11 Transmit Command */ +#define PP_TxLength 0x0146 /* Section 4.5.2 Transmit Length */ +#define PP_IA 0x0158 /* Section 4.6.2 Individual Address (IEEE Address) */ +#define PP_RxStatus 0x0400 /* Section 4.7.1 Receive Status */ +#define PP_RxLength 0x0402 /* Section 4.7.1 Receive Length (in bytes) */ +#define PP_RxFrame 0x0404 /* Section 4.7.2 Receive Frame Location */ +#define PP_TxFrame 0x0a00 /* Section 4.7.2 Transmit Frame Location */ + +/* + * Values + */ + +/* PP_IntNum */ +#define INTRQ0 0x0000 +#define INTRQ1 0x0001 +#define INTRQ2 0x0002 +#define INTRQ3 0x0003 + +/* PP_ProductID */ +#define EISA_REG_CODE 0x630e +#define REVISION(x) (((x) & 0x1f00) >> 8) +#define VERSION(x) ((x) & ~0x1f00) + +#define CS8900A 0x0000 +#define REV_B 7 +#define REV_C 8 +#define REV_D 9 + +/* PP_RxCFG */ +#define Skip_1 0x0040 +#define StreamE 0x0080 +#define RxOKiE 0x0100 +#define RxDMAonly 0x0200 +#define AutoRxDMAE 0x0400 +#define BufferCRC 0x0800 +#define CRCerroriE 0x1000 +#define RuntiE 0x2000 +#define ExtradataiE 0x4000 + +/* PP_RxCTL */ +#define IAHashA 0x0040 +#define PromiscuousA 0x0080 +#define RxOKA 0x0100 +#define MulticastA 0x0200 +#define IndividualA 0x0400 +#define BroadcastA 0x0800 +#define CRCerrorA 0x1000 +#define RuntA 0x2000 +#define ExtradataA 0x4000 + +/* PP_TxCFG */ +#define Loss_of_CRSiE 0x0040 +#define SQErroriE 0x0080 +#define TxOKiE 0x0100 +#define Out_of_windowiE 0x0200 +#define JabberiE 0x0400 +#define AnycolliE 0x0800 +#define T16colliE 0x8000 + +/* PP_BufCFG */ +#define SWint_X 0x0040 +#define RxDMAiE 0x0080 +#define Rdy4TxiE 0x0100 +#define TxUnderruniE 0x0200 +#define RxMissiE 0x0400 +#define Rx128iE 0x0800 +#define TxColOvfiE 0x1000 +#define MissOvfloiE 0x2000 +#define RxDestiE 0x8000 + +/* PP_LineCTL */ +#define SerRxON 0x0040 +#define SerTxON 0x0080 +#define AUIonly 0x0100 +#define AutoAUI_10BT 0x0200 +#define ModBackoffE 0x0800 +#define PolarityDis 0x1000 +#define L2_partDefDis 0x2000 +#define LoRxSquelch 0x4000 + +/* PP_SelfCTL */ +#define RESET 0x0040 +#define SWSuspend 0x0100 +#define HWSleepE 0x0200 +#define HWStandbyE 0x0400 +#define HC0E 0x1000 +#define HC1E 0x2000 +#define HCB0 0x4000 +#define HCB1 0x8000 + +/* PP_BusCTL */ +#define ResetRxDMA 0x0040 +#define DMAextend 0x0100 +#define UseSA 0x0200 +#define MemoryE 0x0400 +#define DMABurst 0x0800 +#define IOCHRDYE 0x1000 +#define RxDMAsize 0x2000 +#define EnableRQ 0x8000 + +/* PP_TestCTL */ +#define DisableLT 0x0080 +#define ENDECloop 0x0200 +#define AUIloop 0x0400 +#define DisableBackoff 0x0800 +#define FDX 0x4000 + +/* PP_ISQ */ +#define RegNum(x) ((x) & 0x3f) +#define RegContent(x) ((x) & ~0x3d) + +#define RxEvent 0x0004 +#define TxEvent 0x0008 +#define BufEvent 0x000c +#define RxMISS 0x0010 +#define TxCOL 0x0012 + +/* PP_RxStatus */ +#define IAHash 0x0040 +#define Dribblebits 0x0080 +#define RxOK 0x0100 +#define Hashed 0x0200 +#define IndividualAdr 0x0400 +#define Broadcast 0x0800 +#define CRCerror 0x1000 +#define Runt 0x2000 +#define Extradata 0x4000 + +#define HashTableIndex(x) ((x) >> 0xa) + +/* PP_TxCMD */ +#define After5 0 +#define After381 1 +#define After1021 2 +#define AfterAll 3 +#define TxStart(x) ((x) << 6) + +#define Force 0x0100 +#define Onecoll 0x0200 +#define InhibitCRC 0x1000 +#define TxPadDis 0x2000 + +/* PP_BusST */ +#define TxBidErr 0x0080 +#define Rdy4TxNOW 0x0100 + +/* PP_TxEvent */ +#define Loss_of_CRS 0x0040 +#define SQEerror 0x0080 +#define TxOK 0x0100 +#define Out_of_window 0x0200 +#define Jabber 0x0400 +#define T16coll 0x8000 + +#define TX_collisions(x) (((x) >> 0xb) & ~0x8000) + +/* PP_BufEvent */ +#define SWint 0x0040 +#define RxDMAFrame 0x0080 +#define Rdy4Tx 0x0100 +#define TxUnderrun 0x0200 +#define RxMiss 0x0400 +#define Rx128 0x0800 +#define RxDest 0x8000 + +/* PP_RxMISS */ +#define MissCount(x) ((x) >> 6) + +/* PP_TxCOL */ +#define ColCount(x) ((x) >> 6) + +/* PP_SelfST */ +#define T3VActive 0x0040 +#define INITD 0x0080 +#define SIBUSY 0x0100 +#define EEPROMpresent 0x0200 +#define EEPROMOK 0x0400 +#define ELpresent 0x0800 +#define EEsize 0x1000 + +/* PP_EEPROMCommand */ +#define EEWriteEnable 0x00F0 +#define EEWriteDisable 0x0000 +#define EEWriteRegister 0x0100 +#define EEReadRegister 0x0200 +#define EEEraseRegister 0x0300 +#define ELSEL 0x0400 + +#endif /* #ifndef CS8900_H */ diff -Nur linux-2.6.14/drivers/net/arm/Kconfig linux-2.6.14_cs8900/drivers/net/arm/Kconfig --- linux-2.6.14/drivers/net/arm/Kconfig 2005-10-28 08:02:08.000000000 +0800 +++ linux-2.6.14_cs8900/drivers/net/arm/Kconfig 2008-02-03 23:16:28.000000000 +0800 @@ -44,3 +44,11 @@ will generate a suitable hw address based on the board serial number (MTD support is required for this). Otherwise you will need to set a suitable hw address using ifconfig. +config ARM_CS8900 + tristate "CS8900 support" + depends on NET_ETHERNET && ARM && ARCH_SMDK2410 + help + Support for CS8900A chipset based Ethernet cards. If you have a network + (Ethernet) card of this type, say Y and read the Ethernet-HOWTO, available + from as well as .To compile this driver as a module, choose M here and read. + The module will be called cs8900.o. diff -Nur linux-2.6.14/drivers/net/arm/Makefile linux-2.6.14_cs8900/drivers/net/arm/Makefile --- linux-2.6.14/drivers/net/arm/Makefile 2005-10-28 08:02:08.000000000 +0800 +++ linux-2.6.14_cs8900/drivers/net/arm/Makefile 2008-02-03 23:44:15.000000000 +0800 @@ -8,3 +8,4 @@ obj-$(CONFIG_ARM_ETHERH) += etherh.o obj-$(CONFIG_ARM_ETHER3) += ether3.o obj-$(CONFIG_ARM_ETHER1) += ether1.o +obj-$(CONFIG_ARM_CS8900) += cs8900.o diff -Nur linux-2.6.14/include/asm-arm/arch-s3c2410/smdk2410.h linux-2.6.14_cs8900/include/asm-arm/arch-s3c2410/smdk2410.h --- linux-2.6.14/include/asm-arm/arch-s3c2410/smdk2410.h 1970-01-01 08:00:00.000000000 +0800 +++ linux-2.6.14_cs8900/include/asm-arm/arch-s3c2410/smdk2410.h 2008-02-03 23:05:36.000000000 +0800 @@ -0,0 +1,7 @@ +#ifndef _INCLUDE_SMDK2410_H_ +#define _INCLUDE_SMDK2410_H_ +#include +#define pSMDK2410_ETH_IO 0x19000000 +#define vSMDK2410_ETH_IO 0xE0000000 +#define SMDK2410_ETH_IRQ IRQ_EINT9 +#endif // _INCLUDE_SMDK2410_H_ skyeye-1.2.5_REL/misc/dev-cpp_support/0000755000175000001440000000000011023514411016313 5ustar kshusersskyeye-1.2.5_REL/misc/dev-cpp_support/skyeye-win.layout0000644000175000001440000003153610541455476021711 0ustar kshusers[Editor_1] CursorCol=1 CursorRow=21 TopLine=1 LeftChar=1 Open=0 Top=0 [Editor_87] CursorCol=19 CursorRow=171 TopLine=154 LeftChar=1 Open=0 Top=0 [Editor_2] CursorCol=35 CursorRow=131 TopLine=109 LeftChar=1 Open=0 Top=0 [Editor_216] CursorCol=1 CursorRow=25 TopLine=1 LeftChar=1 Open=0 Top=0 [Editor_226] CursorCol=1 CursorRow=80 TopLine=50 LeftChar=1 Open=0 Top=0 [Editor_232] CursorCol=27 CursorRow=35 TopLine=10 LeftChar=1 Open=0 Top=0 [Editor_235] CursorCol=1 CursorRow=30 TopLine=11 LeftChar=1 Open=0 Top=0 [Editor_7] CursorCol=58 CursorRow=179 TopLine=160 LeftChar=1 Open=0 Top=0 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OverrideBuildCmd=0 BuildCmd= [Unit240] FileName=utils\debugger\bfin_regdefs.h CompileCpp=0 Folder=utils/debugger Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit241] FileName=utils\debugger\cf_regdefs.h CompileCpp=0 Folder=utils/debugger Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit242] FileName=utils\debugger\skyeye2gdb.c CompileCpp=0 Folder=utils/debugger Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit243] FileName=utils\debugger\skyeye2gdb.h CompileCpp=0 Folder=utils/debugger Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit244] FileName=utils\main\elf32.h CompileCpp=0 Folder=utils/main Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit245] FileName=utils\main\skyeye.c CompileCpp=0 Folder=utils/main Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit246] FileName=utils\main\skyeye.h CompileCpp=0 Folder=utils/main Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit247] FileName=utils\share\ansidecl.h CompileCpp=0 Folder=utils/share Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit248] FileName=utils\stub\skyeye_stub_win32.c CompileCpp=0 Folder=utils/stub Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [VersionInfo] Major=0 Minor=1 Release=1 Build=1 LanguageID=1033 CharsetID=1252 CompanyName= FileVersion= FileDescription=Developed using the Dev-C++ IDE InternalName= LegalCopyright= LegalTrademarks= OriginalFilename= ProductName= ProductVersion= AutoIncBuildNr=0 [Unit249] FileName=Makefile Folder=skyeye-win Compile=0 Link=0 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit250] FileName=arch\arm\mach\mingw_help.c CompileCpp=0 Folder=arch/arm/mach Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit251] FileName=arch\arm\mach\mingw_help.h CompileCpp=0 Folder=arch/arm/mach Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= [Unit252] FileName=device\net\skyeye_net_tap.c CompileCpp=0 Folder=device/net Compile=1 Link=1 Priority=1000 OverrideBuildCmd=0 BuildCmd= skyeye-1.2.5_REL/misc/conf/0000755000175000001440000000000011023514411014106 5ustar kshusersskyeye-1.2.5_REL/misc/conf/scripts/0000755000175000001440000000000011023514411015575 5ustar kshusersskyeye-1.2.5_REL/misc/conf/scripts/Menuconfig0000644000175000001440000006627410541455476017654 0ustar kshusers#! /bin/sh # # This script is used to configure the SkyEye library. # Borrowed from linux kernel configuration scripts. # # This script attempts to parse the configuration files, which are # scattered throughout the source tree, and creates a temporary # set of mini scripts which are in turn used to create nested menus and # radiolists. # # It uses a very modified/mutilated version of the "dialog" utility # written by Savio Lam (lam836@cs.cuhk.hk). Savio is not responsible # for this script or the version of dialog used by this script. # Please do not contact him with questions. The official version of # dialog is available at sunsite.unc.edu or a sunsite mirror. # # # Change this to TRUE if you prefer all configure options listed # in a single menu rather than the standard menu hierarchy. # single_menu_mode= # # Make sure we're really running bash. # [ -z "$BASH" ] && { echo "Menuconfig requires bash" 1>&2; exit 1; } # # Cache function definitions, turn off posix compliance # set -h +o posix # Given a configuration variable, set the global variable $x to its value, # and the global variable $info to the string " (NEW)" if this is a new # variable. # # This function looks for: (1) the current value, or (2) the default value # from the arch-dependent defconfig file, or (3) a default passed by the caller. function set_x_info () { eval x=\$$1 if [ -z "$x" ]; then eval `sed -n -e 's/# \(.*\) is not set.*/\1=n/' -e "/^$1=/p" arch/$ARCH/defconfig` eval x=\${$1:-\"$2\"} eval $1=$x #eval INFO_$1="' (NEW)'" fi eval info=\"\$INFO_$1\" } # # Load the functions used by the config.in files. # # I do this because these functions must be redefined depending # on whether they are being called for interactive use or for # saving a configuration to a file. # # Thank the heavens bash supports nesting function definitions. # load_functions () { # # Additional comments # function comment () { comment_ctr=$[ comment_ctr + 1 ] echo -ne "': $comment_ctr' '--- $1' " >>MCmenu } # # Define a boolean to a specific value. # function define_bool () { eval $1=$2 } function define_tristate () { eval $1=$2 } function define_hex () { eval $1=$2 } function define_int () { eval $1=$2 } function define_string () { eval $1=\"$2\" } function define_mystring () { eval $1=$2 } function define_mystring_null () { eval $1=$2 } # # Create a boolean (Yes/No) function for our current menu # which calls our local bool function. # function bool () { set_x_info "$2" "n" case $x in y|m) flag="*" ;; n) flag=" " ;; esac echo -ne "'$2' '[$flag] $1$info' " >>MCmenu echo -e "function $2 () { l_bool '$2' \"\$1\" ;}\n" >>MCradiolists } # # Create a tristate (Yes/No/Module) radiolist function # which calls our local tristate function. # # Collapses to a boolean (Yes/No) if module support is disabled. # function tristate () { if [ "$CONFIG_MODULES" != "y" ] then bool "$1" "$2" else set_x_info "$2" "n" case $x in y) flag="*" ;; m) flag="M" ;; *) flag=" " ;; esac echo -ne "'$2' '<$flag> $1$info' " >>MCmenu echo -e " function $2 () { l_tristate '$2' \"\$1\" ;}" >>MCradiolists fi } # # Create a tristate radiolist function which is dependent on # another SkyEye configuration option. # # Quote from the original configure script: # # function dep_tristate () { ques="$1" var="$2" dep=y shift 2 while [ $# -gt 0 ]; do if [ "$1" = y ]; then shift elif [ "$1" = m ]; then dep=m shift else dep=n shift $# fi done if [ "$dep" = y ]; then tristate "$ques" "$var" elif [ "$dep" = m ]; then mod_bool "$ques" "$var" else define_tristate "$var" n fi } # # Same as above, but now only Y and N are allowed as dependency # (i.e. third and next arguments). # function dep_bool () { ques="$1" var="$2" dep=y shift 2 while [ $# -gt 0 ]; do if [ "$1" = y ]; then shift else dep=n shift $# fi done if [ "$dep" = y ]; then bool "$ques" "$var" else define_bool "$var" n fi } function dep_mbool () { ques="$1" var="$2" dep=y shift 2 while [ $# -gt 0 ]; do if [ "$1" = y -o "$1" = m ]; then shift else dep=n shift $# fi done if [ "$dep" = y ]; then bool "$ques" "$var" else define_bool "$var" n fi } # # Add a menu item which will call our local int function. # function int () { set_x_info "$2" "$3" echo -ne "'$2' '($x) $1$info' " >>MCmenu echo -e "function $2 () { l_int '$1' '$2' '$3' '$x' ;}" >>MCradiolists } # # Add a menu item which will call our local hex function. # function hex () { set_x_info "$2" "$3" x=${x##*[x,X]} echo -ne "'$2' '($x) $1$info' " >>MCmenu echo -e "function $2 () { l_hex '$1' '$2' '$3' '$x' ;}" >>MCradiolists } # # Add a menu item which will call our local string function. # function string () { set_x_info "$2" "$3" echo -ne "'$2' ' $1: \"$x\"$info' " >>MCmenu echo -e "function $2 () { l_string '$1' '$2' '$3' '$x' ;}" >>MCradiolists } function mystring () { set_x_info "$2" "$3" echo -ne "'$2' ' $1: \"$x\"$info' " >>MCmenu echo -e "function $2 () { l_string '$1' '$2' '$3' '$x' ;}" >>MCradiolists } # # Add a menu item which will call our local One-of-Many choice list. # function choice () { # # Need to remember params cause they're gonna get reset. # title=$1 choices=$2 default=$3 current= # # Find out if one of the choices is already set. # If it's not then make it the default. # set -- $choices firstchoice=$2 while [ -n "$2" ] do if eval [ \"_\$$2\" = \"_y\" ] then current=$1 break fi shift ; shift done : ${current:=$default} echo -ne "'$firstchoice' '($current) $title' " >>MCmenu echo -e " function $firstchoice () \ { l_choice '$title' \"$choices\" \"$current\" ;}" >>MCradiolists } } # END load_functions() function configure_help () { if [ "$CONFIG_HELP_CHN" = "y" ]; then CONFIGURE_HELPFILE=configs/Configure-zh.help else CONFIGURE_HELPFILE=configs/Configure.help fi } # # Extract available help for an option from Configure.help # and send it to standard output. # # Most of this function was borrowed from the original kernel # Configure script. # function extract_help () { configure_help if [ -f $CONFIGURE_HELPFILE ] then #first escape regexp special characters in the argument: var=$(echo "$1"|sed 's/[][\/.^$*]/\\&/g') #now pick out the right help text: text=$(sed -n "/^$var[ ]*\$/,\${ /^$var[ ]*\$/c\\ ${var}:\\ /^#/b /^[^ ]/q s/^ // /]*\\)>/s//\\1/g p }" $CONFIGURE_HELPFILE ) if [ -z "$text" ] then echo "There is no help available for this SkyEye configure option." return 1 else echo "$text" fi else echo "There is no help available for this SkyEye configure option." return 1 fi } # # Activate a help dialog. # function help () { if extract_help $1 >help.out then $DIALOG --backtitle "$backtitle" --title "$2"\ --textbox help.out $ROWS $COLS else $DIALOG --backtitle "$backtitle" \ --textbox help.out $ROWS $COLS fi rm -f help.out } # # Show the README file. # function show_readme () { $DIALOG --backtitle "$backtitle" \ --textbox scripts/README.Menuconfig $ROWS $COLS } # # Begin building the dialog menu command and Initialize the # Radiolist function file. # function menu_name () { echo -ne "$DIALOG --title '$1'\ --backtitle '$backtitle' \ --menu '$menu_instructions' \ $ROWS $COLS $((ROWS-10)) \ '$default' " >MCmenu >MCradiolists } # # Add a submenu option to the menu currently under construction. # function submenu () { echo -ne "'activate_menu $2' '$1 --->' " >>MCmenu } # # Handle a boolean (Yes/No) option. # function l_bool () { if [ -n "$2" ] then case "$2" in y|m) eval $1=y ;; c) eval x=\$$1 case $x in y) eval $1=n ;; n) eval $1=y ;; *) eval $1=y ;; esac ;; *) eval $1=n ;; esac else echo -ne "\007" fi } # # Same as bool() except options are (Module/No) # function mod_bool () { if [ "$CONFIG_MODULES" != "y" ]; then define_bool "$2" "n" else set_x_info "$2" "n" case $x in y|m) flag='M' ;; *) flag=' ' ;; esac echo -ne "'$2' '<$flag> $1$info' " >>MCmenu echo -e "function $2 () { l_mod_bool '$2' \"\$1\" ;}" >>MCradiolists fi } # # Same as l_bool() except options are (Module/No) # function l_mod_bool() { if [ -n "$2" ] then case "$2" in y) echo -en "\007" ${DIALOG} --backtitle "$backtitle" \ --infobox "\ This feature depends on another which has been configured as a module. \ As a result, this feature will be built as a module." 4 70 sleep 5 eval $1=m ;; m) eval $1=m ;; c) eval x=\$$1 case $x in m) eval $1=n ;; n) eval $1=m ;; *) eval $1=m ;; esac ;; *) eval $1=n ;; esac else echo -ne "\007" fi } # # Handle a tristate (Yes/No/Module) option. # function l_tristate () { if [ -n "$2" ] then eval x=\$$1 case "$2" in y) eval $1=y ;; m) eval $1=m ;; c) eval x=\$$1 case $x in y) eval $1=n ;; n) eval $1=m ;; m) eval $1=y ;; *) eval $1=y ;; esac ;; *) eval $1=n ;; esac else echo -ne "\007" fi } # # Create a dialog for entering an integer into a option. # function l_int () { while true do if $DIALOG --title "$1" \ --backtitle "$backtitle" \ --inputbox "$inputbox_instructions_int" \ 10 75 "$4" 2>MCdialog.out then answer="`cat MCdialog.out`" answer="${answer:-$3}" # Semantics of + and ? in GNU expr changed, so # we avoid them: if expr "$answer" : '0$' '|' "$answer" : '[1-9][0-9]*$' '|' "$answer" : '-[1-9][0-9]*$' >/dev/null then eval $2=\"$answer\" else eval $2=\"$3\" echo -en "\007" ${DIALOG} --backtitle "$backtitle" \ --infobox "You have made an invalid entry." 3 43 sleep 2 fi break fi help "$2" "$1" done } # # Create a dialog for entering a hexadecimal into a option. # function l_hex () { while true do if $DIALOG --title "$1" \ --backtitle "$backtitle" \ --inputbox "$inputbox_instructions_hex" \ 10 75 "$4" 2>MCdialog.out then answer="`cat MCdialog.out`" answer="${answer:-$3}" answer="${answer##*[x,X]}" if expr "$answer" : '[0-9a-fA-F][0-9a-fA-F]*$' >/dev/null then eval $2=\"$answer\" else eval $2=\"$3\" echo -en "\007" ${DIALOG} --backtitle "$backtitle" \ --infobox "You have made an invalid entry." 3 43 sleep 2 fi break fi help "$2" "$1" done } # # Create a dialog for entering a string into a option. # function l_string () { while true do if $DIALOG --title "$1" \ --backtitle "$backtitle" \ --inputbox "$inputbox_instructions_string" \ 10 75 "$4" 2>MCdialog.out then answer="`cat MCdialog.out`" answer="${answer:-$3}" # # Someone may add a nice check for the entered # string here... # eval $2=\"$answer\" break fi help "$2" "$1" done } # # Handle a one-of-many choice list. # function l_choice () { # # Need to remember params cause they're gonna get reset. # title="$1" choices="$2" current="$3" chosen= # # Scan current value of choices and set radiolist switches. # list= set -- $choices firstchoice=$2 while [ -n "$2" ] do case "$1" in "$current"*) if [ -z "$chosen" ]; then list="$list $2 $1 ON " chosen=1 else list="$list $2 $1 OFF " fi ;; *) list="$list $2 $1 OFF " ;; esac shift ; shift done while true do if $DIALOG --title "$title" \ --backtitle "$backtitle" \ --radiolist "$radiolist_instructions" \ 15 70 6 $list 2>MCdialog.out then choice=`cat MCdialog.out` break fi help "$firstchoice" "$title" done # # Now set the boolean value of each option based on # the selection made from the radiolist. # set -- $choices while [ -n "$2" ] do if [ "$2" = "$choice" ] then eval $2=\"y\" else eval $2=\"n\" fi shift ; shift done } # # Call awk, and watch for error codes, etc. # function callawk () { awk "$1" || { echo "Awk died with error code $?. Giving up."; exit 1; } } # # A faster awk based recursive parser. (I hope) # function parser1 () { callawk ' BEGIN { menu_no = 0 comment_is_option = 0 parser("'$CONFIG_IN'","MCmenu0") } function parser(ifile,menu) { while (getline >menu newmenu = sprintf("MCmenu%d", menu_no); printf( "function MCmenu%s () {\n"\ "default=$1\n"\ "menu_name %s\n",\ menu_no, $0) >newmenu parser(ifile, newmenu) } else if ($0 ~ /^#|\$MAKE|mainmenu_name/) { printf("") >>menu } else if ($1 ~ "endmenu") { printf("}\n") >>menu return } else if ($1 == "source") { parser($2,menu) } else { print >>menu } } }' } # # Secondary parser for single menu mode. # function parser2 () { callawk ' BEGIN { parser("'$CONFIG_IN'","MCmenu0") } function parser(ifile,menu) { while (getline >menu } else if ($1 ~ /mainmenu_option|endmenu/) { printf("") >>menu } else if ($1 == "source") { parser($2,menu) } else { print >>menu } } }' } # # Parse all the config.in files into mini scripts. # function parse_config_files () { rm -f MCmenu* echo "function MCmenu0 () {" >MCmenu0 echo 'default=$1' >>MCmenu0 echo "menu_name 'Main Menu'" >>MCmenu0 if [ "_$single_menu_mode" = "_TRUE" ] then parser2 else parser1 fi echo "comment ''" >>MCmenu0 echo "g_alt_config" >>MCmenu0 echo "s_alt_config" >>MCmenu0 echo "}" >>MCmenu0 # # These mini scripts must be sourced into the current # environment in order for all of this to work. Leaving # them on the disk as executables screws up the recursion # in activate_menu(), among other things. Once they are # sourced we can discard them. # for i in MCmenu* do echo -n "." source ./$i done rm -f MCmenu* } # # This is the menu tree's bootstrap. # # Executes the parsed menus on demand and creates a set of functions, # one per configuration option. These functions will in turn execute # dialog commands or recursively call other menus. # function activate_menu () { rm -f lxdialog.scrltmp while true do comment_ctr=0 #So comment lines get unique tags $1 "$default" 2> MCerror #Create the lxdialog menu & functions if [ "$?" != "0" ] then clear cat < /' MCerror cat <. You may also send a problem report to . Please indicate the kernel version you are trying to configure and which menu you were trying to enter when this error occurred. EOM cleanup exit 1 fi rm -f MCerror . ./MCradiolists #Source the menu's functions . ./MCmenu 2>MCdialog.out #Activate the lxdialog menu ret=$? read selection "*|*"alt_config"*) show_readme ;; *) eval help $selection ;; esac ;; 255|1) break ;; 139) stty sane clear cat < or post a message to for additional assistance. EOM cleanup exit 139 ;; esac done } # # Create a menu item to load an alternate configuration file. # g_alt_config () { echo -n "get_alt_config 'Load an Alternate Configuration File' "\ >>MCmenu } # # Get alternate config file name and load the # configuration from it. # get_alt_config () { set -f ## Switch file expansion OFF while true do ALT_CONFIG="${ALT_CONFIG:-$DEFAULTS}" $DIALOG --backtitle "$backtitle" \ --inputbox "\ Enter the name of the configuration file you wish to load. \ Accept the name shown to restore the configuration you \ last retrieved. Leave blank to abort."\ 11 55 "$ALT_CONFIG" 2>MCdialog.out if [ "$?" = "0" ] then ALT_CONFIG=`cat MCdialog.out` [ "_" = "_$ALT_CONFIG" ] && break if eval [ -r \"$ALT_CONFIG\" ] then eval load_config_file \"$ALT_CONFIG\" break else echo -ne "\007" $DIALOG --backtitle "$backtitle" \ --infobox "File does not exist!" 3 38 sleep 2 fi else cat <help.out For various reasons, one may wish to keep several different SkyEye configurations available on a single machine. If you have saved a previous configuration in a file other than the kernel's default, entering the name of the file here will allow you to modify that configuration. If you are uncertain, then you have probably never used alternate configuration files. You should therefor leave this blank to abort. EOM $DIALOG --backtitle "$backtitle"\ --title "Load Alternate Configuration"\ --textbox help.out $ROWS $COLS fi done set +f ## Switch file expansion ON rm -f help.out MCdialog.out } # # Create a menu item to store an alternate config file. # s_alt_config () { echo -n "save_alt_config 'Save Configuration to an Alternate File' "\ >>MCmenu } # # Get an alternate config file name and save the current # configuration to it. # save_alt_config () { set -f ## Switch file expansion OFF while true do $DIALOG --backtitle "$backtitle" \ --inputbox "\ Enter a filename to which this configuration should be saved \ as an alternate. Leave blank to abort."\ 10 55 "$ALT_CONFIG" 2>MCdialog.out if [ "$?" = "0" ] then ALT_CONFIG=`cat MCdialog.out` [ "_" = "_$ALT_CONFIG" ] && break if eval touch $ALT_CONFIG 2>/dev/null then eval save_configuration $ALT_CONFIG load_functions ## RELOAD break else echo -ne "\007" $DIALOG --backtitle "$backtitle" \ --infobox "Can't create file! Probably a nonexistent directory." 3 60 sleep 2 fi else cat <help.out For various reasons, one may wish to keep different kernel configurations available on a single machine. Entering a file name here will allow you to later retrieve, modify and use the current configuration as an alternate to whatever configuration options you have selected at that time. If you are uncertain what all this means then you should probably leave this blank. EOM $DIALOG --backtitle "$backtitle"\ --title "Save Alternate Configuration"\ --textbox help.out $ROWS $COLS fi done set +f ## Switch file expansion ON rm -f help.out MCdialog.out } # # Load config options from a file. # Converts all "# OPTION is not set" lines to "OPTION=n" lines # function load_config_file () { awk ' /# .* is not set.*/ { printf("%s=n\n", $2) } ! /# .* is not set.*/ { print } ' $1 >.tmpconfig source ./.tmpconfig rm -f .tmpconfig } # # Just what it says. # save_configuration () { echo echo -n "Saving your SkyEye configuration." # # Now, let's redefine the configuration functions for final # output to the config files. # # Nested function definitions, YIPEE! # function bool () { set_x_info "$2" "n" eval define_bool \"$2\" \"$x\" } function tristate () { set_x_info "$2" "n" eval define_tristate \"$2\" \"$x\" } function dep_tristate () { set_x_info "$2" "n" var="$2" shift 2 while [ $# -gt 0 ]; do if [ "$1" = y ]; then shift elif [ "$1" = m -a "$x" != n ]; then x=m; shift else x=n; shift $# fi done define_tristate "$var" "$x" } function dep_bool () { set_x_info "$2" "n" var="$2" shift 2 while [ $# -gt 0 ]; do if [ "$1" = y ]; then shift else x=n; shift $# fi done define_bool "$var" "$x" } function dep_mbool () { set_x_info "$2" "n" var="$2" shift 2 while [ $# -gt 0 ]; do if [ "$1" = y -o "$1" = m ]; then shift else x=n; shift $# fi done define_bool "$var" "$x" } function int () { set_x_info "$2" "$3" echo "$2=$x" >>$CONFIG echo "#define $2 ($x)" >>$CONFIG_H } function hex () { set_x_info "$2" "$3" echo "$2=$x" >>$CONFIG echo "#define $2 0x${x##*[x,X]}" >>$CONFIG_H } function string () { set_x_info "$2" "$3" echo "$2=\"$x\"" >>$CONFIG echo "#define $2 \"$x\"" >>$CONFIG_H } function mystring () { set_x_info "$2" "$3" echo "$2=$x" >>$CONFIG echo "#define $2 $x" >>$CONFIG_H } function define_hex () { eval $1=\"$2\" echo "$1=$2" >>$CONFIG echo "#define $1 0x${2##*[x,X]}" >>$CONFIG_H } function define_int () { eval $1=\"$2\" echo "$1=$2" >>$CONFIG echo "#define $1 ($2)" >>$CONFIG_H } function define_string () { eval $1=\"$2\" echo "$1=\"$2\"" >>$CONFIG echo "#define $1 \"$2\"" >>$CONFIG_H } function define_mystring () { eval $1=$2 echo "$1=$2" >>$CONFIG echo "#define $1 $2" >>$CONFIG_H } function define_mystring_null () { eval $1=$2 } function define_bool () { define_tristate "$1" "$2" } function define_tristate () { eval $1=\"$2\" case "$2" in y) echo "$1=y" >>$CONFIG echo "#define $1 1" >>$CONFIG_H ;; m) if [ "$CONFIG_MODULES" = "y" ] then echo "$1=m" >>$CONFIG echo "#undef $1" >>$CONFIG_H echo "#define $1_MODULE 1" >>$CONFIG_H else echo "$1=y" >>$CONFIG echo "#define $1 1" >>$CONFIG_H fi ;; n) echo "$1=n" >>$CONFIG echo "#undef $1" >>$CONFIG_H ;; esac } function choice () { # # Find the first choice that's already set to 'y' # choices="$2" default="$3" current= chosen= set -- $choices while [ -n "$2" ] do if eval [ \"_\$$2\" = \"_y\" ] then current=$1 break fi shift ; shift done # # Use the default if none were set. # : ${current:=$default} # # Output all choices (to be compatible with other configs). # set -- $choices while [ -n "$2" ] do case "$1" in "$current"*) if [ -z "$chosen" ]; then define_bool "$2" "y" chosen=1 else define_bool "$2" "n" fi ;; *) define_bool "$2" "n" ;; esac shift ; shift done } function mainmenu_name () { : } function mainmenu_option () { comment_is_option=TRUE } function endmenu () { : } function comment () { if [ "$comment_is_option" ] then comment_is_option= echo >>$CONFIG echo "#" >>$CONFIG echo "# $1" >>$CONFIG echo "#" >>$CONFIG echo >>$CONFIG_H echo "/*" >>$CONFIG_H echo " * $1" >>$CONFIG_H echo " */" >>$CONFIG_H fi } echo -n "." DEF_CONFIG="${1:-.config}" DEF_CONFIG_H="autoconf.h" CONFIG=.tmpconfig CONFIG_H=.tmpconfig.h echo "#" >$CONFIG echo "# Automatically generated by make menuconfig: don't edit" >>$CONFIG echo "#" >>$CONFIG echo "/*" >$CONFIG_H echo " * Automatically generated by make menuconfig: don't edit" >>$CONFIG_H echo " */" >>$CONFIG_H echo "#define AUTOCONF_INCLUDED" >> $CONFIG_H echo -n "." if . $CONFIG_IN >>.menuconfig.log 2>&1 then if [ -f "$DEF_CONFIG" ] then rm -f ${DEF_CONFIG}.old mv $DEF_CONFIG ${DEF_CONFIG}.old fi mv $CONFIG $DEF_CONFIG return 0 else return 1 fi } # # Remove temporary files # cleanup () { cleanup1 cleanup2 } cleanup1 () { rm -f MCmenu* MCradiolists MCdialog.out help.out } cleanup2 () { rm -f .tmpconfig .tmpconfig.h } set_geometry () { # Some distributions export these with incorrect values # which can really screw up some ncurses programs. LINES= COLUMNS= ROWS=${1:-24} COLS=${2:-80} # Just in case the nasty rlogin bug returns. # [ $ROWS = 0 ] && ROWS=24 [ $COLS = 0 ] && COLS=80 if [ $ROWS -lt 19 -o $COLS -lt 80 ] then echo -e "\n\007Your display is too small to run Menuconfig!" echo "It must be at least 19 lines by 80 columns." exit 1 fi ROWS=$((ROWS-4)) COLS=$((COLS-5)) } set_geometry `stty size 2>/dev/null` menu_instructions="\ Arrow keys navigate the menu. \ selects submenus --->. \ Highlighted letters are hotkeys. \ Pressing includes, excludes. \ Press to exit, for Help. \ Legend: [*] included [ ] excluded" radiolist_instructions="\ Use the arrow keys to navigate this window or \ press the hotkey of the item you wish to select \ followed by the . Press for additional information about this option." inputbox_instructions_int="\ Please enter a decimal value. \ Fractions will not be accepted. \ Use the key to move from the input field to the buttons below it." inputbox_instructions_hex="\ Please enter a hexadecimal value. \ Use the key to move from the input field to the buttons below it." inputbox_instructions_string="\ Please enter a string value. \ Use the key to move from the input field to the buttons below it." DIALOG="./scripts/lxdialog/lxdialog" minigui_version="${MAJOR_VERSION}.${MINOR_VERSION}.${MICRO_VERSION}${EXTRAVERSION}" backtitle="SkyEye v$minigui_version Configuration" trap "cleanup ; exit 1" 1 2 15 # # Locate default files. # CONFIG_IN=./config.in if [ "$1" != "" ] ; then CONFIG_IN=$1 fi DEFAULTS=configs/defconfig if [ -f .config ]; then DEFAULTS=.config fi if [ -f .defconfig ]; then DEFAULTS=.defconfig fi if [ -f $DEFAULTS ] then echo "Using defaults found in" $DEFAULTS load_config_file $DEFAULTS else echo "No defaults found" fi # Fresh new log. >.menuconfig.log # Load the functions used by the config.in files. echo -n "Preparing scripts: functions" load_functions if [ ! -e $CONFIG_IN ] then echo "Your main config.in file ($CONFIG_IN) does not exist" exit 1 fi if [ ! -x $DIALOG ] then echo "Your lxdialog utility does not exist" exit 1 fi # # Read config.in files and parse them into one shell function per menu. # echo -n ", parsing" parse_config_files $CONFIG_IN echo "done." # # Start the ball rolling from the top. # activate_menu MCmenu0 # # All done! # cleanup1 # # Confirm and Save # if $DIALOG --backtitle "$backtitle" \ --yesno "Do you wish to save your new SkyEye configuration?" 5 60 then save_configuration scripts/mkconfig #./config-mnu #rm config-mnu echo echo echo else echo echo echo Your SkyEye configuration changes were NOT saved. echo fi # Remove log if empty. if [ ! -s .menuconfig.log ] ; then rm -f .menuconfig.log fi exit 0 skyeye-1.2.5_REL/misc/conf/scripts/Makefile.in0000644000175000001440000002446711023514464017667 0ustar kshusers# Makefile.in generated by automake 1.6.3 from Makefile.am. # @configure_input@ # Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 # Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ SHELL = @SHELL@ srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ prefix = @prefix@ exec_prefix = @exec_prefix@ bindir = @bindir@ sbindir = @sbindir@ libexecdir = @libexecdir@ datadir = @datadir@ sysconfdir = @sysconfdir@ sharedstatedir = @sharedstatedir@ localstatedir = @localstatedir@ libdir = @libdir@ infodir = @infodir@ mandir = @mandir@ includedir = @includedir@ oldincludedir = /usr/include pkgdatadir = $(datadir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ top_builddir = .. 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MNU_CONFIG=.config FEATURE_IN=configs/feature.in CONFIG_MNU=skyeye.conf prefix=/usr/local CC=gcc TARGET=i386-linux HOST=i386-linux CFLAGS= LDFLAGS= CONFIGURE_HELP=.config_help #if [ ! -f configure ]; then # echo "configure not exist, execute autogen to make it" # ./autogen.sh #fi #./configure --help > $CONFIGURE_HELP #echo "#!/bin/sh" > $CONFIG_MNU #echo "# Automatically generated by make menuconfig." >> $CONFIG_MNU #echo >> $CONFIG_MNU #echo "rm config.cache config.status -f" >> $CONFIG_MNU #echo >> $CONFIG_MNU SAVEIFS=$IFS IFS== function check_def_yes () { if grep "$1" $CONFIGURE_HELP | grep "" > /dev/null; then return 0 else return -1 fi } function check_def_no () { if grep "$1" $CONFIGURE_HELP | grep "" > /dev/null; then return 0 else return -1 fi } function check_exist () { if grep "$1" $MNU_CONFIG > /dev/null; then return 0 else return -1 fi } function check_value () { if [ -s $MNU_CONFIG ]; then while read var_config value do if [ "$var_config" = "$1" ]; then if [ "$value" = "y" ]; then return 0 else return -1 fi fi done < $MNU_CONFIG return -1 fi } function get_value () { if [ -s $2 ]; then while read var_config nowvalue do if [ "$var_config" = "$1" ]; then return 0 fi done < $2 return -1 fi } function get_mnu_value () { if get_value $1 $MNU_CONFIG; then return 0 else return -1 fi } if get_mnu_value "PREFIX"; then echo "" prefix=$nowvalue echo "install prefix = $prefix" fi if get_mnu_value "CC"; then CC=$nowvalue echo "compiler = $CC" fi if get_mnu_value "TARGET"; then TARGET=$nowvalue echo "target = $TARGET" fi if get_mnu_value "HOST"; then HOST=$nowvalue echo "host = $HOST" fi # set CFLAGS and LDFLAGS for uClinux # ----------------------------------------------------------------- if check_value "CONFIG_PLATFORM_UCLINUX"; then CFLAGS="-Os -D__uClinux__ -fno-builtin" if get_mnu_value "UC_KERNEL_HEADER"; then CFLAGS="$CFLAGS -I$nowvalue" fi if get_mnu_value "UCLIBC_HEADER"; then CFLAGS="$CFLAGS -I$nowvalue -I$nowvalue/../" fi LDFLAGS="-Wl,-elf2flt -Wl,-move-rodata" if get_mnu_value "UCLIBC_LIB"; then LDFLAGS="$LDFLAGS -L$nowvalue -L$nowvalue/../" fi if check_value "CONFIG_COMPILER_M68K_ELF"; then if check_value "CONFIG_TARGET_M68K_XCOPILOT"; then CFLAGS="$CFLAGS -m68000 -mid-shared-library -mshared-library-id=0" LDFLAGS="$LDFLAGS -Wl,-shared-lib-id,0" fi if check_value "CONFIG_TARGET_M68K_68EZ328"; then CFLAGS="$CFLAGS -m68000 -mid-shared-library -mshared-library-id=0" LDFLAGS="$LDFLAGS -Wl,-shared-lib-id,0" fi if check_value "CONFIG_TARGET_M68K_CF5200"; then CFLAGS="$CFLAGS -m5200 -Wa,-S -Wa,-m5200 -msep-data" fi if check_value "CONFIG_TARGET_M68K_CF5307"; then CFLAGS="$CFLAGS -m5307 -Wa,-S -Wa,-m5307 -msep-data" fi if get_mnu_value "UCLIBC_LIB"; then LDFLAGS="$LDFLAGS -Wl,-R,$nowvalue/../libc.gdb" fi fi if check_value "CONFIG_COMPILER_ARM_ELF"; then CFLAGS="$CFLAGS -D__PIC__ -fpic -msingle-pic-base" fi LDFLAGS="$LDFLAGS -lc" echo "CFLAGS = $CFLAGS" echo "LDFLAGS = $LDFLAGS" fi # uClinux ----------------------------------------------------------- echo "CC=$CC \\" >> $CONFIG_MNU echo "CFLAGS=\"$CFLAGS\" \\" >> $CONFIG_MNU echo "LDFLAGS=\"$LDFLAGS\" \\" >> $CONFIG_MNU echo "./configure \\" >> $CONFIG_MNU echo " --prefix=$prefix \\" >> $CONFIG_MNU echo " --target=$TARGET \\" >> $CONFIG_MNU echo " --host=$HOST \\" >> $CONFIG_MNU if check_value "CONFIG_NO_SHARE"; then echo " --disable-shared \\" >> $CONFIG_MNU fi if [ -s $FEATURE_IN ]; then while read var_config feature do if [ "$feature" != "" ]; then if check_exist $var_config; then if check_value $var_config; then if check_def_no $feature; then echo " --enable-$feature \\" >> $CONFIG_MNU fi else if check_def_yes $feature; then echo " --disable-$feature \\" >> $CONFIG_MNU fi fi fi fi done < $FEATURE_IN fi echo " --build=i386-linux" >> $CONFIG_MNU #rm $CONFIGURE_HELP chmod +x $CONFIG_MNU IFS=$SAVEIFS skyeye-1.2.5_REL/misc/conf/scripts/Makefile.am0000644000175000001440000000006210541455476017652 0ustar kshusersSUBDIRS=lxdialog EXTRA_DIST=Menuconfig mkconfig skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/0000755000175000001440000000000011023514411017400 5ustar kshusersskyeye-1.2.5_REL/misc/conf/scripts/lxdialog/makefile.lx0000644000175000001440000000217710541455476021554 0ustar kshusersHOSTCFLAGS += -DLOCALE LIBS = -lncurses ifeq (/usr/include/ncurses/ncurses.h, $(wildcard /usr/include/ncurses/ncurses.h)) HOSTCFLAGS += -I/usr/include/ncurses -DCURSES_LOC="" else ifeq (/usr/include/ncurses/curses.h, $(wildcard /usr/include/ncurses/curses.h)) HOSTCFLAGS += -I/usr/include/ncurses -DCURSES_LOC="" else ifeq (/usr/include/ncurses.h, $(wildcard /usr/include/ncurses.h)) HOSTCFLAGS += -DCURSES_LOC="" else HOSTCFLAGS += -DCURSES_LOC="" endif endif endif OBJS = checklist.o menubox.o textbox.o yesno.o inputbox.o \ util.o lxdialog.o msgbox.o %.o: %.c $(HOSTCC) $(HOSTCFLAGS) -c -o $@ $< all: ncurses lxdialog lxdialog: $(OBJS) $(HOSTCC) -o lxdialog $(OBJS) $(LIBS) ncurses: @echo "main() {}" > lxtemp.c @if $(HOSTCC) -lncurses lxtemp.c ; then \ rm -f lxtemp.c a.out; \ else \ rm -f lxtemp.c; \ echo -e "\007" ;\ echo ">> Unable to find the Ncurses libraries." ;\ echo ">>" ;\ echo ">> You must have Ncurses installed in order" ;\ echo ">> to use 'make menuconfig'" ;\ echo ;\ exit 1 ;\ fi clean: rm -f core *.o *~ lxdialog skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/checklist.c0000644000175000001440000002304510541455476021544 0ustar kshusers/* * checklist.c -- implements the checklist box * * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * Stuart Herbert - S.Herbert@sheffield.ac.uk: radiolist extension * Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "dialog.h" static int list_width, check_x, item_x, checkflag; /* * Print list item */ static void print_item (WINDOW * win, const char *item, int status, int choice, int selected) { int i; /* Clear 'residue' of last item */ wattrset (win, menubox_attr); wmove (win, choice, 0); for (i = 0; i < list_width; i++) waddch (win, ' '); wmove (win, choice, check_x); wattrset (win, selected ? check_selected_attr : check_attr); if (checkflag == FLAG_CHECK) wprintw (win, "[%c]", status ? 'X' : ' '); else wprintw (win, "(%c)", status ? 'X' : ' '); wattrset (win, selected ? tag_selected_attr : tag_attr); mvwaddch(win, choice, item_x, item[0]); wattrset (win, selected ? item_selected_attr : item_attr); waddstr (win, (char *)item+1); if (selected) { wmove (win, choice, check_x+1); wrefresh (win); } } /* * Print the scroll indicators. */ static void print_arrows (WINDOW * win, int choice, int item_no, int scroll, int y, int x, int height) { wmove(win, y, x); if (scroll > 0) { wattrset (win, uarrow_attr); waddch (win, ACS_UARROW); waddstr (win, "(-)"); } else { wattrset (win, menubox_attr); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); } y = y + height + 1; wmove(win, y, x); if ((height < item_no) && (scroll + choice < item_no - 1)) { wattrset (win, darrow_attr); waddch (win, ACS_DARROW); waddstr (win, "(+)"); } else { wattrset (win, menubox_border_attr); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); } } /* * Display the termination buttons */ static void print_buttons( WINDOW *dialog, int height, int width, int selected) { int x = width / 2 - 11; int y = height - 2; print_button (dialog, "Select", y, x, selected == 0); print_button (dialog, " Help ", y, x + 14, selected == 1); wmove(dialog, y, x+1 + 14*selected); wrefresh (dialog); } /* * Display a dialog box with a list of options that can be turned on or off * The `flag' parameter is used to select between radiolist and checklist. */ int dialog_checklist (const char *title, const char *prompt, int height, int width, int list_height, int item_no, const char * const * items, int flag) { int i, x, y, box_x, box_y; int key = 0, button = 0, choice = 0, scroll = 0, max_choice, *status; WINDOW *dialog, *list; checkflag = flag; /* Allocate space for storing item on/off status */ if ((status = malloc (sizeof (int) * item_no)) == NULL) { endwin (); fprintf (stderr, "\nCan't allocate memory in dialog_checklist().\n"); exit (-1); } /* Initializes status */ for (i = 0; i < item_no; i++) { status[i] = !strcasecmp (items[i * 3 + 2], "on"); if (!choice && status[i]) choice = i; } max_choice = MIN (list_height, item_no); /* center dialog box on screen */ x = (COLS - width) / 2; y = (LINES - height) / 2; draw_shadow (stdscr, y, x, height, width); dialog = newwin (height, width, y, x); keypad (dialog, TRUE); draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); wattrset (dialog, border_attr); mvwaddch (dialog, height-3, 0, ACS_LTEE); for (i = 0; i < width - 2; i++) waddch (dialog, ACS_HLINE); wattrset (dialog, dialog_attr); waddch (dialog, ACS_RTEE); if (title != NULL && strlen(title) >= width-2 ) { /* truncate long title -- mec */ char * title2 = malloc(width-2+1); memcpy( title2, title, width-2 ); title2[width-2] = '\0'; title = title2; } if (title != NULL) { wattrset (dialog, title_attr); mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); waddstr (dialog, (char *)title); waddch (dialog, ' '); } wattrset (dialog, dialog_attr); print_autowrap (dialog, prompt, width - 2, 1, 3); list_width = width - 6; box_y = height - list_height - 5; box_x = (width - list_width) / 2 - 1; /* create new window for the list */ list = subwin (dialog, list_height, list_width, y+box_y+1, x+box_x+1); keypad (list, TRUE); /* draw a box around the list items */ draw_box (dialog, box_y, box_x, list_height + 2, list_width + 2, menubox_border_attr, menubox_attr); /* Find length of longest item in order to center checklist */ check_x = 0; for (i = 0; i < item_no; i++) check_x = MAX (check_x, + strlen (items[i * 3 + 1]) + 4); check_x = (list_width - check_x) / 2; item_x = check_x + 4; if (choice >= list_height) { scroll = choice - list_height + 1; choice -= scroll; } /* Print the list */ for (i = 0; i < max_choice; i++) { print_item (list, items[(scroll+i) * 3 + 1], status[i+scroll], i, i == choice); } print_arrows(dialog, choice, item_no, scroll, box_y, box_x + check_x + 5, list_height); print_buttons(dialog, height, width, 0); wnoutrefresh (list); wnoutrefresh (dialog); doupdate (); while (key != ESC) { key = wgetch (dialog); for (i = 0; i < max_choice; i++) if (toupper(key) == toupper(items[(scroll+i)*3+1][0])) break; if ( i < max_choice || key == KEY_UP || key == KEY_DOWN || key == '+' || key == '-' ) { if (key == KEY_UP || key == '-') { if (!choice) { if (!scroll) continue; /* Scroll list down */ if (list_height > 1) { /* De-highlight current first item */ print_item (list, items[scroll * 3 + 1], status[scroll], 0, FALSE); scrollok (list, TRUE); wscrl (list, -1); scrollok (list, FALSE); } scroll--; print_item (list, items[scroll * 3 + 1], status[scroll], 0, TRUE); wnoutrefresh (list); print_arrows(dialog, choice, item_no, scroll, box_y, box_x + check_x + 5, list_height); wrefresh (dialog); continue; /* wait for another key press */ } else i = choice - 1; } else if (key == KEY_DOWN || key == '+') { if (choice == max_choice - 1) { if (scroll + choice >= item_no - 1) continue; /* Scroll list up */ if (list_height > 1) { /* De-highlight current last item before scrolling up */ print_item (list, items[(scroll + max_choice - 1) * 3 + 1], status[scroll + max_choice - 1], max_choice - 1, FALSE); scrollok (list, TRUE); scroll (list); scrollok (list, FALSE); } scroll++; print_item (list, items[(scroll + max_choice - 1) * 3 + 1], status[scroll + max_choice - 1], max_choice - 1, TRUE); wnoutrefresh (list); print_arrows(dialog, choice, item_no, scroll, box_y, box_x + check_x + 5, list_height); wrefresh (dialog); continue; /* wait for another key press */ } else i = choice + 1; } if (i != choice) { /* De-highlight current item */ print_item (list, items[(scroll + choice) * 3 + 1], status[scroll + choice], choice, FALSE); /* Highlight new item */ choice = i; print_item (list, items[(scroll + choice) * 3 + 1], status[scroll + choice], choice, TRUE); wnoutrefresh (list); wrefresh (dialog); } continue; /* wait for another key press */ } switch (key) { case 'H': case 'h': case '?': delwin (dialog); free (status); return 1; case TAB: case KEY_LEFT: case KEY_RIGHT: button = ((key == KEY_LEFT ? --button : ++button) < 0) ? 1 : (button > 1 ? 0 : button); print_buttons(dialog, height, width, button); wrefresh (dialog); break; case 'S': case 's': case ' ': case '\n': if (!button) { if (flag == FLAG_CHECK) { status[scroll + choice] = !status[scroll + choice]; wmove (list, choice, check_x); wattrset (list, check_selected_attr); wprintw (list, "[%c]", status[scroll + choice] ? 'X' : ' '); } else { if (!status[scroll + choice]) { for (i = 0; i < item_no; i++) status[i] = 0; status[scroll + choice] = 1; for (i = 0; i < max_choice; i++) print_item (list, items[(scroll + i) * 3 + 1], status[scroll + i], i, i == choice); } } wnoutrefresh (list); wrefresh (dialog); for (i = 0; i < item_no; i++) { if (status[i]) { if (flag == FLAG_CHECK) { fprintf (stderr, "\"%s\" ", items[i * 3]); } else { fprintf (stderr, "%s", items[i * 3]); } } } } delwin (dialog); free (status); return button; case 'X': case 'x': key = ESC; case ESC: break; } /* Now, update everything... */ doupdate (); } delwin (dialog); free (status); return -1; /* ESC pressed */ } skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/textbox.c0000644000175000001440000003634010541455476021272 0ustar kshusers/* * textbox.c -- implements the text box * * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "dialog.h" static void back_lines (int n); static void print_page (WINDOW * win, int height, int width); static void print_line (WINDOW * win, int row, int width); static char *get_line (void); static void print_position (WINDOW * win, int height, int width); static int hscroll = 0, fd, file_size, bytes_read; static int begin_reached = 1, end_reached = 0, page_length; static char *buf, *page; /* * Display text from a file in a dialog box. */ int dialog_textbox (const char *title, const char *file, int height, int width) { int i, x, y, cur_x, cur_y, fpos, key = 0; int passed_end; char search_term[MAX_LEN + 1]; WINDOW *dialog, *text; search_term[0] = '\0'; /* no search term entered yet */ /* Open input file for reading */ if ((fd = open (file, O_RDONLY)) == -1) { endwin (); fprintf (stderr, "\nCan't open input file in dialog_textbox().\n"); exit (-1); } /* Get file size. Actually, 'file_size' is the real file size - 1, since it's only the last byte offset from the beginning */ if ((file_size = lseek (fd, 0, SEEK_END)) == -1) { endwin (); fprintf (stderr, "\nError getting file size in dialog_textbox().\n"); exit (-1); } /* Restore file pointer to beginning of file after getting file size */ if (lseek (fd, 0, SEEK_SET) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in dialog_textbox().\n"); exit (-1); } /* Allocate space for read buffer */ if ((buf = malloc (BUF_SIZE + 1)) == NULL) { endwin (); fprintf (stderr, "\nCan't allocate memory in dialog_textbox().\n"); exit (-1); } if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { endwin (); fprintf (stderr, "\nError reading file in dialog_textbox().\n"); exit (-1); } buf[bytes_read] = '\0'; /* mark end of valid data */ page = buf; /* page is pointer to start of page to be displayed */ /* center dialog box on screen */ x = (COLS - width) / 2; y = (LINES - height) / 2; draw_shadow (stdscr, y, x, height, width); dialog = newwin (height, width, y, x); keypad (dialog, TRUE); /* Create window for text region, used for scrolling text */ text = subwin (dialog, height - 4, width - 2, y + 1, x + 1); wattrset (text, dialog_attr); wbkgdset (text, dialog_attr & A_COLOR); keypad (text, TRUE); /* register the new window, along with its borders */ draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); wattrset (dialog, border_attr); mvwaddch (dialog, height-3, 0, ACS_LTEE); for (i = 0; i < width - 2; i++) waddch (dialog, ACS_HLINE); wattrset (dialog, dialog_attr); wbkgdset (dialog, dialog_attr & A_COLOR); waddch (dialog, ACS_RTEE); if (title != NULL && strlen(title) >= width-2 ) { /* truncate long title -- mec */ char * title2 = malloc(width-2+1); memcpy( title2, title, width-2 ); title2[width-2] = '\0'; title = title2; } if (title != NULL) { wattrset (dialog, title_attr); mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); waddstr (dialog, (char *)title); waddch (dialog, ' '); } print_button (dialog, " Exit ", height - 2, width / 2 - 4, TRUE); wnoutrefresh (dialog); getyx (dialog, cur_y, cur_x); /* Save cursor position */ /* Print first page of text */ attr_clear (text, height - 4, width - 2, dialog_attr); print_page (text, height - 4, width - 2); print_position (dialog, height, width); wmove (dialog, cur_y, cur_x); /* Restore cursor position */ wrefresh (dialog); while ((key != ESC) && (key != '\n')) { key = wgetch (dialog); switch (key) { case 'E': /* Exit */ case 'e': case 'X': case 'x': delwin (dialog); free (buf); close (fd); return 0; case 'g': /* First page */ case KEY_HOME: if (!begin_reached) { begin_reached = 1; /* First page not in buffer? */ if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in dialog_textbox().\n"); exit (-1); } if (fpos > bytes_read) { /* Yes, we have to read it in */ if (lseek (fd, 0, SEEK_SET) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in " "dialog_textbox().\n"); exit (-1); } if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { endwin (); fprintf (stderr, "\nError reading file in dialog_textbox().\n"); exit (-1); } buf[bytes_read] = '\0'; } page = buf; print_page (text, height - 4, width - 2); print_position (dialog, height, width); wmove (dialog, cur_y, cur_x); /* Restore cursor position */ wrefresh (dialog); } break; case 'G': /* Last page */ case KEY_END: end_reached = 1; /* Last page not in buffer? */ if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in dialog_textbox().\n"); exit (-1); } if (fpos < file_size) { /* Yes, we have to read it in */ if (lseek (fd, -BUF_SIZE, SEEK_END) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in dialog_textbox().\n"); exit (-1); } if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { endwin (); fprintf (stderr, "\nError reading file in dialog_textbox().\n"); exit (-1); } buf[bytes_read] = '\0'; } page = buf + bytes_read; back_lines (height - 4); print_page (text, height - 4, width - 2); print_position (dialog, height, width); wmove (dialog, cur_y, cur_x); /* Restore cursor position */ wrefresh (dialog); break; case 'K': /* Previous line */ case 'k': case KEY_UP: if (!begin_reached) { back_lines (page_length + 1); /* We don't call print_page() here but use scrolling to ensure faster screen update. However, 'end_reached' and 'page_length' should still be updated, and 'page' should point to start of next page. This is done by calling get_line() in the following 'for' loop. */ scrollok (text, TRUE); wscrl (text, -1); /* Scroll text region down one line */ scrollok (text, FALSE); page_length = 0; passed_end = 0; for (i = 0; i < height - 4; i++) { if (!i) { /* print first line of page */ print_line (text, 0, width - 2); wnoutrefresh (text); } else /* Called to update 'end_reached' and 'page' */ get_line (); if (!passed_end) page_length++; if (end_reached && !passed_end) passed_end = 1; } print_position (dialog, height, width); wmove (dialog, cur_y, cur_x); /* Restore cursor position */ wrefresh (dialog); } break; case 'B': /* Previous page */ case 'b': case KEY_PPAGE: if (begin_reached) break; back_lines (page_length + height - 4); print_page (text, height - 4, width - 2); print_position (dialog, height, width); wmove (dialog, cur_y, cur_x); wrefresh (dialog); break; case 'J': /* Next line */ case 'j': case KEY_DOWN: if (!end_reached) { begin_reached = 0; scrollok (text, TRUE); scroll (text); /* Scroll text region up one line */ scrollok (text, FALSE); print_line (text, height - 5, width - 2); wnoutrefresh (text); print_position (dialog, height, width); wmove (dialog, cur_y, cur_x); /* Restore cursor position */ wrefresh (dialog); } break; case KEY_NPAGE: /* Next page */ case ' ': if (end_reached) break; begin_reached = 0; print_page (text, height - 4, width - 2); print_position (dialog, height, width); wmove (dialog, cur_y, cur_x); wrefresh (dialog); break; case '0': /* Beginning of line */ case 'H': /* Scroll left */ case 'h': case KEY_LEFT: if (hscroll <= 0) break; if (key == '0') hscroll = 0; else hscroll--; /* Reprint current page to scroll horizontally */ back_lines (page_length); print_page (text, height - 4, width - 2); wmove (dialog, cur_y, cur_x); wrefresh (dialog); break; case 'L': /* Scroll right */ case 'l': case KEY_RIGHT: if (hscroll >= MAX_LEN) break; hscroll++; /* Reprint current page to scroll horizontally */ back_lines (page_length); print_page (text, height - 4, width - 2); wmove (dialog, cur_y, cur_x); wrefresh (dialog); break; case ESC: break; } } delwin (dialog); free (buf); close (fd); return -1; /* ESC pressed */ } /* * Go back 'n' lines in text file. Called by dialog_textbox(). * 'page' will be updated to point to the desired line in 'buf'. */ static void back_lines (int n) { int i, fpos; begin_reached = 0; /* We have to distinguish between end_reached and !end_reached since at end of file, the line is not ended by a '\n'. The code inside 'if' basically does a '--page' to move one character backward so as to skip '\n' of the previous line */ if (!end_reached) { /* Either beginning of buffer or beginning of file reached? */ if (page == buf) { if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in " "back_lines().\n"); exit (-1); } if (fpos > bytes_read) { /* Not beginning of file yet */ /* We've reached beginning of buffer, but not beginning of file yet, so read previous part of file into buffer. Note that we only move backward for BUF_SIZE/2 bytes, but not BUF_SIZE bytes to avoid re-reading again in print_page() later */ /* Really possible to move backward BUF_SIZE/2 bytes? */ if (fpos < BUF_SIZE / 2 + bytes_read) { /* No, move less then */ if (lseek (fd, 0, SEEK_SET) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in " "back_lines().\n"); exit (-1); } page = buf + fpos - bytes_read; } else { /* Move backward BUF_SIZE/2 bytes */ if (lseek (fd, -(BUF_SIZE / 2 + bytes_read), SEEK_CUR) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer " "in back_lines().\n"); exit (-1); } page = buf + BUF_SIZE / 2; } if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { endwin (); fprintf (stderr, "\nError reading file in back_lines().\n"); exit (-1); } buf[bytes_read] = '\0'; } else { /* Beginning of file reached */ begin_reached = 1; return; } } if (*(--page) != '\n') { /* '--page' here */ /* Something's wrong... */ endwin (); fprintf (stderr, "\nInternal error in back_lines().\n"); exit (-1); } } /* Go back 'n' lines */ for (i = 0; i < n; i++) do { if (page == buf) { if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in back_lines().\n"); exit (-1); } if (fpos > bytes_read) { /* Really possible to move backward BUF_SIZE/2 bytes? */ if (fpos < BUF_SIZE / 2 + bytes_read) { /* No, move less then */ if (lseek (fd, 0, SEEK_SET) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer " "in back_lines().\n"); exit (-1); } page = buf + fpos - bytes_read; } else { /* Move backward BUF_SIZE/2 bytes */ if (lseek (fd, -(BUF_SIZE / 2 + bytes_read), SEEK_CUR) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer" " in back_lines().\n"); exit (-1); } page = buf + BUF_SIZE / 2; } if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { endwin (); fprintf (stderr, "\nError reading file in " "back_lines().\n"); exit (-1); } buf[bytes_read] = '\0'; } else { /* Beginning of file reached */ begin_reached = 1; return; } } } while (*(--page) != '\n'); page++; } /* * Print a new page of text. Called by dialog_textbox(). */ static void print_page (WINDOW * win, int height, int width) { int i, passed_end = 0; page_length = 0; for (i = 0; i < height; i++) { print_line (win, i, width); if (!passed_end) page_length++; if (end_reached && !passed_end) passed_end = 1; } wnoutrefresh (win); } /* * Print a new line of text. Called by dialog_textbox() and print_page(). */ static void print_line (WINDOW * win, int row, int width) { int y, x; char *line; line = get_line (); line += MIN (strlen (line), hscroll); /* Scroll horizontally */ wmove (win, row, 0); /* move cursor to correct line */ waddch (win, ' '); waddnstr (win, line, MIN (strlen (line), width - 2)); getyx (win, y, x); /* Clear 'residue' of previous line */ #if OLD_NCURSES { int i; for (i = 0; i < width - x; i++) waddch (win, ' '); } #else wclrtoeol(win); #endif } /* * Return current line of text. Called by dialog_textbox() and print_line(). * 'page' should point to start of current line before calling, and will be * updated to point to start of next line. */ static char * get_line (void) { int i = 0, fpos; static char line[MAX_LEN + 1]; end_reached = 0; while (*page != '\n') { if (*page == '\0') { /* Either end of file or end of buffer reached */ if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in " "get_line().\n"); exit (-1); } if (fpos < file_size) { /* Not end of file yet */ /* We've reached end of buffer, but not end of file yet, so read next part of file into buffer */ if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { endwin (); fprintf (stderr, "\nError reading file in get_line().\n"); exit (-1); } buf[bytes_read] = '\0'; page = buf; } else { if (!end_reached) end_reached = 1; break; } } else if (i < MAX_LEN) line[i++] = *(page++); else { /* Truncate lines longer than MAX_LEN characters */ if (i == MAX_LEN) line[i++] = '\0'; page++; } } if (i <= MAX_LEN) line[i] = '\0'; if (!end_reached) page++; /* move pass '\n' */ return line; } /* * Print current position */ static void print_position (WINDOW * win, int height, int width) { int fpos, percent; if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { endwin (); fprintf (stderr, "\nError moving file pointer in print_position().\n"); exit (-1); } wattrset (win, position_indicator_attr); wbkgdset (win, position_indicator_attr & A_COLOR); percent = !file_size ? 100 : ((fpos - bytes_read + page - buf) * 100) / file_size; wmove (win, height - 3, width - 9); wprintw (win, "(%3d%%)", percent); } skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/Makefile.in0000644000175000001440000001425611023514464021465 0ustar kshusers# Makefile.in generated by automake 1.6.3 from Makefile.am. # @configure_input@ # Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 # Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ SHELL = @SHELL@ srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ prefix = @prefix@ exec_prefix = @exec_prefix@ bindir = @bindir@ sbindir = @sbindir@ libexecdir = @libexecdir@ datadir = @datadir@ sysconfdir = @sysconfdir@ sharedstatedir = @sharedstatedir@ localstatedir = @localstatedir@ libdir = @libdir@ infodir = @infodir@ mandir = @mandir@ includedir = @includedir@ oldincludedir = /usr/include pkgdatadir = $(datadir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ top_builddir = ../.. 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you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "dialog.h" /* * Display a message box. Program will pause and display an "OK" button * if the parameter 'pause' is non-zero. */ int dialog_msgbox (const char *title, const char *prompt, int height, int width, int pause) { int i, x, y, key = 0; WINDOW *dialog; /* center dialog box on screen */ x = (COLS - width) / 2; y = (LINES - height) / 2; draw_shadow (stdscr, y, x, height, width); dialog = newwin (height, width, y, x); keypad (dialog, TRUE); draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); if (title != NULL && strlen(title) >= width-2 ) { /* truncate long title -- mec */ char * title2 = malloc(width-2+1); memcpy( title2, title, width-2 ); title2[width-2] = '\0'; title = title2; } if (title != NULL) { wattrset (dialog, title_attr); mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); waddstr (dialog, (char *)title); waddch (dialog, ' '); } wattrset (dialog, dialog_attr); print_autowrap (dialog, prompt, width - 2, 1, 2); if (pause) { wattrset (dialog, border_attr); mvwaddch (dialog, height - 3, 0, ACS_LTEE); for (i = 0; i < width - 2; i++) waddch (dialog, ACS_HLINE); wattrset (dialog, dialog_attr); waddch (dialog, ACS_RTEE); print_button (dialog, " Ok ", height - 2, width / 2 - 4, TRUE); wrefresh (dialog); while (key != ESC && key != '\n' && key != ' ' && key != 'O' && key != 'o' && key != 'X' && key != 'x') key = wgetch (dialog); } else { key = '\n'; wrefresh (dialog); } delwin (dialog); return key == ESC ? -1 : 0; } skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/inputbox.c0000644000175000001440000001404310541455476021441 0ustar kshusers/* * inputbox.c -- implements the input box * * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "dialog.h" unsigned char dialog_input_result[MAX_LEN + 1]; /* * Print the termination buttons */ static void print_buttons(WINDOW *dialog, int height, int width, int selected) { int x = width / 2 - 11; int y = height - 2; print_button (dialog, " Ok ", y, x, selected==0); print_button (dialog, " Help ", y, x + 14, selected==1); wmove(dialog, y, x+1+14*selected); wrefresh(dialog); } /* * Display a dialog box for inputing a string */ int dialog_inputbox (const char *title, const char *prompt, int height, int width, const char *init) { int i, x, y, box_y, box_x, box_width; int input_x = 0, scroll = 0, key = 0, button = -1; unsigned char *instr = dialog_input_result; WINDOW *dialog; /* center dialog box on screen */ x = (COLS - width) / 2; y = (LINES - height) / 2; draw_shadow (stdscr, y, x, height, width); dialog = newwin (height, width, y, x); keypad (dialog, TRUE); draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); wattrset (dialog, border_attr); mvwaddch (dialog, height-3, 0, ACS_LTEE); for (i = 0; i < width - 2; i++) waddch (dialog, ACS_HLINE); wattrset (dialog, dialog_attr); waddch (dialog, ACS_RTEE); if (title != NULL && strlen(title) >= width-2 ) { /* truncate long title -- mec */ char * title2 = malloc(width-2+1); memcpy( title2, title, width-2 ); title2[width-2] = '\0'; title = title2; } if (title != NULL) { wattrset (dialog, title_attr); mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); waddstr (dialog, (char *)title); waddch (dialog, ' '); } wattrset (dialog, dialog_attr); print_autowrap (dialog, prompt, width - 2, 1, 3); /* Draw the input field box */ box_width = width - 6; getyx (dialog, y, x); box_y = y + 2; box_x = (width - box_width) / 2; draw_box (dialog, y + 1, box_x - 1, 3, box_width + 2, border_attr, dialog_attr); print_buttons(dialog, height, width, 0); /* Set up the initial value */ wmove (dialog, box_y, box_x); wattrset (dialog, inputbox_attr); if (!init) instr[0] = '\0'; else strcpy (instr, init); input_x = strlen (instr); if (input_x >= box_width) { scroll = input_x - box_width + 1; input_x = box_width - 1; for (i = 0; i < box_width - 1; i++) waddch (dialog, instr[scroll + i]); } else waddstr (dialog, instr); wmove (dialog, box_y, box_x + input_x); wrefresh (dialog); while (key != ESC) { key = wgetch (dialog); if (button == -1) { /* Input box selected */ switch (key) { case TAB: case KEY_UP: case KEY_DOWN: break; case KEY_LEFT: continue; case KEY_RIGHT: continue; case KEY_BACKSPACE: case 127: if (input_x || scroll) { wattrset (dialog, inputbox_attr); if (!input_x) { scroll = scroll < box_width - 1 ? 0 : scroll - (box_width - 1); wmove (dialog, box_y, box_x); for (i = 0; i < box_width; i++) waddch (dialog, instr[scroll + input_x + i] ? instr[scroll + input_x + i] : ' '); input_x = strlen (instr) - scroll; } else input_x--; instr[scroll + input_x] = '\0'; mvwaddch (dialog, box_y, input_x + box_x, ' '); wmove (dialog, box_y, input_x + box_x); wrefresh (dialog); } continue; default: if (key < 0x100 && isprint (key)) { if (scroll + input_x < MAX_LEN) { wattrset (dialog, inputbox_attr); instr[scroll + input_x] = key; instr[scroll + input_x + 1] = '\0'; if (input_x == box_width - 1) { scroll++; wmove (dialog, box_y, box_x); for (i = 0; i < box_width - 1; i++) waddch (dialog, instr[scroll + i]); } else { wmove (dialog, box_y, input_x++ + box_x); waddch (dialog, key); } wrefresh (dialog); } else flash (); /* Alarm user about overflow */ continue; } } } switch (key) { case 'O': case 'o': delwin (dialog); return 0; case 'H': case 'h': delwin (dialog); return 1; case KEY_UP: case KEY_LEFT: switch (button) { case -1: button = 1; /* Indicates "Cancel" button is selected */ print_buttons(dialog, height, width, 1); break; case 0: button = -1; /* Indicates input box is selected */ print_buttons(dialog, height, width, 0); wmove (dialog, box_y, box_x + input_x); wrefresh (dialog); break; case 1: button = 0; /* Indicates "OK" button is selected */ print_buttons(dialog, height, width, 0); break; } break; case TAB: case KEY_DOWN: case KEY_RIGHT: switch (button) { case -1: button = 0; /* Indicates "OK" button is selected */ print_buttons(dialog, height, width, 0); break; case 0: button = 1; /* Indicates "Cancel" button is selected */ print_buttons(dialog, height, width, 1); break; case 1: button = -1; /* Indicates input box is selected */ print_buttons(dialog, height, width, 0); wmove (dialog, box_y, box_x + input_x); wrefresh (dialog); break; } break; case ' ': case '\n': delwin (dialog); return (button == -1 ? 0 : button); case 'X': case 'x': key = ESC; case ESC: break; } } delwin (dialog); return -1; /* ESC pressed */ } skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/util.c0000644000175000001440000002260410541455476020550 0ustar kshusers/* * util.c * * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "dialog.h" /* use colors by default? */ bool use_colors = 1; const char *backtitle = NULL; const char *dialog_result; /* * Attribute values, default is for mono display */ chtype attributes[] = { A_NORMAL, /* screen_attr */ A_NORMAL, /* shadow_attr */ A_NORMAL, /* dialog_attr */ A_BOLD, /* title_attr */ A_NORMAL, /* border_attr */ A_REVERSE, /* button_active_attr */ A_DIM, /* button_inactive_attr */ A_REVERSE, /* button_key_active_attr */ A_BOLD, /* button_key_inactive_attr */ A_REVERSE, /* button_label_active_attr */ A_NORMAL, /* button_label_inactive_attr */ A_NORMAL, /* inputbox_attr */ A_NORMAL, /* inputbox_border_attr */ A_NORMAL, /* searchbox_attr */ A_BOLD, /* searchbox_title_attr */ A_NORMAL, /* searchbox_border_attr */ A_BOLD, /* position_indicator_attr */ A_NORMAL, /* menubox_attr */ A_NORMAL, /* menubox_border_attr */ A_NORMAL, /* item_attr */ A_REVERSE, /* item_selected_attr */ A_BOLD, /* tag_attr */ A_REVERSE, /* tag_selected_attr */ A_BOLD, /* tag_key_attr */ A_REVERSE, /* tag_key_selected_attr */ A_BOLD, /* check_attr */ A_REVERSE, /* check_selected_attr */ A_BOLD, /* uarrow_attr */ A_BOLD /* darrow_attr */ }; #include "colors.h" /* * Table of color values */ int color_table[][3] = { {SCREEN_FG, SCREEN_BG, SCREEN_HL}, {SHADOW_FG, SHADOW_BG, SHADOW_HL}, {DIALOG_FG, DIALOG_BG, DIALOG_HL}, {TITLE_FG, TITLE_BG, TITLE_HL}, {BORDER_FG, BORDER_BG, BORDER_HL}, {BUTTON_ACTIVE_FG, BUTTON_ACTIVE_BG, BUTTON_ACTIVE_HL}, {BUTTON_INACTIVE_FG, BUTTON_INACTIVE_BG, BUTTON_INACTIVE_HL}, {BUTTON_KEY_ACTIVE_FG, BUTTON_KEY_ACTIVE_BG, BUTTON_KEY_ACTIVE_HL}, {BUTTON_KEY_INACTIVE_FG, BUTTON_KEY_INACTIVE_BG, BUTTON_KEY_INACTIVE_HL}, {BUTTON_LABEL_ACTIVE_FG, BUTTON_LABEL_ACTIVE_BG, BUTTON_LABEL_ACTIVE_HL}, {BUTTON_LABEL_INACTIVE_FG, BUTTON_LABEL_INACTIVE_BG, BUTTON_LABEL_INACTIVE_HL}, {INPUTBOX_FG, INPUTBOX_BG, INPUTBOX_HL}, {INPUTBOX_BORDER_FG, INPUTBOX_BORDER_BG, INPUTBOX_BORDER_HL}, {SEARCHBOX_FG, SEARCHBOX_BG, SEARCHBOX_HL}, {SEARCHBOX_TITLE_FG, SEARCHBOX_TITLE_BG, SEARCHBOX_TITLE_HL}, {SEARCHBOX_BORDER_FG, SEARCHBOX_BORDER_BG, SEARCHBOX_BORDER_HL}, {POSITION_INDICATOR_FG, POSITION_INDICATOR_BG, POSITION_INDICATOR_HL}, {MENUBOX_FG, MENUBOX_BG, MENUBOX_HL}, {MENUBOX_BORDER_FG, MENUBOX_BORDER_BG, MENUBOX_BORDER_HL}, {ITEM_FG, ITEM_BG, ITEM_HL}, {ITEM_SELECTED_FG, ITEM_SELECTED_BG, ITEM_SELECTED_HL}, {TAG_FG, TAG_BG, TAG_HL}, {TAG_SELECTED_FG, TAG_SELECTED_BG, TAG_SELECTED_HL}, {TAG_KEY_FG, TAG_KEY_BG, TAG_KEY_HL}, {TAG_KEY_SELECTED_FG, TAG_KEY_SELECTED_BG, TAG_KEY_SELECTED_HL}, {CHECK_FG, CHECK_BG, CHECK_HL}, {CHECK_SELECTED_FG, CHECK_SELECTED_BG, CHECK_SELECTED_HL}, {UARROW_FG, UARROW_BG, UARROW_HL}, {DARROW_FG, DARROW_BG, DARROW_HL}, }; /* color_table */ /* * Set window to attribute 'attr' */ void attr_clear (WINDOW * win, int height, int width, chtype attr) { int i, j; wattrset (win, attr); for (i = 0; i < height; i++) { wmove (win, i, 0); for (j = 0; j < width; j++) waddch (win, ' '); } touchwin (win); } void dialog_clear (void) { attr_clear (stdscr, LINES, COLS, screen_attr); /* Display background title if it exists ... - SLH */ if (backtitle != NULL) { int i; wattrset (stdscr, screen_attr); mvwaddstr (stdscr, 0, 1, (char *)backtitle); wmove (stdscr, 1, 1); for (i = 1; i < COLS - 1; i++) waddch (stdscr, ACS_HLINE); } wnoutrefresh (stdscr); } /* * Do some initialization for dialog */ void init_dialog (void) { initscr (); /* Init curses */ keypad (stdscr, TRUE); cbreak (); noecho (); if (use_colors) /* Set up colors */ color_setup (); dialog_clear (); } /* * Setup for color display */ void color_setup (void) { int i; if (has_colors ()) { /* Terminal supports color? */ start_color (); /* Initialize color pairs */ for (i = 0; i < ATTRIBUTE_COUNT; i++) init_pair (i + 1, color_table[i][0], color_table[i][1]); /* Setup color attributes */ for (i = 0; i < ATTRIBUTE_COUNT; i++) attributes[i] = C_ATTR (color_table[i][2], i + 1); } } /* * End using dialog functions. */ void end_dialog (void) { endwin (); } /* * Print a string of text in a window, automatically wrap around to the * next line if the string is too long to fit on one line. Newline * characters '\n' are replaced by spaces. We start on a new line * if there is no room for at least 4 nonblanks following a double-space. */ void print_autowrap (WINDOW * win, const char *prompt, int width, int y, int x) { int newl, cur_x, cur_y; int i, prompt_len, room, wlen; char tempstr[MAX_LEN + 1], *word, *sp, *sp2; strcpy (tempstr, prompt); prompt_len = strlen(tempstr); /* * Remove newlines */ for(i=0; i room || (newl && wlen < 4 && sp && wlen+1+strlen(sp) > room && (!(sp2 = index(sp, ' ')) || wlen+1+(sp2-sp) > room))) { cur_y++; cur_x = x; } wmove (win, cur_y, cur_x); waddstr (win, word); getyx (win, cur_y, cur_x); cur_x++; if (sp && *sp == ' ') { cur_x++; /* double space */ while (*++sp == ' '); newl = 1; } else newl = 0; word = sp; } } } /* * Print a button */ void print_button (WINDOW * win, const char *label, int y, int x, int selected) { int i, temp; wmove (win, y, x); wattrset (win, selected ? button_active_attr : button_inactive_attr); waddstr (win, "<"); temp = strspn (label, " "); label += temp; wattrset (win, selected ? button_label_active_attr : button_label_inactive_attr); for (i = 0; i < temp; i++) waddch (win, ' '); wattrset (win, selected ? button_key_active_attr : button_key_inactive_attr); waddch (win, label[0]); wattrset (win, selected ? button_label_active_attr : button_label_inactive_attr); waddstr (win, (char *)label + 1); wattrset (win, selected ? button_active_attr : button_inactive_attr); waddstr (win, ">"); wmove (win, y, x + temp + 1); } /* * Draw a rectangular box with line drawing characters */ void draw_box (WINDOW * win, int y, int x, int height, int width, chtype box, chtype border) { int i, j; wattrset (win, 0); for (i = 0; i < height; i++) { wmove (win, y + i, x); for (j = 0; j < width; j++) if (!i && !j) waddch (win, border | ACS_ULCORNER); else if (i == height - 1 && !j) waddch (win, border | ACS_LLCORNER); else if (!i && j == width - 1) waddch (win, box | ACS_URCORNER); else if (i == height - 1 && j == width - 1) waddch (win, box | ACS_LRCORNER); else if (!i) waddch (win, border | ACS_HLINE); else if (i == height - 1) waddch (win, box | ACS_HLINE); else if (!j) waddch (win, border | ACS_VLINE); else if (j == width - 1) waddch (win, box | ACS_VLINE); else waddch (win, box | ' '); } } /* * Draw shadows along the right and bottom edge to give a more 3D look * to the boxes */ void draw_shadow (WINDOW * win, int y, int x, int height, int width) { int i; if (has_colors ()) { /* Whether terminal supports color? */ wattrset (win, shadow_attr); wmove (win, y + height, x + 2); for (i = 0; i < width; i++) waddch (win, winch (win) & A_CHARTEXT); for (i = y + 1; i < y + height + 1; i++) { wmove (win, i, x + width); waddch (win, winch (win) & A_CHARTEXT); waddch (win, winch (win) & A_CHARTEXT); } wnoutrefresh (win); } } /* * Return the position of the first alphabetic character in a string. */ int first_alpha(const char *string, const char *exempt) { int i, in_paren=0, c; for (i = 0; i < strlen(string); i++) { c = tolower(string[i]); if (strchr("<[(", c)) ++in_paren; if (strchr(">])", c)) --in_paren; if ((! in_paren) && isalpha(c) && strchr(exempt, c) == 0) return i; } return 0; } skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/lxdialog.c0000644000175000001440000001360710541455476021401 0ustar kshusers/* * dialog - Display simple dialog boxes from shell scripts * * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "dialog.h" static void Usage (const char *name); typedef int (jumperFn) (const char *title, int argc, const char * const * argv); struct Mode { char *name; int argmin, argmax, argmod; jumperFn *jumper; }; jumperFn j_menu, j_checklist, j_radiolist, j_yesno, j_textbox, j_inputbox; jumperFn j_msgbox, j_infobox; static struct Mode modes[] = { {"--menu", 9, 0, 3, j_menu}, {"--checklist", 9, 0, 3, j_checklist}, {"--radiolist", 9, 0, 3, j_radiolist}, {"--yesno", 5,5,1, j_yesno}, {"--textbox", 5,5,1, j_textbox}, {"--inputbox", 5, 6, 1, j_inputbox}, {"--msgbox", 5, 5, 1, j_msgbox}, {"--infobox", 5, 5, 1, j_infobox}, {NULL, 0, 0, 0, NULL} }; static struct Mode *modePtr; #ifdef LOCALE #include #endif int main (int argc, const char * const * argv) { int offset = 0, clear_screen = 0, end_common_opts = 0, retval; const char *title = NULL; #ifdef LOCALE (void) setlocale (LC_ALL, ""); #endif #ifdef TRACE trace(TRACE_CALLS|TRACE_UPDATE); #endif if (argc < 2) { Usage (argv[0]); exit (-1); } while (offset < argc - 1 && !end_common_opts) { /* Common options */ if (!strcmp (argv[offset + 1], "--title")) { if (argc - offset < 3 || title != NULL) { Usage (argv[0]); exit (-1); } else { title = argv[offset + 2]; offset += 2; } } else if (!strcmp (argv[offset + 1], "--backtitle")) { if (backtitle != NULL) { Usage (argv[0]); exit (-1); } else { backtitle = argv[offset + 2]; offset += 2; } } else if (!strcmp (argv[offset + 1], "--clear")) { if (clear_screen) { /* Hey, "--clear" can't appear twice! */ Usage (argv[0]); exit (-1); } else if (argc == 2) { /* we only want to clear the screen */ init_dialog (); refresh (); /* init_dialog() will clear the screen for us */ end_dialog (); return 0; } else { clear_screen = 1; offset++; } } else /* no more common options */ end_common_opts = 1; } if (argc - 1 == offset) { /* no more options */ Usage (argv[0]); exit (-1); } /* use a table to look for the requested mode, to avoid code duplication */ for (modePtr = modes; modePtr->name; modePtr++) /* look for the mode */ if (!strcmp (argv[offset + 1], modePtr->name)) break; if (!modePtr->name) Usage (argv[0]); if (argc - offset < modePtr->argmin) Usage (argv[0]); if (modePtr->argmax && argc - offset > modePtr->argmax) Usage (argv[0]); init_dialog (); retval = (*(modePtr->jumper)) (title, argc - offset, argv + offset); if (clear_screen) { /* clear screen before exit */ attr_clear (stdscr, LINES, COLS, screen_attr); refresh (); } end_dialog(); exit (retval); } /* * Print program usage */ static void Usage (const char *name) { fprintf (stderr, "\ \ndialog, by Savio Lam (lam836@cs.cuhk.hk).\ \n patched by Stuart Herbert (S.Herbert@shef.ac.uk)\ \n modified/gutted for use as a Linux kernel config tool by \ \n William Roadcap (roadcapw@cfw.com)\ \n\ \n* Display dialog boxes from shell scripts *\ \n\ \nUsage: %s --clear\ \n %s [--title ] [--backtitle <backtitle>] --clear <Box options>\ \n\ \nBox options:\ \n\ \n --menu <text> <height> <width> <menu height> <tag1> <item1>...\ \n --checklist <text> <height> <width> <list height> <tag1> <item1> <status1>...\ \n --radiolist <text> <height> <width> <list height> <tag1> <item1> <status1>...\ \n --textbox <file> <height> <width>\ \n --inputbox <text> <height> <width> [<init>]\ \n --yesno <text> <height> <width>\ \n", name, name); exit (-1); } /* * These are the program jumpers */ int j_menu (const char *t, int ac, const char * const * av) { return dialog_menu (t, av[2], atoi (av[3]), atoi (av[4]), atoi (av[5]), av[6], (ac - 6) / 2, av + 7); } int j_checklist (const char *t, int ac, const char * const * av) { return dialog_checklist (t, av[2], atoi (av[3]), atoi (av[4]), atoi (av[5]), (ac - 6) / 3, av + 6, FLAG_CHECK); } int j_radiolist (const char *t, int ac, const char * const * av) { return dialog_checklist (t, av[2], atoi (av[3]), atoi (av[4]), atoi (av[5]), (ac - 6) / 3, av + 6, FLAG_RADIO); } int j_textbox (const char *t, int ac, const char * const * av) { return dialog_textbox (t, av[2], atoi (av[3]), atoi (av[4])); } int j_yesno (const char *t, int ac, const char * const * av) { return dialog_yesno (t, av[2], atoi (av[3]), atoi (av[4])); } int j_inputbox (const char *t, int ac, const char * const * av) { int ret = dialog_inputbox (t, av[2], atoi (av[3]), atoi (av[4]), ac == 6 ? av[5] : (char *) NULL); if (ret == 0) fprintf(stderr, dialog_input_result); return ret; } int j_msgbox (const char *t, int ac, const char * const * av) { return dialog_msgbox (t, av[2], atoi (av[3]), atoi (av[4]), 1); } int j_infobox (const char *t, int ac, const char * const * av) { return dialog_msgbox (t, av[2], atoi (av[3]), atoi (av[4]), 0); } �������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/dialog.h������������������������������������������������0000644�0001750�0000144�00000013460�10541455476�021037� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������ /* * dialog.h -- common declarations for all dialog modules * * AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <sys/types.h> #include <fcntl.h> #include <unistd.h> #include <ctype.h> #include <stdlib.h> #include <string.h> #include CURSES_LOC /* * Colors in ncurses 1.9.9e do not work properly since foreground and * background colors are OR'd rather than separately masked. This version * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible * with standard curses. The simplest fix (to make this work with standard * curses) uses the wbkgdset() function, not used in the original hack. * Turn it off if we're building with 1.9.9e, since it just confuses things. */ #if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE) #define OLD_NCURSES 1 #undef wbkgdset #define wbkgdset(w,p) /*nothing*/ #else #define OLD_NCURSES 0 #endif #define TR(params) _tracef params #define ESC 27 #define TAB 9 #define MAX_LEN 2048 #define BUF_SIZE (10*1024) #define MIN(x,y) (x < y ? x : y) #define MAX(x,y) (x > y ? x : y) #ifndef ACS_ULCORNER #define ACS_ULCORNER '+' #endif #ifndef ACS_LLCORNER #define ACS_LLCORNER '+' #endif #ifndef ACS_URCORNER #define ACS_URCORNER '+' #endif #ifndef ACS_LRCORNER #define ACS_LRCORNER '+' #endif #ifndef ACS_HLINE #define ACS_HLINE '-' #endif #ifndef ACS_VLINE #define ACS_VLINE '|' #endif #ifndef ACS_LTEE #define ACS_LTEE '+' #endif #ifndef ACS_RTEE #define ACS_RTEE '+' #endif #ifndef ACS_UARROW #define ACS_UARROW '^' #endif #ifndef ACS_DARROW #define ACS_DARROW 'v' #endif /* * Attribute names */ #define screen_attr attributes[0] #define shadow_attr attributes[1] #define dialog_attr attributes[2] #define title_attr attributes[3] #define border_attr attributes[4] #define button_active_attr attributes[5] #define button_inactive_attr attributes[6] #define button_key_active_attr attributes[7] #define button_key_inactive_attr attributes[8] #define button_label_active_attr attributes[9] #define button_label_inactive_attr attributes[10] #define inputbox_attr attributes[11] #define inputbox_border_attr attributes[12] #define searchbox_attr attributes[13] #define searchbox_title_attr attributes[14] #define searchbox_border_attr attributes[15] #define position_indicator_attr attributes[16] #define menubox_attr attributes[17] #define menubox_border_attr attributes[18] #define item_attr attributes[19] #define item_selected_attr attributes[20] #define tag_attr attributes[21] #define tag_selected_attr attributes[22] #define tag_key_attr attributes[23] #define tag_key_selected_attr attributes[24] #define check_attr attributes[25] #define check_selected_attr attributes[26] #define uarrow_attr attributes[27] #define darrow_attr attributes[28] /* number of attributes */ #define ATTRIBUTE_COUNT 29 /* * Global variables */ extern bool use_colors; extern bool use_shadow; extern chtype attributes[]; extern const char *backtitle; /* * Function prototypes */ extern void create_rc (const char *filename); extern int parse_rc (void); void init_dialog (void); void end_dialog (void); void attr_clear (WINDOW * win, int height, int width, chtype attr); void dialog_clear (void); void color_setup (void); void print_autowrap (WINDOW * win, const char *prompt, int width, int y, int x); void print_button (WINDOW * win, const char *label, int y, int x, int selected); void draw_box (WINDOW * win, int y, int x, int height, int width, chtype box, chtype border); void draw_shadow (WINDOW * win, int y, int x, int height, int width); int first_alpha (const char *string, const char *exempt); int dialog_yesno (const char *title, const char *prompt, int height, int width); int dialog_msgbox (const char *title, const char *prompt, int height, int width, int pause); int dialog_textbox (const char *title, const char *file, int height, int width); int dialog_menu (const char *title, const char *prompt, int height, int width, int menu_height, const char *choice, int item_no, const char * const * items); int dialog_checklist (const char *title, const char *prompt, int height, int width, int list_height, int item_no, const char * const * items, int flag); extern unsigned char dialog_input_result[]; int dialog_inputbox (const char *title, const char *prompt, int height, int width, const char *init); /* * This is the base for fictitious keys, which activate * the buttons. * * Mouse-generated keys are the following: * -- the first 32 are used as numbers, in addition to '0'-'9' * -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o') * -- uppercase chars are used to invoke the button (M_EVENT + 'O') */ #define M_EVENT (KEY_MAX+1) /* * The `flag' parameter in checklist is used to select between * radiolist and checklist */ #define FLAG_CHECK 1 #define FLAG_RADIO 0 ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/yesno.c�������������������������������������������������0000644�0001750�0000144�00000005773�10541455476�020740� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * yesno.c -- implements the yes/no box * * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "dialog.h" /* * Display termination buttons */ static void print_buttons(WINDOW *dialog, int height, int width, int selected) { int x = width / 2 - 10; int y = height - 2; print_button (dialog, " Yes ", y, x, selected == 0); print_button (dialog, " No ", y, x + 13, selected == 1); wmove(dialog, y, x+1 + 13*selected ); wrefresh (dialog); } /* * Display a dialog box with two buttons - Yes and No */ int dialog_yesno (const char *title, const char *prompt, int height, int width) { int i, x, y, key = 0, button = 0; WINDOW *dialog; /* center dialog box on screen */ x = (COLS - width) / 2; y = (LINES - height) / 2; draw_shadow (stdscr, y, x, height, width); dialog = newwin (height, width, y, x); keypad (dialog, TRUE); draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); wattrset (dialog, border_attr); mvwaddch (dialog, height-3, 0, ACS_LTEE); for (i = 0; i < width - 2; i++) waddch (dialog, ACS_HLINE); wattrset (dialog, dialog_attr); waddch (dialog, ACS_RTEE); if (title != NULL && strlen(title) >= width-2 ) { /* truncate long title -- mec */ char * title2 = malloc(width-2+1); memcpy( title2, title, width-2 ); title2[width-2] = '\0'; title = title2; } if (title != NULL) { wattrset (dialog, title_attr); mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); waddstr (dialog, (char *)title); waddch (dialog, ' '); } wattrset (dialog, dialog_attr); print_autowrap (dialog, prompt, width - 2, 1, 3); print_buttons(dialog, height, width, 0); while (key != ESC) { key = wgetch (dialog); switch (key) { case 'Y': case 'y': delwin (dialog); return 0; case 'N': case 'n': delwin (dialog); return 1; case TAB: case KEY_LEFT: case KEY_RIGHT: button = ((key == KEY_LEFT ? --button : ++button) < 0) ? 1 : (button > 1 ? 0 : button); print_buttons(dialog, height, width, button); wrefresh (dialog); break; case ' ': case '\n': delwin (dialog); return button; case ESC: break; } } delwin (dialog); return -1; /* ESC pressed */ } �����skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/colors.h������������������������������������������������0000644�0001750�0000144�00000012410�10541455476�021073� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * colors.h -- color attribute definitions * * AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* * Default color definitions * * *_FG = foreground * *_BG = background * *_HL = highlight? */ #define SCREEN_FG COLOR_CYAN #define SCREEN_BG COLOR_BLUE #define SCREEN_HL TRUE #define SHADOW_FG COLOR_BLACK #define SHADOW_BG COLOR_BLACK #define SHADOW_HL TRUE #define DIALOG_FG COLOR_BLACK #define DIALOG_BG COLOR_WHITE #define DIALOG_HL FALSE #define TITLE_FG COLOR_YELLOW #define TITLE_BG COLOR_WHITE #define TITLE_HL TRUE #define BORDER_FG COLOR_WHITE #define BORDER_BG COLOR_WHITE #define BORDER_HL TRUE #define BUTTON_ACTIVE_FG COLOR_WHITE #define BUTTON_ACTIVE_BG COLOR_BLUE #define BUTTON_ACTIVE_HL TRUE #define BUTTON_INACTIVE_FG COLOR_BLACK #define BUTTON_INACTIVE_BG COLOR_WHITE #define BUTTON_INACTIVE_HL FALSE #define BUTTON_KEY_ACTIVE_FG COLOR_WHITE #define BUTTON_KEY_ACTIVE_BG COLOR_BLUE #define BUTTON_KEY_ACTIVE_HL TRUE #define BUTTON_KEY_INACTIVE_FG COLOR_RED #define BUTTON_KEY_INACTIVE_BG COLOR_WHITE #define BUTTON_KEY_INACTIVE_HL FALSE #define BUTTON_LABEL_ACTIVE_FG COLOR_YELLOW #define BUTTON_LABEL_ACTIVE_BG COLOR_BLUE #define BUTTON_LABEL_ACTIVE_HL TRUE #define BUTTON_LABEL_INACTIVE_FG COLOR_BLACK #define BUTTON_LABEL_INACTIVE_BG COLOR_WHITE #define BUTTON_LABEL_INACTIVE_HL TRUE #define INPUTBOX_FG COLOR_BLACK #define INPUTBOX_BG COLOR_WHITE #define INPUTBOX_HL FALSE #define INPUTBOX_BORDER_FG COLOR_BLACK #define INPUTBOX_BORDER_BG COLOR_WHITE #define INPUTBOX_BORDER_HL FALSE #define SEARCHBOX_FG COLOR_BLACK #define SEARCHBOX_BG COLOR_WHITE #define SEARCHBOX_HL FALSE #define SEARCHBOX_TITLE_FG COLOR_YELLOW #define SEARCHBOX_TITLE_BG COLOR_WHITE #define SEARCHBOX_TITLE_HL TRUE #define SEARCHBOX_BORDER_FG COLOR_WHITE #define SEARCHBOX_BORDER_BG COLOR_WHITE #define SEARCHBOX_BORDER_HL TRUE #define POSITION_INDICATOR_FG COLOR_YELLOW #define POSITION_INDICATOR_BG COLOR_WHITE #define POSITION_INDICATOR_HL TRUE #define MENUBOX_FG COLOR_BLACK #define MENUBOX_BG COLOR_WHITE #define MENUBOX_HL FALSE #define MENUBOX_BORDER_FG COLOR_WHITE #define MENUBOX_BORDER_BG COLOR_WHITE #define MENUBOX_BORDER_HL TRUE #define ITEM_FG COLOR_BLACK #define ITEM_BG COLOR_WHITE #define ITEM_HL FALSE #define ITEM_SELECTED_FG COLOR_WHITE #define ITEM_SELECTED_BG COLOR_BLUE #define ITEM_SELECTED_HL TRUE #define TAG_FG COLOR_YELLOW #define TAG_BG COLOR_WHITE #define TAG_HL TRUE #define TAG_SELECTED_FG COLOR_YELLOW #define TAG_SELECTED_BG COLOR_BLUE #define TAG_SELECTED_HL TRUE #define TAG_KEY_FG COLOR_YELLOW #define TAG_KEY_BG COLOR_WHITE #define TAG_KEY_HL TRUE #define TAG_KEY_SELECTED_FG COLOR_YELLOW #define TAG_KEY_SELECTED_BG COLOR_BLUE #define TAG_KEY_SELECTED_HL TRUE #define CHECK_FG COLOR_BLACK #define CHECK_BG COLOR_WHITE #define CHECK_HL FALSE #define CHECK_SELECTED_FG COLOR_WHITE #define CHECK_SELECTED_BG COLOR_BLUE #define CHECK_SELECTED_HL TRUE #define UARROW_FG COLOR_GREEN #define UARROW_BG COLOR_WHITE #define UARROW_HL TRUE #define DARROW_FG COLOR_GREEN #define DARROW_BG COLOR_WHITE #define DARROW_HL TRUE /* End of default color definitions */ #define C_ATTR(x,y) ((x ? A_BOLD : 0) | COLOR_PAIR((y))) #define COLOR_NAME_LEN 10 #define COLOR_COUNT 8 /* * Global variables */ typedef struct { char name[COLOR_NAME_LEN]; int value; } color_names_st; extern color_names_st color_names[]; extern int color_table[][3]; ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/Makefile.am���������������������������������������������0000644�0001750�0000144�00000000247�10541455476�021462� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������EXTRA_DIST=colors.h inputbox.c lxdialog.c makefile.lx msgbox.c yesno.c \ checklist.c menubox.c util.c dialog.h textbox.c ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/scripts/lxdialog/menubox.c�����������������������������������������������0000644�0001750�0000144�00000031054�10541455476�021247� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * menubox.c -- implements the menu box * * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* * Changes by Clifford Wolf (god@clifford.at) * * [ 1998-06-13 ] * * *) A bugfix for the Page-Down problem * * *) Formerly when I used Page Down and Page Up, the cursor would be set * to the first position in the menu box. Now lxdialog is a bit * smarter and works more like other menu systems (just have a look at * it). * * *) Formerly if I selected something my scrolling would be broken because * lxdialog is re-invoked by the Menuconfig shell script, can't * remember the last scrolling position, and just sets it so that the * cursor is at the bottom of the box. Now it writes the temporary file * lxdialog.scrltmp which contains this information. The file is * deleted by lxdialog if the user leaves a submenu or enters a new * one, but it would be nice if Menuconfig could make another "rm -f" * just to be sure. Just try it out - you will recognise a difference! * * [ 1998-06-14 ] * * *) Now lxdialog is crash-safe against broken "lxdialog.scrltmp" files * and menus change their size on the fly. * * *) If for some reason the last scrolling position is not saved by * lxdialog, it sets the scrolling so that the selected item is in the * middle of the menu box, not at the bottom. * * 02 January 1999, Michael Elizabeth Chastain (mec@shout.net) * Reset 'scroll' to 0 if the value from lxdialog.scrltmp is bogus. * This fixes a bug in Menuconfig where using ' ' to descend into menus * would leave mis-synchronized lxdialog.scrltmp files lying around, * fscanf would read in 'scroll', and eventually that value would get used. */ #include "dialog.h" static int menu_width, item_x; /* * Print menu item */ static void print_item (WINDOW * win, const char *item, int choice, int selected, int hotkey) { int j; char menu_item[menu_width+1]; strncpy(menu_item, item, menu_width); menu_item[menu_width] = 0; j = first_alpha(menu_item, "YyNnMm"); /* Clear 'residue' of last item */ wattrset (win, menubox_attr); wmove (win, choice, 0); #if OLD_NCURSES { int i; for (i = 0; i < menu_width; i++) waddch (win, ' '); } #else wclrtoeol(win); #endif wattrset (win, selected ? item_selected_attr : item_attr); mvwaddstr (win, choice, item_x, menu_item); if (hotkey) { wattrset (win, selected ? tag_key_selected_attr : tag_key_attr); mvwaddch(win, choice, item_x+j, menu_item[j]); } if (selected) { wmove (win, choice, item_x+1); wrefresh (win); } } /* * Print the scroll indicators. */ static void print_arrows (WINDOW * win, int item_no, int scroll, int y, int x, int height) { int cur_y, cur_x; getyx(win, cur_y, cur_x); wmove(win, y, x); if (scroll > 0) { wattrset (win, uarrow_attr); waddch (win, ACS_UARROW); waddstr (win, "(-)"); } else { wattrset (win, menubox_attr); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); } y = y + height + 1; wmove(win, y, x); if ((height < item_no) && (scroll + height < item_no)) { wattrset (win, darrow_attr); waddch (win, ACS_DARROW); waddstr (win, "(+)"); } else { wattrset (win, menubox_border_attr); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); waddch (win, ACS_HLINE); } wmove(win, cur_y, cur_x); } /* * Display the termination buttons. */ static void print_buttons (WINDOW *win, int height, int width, int selected) { int x = width / 2 - 16; int y = height - 2; print_button (win, "Select", y, x, selected == 0); print_button (win, " Exit ", y, x + 12, selected == 1); print_button (win, " Help ", y, x + 24, selected == 2); wmove(win, y, x+1+12*selected); wrefresh (win); } /* * Display a menu for choosing among a number of options */ int dialog_menu (const char *title, const char *prompt, int height, int width, int menu_height, const char *current, int item_no, const char * const * items) { int i, j, x, y, box_x, box_y; int key = 0, button = 0, scroll = 0, choice = 0, first_item = 0, max_choice; WINDOW *dialog, *menu; FILE *f; max_choice = MIN (menu_height, item_no); /* center dialog box on screen */ x = (COLS - width) / 2; y = (LINES - height) / 2; draw_shadow (stdscr, y, x, height, width); dialog = newwin (height, width, y, x); keypad (dialog, TRUE); draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); wattrset (dialog, border_attr); mvwaddch (dialog, height - 3, 0, ACS_LTEE); for (i = 0; i < width - 2; i++) waddch (dialog, ACS_HLINE); wattrset (dialog, dialog_attr); wbkgdset (dialog, dialog_attr & A_COLOR); waddch (dialog, ACS_RTEE); if (title != NULL && strlen(title) >= width-2 ) { /* truncate long title -- mec */ char * title2 = malloc(width-2+1); memcpy( title2, title, width-2 ); title2[width-2] = '\0'; title = title2; } if (title != NULL) { wattrset (dialog, title_attr); mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); waddstr (dialog, (char *)title); waddch (dialog, ' '); } wattrset (dialog, dialog_attr); print_autowrap (dialog, prompt, width - 2, 1, 3); menu_width = width - 6; box_y = height - menu_height - 5; box_x = (width - menu_width) / 2 - 1; /* create new window for the menu */ menu = subwin (dialog, menu_height, menu_width, y + box_y + 1, x + box_x + 1); keypad (menu, TRUE); /* draw a box around the menu items */ draw_box (dialog, box_y, box_x, menu_height + 2, menu_width + 2, menubox_border_attr, menubox_attr); /* * Find length of longest item in order to center menu. * Set 'choice' to default item. */ item_x = 0; for (i = 0; i < item_no; i++) { item_x = MAX (item_x, MIN(menu_width, strlen (items[i * 2 + 1]) + 2)); if (strcmp(current, items[i*2]) == 0) choice = i; } item_x = (menu_width - item_x) / 2; /* get the scroll info from the temp file */ if ( (f=fopen("lxdialog.scrltmp","r")) != NULL ) { if ( (fscanf(f,"%d\n",&scroll) == 1) && (scroll <= choice) && (scroll+max_choice > choice) && (scroll >= 0) && (scroll+max_choice <= item_no) ) { first_item = scroll; choice = choice - scroll; fclose(f); } else { scroll=0; remove("lxdialog.scrltmp"); fclose(f); f=NULL; } } if ( (choice >= max_choice) || (f==NULL && choice >= max_choice/2) ) { if (choice >= item_no-max_choice/2) scroll = first_item = item_no-max_choice; else scroll = first_item = choice - max_choice/2; choice = choice - scroll; } /* Print the menu */ for (i=0; i < max_choice; i++) { print_item (menu, items[(first_item + i) * 2 + 1], i, i == choice, (items[(first_item + i)*2][0] != ':')); } wnoutrefresh (menu); print_arrows(dialog, item_no, scroll, box_y, box_x+item_x+1, menu_height); print_buttons (dialog, height, width, 0); wmove (menu, choice, item_x+1); wrefresh (menu); while (key != ESC) { key = wgetch(menu); if (key < 256 && isalpha(key)) key = tolower(key); if (strchr("ynm", key)) i = max_choice; else { for (i = choice+1; i < max_choice; i++) { j = first_alpha(items[(scroll+i)*2+1], "YyNnMm"); if (key == tolower(items[(scroll+i)*2+1][j])) break; } if (i == max_choice) for (i = 0; i < max_choice; i++) { j = first_alpha(items[(scroll+i)*2+1], "YyNnMm"); if (key == tolower(items[(scroll+i)*2+1][j])) break; } } if (i < max_choice || key == KEY_UP || key == KEY_DOWN || key == '-' || key == '+' || key == KEY_PPAGE || key == KEY_NPAGE) { print_item (menu, items[(scroll+choice)*2+1], choice, FALSE, (items[(scroll+choice)*2][0] != ':')); if (key == KEY_UP || key == '-') { if (choice < 2 && scroll) { /* Scroll menu down */ scrollok (menu, TRUE); wscrl (menu, -1); scrollok (menu, FALSE); scroll--; print_item (menu, items[scroll * 2 + 1], 0, FALSE, (items[scroll*2][0] != ':')); } else choice = MAX(choice - 1, 0); } else if (key == KEY_DOWN || key == '+') { print_item (menu, items[(scroll+choice)*2+1], choice, FALSE, (items[(scroll+choice)*2][0] != ':')); if ((choice > max_choice-3) && (scroll + max_choice < item_no) ) { /* Scroll menu up */ scrollok (menu, TRUE); scroll (menu); scrollok (menu, FALSE); scroll++; print_item (menu, items[(scroll+max_choice-1)*2+1], max_choice-1, FALSE, (items[(scroll+max_choice-1)*2][0] != ':')); } else choice = MIN(choice+1, max_choice-1); } else if (key == KEY_PPAGE) { scrollok (menu, TRUE); for (i=0; (i < max_choice); i++) { if (scroll > 0) { wscrl (menu, -1); scroll--; print_item (menu, items[scroll * 2 + 1], 0, FALSE, (items[scroll*2][0] != ':')); } else { if (choice > 0) choice--; } } scrollok (menu, FALSE); } else if (key == KEY_NPAGE) { for (i=0; (i < max_choice); i++) { if (scroll+max_choice < item_no) { scrollok (menu, TRUE); scroll(menu); scrollok (menu, FALSE); scroll++; print_item (menu, items[(scroll+max_choice-1)*2+1], max_choice-1, FALSE, (items[(scroll+max_choice-1)*2][0] != ':')); } else { if (choice+1 < max_choice) choice++; } } } else choice = i; print_item (menu, items[(scroll+choice)*2+1], choice, TRUE, (items[(scroll+choice)*2][0] != ':')); print_arrows(dialog, item_no, scroll, box_y, box_x+item_x+1, menu_height); wnoutrefresh (dialog); wrefresh (menu); continue; /* wait for another key press */ } switch (key) { case KEY_LEFT: case TAB: case KEY_RIGHT: button = ((key == KEY_LEFT ? --button : ++button) < 0) ? 2 : (button > 2 ? 0 : button); print_buttons(dialog, height, width, button); wrefresh (menu); break; case ' ': case 's': case 'y': case 'n': case 'm': /* save scroll info */ if ( (f=fopen("lxdialog.scrltmp","w")) != NULL ) { fprintf(f,"%d\n",scroll); fclose(f); } delwin (dialog); fprintf(stderr, "%s\n", items[(scroll + choice) * 2]); switch (key) { case 's': return 3; case 'y': return 3; case 'n': return 4; case 'm': return 5; case ' ': return 6; } return 0; case 'h': case '?': button = 2; case '\n': delwin (dialog); if (button == 2) fprintf(stderr, "%s \"%s\"\n", items[(scroll + choice) * 2], items[(scroll + choice) * 2 + 1] + first_alpha(items[(scroll + choice) * 2 + 1],"")); else fprintf(stderr, "%s\n", items[(scroll + choice) * 2]); remove("lxdialog.scrltmp"); return button; case 'e': case 'x': key = ESC; case ESC: break; } } delwin (dialog); remove("lxdialog.scrltmp"); return -1; /* ESC pressed */ } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/configs/�����������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015536� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/configs/defconfig��������������������������������������������������������0000644�0001750�0000144�00000006120�10541455476�017427� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������# default config file, made by mkdefconfig # # System wide options # CONFIG_LITE=n CONFIG_STAND_ALONE=n CONFIG_INCORE_RES=n CONFIG_TIMERUNIT10MS=y CONFIG_CURSORSUPPORT=y CONFIG_MOVEABLE=y CONFIG_DBCLK=y CONFIG_DEBUG=n CONFIG_TRACEMESSAGE=n CONFIG_MSGSTR=n # # GAL engine options # CONFIG_NEWGAL=y CONFIG_GAL_NATIVE=y CONFIG_GAL_NATIVE_QVFB=y CONFIG_GAL_NATIVE_COORTRANS_CW=n CONFIG_GAL_NATIVE_COORTRANS_CCW=n CONFIG_GAL_NATIVE_R1BPPFB=n CONFIG_GAL_NATIVE_L1BPPFB=n CONFIG_GAL_NATIVE_R2BPPFB=n CONFIG_GAL_NATIVE_L2BPPFB=n CONFIG_GAL_NATIVE_R4BPPFB=n CONFIG_GAL_NATIVE_L4BPPFB=n CONFIG_GAL_NATIVE_8BPPFB=y CONFIG_GAL_NATIVE_16BPPFB=y CONFIG_GAL_NATIVE_24BPPFB=n CONFIG_GAL_NATIVE_32BPPFB=y CONFIG_GAL_NATIVE_VGA16FB=n CONFIG_GALIAL_SVGALIB=n CONIFG_GALIAL_LIBGGI=n CONFIG_GAL_EP7211=n CONFIG_GAL_ADS=n CONFIG_GAL_VGA16=n CONFIG_NEWGAL_FBCON=y CONFIG_NEWGAL_QVFB=y CONFIG_NEWGAL_DUMMY=y # # IAL engine options # CONFIG_IAL_EP7211=n CONFIG_IAL_ADS=n CONFIG_IAL_IPAQ=n CONFIG_IAL_MPC823=n CONFIG_IAL_VR4181=n CONFIG_IAL_HELIO=n CONFIG_IAL_MTT800=n CONFIG_IAL_DUMMY=y CONFIG_IAL_NATIVE=y CONFIG_IAL_MC68X328=n CONFIG_IAL_NATIVE_PS2MOUSE=y CONFIG_IAL_NATIVE_IMPS2MOUSE=y CONFIG_IAL_NATIVE_MSMOUSE=y CONFIG_IAL_NATIVE_MS3MOUSE=y CONFIG_IAL_NATIVE_GPM=y # # Font options # CONFIG_FONT_RBF=y CONFIG_FONT_INCOREGB12=y CONFIG_FONT_VBF=y CONFIG_FONT_INCORESSERIF=y CONFIG_FONT_INCORECOURIER=y CONFIG_FONT_INCORESYMBOL=y CONFIG_FONT_INCOREVGAS=y CONFIG_FONT_QPF=y CONFIG_FONT_TTF=y CONFIG_FONT_TYPE1=y # # Charset options # CONFIG_CHARSET_LATIN2=n CONFIG_CHARSET_LATIN3=n CONFIG_CHARSET_LATIN4=n CONFIG_CHARSET_CYRILLIC=n CONFIG_CHARSET_ARABIC=n CONFIG_CHARSET_GREEK=n CONFIG_CHARSET_HEBREW=n CONFIG_CHARSET_LATIN5=n CONFIG_CHARSET_LATIN6=n CONFIG_CHARSET_THAI=n CONFIG_CHARSET_LATIN7=n CONFIG_CHARSET_LATIN8=n CONFIG_CHARSET_LATIN9=y CONFIG_CHARSET_LATIN10=n CONFIG_CHARSET_GB2312=y CONFIG_CHARSET_GBK=y CONFIG_CHARSET_GB18030=n CONFIG_CHARSET_BIG5=y CONFIG_CHARSET_EUCKR=n CONFIG_CHARSET_EUCJP=n CONFIG_CHARSET_SHIFTJIS=n CONFIG_CHARSET_UNICODE=y # # Keyboard layout specific options # CONFIG_KBD_FRPC=n CONFIG_KBD_FR=n CONFIG_KBD_DE=n CONFIG_KBD_DELATIN1=n CONFIG_KBD_IT=n CONFIG_KBD_ES=n CONFIG_KBD_ESCP850=n # # Image options # CONFIG_IMAGE_SAVEBMP=y CONFIG_IMAGE_PCX=n CONFIG_IMAGE_LBM=n CONFIG_IMAGE_TGA=n CONFIG_IMAGE_GIF=y CONFIG_IMAGE_JPG=y CONFIG_IMAGE_PNG=y # # Input method options # CONFIG_IME_GB2312=y CONFIG_IME_GB2312PINYIN=y # # Appearance options # CONFIG_APPEARANCE_FLATSTYLE=n CONFIG_APPEARANCE_TINYSCR=n # # Misc options # CONFIG_MISC_ABOUTDLG=y CONFIG_MISC_SAVESCR=y CONFIG_MISC_TEXTMODE=y # # Controls options # CONFIG_CTRL_STATIC=y CONFIG_CTRL_BUTTON=y CONFIG_CTRL_SIMEDIT=y CONFIG_CTRL_SLEDIT=y CONFIG_CTRL_MLEDIT=y CONFIG_CTRL_LISTBOX=y CONFIG_CTRL_PROGRESSBAR=y CONFIG_CTRL_TOOLBAR=y CONFIG_CTRL_NEWTOOLBAR=y CONFIG_CTRL_MENUBUTTON=y CONFIG_CTRL_TRACKBAR=y CONFIG_CTRL_COMBOBOX=y CONFIG_CTRL_PROPSHEET=y # # Ext library options # CONFIG_EXT_TREEVIEW=y CONFIG_EXT_LISTVIEW=y CONFIG_EXT_MONTHCAL=y CONFIG_EXT_SPINBOX=y CONFIG_EXT_COOLBAR=y CONFIG_EXT_FULLGIF=n CONFIG_PLATFORM_LINUX=y CONFIG_COMPILER_X86=y CONFIG_LIBC_GLIBC=y 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Makefile.am. # @configure_input@ # Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 # Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ SHELL = @SHELL@ srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ prefix = @prefix@ exec_prefix = @exec_prefix@ bindir = @bindir@ sbindir = @sbindir@ libexecdir = @libexecdir@ datadir = @datadir@ sysconfdir = @sysconfdir@ sharedstatedir = @sharedstatedir@ localstatedir = @localstatedir@ libdir = @libdir@ infodir = @infodir@ mandir = @mandir@ includedir = @includedir@ oldincludedir = /usr/include pkgdatadir = $(datadir)/@PACKAGE@ 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Order of the help texts does not matter, # however, no variable should be documented twice: if it is, only the # first occurrence will be used. We try to keep the help texts of related # variables close together. Lines starting with `#' are ignored. To be # nice to menuconfig, limit your line length to 70 characters. Use emacs' # kfill.el to edit and ispell.el to spell check this file or you lose. # # Comments of the form "# Choice:" followed by a menu name are used # internally by the maintainers' consistency-checking tools. # # If you add a help text to this file, please try to be as gentle as # possible. Don't use unexplained acronyms and generally write for the # hypothetical ignorant but intelligent user who has just bought a PC, # removed Windows, installed Linux and is now recompiling the kernel # for the first time. Tell them what to do if they're unsure. Technical # information should go in a README in the Documentation directory. # # Mention all the relevant READMEs and HOWTOs in the help text. # Make them file URLs relative to the top level of the source tree so # that help browsers can turn them into hotlinks. All URLs should be # surrounded by <>. # # Repetitions are fine since the help texts are not meant to be read # in sequence. It is good style to include URLs pointing to more # detailed technical information, pictures of the hardware, etc. # # The most important thing to include in a help entry is *motivation*. # Explain why someone configuring a kernel might want to select your # option. Build MiniGUI-Lite CONFIG_LITE Build MiniGUI-Lite version library. If you excludes this option, the MiniGUI library will be built as MiniGUI-Threads version. In MiniGUI-Lite version, the applications(tasks) are organized as separate processes. There is a server application(process) called "mginit", and other client applications(processes). The clients and the server communicates with each other via UNIX Domain Sockets. The MiniGUI-Threads version uses pthread library, and the tasks are organized as threads. Build Stand-Alone version of MiniGUI-Lite CONFIG_STAND_ALONE Build Stand-Alone version of MiniGUI-Lite. In normal MiniGUI-Lite version, the applications (tasks) are organized as separate processes. Include this option, we will get a stand-alone version, i.e., there is only a process, and no clients can run on the process. Use built-in resource CONFIG_INCORE_RES Use incore resource data to initialize MiniGUI instead of file I/O. Choose this option will override the configuration in MiniGUI.cfg file. Unit of timer is 10ms CONFIG_TIMERUNIT10MS The MiniGUI timer timeout value is in unit of 10 ms. BOOL GUIAPI SetTimer (HWND hWnd, int id, unsigned int speed); The argument "speed" in SetTimer function may represent the frequency of the timer, or represent the timeout value of the timer. This is depend on the runtime library of MiniGUI. If _TIMER_UNIT_10MS is defined, "speed" represents the timeout value of the timer, in the unit of 10ms, else is the frequency. If "speed" represents the frequency of the timer, when it is equal to 10, the timer will expire after every second. If you wants to define _TIMER_UNIT_10MS (default), includes this option. Cursor support (for MiniGUI-Lite) CONFIG_CURSORSUPPORT You can excludes cursor support from MiniGUI library by excluding this option. User can move window with mouse CONFIG_MOVEABLE In embedded systems, this option may usually be excluded. No one will need or like a moveable window on handheld devices like PDA. Mouse button can do double click CONFIG_DBCLK Double click is not usual in embedded system, you may want to exclude this option. Build with debugging messages CONFIG_DEBUG Build MiniGUI library with debugging messages. Trace messages of MiniGUI CONFIG_TRACEMESSAGE Trace messages of MiniGUI. Include symbol name of messages CONFIG_MSGSTR Include symbol name of messages Uses old GAL interface and its engines CONFIG_OLDGAL Uses old GAL engines and old GDI interfaces instead of NEWGAL. NEWGAL engine and new GDI interfaces are more powerful and flexible, but NEWGAL only supports linear FrameBuffer above 8BPP. Old GAL supports more display mode (lowest color depth supported is 1BPP black-white mode). If you want to use MiniGUI in low color depth devices, includes this option. Native FrameBuffer graphics GAL engine CONFIG_GAL_NATIVE Native/FBcon FrameBuffer grahpics GAL engine. Based on Linux FrameBuffer, and supports various color depths. Native FrameBuffer graphics GAL engine on Qt Virtual FrameBuffer CONFIG_GAL_NATIVE_QVFB Native/FBcon GAL engine on Qt Virtual FrameBuffer. If you enable it, Native/FBCon GAL engine can run on QVFB. Support for clockwise rotation of screen CONFIG_GAL_NATIVE_COORTRANS Support for clockwise rotation of screen. This option is useful for iPAQ. R1BPP FB CONFIG_GAL_NATIVE_R1BPPFB Native GAL engine 1BPP FB subdriver (Most significant bit is right). L1BPP FB CONFIG_GAL_NATIVE_L1BPPFB Native GAL engine 1BPP FB subdriver (Most significant bit is left). R2BPP FB CONFIG_GAL_NATIVE_R2BPPFB Native GAL engine 2BPP FB subdriver (Most significant bit is right). L2BPP FB CONFIG_GAL_NATIVE_L2BPPFB Native GAL engine 2BPP FB subdriver (Most significant bit is left). R4BPP FB CONFIG_GAL_NATIVE_R4BPPFB Native GAL engine 4BPP FB subdriver (Most significant bit is right). L4BPP FB CONFIG_GAL_NATIVE_L4BPPFB Native GAL engine 4BPP FB subdriver (Most significant bit is left). 8BPP FB CONFIG_GAL_NATIVE_8BPPFB Native GAL engine 8BPP FB subdriver 16BPP FB CONFIG_GAL_NATIVE_16BPPFB Native GAL engine 16BPP FB subdriver 24BPP FB (incompleted) CONFIG_GAL_NATIVE_24BPPFB Native GAL engine 24BPP FB subdriver 32BPP FB CONFIG_GAL_NATIVE_32BPPFB Native GAL engine 32BPP FB subdriver VGA16 FB (do not include, dangerous) CONFIG_GAL_NATIVE_VGA16FB Dangerous, do not include. GAL and IAL engine on SVGALIB (for old GAL and MiniGUI-Threads) CONFIG_GALIAL_SVGALIB GAL and IAL engine on SVGALIB (for old GAL and MiniGUI-Threads) GAL and IAL engine on LibGGI (for old GAL and MiniGUI-Threads) CONIFG_GALIAL_LIBGGI GAL and IAL engine on LibGGI (for old GAL and MiniGUI-Threads) EP7211-based board (obsolete, do not include) CONFIG_GAL_EP7211 EP7211-based board (obsolete, do not include) ADS Graphics Client board (obsolete, do not include) CONFIG_GAL_ADS ADS Graphics Client board (obsolete, do not include) VGA 16-color mode CONFIG_GAL_VGA16 Standar VGA 16-color display mode. Enable text mode CONFIG_GAL_TEXTMODE Excludes this option when your Linux system have text mode, i.e. no console. EP7211-based board CONFIG_IAL_EP7211 EP7211-based board input support ADS Graphics Client CONFIG_IAL_ADS ADS Graphics Client IAL (StrongARM SA1110). iPAQ H3600 (also H3800) CONFIG_IAL_IPAQ iPAQ H3600 and H3800 series input support MPC823 CONFIG_IAL_MPC823 Support for Sinovee SC823 board touchpad and keyboard. Touchpad: ads7846 Keyboard: zlg7289 NEC VR4181 CONFIG_IAL_VR4181 NEC VR4181 IAL. Helio Touch Panel CONFIG_IAL_HELIO Helio Touch Panel. MT T800 CONFIG_IAL_MTT800 MT T800 IAL. Dummy IAL engine CONFIG_IAL_DUMMY You can skip input processing by using Dummy IAL engine. Native (console) input engine CONFIG_IAL_NATIVE Native (console) input engine is used to support mouse and keyboard on standar PC console. PS2 mouse CONFIG_IAL_NATIVE_PS2MOUSE Support for PS2 mouse protocol. IntelligentMouse (IMPS/2) mouse CONFIG_IAL_NATIVE_IMPS2MOUSE Support for IntelligentMouse (IMPS/2) mouse protocol. MS mouse CONFIG_IAL_NATIVE_MSMOUSE Support for old MS serial mouse. MS3 mouse CONFIG_IAL_NATIVE_MS3MOUSE Support for MS3 serial mouse. GPM daemon CONFIG_IAL_NATIVE_GPM Support for GPM mouse daemon. You can use GPM to support obsolete mouse type such as serial mouse. Raw bitmap font CONFIG_FONT_RBF Support for Raw Bitmap Font. Raw Bitmap Font format used in MiniGUI is defined by Feynman Software. MiniGUI needs at lease one kind RBF font to run (the system font must be Raw Bitmap Font), so you should not exclude this option. Incore GB2312 12x12 RBF font CONFIG_FONT_INCOREGB12 Include incore RBF font for GB2312 charset. This option is only effective when INCORE_RES option is enabled. Var bitmap font CONFIG_FONT_VBF Support for Var Bitmap Font (Variable width Bitmap Font). Var Bitmap Font format used in MiniGUI is defined by Feynman Software. VBF fonts includes Courier, Times and Helvetica fonts. Incore font sansserif CONFIG_FONT_INCORESSERIF Incore font sansserif Incore font courier CONFIG_FONT_INCORECOURIER Incore font courier Incore font symbol CONFIG_FONT_INCORESYMBOL Incore font symbol Incore font vgas CONFIG_FONT_INCOREVGAS Incore font vgas Qt Prerendered Font CONFIG_FONT_QPF Qt Prerendered Font. This font format is defined in Qt/Embedded. QPF font uses UNICODE encoding, so UNICODE support must be included if you want to include this option. TrueType font CONFIG_FONT_TTF TrueType font support. MiniGUI uses freetype 1.3.x library to render truetype fonts. Note that MiniGUI can't work on freetype 2.0, so you may need to exclude this option if your system uses freetype 2.0. Adobe Type1 font CONFIG_FONT_TYPE1 Adobe Type1 font support. MiniGUI uses t1 library to render type1 fonts. East European (Latin 2, ISO-8859-2) charset CONFIG_CHARSET_LATIN2 East European (Latin 2, ISO-8859-2) charset South European (Latin 3, ISO-8859-3) charset CONFIG_CHARSET_LATIN3 South European (Latin 3, ISO-8859-3) charset North European (Latin 4, ISO-8859-4) charset CONFIG_CHARSET_LATIN4 North European (Latin 4, ISO-8859-4) charset Cyrillic (ISO-8859-5) charset CONFIG_CHARSET_CYRILLIC Cyrillic (ISO-8859-5) charset Arabic (ISO-8859-6) charset CONFIG_CHARSET_ARABIC Arabic (ISO-8859-6) charset Greek (ISO-8859-7) charset CONFIG_CHARSET_GREEK Greek (ISO-8859-7) charset Hebrew (ISO-8859-8) charset CONFIG_CHARSET_HEBREW Hebrew (ISO-8859-8) charset Turkish (Latin 5, ISO-8859-9) charset CONFIG_CHARSET_LATIN5 Turkish (Latin 5, ISO-8859-9) charset Nordic, Latin 6, ISO-8859-10) charset CONFIG_CHARSET_LATIN6 Nordic, Latin 6, ISO-8859-10) charset Thai (ISO-8859-11) charset CONFIG_CHARSET_THAI Thai (ISO-8859-11) charset Latin 7 (ISO-8859-13) charset CONFIG_CHARSET_LATIN7 Latin 7 (ISO-8859-13) charset Latin 8 (ISO-8859-14) charset CONFIG_CHARSET_LATIN8 Latin 8 (ISO-8859-14) charset Latin 9 (ISO-8859-15, West Extended) charset CONFIG_CHARSET_LATIN9 Latin 9 (ISO-8859-15, West Extended) charset Latin 10 (ISO-8859-16, Romanian) charset CONFIG_CHARSET_LATIN10 Latin 10 (ISO-8859-16, Romanian) charset EUC encoding of GB2312 charset CONFIG_CHARSET_GB2312 EUC encoding of GB2312 charset GBK charset CONFIG_CHARSET_GBK GBK charset GB18030-0 charset CONFIG_CHARSET_GB18030 GB18030-0 charset BIG5 charset CONFIG_CHARSET_BIG5 BIG5 charset EUC encoding of KSC5636 and KSC5601 charsets CONFIG_CHARSET_EUCKR EUC encoding of KSC5636 and KSC5601 charsets EUC encoding of JISX0201 and JISX0208 charsets CONFIG_CHARSET_EUCJP EUC encoding of JISX0201 and JISX0208 charsets Shift-JIS encoding of JISX0201 and JISX0208 charsets CONFIG_CHARSET_SHIFTJIS Shift-JIS encoding of JISX0201 and JISX0208 charsets UNICODE (ISO-10646-1 and UTF-8 encoding) CONFIG_CHARSET_UNICODE UNICODE (ISO-10646-1 and UTF-8 encoding) French PC keyboard (non-US 102 keys) CONFIG_KBD_FRPC French PC keyboard (non-US 102 keys) Keyboard layout for French CONFIG_KBD_FR Keyboard layout for French Keyboard layout for German CONFIG_KBD_DE Keyboard layout for German Keyboard layout for German Latin1 CONFIG_KBD_DELATIN1 Keyboard layout for German Latin1 Keyboard layout for Italian CONFIG_KBD_IT Keyboard layout for Italian Keyboard layout for Spanish CONFIG_KBD_ES Keyboard layout for Spanish Keyboard layout for Spanish CP850 CONFIG_KBD_ESCP850 Keyboard layout for Spanish CP850 Includes SaveBitmap-related functions CONFIG_IMAGE_SAVEBMP Includes SaveBitmap-related functions support. If you include this option, SaveBitmapToFile and SaveMyBitmapToFile will be supported. You may use this two functions to save BITMAP and MYBITMAP structure to bmp file. PCX file support CONFIG_IMAGE_PCX Supports PCX image format. LBM/PBM file support CONFIG_IMAGE_LBM Supports LBM/PBM image format. TGA file support CONFIG_IMAGE_TGA TGA file support GIF file support CONFIG_IMAGE_GIF GIF file support JPG file support CONFIG_IMAGE_JPG JPG file support. You may need libjpeg library if support this option. PNG file support CONFIG_IMAGE_PNG PNG file support You may need libpng library if support this option. IME (GB2312) support CONFIG_IME_GB2312 Includes GB2312 pinyin input method. Pinyin input method needs some ime resource files, including pinyin.tab, pinyin.cin, pinyin.map, pinyin.tab.lx, pinyin.tab.phr. IME (GB2312) Intelligent Pinyin module CONFIG_IME_GB2312PINYIN IME (GB2312) Intelligent Pinyin module Using flat window style instead of 3D style CONFIG_APPEARANCE_FLATSTYLE Using flat window style instead of the default 3D style. In flat window style, the windows and controls are drawn with flat style, and the bitmap resources used are also different from the 3D style. Target is a gray screen CONFIG_APPEARANCE_GRAYSCR Supports for gray scale devices. The windows and controls are drawn with flat style and gray scale colors. Used within flat window style. Target is a tiny-size screen CONFIG_APPEARANCE_TINYSCR Supports for tiny-size screen. Adjusts the message box size for tiny screen devices. Suitable for 160x160 size, and etc. Include About Dialog Box CONFIG_MISC_ABOUTDLG Supports for 'About MiniGUI' dialog. To open or active the 'About MiniGUI' dialog, you should call OpenAboutDialog function. Calling this function will create a main window displaying copyright and license information of MiniGUI. When the about dialog is displaying, calling this function again will bring the dialog to be the topmost main window, not create a new one. Include code for screenshots CONFIG_MISC_SAVESCR Includes codes for getting screenshots. If this option is included, you can use SaveMainWindowContent function to save content of a main window to a file. Static CONFIG_CTRL_STATIC Static control is used to display information and text, without input capability. Button CONFIG_CTRL_BUTTON Button control is used to activate an action. Simple EDIT CONFIG_CTRL_SIMEDIT Simple EDIT control is used to input and display text. This edit control uses the system default fixed logical font. Single-Line EDIT CONFIG_CTRL_SLEDIT Single-line EDIT control is used to input and display text. This edit control uses the system logical font for control, which may be variable-width font. Multi-Line EDIT CONFIG_CTRL_MLEDIT Multi-line EDIT control is used to input and display text. This edit control uses the system logical font for control, which may be variable-width font. Listbox CONFIG_CTRL_LISTBOX Listbox control is used to display a list of items. Progressbar CONFIG_CTRL_PROGRESSBAR Progressbar control is used to show the varying progress status. Toolbar CONFIG_CTRL_TOOLBAR Toolbar control is a tool bar with some button-like item. Newtoolbar CONFIG_CTRL_NEWTOOLBAR Newtoolbar control is a image-button tool bar used to activate actions. Menubutton CONFIG_CTRL_MENUBUTTON Menubutton control is a button-like control, clicking on it will drop a menu to choose from. Trackbar CONFIG_CTRL_TRACKBAR Trackbar control is a track-like bar with a slider on it. This control is used to show position status and variance. Combobox CONFIG_CTRL_COMBOBOX With an input area and a click area(arrow), the Combobox controls is used to choose an item and show it in the input area. Combobox control with CBS_DROPDOWNLIST style is somewhat like menubutton control. Clicking on a combobox control will drop a menu to choose an item. CBS_SIMPLE style Combobox creates a listbox to display items. The current selection in the list box is displayed in the edit control. CBS_AUTOSPIN style Combobox creates AutoSpin box to choose an item. AutoSpin box has an input field with a spin button. The input field displays an integer, and you can click spin button to increase or decrease the value of the integer. CBS_SPINLIST style Combobox creates SpinList to choose an item. SpinList box has an input field with a spin button. The input field displays some text, and you can click spin button to change the text. The candidate text string comes from the strings you add to the box. Propsheet CONFIG_CTRL_PROPSHEET Propsheet control has a page title area and a page conten area. Clicking on the page title will cause changing the current page and the showing content. Treeview control CONFIG_EXT_TREEVIEW Treeview control is used to show a list of items with a tree-like fashion. Listview control CONFIG_EXT_LISTVIEW Listview control is used to display the properties of a list of items. A listview is consist of some rows and columns. Monthcalendar control CONFIG_EXT_MONTHCAL Monthcalendar control displays date information in a calendar-like fashion. Spinbox control CONFIG_EXT_SPINBOX Spinbox control is a control with fixed width and height. User can click on the up arrow or the down arrow to change the spinbox current value. Coolbar control CONFIG_EXT_COOLBAR Coolbar control is a simple tool bar with text or image button-like items. Full gif support CONFIG_EXT_FULLGIF Includes gif animation support. platform CONFIG_PLATFORM_LINUX Selects the OS platform. uClinux(http://www.uclinux.org) is a derivative of Linux kernel intended for microcontrollers without Memory Management Units (MMUs). uClinux kernel was created to support non-MMU microprocessors, it is small but retains the main advantages of the linux operating system: stability, superior network capability, and excellent file system support. Most Linux applications can run on uClinux with little or without any changes. MiniGUI version 1.3 makes some optimization for uClinux, such as built-in resources support, and specific memory allocations. To use MiniGUI under uClinux, compiles it as static library. compiler CONFIG_COMPILER_ARM Choose your cross compiler here. arm-linux-gcc : arm cross compiler for StrongARM, gcc 2.1.3. armv4l-linux-gcc : arm cross compiler for arm version 4 little endian, including StrongARM, arm7, arm9. mipsel-linux-gcc : mipsel cross compiler. ppc-linux-gcc : PowerPC cross compiler. m68k-elf-gcc : m68k cross compiler for uClinux. arm-elf-gcc : arm cross compiler for uClinux. i386 : x86 gcc compiler, default. target CONFIG_TARGET_M68K_XCOPILOT Choose your target processor, useful if compiling for uClinux. m68k/68328 : Motorola mc68328 processor, including Xcopilot emulator, etc m68k/68ez328 : Motorola 68ez328 processor, including Arcturus/uCsimm, etc. m68k/Coldfire 5200: Coldfire 5200. m68k/Coldfire 5307: Coldfire 5307. libc CONFIG_LIBC_GLIBC Selects the uClibc or glibc as the libc. uClibc - a Small C Library for Linux Erik Andersen <andersen@codepoet.org> uClibc is a C library for developing embedded Linux systems. It is much smaller than the GNU C Library, but nearly all applications supported by glibc also work perfectly with uClibc. Porting applications from glibc to uClibc typically involves just recompiling the source code. uClibc even supports shared libraries and threading. It currently runs on standard Linux and MMU-less (also known as uClinux) systems with support for alpha, ARM, i386, i960, h8300, m68k, mips/mipsel, PowerPC, SH, SPARC, and v850 processors. If you are building an embedded Linux system and you find that glibc is eating up too much space, you should consider using uClibc. If you are building a huge fileserver with 12 Terabytes of storage, then using glibc may be a better choice... uClibc is maintained by Erik Andersen and is licensed under the GNU LIBRARY GENERAL PUBLIC LICENSE . This license allows you to make closed source commercial applications using uClibc (Please consider sharing some of the money you make ;-). You do not need to give away all your source code just because you use uClibc and/or run on Linux. -------------------------------------------------------------- uClibc does not support shared library under uClinux now, so you may need to compile MiniGUI as static library. If you are compiling MiniGUI for uClinux and choose uClibc as the libc library, you do not need to configure uClibc separately. If you are not using uClibc under uClinux-dist, make sure you have compiled and install uClibc v0.9.19 in the director: "/usr/ARCH-linux-uclibc". uClinux-Dist directory UCDIST_DIR Set directory of your uClinux-dist if you are using uClinux. uClibc directory CONFIG_UCLIBC_DIR Set directory of your uClibc if you are not using uClibc under uClinux. uClibc header directory UCLIBC_HEADER Directory of your uClibc header. uClibc library directory UCLIBC_LIB Directory of your binary uClibc library. Installation prefix PREFIX Installation prefix for MiniGUI, you are recommended to use the default value. # End: �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/configs/config.in��������������������������������������������������������0000644�0001750�0000144�00000004513�10541455476�017361� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������# # For a description of the syntax of this configuration file, # see _LINUX_SOURCE_DIR/Documentation/kbuild/config-language.txt. # mainmenu_name "SkyEye Configuration" # system wide options mainmenu_option next_comment comment 'Arch options' choice 'ARM system type' \ "ARM CONFIG_ARCH_ARM \ Blackfin CONFIG_ARCH_BLACKFIN \ Coldfire CONFIG_ARCH_COLDFIRE \ MIPS CONFIG_ARCH_MIPS " \ ARM if [ "$CONFIG_ARCH_ARM" = "y" ]; then choice 'Machine type' \ "AT91 CONFIG_MACH_AT91 \ LPC2229 CONFIG_MACH_LPC2229 \ S3C44b0 CONFIG_MACH_S3C44B0 \ S3C4510 CONFIG_MACH_S3C4510 \ EP7312 CONFIG_MACH_EP7312 \ EP9312 CONFIG_MACH_EP9312 \ AT91RM9200 CONFIG_MACH_RM9200 \ S3C2410 CONFIG_MACH_2410 \ StrongARM CONFIG_MACH_STRONGARM \ PXA255 CONFIG_MACH_PXA255 \ PXA27x CONFIG_MACH_PXA27x " AT91 fi dep_bool 'DBCT enable' CONFIG_DBCT $CONFIG_ARCH_ARM endmenu mainmenu_option next_comment comment 'Memory bank options' comment 'Memory bank1' hex ' start address' CONFIG_MEMBANK1_START_ADDR 0 hex ' size' CONFIG_MEMBANK1_SIZE 0 string 'type ' CONFIG_MEMBANK1_TYPE "" bool "Load image file in this bank" CONFIG_MEMBANK1_LOAD if ["$CONFIG_MEMBANK1_LOAD" = "y" ] ; then string "Image file path" CONFIG_MEMBANK1_FILE fi comment 'Memory Bank2 ' hex 'Start Address' CONFIG_MEMBANK2_START_ADDR 0 hex ' Size ' CONFIG_MEMBANK2_SIZE 0 string 'Type' CONFIG_MEMBANK2_TYPE "" endmenu # Netcard Simulation mainmenu_option next_comment comment 'Netcard Simulation' bool 'Netcard simulation' CONFIG_NETCARD hex 'Netcard Numbers' CONFIG_NETCARD_NUM choice 'Netcard Mode' \ " linux CONFIG_NETCARD_LINUX_MOD \ tuntap CONFIG_NETCARD_TUNTAP_MOD \ win CONFIG_NETCARD_WIN_MOD \ vnet CONFIG_NETCARD_VNET_MOD " tuntap string 'Mac address' CONFIG_NETCARD_MAC_ADDR "" string 'Host ip address' CONFIG_NETCARD_HOST_IP "10.0.0.1" endmenu # LCD engine options mainmenu_option next_comment comment 'LCD Simulation' bool 'LCD simulation' CONFIG_LCD hex 'Start Address' CONFIG_LCD1_START_ADDR 0 hex 'Size' CONFIG_LCD1_SIZE 0 choice 'LCD mode' \ "gtk CONFIG_LCD_MOD_GTK" gtk endmenu #FLASH engine options mainmenu_option next_comment comment 'Flash Simulation' bool 'Flash simulation' CONFIG_FLASH endmenu #log options mainmenu_option next_comment comment 'Log options' bool 'Log enable' CONFIG_LOG endmenu �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/configs/mkdefconfig������������������������������������������������������0000755�0001750�0000144�00000001441�10541455476�017763� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/sh # This script is used to make the default config file: defconfig. FEATURE_IN=feature.in DEFCONFIG=defconfig SAVEIFS=$IFS IFS== function check_def_yes () { if grep "$1" $CONFIGURE_HELP | grep "<default=yes>" > /dev/null; then return 0 else return -1 fi } echo "# default config file, made by mkdefconfig" > $DEFCONFIG echo "" >> $DEFCONFIG if [ -s $FEATURE_IN ]; then while read var_config feature do if [ "$feature" != "" ]; then if check_def_yes $feature; then echo $var_config=y >> $DEFCONFIG else echo $var_config=n >> $DEFCONFIG fi else echo $var_config >> $DEFCONFIG fi done < $FEATURE_IN fi echo \ "CONFIG_PLATFORM_LINUX=y CONFIG_COMPILER_X86=y CONFIG_LIBC_GLIBC=y" \ >> $DEFCONFIG IFS=$SAVEIFS �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/configs/feature.in�������������������������������������������������������0000644�0001750�0000144�00000007734�10541455476�017557� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������# # System wide options # CONFIG_LITE=lite CONFIG_STAND_ALONE=standalone CONFIG_INCORE_RES=incoreres CONFIG_TIMERUNIT10MS=timerunitm CONFIG_CURSORSUPPORT=cursor CONFIG_MOVEABLE=micemoveable CONFIG_DBCLK=dblclk CONFIG_DEBUG=debug CONFIG_TRACEMESSAGE=tracemsg CONFIG_MSGSTR=msgstr # # GAL engine options # CONFIG_NEWGAL=newgal CONFIG_GAL_NATIVE=nativegal CONFIG_GAL_NATIVE_QVFB=nativegalqvfb CONFIG_GAL_NATIVE_COORTRANS_CW=coortrans_cw CONFIG_GAL_NATIVE_COORTRANS_CCW=coortrans_ccw CONFIG_GAL_NATIVE_R1BPPFB=fblin1r CONFIG_GAL_NATIVE_L1BPPFB=fblin1l CONFIG_GAL_NATIVE_R2BPPFB=fblin2r CONFIG_GAL_NATIVE_L2BPPFB=fblin2l CONFIG_GAL_NATIVE_R4BPPFB=fblin4r CONFIG_GAL_NATIVE_L4BPPFB=fblin4l CONFIG_GAL_NATIVE_8BPPFB=fblin8 CONFIG_GAL_NATIVE_16BPPFB=fblin16 CONFIG_GAL_NATIVE_24BPPFB=fblin24 CONFIG_GAL_NATIVE_32BPPFB=fblin32 CONFIG_GAL_NATIVE_VGA16FB=fbvga16 CONFIG_GALIAL_SVGALIB=svgalib CONIFG_GALIAL_LIBGGI=libggi CONFIG_GAL_VGA16=vga16gal CONFIG_NEWGAL_FBCON=video-fbcon CONFIG_NEWGAL_QVFB=video-qvfb CONFIG_NEWGAL_DUMMY=video-dummy # # IAL engine options # CONFIG_IAL_EP7211=ep7211ial CONFIG_IAL_ADS=adsial CONFIG_IAL_IPAQ=ipaqial CONFIG_IAL_MPC823=mpc823ial CONFIG_IAL_VR4181=vr4181ial CONFIG_IAL_HELIO=helioial CONFIG_IAL_MTT800=t800ial CONFIG_IAL_DUMMY=dummyial CONFIG_IAL_NATIVE=nativeial CONFIG_IAL_MC68X328=mc68x328ial CONFIG_IAL_NATIVE_PS2MOUSE=nativeps2 CONFIG_IAL_NATIVE_IMPS2MOUSE=nativeimps2 CONFIG_IAL_NATIVE_MSMOUSE=nativems CONFIG_IAL_NATIVE_MS3MOUSE=nativems3 CONFIG_IAL_NATIVE_GPM=nativegpm # # Font options # CONFIG_FONT_RBF=rbfsupport CONFIG_FONT_INCOREGB12=rbfgb12 CONFIG_FONT_VBF=vbfsupport CONFIG_FONT_INCORESSERIF=fontsserif CONFIG_FONT_INCORECOURIER=fontcourier CONFIG_FONT_INCORESYMBOL=fontsymbol CONFIG_FONT_INCOREVGAS=fontvgas CONFIG_FONT_QPF=qpfsupport CONFIG_FONT_TTF=ttfsupport CONFIG_FONT_TYPE1=type1support # # Charset options # CONFIG_CHARSET_LATIN2=latin2support CONFIG_CHARSET_LATIN3=latin3support CONFIG_CHARSET_LATIN4=latin4support CONFIG_CHARSET_CYRILLIC=cyrillicsupport CONFIG_CHARSET_ARABIC=arabicsupport CONFIG_CHARSET_GREEK=greeksupport CONFIG_CHARSET_HEBREW=hebrewsupport CONFIG_CHARSET_LATIN5=latin5support CONFIG_CHARSET_LATIN6=latin6support CONFIG_CHARSET_THAI=thaisupport CONFIG_CHARSET_LATIN7=latin7support CONFIG_CHARSET_LATIN8=latin8support CONFIG_CHARSET_LATIN9=latin9support CONFIG_CHARSET_LATIN10=latin10support CONFIG_CHARSET_GB2312=gbsupport CONFIG_CHARSET_GBK=gbksupport CONFIG_CHARSET_GB18030=gb18030support CONFIG_CHARSET_BIG5=big5support CONFIG_CHARSET_EUCKR=euckrsupport CONFIG_CHARSET_EUCJP=eucjpsupport CONFIG_CHARSET_SHIFTJIS=shiftjissupport CONFIG_CHARSET_UNICODE=unicodesupport # # Keyboard layout specific options # CONFIG_KBD_FRPC=kbdfrpc CONFIG_KBD_FR=kbdfr CONFIG_KBD_DE=kbdde CONFIG_KBD_DELATIN1=kbddelatin1 CONFIG_KBD_IT=kbdit CONFIG_KBD_ES=kbdes CONFIG_KBD_ESCP850=kbdescp850 # # Image options # CONFIG_IMAGE_SAVEBMP=savebitmap CONFIG_IMAGE_PCX=pcxsupport CONFIG_IMAGE_LBM=lbmsupport CONFIG_IMAGE_TGA=tgasupport CONFIG_IMAGE_GIF=gifsupport CONFIG_IMAGE_JPG=jpgsupport CONFIG_IMAGE_PNG=pngsupport # # Input method options # CONFIG_IME_GB2312=imegb2312 CONFIG_IME_GB2312PINYIN=imegb2312py # # Appearance options # CONFIG_APPEARANCE_FLATSTYLE=flatstyle CONFIG_APPEARANCE_TINYSCR=tinyscreen # # Misc options # CONFIG_MISC_ABOUTDLG=aboutdlg CONFIG_MISC_SAVESCR=savescreen CONFIG_MISC_TEXTMODE=textmode # # Controls options # CONFIG_CTRL_STATIC=ctrlstatic CONFIG_CTRL_BUTTON=ctrlbutton CONFIG_CTRL_SIMEDIT=ctrlsimedit CONFIG_CTRL_SLEDIT=ctrlsledit CONFIG_CTRL_MLEDIT=ctrlmledit CONFIG_CTRL_LISTBOX=ctrllistbox CONFIG_CTRL_PROGRESSBAR=ctrlpgbar CONFIG_CTRL_TOOLBAR=ctrltoolbar CONFIG_CTRL_NEWTOOLBAR=ctrlnewtoolbar CONFIG_CTRL_MENUBUTTON=ctrlmenubtn CONFIG_CTRL_TRACKBAR=ctrltrackbar CONFIG_CTRL_COMBOBOX=ctrlcombobox CONFIG_CTRL_PROPSHEET=ctrlpropsheet # # Ext library options # CONFIG_EXT_TREEVIEW=extctrltreeview CONFIG_EXT_LISTVIEW=extctrllistview CONFIG_EXT_MONTHCAL=extctrlmonthcal CONFIG_EXT_SPINBOX=extctrlspinbox CONFIG_EXT_COOLBAR=extctrlcoolbar CONFIG_EXT_FULLGIF=extfullgif ������������������������������������skyeye-1.2.5_REL/misc/conf/configs/Makefile.am������������������������������������������������������0000644�0001750�0000144�00000000111�10541455476�017606� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������EXTRA_DIST=config.in Configure.help defconfig feature.in mkdefconfig �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/conf/makefile�����������������������������������������������������������������0000644�0001750�0000144�00000004053�10541455476�015633� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������MAJOR_VERSION = 1 MINOR_VERSION = 3 MICRO_VERSION = 0 EXTRAVERSION = MINIGUI_RELEASE=$(MAJOR_VERSION).$(MINOR_VERSION).$(MICRO_VERSION)$(EXTRAVERSION) # SUBARCH tells the usermode build what the underlying arch is. That is set # first, and if a usermode build is happening, the "ARCH=um" on the command # line overrides the setting of ARCH below. If a native build is happening, # then ARCH is assigned, getting whatever value it gets normally, and # SUBARCH is subsequently ignored. SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/) ARCH := $(SUBARCH) MINIGUI_PATH=kernel-$(shell echo $(MINIGUI_RELEASE) | sed -e "s/-//g") CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ else if [ -x /bin/bash ]; then echo /bin/bash; \ else echo sh; fi ; fi) TOPDIR := $(shell /bin/pwd) HPATH = $(TOPDIR)/include HOSTCC = gcc HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer CROSS_COMPILE = # # Include the make variables (CC, etc...) # AS = $(CROSS_COMPILE)as LD = $(CROSS_COMPILE)ld CC = $(CROSS_COMPILE)gcc CPP = $(CC) -E AR = $(CROSS_COMPILE)ar NM = $(CROSS_COMPILE)nm STRIP = $(CROSS_COMPILE)strip OBJCOPY = $(CROSS_COMPILE)objcopy OBJDUMP = $(CROSS_COMPILE)objdump MAKEFILES = $(TOPDIR)/.config GENKSYMS = /sbin/genksyms DEPMOD = /sbin/depmod KALLSYMS = /sbin/kallsyms MODFLAGS = -DMODULE CFLAGS_KERNEL = PERL = perl AWK = awk TMPPREFIX = export MAJOR_VERSION MINOR_VERSION MICRO_VERSION EXTRAVERSION MINIGUI_RELEASE ARCH \ CONFIG_SHELL TOPDIR HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC \ CPP AR NM STRIP OBJCOPY OBJDUMP MAKE MAKEFILES GENKSYMS MODFLAGS PERL AWK -include Makefile doit: @echo "You may need to run configure script to build Makefile." .PHONY : menuconfig menuconfig: $(MAKE) -C scripts/lxdialog -f makefile.lx all $(CONFIG_SHELL) scripts/Menuconfig configs/config.in .PHONY : defconfig defconfig: @cp configs/defconfig .defconfig $(MAKE) -C scripts/lxdialog -f makefile.lx all $(CONFIG_SHELL) scripts/Menuconfig configs/config.in @rm .defconfig �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/energy_prof/������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015500� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/misc/energy_prof/ksh_energy_skyeye_r301.diff���������������������������������������0000644�0001750�0000144�00000137147�10667242665�022671� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Index: utils/main/skyeye.c =================================================================== --- utils/main/skyeye.c (revision 301) +++ utils/main/skyeye.c (working copy) @@ -148,7 +148,7 @@ if (state->EndCondition == 0) { //chy 20050729 ???? - printf ("error in sim_resume for state->EndCondition"); + fprintf (stderr, "error in sim_resume for state->EndCondition"); skyeye_exit (-1); } } @@ -547,6 +547,14 @@ /* 2007-01-31 disabled by Anthony Lee on BeOS for multi-thread safe. */ void sigint_handler (int signum) { + if (state->energy.outfile) { + ARMul_ReportEnergy(state,state->energy.outfile); /* <tktan> BUG200104111423, BUG200105222137 */ + fprintf(state->energy.outfile, "total instructions = %lld\n", state->NumInstrs); + fprintf(state->energy.outfile, "total cycles = %lld\n", state->energy.tcycle) ; + fprintf(state->energy.outfile, "total energy = %lf\n", state->energy.t_energy) ; + fclose(state->energy.outfile); + } + longjmp (ctrl_c_cleanup, 1); } #endif Index: arch/arm/common/armsym.c =================================================================== --- arch/arm/common/armsym.c (revision 301) +++ arch/arm/common/armsym.c (working copy) @@ -22,133 +22,125 @@ #include "armdefs.h" -static char itoa_tab[16] = - { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', -'d', 'e', - 'f' -}; -static int storage_needed; +static char itoa_tab[16] = {'0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'} ; +static long storage_needed; static asymbol **symbol_table; -static unsigned int number_of_symbols, kernel_number; +static unsigned long number_of_symbols, kernel_number; -static SYM_FUNC trap_sym = { "Trap", 0, 0, 0 }; -static SYM_FUNC init_sym = { "Init", 0, 0, 0 }; /* <tktan> BUG200103311736 */ -static FUNC_NODE init_node = { &init_sym, 0, 0, 0 }; +static SYM_FUNC trap_sym = {"Trap", 0, 0, 0}; +static SYM_FUNC init_sym = {"Init", 0, 0, 0}; /* <tktan> BUG200103311736 */ +static FUNC_NODE init_node = {&init_sym, 0, 0,0}; static ARMword debug; #if 0 -void -ARMul_InitSymTable () +void ARMul_InitSymTable() { - int i, j, digit; - ENTRY newentry, *oldentry; - SYM_FUNC *symp; - asymbol *symptr; - int key; - bfd *appl_bfd; - bfd *abfd; - int appl_storage_needed; + long i,j, digit; + ENTRY newentry, *oldentry; + SYM_FUNC *symp; + asymbol *symptr; + int key; + bfd *appl_bfd; + bfd *abfd; + long appl_storage_needed; abfd = bfd_openr ("./vmlinux", 0); - /* <tktan> BUG200105221946 : get symbol from usrappl */ - appl_bfd = bfd_openr ("init/usrappl", 0); - if (appl_bfd == NULL) { - printf ("Can't open init/usrappl\n"); - exit (0); - } + /* <tktan> BUG200105221946 : get symbol from usrappl */ + appl_bfd = bfd_openr ("init/usrappl", 0); + if (appl_bfd == NULL) + { + printf("Can't open init/usrappl\n"); + exit(0); + } - if (!bfd_check_format (appl_bfd, bfd_object)) { - printf ("Wrong format\n"); - exit (0); - } + if (!bfd_check_format(appl_bfd, bfd_object)) { + printf("Wrong format\n") ; + exit(0); + } - appl_storage_needed = bfd_get_symtab_upper_bound (appl_bfd); - if (appl_storage_needed < 0) { - printf ("FAIL\n"); - exit (0); - } - /* <tktan> BUG200105221946 */ + appl_storage_needed = bfd_get_symtab_upper_bound(appl_bfd); + if (appl_storage_needed < 0){ + printf("FAIL\n"); + exit(0); + } + /* <tktan> BUG200105221946 */ - if (!bfd_check_format (abfd, bfd_object)) { - printf ("Wrong format\n"); - exit (0); - } + if (!bfd_check_format(abfd, bfd_object)) { + printf("Wrong format\n") ; + exit(0); + } - storage_needed = bfd_get_symtab_upper_bound (abfd); - if (storage_needed < 0) { - printf ("FAIL\n"); - exit (0); - } + storage_needed = bfd_get_symtab_upper_bound(abfd); + if (storage_needed < 0){ + printf("FAIL\n"); + exit(0); + } - // <tktan> BUG200105221946 :symbol_table = (asymbol **) malloc (storage_needed); - symbol_table = - (asymbol **) malloc (appl_storage_needed + storage_needed); + // <tktan> BUG200105221946 :symbol_table = (asymbol **) malloc (storage_needed); + symbol_table = (asymbol **) malloc (appl_storage_needed + storage_needed); - number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); - kernel_number = number_of_symbols; /* <tktan> BUG200106022219 */ + number_of_symbols = + bfd_canonicalize_symtab (abfd, symbol_table); + kernel_number = number_of_symbols; /* <tktan> BUG200106022219 */ - if (number_of_symbols < 0) { - printf ("FAIL\n"); - exit (0); - } + if (number_of_symbols < 0){ + printf("FAIL\n"); + exit(0); + } - /* <tktan> BUG200105221946 */ - number_of_symbols += - bfd_canonicalize_symtab (appl_bfd, - &(symbol_table[number_of_symbols])); + /* <tktan> BUG200105221946 */ + number_of_symbols += bfd_canonicalize_symtab(appl_bfd, &(symbol_table[number_of_symbols])); - // printf("Number of symbols = %d\n", number_of_symbols) ; + // printf("Number of symbols = %d\n", number_of_symbols) ; - if (!hcreate (number_of_symbols << 1)) { - printf ("Not enough memory for hash table\n"); - exit (0); - } - for (i = 0; i < number_of_symbols; i++) { - symptr = symbol_table[i]; - key = symptr->value + symptr->section->vma; // adjust for section address + if (!hcreate(number_of_symbols << 1)) { + printf("Not enough memory for hash table\n"); + exit(0); + } + for (i = 0; i < number_of_symbols; i++) { + symptr = symbol_table[i] ; + key = symptr->value + symptr->section->vma; // adjust for section address - if (((i < kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 - ((i < kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654 - (symbol_table[i]->flags & 0x10)) { // Is a function symbol - // printf("%x %8x %s\n", symbol_table[i]->flags, key, symbol_table[i]->name); + if (((i<kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 + ((i<kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654 + (symbol_table[i]->flags & 0x10)) { // Is a function symbol + // printf("%x %8x %s\n", symbol_table[i]->flags, key, symbol_table[i]->name); - // *********************************************************** - // This is converting the function symbol value to char string - // and use it as a key in the GNU hash table - // ******************************************************** - newentry.key = (char *) malloc (9); - for (j = 0; j < 8; j++) { - newentry.key[j] = - itoa_tab[((key) >> (j << 2)) & 0xf]; - } - newentry.key[8] = 0; + // *********************************************************** + // This is converting the function symbol value to char string + // and use it as a key in the GNU hash table + // ******************************************************** + newentry.key = (char *) malloc(9); + for (j=0;j<8;j++) { + newentry.key[j] = itoa_tab[((key) >> (j << 2)) & 0xf] ; + } + newentry.key[8] = 0 ; - // ************************************************* - // This is allocating memory for a struct funcsym - // ************************************************* - symp = (SYM_FUNC *) malloc (sizeof (SYM_FUNC)); - newentry.data = (char *) symp; - symp->name = (char *) symbol_table[i]->name; - symp->total_cycle = 0; - symp->total_energy = 0; - symp->instances = 0; + // ************************************************* + // This is allocating memory for a struct funcsym + // ************************************************* + symp = (SYM_FUNC *) malloc(sizeof(SYM_FUNC)); + newentry.data = (char *) symp; + symp->name = (char *) symbol_table[i]->name ; + symp->total_cycle = 0; + symp->total_energy = 0; + symp->instances = 0; - // *********************************************** - // Insert into hash table - // ******************************************* - /* <tktan> BUG200106022219 */ - oldentry = hsearch (newentry, FIND); - if (oldentry) { // was entered - // printf("Duplicate Symbol: %x %s\n", key, symp->name); - oldentry->data = (char *) symp; - } - else if (!hsearch (newentry, ENTER)) { - printf ("Insufficient memory\n"); - exit (0); - } - } - } + // *********************************************** + // Insert into hash table + // ******************************************* + /* <tktan> BUG200106022219 */ + oldentry = hsearch(newentry, FIND) ; + if (oldentry) { // was entered + // printf("Duplicate Symbol: %x %s\n", key, symp->name); + oldentry->data = (char *) symp ; + } else if (!hsearch(newentry, ENTER)) { + printf("Insufficient memory\n"); + exit(0) ; + } + } + } - return; + return; } #else @@ -161,103 +153,100 @@ **************************************************************************/ /*************** * added by ksh - ***************/ -void -ARMul_InitSymTable (char *filename) + ***************/ +void ARMul_InitSymTable(char* filename) { - int i, j, digit; - ENTRY newentry, *oldentry; - SYM_FUNC *symp; - asymbol *symptr; - int key; - bfd *abfd; - printf ("call ARMul_InitSymTable,kernle filename is %s. \n", - filename); + long i,j, digit; + ENTRY newentry, *oldentry; + SYM_FUNC *symp; + asymbol *symptr; + int key; + bfd *abfd; + printf("call ARMul_InitSymTable,kernle filename is %s. \n",filename); - if (!filename) { - printf ("Can not get correct kernel filename!Maybe your skyeye.conf have something wrong!\n"); - skyeye_exit (-1); + if(!filename){ + printf("Can not get correct kernel filename!Maybe your skyeye.conf have something wrong!\n"); + exit(-1); } - /* <tktan> BUG200105221946 : get symbol from usrappl */ - abfd = bfd_openr (filename, 0); + /* <tktan> BUG200105221946 : get symbol from usrappl */ + abfd = bfd_openr (filename, 0); - /* <tktan> BUG200105221946 : get symbol from usrappl */ + /* <tktan> BUG200105221946 : get symbol from usrappl */ - /* <tktan> BUG200105221946 */ + /* <tktan> BUG200105221946 */ - if (!bfd_check_format (abfd, bfd_object)) { - printf ("Wrong format\n"); - skyeye_exit (0); - } + if (!bfd_check_format(abfd, bfd_object)) { + printf("Wrong format\n") ; + exit(0); + } - storage_needed = bfd_get_symtab_upper_bound (abfd); - if (storage_needed < 0) { - printf ("FAIL\n"); - skyeye_exit (0); - } + storage_needed = bfd_get_symtab_upper_bound(abfd); + if (storage_needed < 0){ + printf("FAIL\n"); + exit(0); + } - // <tktan> BUG200105221946 :symbol_table = (asymbol **) malloc (storage_needed); - symbol_table = (asymbol **) malloc (storage_needed); + // <tktan> BUG200105221946 :symbol_table = (asymbol **) malloc (storage_needed); + symbol_table = (asymbol **) malloc (storage_needed); - number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); - kernel_number = number_of_symbols; /* <tktan> BUG200106022219 */ + number_of_symbols = + bfd_canonicalize_symtab (abfd, symbol_table); + kernel_number = number_of_symbols; /* <tktan> BUG200106022219 */ - if (number_of_symbols < 0) { - printf ("FAIL\n"); - skyeye_exit (0); - } + if (number_of_symbols < 0){ + printf("FAIL\n"); + exit(0); + } - if (!hcreate (number_of_symbols << 1)) { - printf ("Not enough memory for hash table\n"); - skyeye_exit (0); - } - for (i = 0; i < number_of_symbols; i++) { - symptr = symbol_table[i]; - key = symptr->value + symptr->section->vma; // adjust for section address + if (!hcreate(number_of_symbols << 1)) { + printf("Not enough memory for hash table\n"); + exit(0); + } + for (i = 0; i < number_of_symbols; i++) { + symptr = symbol_table[i] ; + key = symptr->value + symptr->section->vma; // adjust for section address - if (((i < kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 - ((i < kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654 - (symbol_table[i]->flags & 0x10)) { // Is a function symbol - // printf("%x %8x %s\n", symbol_table[i]->flags, key, symbol_table[i]->name); + if (((i<kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 + ((i<kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654 + (symbol_table[i]->flags & 0x10)) { // Is a function symbol + // printf("%x %8x %s\n", symbol_table[i]->flags, key, symbol_table[i]->name); - // *********************************************************** - // This is converting the function symbol value to char string - // and use it as a key in the GNU hash table - // ******************************************************** - newentry.key = (char *) malloc (9); - for (j = 0; j < 8; j++) { - newentry.key[j] = - itoa_tab[((key) >> (j << 2)) & 0xf]; - } - newentry.key[8] = 0; + // *********************************************************** + // This is converting the function symbol value to char string + // and use it as a key in the GNU hash table + // ******************************************************** + newentry.key = (char *) malloc(9); + for (j=0;j<8;j++) { + newentry.key[j] = itoa_tab[((key) >> (j << 2)) & 0xf] ; + } + newentry.key[8] = 0 ; - // ************************************************* - // This is allocating memory for a struct funcsym - // ************************************************* - symp = (SYM_FUNC *) malloc (sizeof (SYM_FUNC)); - newentry.data = (char *) symp; - symp->name = (char *) symbol_table[i]->name; - symp->total_cycle = 0; - symp->total_energy = 0; - symp->instances = 0; + // ************************************************* + // This is allocating memory for a struct funcsym + // ************************************************* + symp = (SYM_FUNC *) malloc(sizeof(SYM_FUNC)); + newentry.data = (char *) symp; + symp->name = (char *) symbol_table[i]->name ; + symp->total_cycle = 0; + symp->total_energy = 0; + symp->instances = 0; - // *********************************************** - // Insert into hash table - // ******************************************* - /* <tktan> BUG200106022219 */ - oldentry = hsearch (newentry, FIND); - if (oldentry) { // was entered - // printf("Duplicate Symbol: %x %s\n", key, symp->name); - oldentry->data = (char *) symp; - } - else if (!hsearch (newentry, ENTER)) { - printf ("Insufficient memory\n"); - skyeye_exit (0); - } - } - } + // *********************************************** + // Insert into hash table + // ******************************************* + /* <tktan> BUG200106022219 */ + oldentry = hsearch(newentry, FIND) ; + if (oldentry) { // was entered + // printf("Duplicate Symbol: %x %s\n", key, symp->name); + oldentry->data = (char *) symp ; + } else if (!hsearch(newentry, ENTER)) { + printf("Insufficient memory\n"); + exit(0) ; + } + } + } - return; + return; } #endif /*************************************************************** @@ -265,453 +254,426 @@ If it exists, the corresponding pointer to the SYM_FUNC will be returned *************************************************************/ -SYM_FUNC * -ARMul_GetSym (ARMword address) +SYM_FUNC *ARMul_GetSym(ARMword address) { - int j; - ENTRY entry, *ep; - char text[9]; - SYM_FUNC *symp; + int j ; + ENTRY entry, *ep; + char text[9] ; + SYM_FUNC *symp; - //printf("GetSym %x\n", address); - entry.key = text; - for (j = 0; j < 8; j++) { - entry.key[j] = itoa_tab[(address >> (j << 2)) & 0xf]; - } - entry.key[8] = 0; + //printf("GetSym %x\n", address); + entry.key = text ; + for (j=0;j<8;j++) { + entry.key[j] = itoa_tab[(address >> (j << 2)) & 0xf] ; + } + entry.key[8] = 0 ; /*a bug need to fixed */ - ep = hsearch (entry, FIND); + ep = hsearch(entry, FIND) ; - if (ep != 0) { - symp = (SYM_FUNC *) ep->data; - return (symp); - } - else + if (ep != 0) { + symp = (SYM_FUNC *) ep->data; + return(symp); + } else - return (0); + return(0); } /*************************************** * Function to initialize the energy profiling tree root ***************************************************/ -void -ARMul_ProfInit (ARMul_State * state) -{ /* <tktan> BUG200103311736 */ - TASK_STACK *tsp; - printf ("call ARMul_ProfInit \n"); - tsp = malloc (sizeof (TASK_STACK)); - if (tsp <= 0) { - printf ("Memory allocation error in ARMul_ProfInit \n"); - skyeye_exit (-1); +void ARMul_ProfInit(ARMul_State *state) /* <tktan> BUG200103311736 */ + +{ + TASK_STACK *tsp; + printf("call ARMul_ProfInit \n"); + tsp = malloc(sizeof(TASK_STACK)); + if(tsp <= 0){ + printf("Memory allocation error in ARMul_ProfInit \n"); + exit(-1); } - state->energy.cur_task = (void *) tsp; - tsp->task_id = 0xc00f0000; // where the INIT_TASK reside - memcpy (&(tsp->func_stack[0]), &init_node, sizeof (FUNC_NODE)); - tsp->level = 0; - tsp->total_energy = 0; - tsp->total_cycle = 0; - tsp->next = tsp; + state->energy.cur_task = (void *) tsp; + //tsp->thread_id = 0xc00f0000; // where the INIT_TASK reside + //tsp->thread_id = 0xc023bbe4; + tsp->thread_id = 0xc0236000; + memcpy(&(tsp->func_stack[0]), &init_node, sizeof(FUNC_NODE)); + tsp->level=0; + tsp->total_energy=0; + tsp->total_cycle=0; + tsp->next = tsp; - return; + return; } - + /**************************************** * Function to create child function node ****************************************/ -FUNC_NODE * -ARMul_CreateChild (ARMul_State * state) +FUNC_NODE *ARMul_CreateChild(ARMul_State *state) { - TASK_STACK *tsp; - int level; - FUNC_NODE *fnp; - - tsp = (TASK_STACK *) state->energy.cur_task; - (tsp->level)++; - level = tsp->level; - /* <tktan> BUG200105311233 */ - if (level >= MAX_LEVEL) { - printf ("ARMul_CreateChild failed\n"); - assert (0); - } - - fnp = &(tsp->func_stack[level]); + TASK_STACK *tsp; + int level; + FUNC_NODE *fnp; + + tsp = (TASK_STACK *) state->energy.cur_task; + (tsp->level)++; + level = tsp->level; + /* <tktan> BUG200105311233 */ + if (level >= MAX_LEVEL) { + printf("ARMul_CreateChild failed\n"); + assert(0); + } + + fnp = &(tsp->func_stack[level]); // printf("Create Child!\n "); - fnp->tenergy = tsp->total_energy; - fnp->tcycle = tsp->total_cycle; - return (fnp); + fnp->tenergy = tsp->total_energy; + fnp->tcycle = tsp->total_cycle; + return(fnp); } /****************************************** * Function to destroy child nodes *****************************************/ -void -ARMul_DestroyChild (ARMul_State * state) +void ARMul_DestroyChild(ARMul_State *state) { - TASK_STACK *tsp; - int level; - long long fenergy; - long long fcycle; - FUNC_NODE *fnp; + TASK_STACK *tsp; + int level; + long long fenergy; + long long fcycle; + FUNC_NODE *fnp; - tsp = (TASK_STACK *) state->energy.cur_task; - level = tsp->level; - fnp = &(tsp->func_stack[level]); - // <tktan> BUG200105222137 fenergy = state->t_energy - fnp->tenergy; - fenergy = tsp->total_energy - fnp->tenergy; - fcycle = tsp->total_cycle - fnp->tcycle; + tsp = (TASK_STACK *) state->energy.cur_task; + level = tsp->level; + fnp = &(tsp->func_stack[level]); + // <tktan> BUG200105222137 fenergy = state->t_energy - fnp->tenergy; + fenergy = tsp->total_energy - fnp->tenergy; + fcycle = tsp->total_cycle - fnp->tcycle; - /* <tktan> BUG200105181702 */ - if ((state->energy.enable_func_energy) - && !(strcmp (state->energy.func_energy, fnp->func_symbol->name))) { - printf ("energy_report %s %f\n", fnp->func_symbol->name, - fenergy); - } - - /* <tktan> BUG200104101936 */ - if (state->energy.energy_prof) { - fnp->func_symbol->total_energy += fenergy; - fnp->func_symbol->total_cycle += fcycle; - (fnp->func_symbol->instances)++; - } - //printf("Destroy child,name %s \n",fnp->func_symbol->name); - tsp->level = level - 1; - return; + /* <tktan> BUG200105181702 */ + if ((state->energy.enable_func_energy) && !(strcmp(state->energy.func_energy, fnp->func_symbol->name))) { + printf("energy_report %s %f\n", fnp->func_symbol->name, fenergy); + } + + /* <tktan> BUG200104101936 */ + if (state->energy.energy_prof) { + fnp->func_symbol->total_energy += fenergy; + fnp->func_symbol->total_cycle += fcycle; + (fnp->func_symbol->instances)++; + } + //printf("Destroy child,name %s \n",fnp->func_symbol->name); + tsp->level = level - 1; + return; } /************************************************ Function to check the different kind of branch ************************************************/ -void -ARMul_CallCheck (ARMul_State * state, ARMword cur_pc, ARMword to_pc, - ARMword instr) +void ARMul_CallCheck(ARMul_State *state, ARMword cur_pc, ARMword to_pc, ARMword instr) { - FUNC_NODE *child_node; - TASK_STACK *tsp; - SYM_FUNC *symp; - int i, bt, level; - ARMword new_task_id, fp_value; + FUNC_NODE *child_node ; + TASK_STACK *tsp; + SYM_FUNC *symp; + int i, bt, level; + ARMword new_thread_id, fp_value; - tsp = (TASK_STACK *) state->energy.cur_task; - level = tsp->level; - fp_value = state->Reg[11]; // BUG200311301153 + tsp = (TASK_STACK *) state->energy.cur_task; + level = tsp->level; + fp_value = state->Reg[11]; // BUG200311301153 #if 0 - if (debug != tsp->task_id || !debug) { - printf ("cur_task is changed! %x \n", tsp->task_id); - debug = tsp->task_id; - } +if(debug != tsp->thread_id || !debug){ + printf("cur_task is changed! %x \n",tsp->thread_id); + debug = tsp->thread_id; +} #endif - /* <tktan> BUG200105311233 */ - if (level >= MAX_LEVEL) { - printf ("ARMul_CallCheck failed\n"); - printf ("level %d \n", level); - //exit(-1); - } - // First check if it is normal return - if (to_pc == (tsp->func_stack[level].ret_addr + 4)) { - if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ - //if(1){ - printf ("[%x:%d:%x] Function return %s (%x)--> %s (%x)\n", tsp->task_id, level, fp_value, tsp->func_stack[level].func_symbol->name, cur_pc, tsp->func_stack[level - 1].func_symbol->name, to_pc); - } + /* <tktan> BUG200105311233 */ + if (level >= MAX_LEVEL) { + printf("ARMul_CallCheck failed\n"); + printf("level %d \n",level); + //exit(-1); + } + // First check if it is normal return + if (to_pc == (tsp->func_stack[level].ret_addr+4)) { + if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ + //if(1){ + printf("[%x:%d:%x] Function return %s (%x)--> %s (%x)\n", tsp->thread_id, level, fp_value, \ + tsp->func_stack[level].func_symbol->name, cur_pc, tsp->func_stack[level-1].func_symbol->name, to_pc); + } - /* <tktan> BUG200104101736 */ - ARMul_DestroyChild (state); + /* <tktan> BUG200104101736 */ + ARMul_DestroyChild(state); - return; - } - // Check if it is a trap return - // a trap return is one that jump to a saved interrupted address, saved - // in .ret_addr - bt = 0; - while ((level - bt >= 0) && (bt <= 3)) { - if (to_pc == tsp->func_stack[level - bt].ret_addr) { - if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ - printf ("[%x:%d:%x] Trap Return -> %s\n", - tsp->task_id, level, fp_value, - tsp->func_stack[level - bt - - 1].func_symbol->name); - } + return; + } + // Check if it is a trap return + // a trap return is one that jump to a saved interrupted address, saved + // in .ret_addr + bt = 0; + while ((level - bt >= 0) && (bt <= 3)) { + if (to_pc == tsp->func_stack[level-bt].ret_addr) { + if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ + printf("[%x:%d:%x] Trap Return -> %s\n", tsp->thread_id, level, fp_value, \ + tsp->func_stack[level-bt-1].func_symbol->name); + } - /* <tktan> BUG200104101736 */ - for (i = 0; i <= bt; i++) { - ARMul_DestroyChild (state); - } + /* <tktan> BUG200104101736 */ + for (i=0;i<=bt;i++) { + ARMul_DestroyChild(state); + } - return; - } - bt++; - } + return; + } + bt++; + } - // BUG200311212039 - // check if it is a recursive call, or I was missing some returns through - // abnormal jumps - bt = 0; - while ((level - bt >= 0) && (bt <= 2)) { - if (to_pc == tsp->func_stack[level - bt].func_start_addr) { - if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ - printf ("[%x:%d:%x] Function %s ended\n", - tsp->task_id, level, fp_value, - tsp->func_stack[level - - bt].func_symbol-> - name); - } + // BUG200311212039 + // check if it is a recursive call, or I was missing some returns through + // abnormal jumps + bt = 0; + while ((level - bt >=0) && (bt <=2)) { + if (to_pc == tsp->func_stack[level-bt].func_start_addr) { + if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ + printf("[%x:%d:%x] Function %s ended\n", tsp->thread_id, level, fp_value, \ + tsp->func_stack[level-bt].func_symbol->name); + } + + /* <tktan> BUG200104101736 */ + for (i=0;i<=bt;i++) { + ARMul_DestroyChild(state); + } - /* <tktan> BUG200104101736 */ - for (i = 0; i <= bt; i++) { - ARMul_DestroyChild (state); - } + } + bt++; + } + tsp = (TASK_STACK *) state->energy.cur_task; + level = tsp->level; + + // check if it is a trap + //if (!(to_pc & 0xffffffe0) && (state->Reg[14] == (cur_pc+4))) { // check for pc from 0x0 - 0x1f + // BUG200311302126: Reg[14]_abt is cur_pc+8 for DataAbort, + // but cur_pc+4 for other exception. So, better not check it + if (!(to_pc & 0xffffffe0)) { // check for pc from 0x0 - 0x1f + child_node = ARMul_CreateChild(state); /* <tktan> BUG200104101736 */ + child_node->ret_addr = cur_pc; + child_node->func_start_addr = to_pc; + child_node->func_symbol = &trap_sym ; - } - bt++; - } - tsp = (TASK_STACK *) state->energy.cur_task; - level = tsp->level; + if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ + printf("[%x:%d:%x] Function %s(%x) --> Trap %x\n", tsp->thread_id, level, fp_value, \ + tsp->func_stack[level].func_symbol->name, cur_pc, to_pc); + } + return; + } - // check if it is a trap - //if (!(to_pc & 0xffffffe0) && (state->Reg[14] == (cur_pc+4))) { // check for pc from 0x0 - 0x1f - // BUG200311302126: Reg[14]_abt is cur_pc+8 for DataAbort, - // but cur_pc+4 for other exception. So, better not check it - if (!(to_pc & 0xffffffe0)) { // check for pc from 0x0 - 0x1f - child_node = ARMul_CreateChild (state); /* <tktan> BUG200104101736 */ - child_node->ret_addr = cur_pc; - child_node->func_start_addr = to_pc; - child_node->func_symbol = &trap_sym; + // Check if it is a function call - if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ - printf ("[%x:%d:%x] Function %s(%x) --> Trap %x\n", - tsp->task_id, level, fp_value, - tsp->func_stack[level].func_symbol->name, - cur_pc, to_pc); - } - return; - } + if ((state->Reg[14] == (cur_pc+4)) || /* <tktan> BUG200105172030 */ + (BITS(20,27) & 0xf0) == 0xb0) { /* <tktan> BUG200104012116 */ - // Check if it is a function call + symp = ARMul_GetSym(to_pc) ; + if (symp) { + // it is an entry into a function + child_node = ARMul_CreateChild(state); /* <tktan> BUG2001040101736 */ + child_node->ret_addr = cur_pc; + child_node->func_start_addr = to_pc; + child_node->func_symbol = symp; - if ((state->Reg[14] == (cur_pc + 4)) || /* <tktan> BUG200105172030 */ - (BITS (20, 27) & 0xf0) == 0xb0) { /* <tktan> BUG200104012116 */ - symp = ARMul_GetSym (to_pc); - if (symp) { - // it is an entry into a function - child_node = ARMul_CreateChild (state); /* <tktan> BUG2001040101736 */ - child_node->ret_addr = cur_pc; - child_node->func_start_addr = to_pc; - child_node->func_symbol = symp; + /* <tktan> BUG200105211055 : perform task switch */ + if (!strcmp(symp->name, "__switch_to")) { // BUG200204021340 + ARMul_TaskSwitch(state); + } + if (!strcmp(symp->name, "copy_thread")) { + new_thread_id = ARMul_TaskCreate(state); + } + } - - /* <tktan> BUG200105211055 : perform task switch */ - if (!strcmp (symp->name, "__switch_to")) { // BUG200204021340 - ARMul_TaskSwitch (state); - } - if (!strcmp (symp->name, "copy_thread")) { - new_task_id = ARMul_TaskCreate (state); - } - } - - } /* <tktan> BUG200104012116 */ - // Just a normal branch, maybe - return; + } /* <tktan> BUG200104012116 */ + // Just a normal branch, maybe + return; } /* <tktan> BUG200105211055 : perform task switch */ -void -ARMul_TaskSwitch (ARMul_State * state) +void ARMul_TaskSwitch(ARMul_State *state) { - TASK_STACK *ctsp, *oldtsp, *newtsp; - //ARMword to_thread_id; - ARMword to_task_id; - int done = 0; + TASK_STACK *ctsp, *oldtsp, *newtsp; + ARMword to_thread_id; + //ARMword to_thread_id; + int done=0; - //to_thread_id = state->Reg[2] ; // r1, the to_task task structure - to_task_id = state->Reg[7]; - oldtsp = (TASK_STACK *) state->energy.cur_task; - //printf("cur_task id %x \n",state->Reg[0]); - oldtsp->task_id = state->Reg[0]; /* <tktan> BUG200106051701 */ - //printf("Task ThreadInfo Switch from %x to %x\n", oldtsp->thread_id, to_thread_id); - //printf("task switch from %x to %x \n",oldtsp->task_id,to_task_id); - ctsp = oldtsp->next; - while (!done && (ctsp != oldtsp)) { - if (ctsp->task_id == to_task_id) { - done = 1; - newtsp = ctsp; - } -// printf("ctsp taskid=%x,next task_id=%x \n",ctsp->task_id,ctsp->next->task_id); - ctsp = ctsp->next; - } - - if (done) - state->energy.cur_task = (void *) newtsp; - else { - printf ("Error : Can not find task stack\n"); - //print_allTask(state); - skyeye_exit (-1); - } + to_thread_id = state->Reg[2] ; // r1, the to_task task structure + //to_thread_id = state->Reg[7]; + oldtsp = (TASK_STACK *) state->energy.cur_task; + //printf("cur_task id %x \n",state->Reg[0]); + oldtsp->thread_id = state->Reg[1]; /* <tktan> BUG200106051701 */ + //printf("Task ThreadInfo Switch from %x to %x\n", oldtsp->thread_id, to_thread_id); + //printf("task switch from %x to %x \n",oldtsp->thread_id,to_thread_id); + ctsp = oldtsp->next; + while (!done && (ctsp != oldtsp)) { + if (ctsp->thread_id == to_thread_id) { + done = 1; + newtsp = ctsp; + } + //printf("ctsp taskid=%x,next thread_id=%x \n",ctsp->thread_id,ctsp->next->thread_id); + ctsp = ctsp->next; + } + + if (done) + state->energy.cur_task = (void *) newtsp; + else { + printf("Error : Can not find task stack\n"); + //print_allTask(state); + exit(-1); + } } -void -print_allTask (ARMul_State * state) -{ +void print_allTask(ARMul_State *state){ TASK_STACK *ctsp, *oldtsp, *newtsp; - ARMword to_task_id; + ARMword to_thread_id; - oldtsp = (TASK_STACK *) state->energy.cur_task; - ctsp = oldtsp; + oldtsp = (TASK_STACK *) state->energy.cur_task; + ctsp = oldtsp; #if 0 - printf ("Begin to print all task...\n"); - do { - printf ("ctsp taskid=%x,next task_id=%x \n", ctsp->task_id, - ctsp->next->task_id); - ctsp = ctsp->next; - } - while (ctsp != oldtsp); - printf ("End to print....\n"); +printf("Begin to print all task...\n"); +do{ + printf("ctsp taskid=%x,next thread_id=%x \n",ctsp->thread_id,ctsp->next->thread_id); + ctsp = ctsp->next; +}while(ctsp != oldtsp); +printf("End to print....\n"); #endif } - -/* <tktan> BUG200105211055 : create new task stack */ -ARMword -ARMul_TaskCreate (ARMul_State * state) +/* <tktan> BUG200105211055 : create new task stack */ +ARMword ARMul_TaskCreate(ARMul_State *state) { - TASK_STACK *oldtsp, *newtsp, *oldnext; - ARMword to_task_id; - int i; + TASK_STACK *oldtsp, *newtsp, *oldnext; + ARMword to_thread_id; + int i; - to_task_id = state->Reg[3]; // r3, the to_task task structure - if (to_task_id == 0x00000000) { // BUG200204081717 - to_task_id = state->Reg[5]; // r5 store the to_task task structure - } + /* get thread_id according to copy_thread function in arch/arm/kernel/process.c */ + unsigned long task_p = mem_read_word(state, state->Reg[13]); + to_thread_id = mem_read_word(state, (task_p + 4)); + //to_thread_id = state->Reg[3] ; // r3, the to_task task structure + if (to_thread_id == 0x00000000) { // BUG200204081717 + to_thread_id = state->Reg[5] ; // r5 store the to_task task structure + } - oldtsp = (TASK_STACK *) state->energy.cur_task; + oldtsp = (TASK_STACK *) state->energy.cur_task; - newtsp = malloc (sizeof (TASK_STACK)); - memcpy (newtsp, oldtsp, sizeof (TASK_STACK)); - newtsp->task_id = to_task_id; - newtsp->level -= 2; // point to the SWI level + newtsp = malloc(sizeof(TASK_STACK)); + memcpy(newtsp, oldtsp, sizeof(TASK_STACK)); + newtsp->thread_id = to_thread_id; + newtsp->level -= 2; // point to the SWI level + + /* <tktan> BUG200105222137 */ + newtsp->total_cycle = 0; + // newtsp->total_energy = 0.0; BUG200106142205, possible problem + newtsp->total_energy = 0; + for (i=0;i<=newtsp->level;i++) { + newtsp->func_stack[i].tcycle = 0; + newtsp->func_stack[i].tenergy = 0; + } - /* <tktan> BUG200105222137 */ - newtsp->total_cycle = 0; - // newtsp->total_energy = 0.0; BUG200106142205, possible problem - newtsp->total_energy = 0; - for (i = 0; i <= newtsp->level; i++) { - newtsp->func_stack[i].tcycle = 0; - newtsp->func_stack[i].tenergy = 0; - } - - /* put newtsp after oldtsp */ - oldnext = oldtsp->next; - oldtsp->next = newtsp; - newtsp->next = oldnext; - //printf("Create a new task,task_id=%x \n",to_task_id); + /* put newtsp after oldtsp */ + oldnext = oldtsp->next; + oldtsp->next = newtsp; + newtsp->next = oldnext; +// printf("Create a new task,thread_id=%x \n",to_thread_id); //print_allTask(state); - return (to_task_id); + return(to_thread_id); } /******************************************** * Function to report energy tree *******************************************/ -void -ARMul_ReportEnergy (ARMul_State * state, FILE * pf) +void ARMul_ReportEnergy(ARMul_State *state, FILE* pf) { - int i, j; - ENTRY entry, *ep; - char text[9]; - SYM_FUNC *symp; - asymbol *symptr; - ARMword address; - TASK_STACK *ctsp, *oldtsp; - float energy; + int i, j; + ENTRY entry, *ep; + char text[9]; + SYM_FUNC *symp; + asymbol *symptr; + ARMword address; + TASK_STACK *ctsp, *oldtsp; + float energy; - ARMul_Consolidate (state); // <tktan> BUG200105222137 + ARMul_Consolidate(state); // <tktan> BUG200105222137 - for (i = 0; i < number_of_symbols; i++) { - symptr = symbol_table[i]; - address = symptr->value + symptr->section->vma; // adjust for section address + for(i=0;i<number_of_symbols;i++) { + symptr = symbol_table[i] ; + address = symptr->value + symptr->section->vma; // adjust for section address - if (((i < kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 - ((i < kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654, BUG200311211406 - (symbol_table[i]->flags & 0x10)) { // Is a function symbol + if (((i<kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 + ((i<kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654, BUG200311211406 + (symbol_table[i]->flags & 0x10)) { // Is a function symbol - // *********************************************************** - // This is converting the function symbol value to char string - // and use it as a key in the GNU hash table - // ******************************************************** - entry.key = text; - for (j = 0; j < 8; j++) { - entry.key[j] = - itoa_tab[(address >> (j << 2)) & 0xf]; - } - entry.key[8] = 0; + // *********************************************************** + // This is converting the function symbol value to char string + // and use it as a key in the GNU hash table + // ******************************************************** + entry.key = text ; + for (j=0;j<8;j++) { + entry.key[j] = itoa_tab[(address >> (j << 2)) & 0xf] ; + } + entry.key[8] = 0 ; - ep = hsearch (entry, FIND); - if (ep != 0) { - symp = (SYM_FUNC *) ep->data; - /*modified by ksh for evaluate the usrappl program only */ - /* - if(strncmp(symp->name,"usrappl",7) != 0){ - continue; - } - */ - if (symp->instances > 0) { // only show if executed - energy = symp->total_energy; - fprintf (pf, "%s %d %lld %f\n", - symp->name, symp->instances, - symp->total_cycle, energy); - } - } + ep = hsearch(entry, FIND) ; + if (ep != 0) { + symp = (SYM_FUNC *) ep->data; + /*modified by ksh for evaluate the usrappl program only*/ + /* + if(strncmp(symp->name,"usrappl",7) != 0){ + continue; } + */ + if (symp->instances > 0) {// only show if executed + energy = symp->total_energy; + fprintf(pf,"%s %d %lld %f\n", symp->name, symp->instances, symp->total_cycle, energy); } + } + } + } - /* <tktan> BUG200105222137 : print out task energy */ - oldtsp = (TASK_STACK *) state->energy.cur_task; - ctsp = oldtsp; - do { - energy = ctsp->total_energy; - fprintf (pf, "Task[%x] %lld %f\n", ctsp->task_id, - ctsp->total_cycle, energy); - ctsp = ctsp->next; - } - while (ctsp != oldtsp); + /* <tktan> BUG200105222137 : print out task energy */ + oldtsp = (TASK_STACK *) state->energy.cur_task; + ctsp = oldtsp; + fprintf(pf, "TASK_ID Cycles Energy\n"); + do { + energy = ctsp->total_energy; + fprintf(pf,"Task[%x] %lld %f\n", ctsp->thread_id, ctsp->total_cycle, energy); + ctsp = ctsp->next; + } while (ctsp != oldtsp); } /* <tktan> BUG200105222137 : consolidate unfinished function energy */ -void -ARMul_Consolidate (ARMul_State * state) +void ARMul_Consolidate(ARMul_State *state) { - long long fenergy; // <tktan> BUG200106142205 - long long fcycle; // <tktan> BUG200106142205 - FUNC_NODE *fnp; - TASK_STACK *ctsp, *oldtsp; - int i; - double energy; + long long fenergy; // <tktan> BUG200106142205 + long long fcycle; // <tktan> BUG200106142205 + FUNC_NODE *fnp; + TASK_STACK *ctsp, *oldtsp; + int i; + double energy; - /* <tktan> BUG200105222137 : report energy for tasks */ - /* <tktan> BUG200106041235 : use do instead of while */ - oldtsp = (TASK_STACK *) state->energy.cur_task; - ctsp = oldtsp; - do { - for (i = ctsp->level; i >= 0; i--) { - fnp = &(ctsp->func_stack[i]); - fenergy = ctsp->total_energy - fnp->tenergy; - fcycle = ctsp->total_cycle - fnp->tcycle; + /* <tktan> BUG200105222137 : report energy for tasks */ + /* <tktan> BUG200106041235 : use do instead of while */ + oldtsp = (TASK_STACK *) state->energy.cur_task; + ctsp = oldtsp; + do { + for (i=ctsp->level;i>=0;i--) { + fnp = &(ctsp->func_stack[i]); + fenergy = ctsp->total_energy - fnp->tenergy; + fcycle = ctsp->total_cycle - fnp->tcycle; - /* copied from <tktan> BUG200105181702 */ - if ((state->energy.enable_func_energy) - && - !(strcmp - (state->energy.func_energy, - fnp->func_symbol->name))) { - //energy = I2ENERGY(fenergy); - //fprintf(pf,"energy_report %s %f\n", fnp->func_symbol->name, energy); - } + /* copied from <tktan> BUG200105181702 */ + if ((state->energy.enable_func_energy) && !(strcmp(state->energy.func_energy, fnp->func_symbol->name))) { + //energy = I2ENERGY(fenergy); + //fprintf(pf,"energy_report %s %f\n", fnp->func_symbol->name, energy); + } - /* copied from <tktan> BUG200104101936 */ - fnp->func_symbol->total_energy += fenergy; - fnp->func_symbol->total_cycle += fcycle; - (fnp->func_symbol->instances)++; - } - ctsp = ctsp->next; - } - while (ctsp != oldtsp); + /* copied from <tktan> BUG200104101936 */ + fnp->func_symbol->total_energy += fenergy; + fnp->func_symbol->total_cycle += fcycle; + (fnp->func_symbol->instances)++; + } + ctsp = ctsp->next; + } while (ctsp != oldtsp); } Index: arch/arm/common/armsym.h =================================================================== --- arch/arm/common/armsym.h (revision 301) +++ arch/arm/common/armsym.h (working copy) @@ -20,43 +20,41 @@ #include "armdefs.h" -struct sym_func -{ - char *name; - long long total_energy; // for all instances - long long total_cycle; // for all instances - int instances; // number of instances +struct sym_func { + char *name; + long long total_energy; // for all instances + long long total_cycle; // for all instances + int instances; // number of instances }; typedef struct sym_func SYM_FUNC; -struct sym_funcinst -{ - /* Function Info */ - SYM_FUNC *func_symbol; - ARMword func_start_addr; // the address at which this function starts - ARMword ret_addr; // the PC at which we make sub-routine call +struct sym_funcinst { + /* Function Info */ + SYM_FUNC *func_symbol; + ARMword func_start_addr; // the address at which this function starts + ARMword ret_addr; // the PC at which we make sub-routine call - /* Profiling Data */ - float tenergy; - long long tcycle; + /* Profiling Data */ + float tenergy; + long long tcycle; }; #define MAX_LEVEL 1024 -struct sym_taskinst -{ - ARMword task_id; // Actually is the pointer to Linux struct task_struct - /* Task call stack */ - struct sym_funcinst func_stack[MAX_LEVEL]; - int level; +struct sym_taskinst { + //ARMword task_id; // Actually is the pointer to Linux struct task_struct + ARMword thread_id; // Actually is the pointer to Linux struct thread_info + /* Task call stack */ + struct sym_funcinst func_stack[MAX_LEVEL]; + int level; - /* Profiling Data */ - float total_energy; - long long total_cycle; + /* Profiling Data */ + float total_energy; + long long total_cycle; - /* link data */ - struct sym_taskinst *next; + /* link data */ + struct sym_taskinst *next; }; typedef struct sym_funcinst FUNC_NODE; @@ -66,14 +64,14 @@ Function declaration ******************************************************/ //void ARMul_InitSymTable(bfd *abfd); -SYM_FUNC *ARMul_GetSym (ARMword address); -void ARMul_ProfInit (ARMul_State * state); -FUNC_NODE *ARMul_CreateChild (ARMul_State * state); -void ARMul_DestroyChild (ARMul_State * state); -void ARMul_CallCheck (ARMul_State * state, ARMword cur_pc, ARMword to_pc, - ARMword instr); -void ARMul_TaskSwitch (ARMul_State * state); -ARMword ARMul_TaskCreate (ARMul_State * state); -void ARMul_ReportEnergy (ARMul_State * state, FILE * pf); -void ARMul_Consolidate (ARMul_State * state); +SYM_FUNC *ARMul_GetSym(ARMword address); +void ARMul_ProfInit(ARMul_State *state); +FUNC_NODE *ARMul_CreateChild(ARMul_State *state); +void ARMul_DestroyChild(ARMul_State *state); +void ARMul_CallCheck(ARMul_State *state, ARMword cur_pc, ARMword to_pc, ARMword instr); +void ARMul_TaskSwitch(ARMul_State *state); +ARMword ARMul_TaskCreate(ARMul_State *state); +void ARMul_ReportEnergy(ARMul_State *state, FILE* pf); +void ARMul_Consolidate(ARMul_State *state); #endif + Index: arch/arm/common/armmem.c =================================================================== --- arch/arm/common/armmem.c (revision 301) +++ arch/arm/common/armmem.c (working copy) @@ -284,7 +284,7 @@ fprintf(stderr, "SKYEYE:NumInstrs %llu, mem_write_byte addr = %x no bank\n",state->NumInstrs, addr); //chy 2003-09-03 //SKYEYE_OUTREGS(stderr); - skyeye_exit(-1); + //skyeye_exit(-1); } } void Index: arch/arm/common/armemu.c =================================================================== --- arch/arm/common/armemu.c (revision 301) +++ arch/arm/common/armemu.c (working copy) @@ -598,23 +598,25 @@ if (state->NresetSig == LOW) { ARMul_Abort (state, ARMul_ResetV); - /*added energy_prof statement by ksh in 2004-11-26 */ - //chy 2005-07-28 for standalone - //ARMul_do_energy(state,instr,pc); + /* Energy profiling */ + if (skyeye_config.energy.energy_prof) + ARMul_do_energy(state,instr,pc); break; } else if (!state->NfiqSig && !FFLAG) { ARMul_Abort (state, ARMul_FIQV); - /*added energy_prof statement by ksh in 2004-11-26 */ - //chy 2005-07-28 for standalone - //ARMul_do_energy(state,instr,pc); + + /* Add energy profiling */ + if(skyeye_config.energy.energy_prof) + ARMul_do_energy(state,instr,pc); break; } else if (!state->NirqSig && !IFLAG) { ARMul_Abort (state, ARMul_IRQV); - /*added energy_prof statement by ksh in 2004-11-26 */ - //chy 2005-07-28 for standalone - //ARMul_do_energy(state,instr,pc); + + /* Add energy profiling */ + if(skyeye_config.energy.energy_prof) + ARMul_do_energy(state,instr,pc); break; } @@ -4080,9 +4082,9 @@ } #endif /* NEED_UI_LOOP_HOOK */ - /*added energy_prof statement by ksh in 2004-11-26 */ - //chy 2005-07-28 for standalone - //ARMul_do_energy(state,instr,pc); + /* Energy profiling */ + if(skyeye_config.energy.energy_prof) + ARMul_do_energy(state,instr,pc); //teawater add for record reg value to ./reg.txt 2005.07.10--------------------- if (state->tea_break_ok && pc == state->tea_break_addr) { ARMul_Debug (state, 0, 0); Index: arch/arm/common/armengr.c =================================================================== --- arch/arm/common/armengr.c (revision 301) +++ arch/arm/common/armengr.c (working copy) @@ -107,7 +107,6 @@ float Core_freq; float Vdd; unsigned int cccr = state->energy.cccr; -// printf("before calculate:cccr=0x%x,cccr&0x0=0x%x \n",cccr,cccr&0x0); switch ((cccr >> 7) & 0x7) { case 2: N = 1; @@ -126,7 +125,6 @@ N = 1; break; } -//printf("before calculate:cccr=0x%x,cccr&0x0=0x%x \n",cccr,cccr&0x0); switch ((cccr >> 5) & 0x3) { case 1: M = 1; Index: arch/arm/common/arm_arch_interface.c =================================================================== --- arch/arm/common/arm_arch_interface.c (revision 301) +++ arch/arm/common/arm_arch_interface.c (working copy) @@ -18,11 +18,6 @@ ARMul_ConsolePrint (ARMul_State * state, const char *format, ...) { } -void -ARMul_CallCheck (ARMul_State * state, ARMword cur_pc, ARMword to_pc, - ARMword instr) -{ -} static void base_termios_exit (void) @@ -78,6 +73,15 @@ //chy 2005-08-01 commit and disable ksh's energy estimantion, will be recover in the future /*added by ksh for energy estimation,in 2004-11-26 */ state->energy.energy_prof = skyeye_config.energy.energy_prof; + ARMul_EnergyInit(state); + ARMul_ProfInit(state); + if(!state->energy.outfile) + if(!(state->energy.outfile = fopen(skyeye_config.energy.logfile, "w"))){ + fprintf(stderr, "Error when open energy log file %s\n", skyeye_config.energy.logfile); + skyeye_exit(-1); + } + else + printf("Open energy log file %s for profiling.\n", skyeye_config.energy.logfile); /*mach init */ skyeye_config.mach->mach_init (state, skyeye_config.mach); } Index: Makefile =================================================================== --- Makefile (revision 301) +++ Makefile (working copy) @@ -191,7 +191,7 @@ $(DEVICE_CFLAGS) $(UTILS_CFLAGS) -g -O endif -SIM_ARM_OBJS = binary/armcopro.o binary/armemu26.o binary/armemu32.o binary/arminit.o binary/armsupp.o binary/armos.o binary/thumbemu.o binary/armvirt.o binary/armmmu.o binary/armmem.o binary/armio.o binary/arm_arch_interface.o +SIM_ARM_OBJS = binary/armcopro.o binary/armemu26.o binary/armemu32.o binary/arminit.o binary/armsupp.o binary/armos.o binary/thumbemu.o binary/armvirt.o binary/armmmu.o binary/armmem.o binary/armio.o binary/arm_arch_interface.o binary/armengr.o binary/armsym.o BFIN_DBCT_OBJS = binary/bfin_tb.o binary/dbct_step.o binary/bfin2x86_load_store.o binary/bfin2x86_move.o binary/bfin2x86_arith.o BFIN_COMMON_OBJS = binary/bfin_arch_interface.o binary/iomem.o binary/bfin-dis.o BFIN_MACH_OBJS = binary/bf533_io.o binary/bf537_io.o @@ -554,6 +554,10 @@ $(CC) -c $< -o $@ $(ALL_CFLAGS) binary/arm_arch_interface.o: $(ARM_COMMON_PATH)/arm_arch_interface.c $(CC) -c $< -o $@ $(ALL_CFLAGS) +binary/armengr.o: $(ARM_COMMON_PATH)/armengr.c + $(CC) -c $< -o $@ $(ALL_CFLAGS) +binary/armsym.o: $(ARM_COMMON_PATH)/armsym.c $(ARM_COMMON_PATH)/armsym.h + $(CC) -c $< -o $@ $(ALL_CFLAGS) #SIM_MMU_OBJS binary/arm7100_mmu.o: $(ARM_COMMON_PATH)/mmu/arm7100_mmu.c $(ARM_COMMON_PATH)/mmu/arm7100_mmu.h $(CC) $(ALL_CFLAGS) -c $< -o $@ �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/������������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�013142� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/oplet/������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014265� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/oplet/reg_gen.c���������������������������������������������������������������0000644�0001750�0000144�00000000534�10541455476�016064� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <fcntl.h> #include <stdio.h> #include <reg_map.h> #include <host_reg.h> int main(){ char * filename = "reg_defs.h"; FILE * fd = fopen(filename, "w+"); int i = 0; for(; i < sizeof(host_regs)/sizeof(reg_t) ;i++){ fprintf(fd, "register uint32_t %s asm (\"%s\")\n", host_regs[i].ir_regname, host_regs[i].host_regname); } close(fd); } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/oplet/Makefile����������������������������������������������������������������0000644�0001750�0000144�00000000422�10571723704�015741� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������CFLAGS=-I$(PWD)/../include all: reg_gen movl_gen shift_gen reg_gen:reg_gen.c gcc $(CFLAGS) -o reg_gen reg_gen.c movl_gen:movl_gen.c gcc $(CFLAGS) -o movl_gen movl_gen.c shift_gen:shift_gen.c gcc $(CFLAGS) -o shift_gen shift_gen.c clean: rm -f reg_gen movl_gen shift_gen ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/oplet/movl_gen.c��������������������������������������������������������������0000644�0001750�0000144�00000001621�10571723704�016255� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <stdio.h> #include "target_reg.h" #include "host_reg.h" int main(){ char * filename = "movl_oplet.c"; FILE * fd = fopen(filename, "w+"); int i = 0, j = 0; for(; i < sizeof(host_regs)/sizeof(reg_t);i++){ j = 0; for(; j < sizeof(host_regs)/sizeof(reg_t);j++){ fprintf(fd, "uint8_t * get_op_movl_%s_%s (int * len)\n", host_regs[i].ir_regname, host_regs[j].ir_regname); fprintf(fd, "{\n"); fprintf(fd, "\tuint8_t * ret;\n"); fprintf(fd, "\tOP_BEGIN (\"get_op_movl_%s_%s\");\n", host_regs[i].ir_regname, host_regs[j].ir_regname); fprintf(fd, "\t%s = %s;\n", host_regs[j].ir_regname, target_regs[i].regvalue); fprintf(fd, "\tOP_END (\"get_op_movl_%s_%s\");\n", target_regs[i].regname, host_regs[j].ir_regname); fprintf(fd, "\t*len = end - begin;\n"); fprintf(fd, "\tret = (uint8_t *)begin;\n"); fprintf(fd, "\treturn (ret);\n"); fprintf(fd, "}\n"); } } fclose(fd); } ���������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/include/����������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014565� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/include/host_reg.h������������������������������������������������������������0000644�0001750�0000144�00000000135�10541455476�016572� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <reg_map.h> reg_t host_regs[] = { {"T0", "ebx"}, {"T1", "esi"}, {"T2", "edi"} }; �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/include/reg_map.h�������������������������������������������������������������0000644�0001750�0000144�00000000371�10541455476�016374� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef __REG_MAP_H__ #define __REG_MAP_H__ struct _reg_s { char * ir_regname; char * host_regname; }; typedef struct _reg_s reg_t; struct _target_reg_s { char * regname; char * regvalue; }; typedef struct _target_reg_s target_reg_t; #endif �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/include/i386_reg.h������������������������������������������������������������0000644�0001750�0000144�00000000120�10541455476�016300� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������struct _reg_s i386_regs[] = { {"T0", "ebx"}, {"T1", "esi"}, {"T2", "edi"} }; ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/include/target_reg.h����������������������������������������������������������0000644�0001750�0000144�00000000664�10541455476�017112� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "reg_map.h" target_reg_t target_regs[] = { {"r0", "st->Reg[0]"}, {"r1", "st->Reg[1]"}, {"r2", "st->Reg[2]"}, {"r3", "st->Reg[3]"}, {"r4", "st->Reg[4]"}, {"r5", "st->Reg[5]"}, {"r6", "st->Reg[6]"}, {"r7", "st->Reg[7]"}, {"r8", "st->Reg[8]"}, {"r9", "st->Reg[9]"}, {"r10", "st->Reg[10]"}, {"r11", "st->Reg[11]"}, {"r12", "st->Reg[12]"}, {"r13", "st->Reg[13]"}, {"r14", "st->Reg[14]"}, {"r15", "st->Reg[15]"}, }; ����������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/host/�������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014117� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/dbct/host/i386_reg.h���������������������������������������������������������������0000644�0001750�0000144�00000000173�10541455476�015642� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������struct _reg_s{ char * ir_regname char * regname; } struct i386_reg = { {"T0", "ebx"}, {"T1", "esi"}, {"T2", "edi"} }; �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/AUTHORS����������������������������������������������������������������������������0000644�0001750�0000144�00000000000�11006126165�013272� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/missing����������������������������������������������������������������������������0000644�0001750�0000144�00000025577�11006120657�013650� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#! /bin/sh # Common stub for a few missing GNU programs while installing. scriptversion=2006-05-10.23 # Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004, 2005, 2006 # Free Software Foundation, Inc. # Originally by Fran,cois Pinard <pinard@iro.umontreal.ca>, 1996. # This program is free software; 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If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. 9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. 10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. <one line to give the program's name and a brief idea of what it does.> Copyright (C) 19yy <name of author> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: Gnomovision version 69, Copyright (C) 19yy name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. <signature of Ty Coon>, 1 April 1989 Ty Coon, President of Vice This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Library General Public License instead of this License. �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/configure��������������������������������������������������������������������������0000755�0001750�0000144�00001137571�11023514465�014165� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#! /bin/sh # Guess values for system-dependent variables and create Makefiles. # Generated by GNU Autoconf 2.61 for SkyEye 1.2.5. # # Report bugs to <skyeye-developer@lists.gro.clinux.org>. # # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, # 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. ## --------------------- ## ## M4sh Initialization. ## ## --------------------- ## # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then emulate sh NULLCMD=: # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which # is contrary to our usage. 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echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } { (ac_try="$ac_compiler -V >&5" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compiler -V >&5") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } { echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5 echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6; } if test "${ac_cv_c_compiler_gnu+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { #ifndef __GNUC__ choke me #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_compiler_gnu=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_compiler_gnu=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ac_cv_c_compiler_gnu=$ac_compiler_gnu fi { echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5 echo "${ECHO_T}$ac_cv_c_compiler_gnu" >&6; } GCC=`test $ac_compiler_gnu = yes && echo yes` ac_test_CFLAGS=${CFLAGS+set} ac_save_CFLAGS=$CFLAGS { echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5 echo $ECHO_N "checking whether $CC accepts -g... $ECHO_C" >&6; } if test "${ac_cv_prog_cc_g+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_save_c_werror_flag=$ac_c_werror_flag ac_c_werror_flag=yes ac_cv_prog_cc_g=no CFLAGS="-g" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_prog_cc_g=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 CFLAGS="" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_c_werror_flag=$ac_save_c_werror_flag CFLAGS="-g" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_prog_cc_g=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ac_c_werror_flag=$ac_save_c_werror_flag fi { echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 echo "${ECHO_T}$ac_cv_prog_cc_g" >&6; } if test "$ac_test_CFLAGS" = set; then CFLAGS=$ac_save_CFLAGS elif test $ac_cv_prog_cc_g = yes; then if test "$GCC" = yes; then CFLAGS="-g -O2" else CFLAGS="-g" fi else if test "$GCC" = yes; then CFLAGS="-O2" else CFLAGS= fi fi { echo "$as_me:$LINENO: checking for $CC option to accept ISO C89" >&5 echo $ECHO_N "checking for $CC option to accept ISO C89... $ECHO_C" >&6; } if test "${ac_cv_prog_cc_c89+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_prog_cc_c89=no ac_save_CC=$CC cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <stdarg.h> #include <stdio.h> #include <sys/types.h> #include <sys/stat.h> /* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ struct buf { int x; }; FILE * (*rcsopen) (struct buf *, struct stat *, int); static char *e (p, i) char **p; int i; { return p[i]; } static char *f (char * (*g) (char **, int), char **p, ...) { char *s; va_list v; va_start (v,p); s = g (p, va_arg (v,int)); va_end (v); return s; } /* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. 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grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_c_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_c_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_c_main" >&5 echo "${ECHO_T}$ac_cv_lib_c_main" >&6; } if test $ac_cv_lib_c_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBC 1 _ACEOF LIBS="-lc $LIBS" fi # FIXME: Replace `main' with a function in `-lgdi32': { echo "$as_me:$LINENO: checking for main in -lgdi32" >&5 echo $ECHO_N "checking for main in -lgdi32... $ECHO_C" >&6; } if test "${ac_cv_lib_gdi32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lgdi32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_gdi32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_gdi32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_gdi32_main" >&5 echo "${ECHO_T}$ac_cv_lib_gdi32_main" >&6; } if test $ac_cv_lib_gdi32_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBGDI32 1 _ACEOF LIBS="-lgdi32 $LIBS" fi # FIXME: Replace `main' with a function in `-liberty': { echo "$as_me:$LINENO: checking for main in -liberty" >&5 echo $ECHO_N "checking for main in -liberty... $ECHO_C" >&6; } if test "${ac_cv_lib_iberty_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-liberty $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_iberty_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_iberty_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_iberty_main" >&5 echo "${ECHO_T}$ac_cv_lib_iberty_main" >&6; } if test $ac_cv_lib_iberty_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBIBERTY 1 _ACEOF LIBS="-liberty $LIBS" fi # FIXME: Replace `main' with a function in `-lintl': { echo "$as_me:$LINENO: checking for main in -lintl" >&5 echo $ECHO_N "checking for main in -lintl... $ECHO_C" >&6; } if test "${ac_cv_lib_intl_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lintl $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_intl_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_intl_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_intl_main" >&5 echo "${ECHO_T}$ac_cv_lib_intl_main" >&6; } if test $ac_cv_lib_intl_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBINTL 1 _ACEOF LIBS="-lintl $LIBS" fi # FIXME: Replace `main' with a function in `-lkernel32': { echo "$as_me:$LINENO: checking for main in -lkernel32" >&5 echo $ECHO_N "checking for main in -lkernel32... $ECHO_C" >&6; } if test "${ac_cv_lib_kernel32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lkernel32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_kernel32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_kernel32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_kernel32_main" >&5 echo "${ECHO_T}$ac_cv_lib_kernel32_main" >&6; } if test $ac_cv_lib_kernel32_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBKERNEL32 1 _ACEOF LIBS="-lkernel32 $LIBS" fi # FIXME: Replace `main' with a function in `-lm': { echo "$as_me:$LINENO: checking for main in -lm" >&5 echo $ECHO_N "checking for main in -lm... $ECHO_C" >&6; } if test "${ac_cv_lib_m_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lm $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_m_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_m_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_m_main" >&5 echo "${ECHO_T}$ac_cv_lib_m_main" >&6; } if test $ac_cv_lib_m_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBM 1 _ACEOF LIBS="-lm $LIBS" fi # FIXME: Replace `main' with a function in `-lmsvcrt': { echo "$as_me:$LINENO: checking for main in -lmsvcrt" >&5 echo $ECHO_N "checking for main in -lmsvcrt... $ECHO_C" >&6; } if test "${ac_cv_lib_msvcrt_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lmsvcrt $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_msvcrt_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_msvcrt_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_msvcrt_main" >&5 echo "${ECHO_T}$ac_cv_lib_msvcrt_main" >&6; } if test $ac_cv_lib_msvcrt_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBMSVCRT 1 _ACEOF LIBS="-lmsvcrt $LIBS" fi # FIXME: Replace `main' with a function in `-ln': { echo "$as_me:$LINENO: checking for main in -ln" >&5 echo $ECHO_N "checking for main in -ln... $ECHO_C" >&6; } if test "${ac_cv_lib_n_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ln $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_n_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_n_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_n_main" >&5 echo "${ECHO_T}$ac_cv_lib_n_main" >&6; } if test $ac_cv_lib_n_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBN 1 _ACEOF LIBS="-ln $LIBS" fi # FIXME: Replace `main' with a function in `-lnet': { echo "$as_me:$LINENO: checking for main in -lnet" >&5 echo $ECHO_N "checking for main in -lnet... $ECHO_C" >&6; } if test "${ac_cv_lib_net_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lnet $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_net_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_net_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_net_main" >&5 echo "${ECHO_T}$ac_cv_lib_net_main" >&6; } if test $ac_cv_lib_net_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBNET 1 _ACEOF LIBS="-lnet $LIBS" fi # FIXME: Replace `main' with a function in `-lroot': { echo "$as_me:$LINENO: checking for main in -lroot" >&5 echo $ECHO_N "checking for main in -lroot... $ECHO_C" >&6; } if test "${ac_cv_lib_root_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lroot $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_root_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_root_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_root_main" >&5 echo "${ECHO_T}$ac_cv_lib_root_main" >&6; } if test $ac_cv_lib_root_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBROOT 1 _ACEOF LIBS="-lroot $LIBS" fi # FIXME: Replace `main' with a function in `-lsocket': { echo "$as_me:$LINENO: checking for main in -lsocket" >&5 echo $ECHO_N "checking for main in -lsocket... $ECHO_C" >&6; } if test "${ac_cv_lib_socket_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_socket_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_socket_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_socket_main" >&5 echo "${ECHO_T}$ac_cv_lib_socket_main" >&6; } if test $ac_cv_lib_socket_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBSOCKET 1 _ACEOF LIBS="-lsocket $LIBS" fi # FIXME: Replace `main' with a function in `-luser32': { echo "$as_me:$LINENO: checking for main in -luser32" >&5 echo $ECHO_N "checking for main in -luser32... $ECHO_C" >&6; } if test "${ac_cv_lib_user32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-luser32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_user32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_user32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_user32_main" >&5 echo "${ECHO_T}$ac_cv_lib_user32_main" >&6; } if test $ac_cv_lib_user32_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBUSER32 1 _ACEOF LIBS="-luser32 $LIBS" fi # FIXME: Replace `main' with a function in `-lwinmm': { echo "$as_me:$LINENO: checking for main in -lwinmm" >&5 echo $ECHO_N "checking for main in -lwinmm... $ECHO_C" >&6; } if test "${ac_cv_lib_winmm_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lwinmm $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_winmm_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_winmm_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_winmm_main" >&5 echo "${ECHO_T}$ac_cv_lib_winmm_main" >&6; } if test $ac_cv_lib_winmm_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBWINMM 1 _ACEOF LIBS="-lwinmm $LIBS" fi # FIXME: Replace `main' with a function in `-lws2_32': { echo "$as_me:$LINENO: checking for main in -lws2_32" >&5 echo $ECHO_N "checking for main in -lws2_32... $ECHO_C" >&6; } if test "${ac_cv_lib_ws2_32_main+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lws2_32 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { return main (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_ws2_32_main=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_ws2_32_main=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_ws2_32_main" >&5 echo "${ECHO_T}$ac_cv_lib_ws2_32_main" >&6; } if test $ac_cv_lib_ws2_32_main = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBWS2_32 1 _ACEOF LIBS="-lws2_32 $LIBS" fi { echo "$as_me:$LINENO: checking for bfd_openr in -lbfd" >&5 echo $ECHO_N "checking for bfd_openr in -lbfd... $ECHO_C" >&6; } if test "${ac_cv_lib_bfd_bfd_openr+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lbfd $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char bfd_openr (); int main () { return bfd_openr (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_bfd_bfd_openr=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_bfd_bfd_openr=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_bfd_bfd_openr" >&5 echo "${ECHO_T}$ac_cv_lib_bfd_bfd_openr" >&6; } if test $ac_cv_lib_bfd_bfd_openr = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_LIBBFD 1 _ACEOF LIBS="-lbfd $LIBS" fi # Checks for header files. { echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5 echo $ECHO_N "checking for grep that handles long lines and -e... $ECHO_C" >&6; } if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # Extract the first word of "grep ggrep" to use in msg output if test -z "$GREP"; then set dummy grep ggrep; ac_prog_name=$2 if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_GREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in grep ggrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue # Check for GNU ac_path_GREP and select it if it is found. # Check for GNU $ac_path_GREP case `"$ac_path_GREP" --version 2>&1` in *GNU*) ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'GREP' >> "conftest.nl" "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_GREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_GREP_found && break 3 done done done IFS=$as_save_IFS fi GREP="$ac_cv_path_GREP" if test -z "$GREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_GREP=$GREP fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5 echo "${ECHO_T}$ac_cv_path_GREP" >&6; } GREP="$ac_cv_path_GREP" { echo "$as_me:$LINENO: checking for egrep" >&5 echo $ECHO_N "checking for egrep... $ECHO_C" >&6; } if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 then ac_cv_path_EGREP="$GREP -E" else # Extract the first word of "egrep" to use in msg output if test -z "$EGREP"; then set dummy egrep; ac_prog_name=$2 if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_EGREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in egrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue # Check for GNU ac_path_EGREP and select it if it is found. # Check for GNU $ac_path_EGREP case `"$ac_path_EGREP" --version 2>&1` in *GNU*) ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'EGREP' >> "conftest.nl" "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_EGREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_EGREP_found && break 3 done done done IFS=$as_save_IFS fi EGREP="$ac_cv_path_EGREP" if test -z "$EGREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_EGREP=$EGREP fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5 echo "${ECHO_T}$ac_cv_path_EGREP" >&6; } EGREP="$ac_cv_path_EGREP" { echo "$as_me:$LINENO: checking for ANSI C header files" >&5 echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6; } if test "${ac_cv_header_stdc+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <stdlib.h> #include <stdarg.h> #include <string.h> #include <float.h> int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdc=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <string.h> _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "memchr" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <stdlib.h> _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "free" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. if test "$cross_compiling" = yes; then : else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <ctype.h> #include <stdlib.h> #if ((' ' & 0x0FF) == 0x020) # define ISLOWER(c) ('a' <= (c) && (c) <= 'z') # define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) #else # define ISLOWER(c) \ (('a' <= (c) && (c) <= 'i') \ || ('j' <= (c) && (c) <= 'r') \ || ('s' <= (c) && (c) <= 'z')) # define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) #endif #define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) int main () { int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) return 2; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then : else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_header_stdc=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 echo "${ECHO_T}$ac_cv_header_stdc" >&6; } if test $ac_cv_header_stdc = yes; then cat >>confdefs.h <<\_ACEOF #define STDC_HEADERS 1 _ACEOF fi # On IRIX 5.3, sys/types and inttypes.h are conflicting. for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ inttypes.h stdint.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then eval "$as_ac_Header=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_Header=no" fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_header in fcntl.h inttypes.h limits.h locale.h netdb.h netinet/in.h stddef.h stdint.h stdlib.h string.h sys/file.h sys/ioctl.h sys/socket.h sys/time.h termios.h unistd.h gtk/gtk.h bfd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX ## ---------------------------------------------------- ## ## Report this to skyeye-developer@lists.gro.clinux.org ## ## ---------------------------------------------------- ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done # Checks for typedefs, structures, and compiler characteristics. { echo "$as_me:$LINENO: checking for stdbool.h that conforms to C99" >&5 echo $ECHO_N "checking for stdbool.h that conforms to C99... $ECHO_C" >&6; } if test "${ac_cv_header_stdbool_h+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <stdbool.h> #ifndef bool "error: bool is not defined" #endif #ifndef false "error: false is not defined" #endif #if false "error: false is not 0" #endif #ifndef true "error: true is not defined" #endif #if true != 1 "error: true is not 1" #endif #ifndef __bool_true_false_are_defined "error: __bool_true_false_are_defined is not defined" #endif struct s { _Bool s: 1; _Bool t; } s; char a[true == 1 ? 1 : -1]; char b[false == 0 ? 1 : -1]; char c[__bool_true_false_are_defined == 1 ? 1 : -1]; char d[(bool) 0.5 == true ? 1 : -1]; bool e = &s; char f[(_Bool) 0.0 == false ? 1 : -1]; char g[true]; char h[sizeof (_Bool)]; char i[sizeof s.t]; enum { j = false, k = true, l = false * true, m = true * 256 }; _Bool n[m]; char o[sizeof n == m * sizeof n[0] ? 1 : -1]; char p[-1 - (_Bool) 0 < 0 && -1 - (bool) 0 < 0 ? 1 : -1]; # if defined __xlc__ || defined __GNUC__ /* Catch a bug in IBM AIX xlc compiler version 6.0.0.0 reported by James Lemley on 2005-10-05; see http://lists.gnu.org/archive/html/bug-coreutils/2005-10/msg00086.html This test is not quite right, since xlc is allowed to reject this program, as the initializer for xlcbug is not one of the forms that C requires support for. However, doing the test right would require a runtime test, and that would make cross-compilation harder. Let us hope that IBM fixes the xlc bug, and also adds support for this kind of constant expression. In the meantime, this test will reject xlc, which is OK, since our stdbool.h substitute should suffice. We also test this with GCC, where it should work, to detect more quickly whether someone messes up the test in the future. */ char digs[] = "0123456789"; int xlcbug = 1 / (&(digs + 5)[-2 + (bool) 1] == &digs[4] ? 1 : -1); # endif /* Catch a bug in an HP-UX C compiler. See http://gcc.gnu.org/ml/gcc-patches/2003-12/msg02303.html http://lists.gnu.org/archive/html/bug-coreutils/2005-11/msg00161.html */ _Bool q = true; _Bool *pq = &q; int main () { *pq |= q; *pq |= ! q; /* Refer to every declared value, to avoid compiler optimizations. */ return (!a + !b + !c + !d + !e + !f + !g + !h + !i + !!j + !k + !!l + !m + !n + !o + !p + !q + !pq); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdbool_h=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdbool_h=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdbool_h" >&5 echo "${ECHO_T}$ac_cv_header_stdbool_h" >&6; } { echo "$as_me:$LINENO: checking for _Bool" >&5 echo $ECHO_N "checking for _Bool... $ECHO_C" >&6; } if test "${ac_cv_type__Bool+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef _Bool ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type__Bool=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type__Bool=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type__Bool" >&5 echo "${ECHO_T}$ac_cv_type__Bool" >&6; } if test $ac_cv_type__Bool = yes; then cat >>confdefs.h <<_ACEOF #define HAVE__BOOL 1 _ACEOF fi if test $ac_cv_header_stdbool_h = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_STDBOOL_H 1 _ACEOF fi { echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6; } if test "${ac_cv_c_const+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { /* FIXME: Include the comments suggested by Paul. */ #ifndef __cplusplus /* Ultrix mips cc rejects this. */ typedef int charset[2]; const charset cs; /* SunOS 4.1.1 cc rejects this. */ char const *const *pcpcc; char **ppc; /* NEC SVR4.0.2 mips cc rejects this. */ struct point {int x, y;}; static struct point const zero = {0,0}; /* AIX XL C 1.02.0.0 rejects this. It does not let you subtract one const X* pointer from another in an arm of an if-expression whose if-part is not a constant expression */ const char *g = "string"; pcpcc = &g + (g ? g-g : 0); /* HPUX 7.0 cc rejects these. */ ++pcpcc; ppc = (char**) pcpcc; pcpcc = (char const *const *) ppc; { /* SCO 3.2v4 cc rejects this. */ char *t; char const *s = 0 ? (char *) 0 : (char const *) 0; *t++ = 0; if (s) return 0; } { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ int x[] = {25, 17}; const int *foo = &x[0]; ++foo; } { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ typedef const int *iptr; iptr p = 0; ++p; } { /* AIX XL C 1.02.0.0 rejects this saying "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ struct s { int j; const int *ap[3]; }; struct s *b; b->j = 5; } { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ const int foo = 10; if (!foo) return 0; } return !cs[0] && !zero.x; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_const=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_const=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 echo "${ECHO_T}$ac_cv_c_const" >&6; } if test $ac_cv_c_const = no; then cat >>confdefs.h <<\_ACEOF #define const _ACEOF fi { echo "$as_me:$LINENO: checking for inline" >&5 echo $ECHO_N "checking for inline... $ECHO_C" >&6; } if test "${ac_cv_c_inline+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #ifndef __cplusplus typedef int foo_t; static $ac_kw foo_t static_foo () {return 0; } $ac_kw foo_t foo () {return 0; } #endif _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_inline=$ac_kw else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_inline" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5 echo "${ECHO_T}$ac_cv_c_inline" >&6; } case $ac_cv_c_inline in inline | yes) ;; *) case $ac_cv_c_inline in no) ac_val=;; *) ac_val=$ac_cv_c_inline;; esac cat >>confdefs.h <<_ACEOF #ifndef __cplusplus #define inline $ac_val #endif _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int16_t" >&5 echo $ECHO_N "checking for int16_t... $ECHO_C" >&6; } if test "${ac_cv_c_int16_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int16_t=no for ac_type in 'int16_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 1))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (16 - 2)) - 1) * 2 + 2))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int16_t) ac_cv_c_int16_t=yes ;; *) ac_cv_c_int16_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int16_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int16_t" >&5 echo "${ECHO_T}$ac_cv_c_int16_t" >&6; } case $ac_cv_c_int16_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF #define int16_t $ac_cv_c_int16_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int32_t" >&5 echo $ECHO_N "checking for int32_t... $ECHO_C" >&6; } if test "${ac_cv_c_int32_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int32_t=no for ac_type in 'int32_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 1))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (32 - 2)) - 1) * 2 + 2))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int32_t) ac_cv_c_int32_t=yes ;; *) ac_cv_c_int32_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int32_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int32_t" >&5 echo "${ECHO_T}$ac_cv_c_int32_t" >&6; } case $ac_cv_c_int32_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF #define int32_t $ac_cv_c_int32_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int64_t" >&5 echo $ECHO_N "checking for int64_t... $ECHO_C" >&6; } if test "${ac_cv_c_int64_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int64_t=no for ac_type in 'int64_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 1))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (64 - 2)) - 1) * 2 + 2))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int64_t) ac_cv_c_int64_t=yes ;; *) ac_cv_c_int64_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int64_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int64_t" >&5 echo "${ECHO_T}$ac_cv_c_int64_t" >&6; } case $ac_cv_c_int64_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF #define int64_t $ac_cv_c_int64_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for int8_t" >&5 echo $ECHO_N "checking for int8_t... $ECHO_C" >&6; } if test "${ac_cv_c_int8_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_int8_t=no for ac_type in 'int8_t' 'int' 'long int' \ 'long long int' 'short int' 'signed char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(0 < ($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 1))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 1) < ($ac_type) (((($ac_type) 1 << (8 - 2)) - 1) * 2 + 2))]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 case $ac_type in int8_t) ac_cv_c_int8_t=yes ;; *) ac_cv_c_int8_t=$ac_type ;; esac fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_int8_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_int8_t" >&5 echo "${ECHO_T}$ac_cv_c_int8_t" >&6; } case $ac_cv_c_int8_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF #define int8_t $ac_cv_c_int8_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for off_t" >&5 echo $ECHO_N "checking for off_t... $ECHO_C" >&6; } if test "${ac_cv_type_off_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef off_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_off_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_off_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5 echo "${ECHO_T}$ac_cv_type_off_t" >&6; } if test $ac_cv_type_off_t = yes; then : else cat >>confdefs.h <<_ACEOF #define off_t long int _ACEOF fi { echo "$as_me:$LINENO: checking for size_t" >&5 echo $ECHO_N "checking for size_t... $ECHO_C" >&6; } if test "${ac_cv_type_size_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef size_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_size_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_size_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5 echo "${ECHO_T}$ac_cv_type_size_t" >&6; } if test $ac_cv_type_size_t = yes; then : else cat >>confdefs.h <<_ACEOF #define size_t unsigned int _ACEOF fi { echo "$as_me:$LINENO: checking for ssize_t" >&5 echo $ECHO_N "checking for ssize_t... $ECHO_C" >&6; } if test "${ac_cv_type_ssize_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef ssize_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_ssize_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_ssize_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_ssize_t" >&5 echo "${ECHO_T}$ac_cv_type_ssize_t" >&6; } if test $ac_cv_type_ssize_t = yes; then : else cat >>confdefs.h <<_ACEOF #define ssize_t int _ACEOF fi { echo "$as_me:$LINENO: checking whether time.h and sys/time.h may both be included" >&5 echo $ECHO_N "checking whether time.h and sys/time.h may both be included... $ECHO_C" >&6; } if test "${ac_cv_header_time+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <sys/types.h> #include <sys/time.h> #include <time.h> int main () { if ((struct tm *) 0) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_time=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_time=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_time" >&5 echo "${ECHO_T}$ac_cv_header_time" >&6; } if test $ac_cv_header_time = yes; then cat >>confdefs.h <<\_ACEOF #define TIME_WITH_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking whether struct tm is in sys/time.h or time.h" >&5 echo $ECHO_N "checking whether struct tm is in sys/time.h or time.h... $ECHO_C" >&6; } if test "${ac_cv_struct_tm+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <sys/types.h> #include <time.h> int main () { struct tm tm; int *p = &tm.tm_sec; return !p; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_struct_tm=time.h else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_struct_tm=sys/time.h fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_struct_tm" >&5 echo "${ECHO_T}$ac_cv_struct_tm" >&6; } if test $ac_cv_struct_tm = sys/time.h; then cat >>confdefs.h <<\_ACEOF #define TM_IN_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking for uid_t in sys/types.h" >&5 echo $ECHO_N "checking for uid_t in sys/types.h... $ECHO_C" >&6; } if test "${ac_cv_type_uid_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <sys/types.h> _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "uid_t" >/dev/null 2>&1; then ac_cv_type_uid_t=yes else ac_cv_type_uid_t=no fi rm -f conftest* fi { echo "$as_me:$LINENO: result: $ac_cv_type_uid_t" >&5 echo "${ECHO_T}$ac_cv_type_uid_t" >&6; } if test $ac_cv_type_uid_t = no; then cat >>confdefs.h <<\_ACEOF #define uid_t int _ACEOF cat >>confdefs.h <<\_ACEOF #define gid_t int _ACEOF fi { echo "$as_me:$LINENO: checking for uint16_t" >&5 echo $ECHO_N "checking for uint16_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint16_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint16_t=no for ac_type in 'uint16_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) -1 >> (16 - 1) == 1)]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint16_t) ac_cv_c_uint16_t=yes ;; *) ac_cv_c_uint16_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint16_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint16_t" >&5 echo "${ECHO_T}$ac_cv_c_uint16_t" >&6; } case $ac_cv_c_uint16_t in #( no|yes) ;; #( *) cat >>confdefs.h <<_ACEOF #define uint16_t $ac_cv_c_uint16_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for uint32_t" >&5 echo $ECHO_N "checking for uint32_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint32_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint32_t=no for ac_type in 'uint32_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) -1 >> (32 - 1) == 1)]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint32_t) ac_cv_c_uint32_t=yes ;; *) ac_cv_c_uint32_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint32_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint32_t" >&5 echo "${ECHO_T}$ac_cv_c_uint32_t" >&6; } case $ac_cv_c_uint32_t in #( no|yes) ;; #( *) cat >>confdefs.h <<\_ACEOF #define _UINT32_T 1 _ACEOF cat >>confdefs.h <<_ACEOF #define uint32_t $ac_cv_c_uint32_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for uint64_t" >&5 echo $ECHO_N "checking for uint64_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint64_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint64_t=no for ac_type in 'uint64_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) -1 >> (64 - 1) == 1)]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint64_t) ac_cv_c_uint64_t=yes ;; *) ac_cv_c_uint64_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint64_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint64_t" >&5 echo "${ECHO_T}$ac_cv_c_uint64_t" >&6; } case $ac_cv_c_uint64_t in #( no|yes) ;; #( *) cat >>confdefs.h <<\_ACEOF #define _UINT64_T 1 _ACEOF cat >>confdefs.h <<_ACEOF #define uint64_t $ac_cv_c_uint64_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for uint8_t" >&5 echo $ECHO_N "checking for uint8_t... $ECHO_C" >&6; } if test "${ac_cv_c_uint8_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_c_uint8_t=no for ac_type in 'uint8_t' 'unsigned int' 'unsigned long int' \ 'unsigned long long int' 'unsigned short int' 'unsigned char'; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { static int test_array [1 - 2 * !(($ac_type) -1 >> (8 - 1) == 1)]; test_array [0] = 0 ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then case $ac_type in uint8_t) ac_cv_c_uint8_t=yes ;; *) ac_cv_c_uint8_t=$ac_type ;; esac else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext test "$ac_cv_c_uint8_t" != no && break done fi { echo "$as_me:$LINENO: result: $ac_cv_c_uint8_t" >&5 echo "${ECHO_T}$ac_cv_c_uint8_t" >&6; } case $ac_cv_c_uint8_t in #( no|yes) ;; #( *) cat >>confdefs.h <<\_ACEOF #define _UINT8_T 1 _ACEOF cat >>confdefs.h <<_ACEOF #define uint8_t $ac_cv_c_uint8_t _ACEOF ;; esac { echo "$as_me:$LINENO: checking for working volatile" >&5 echo $ECHO_N "checking for working volatile... $ECHO_C" >&6; } if test "${ac_cv_c_volatile+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { volatile int x; int * volatile y = (int *) 0; return !x && !y; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_volatile=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_volatile=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_c_volatile" >&5 echo "${ECHO_T}$ac_cv_c_volatile" >&6; } if test $ac_cv_c_volatile = no; then cat >>confdefs.h <<\_ACEOF #define volatile _ACEOF fi # Checks for library functions. { echo "$as_me:$LINENO: checking for error_at_line" >&5 echo $ECHO_N "checking for error_at_line... $ECHO_C" >&6; } if test "${ac_cv_lib_error_at_line+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <error.h> int main () { error_at_line (0, 0, "", 0, "an error occurred"); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_error_at_line=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_error_at_line=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_lib_error_at_line" >&5 echo "${ECHO_T}$ac_cv_lib_error_at_line" >&6; } if test $ac_cv_lib_error_at_line = no; then case " $LIBOBJS " in *" error.$ac_objext "* ) ;; *) LIBOBJS="$LIBOBJS error.$ac_objext" ;; esac fi if test $ac_cv_c_compiler_gnu = yes; then { echo "$as_me:$LINENO: checking whether $CC needs -traditional" >&5 echo $ECHO_N "checking whether $CC needs -traditional... $ECHO_C" >&6; } if test "${ac_cv_prog_gcc_traditional+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_pattern="Autoconf.*'x'" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <sgtty.h> Autoconf TIOCGETP _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "$ac_pattern" >/dev/null 2>&1; then ac_cv_prog_gcc_traditional=yes else ac_cv_prog_gcc_traditional=no fi rm -f conftest* if test $ac_cv_prog_gcc_traditional = no; then cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <termio.h> Autoconf TCGETA _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "$ac_pattern" >/dev/null 2>&1; then ac_cv_prog_gcc_traditional=yes fi rm -f conftest* fi fi { echo "$as_me:$LINENO: result: $ac_cv_prog_gcc_traditional" >&5 echo "${ECHO_T}$ac_cv_prog_gcc_traditional" >&6; } if test $ac_cv_prog_gcc_traditional = yes; then CC="$CC -traditional" fi fi for ac_header in stdlib.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX ## ---------------------------------------------------- ## ## Report this to skyeye-developer@lists.gro.clinux.org ## ## ---------------------------------------------------- ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for GNU libc compatible malloc" >&5 echo $ECHO_N "checking for GNU libc compatible malloc... $ECHO_C" >&6; } if test "${ac_cv_func_malloc_0_nonnull+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_malloc_0_nonnull=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined STDC_HEADERS || defined HAVE_STDLIB_H # include <stdlib.h> #else char *malloc (); #endif int main () { return ! malloc (0); ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_malloc_0_nonnull=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_malloc_0_nonnull=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_malloc_0_nonnull" >&5 echo "${ECHO_T}$ac_cv_func_malloc_0_nonnull" >&6; } if test $ac_cv_func_malloc_0_nonnull = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_MALLOC 1 _ACEOF else cat >>confdefs.h <<\_ACEOF #define HAVE_MALLOC 0 _ACEOF case " $LIBOBJS " in *" malloc.$ac_objext "* ) ;; *) LIBOBJS="$LIBOBJS malloc.$ac_objext" ;; esac cat >>confdefs.h <<\_ACEOF #define malloc rpl_malloc _ACEOF fi { echo "$as_me:$LINENO: checking for working memcmp" >&5 echo $ECHO_N "checking for working memcmp... $ECHO_C" >&6; } if test "${ac_cv_func_memcmp_working+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_memcmp_working=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { /* Some versions of memcmp are not 8-bit clean. */ char c0 = '\100', c1 = '\200', c2 = '\201'; if (memcmp(&c0, &c2, 1) >= 0 || memcmp(&c1, &c2, 1) >= 0) return 1; /* The Next x86 OpenStep bug shows up only when comparing 16 bytes or more and with at least one buffer not starting on a 4-byte boundary. William Lewis provided this test program. */ { char foo[21]; char bar[21]; int i; for (i = 0; i < 4; i++) { char *a = foo + i; char *b = bar + i; strcpy (a, "--------01111111"); strcpy (b, "--------10000000"); if (memcmp (a, b, 16) >= 0) return 1; } return 0; } ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_memcmp_working=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_memcmp_working=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_memcmp_working" >&5 echo "${ECHO_T}$ac_cv_func_memcmp_working" >&6; } test $ac_cv_func_memcmp_working = no && case " $LIBOBJS " in *" memcmp.$ac_objext "* ) ;; *) LIBOBJS="$LIBOBJS memcmp.$ac_objext" ;; esac for ac_header in $ac_header_list do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX ## ---------------------------------------------------- ## ## Report this to skyeye-developer@lists.gro.clinux.org ## ## ---------------------------------------------------- ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_func in $ac_func_list do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. For example, HP-UX 11i <limits.h> declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer <limits.h> to <assert.h> if __STDC__ is defined, since <limits.h> exists even on freestanding compilers. */ #ifdef __STDC__ # include <limits.h> #else # include <assert.h> #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for working mktime" >&5 echo $ECHO_N "checking for working mktime... $ECHO_C" >&6; } if test "${ac_cv_func_working_mktime+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_working_mktime=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Test program from Paul Eggert and Tony Leneis. */ #ifdef TIME_WITH_SYS_TIME # include <sys/time.h> # include <time.h> #else # ifdef HAVE_SYS_TIME_H # include <sys/time.h> # else # include <time.h> # endif #endif #include <stdlib.h> #ifdef HAVE_UNISTD_H # include <unistd.h> #endif #ifndef HAVE_ALARM # define alarm(X) /* empty */ #endif /* Work around redefinition to rpl_putenv by other config tests. */ #undef putenv static time_t time_t_max; static time_t time_t_min; /* Values we'll use to set the TZ environment variable. */ static char *tz_strings[] = { (char *) 0, "TZ=GMT0", "TZ=JST-9", "TZ=EST+3EDT+2,M10.1.0/00:00:00,M2.3.0/00:00:00" }; #define N_STRINGS (sizeof (tz_strings) / sizeof (tz_strings[0])) /* Return 0 if mktime fails to convert a date in the spring-forward gap. Based on a problem report from Andreas Jaeger. */ static int spring_forward_gap () { /* glibc (up to about 1998-10-07) failed this test. */ struct tm tm; /* Use the portable POSIX.1 specification "TZ=PST8PDT,M4.1.0,M10.5.0" instead of "TZ=America/Vancouver" in order to detect the bug even on systems that don't support the Olson extension, or don't have the full zoneinfo tables installed. */ putenv ("TZ=PST8PDT,M4.1.0,M10.5.0"); tm.tm_year = 98; tm.tm_mon = 3; tm.tm_mday = 5; tm.tm_hour = 2; tm.tm_min = 0; tm.tm_sec = 0; tm.tm_isdst = -1; return mktime (&tm) != (time_t) -1; } static int mktime_test1 (now) time_t now; { struct tm *lt; return ! (lt = localtime (&now)) || mktime (lt) == now; } static int mktime_test (now) time_t now; { return (mktime_test1 (now) && mktime_test1 ((time_t) (time_t_max - now)) && mktime_test1 ((time_t) (time_t_min + now))); } static int irix_6_4_bug () { /* Based on code from Ariel Faigon. */ struct tm tm; tm.tm_year = 96; tm.tm_mon = 3; tm.tm_mday = 0; tm.tm_hour = 0; tm.tm_min = 0; tm.tm_sec = 0; tm.tm_isdst = -1; mktime (&tm); return tm.tm_mon == 2 && tm.tm_mday == 31; } static int bigtime_test (j) int j; { struct tm tm; time_t now; tm.tm_year = tm.tm_mon = tm.tm_mday = tm.tm_hour = tm.tm_min = tm.tm_sec = j; now = mktime (&tm); if (now != (time_t) -1) { struct tm *lt = localtime (&now); if (! (lt && lt->tm_year == tm.tm_year && lt->tm_mon == tm.tm_mon && lt->tm_mday == tm.tm_mday && lt->tm_hour == tm.tm_hour && lt->tm_min == tm.tm_min && lt->tm_sec == tm.tm_sec && lt->tm_yday == tm.tm_yday && lt->tm_wday == tm.tm_wday && ((lt->tm_isdst < 0 ? -1 : 0 < lt->tm_isdst) == (tm.tm_isdst < 0 ? -1 : 0 < tm.tm_isdst)))) return 0; } return 1; } static int year_2050_test () { /* The correct answer for 2050-02-01 00:00:00 in Pacific time, ignoring leap seconds. */ unsigned long int answer = 2527315200UL; struct tm tm; time_t t; tm.tm_year = 2050 - 1900; tm.tm_mon = 2 - 1; tm.tm_mday = 1; tm.tm_hour = tm.tm_min = tm.tm_sec = 0; tm.tm_isdst = -1; /* Use the portable POSIX.1 specification "TZ=PST8PDT,M4.1.0,M10.5.0" instead of "TZ=America/Vancouver" in order to detect the bug even on systems that don't support the Olson extension, or don't have the full zoneinfo tables installed. */ putenv ("TZ=PST8PDT,M4.1.0,M10.5.0"); t = mktime (&tm); /* Check that the result is either a failure, or close enough to the correct answer that we can assume the discrepancy is due to leap seconds. */ return (t == (time_t) -1 || (0 < t && answer - 120 <= t && t <= answer + 120)); } int main () { time_t t, delta; int i, j; /* This test makes some buggy mktime implementations loop. Give up after 60 seconds; a mktime slower than that isn't worth using anyway. */ alarm (60); for (time_t_max = 1; 0 < time_t_max; time_t_max *= 2) continue; time_t_max--; if ((time_t) -1 < 0) for (time_t_min = -1; (time_t) (time_t_min * 2) < 0; time_t_min *= 2) continue; delta = time_t_max / 997; /* a suitable prime number */ for (i = 0; i < N_STRINGS; i++) { if (tz_strings[i]) putenv (tz_strings[i]); for (t = 0; t <= time_t_max - delta; t += delta) if (! mktime_test (t)) return 1; if (! (mktime_test ((time_t) 1) && mktime_test ((time_t) (60 * 60)) && mktime_test ((time_t) (60 * 60 * 24)))) return 1; for (j = 1; 0 < j; j *= 2) if (! bigtime_test (j)) return 1; if (! bigtime_test (j - 1)) return 1; } return ! (irix_6_4_bug () && spring_forward_gap () && year_2050_test ()); } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_working_mktime=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_working_mktime=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_working_mktime" >&5 echo "${ECHO_T}$ac_cv_func_working_mktime" >&6; } if test $ac_cv_func_working_mktime = no; then case " $LIBOBJS " in *" mktime.$ac_objext "* ) ;; *) LIBOBJS="$LIBOBJS mktime.$ac_objext" ;; esac fi for ac_header in stdlib.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX ## ---------------------------------------------------- ## ## Report this to skyeye-developer@lists.gro.clinux.org ## ## ---------------------------------------------------- ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_func in getpagesize do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. For example, HP-UX 11i <limits.h> declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer <limits.h> to <assert.h> if __STDC__ is defined, since <limits.h> exists even on freestanding compilers. */ #ifdef __STDC__ # include <limits.h> #else # include <assert.h> #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for working mmap" >&5 echo $ECHO_N "checking for working mmap... $ECHO_C" >&6; } if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_mmap_fixed_mapped=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default /* malloc might have been renamed as rpl_malloc. */ #undef malloc /* Thanks to Mike Haertel and Jim Avera for this test. Here is a matrix of mmap possibilities: mmap private not fixed mmap private fixed at somewhere currently unmapped mmap private fixed at somewhere already mapped mmap shared not fixed mmap shared fixed at somewhere currently unmapped mmap shared fixed at somewhere already mapped For private mappings, we should verify that changes cannot be read() back from the file, nor mmap's back from the file at a different address. (There have been systems where private was not correctly implemented like the infamous i386 svr4.0, and systems where the VM page cache was not coherent with the file system buffer cache like early versions of FreeBSD and possibly contemporary NetBSD.) For shared mappings, we should conversely verify that changes get propagated back to all the places they're supposed to be. Grep wants private fixed already mapped. The main things grep needs to know about mmap are: * does it exist and is it safe to write into the mmap'd area * how to use it (BSD variants) */ #include <fcntl.h> #include <sys/mman.h> #if !defined STDC_HEADERS && !defined HAVE_STDLIB_H char *malloc (); #endif /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H # define HAVE_SYS_PARAM_H 1 # endif # ifdef _SC_PAGESIZE # define getpagesize() sysconf(_SC_PAGESIZE) # else /* no _SC_PAGESIZE */ # ifdef HAVE_SYS_PARAM_H # include <sys/param.h> # ifdef EXEC_PAGESIZE # define getpagesize() EXEC_PAGESIZE # else /* no EXEC_PAGESIZE */ # ifdef NBPG # define getpagesize() NBPG * CLSIZE # ifndef CLSIZE # define CLSIZE 1 # endif /* no CLSIZE */ # else /* no NBPG */ # ifdef NBPC # define getpagesize() NBPC # else /* no NBPC */ # ifdef PAGESIZE # define getpagesize() PAGESIZE # endif /* PAGESIZE */ # endif /* no NBPC */ # endif /* no NBPG */ # endif /* no EXEC_PAGESIZE */ # else /* no HAVE_SYS_PARAM_H */ # define getpagesize() 8192 /* punt totally */ # endif /* no HAVE_SYS_PARAM_H */ # endif /* no _SC_PAGESIZE */ #endif /* no HAVE_GETPAGESIZE */ int main () { char *data, *data2, *data3; int i, pagesize; int fd; pagesize = getpagesize (); /* First, make a file with some known garbage in it. */ data = (char *) malloc (pagesize); if (!data) return 1; for (i = 0; i < pagesize; ++i) *(data + i) = rand (); umask (0); fd = creat ("conftest.mmap", 0600); if (fd < 0) return 1; if (write (fd, data, pagesize) != pagesize) return 1; close (fd); /* Next, try to mmap the file at a fixed address which already has something else allocated at it. If we can, also make sure that we see the same garbage. */ fd = open ("conftest.mmap", O_RDWR); if (fd < 0) return 1; data2 = (char *) malloc (2 * pagesize); if (!data2) return 1; data2 += (pagesize - ((long int) data2 & (pagesize - 1))) & (pagesize - 1); if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_FIXED, fd, 0L)) return 1; for (i = 0; i < pagesize; ++i) if (*(data + i) != *(data2 + i)) return 1; /* Finally, make sure that changes to the mapped area do not percolate back to the file as seen by read(). (This is a bug on some variants of i386 svr4.0.) */ for (i = 0; i < pagesize; ++i) *(data2 + i) = *(data2 + i) + 1; data3 = (char *) malloc (pagesize); if (!data3) return 1; if (read (fd, data3, pagesize) != pagesize) return 1; for (i = 0; i < pagesize; ++i) if (*(data + i) != *(data3 + i)) return 1; close (fd); return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_mmap_fixed_mapped=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_mmap_fixed_mapped=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5 echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6; } if test $ac_cv_func_mmap_fixed_mapped = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_MMAP 1 _ACEOF fi rm -f conftest.mmap for ac_header in stdlib.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX ## ---------------------------------------------------- ## ## Report this to skyeye-developer@lists.gro.clinux.org ## ## ---------------------------------------------------- ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for GNU libc compatible realloc" >&5 echo $ECHO_N "checking for GNU libc compatible realloc... $ECHO_C" >&6; } if test "${ac_cv_func_realloc_0_nonnull+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_realloc_0_nonnull=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined STDC_HEADERS || defined HAVE_STDLIB_H # include <stdlib.h> #else char *realloc (); #endif int main () { return ! realloc (0, 0); ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_realloc_0_nonnull=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_realloc_0_nonnull=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_realloc_0_nonnull" >&5 echo "${ECHO_T}$ac_cv_func_realloc_0_nonnull" >&6; } if test $ac_cv_func_realloc_0_nonnull = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_REALLOC 1 _ACEOF else cat >>confdefs.h <<\_ACEOF #define HAVE_REALLOC 0 _ACEOF case " $LIBOBJS " in *" realloc.$ac_objext "* ) ;; *) LIBOBJS="$LIBOBJS realloc.$ac_objext" ;; esac cat >>confdefs.h <<\_ACEOF #define realloc rpl_realloc _ACEOF fi for ac_header in sys/select.h sys/socket.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? 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If the typedef was allowed, the #define below would cause a syntax error. */ #undef _UINT8_T /* Define to empty if `const' does not conform to ANSI C. */ #undef const /* Define to `int' if <sys/types.h> doesn't define. */ #undef gid_t /* Define to `__inline__' or `__inline' if that's what the C compiler calls it, or to nothing if 'inline' is not supported under any name. */ #ifndef __cplusplus #undef inline #endif /* Define to the type of a signed integer type of width exactly 16 bits if such a type exists and the standard includes do not define it. */ #undef int16_t /* Define to the type of a signed integer type of width exactly 32 bits if such a type exists and the standard includes do not define it. */ #undef int32_t /* Define to the type of a signed integer type of width exactly 64 bits if such a type exists and the standard includes do not define it. */ #undef int64_t /* Define to the type of a signed integer type of width exactly 8 bits if such a type exists and the standard includes do not define it. */ #undef int8_t /* Define to rpl_malloc if the replacement function should be used. */ #undef malloc /* Define to `long int' if <sys/types.h> does not define. */ #undef off_t /* Define to rpl_realloc if the replacement function should be used. */ #undef realloc /* Define to `unsigned int' if <sys/types.h> does not define. */ #undef size_t /* Define to `int' if <sys/types.h> does not define. */ #undef ssize_t /* Define to `int' if <sys/types.h> doesn't define. */ #undef uid_t /* Define to the type of an unsigned integer type of width exactly 16 bits if such a type exists and the standard includes do not define it. */ #undef uint16_t /* Define to the type of an unsigned integer type of width exactly 32 bits if such a type exists and the standard includes do not define it. */ #undef uint32_t /* Define to the type of an unsigned integer type of width exactly 64 bits if such a type exists and the standard includes do not define it. */ #undef uint64_t /* Define to the type of an unsigned integer type of width exactly 8 bits if such a type exists and the standard includes do not define it. */ #undef uint8_t /* Define to empty if the keyword `volatile' does not work. Warning: valid code using `volatile' can become incorrect without. Disable with care. */ #undef volatile ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/NEWS�������������������������������������������������������������������������������0000644�0001750�0000144�00000000000�11006126165�012721� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/TODO�������������������������������������������������������������������������������0000644�0001750�0000144�00000001077�10634527740�012743� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������known issue: --------------------- gdb remote debug is not stable type very slow in several testcases short term: ---------- - improve the auto test framework to test network , lcd, flash etc. - mips simulation - x86 simulation - ppc simulation long term: ------------ - mutilple thread implementation in simualtion - a common dynamic translation framework for arm and blackfin lower priority: -------------- - skyeye.conf in XML format - GUI config program for skyeye.conf - improve speed of skyeye simulation - performace test of skyeye simulation, maybe nbench-byte? �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/ChangeLog��������������������������������������������������������������������������0000644�0001750�0000144�00000254227�11023115225�014014� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������2008-06-08 Michael.Kang * DBCT is disabled in current version sinece we have not detect the build environment for DBCT in configure. * Changed files: skyeye-1.2.5/autom4te.cache/output.0 skyeye-1.2.5/autom4te.cache/output.1 skyeye-1.2.5/configure skyeye-1.2.5/configure.in 2008-05-13 Michael.Kang * Fix some build error on solaris platform * Changed files: arch/bfin/mach/bf533_io.c arch/mips/mach/skyeye_mach_nedved.c device/net/skyeye_net_tuntap.c device/net/skyeye_net_vnet.c 2008-05-03 Michael.kang * fix bfd dependency issues on the platforms without bfd library. * Changed files: utils/profile/symbol.[ch] utils/Makefile.am utils/main/skyeye.c Makefile.am 2008-05-03 Michael.Kang * move symbol.[ch] from utils/main to utili/profile directory * moved files: utils/main/symbol.[ch] to utils/profile/symbol.[ch] 2008-05-02 Michael.kang * merge code coverage profile patch to trunk * Changed files: Makefile.am arch/arm/Makefile.am arch/arm/common/armmem.c arch/arm/common/armvirt.c utils/Makefile.am utils/config/skyeye_config.h utils/config/skyeye_options.c utils/config/skyeye_options.h utils/main/skyeye.c * Added files and directory: utils/profile utils/profile/code_cov.c utils/profile/code_cov.h 2008-05-02 Michael.Kang * Add load_addr option, so we can relocate elf image file to another address * Changed files: utils/config/skyeye_config.h utils/config/skyeye_options.c utils/main/skyeye.c 2008-05-02 Michael.Kang * fix lcd crash. The patch provided by Anthony Lee * Changed files: device/lcd/skyeye_lcd_gtk.c 2008-05-01 Michael.Kang * merge the mips simulation code from mips_branch * Now linux can run on mips simulator , but not stable 2008-05-01 Michael.kang * Fix next command during gdb remote debug * Changed files: utils/debugger/gdbserver.c 2008-05-01 Michael.Kang * merge autoconf_branch to trunk * added files: configure.in configure Makefile.am arch/arm/Makefile.am arch/bfin/Makefile.am arch/coldfire/Makefile.am arch/mips/Makefile.am arch/ppc/Makefile.am utils/Makefile.am device/Makefile.am 2008-02-01 Michael.Kang * Add cs8900a driver of linux, so that is convince for us to use it test our netcard simulation * Added directory and file: cs8900a cs8900a/linux_2_6_14_cs8900.diff 2008-02-01 Michael.Kang * Fix the bug. Now cs8900a netcard can run on SkyEye. We can use ftp to transfer file by netcard driver * Changed files: net/dev_net_cs8900a.c 2007-11-15 Michael.Kang * Merge the patch from anthony.lee to support cygwin , BeOS, MacOS * Changed files: skyeye-1.2.4/utils/main/skyeye.h skyeye-1.2.4/arch/arm/mach/skyeye_mach_at91rm92.c skyeye-1.2.4/arch/ppc/common/ppc_mmu.c skyeye-1.2.4/arch/ppc/common/types.h skyeye-1.2.4/arch/coldfire/mach/skyeye_mach_mcf5272.c skyeye-1.2.4/Makefile 2007-11-08 Michael.Kang * Merge the patch from anthony.Lee to support MacOS on x86. * Changed files: arch/arm/dbct/arm2x86.c arch/arm/dbct/arm2x86.h arch/arm/dbct/arm2x86_mem.c arch/arm/dbct/tb.c device/net/skyeye_net_tuntap.c device/net/skyeye_net_vnet.c 2007-11-07 Michael.Kang * Merge the patch from Marc Hoffman to support MACOS * Changed files: arch/arm/dbct/tb.c device/net/skyeye_net_tuntap.c device/net/skyeye_net_vnet.c 2007-11-06 Michael.Kang * Fix a bug in x86_64, we should always define 32bit variable to "int" type, but not "long" type. * Changed files: arch/ppc/common/ppc_boot.h 2007-11-03 Michael.Kang * Fix a bug of timer write.Now ticker.exe of rtems csb350 BSP can run on SkyEye. * Changed files: arch/coldfire/mach/skyeye_mach_mcf5272.c arch/coldfire/mach/mcf5272.h 2007-11-03 Michael.Kang * Fix a bug in DBGU of at91rm9200, now uboot can receive some char * Changed files: arch/arm/mach/skyeye_mach_at91rm92.c 2007-11-02 Michael.Kang * workaound for round-robin replace of TLB0 entry, not same with the replacement algorithms described in e500 manual, need to be fixed later. * Changed files: arch/ppc/common/ppc_mmu.c arch/ppc/common/ppc_e500_exc.c 2007-10-31 Michael.Kang * Add some function of bootloader, now we can boot unmodified linux without u-boot * UART recv interrupt simulation is completed. * Add SCC2 support and some register of PIC * Changed files: arch/ppc/common/ppc_mmu.c arch/ppc/common/ppc_cpu.h arch/ppc/common/ppc_arch_interface.c arch/ppc/common/ppc_e500_exc.c Makefile * Added files: arch/ppc/common/ppc_boot.c arch/ppc/common/ppc_boot.h 2007-10-29 Michael.Kang * CPM uart interrupt is implemented.Now ppc simulator can receive some characers and exceute the command from uart.But not stable. * A isel instruction is added * Changed files: ppc/common/ppc_mmu.c ppc/common/ppc_dec.c ppc/common/ppc_cpu.h ppc/common/ppc_arch_interface.c ppc/common/ppc_e500_exc.c ppc/mach/skyeye_mach_mpc8560.c * Added files: ppc/common/ppc_irq.h 2007-10-28 Michael.Kang * some important improvement for ppc simulation.Now ppc simulation is near to its success. Sash can run correctly ,but cpm_uart receive function is not implement. * Fix the bug in TLB entry update * Fix the bug in cpm uart, there is a data that have not been type-tran * Implement dbcz, that solves some critical bug during run linux * Workaround permission check in mtspr and mfspr * Changed files: ppc/common/ppc_arch_interface.c ppc/common/ppc_mmu.c ppc/common/ppc_e500_exc.c ppc/common/ppc_opc.c ppc/common/ppc_dec.c 2007-10-10 Michael.Kang * Commit the patch provided by Anthony Lee, that can solve some compilation issues under MingW environment. * Changed files: skyeye-v1/trunk/Makefile skyeye-v1/trunk/arch/arm/mach/skyeye_mach_ep7312.c skyeye-v1/trunk/arch/arm/mach/skyeye_mach_s3c44b0x.c skyeye-v1/trunk/arch/ppc/common/types.h skyeye-v1/trunk/device/nandflash/nandflash_smallblock.c skyeye-v1/trunk/device/nandflash/nandflash_smallblock.h skyeye-v1/trunk/device/net/skyeye_net_tap_win32.c skyeye-v1/trunk/device/uart/skyeye_uart_pipe.c skyeye-v1/trunk/device/uart/skyeye_uart_stdio.c skyeye-v1/trunk/utils/debugger/gdbserver.c skyeye-v1/trunk/utils/main/skyeye.c 2007-10-10 Michael.Kang * Add sram defination and uart initialization for csb360 BSP of RTEMS * Now csb360 of RTEMS can run on SkyEye * Changed files: arch/coldfire/common/cf_arch_interface.c arch/coldfire/common/memory.c arch/coldfire/mach/skyeye_mach_mcf5272.c 2007-10-07 Michael.Kang * More improvements for ppc simulation * Changed files: arch/ppc/common/io.h arch/ppc/common/ppc_alu.c arch/ppc/common/ppc_arch_interface.c arch/ppc/common/ppc_cpu.c arch/ppc/common/ppc_e500_exc.c arch/ppc/common/ppc_memory.h arch/ppc/common/ppc_mmu.c arch/ppc/common/ppc_opc.c 2007-10-07 Michael.Kang * commit the patch provided by rayx, that fix some bugs in lpc simulation * Now rtl22xx BSP of RTEMS can run on SkyEye. * Changed files: arch/arm/mach/skyeye_mach_lpc2210.c 2007-09-07 Michael.Kang * A lot of improvement for ppc simualtion * timer interrupt seems work normally * Uart seems work normally * Add system call exception * Fix the bug in implementation of wrtee and wrteei instruction * Add some register defination for some peripherals * Changed files: ppc/common/ppc_cpu.h ppc/common/ppc_arch_interface.c ppc/common/ppc_mmu.c ppc/common/types.h ppc/common/ppc_e500_exc.c ppc/common/ppc_alu.c ppc/common/ppc_opc.c ppc/mach/skyeye_mach_mpc8560.c ppc/mach/skyeye_mach_mpc823.c 2007-08-27 Michael.Kang * Implement remap function for LPC, now uClinux can run on SkyEye. * Changed files: common/arminit.c common/armmem.c common/armdefs.h common/arm_arch_interface.c 2007-08-26 Michael.Kang * Add more register defination for MPC8560. * Fix the bug of TLB update. * Changed files: ppc/common/ppc_cpu.h ppc/common/ppc_arch_interface.c ppc/common/ppc_mmu.c ppc/common/ppc_e500_exc.c ppc/common/ppc_alu.c ppc/mach/skyeye_mach_mpc8560.c 2007-08-26 Michael.Kang * improved by Stano. Now rtl8019 netcard simulation can run stable. * Changed files: dev_net_rtl8019.c 2007-08-26 Michael.Kang * Add more timer support. Now redboot can run on AT91 simulation * Workaround for 8019 driver of linux-2.4.x in uClinux-dist * Changed files: skyeye_mach_at91.c 2007-08-26 Michael.Kang * Add linux_driver directory to contains some driver source for linux OS * Add rtl8019.[ch] to our source repository. Originally provided by Anthony Lee, emhanced by Stanislav Meduna. * Add file and directory: misc/linux_driver misc/linux_driver/rtl8019 misc/linux_driver/rtl8019/rtl8019.c misc/linux_driver/rtl8019/rtl8019.h misc/linux_driver/rtl8019/README 2007-07-26 Michael.Kang * add NV implementation to auto update TLB * Changed files: arch/ppc/common/ppc_mmu.c arch/ppc/common/ppc_mmu.h arch/ppc/common/ppc_e500_exc.c 2007-07-26 Michael.Kang * workaround ICE_read of wrong address for the * ppc debugger. That is a * bug that need to be fixed in the future. * Changed files: arch/ppc/common/ppc_arch_interface.c 2007-07-26 Michael.Kang * Add isel instruction implementation * Changed files: arch/ppc/common/ppc_dec.c arch/ppc/common/ppc_alu.c arch/ppc/common/ppc_alu.h 2007-07-24 Michael.Kang * Fix the compilation issue for "Make No_BFD". That is reported by Anthony Lee * Changed files: Makefile utils/main/skyeye.c 2007-07-24 Michael.Kang * Fix the bug cuased by register defination. I can not find useful info in GDBSOURCE/gdb/regformats/reg-ppc.dat for register layout of ppc * Changed files: utils/debugger/ppc_regdefs.c 2007-07-24 Michael.Kang * We setup the initial tlb entry to map 0x0 to 0xc0000 before linux boot for convience. * Since mmu always enbaled in ppc architecture, we read/write virual address in the current ICE_read/write_byte function of ppc arch. * Changed files: ppc/common/ppc_arch_interface.c ppc/common/ppc_mmu.c ppc/common/ppc_mmu.h ppc/common/ppc_e500_exc.c ppc/common/ppc_opc.c 2007-07-23 Michael.Kang * More improvement for mips simulation.Now we can output something by uart in the linux boot stage. * Changed files: mips/common/exception.c mips/common/emul.c mips/common/decoder.c mips/common/cp0.c mips/common/mips_arch_interface.c mips/mach/skyeye_mach_au1100.c 2007-07-20 Michael.Kang * Fix the bug in mips debugger. Now we can debug mips program by gdb * Changed files: debugger/gdbserver.c debugger/mips_regdefs.c 2007-07-19 Michael.Kang * Fix the bug in free_bootmem_core of linux source.Due to incorrect sign extend for 32bit * add more register simulation for au1100 * Changed files: arch/mips/common/decoder.c arch/mips/common/exception.c arch/mips/common/instr.h arch/mips/common/mips_arch_interface.c arch/mips/mach/skyeye_mach_au1100.c * Added files: arch/mips/mach/au1000.h 2007-07-19 Michael.Kang * Fix the bug caused by uart read/write, add more register support * Changed files: skyeye_mach_at91rm92.c at91rm92.h 2007-07-19 Michael.Kang * add more timer support for at91 simulation * Changed files: arch/arm/mach/skyeye_mach_at91.c 2007-07-07 Michael.Kang * Big improvement for mips simulation, add more register and instruction * Changed files: mips/common/mipsio.c mips/common/emul.c mips/common/instr.h mips/common/decoder.c mips/common/mipsmem.c mips/common/dcache.c mips/common/emul.h mips/common/tlb.c mips/common/cp0.c mips/common/mips_arch_interface.c mips/mach/skyeye_mach_au1100.c 2007-07-07 Michael.Kang * add file dependency for ppc_cpu.h. A big bug fixed. * Changed files: Makefile 2007-07-07 Michael.Kang * add more register defination for ppc cpu struct * Changed files: arch/ppc/common/ppc_arch_interface.c arch/ppc/common/ppc_cpu.c arch/ppc/common/ppc_cpu.h arch/ppc/common/ppc_dec.c arch/ppc/common/ppc_exc.c arch/ppc/common/ppc_mmu.c arch/ppc/common/ppc_opc.c 2007-07-03 Michael.Kang * commit patch from Anthony Lee <don.anthony.lee@gmail.com> to fix the * compilation issue on BeOS * Changed files: arch/ppc/common/types.h utils/main/elf32.h utils/main/skyeye.c 2007-07-03 Michael.Kang * Add kseg0,kseg1 support, but not sure if it is correct... * Changed files: arch/mips/common/mips_arch_interface.c arch/mips/common/mipsmem.c arch/mips/common/tlb.c 2007-07-03 Michael.Kang * add isram_read_long function and clean some useless code. * Changed files: bfin/common/iomem.c bfin/common/bfin-sim.h bfin/common/bfin-dis.c bfin/common/bfin_arch_interface.c bfin/mach/bf533_io.c 2007-07-03 Michael.Kang * Add symbol print support in debug log * Added files: utils/main/symbol.c utils/main/symbol.h * Changed files: utils/main/skyeye.c 2007-07-03 Michael.Kang * Add simulation for imx processor of freescale, not complete... * Changed files: Makefile * Added files: arch/arm/mach/skyeye_mach_9238imx.c arch/arm/mach/imx-regs.h 2007-07-03 Michael.kang * Add some new instructions implementation,such as isel. * Add some initial tlb map for booting linux * Changed files: ppc/common/ppc_cpu.h ppc/common/ppc_arch_interface.c ppc/common/ppc_mmu.c ppc/common/ppc_mmu.h ppc/common/ppc_memory.h ppc/common/ppc_alu.c ppc/common/ppc_opc.c ppc/common/ppc_alu.h ppc/common/ppc_dec.c 2007-06-15 Michael.Kang * add remap support for lpc simulation, but lpc simulation seems still not work. * modified files: common/armdefs.h common/arminit.c mach/skyeye_mach_lpc.c 2007-06-15 Michael.Kang * add some register defination for 2410 simulation * Changed files: skyeye_mach_s3c2410x.c 2007-06-15 Michael.Kang * add some error handler for mips simulation * Changed files: arch/mips/common/mips_arch_interface.c arch/mips/common/mipsmem.c 2007-06-15 Michael.Kang * add ppc simulation to SkyEye * Added files: arch/ppc/* 2007-06-12 Michael.Kang * modify the timer prescale value of bf533 simulation. The patch is provided by Alain Schaefer. * Changed files: arch/bfin/mach/bf533_io.c 2007-06-06 Michael.Kang * add dbgu and more uart support for at91rm9200 platform * Changed files: arch/arm/mach/skyeye_mach_at91rm92.c arch/arm/mach/at91rm92.h 2007-04-14 anthonylee * Speed-up lookup-table dependable LCD simulation. * Clean-up LCD device framework. * Implemented native mmap/munmap() for BeOS/Windows. * Changed files: arch/arm/common/armio.c device/skyeye_device.c[h] device/lcd/dev_lcd_s3c44b0x.c device/lcd/skyeye_lcd.c[h] device/lcd/skyeye_lcd_beos.c[cpp, h] device/lcd/skyeye_lcd_gtk.c device/lcd/skyeye_lcd_win32.c utils/portable/mman.c * Added files: utils/portable/beos/mman.c utils/portable/win32/mman.c 2007-04-11 anthonylee * Implemented UART_PIPE for Windows, test on HyperTerminal. * Fixed RTL8019AS for polling mode, test on RedBoot. * Changed files: device/uart/skyeye_uart_pipe.c device/net/dev_net_rtl8019.c 2007-04-08 anthonylee * Pick up the original works: S3C3410X simulation. * Changed files: Makefile arch/arm/common/arm_arch_interface.c * Added files: arch/arm/mach/s3c3410x.h arch/arm/mach/skyeye_mach_s3c3410x.c 2007-04-05 anthonylee * Fixed Timer/BDMA of S3C44B0X simulation. * Added Am29LV160,Am29LV800 flash simulation. * Added "dump" option for flash simulation. * Fixed UART/TIMER of S3C2410X simulation, now it can run RedBoot. * Fixed open mode for MinGW, now "make NO_BFD=1" on MinGW OK. * Fixed write overflow of RTL8019AS simulation. * Changed files: Makefile README arch/arm/mach/skyeye_mach_s3c2410x.c arch/arm/mach/skyeye_mach_s3c44b0x.c device/flash/dev_flash_sst39lvf160.c device/flash/skyeye_flash.c[h] device/net/dev_net_rtl8019.c utils/config/skyeye_options.c[h] utils/main/skyeye.c utils/portable/mman.c * Added files: device/flash/dev_flash_am29.c[h] 2007-04-03 anthonylee * Added SST39LF/VF160 flash simulation: skyeye.conf example: mem_bank: map=F, type=RW, addr=0x00000000, size=0x00020000, file=./u-boot.bin mem_bank: map=F, type=RW, addr=0x00020000, size=0x001e0000, file=./uImage flash: type=SST39VF160, base=0x00000000, size=0x00200000 * Changed files: Makefile device/flash/skyeye_flash.c[h] * Added files: device/flash/dev_flash_sst39lvf160.c[h] 2007-04-01 anthonylee * Added 16-bits mode of RTL8019AS device: skyeye.conf example: net: type=rtl8019_16, ethmod=tuntap, hostip=10.0.0.1 * Added simple JTAG DCC Terminal simulation: skyeye.conf example: uart: mod=stdio, converter=dcc * Changed files: Makefile device/net/dev_net_rtl8019.c[h] device/uart/skyeye_uart.c[h] utils/config/skyeye_options.c[h] utils/main/skyeye.c * Added files: device/uart/skyeye_uart_cvt_dcc.c 2007-03-30 anthonylee * Added NO_CHECK option to Makefile * Added skyeye_convert_color_from_lcd_dma() helper function. * Fixed LCD of S3C44B0X simualtion to support big-endian. * Fixed for running Blackfin/Coldfire/MIPS simulation as non bfd library. * Changed files: Makefile device/lcd/dev_lcd_s3c44b0x.c device/lcd/skyeye_lcd.c[h] device/lcd/skyeye_lcd_gtk.c device/lcd/skyeye_lcd_win32.c device/lcd/skyeye_lcd_beos.cpp[h] utils/main/elf32.h utils/main/skyeye.c 2007-03-28 anthonylee * Added check scripts for Makefile * Added a "-b" option to specify big endian when non "-e" option. * Fixed for big endian, now it seems OK. * Changed files: Makefile arch/arm/common/arm_arch_interface.c arch/arm/mach/skyeye_mach_s3c44b0x.c arch/arm/mach/s3c44b0.h utils/main/skyeye.c * Added files: utils/scripts/check-bfd.sh utils/scripts/check-bigendian.sh utils/scripts/check-gcc.sh utils/scripts/check-x86-asm.sh 2007-03-27 Michael.Kang * merge zied's patch for support tracepoint. * Changed files: arch/arm/common/arm_arch_interface.c arch/arm/common/armemu.c Makefile utils/debugger/gdbserver.c utils/debugger/skyeye2gdb.h utils/main/skyeye.c * Added files: utils/debugger/gdb_tracepoint.c utils/debugger/gdb_tracepoint.h 2007-03-27 anthonylee * Added sound device framework, the pcm module of sound simulation uncompleted yet. * Changed files: Makefile README arch/arm/mach/s3c44b0.h arch/arm/mach/skyeye_mach_s3c44b0x.c device/skyeye_device.[ch] device/sound/dev_sound_s3c44b0x.c utils/config/skyeye_config.h utils/config/skyeye_options.[ch] * Added files: device/sound/skyeye_sound.[ch] device/sound/skyeye_sound_pcm.c 2007-03-25 anthonylee * Added DMA, IIS of S3C44B0X simulation. * Added IIS Sound of S3C44B0X simulation (just for Windows): $ make EXTRA_CFLAGS="-DS3C44B0X_SOUND" EXTRA_LIBS="-lwinmm" * Changed files: arch/arm/mach/skyeye_mach_s3c44b0x.c arch/arm/mach/s3c44b0.h * Added files: device/sound/dev_sound_s3c44b0x.c 2007-03-22 anthonylee * WARNING: Revision 136, if anybody want to revert it. * Added additional options for cross-compile to Makefile. * Added touchscreen device framework without changing any existing files, see "README" for more about configuration. * Removed the oldest s3c44b0 simulation. * Changed files: Makefile README arch/arm/common/arm_arch_interface.c device/lcd/skyeye_lcd.c device/skyeye_device.c device/skyeye_device.h utils/config/skyeye_config.h utils/config/skyeye_options.c utils/config/skyeye_options.h * Added files: device/touchscreen/dev_touchscreen_skyeye.c device/touchscreen/skyeye_touchscreen.c device/touchscreen/skyeye_touchscreen.h * Removed files: arch/arm/mach/skyeye_mach_s3c44b0.c 2007-03-20 anthonylee * Cleanup Makefile system. * Fixed for compiling with gcc-3.x on BeOS, now DBCT and MIPS can compile on BeOS without any modification. * Changed files: Makefile arch/coldfire/Makefile arch/coldfire/common/Makefile arch/coldfire/i_5206/Makefile arch/coldfire/tracer/Makefile arch/ppc/Makefile arch/ppc/common/Makefile arch/ppc/mach/Makefile utils/portable/beos/tap_driver/Makefile arch/coldfire/mach/skyeye_mach_mcf5249.c arch/coldfire/mach/skyeye_mach_mcf5272.c arch/mips/common/decoder.c arch/mips/common/emul.h arch/mips/common/inttypes.h utils/debugger/cf_regdefs.c utils/portable/beos/stdint.h * Removed files: arch/coldfire/i_5206/Makefile.in arch/coldfire/tracer/Makefile.in 2007-03-20 anthonylee * Disabled gcc-2.x support. It means skyeye won't support generic BeOS any more except that you have a modified gcc-3.x. * Fixed skyeye_find_lcd_dma() for support mips architecture. * Added au1100 LCD support, but uncompleted yet until ksh finished the au1100 simulation. * Changed files: Makefile device/lcd/skyeye_lcd.[ch] utils/config/skyeye_arch.c * Added files: device/lcd/dev_lcd_au1100.[ch] 2007-03-19 anthonylee * Replaced the codes based on sigaction with portable functions in net device. * Cleanup the useless codes of "device/net/dev_net_s3c4510b.c". * Changed files: device/net/dev_net_rtl8019.[ch] device/net/dev_net_cs8900a.[ch] device/net/dev_net_s3c4510b.c 2007-03-17 anthonylee * Changed ARM dependent codes for write more LCD drivers. Now it's suitable to write drivers more than ARM, such as au1100 LCD. * Disabled closable action of GTK_LCD's window. * Completed WATCHDOG/RTC of S3C44B0X simulation. * Improved timer of S3C44B0X simulation to make it more near realtime. * Improved UART Rx FIFO of S3C44B0X simulation for speed. * Removed useless codes for MinGW from "skyeye.c". * Changed files: arch/arm/mach/skyeye_mach_s3c44b0x.c device/lcd/skyeye_lcd.c device/lcd/skyeye_lcd.h device/lcd/skyeye_lcd_beos.c device/lcd/skyeye_lcd_gtk.c device/lcd/skyeye_lcd_win32.c utils/main/skyeye.c utils/portable/gettimeofday.h 2007-03-16 ksh * some structure is redesigned to contain more machine simulation. * 5272 simulation is finished.uClinux can run on our SkyEye.But some bugs still exist. * Added files: arch/coldfire/i_5206/i_div.c arch/coldfire/mach/skyeye_mach_mcf5272.c arch/coldfire/mach/mcf5272.h * Changed files: Makefile arch/coldfire/i_5206/Makefile.in arch/coldfire/i_5206/Makefile arch/coldfire/common/cf_arch_interface.c arch/coldfire/common/i.c arch/coldfire/common/memory.c arch/coldfire/common/memory.h arch/coldfire/mach/skyeye_mach_mcf5249.c 2007-03-14 ksh * directory structure is adapted.I move some tools or some code not compiled by make command to misc directory. I think that maybe more clear for our source tree. These include utils/conf, utils/tools/ etc. * Changed dir: utils/tools/auto_test utils/conf utils/tools/dev-cpp_support * added dir: misc misc/gdb 2007-03-14 ksh * add teawater's gdb support.Now you can use gdb to debug the code run on SkyEye. * Added files: misc/gdb/README misc/gdb/skyeye_1.2_for_gdb_6.4.diff 2007-03-14 anthonylee * Fixed S3C44B0X simulation for UART, NET. Now our S3C44B0X simulation finished Interrupt, UART, Timer, LCD, NET. * Fixed "hostip" option support for TAP_Win32 (just NT/2K/XP works). * Fixed RTL8019AS ether card simulation. * Changed files: arch/arm/mach/skyeye_mach_s3c44b0x.c device/net/skyeye_net_tap_win32.c device/net/dev_net_rtl8019.c 2007-03-07 ksh * workaround for "call _real_start" in bf537 boot code.You can get more info by the URL: http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_id=141&tracker_item_id=2781 * Changed files: arch/bfin/common/bfin-dis.c 2007-03-07 ksh * Change some io functions to functions of machine_config_t structure * Changed files: common/mipsio.c 2007-03-07 ksh * add some peripherals define for integrator machine * Changed files: skyeye_mach_integrator.c 2007-03-07 ksh * improve implementation of au1100 and nedved machine * added files: arch/mips/mach/skyeye_mach_au1100.c arch/mips/mach/skyeye_mach_nedved.c * Changed files: Makefile 2007-03-07 ksh * fix a bug by update interrupt mode of uart * Changed files: arch/coldfire/mach/skyeye_mach_mcf5249.c 2007-03-07 ksh * improve bf537 simulation for different irq number comparing to bf533 * Changed files: arch/bfin/mach/bf537_io.c 2007-03-06 anthonylee * Rewrite S3C44B0X implementation, now the old version can replace with it, but something still has to be improved. Please replace "s3c44b0" with "s3c44b0x" in "skyeye.conf" to try the new implementation. * Changed files: Makefile arch/arm/common/arm_arch_interface.c device/lcd/dev_lcd_s3c44b0x.c * Added files: arch/arm/mach/skyeye_mach_s3c44b0x.c 2007-03-03 anthonylee * Just enable DBCT on gcc-3.x * Added BONE headers path to "Makefile" for modified gcc-3.x on BeOS * Added "stdint.h" for BeOS * Fixed for uart framework * Added some portable functions * Reformated some files * Changed files: Makefile arch/arm/common/armdefs.h arch/bfin/mach/bf533_io.c arch/bfin/mach/bf537_io.c arch/coldfire/common/memory.c arch/codefire/mach/skyeye_mach_mcf5249.c arch/ppc/common/bus.c arch/ppc/common/bus.h arch/ppc/common/cpu_ppc.h arch/ppc/common/idecode_ppc.h arch/ppc/common/instructions_ppc.c arch/ppc/common/Makefile arch/ppc/common/mmu_ppc.c device/net/skyeye_net_tap_beos.c device/net/skyeye_net_tuntap.c device/uart/skyeye_uart.c device/uart/skyeye_uart.h device/uart/skyeye_uart_stdio.c utils/config/skyeye_arch.c utils/config/skyeye_defs.h utils/config/skyeye_types.h utils/debugger/skyeye2gdb.c utils/portable/mman.c * Added files: utils/portable/gettimeofday.c utils/portable/gettimeofday.h utils/portable/usleep.c utils/portable/usleep.h utils/portable/beos/stdint.h utils/portable/beos/usleep.c utils/portable/win32/gettimeofday.c utils/portable/win32/usleep.c 2007-03-02 ksh * add integrator support, not complete.. * added files: skyeye_mach_integrator.c 2007-03-02 ksh * fix bug in coldfire debugger and add endian flag * Changed files: debugger/arm_regdefs.c debugger/ppc_regdefs.c debugger/cf_regdefs.c debugger/skyeye2gdb.c debugger/arch_regdefs.c 2007-03-02 ksh * add armv6 support * Changed files: arm/common/arminit.c arm/common/armemu.c arm/common/armdefs.h arm/common/arm_arch_interface.c arm/mach/skyeye_mach_at91rm92.c arm/mach/skyeye_mach_ns9750.c arm/mach/s3c2410x.h 2007-03-02 ksh * add bf537 support * Added files: bfin/mach/bf537_io.c 2007-03-02 ksh * The framework of blackfin simulation is adapted for add new blackfin mach * Changed files: common/dma.h common/iomem.c common/bfin-sim.h common/types.h common/sysname.h common/bfin-dis.c common/bfin_arch_interface.c mach/bf533_io.h mach/bf533_irq.h mach/bf533_io.c 2007-03-02 ksh * improve coldfire simulation, now uclinux kernel can run on SkyEye * Changed files: arch/coldfire/common/cf_arch_interface.c arch/coldfire/common/exception.c arch/coldfire/common/memory.c arch/coldfire/common/memory.h arch/coldfire/i_5206/i_movec.c 2007-03-02 ksh * add coldfire 5249 support * added directories and files: arch/coldfire/mach arch/coldfire/mach/mcf5249.h arch/coldfire/mach/skyeye_mach_mcf5249.c 2007-02-09 anthonylee * Fixed s3c2410x for running linux-2.6.20, it contains: Corrected GPIO for CPU ID. Corrected UFSTAT for length of URXH. * Changed files: arch/arm/mach/skyeye_mach_s3c2410x.c 2007-02-05 ksh * fix two bug in bf533 interrupt implementation * add a new vector instruction for blackfin simulation * Changed files: arch/bfin/mach/bf533_io.c bfin/common/bfin-dis.c 2007-02-05 ksh * fix a bug related to the timing issue of raise instruction, we should execute the instruction after raise instruction, then we trigger interrupt caused by raise. * Changed files: arch/bfin/common/bfin-dis.c arch/bfin/common/bfin_arch_interface.c 2007-02-03 anthonylee * Added another auto_test script for bash. * Changed files: utils/tools/auto_test/exec_skyeye.sh utils/tools/auto_test/exec_skyeye_dbct.sh * Added files: utils/tools/auto_test/another_auto_test 2007-02-02 anthonylee * Added TAP driver for SkyEye on BeOS, see "utils/portable/beos/tap_driver/README" for more detail. * Added net and lcd simulation for BeOS, tested on R5/BONE. * Disabled setjmp/longjmp in "utils/main/skyeye.c" on BeOS for multi-thread safe. * Renamed files: device/net/skyeye_net_tap.c => device/net/skyeye_net_tap_win32.c * Changed files: Makefile arch/ppc/common/byteorder.h device/lcd/skyeye_lcd.h device/lcd/skyeye_lcd.c device/net/skyeye_net_tuntap.c device/uart/skyeye_uart.c device/uart/skyeye_uart_pipe.c device/uart/skyeye_uart_stdio.c utils/config/skyeye_options.c utils/debugger/gdbserver.c utils/main/skyeye.c utils/portable/mman.c * Added files: device/lcd/skyeye_lcd_beos.c device/lcd/skyeye_lcd_beos.cpp device/lcd/skyeye_lcd_beos.h device/net/skyeye_net_tap_beos.c utils/portable/beos/tap_driver/Makefile utils/portable/beos/tap_driver/README utils/portable/beos/tap_driver/skyeye_tap.c utils/portable/beos/tap_driver/skyeye_tap.h 2007-01-30 anthonylee * A little step for BeOS port, the BeOS port just for my favorite, but both net and lcd simulation not available on BeOS. * BeOS port just work on BONE version, test OK on MinGW/CygWin. * The gcc on BeOS don't support the code style of current MIPS simulation, so I turn off the MIPS simulation on BeOS. * Fixed for CygWin * Added portable function * Changed files: Makefile arch/arm/common/armdefs.h arch/arm/common/armmem.c arch/arm/dbct/tb.c arch/bfin/mach/bf533_io.c arch/mips/common/dcache.c arch/ppc/common/bus.c arch/ppc/common/bus.h arch/ppc/common/byteorder.h arch/ppc/common/cpu_ppc.c arch/ppc/common/cpu_ppc.h arch/ppc/common/idecode_ppc.c arch/ppc/common/idecode_ppc.h arch/ppc/common/instructions_ppc.c arch/ppc/common/mmu_ppc.c device/lcd/skyeye_lcd_win32.c device/net/dev_net_cs8900a.c device/net/dev_net_rtl8019.c device/net/dev_net_s3c4510b.c device/net/skyeye_net_tuntap.c device/net/skyeye_net_vnet.c utils/config/skyeye_arch.c utils/config/skyeye_defs.h utils/config/skyeye_types.h utils/debugger/arch_regdefs.c utils/debugger/gdbserver.c utils/debugger/skyeye2gdb.c utils/main/skyeye.c * Added files: utils/portable/mman.c utils/portable/mman.h 2007-01-29 anthonylee * Fixed LCD_GTK model to support "lcd_lookup_color()" * Cleanup LCD_WIN32 and LCD_S3C44B0X * Changed files: device/lcd/dev_lcd_ep7312.c device/lcd/dev_lcd_s3c44b0x.c device/lcd/skyeye_lcd_gtk.c device/lcd/skyeye_lcd_win32.c 2007-01-29 ksh * fix a bug about gpio address range in 2410 simulation * Changed files: arch/arm/mach/skyeye_mach_at91.c arch/arm/mach/skyeye_mach_s3c2410x.c 2007-01-29 ksh * coldfire simulation is improved. * Changed files: arch/coldfire/common/cf_arch_interface.c arch/coldfire/common/memory.c 2007-01-29 ksh * powerpc simulation is improved. but still a lot of thing to do. * Changed files: arch/ppc/common/bus.c arch/ppc/common/ppc_arch_interface.c 2007-01-29 ksh * some code is re-formated * Changed files: utils/config/skyeye_arch.h utils/config/skyeye_config.h utils/config/skyeye_types.h utils/main/skyeye.c 2007-01-29 ksh * coldfire debug function is improved * Changed files: utils/debugger/cf_regdefs.c 2007-01-29 ksh * some improved for blackfin simualtion * Changed files: arch/bfin/common/bfin-dis.c arch/bfin/common/bfin_arch_interface.c arch/bfin/common/iomem.c arch/bfin/common/mem_map.h arch/bfin/mach/bf533_io.c 2007-01-28 anthonylee * TODO: support virtual screen * Added lcd_lookup_color() function to "struct lcd_device", but just LCD_WIN32 model worked, LCD_GTK model need to be changed yet. * Fixed for s3c44b0x lcd simulation, now it seems OK. * Changed files: arch/arm/mach/skyeye_mach_s3c44b0.c device/lcd/dev_lcd_s3c44b0x.c device/lcd/skyeye_lcd.h device/lcd/skyeye_lcd_gtk.c device/lcd/skyeye_lcd_win32.c 2007-01-27 anthonylee * Try s3c44b0x lcd simulation * Fixed maximum number of uart devices * Changed files: Makefile utils/config/skyeye_config.h device/lcd/skyeye_lcd.c * Added files: device/lcd/dev_lcd_s3c44b0x.c device/lcd/dev_lcd_s3c44b0x.h 2007-01-24 anthonylee * The revision is 19, Merged from the NG branch * Added new uart device frame UART_SIM_STDIO UART_SIM_PIPE(except MinGW) UART_SIM_NET(not yet) At default, SkyEye try UART_SIM_STDIO, and you can add the line like below to "skyeye.conf" uart: mod=pipe, desc_in=/dev/ttyS1, desc_out=/dev/ttyS1 or uart: mod=pipe, desc=/dev/ttyS1 or uart: fd_in=/dev/ttyS1, fd_out=/dev/ttyS1 * Fixed uart of sa1100 implementation * Fixed lcd_setup() --- memset's sizeof argument * Minor cleanup for uart device and MinGW * Moved SKYEYE4ECLIPSE from "skyeye_options.c" to "skyeye_config.c" * Added warning when user uses rxvt shell on MinGW * Fixed Makefile for cleanup the objects of ppc simulation. * Removed "-mthreads" from Makefile on CygWin platform. * Changed files: Makefile arch/arm/common/arm_arch_interface.c arch/arm/common/armdefs.h arch/arm/common/arminit.c arch/arm/common/mmu/arm7100_mmu.c arch/arm/common/mmu/arm920t_mmu.c arch/arm/common/mmu/arm926ejs_mmu.c arch/arm/common/mmu/cache.c arch/arm/common/mmu/maverick.c arch/arm/common/mmu/rb.c arch/arm/common/mmu/sa_mmu.c arch/arm/common/mmu/tlb.c arch/arm/common/mmu/wb.c arch/arm/common/mmu/xscale_copro.c arch/arm/mach/skyeye_mach_*.c arch/bfin/mach/bf533_io.c arch/coldfire/common/Makefile arch/coldfire/i_5206/Makefile arch/codefire/tracer/Makefile arch/mips/mach/nedeved.c arch/ppc/common/Makefile arch/ppc/mach/Makefile device/flash/armflash.c device/flash/dev_flash_intel.c device/flash/skyeye_flash.c device/flash/skyeye_flash.h device/net/if_vnet.h device/net/skyeye_net_tap.c utils/config/syeye_arch.c utils/config/skyeye_config.c utils/config/skyeye_config.h utils/config/skyeye_options.c utils/config/skyeye_options.h utils/debugger/arch_regdefs.c utils/debugger/skyeye2gdb.c utils/main/skyeye.c * Removed files: utils/stub/skyeye_win32_stdio.c * Added files: device/uart/skyeye_uart.c device/uart/skyeye_uart.h device/uart/skyeye_uart_net.c device/uart/skyeye_uart_pipe.c device/uart/skyeye_uart_stdio.c 2007-01-14 anthonylee * Removed multi-threaded codes from "skyeye_net_tap.c" and "skyeye_lcd_win32.c". * Added net_wait_packet() function to "skyeye-v1/device/skyeye_net.h". * Added GTK+ detection for "skyeye-v1/Makefile". * Now the net simulation worked on MinGW/CygWin by OpenVPN's TAP-Win32 driver, and you must set the IP address of the virtual adapter to be 10.0.0.1 and net mask to be 255.255.255.0 manually. * Fixed Makefile for Win32 platform * Added byte order macro to "skyeye-v1/arch/ppc/common/byteorder.h" for Win32 * Changed files: skyeye-v1/Makefile skyeye-v1/arch/arm/mach/skyeye_mach_ps7500.c skyeye-v1/arch/coldfire/common/Makefile skyeye-v1/arch/coldfire/i_5206/Makefile skyeye-v1/arch/coldfire/tracer/Makefile skyeye-v1/arch/ppc/mach/Makefile skyeye-v1/arch/ppc/common/Makefile skyeye-v1/arch/ppc/common/byteorder.h skyeye-v1/device/lcd/dev_lcd_ep7312.c skyeye-v1/device/lcd/dev_lcd_pxa.c skyeye-v1/device/lcd/dev_lcd_s3c2410.c skyeye-v1/device/lcd/skyeye_lcd.c skyeye-v1/device/lcd/skyeye_lcd.h skyeye-v1/device/lcd/skyeye_lcd_gtk.c skyeye-v1/device/lcd/skyeye_lcd_win32.c skyeye-v1/device/net/dev_net_cs8900a.c skyeye-v1/device/net/dev_net_rtl8019.c skyeye-v1/device/net/dev_net_s3c4510b.c skyeye-v1/device/net/skyeye_net.c skyeye-v1/device/net/skyeye_net.h skyeye-v1/device/net/skyeye_net_tap.c skyeye-v1/device/net/skyeye_net_tuntap.c skyeye-v1/device/net/skyeye_net_vnet.c skyeye-v1/utils/config/skyeye_options.c skyeye-v1/utils/debugger/gdbserver.c * Removed files: skyeye-v1/Makefile.MinGW32 skyeye-v1/Makefile.win skyeye-v1/Makefile_gcc-3.3_with_DBCT_X86_32 skyeye-v1/utils/stub/mingw_help.c skyeye-v1/utils/stub/mingw_help.h skyeye-v1/utils/stub/skyeye_stub_win32.c 2007-01-13 ksh * add gpio control register R/W to avoid some error message * Changed files: arch/arm/mach/skyeye_mach_s3c2410x.c arch/arm/mach/s3c2410x.h 2006-12-31 ksh * Improve blackfin debug a lot.Now we can set breakpoint,step run, view disassemle and register info when we debug blackfin program by remote debug. * Changed files: utils/main/skyeye.c utils/debugger/bfin_regdefs.c arch/bfin/bfin_arch_interface.c 2006-12-29 ksh * add "-l option" to load elf image to another address not its entry * Changed file: utils/main/skyeye.c 2006-12-26 ksh * add mips debug code for gdbserver, but it seems not work now 2006-12-22 ksh * import initial ppc simulation code. * add ppc debug function.Now you can step run ppc code and see some values * of register.Breakpoint is not implemented. 2006-12-17 ksh * improve the simulation of blackfin DMA * add some new instruction in blackfin simulation 2006-12-17 ksh * rewrite the framework of gdbserver * two bugs is fixed arch/arm/common/armvirt.c utils/debugger/* 2006-12-11 benno * Changed arch/arm/common/armdefs.h arch/arm/common/armemu.c arch/arm/common/thumbemu.c arch/arm/common/mmu/xscale_copro.c * Updated support for Thumb mode. Patch supplied by carl@ok-labs.com 2006-12-11 benno * Change Makefile Enable -O2 level optimisation. Enable >2GB tracefiles on Linux by adding "-D_FILE_OFFSET_BITS=64" 2006-12-11 benno * Changed arch/arm/common/arm_arch_interface.c, utils/main/skyeye.c This patch correctly fixes cleaning up the terminal setting on exit, including exit due to Ctrl-C by the user. There is still some fixup required as the console is put into raw mode in the main code and also within the simulator itself. (patch provided by malcolmp@ok-labs.com) 2006-12-11 benno * Changed skyeye2gdb.c to enable compiling on MacOSX * Changed Makefile to create binary directory when needed. * Changed utils/main/skyeye.c to fix bug in non-BFD loaded. (patch provided by malcolmp@ok-labs.com) 2006-11-29 ksh * fix a bug in dma simulation in blackfin 533 architecture * Changed file: arch/bfin/mach/bf533_io.c 2006-11-29 ksh * workaround for 2410 code in linux-2.6.x.Now linux-2.6 can run on 2410 simulation * Changed file: arch/arm/mach/skyeye_mach_s3c2410x.c 2006-10-27 ksh * commit the patch provided by alain * Changed file: arch/bfin/common/iomem.c arch/bfin/common/mem_map.h arch/bfin/mach/bf533_io.c 2006-10-05: ksh * a bug caused by null pointer in dev_lcd_ep7312.c is fixed! * Changed file: device/lcd/dev_lcd_ep7312.c 2006-09-19: ksh * add pf peripheral support in blackfin simulation * Changed file: arch/bfin/mach/bf533_io.c 2006-09-19: ksh * add "@" in the commmand of make to prevent some useless info in the screen * Changed file: Makefile 2006-09-19: ksh * commit the patch contributed by Anthony Lee. * Changed files: Makefile Makefile.MinGW32 Makefile.win README.win32.cn arch/arm/common/arm_arch_interface.c arch/arm/common/armcopro.c arch/arm/common/armdefs.h arch/arm/dbct/arm2x86.c arch/arm/dbct/arm2x86.h arch/arm/dbct/arm2x86_coproc.c arch/arm/dbct/arm2x86_dp.c arch/arm/dbct/arm2x86_mem.c arch/arm/dbct/arm2x86_movl.c arch/arm/dbct/arm2x86_mul.c arch/arm/dbct/arm2x86_other.c arch/arm/dbct/arm2x86_psr.c arch/arm/dbct/arm2x86_shift.c arch/arm/dbct/arm2x86_test.c arch/arm/dbct/tb.c arch/arm/mach/skyeye_mach_at91.c arch/arm/mach/skyeye_mach_at91rm92.c arch/arm/mach/skyeye_mach_cs89712.c arch/arm/mach/skyeye_mach_ep7312.c arch/arm/mach/skyeye_mach_ep9312.c arch/arm/mach/skyeye_mach_ep9315.c arch/arm/mach/skyeye_mach_lh79520.c arch/arm/mach/skyeye_mach_lpc.c arch/arm/mach/skyeye_mach_lpc2210.c arch/arm/mach/skyeye_mach_ns9750.c arch/arm/mach/skyeye_mach_ps7500.c arch/arm/mach/skyeye_mach_pxa250.c arch/arm/mach/skyeye_mach_pxa270.c arch/arm/mach/skyeye_mach_s3c2410x.c arch/arm/mach/skyeye_mach_s3c2440.c arch/arm/mach/skyeye_mach_s3c44b0.c arch/arm/mach/skyeye_mach_s3c4510b.c arch/arm/mach/skyeye_mach_sa.c arch/arm/mach/skyeye_mach_sharp.c arch/bfin/common/bfin_arch_interface.c arch/bfin/mach/bf533_io.c arch/coldfire/common/Makefile arch/coldfire/i_5206/Makefile arch/coldfire/tracer/Makefile arch/mips/common/decoder.c arch/mips/common/mipsmem.c arch/mips/common/types.h arch/mips/mach/nedved.c device/lcd/skyeye_lcd.c device/lcd/skyeye_lcd.h device/lcd/skyeye_lcd_gtk.c device/lcd/skyeye_lcd_win32.c device/net/dev_net_s3c4510b.c utils/config/skyeye_config.h utils/config/skyeye_options.c utils/config/skyeye_options.h utils/debugger/skyeye2gdb.c utils/main/skyeye.c utils/stub/mingw_help.c utils/stub/skyeye_stub_win32.c utils/stub/skyeye_win32_stdio.c 2006-09-08: ksh * add mips simulation developed by shiyang(shy828301@126.com). A great work! * added files: arch/mips/* * Changed files: utils/config/skyeye_arch.c Makefile 2006-09-04: ksh * add two dimensional dma support * Changed files: arch/bfin/mach/bf533_io.c arch/bfin/common/dma.h 2006-08-27: ksh * commit a patch to support win32 API written by Li DongSheng.Thanks! * Added files: Makefile.MinGW32 utils/stub/skyeye_win32_stdio.c device/lcd/skyeye_lcd_win32.c * Changed files: arch/arm/mach/skyeye_mach_at91.c arch/arm/mach/skyeye_mach_at91rm92.c arch/arm/mach/skyeye_mach_cs89712.c arch/arm/mach/skyeye_mach_ep7312.c arch/arm/mach/skyeye_mach_ep9312.c arch/arm/mach/skyeye_mach_ep9315.c arch/arm/mach/skyeye_mach_lh79520.c arch/arm/mach/skyeye_mach_lpc.c arch/arm/mach/skyeye_mach_lpc2210.c arch/arm/mach/skyeye_mach_ns9750.c arch/arm/mach/skyeye_mach_ps7500.c arch/arm/mach/skyeye_mach_pxa250.c arch/arm/mach/skyeye_mach_pxa270.c arch/arm/mach/skyeye_mach_s3c2410x.c arch/arm/mach/skyeye_mach_s3c2440.c arch/arm/mach/skyeye_mach_s3c44b0.c arch/arm/mach/skyeye_mach_s3c4510b.c arch/arm/mach/skyeye_mach_sa.c arch/arm/mach/skyeye_mach_sharp.c 2006-08-13:2 chy * Fix yet another bug in Flash simulation. now flash WRITE simulation seems OK! * Changed files: device/flash/dev_flash_intel.c 2006-08-13 chy * Fix another bug in Flash simulation. now flash WRITE simulation seems OK! * Changed files: device/flash/dev_flash_intel.c 2006-08-12 chy * Fix a big bug in Flash simulation: didn't care the global_mpb=bank_ptr(address) when read/write things * BUT flash WRITE simulation still have BUGS!!!! * Changed files: device/flash/dev_flash_intel.c 2006-08-09 benno * Fix Xscale MMU operations to return ARMul_DONE, not the value. (patch provided by Matthew.Warton@nicta.com.au) * Changed files: arch/arm/common/mmu/xscale_copro.c 2006-08-09 benno * Fix pxa250 serial device interrupt enable acorrding to Xscale spec. (patch provided by Carl.vanSchaik@nicta.com.au) * Changed files: arch/arm/mach/skyeye_mach_pxa250.c 2006-08-08 ksh * fixed a bug by tomei.ningen@yahoo.com * Changed files: utils/debugger/arch_reg.c 2006-08-05 chy * gcc-2.95/3.3/3.4/4.0/4.1 can compile skyeye * add amd64 support, update autotest, * in 64bit system, long=64 bit int=32bit, long long =64 bit, long int=64bit; * in 32bit system, long = 32 bit, int=32bit, long long =64 bit, long int=32bit * so I do: long ---> int * Changed files: *.[ch] which has long --->int , long int ---> int Makefile utils/tools/auto_test/daily_test.sh * added files: Makefile_gcc-3.3_with_DBCT_X86_32 2006-07-04 ksh * add a patch provided by Phil Wilshire that add trace buffer simulation of blackfin * Changed files: arch/bfin/mach/bf533_io.c arch/bfin/mach/bf533_io.c 2006-06-17 ksh * add a patch provided by Phil Wilshire that add scrachpad memory simulation of blackfin * Changed files: arch/bfin/common/bfin-sim.h arch/bfin/common/mem_map.h arch/bfin/common/bfin_arch_interface.c arch/bfin/common/iomem.c 2006-06-11 ksh * add ps7500 simulation patch provided by acassis@gmail.com * added files: arch/arm/mach/skyeye_mach_ps7500.c arch/arm/mach/ps7500.h * Changed files: arch/arm/common/arm_arch_interface.c Makefile 2006-05-27 ksh * add a menuconfig-like system to select various config options and generate skyeye.conf by the selected result. * added files: utils/conf/makefile utils/conf/configs/Configure.help utils/conf/configs/Makefile.am utils/conf/configs/Makefile.in utils/conf/configs/config.in utils/conf/configs/defconfig utils/conf/configs/feature.in utils/conf/configs/mkdefconfig utils/conf/scripts/Makefile.am utils/conf/scripts/Makefile.in utils/conf/scripts/Menuconfig utils/conf/scripts/mkconfig utils/conf/scripts/lxdialog/Makefile.am utils/conf/scripts/lxdialog/Makefile.in utils/conf/scripts/lxdialog/checklist.c utils/conf/scripts/lxdialog/colors.h utils/conf/scripts/lxdialog/dialog.h utils/conf/scripts/lxdialog/inputbox.c utils/conf/scripts/lxdialog/lxdialog.c utils/conf/scripts/lxdialog/makefile.lx utils/conf/scripts/lxdialog/menubox.c utils/conf/scripts/lxdialog/msgbox.c utils/conf/scripts/lxdialog/textbox.c utils/conf/scripts/lxdialog/util.c utils/conf/scripts/lxdialog/yesno.c 2006-05-23 chy * fix a bug only exist in MingW (for OS--elastos 2 ). * in order to support elastos 2, I will change skyeye-mach-pxa*.c ... in the future. Makefile.win also need change. * Changed files: arch/arm/common/armmem.[ch] 2006-04-24 chy (REL_1_2_RC7_3) * for more stable and useable, change exit FUN to skyeye_exit FUN and change display_all_support FUN * In the future, if you want to use exit() FUN in skyeye, please use skyeye_exit() instead. * Changed files: arch/arm/common/arm_arch_interface.c arch/arm/common/armengr.c arch/arm/common/arminit.c arch/arm/common/armmem.c arch/arm/common/armmmu.c arch/arm/common/armsupp.c arch/arm/common/armsym.c arch/arm/common/mmu/arm7100_mmu.c arch/arm/common/mmu/arm920t_mmu.c arch/arm/common/mmu/arm926ejs_mmu.c arch/arm/common/mmu/maverick.c arch/arm/common/mmu/sa_mmu.c arch/arm/common/mmu/xscale_copro.c arch/arm/dbct/tb.c arch/arm/mach/skyeye_mach_cs89712.c arch/arm/mach/skyeye_mach_ep7312.c arch/arm/mach/skyeye_mach_lh79520.c arch/arm/mach/skyeye_mach_s3c44b0.c arch/arm/mach/skyeye_mach_sa.c arch/arm/mach/skyeye_mach_sharp.c arch/bfin/common/bfin-dis.c arch/bfin/common/bfin_arch_interface.c arch/bfin/mach/bf533_io.c arch/coldfire/common/i.c arch/coldfire/common/memory.c device/net/skyeye_net_vnet.c utils/config/skyeye_config.c utils/config/skyeye_options.c utils/debugger/skyeye2gdb.c utils/main/skyeye.c utils/main/skyeye.h 2006-04-15 chy (REL_1_2_RC7_2) * fix remote debug for READ and WRITE byte * Changed files: utils/main/skyeye.c utils/debugger/skyeye2gdb.c utils/debugger/arch_reg.c utils/config/skyeye_types.h utils/config/skyeye_config.h arch/coldfire/common/cf_arch_interface.c arch/bfin/common/bfin_arch_interface.c arch/arm/common/armvirt.c arch/arm/common/arm_arch_interface.c Makefile 2006-04-12 chy (REL_1_2_RC7_1) * fix remote_interrupt test bug: put this test from ARMul_DoProg::arminit.c to ARMul_EMulate32::armemu.c, and test one time between 2000 instrs. should set 2000 in skyeye.conf. I will do it in the future * Changed files: arch/arm/common/armemu.c arch/arm/common/arminit.c 2006-04-12 chy (REL_1_2_RC7) * add ICE breakpoint debug function for SkyEye interpretting execution. * can support other 32bit cpu, now tested on ARM cpus. * changed files: Makefile arch/arm/common/armdefs.h arch/arm/common/armemu.c utils/debugger/arch_reg.c utils/debugger/skyeye2gdb.c utils/debugger/skyeye2gdb.h * NOTICE! benno changed skyeye_mach_pxa250.c, we also should change skyeye_mach_pxa270.c for the same bug 2006-04-12 chy * fix bug for debuging arm with mmu (REL_1_2_RC6_3) * Changed files: utils/debugger/arch_reg.c 2006-04-04 chy * now, ecos for s3c2410 can run on skyeye(mmu disable). * for eCos on s3c2410. SRCPND will change the INTPND, INTOFFSET, * so when write SRCPND, the interrupt should be updated * (Thank Zhao Tan!) * Changed files: arch/arm/mach/skyeye_mach_s3c2410x.c 2006-03-22 benno * Fix timer interrupt acknowledgement bug on pxa25x target. * Removed dead code in skyeye_mach_pxa250.c * changed files: arch/arm/mach/skyeye_mach_pxa250.c 2006-03-20 ksh * add some friendly exit code. * modified files: utils/config/skyeye_config.c utils/config/skyeye_config.h utils/main/skyeye.c 2006-03-18 ksh * add a TODO file to indicate our development plan. I list some features, feel free to add or modify. * added files: TODO 2006-02-26 chy * update arch/coldfire/common/Makefile, now when you make CC=gcc-x.x, all src are compiled by gcc-x.x * changed files: arch/coldfire/common/Makefile 2006-02-22 chy * fix a bug about remote_debug * add strongarm,blackfin testsuit in auto_test * changed files: arch/arm/common/arminit.c utils/tools/auto_test/auto_test 2006-02-18 ksh * enable uClinux kernel for blackfin platform. * correct the read/write of memory of blackfin * reverse the previous bfd load. change lma load to vma load in utils/main/skyeye.c for run blackfin.This issue needs to be dig into...... * changed files: utils/main/skyeye.c arch/blackfin/commom/iomem.c arch/blackfin/mach/bf533_io.c 2006-02-16 chy * change in 2006-02-15 is not correct. * according p35 in ARMARM book, we should consider SYSTEMMODE as privileged mode. Add SYSTEM32MODE and fix MSR instr (include translate and DBCT) simulation * update skyeye.c to allow binary image kernel can run * update auto_test tools, add cs89712 auto test * changed files utils/main/skyeye.c utils/tools/auto_test/auto_test arch/arm/common/{armemu.c, armcopro.c, armdefs.h, armsupp.c,mmu/tlb.c} arch/arm/dbct/arm2x86_psr.c NOTICE: compared with skyeye 2006-02-14, just changed armemu.c:: case TRAP_SET_CPSR (about 4120 line) CHANGE "if (state->Bank > 0) {" TO "if (state->Mode != USER26MODE && state->Mode !=USER32MODE){" 2006-02-15 chy * change in 2006-02-14 is not correct. * according p165 in ARMARM book, we should consider SYSTEMMODE. Add SYSTEM32MODE and fix MSR instr (include translate and DBCT) simulation * changed files arch/arm/common/{armemu.c, armcopro.c, armdefs.h, armsupp.c, mmu/tlb.c} arch/arm/dbct/arm2x86_psr.c 2006-02-14 chy * fix a DBCT bug. when cpu is in user or system mode, can exec change cpsr instr * update auto_test tools: add pxa27x auto test * changed files: arch/arm/common/armemu.c utils/tools/auto_test/auto_test 2006-02-13 chy * update auto-test tools * changed files: utils/tools/auto_test/{README, daily_test.sh, auto_test} 2006-02-12 chy * fix DBCT bug for CLZ instruction translation in arm2x86_dp.c * chage logical NOT to bit NOT in SUB instrs translation in arm2x86_dp.c * change a little in Makefile * change auto text tools * modifed files: arch/arm/dbct/arm2x86_dp.c Makefile utils/tools/auto_test/{daily_test.sh, auto_test} *added file utils/tools/auto_test/exec_skyeye_dbct.sh 2006-1-27 dwon * remove "state->Exception" variable (from ARMul_State), which is unnecessary and could introduce bugs * modified files: arch/arm/common/armcopro.c arch/arm/common/armdefs.h arch/arm/common/armemu.c arch/arm/common/arminit.c arch/arm/common/armsupp.c arch/arm/dbct/arm2x86.h arch/arm/mach/skyeye_mach_at91.c arch/arm/mach/skyeye_mach_cs89712.c arch/arm/mach/skyeye_mach_ep7312.c arch/arm/mach/skyeye_mach_lpc.c arch/arm/mach/skyeye_mach_lpc2210.c 2006-1-26 dwon * rewrite lh79520-irqs.h so that it can be distributed under GPLv2 "or any later version" * added files: arch/arm/mach/lh79520_irq.h * deleted files: arch/arm/mach/lh79520-irqs.h * modified files: arch/arm/mach/skyeye_mach_lh79520.c Makefile 2006-1-25 dwon * add support for LH79520 Chip ID register (in RCPC) * modified files: arch/arm/mach/lh79520.h arch/arm/mach/skyeye_mach_lh79520.c 2006-1-21 ksh * add a more friendly hint when missing the image option * motified files: utils/main/skyeye.c 2006-1-9 chy * add a patch from Dwayne C. Litzenberger <dlitz5321@dlitz.net> to * support small/tiny pagetable * modified files: arch/arm/common/mmu/tlb.c arch/arm/common/mmu/tlb.h 2006-1-8 ksh * add INTMR3 and INTMR2 defination in skyeye_mach_ep7312.c,so rtems can run without workaround code * modified files: arch/arm/mach/skyeye_mach_ep7312.c arch/arm/mach/clps7110.h 2006-1-5 ksh * add a patch from Dwayne C. Litzenberger <dlitz5321@dlitz.net> to fix rom initialization * modified files: utils/main/skyeye.c 2006-1-5 ksh * fix a bug that make xscale testcase can not run normally. * modified files: arch/arm/common/arm_arch_interface.c 2005-12-29 ksh * get rid of some debugging message printed by remote debug .If you need these message , you can get it by define macro in skyeye2gdb.c * modified files: utils/debugger/skyeye2gdb.c arch/arm/common/armos.c 2005-12-28 ksh * add linxz's patch that we can stop skyeye by press Ctrl+C in the gdb side, but now only arm simulation is supported. * modified files: utils/debugger/skyeye2gdb.c arch/arm/common/arminit.c 2005-12-28 ksh * fix a bug that can not stop on arm breakpoint instruction * modified files: utils/debugger/skyeye2gdb.c utils/debugger/arch_reg.c arch/arm/common/armos.c 2005-12-25 ksh * add a simple script to support daily build and test skyeye source in the cvs * added files: utils/tools/auto_test/daily_test.sh utils.tools/auto_test/README.daily * add an option in skyeye.c for list all the supported arch and cpu information * changed files: utils/main/skyeye.c 2005-12-20 koodailar * add support for mingw on windows, including tap-win32 and gtk * changed files: arm/mach/*.c arm/common/armcoproc.c arm/common/armdefs.h arm/common/arminit.c arm/common/armmem.c arm/common/arm_arch_interface.c arm/common/mmu/arm7100_mmu.c arm/common/mmu/arm920t_mmu.c arm/common/mmu/arm926ejs_mmu.c arm/common/mmu/cache.c arm/common/mmu/sa_mmu.c arm/common/mmu/tlb.c arm/common/mmu/wb.c arm/common/mmu/xscale_copro.c arm/dbct/arm2x86.c arm/dbct/arm2x86.h arm/dbct/arm2x86_coproc.c arm/dbct/arm2x86_dp.c arm/dbct/arm2x86_mem.c arm/dbct/tb.c arm/dbct/arm2x86_movl.c arm/dbct/arm2x86_mul.c arm/dbct/arm2x86_other.c arm/dbct/arm2x86_psr.c arm/dbct/arm2x86_shift.c arm/dbct/arm2x86_test.c bfin/mach/bf533_io.c device/flash/armflash.c device/flash/skyeye_flash.c device/flash/skyeye_flash.h device/lcd/dev_lcd_ep7312.c device/lcd/dev_lcd_pxa.c device/lcd/dev_lcd_s3c2410.c device/lcd/skyeye_lcd.c device/net/dev_net_cs8900a.c device/net/dev_net_rtl8019.c device/net/dev_net_s3c4510b.c device/net/skyeye_net.c device/net/skyeye_net_tuntap.c device/net/skyeye_net_vnet.c utils/config/skyeye_arch.c utils/config/skyeye_config.h utils/config/skyeye_options.h utils/debugger/arch_reg.c utils/debugger/skyeye2gdb.c * added files: utils/tool/dev-cpp_support/skyeye-win.dev utils/tool/dev-cpp_support/skyeye-win.layout device/net/skyeye_net_tap.c utils/main/ide.py utils/main/setup.py utils/stub/mingw_help.c utils/stub/mingw_help.h * comment 1. Build SDL the default SDL implementation disabled stdin and stdout, i enabled them You can do the same thing by modifying \SDL-1.2.9\src\main\macos\SDL_main.c and uncomment *fclose(stdout)* in static void cleanup_output(void) then ./configure --prefix=/mingw/ make make install 2. Build skyeye quite normal. But devcpp(mingw) does not know `pkg-config gtk+-2.0 --cflags --libs`, so I insert the result by hand. You have to make some change to the default path. On my machine it is "-LD:/Dev-cpp....". I think you understand what i mean 3. Build python actually *.py script is satisfiable. But someone says that .exe is more suitable for windows, because not everyone have python installed. So i make an exe file. You can do it too, by python setup.py py2exe In order to make python look beautiful, i use Tix package. However the default implementation of py2exe ignored the Tix tarball. So i modified a setup.py to direct its action. 4. For gtk after install GTK-Development-Environment-2.2.4-3.exe, modify include/glib-2.0/glib/gwin32.h, and comment line 72 and 73 5. For tap-win32 1. install tap-win32 in openvpn 2. original net adapter->properties->advanced choose "allow other network users to ..." 3. by default, the new tap adapter will have the address 191.168.0.1 do not change it. 2005-12-4 ksh * add some reg definition for blackfin and coldfire, So we can remote debug on these platform * changed files: utils/debugger/skyeye2gdb.c utils/debugger/skyeye2gdb.h * added files: utils/debugger/arch_reg.c utils/debugger/arm_regdefs.h utils/debugger/cf_regdefs.h 2005-12-3 ksh * modify skyeye2gdb.c to support remote debug on mutilple architectures * changed files: arch/bfin/common/bfin_arch_interface.c arch/bfin/common/iomem.h utils/config/skyeye_arch.c utils/config/skyeye_config.h utils/config/skyeye_types.h utils/debugger/skyeye2gdb.c utils/main/skyeye.c 2005-12-3 ksh * Added coldfire simulation,now coldfire can not run linux,just execute some instructions. * added file: arch/coldfire/ * changed files: Makefile utils/config/skyeye_config.h utils/config/skyeye_config.c utils/config/skyeye_options.h utils/config/skyeye_options.c utils/main/skyeye.c 2005-11-29 benno * Added option to allow compilation of a static binary * Changed files: README Makefile 2005-11-29 benno * Wrote ELF loader so that libbfd is not required. Enabled by NO_BFD compile option. * Changed files: README Makefile utils/main/skyeye.c * Added files: utils/main/elf32.h 2005-11-16 chenyu fix some bug when compiling on cygwin * changed file: arch/arm/mach/skyeye_mach_lpc2210.c Makefile 2005-11-15 ksh * commit linxz's code for lpc2210 simulation, lots of thanks to him. * Added file: arch/arm/mach/skyeye_mach_lpc2210.c * Changed files: arch/arm/common/arm_arch_architecture.c Makefile 2005-11-15 ksh * fix the bug in bfin simualation that will error under gcc4 compilation * Changed file: arch/bfin/common/iomem.c 2005-10-24 teawater * Add DBCT_TEST_SPEED function. (To use this function, open "#define DBCT_TEST_SPEED" in arch/arm/common/armdefs.h & recompile skyeye. Set "dbct_test_speed_sec:20" in config file to set test sec.) * Correct a little bug in dbct. * Add cache all tb address in dbct. * Change TB_LEN to 1024. * Add tb last use addr function. * Add DBCT local tb branch directly jump function. * Add compile switch for DBCT GDB RSP function. (To use this function, open "#define DBCT_GDBRSP" in arch/arm/common/armdefs.h & recompile skyeye.) * remove "tb_translate_find". * Changed files: arch/arm/common/armdefs.h arch/arm/common/arminit.c arch/arm/common/armio.c arch/arm/dbct/arm2x86.c arch/arm/dbct/arm2x86.h arch/arm/dbct/arm2x86_dp.h arch/arm/dbct/arm2x86_movl.h arch/arm/dbct/arm2x86_other.c arch/arm/dbct/arm2x86_other.h arch/arm/dbct/arm2x86_shift.c arch/arm/dbct/arm2x86_shift.h arch/arm/dbct/arm2x86_test.h arch/arm/dbct/tb.c arch/arm/dbct/tb.h arch/arm/mach/skyeye_mach_at91.c arch/arm/mach/skyeye_mach_at91rm92.c arch/arm/mach/skyeye_mach_cs89712.c arch/arm/mach/skyeye_mach_ep7312.c arch/arm/mach/skyeye_mach_ep9312.c arch/arm/mach/skyeye_mach_ep9315.c arch/arm/mach/skyeye_mach_lh79520.c arch/arm/mach/skyeye_mach_lpc.c arch/arm/mach/skyeye_mach_ns9750.c arch/arm/mach/skyeye_mach_s3c2410x.c arch/arm/mach/skyeye_mach_s3c2440.c arch/arm/mach/skyeye_mach_s3c44b0.c arch/arm/mach/skyeye_mach_s3c4510b.c utils/config/skyeye_config.h utils/config/skyeye_options.c 2005-10-10 walimis * Use "indent -i8 -bli8 -bls -br -ts8" to reformat all codes. * Use dos2unix to convert some dos format * Changed files: all files 2005-10-08 walimis * Combine ksh's patches to cvs * Now skyeye can support blackfin architecture. * Changed files: utils/config/skyeye_options.c 2005-10-1 ksh * add BlackFin architecture, You can download its datasheet from www.Analog.com and get its * toolchain and uclinux source code from blackfin.uclinux.org * add support for mutil architecture. Get rid of arm related code from utils. * Added directory and files: arch/bfin/ arch/arm/common/arm_arch_interface.c utils/config/skyeye_defs.h utils/config/skyeye_types.h utils/config/skyeye_arch.c utils/config/skyeye_arch.h * changed files: Makefile utils/config/skyeye_config.h utils/config/skyeye_config.c utils/config/skyeye_options.h utils/config/skyeye_options.c utils/main/skyeye.c arch/arm/common/armdefs.h arch/arm/common/arminit.c arch/arm/common/armmem.c arch/arm/common/armmmu.c arch/arm/common/mmu/arm7100_mmu.c arch/arm/common/mmu/arm920t_mmu.c arch/arm/common/mmu/arm926ejs_mmu.c arch/arm/common/mmu/sa_mmu.c arch/arm/common/mmu/xscale_copro.c arch/arm/dbct/tb.c device/lcd/skyeye_lcd_gtk.c 2005-09-28 walimis * Rewrite pxa simulation to support new framework. * Changed files: utils/config/skyeye_options.c arch/arm/common/armio.c arch/arm/common/armio.c arch/arm/mach/skyeye_mach_pxa250.c arch/arm/mach/skyeye_mach_pxa270.c 2005-09-26-2 teawater * fix bug , 64bit multply: arch/arm/common/tb.c arch/arm/dbct/arm2x86_other.h 2005-09-26 teawater * Add some instructions in DBCT to support armv5(include XScale). Changed files: arch/arm/common/armemu.c arch/arm/dbct/arm2x86.c arch/arm/dbct/arm2x86.h arch/arm/dbct/arm2x86_dp.c arch/arm/dbct/arm2x86_dp.h arch/arm/dbct/arm2x86_movl.c arch/arm/dbct/arm2x86_movl.h arch/arm/dbct/arm2x86_other.c arch/arm/dbct/arm2x86_other.h arch/arm/dbct/arm2x86_test.c arch/arm/dbct/arm2x86_test.h arch/arm/dbct/arm2x86_coproc.c arch/arm/dbct/arm2x86_coproc.h arch/arm/dbct/arm2x86_mem.c arch/arm/dbct/arm2x86_mem.h arch/arm/dbct/arm2x86_mul.c arch/arm/dbct/arm2x86_mul.h arch/arm/dbct/arm2x86_psr.c arch/arm/dbct/arm2x86_psr.h arch/arm/dbct/arm2x86_shift.c arch/arm/dbct/arm2x86_shift.h arch/arm/dbct/tb.c arch/arm/dbct/tb.h arch/arm/dbct/arm2x86_self.h arch/arm/dbct/list.h 2005-09-22 walimis * Rewrite flash simulation. Changed files: Makefile arch/arm/common/armmem.c arch/arm/common/armsupp.c arch/arm/mach/skyeye_mach_pxa250.c arch/arm/mach/skyeye_mach_pxa270.c device/skyeye_device.c device/flash/armflash.c device/flash/skyeye_flash.c device/flash/skyeye_flash.h utils/config/skyeye_config.h utils/config/skyeye_options.c utils/config/skyeye_options.h *Added files: device/flash/dev_flash_intel.c device/flash/dev_flash_intel.h 2005-9-20 benno * Prived a NO_NET option, to disable compiling network device files * Changes files: Makefile README device/skyeye_device.c 2005-9-20 benno * Provided a NO_DBCT option, to disable compiling DBCT files. * Changed file: Makefile README arch/arm/common/armemu.c arch/arm/common/arminit.c arch/arm/common/armmem.c arch/arm/common/mmu/wb.c utils/config/skyeye_options.c 2005-9-19 chy * pxa27x CP6 simualtion over. now linux needn't be changed. * Changed file: arch/arm/common/armcopro.c arch/arm/common/armdefs.h arch/arm/common/arminit.c arch/arm/common/mmu/xscale_copro.c arch/arm/mach/pxa.h arch/arm/mach/skyeye_mach_pxa250.c arch/arm/mach/skyeye_mach_pxa270.c 2005-09-15 walimis * Remove some include files. Changed files: device/net/dev_net_cs8900a.c device/net/dev_net_rtl8019.c device/net/dev_net_s3c4510b.c * Modify for freebsd platform. Changed files: Makefile utils/main/skyeye.c device/net/skyeye_net_tuntap.c device/net/skyeye_net_vnet.c README 2005-09-14-2 chy * linux for pxa27x can run on skyeye, I changed linux code :( * mainstone LCD can show now, but size isn't correct. :( * * changed file: arch/arm/mach/skyeye_mach_pxa270.c device/lcd/dev_lcd_pxa.c 2005-09-14 walimis * Make skyeye can be compiled without lcd support. * If you want to compile skyeye without lcd, just type: * make NO_LCD=1 all * Changed files: Makefile device/skyeye_device.c arch/arm/mach/skyeye_mach_ep7312.c arch/arm/mach/skyeye_mach_at91.c arch/arm/mach/skyeye_mach_pxa250.c arch/arm/mach/skyeye_mach_pxa270.c 2005-09-14 chy * SkyEye-V1.0 released! * cvs import to gro.clinux.org, using skyeye-v1 module * add PXA27x initial simulation. PXA TouchScreen still has problem. * added file arch/arm/mach/skyeye_mach_pxa270.c * changed file: arch/arm/mach/skyeye_mach_pxa.c ---> skyeye_mach_pxa250.c utils/config/skyeye_options.c utils/config/skyeye_config.h utils/main/skyeye.c (change the command option ("-f" to "-c")for skyeye configure) arch/arm/common/armmmu.c arch/arm/dbct/tb.c (for gcc-3.3.x compiling) Makefile * NOTICE: skyeye.conf for PXA has changed if is PXA25x based Lubbock board cpu: pxa25x mach: pxa_lubbock ...... if is PXA27x based MainStone board cpu: pxa27x mach: pxa_mainstone ...... 2005-09-12 chy * SkyEye-v1.0-RC2 released! * now SkyEye is a standalone software, which can use RSP protocol to talk with GDB. * skyeye is changed a lot(especially the directory), But we didn't change the internal of skyeye. * little changed files from skyeye-2005-08-03, check chy-2005-09-12 comment: utils/debugger/skyeye2gdb.c arch/arm/common/armos.c arch/arm/common/armvirt.c arch/arm/dbct/tb.c (teawater found) 2005-08-15 walimis * Add a simple device framework to skyeye. It should be rewrited and impoved in 2.x. * Add net controller simulation: rtl8019, cs8900a, s3c4510b. * Add lcd controller simulation: ep7312, s3c2410, pxa. * Flash simulation should be added into this framework in the future. * Added files: device/skyeye_device.c device/skyeye_device.h device/lcd/dev_lcd_ep7312.c device/lcd/dev_lcd_ep7312.h device/lcd/dev_lcd_pxa.c device/lcd/dev_lcd_pxa.h device/lcd/dev_lcd_s3c2410.c device/lcd/dev_lcd_s3c2410.h device/net/dev_net_cs8900a.c device/net/dev_net_cs8900a.h device/net/dev_net_rtl8019.c device/net/dev_net_rtl8019.h device/net/dev_net_s3c4510b.c device/net/dev_net_s3c4510b.h 2005-07-26 Teawater * Add simple debug function to DBCT (Such as break, step, stepi, next, nexti). * Change DBCT that if current running TB is wrotten, it will return & translate again. * Change insn_bank_ptr to bank_ptr in tb_setdirty. * Add "sim reg file" command to help DBCT debug. * Add dynamic TBT & TBP function in DBCT to make it can be used in small memory PC. The default options of DBCT are static TBT & dynamic TBP (64M) & they can be set in config file. * Add for tb_setdirty fflash cache function. * Add bx instruction support. * Debug for cs89712. * Change align in tb_find & tb_setdirty to make speed up. * Change DBCT that translate stop if the code must return. * Rewrite tb_find & tb_setdirty to make code clear & speed up. * changed files: sim/arm/armdefs.h sim/arm/armemu.c sim/arm/skyeye_config.h sim/arm/skyeye_mach_cs89712.c sim/arm/skyeye_options.c sim/arm/wrapper.c sim/arm/dbct/arm2x86.c sim/arm/dbct/arm2x86.h sim/arm/dbct/arm2x86_other.c sim/arm/dbct/arm2x86_other.h sim/arm/dbct/arm2x86_shift.c sim/arm/dbct/arm2x86_test.c sim/arm/dbct/arm2x86_test.h sim/arm/dbct/tb.c sim/arm/dbct/tb.h sim/arm/mmu/wb.c 2005-07-06 Teawater * DBCT for all of the CPU with MMU. * change some write back code of DBCT. (according to arm_arm A2-18) * debug for CYGWIN function call of DBCT. * add auto set the console to default state function. * change gcc optimize flag of DBCT code that to make it can compile with the newest gcc. * changed files: sim/arm/dbct/arm2x86.h sim/arm/dbct/arm2x86_dp.c sim/arm/dbct/arm2x86_mem.c sim/arm/dbct/arm2x86_movl.c sim/arm/dbct/arm2x86_movl.h sim/arm/dbct/arm2x86_other.c sim/arm/dbct/arm2x86_other.h sim/arm/dbct/arm2x86_shift.c sim/arm/dbct/arm2x86_shift.h sim/arm/dbct/tb.h sim/arm/Makefile.in sim/arm/arm7100_mmu.c sim/arm/arm920t_mmu.c sim/arm/armdefs.h sim/arm/sa_mmu.c sim/arm/skyeye_mach_ep7312.c sim/arm/wrapper.c sim/arm/xscale_copro.c 2005-06-14 TeaWater * DBCT for CPU with MMU. now skyeye-0.9.6 * debug for init of sbc instruction * add sim command for debug (see it in the bottom of wrapper.c) * change some write back code of dbct (according to arm_arm A2-17) * changed file: sim/arm/dbct/arm2x86_*.[ch] sim/arm/dbct/tb.[ch] sim/arm/arm7100_mmu.c sim/arm/armdefs.h sim/arm/armemu.c sim/arm/arminit.c sim/arm/armmmu.[ch] sim/arm/wrapper.c 2005-05-11 Chy * make the skyeye-0.9.4 run on cygwin. now skyeye-0.9.5 released! * changed file: sim/arm/armdefs.h sim/arm/dbct/arm2x86.[ch] sim/arm/dbct/arm2x86_mem.c 2005-04-22 Yin Wen Chao * open teawater's code in bank_ptr, and add insn_bank_ptr for dbct * add a global variable to store the bank_ptr result in mem_*_*. The coresponding real_*_* just use the result directly, no need to call bank_ptr again * move tb_setdirty from mem_write_* to real_write_* * changed file: sim/arm/dbct/tb.c sim/arm/armmem.c 2005-04-12 walimis * add s3c2440 simulation * add files: add s3c2440 mach. sim/arm/skyeye_mach_s3c2440.c sim/arm/s3c2440.h * changed files: add s3c2440 mach. sim/arm/skyeye_options.c sim/arm/Makefile.in sim/arm/Makefile.in.gtk-1.2 sim/arm/Makefile.in.gtk-2.0 2005-04-07 Yin Wen Chao * fix little bug for dbct init * changed file: sim/arm/arminit.c 2005-04-01 teawater Yin Wenchao * version 0.9.2 * add dynamic binary code translation, thanks for teawater's great work . * fix a bug in flash simulation * add directory: sim/arm/dbct * add files: sim/arm/dbct/arm2x86.[ch] sim/arm/dbct/arm2x86_dp.[ch] sim/arm/dbct/arm2x86_mem.[ch] sim/arm/dbct/arm2x86_movl.[ch] sim/arm/dbct/arm2x86_mul.[ch] sim/arm/dbct/arm2x86_other.[ch] sim/arm/dbct/arm2x86_psr.[ch] sim/arm/dbct/arm2x86_shift.[ch] sim/arm/dbct/arm2x86_test.[ch] sim/arm/dbct/tb.[ch] sim/arm/dbct/arm2x86_self.h sim/arm/dbct/list.h * changed files: sim/arm/armdefs.h sim/arm/armemu.c sim/arm/arminit.c sim/arm/armmem.[ch] sim/arm/skyeye_options.c sim/arm/wrapper.c sim/arm/Makefile.in sim/arm/skyeye_mach_lpc.c sim/arm/skyeye_config.h sim/arm/skyeye_flash.c 2005-03-30 YIN Wenchao Ye Wen(wenye@cs.ucsb.edu) * version 0.9.0 * add flash simulation, many thanks to Ye Wen . * add files: sim/arm/armflash.[ch] sim/arm/skyeye_flash.[ch] * changed files: sim/arm/skyeye_config.h sim/arm/skyeye_options.c sim/arm/armmem.c sim/arm/skyeye_mach_pxa.c sim/arm/Makefile.in 2005-02-25 zhangzhichao(zhang_zhichao@hotmail.com) watercloud(watercloud@xfocus.org) * base on version 0.8.7 * integrate insight with skyeye, many thanks to watercloud. * port skyeye to cygwin. 1) temporary disable network simulation on win32. 2) lcd simulation on win32 need gtk support.There are many way to run gtk on win32. we had test the following two methods. a)using Xserver(XWin) which delivered with cygwin b)using GTK binary release for cygwin on http://web.sfc.keio.ac.jp/~s01397ms/cygwin/index.html.en * fix some bugs in makefile, let skyeye can compile in separate path * Known bug: currently skyeye+insight on cygwin can not corrently deal with console input&output. Any comments about this issue,pls share with us.thanks. * added file: sim\arm\skyeye_stub_win32.c * changed files: gdb\Makefile.in sim\Makefile.in sim\common\Make-common.in sim\common\Makefile.in sim\arm\Makefile.in sim\arm\skyeye_mach_at91.c sim\arm\skyeye_mach_at91rm92.c sim\arm\skyeye_mach_cs89712.c sim\arm\skyeye_mach_ep7312.c sim\arm\skyeye_mach_ep9312.c sim\arm\skyeye_mach_lh79520.c sim\arm\skyeye_mach_lpc.c sim\arm\skyeye_mach_s3c2410x.c sim\arm\skyeye_mach_s3c44b0.c sim\arm\skyeye_mach_s3c4510b.c sim\arm\skyeye_net_tuntap.c sim\arm\skyeye_net_vnet.c sim\arm\skyeye-ne2k.c 2005-01-19 walimis shiyang * add s3c2410x simulation, many thanks to shiyang. * add files: add s3c2410x mach. now it can boot 2.4.18 kernel. sim/arm/skyeye_mach_s3c2410x.c sim/arm/s3c2410x.h * changed files: add s3c2410x mach. sim/arm/skyeye_options.c sim/arm/Makefile.in 2005-01-07 chenyu * version 0.8.6 * make gcc-2.95 can compile skyeye * add and commit teawater' codes for armmem.c * add -O2 compile option for Make * changed file sim/arm/arm7100_mmu.c sim/arm/arm920t_mmu.c sim/arm/armsym.c sim/arm/sa_mmu.c sim/arm/skyeye_mach_at91.c sim/arm/skyeye_mach_cs89712.c sim/arm/xscale_copro.c sim/arm/mmu/cache.c sim/arm/mmu/tlb.c sim/arm/mmu/wb.c sim/arm/armmem.c gdb/top.c ./Makefile.in sim/arm/Makefile.in ./README 2004-12-23 walimis <wlm@student.dlut.edu.cn> * skyeye_mach_s3c4510b.c: modify mach_init 2004-12-5 chenyu * change skyeye_options.c for eclipse,only for test 2004-12-2 chenyu * make the gcc-3.4 can compile skyeye * changed file: sim/arm/skyeye_mach_at91rm92.c sim/arm/skyeye_mach_cs89712.c sim/arm/skyeye_mach_lh79520.c sim/arm/skyeye_mach_lpc.c gdb/arm-tdep.c 2004-11-30 YinWenChao * update LCD simulation on ep7312(add support to depth 12 ) * add LCD simulation on pxa (successfully ported minigui ) * add LCD simulation on at91 (framebuffer works,but minigui has error) * changed files: skyeye_lcd.c skyeye_mach_ep7312.c skyeye_mach_pxa.c pxa.h xscale-copro.c skyeye_math_at91.c at91.h 2004-11-29 Cai Qiang <caiqiang@ustc.edu> * add simulation of LH79520 * changed files: skyeye_options.c Makefile.in * add files: skyeye_mach_lh79520.c, lh79520-hardware.h, lh79520-irqs.h, serial_amba_pl011.h, lh79520.h 2004-11-26 ksh * add energy profile function,now only support pxa * changed file in sim/arm: Makefile.in armdefs.h armemu.c armengr.c armengr.h armsym.c armsym.h skyeye_config.h skyeye_options.c wrapper.c skyeye_mach_pxa.c /*not completed*/ 2004-11-24 Benno <benjl@cse.unsw.edu.au>, chenyu * Thanks Benno, etc who developed L4 OS found bugs * The bug is in the LoadMult function: (sim/arm/armemu.c). Basically the value should not be updated on an abort. Without this fix data is corrupted while running the L4 operating system. With this fix we are able to run L4 and Linux server on top of L4. * changed file: skyeye/sim/arm/armemu.c 2004-11-12 teawater,oyangjian * modify ~/sim/arm/wrapper.c,skyeye_config.h,skyeye_option.c,armdefs.h * if add below option in skyeye.conf * step_disassemble:on[off] * then after each step command, the skyeye will show the next instrument * 2004-11-6 Cai Qiang, walimis <wlm@student.dlut.edu.cn> * add files for simulation of EP9312 * add EP9312 simulation, changed files: skyeye_options.c Makefile.in * add files: skyeye_mach_ep9312.c, clps9312.h ep9312.h serial_amba.h 2004-11-4 walimis <wlm@student.dlut.edu.cn> * clean at91rm9200 simulation code: at91rm92.h skyeye_mach_at91rm92.c 2004-11-3 walimis <wlm@student.dlut.edu.cn> * modified at91rm9200 uart simulation. now it can boot ARMLinux. * clean some codes of s3c4510b * changed file: skyeye_mach_at91rm92.c, at91rm92.h, skyeye_mach_s3c4510b.c 2004-10-30 walimis <wlm@student.dlut.edu.cn> * add ethernet support for s3c4510b. thanks to telpro2003@yahoo.com.cn * add files: dev_net_s3c4510b.h * changed files: skyeye_mach_s3c4510b.c 2004-09-29 chy * fix some no used code for lcd address test in armmem.c * fix some files for gtk-2.0 using pkg-config * changed files: gdb/Makefile.in sim/arm/Makefile.in sim/arm/configure 2004-08-07 chy * provide more info when open log file error * add ringbuffer log function, using log:length Option * changed files: skyeye_options.c skyeye_config.[ch] armemu.c 2004-8-7 Ksh, YinWenChao * update LCD simulation on ep7312 (minigui can run on skyeye) (by YiWenChao) * add Philips LPC2xxxx CPU simulation (by Kang Suo) * added files: lpc.h skyeye_mach_lpc.c * changed files: skyeye_lcd.c skyeye_options.c skyeye_mach_ep7312.c Makefile.in 2004-8-1 walimis <wlm@student.dlut.edu.cn> * add at91rm9200 simulation and mmu for arm920t. but it isn't completed. * correct s3c4510b interrupt simulation. thanks to telpro2003@yahoo.com.cn * add files: skyeye_mach_at91rm92.c, at91rm92.h,arm920t_mmu.c, arm920t_mmu.h. * changed files: armemu.c, armemu.h, mmu/cache.ch, skyeye_options.c 2004-07-21 LuZeTao * luzetao make the pxa uart simulation more perfect! * Change file: skyeye_mach_pxa.c 2004-07-19 LianZhuLing * add sharp lh7a400 (arm922t) CPU simulation from lianzhuling, now have not arm922t mmu cache support * add file: sharp.h skyeye_mach_sharp.c * changed file: skyeye_option.c Makefile.in 2004-07-19 LuZeTao, chenyu * luzetao find a solution to make linux-2.6.x output correctly through serail: if (pxa_io.ffier&0x2){ irq |= FFUART_IRQ; } ,then linux-2.6.x can run correctly! * add support of xscale MMU_CacheDisabled option control in cache read or write * fix skyeye_mach_pxa.c refresh_irq FUN * commit some info about xscale simulation not realized,so maybe fix in the future. Notice 2004-07-19 * change file: skyeye_mach_pxa.c armsupp.c xscale_copro.c 2004-06-23 chenyu * fix skyeye_mach_pxa.c refresh_irq FUN, FFIER TIE or RAVIE, so shoud be 3, FFIIR 0x4 or 0x2=0x6 * change file: skyeye_mach_pxa.c 2004-06-06 chenyu, lyh * set version 0.7.4 * fix bugs found by wenye@cs.ucsb.edu. rb_masks error in rb.c , malloc wb->data error in mmu_wb_init FUN in wb.c * mmu_rb_load FUN in rb.c, mmu_rb_search FUN in rb.c, mcr MMU_PID process in sa_mmu.c * Change file: mmu/rb.c mmu/wb.c sa_mmu.c * fix bugs in LoadSMult function in armemu.c, read line 4615 for more info * add log level, 0--no log info, 1-- pc instr, 2-- pc, instr state->Reg[0-15], 3 --pc, instr state->Reg state->RegBank * Change file: armemu.c * improve the simulation speed of SA11xx and PXAxxx * Change file: skyeye_mach_sa.c skyeye_mach_pxa.c 2004-05-25 chenyu * set version 0.7.3 * fix bug provided by Carl van Schaik <cvansch@cse.unsw.EDU.AU> , ARMul_Emulate32 FUN in armemu.c * fix bug that LDC STC process dataabort. ARMul_LDC ARMul_STC FUNs in armsupp.c * fix bug that use/system code use mrc/mcr coprocessor1, stc/ldc coprocessor2 instr, cause underfinedinstr error. ARMul_CoProInit FUN in armcopro.c * Changed file: armemu.c armsupp.c armcopro.c skyeye/gdb/top.c (for version number) 2004-05-23 chenyu, Xie Jun, Jiao Zhenqiang * fix a bug for strongarm, xscale, just like 2004-05-09 bug, * include LoadMult LoadSMult StoreMult StoreSMult functins. * now, the application using dynamic lib can run correctly. * NOTICE, not take care LDC STC intructions,look armsupp.c ARMul_LDC ARMul_STC !!!! * Changed files: armemu.c armsupp.c 2004-05-09 Kang Shuo, Xie Jun, Jiao Zhenqiang,chenyu * fix a bug for xscale,added ESP(extend small page) support in tlb.You can refer to xscle development menual(XJ, Ksh) * added ffuart read support in xscale(Ksh) * Changed files: tlb.c,tlb.h,skyeye_mach_pxa.c 2004-05-09 chenyu, Xie Jun, Jiao Zhenqiang, Kang Shuo * fix a HUGE BUG. When skyeye simulates strongarm, xscale and other with MMU cpus (not include ARM720T, such as ep7312), the user program uses instruction with WriteBack Attr. to accesses a nonexist page(data abort will happen), then the REGbase will be changed. This is a error. * if state->lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) * if state->lateabtSig=0, then it means Base Restored Abort Model * read armdefs.h for more info * Changed files: armcopro.c armdefs.h arminit.c skyeye_mach_at91.c skyeye_mach_cs89712.c skyeye_mach_ep7312.c skyeye_mach_ep7312.c skyeye_mach_pxa.c skyeye_mach_s3c44b0.c skyeye_mach_s3c4510b.c skyeye_mach_sa.c 2004-04-24 Ying Wenchao, Zeng Yi, chenyu * optimize LCD simulation * add Touch Screen on ep7312 simulation * Changed files: armdefs.h clps7110.h skyeye_lcd.c skyeye_mach_ep7312.c 2004-03-14 chenyu, Ying Wenchao, Xie Jun * fix a printf bug * changed file : skyeye_lcd.c 2004-03-13 chenyu, Ying Wenchao, Xie Jun * add LCD on ep7312 simulation * Changed files: deleted file: armlcd.c * added file: skyeye_lcd.c * changed file: gdb/Makefile.in sim/arm/Makefile.in armdefs.h armem.c skyeye_config.h skyeye_optin.c skyeye_mach_ep7312.c 2004-03-11 Kang Shuo, chenyu * add ne2k chip on ep7312 simulation * Important: add struct ARMul_io io in ARMul_State for more scalable Device support * changed files: armdefs.h clps7110.h skyeye_mach_at91.c skyeye_mach_ep7312.c skyeye-ne2k.[ch] 2004-01-14 Trilok Soni<trilok_soni@yahoo.co.in>, chenyu * Trilok Soni added simulation codes for cs89712. * new files: ep7212.h cs89712.h skyeye_mach_cs89712.c * changed files: skyeye_option.c 2003-10-06 walimis <wlm@student.dlut.edu.cn> * skyeye_mach_s3c4510b.c: clean some codes, modify interrupt routine, now successfully support booting uclinux. 2003-09-29 aleph <aleph@develer.com> * skyeye_options.c (split_param): put parameter name in param argument even when no "=" is found and error is returned. 2003-09-21 chenyu * :don't malloc space for io addr (so skyeye couldn't eat more mem),and process mem type in skyeye_options.c * : add type field in mem_bank_t struct, mem_type: MEMTYPE_IO, MEMTYPE_RAM, MEMTYPE_ROM * : fix bug: process boot parameter :do_mem_bank_option funtion:skyeye_options:224 * changed file: armmem.c armmem.h skyeye_config.h skyeye_options.c 2003-09-12 simoz * changed file: sa_mmu.c Fixed bug: Next and Step doesn't work when mmu wasn't enabled 2003-09-12 chenyu * cancel the limit that only support one io bank in skyeye.conf, now support more io_banks in skyeye.conf * changed file: skyeye_config.h skyeye_options.c *------- * add judgement after malloc, so when malloc failed, skyeye will exit. * changed file: arminit.c armmem.c armsupp.c skyeye_config.c wrapper.c mmu/rb.c 2003-09-10 simoz * changed file: armmem.c More checks on pointers 2003-09-10 simoz,chenyu * changed file: armmem.c recover clean up code from simoz: v1.4 v1.5 2003-09-10 simoz * changed file: sa_mmu.c checked the instruction cache in function sa_mmu_write. This will prevent the instruction cache to differ from memory. This patch fix the bug #1. It's now possible to use 'step' and 'next' command in gdb enviroment. 2003-09-03 chenyu * add xscale simulation, and change a lot of files: Important changes are in armemu.c(based on armemu.c in gdb+dejagnu-20030726.tar.bz2), which support ARMv5 instructions; armcopro.c, which support more coporcessors; armsupp.c&arminit.c, which change some init functions. Important added files are skyeye_mach_pxa.c, pxa.h, xscale_copro.c please notice important comments wich strings: '2003-08-' or '2003-09-'or '????'. Try command 'grep 2003-08- *.[ch] 2003-08-26 simoz, chenyu * fix bugs in skyeye_mach_sa.c skyeye_options.c: skyeye_mach_sa.c - Changed constant fd with parameter skyeye_config.uart.fd_in. - change fun select(1,....) to select(skyeye_config.uart.fd_in+1,...) skyeye_options.c - Fixed bug checking a return value. 2003-08-21 chenyu * changed file: * add function to log skyeye state info to a log file: skyeye_config.h: modify macro: SKYEYE_OUTREGS, SKYEYE_OUTMOREREGS, add log_config_t define... all for log_config_t skyeye_config.c: disable old skyeye_logfd process,the process now is in do_log_option::skyeye_option.c skyeye_options.c: add fun do_log_option to log skyeye info to a log file in skyeye.conf, could add a line like below: log: logon=0, logfile=/tmp/sk1.log, start=100000, end=200000 logon = 0 or 1 0:doesn't log, 1 do log logfile: the filename which have the log info start: the start point of instruction flow to log, should >=0 end: the end point of instruction flow to log * fix bug: skyeye_config.c::line 79: error :: only malloc string_i byte! from params[num_params] = malloc(string_i); to params[num_params] = malloc((string_i+16)&0xfffffff0); 2003-8-09 walimis <wlm@student.dlut.edu.cn> * changed file: skyeye_config.h skyeye_options.c : add boot parameter to mem_bankoption. add start_address to skyeye_config_t struct. this member is the start address of program. if a mem_bank has this parameter, the addr of this mem_bank should should be the start address of the program. e.g. mem_bank: map=M, type=RW, addr=0x10000000, size=0x00000800, file=./loader.bin, boot=yes then 0x10000000 should be the start address. wrapper.c: before program is running, set the PC of CPU to the start_address. 2003-8-08 walimis <wlm@student.dlut.edu.cn> * changed file: skyeye_config.h, skyeye_options.c:add uart option, which has fd_in and fd_out. now you can use them to connect real serial port. you can add an option to skyeye.conf as below: uart: fd_in=/dev/ttyS0, fd_out=/dev/ttyS0. then use a terminal connect host's COM1, you can see the output in the terminal. skyeye_mach_ep7312.c, skyeye_mach_at91.c: replace stdin and stdout with new uart option, fd_in and fd_out. wrapper.c: add skyeye_option_init function before skyeye_read_config. 2003-8-01 simoz * changed file: armmem.c cleanup code 2003-8-01 chenyu * changed file: skyeye_mach_at91.c :more strict exam in io_write_word and io_read_word when os access unknown addr armmem.c : use SKYEYE_OUTREGS in some place armemu.c : use SKYEYE_OUTREGS in line379 skyeye_config.h : add a info function macro: SKYEYE_OUTREGS 2003-7-21 walimis <wlm@student.dlut.edu.cn> * add files:skyeye_mach_s3c44b0.c and s3c44b0.h to support s3c44b0. but it's not completed. * change files: skyeye_options.c and Makefile.in to support s3c44b0. * change files: skyeye_mach_s3c4510b.c. correct timer support.now it can boot uclinux for s3c4510b. 2003-7-17 walimis <wlm@student.dlut.edu.cn> * change file:skyeye_config.h, add "mach_io_reset" and "mach_update_int" members to machine_config_t. now every machine has its io_reset and update_int functions. then we can remove update_int from armio.c. * change file:armio.c, clean some routines. later we should move the lcd routine somewhere. * change file:armio.h, remove struct io_state_t. * change file:armdefs.h, remove io_state_t from ARMul_State struct. * change file:arminit.c, remove io_reset. * change file:armmem.c, clean codes. * change file:wrapper.c, move io_reset here. * change file:skyeye_mach_*.c, add io_state struct to every machine. * add file:at91.h for skyeye_mach_at91.c * :s3c4510b.h. * change file:skyeye-ne2k.c, change state->io.intsr to state->interrupt. update_int to mach_update_int 2003-07-11 lyh chenyu * : skyeye-v0.3.0 is released. * : merge strongarm simulation from lyh based on skyeye-v0.2.6 with skyeye-v0.2.9 * : change the simulation of read/write byte/halfword process. the changed files include armvirt.[ch] armmmu.[ch] * : armem.[ch] skyeye_mach_*.* *_mmu.* * : change the simulation of write buffer process. the access size be changed from word to byte. the changed files * : include mmu/wb.* 2003-06-06 chenyu * :support vnet driver ver0.2, now host OS <----> many guest OSes ok! * add file:if_vnet.h, should be same as vnet/if_vnet.h * change file: sim/arm/skyeye_net_vnet.c, sim/arm/skyeye_net_tuntap.c(little change) * notice: only one skyeye file config hostip=x.x.x.x, other skyeye file config hosip=0.x.x.x, then * : skyeye know only open dev file for hostif one time. 2003-05-31 chenyu * :move to gdb-5.3 * change file: gdb/main.c gdb/Makefile.in sim/common/run.c sim/common/Make-common.in sim/arm/* 2003-05-26 chenyu * fixed bugs: the 8019's BNRY is been changed when xmit packet in driver, because when outb(NE_DMA), the skyeye will read the content of NE_DMA, so the BNRY changed. * change file: armvirt.c : fix bug: when wirte byte or halfword in io addr space, shoud not read it first. skyeye_config.h: add: add ioaddr_config struct and field in skyeye_config global variable skyeye_options.c: add: get options and set them to ioaddr_config struct in skyeye_config global variable 2003-04-27 chenyu * aim: change skyeye to support vnet or tuntap net device at the same time * add file: skyeye_net.c skyeye_net_tuntap.c skyeye_net_vnet.c * change file: skyeye_config.[ch] skyeye_options.c skyeye-ne2k.c Makefile.in ... 2003-4-2 walimis <walimi@peoplemail.com.cn> * add skyeye.h,include some macros for debug.and replace DEB_PRINT in skyeye_mach_ep7312.c.add include file skyeye.h to armdef.h * add files below to support samsung s3c4510b.but now it hasn't been completed: skyeye_mach_s3c4510b.c s3c4510b.h * modify skyeye_armmach.h to support samsung s3c4510b. add mach "s3c4510b". * modify Makefile.in to add skyeye_mach_s3c4510b.c. * add our skyeye's ChangeLog file. rename original ChangeLog to ChangeLog.old. * add net option. 2003-01-31: yangye,chenyu * skyeye-v0.2 * support NIC simulation 2002-12-14: chenyu * skyeye-v0.1 * add function to parse skyeye.conf, support ucosii and uclinux 2002-12-01: chenyu SkyEye Project initialized. �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/config.guess�����������������������������������������������������������������������0000644�0001750�0000144�00000126662�11006120657�014566� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#! 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The system name ranges from "MiNT" over "FreeMiNT" # to the lowercase version "mint" (or "freemint"). Finally # the system name "TOS" denotes a system which is actually not # MiNT. But MiNT is downward compatible to TOS, so this should # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} exit ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} exit ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} exit ;; m68k:machten:*:*) echo m68k-apple-machten${UNAME_RELEASE} exit ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} exit ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 exit ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} exit ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} exit ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} exit ;; mips:*:*:UMIPS | mips:*:*:RISCos) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #ifdef __cplusplus #include <stdio.h> /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #if defined (host_mips) && defined (MIPSEB) #if defined (SYSTYPE_SYSV) printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_SVR4) printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); #endif #endif exit (-1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` && SYSTEM_NAME=`$dummy $dummyarg` && { echo "$SYSTEM_NAME"; exit; } echo mips-mips-riscos${UNAME_RELEASE} exit ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax exit ;; Motorola:*:4.3:PL8-*) echo powerpc-harris-powermax exit ;; Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) echo powerpc-harris-powermax exit ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix exit ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 exit ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 exit ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 exit ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] then if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ [ ${TARGET_BINARY_INTERFACE}x = x ] then echo m88k-dg-dgux${UNAME_RELEASE} else echo m88k-dg-dguxbcs${UNAME_RELEASE} fi else echo i586-dg-dgux${UNAME_RELEASE} fi exit ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 exit ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 exit ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 exit ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd exit ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` exit ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id exit ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix exit ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} exit ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include <sys/systemcfg.h> main() { if (!__power_pc()) exit(1); puts("powerpc-ibm-aix3.2.5"); exit(0); } EOF if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` then echo "$SYSTEM_NAME" else echo rs6000-ibm-aix3.2.5 fi elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi exit ;; *:AIX:*:[45]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then IBM_ARCH=rs6000 else IBM_ARCH=powerpc fi if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} exit ;; *:AIX:*:*) echo rs6000-ibm-aix exit ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 exit ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to exit ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx exit ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 exit ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd exit ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 exit ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in 9000/31? ) HP_ARCH=m68000 ;; 9000/[34]?? ) HP_ARCH=m68k ;; 9000/[678][0-9][0-9]) if [ -x /usr/bin/getconf ]; then sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in 32) HP_ARCH="hppa2.0n" ;; 64) HP_ARCH="hppa2.0w" ;; '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 esac ;; esac fi if [ "${HP_ARCH}" = "" ]; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #define _HPUX_SOURCE #include <stdlib.h> #include <unistd.h> int main () { #if defined(_SC_KERNEL_BITS) long bits = sysconf(_SC_KERNEL_BITS); #endif long cpu = sysconf (_SC_CPU_VERSION); switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0"); break; case CPU_PA_RISC1_1: puts ("hppa1.1"); break; case CPU_PA_RISC2_0: #if defined(_SC_KERNEL_BITS) switch (bits) { case 64: puts ("hppa2.0w"); break; case 32: puts ("hppa2.0n"); break; default: puts ("hppa2.0"); break; } break; #else /* !defined(_SC_KERNEL_BITS) */ puts ("hppa2.0"); break; #endif default: puts ("hppa1.0"); break; } exit (0); } EOF (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` test -z "$HP_ARCH" && HP_ARCH=hppa fi ;; esac if [ ${HP_ARCH} = "hppa2.0w" ] then eval $set_cc_for_build # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler # generating 64-bit code. GNU and HP use different nomenclature: # # $ CC_FOR_BUILD=cc ./config.guess # => hppa2.0w-hp-hpux11.23 # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess # => hppa64-hp-hpux11.23 if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | grep __LP64__ >/dev/null then HP_ARCH="hppa2.0w" else HP_ARCH="hppa64" fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} exit ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} exit ;; 3050*:HI-UX:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include <unistd.h> int main () { long cpu = sysconf (_SC_CPU_VERSION); /* The order matters, because CPU_IS_HP_MC68K erroneously returns true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct results, however. */ if (CPU_IS_PA_RISC (cpu)) { switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; default: puts ("hppa-hitachi-hiuxwe2"); break; } } else if (CPU_IS_HP_MC68K (cpu)) puts ("m68k-hitachi-hiuxwe2"); else puts ("unknown-hitachi-hiuxwe2"); exit (0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && { echo "$SYSTEM_NAME"; exit; } echo unknown-hitachi-hiuxwe2 exit ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd exit ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd exit ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix exit ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf exit ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf exit ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi exit ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites exit ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd exit ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd exit ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd exit ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd exit ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' exit ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; *:UNICOS/mp:*:*) echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; 5000:UNIX_System_V:4.*:*) FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} exit ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} exit ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit ;; *:FreeBSD:*:*) case ${UNAME_MACHINE} in pc98) echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; amd64) echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; *) echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; esac exit ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin exit ;; i*:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit ;; i*:windows32*:*) # uname -m includes "-pc" on this system. echo ${UNAME_MACHINE}-mingw32 exit ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 exit ;; x86:Interix*:[3456]*) echo i586-pc-interix${UNAME_RELEASE} exit ;; EM64T:Interix*:[3456]*) echo x86_64-unknown-interix${UNAME_RELEASE} exit ;; [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) echo i${UNAME_MACHINE}-pc-mks exit ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we # UNAME_MACHINE based on the output of uname instead of i386? echo i586-pc-interix exit ;; i*:UWIN*:*) echo ${UNAME_MACHINE}-pc-uwin exit ;; amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*) echo x86_64-unknown-cygwin exit ;; p*:CYGWIN*:*) echo powerpcle-unknown-cygwin exit ;; prep*:SunOS:5.*:*) echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit ;; *:GNU:*:*) # the GNU system echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit ;; *:GNU/*:*:*) # other systems with GNU libc and userland echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu exit ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit ;; arm*:Linux:*:*) echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu exit ;; avr32*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; cris:Linux:*:*) echo cris-axis-linux-gnu exit ;; crisv32:Linux:*:*) echo crisv32-axis-linux-gnu exit ;; frv:Linux:*:*) echo frv-${VENDOR}-linux-gnu exit ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu exit ;; m32r*:Linux:*:*) echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu exit ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu exit ;; mips:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips #undef mipsel #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mipsel #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips #else CPU= #endif #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^CPU/{ s: ::g p }'`" test x"${CPU}" != x && { echo "${CPU}-${VENDOR}-linux-gnu"; exit; } ;; mips64:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips64 #undef mips64el #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mips64el #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips64 #else CPU= #endif #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^CPU/{ s: ::g p }'`" test x"${CPU}" != x && { echo "${CPU}-${VENDOR}-linux-gnu"; exit; } ;; or32:Linux:*:*) echo or32-${VENDOR}-linux-gnu exit ;; ppc:Linux:*:*) echo powerpc-${VENDOR}-linux-gnu exit ;; ppc64:Linux:*:*) echo powerpc64-${VENDOR}-linux-gnu exit ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; EV56) UNAME_MACHINE=alphaev56 ;; PCA56) UNAME_MACHINE=alphapca56 ;; PCA57) UNAME_MACHINE=alphapca56 ;; EV6) UNAME_MACHINE=alphaev6 ;; EV67) UNAME_MACHINE=alphaev67 ;; EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu${LIBC} exit ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in PA7*) echo hppa1.1-${VENDOR}-linux-gnu ;; PA8*) echo hppa2.0-${VENDOR}-linux-gnu ;; *) echo hppa-${VENDOR}-linux-gnu ;; esac exit ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-${VENDOR}-linux-gnu exit ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit ;; sh64*:Linux:*:*) echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu exit ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu exit ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-${VENDOR}-linux-gnu exit ;; vax:Linux:*:*) echo ${UNAME_MACHINE}-dec-linux-gnu exit ;; x86_64:Linux:*:*) echo x86_64-${VENDOR}-linux-gnu exit ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent # problems with other programs or directories called `ld' in the path. # Set LC_ALL=C to ensure ld outputs messages in English. ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ | sed -ne '/supported targets:/!d s/[ ][ ]*/ /g s/.*supported targets: *// s/ .*// p'` case "$ld_supported_targets" in elf32-i386) TENTATIVE="${UNAME_MACHINE}-${VENDOR}-linux-gnu" ;; a.out-i386-linux) echo "${UNAME_MACHINE}-${VENDOR}-linux-gnuaout" exit ;; coff-i386) echo "${UNAME_MACHINE}-${VENDOR}-linux-gnucoff" exit ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-${VENDOR}-linux-gnuoldld" exit ;; esac # Determine whether the default compiler is a.out or elf eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include <features.h> #ifdef __ELF__ # ifdef __GLIBC__ # if __GLIBC__ >= 2 LIBC=gnu # else LIBC=gnulibc1 # endif # else LIBC=gnulibc1 # endif #else #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) LIBC=gnu #else LIBC=gnuaout #endif #endif #ifdef __dietlibc__ LIBC=dietlibc #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^LIBC/{ s: ::g p }'`" test x"${LIBC}" != x && { echo "${UNAME_MACHINE}-${VENDOR}-linux-${LIBC}" exit } test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; } ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 exit ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... # I am not positive that other SVR4 systems won't match this, # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} exit ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx exit ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop exit ;; i*86:atheos:*:*) echo ${UNAME_MACHINE}-unknown-atheos exit ;; i*86:syllable:*:*) echo ${UNAME_MACHINE}-pc-syllable exit ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} exit ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp exit ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi exit ;; i*86:*:5:[678]*) # UnixWare 7.x, OpenUNIX and OpenServer 6. case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} exit ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' </usr/options/cb.name` echo ${UNAME_MACHINE}-pc-isc$UNAME_REL elif /bin/uname -X 2>/dev/null >/dev/null ; then UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ && UNAME_MACHINE=i586 (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ && UNAME_MACHINE=i686 (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ && UNAME_MACHINE=i686 echo ${UNAME_MACHINE}-pc-sco$UNAME_REL else echo ${UNAME_MACHINE}-pc-sysv32 fi exit ;; pc:*:*:*) # Left here for compatibility: # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i386. echo i386-pc-msdosdjgpp exit ;; Intel:Mach:3*:*) echo i386-pc-mach3 exit ;; paragon:*:*:*) echo i860-intel-osf1 exit ;; i860:*:4.*:*) # i860-SVR4 if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 else # Add other i860-SVR4 vendors below as they are discovered. echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 fi exit ;; mini*:CTIX:SYS*5:*) # "miniframe" echo m68010-convergent-sysv exit ;; mc68k:UNIX:SYSTEM5:3.51m) echo m68k-convergent-sysv exit ;; M680?0:D-NIX:5.3:*) echo m68k-diab-dnix exit ;; M68*:*:R3V[5678]*:*) test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) OS_REL='' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && { echo i486-ncr-sysv4.3${OS_REL}; exit; } /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && { echo i486-ncr-sysv4; exit; } ;; m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) echo m68k-unknown-lynxos${UNAME_RELEASE} exit ;; mc68030:UNIX_System_V:4.*:*) echo m68k-atari-sysv4 exit ;; TSUNAMI:LynxOS:2.*:*) echo sparc-unknown-lynxos${UNAME_RELEASE} exit ;; rs6000:LynxOS:2.*:*) echo rs6000-unknown-lynxos${UNAME_RELEASE} exit ;; PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) echo powerpc-unknown-lynxos${UNAME_RELEASE} exit ;; SM[BE]S:UNIX_SV:*:*) echo mips-dde-sysv${UNAME_RELEASE} exit ;; RM*:ReliantUNIX-*:*:*) echo mips-sni-sysv4 exit ;; RM*:SINIX-*:*:*) echo mips-sni-sysv4 exit ;; *:SINIX-*:*:*) if uname -p 2>/dev/null >/dev/null ; then UNAME_MACHINE=`(uname -p) 2>/dev/null` echo ${UNAME_MACHINE}-sni-sysv4 else echo ns32k-sni-sysv fi exit ;; PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort # says <Richard.M.Bartel@ccMail.Census.GOV> echo i586-unisys-sysv4 exit ;; *:UNIX_System_V:4*:FTX*) # From Gerald Hewes <hewes@openmarket.com>. # How about differentiating between stratus architectures? -djm echo hppa1.1-stratus-sysv4 exit ;; *:*:*:FTX*) # From seanf@swdc.stratus.com. echo i860-stratus-sysv4 exit ;; i*86:VOS:*:*) # From Paul.Green@stratus.com. echo ${UNAME_MACHINE}-stratus-vos exit ;; *:VOS:*:*) # From Paul.Green@stratus.com. echo hppa1.1-stratus-vos exit ;; mc68*:A/UX:*:*) echo m68k-apple-aux${UNAME_RELEASE} exit ;; news*:NEWS-OS:6*:*) echo mips-sony-newsos6 exit ;; R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) if [ -d /usr/nec ]; then echo mips-nec-sysv${UNAME_RELEASE} else echo mips-unknown-sysv${UNAME_RELEASE} fi exit ;; BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. echo powerpc-be-beos exit ;; BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. echo powerpc-apple-beos exit ;; BePC:BeOS:*:*) # BeOS running on Intel PC compatible. echo i586-pc-beos exit ;; SX-4:SUPER-UX:*:*) echo sx4-nec-superux${UNAME_RELEASE} exit ;; SX-5:SUPER-UX:*:*) echo sx5-nec-superux${UNAME_RELEASE} exit ;; SX-6:SUPER-UX:*:*) echo sx6-nec-superux${UNAME_RELEASE} exit ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} exit ;; *:Rhapsody:*:*) echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} exit ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown case $UNAME_PROCESSOR in unknown) UNAME_PROCESSOR=powerpc ;; esac echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) UNAME_PROCESSOR=`uname -p` if test "$UNAME_PROCESSOR" = "x86"; then UNAME_PROCESSOR=i386 UNAME_MACHINE=pc fi echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} exit ;; *:QNX:*:4*) echo i386-pc-qnx exit ;; NSE-?:NONSTOP_KERNEL:*:*) echo nse-tandem-nsk${UNAME_RELEASE} exit ;; NSR-?:NONSTOP_KERNEL:*:*) echo nsr-tandem-nsk${UNAME_RELEASE} exit ;; *:NonStop-UX:*:*) echo mips-compaq-nonstopux exit ;; BS2000:POSIX*:*:*) echo bs2000-siemens-sysv exit ;; DS/*:UNIX_System_V:*:*) echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} exit ;; *:Plan9:*:*) # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 # operating systems. if test "$cputype" = "386"; then UNAME_MACHINE=i386 else UNAME_MACHINE="$cputype" fi echo ${UNAME_MACHINE}-unknown-plan9 exit ;; *:TOPS-10:*:*) echo pdp10-unknown-tops10 exit ;; *:TENEX:*:*) echo pdp10-unknown-tenex exit ;; KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) echo pdp10-dec-tops20 exit ;; XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) echo pdp10-xkl-tops20 exit ;; *:TOPS-20:*:*) echo pdp10-unknown-tops20 exit ;; *:ITS:*:*) echo pdp10-unknown-its exit ;; SEI:*:*:SEIUX) echo mips-sei-seiux${UNAME_RELEASE} exit ;; *:DragonFly:*:*) echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` exit ;; *:*VMS:*:*) UNAME_MACHINE=`(uname -p) 2>/dev/null` case "${UNAME_MACHINE}" in A*) echo alpha-dec-vms ; exit ;; I*) echo ia64-dec-vms ; exit ;; V*) echo vax-dec-vms ; exit ;; esac ;; *:XENIX:*:SysV) echo i386-pc-xenix exit ;; i*86:skyos:*:*) echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' exit ;; i*86:rdos:*:*) echo ${UNAME_MACHINE}-pc-rdos exit ;; esac #echo '(No uname command or uname output not recognized.)' 1>&2 #echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 eval $set_cc_for_build cat >$dummy.c <<EOF #ifdef _SEQUENT_ # include <sys/types.h> # include <sys/utsname.h> #endif main () { #if defined (sony) #if defined (MIPSEB) /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, I don't know.... */ printf ("mips-sony-bsd\n"); exit (0); #else #include <sys/param.h> printf ("m68k-sony-newsos%s\n", #ifdef NEWSOS4 "4" #else "" #endif ); exit (0); #endif #endif #if defined (__arm) && defined (__acorn) && defined (__unix) printf ("arm-acorn-riscix\n"); exit (0); #endif #if defined (hp300) && !defined (hpux) printf ("m68k-hp-bsd\n"); exit (0); #endif #if defined (NeXT) #if !defined (__ARCHITECTURE__) #define __ARCHITECTURE__ "m68k" #endif int version; version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; if (version < 4) printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); else printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); exit (0); #endif #if defined (MULTIMAX) || defined (n16) #if defined (UMAXV) printf ("ns32k-encore-sysv\n"); exit (0); #else #if defined (CMU) printf ("ns32k-encore-mach\n"); exit (0); #else printf ("ns32k-encore-bsd\n"); exit (0); #endif #endif #endif #if defined (__386BSD__) printf ("i386-pc-bsd\n"); exit (0); #endif #if defined (sequent) #if defined (i386) printf ("i386-sequent-dynix\n"); exit (0); #endif #if defined (ns32000) printf ("ns32k-sequent-dynix\n"); exit (0); #endif #endif #if defined (_SEQUENT_) struct utsname un; uname(&un); if (strncmp(un.version, "V2", 2) == 0) { printf ("i386-sequent-ptx2\n"); exit (0); } if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ printf ("i386-sequent-ptx1\n"); exit (0); } printf ("i386-sequent-ptx\n"); exit (0); #endif #if defined (vax) # if !defined (ultrix) # include <sys/param.h> # if defined (BSD) # if BSD == 43 printf ("vax-dec-bsd4.3\n"); exit (0); # else # if BSD == 199006 printf ("vax-dec-bsd4.3reno\n"); exit (0); # else printf ("vax-dec-bsd\n"); exit (0); # endif # endif # else printf ("vax-dec-bsd\n"); exit (0); # endif # else printf ("vax-dec-ultrix\n"); exit (0); # endif #endif #if defined (alliant) && defined (i860) printf ("i860-alliant-bsd\n"); exit (0); #endif exit (1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && { echo "$SYSTEM_NAME"; exit; } # Apollos put the system type in the environment. test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } # Convex versions that predate uname can use getsysinfo(1) if [ -x /usr/convex/getsysinfo ] then case `getsysinfo -f cpu_type` in c1*) echo c1-convex-bsd exit ;; c2*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit ;; c34*) echo c34-convex-bsd exit ;; c38*) echo c38-convex-bsd exit ;; c4*) echo c4-convex-bsd exit ;; esac fi cat >&2 <<EOF $0: unable to guess system type This script, last modified $timestamp, has failed to recognize the operating system you are using. It is advised that you download the most up to date version of the config scripts from http://savannah.gnu.org/cgi-bin/viewcvs/*checkout*/config/config/config.guess and http://savannah.gnu.org/cgi-bin/viewcvs/*checkout*/config/config/config.sub If the version you run ($0) is already up to date, please send the following data and any information you think might be pertinent to <config-patches@gnu.org> in order to provide the needed information to handle your system. config.guess timestamp = $timestamp uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` /bin/uname -X = `(/bin/uname -X) 2>/dev/null` hostinfo = `(hostinfo) 2>/dev/null` /bin/universe = `(/bin/universe) 2>/dev/null` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` /bin/arch = `(/bin/arch) 2>/dev/null` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` UNAME_MACHINE = ${UNAME_MACHINE} UNAME_RELEASE = ${UNAME_RELEASE} UNAME_SYSTEM = ${UNAME_SYSTEM} UNAME_VERSION = ${UNAME_VERSION} EOF exit 1 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: ������������������������������������������������������������������������������skyeye-1.2.5_REL/INSTALL����������������������������������������������������������������������������0000644�0001750�0000144�00000022310�11006120657�013263� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Installation Instructions ************************* Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc. This file is free documentation; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. Basic Installation ================== Briefly, the shell commands `./configure; make; make install' should configure, build, and install this package. The following more-detailed instructions are generic; see the `README' file for instructions specific to this package. The `configure' shell script attempts to guess correct values for various system-dependent variables used during compilation. It uses those values to create a `Makefile' in each directory of the package. It may also create one or more `.h' files containing system-dependent definitions. Finally, it creates a shell script `config.status' that you can run in the future to recreate the current configuration, and a file `config.log' containing compiler output (useful mainly for debugging `configure'). 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In order to avoid this problem, you should set them in the `configure' command line, using `VAR=value'. For example: ./configure CC=/usr/local2/bin/gcc causes the specified `gcc' to be used as the C compiler (unless it is overridden in the site shell script). Unfortunately, this technique does not work for `CONFIG_SHELL' due to an Autoconf bug. Until the bug is fixed you can use this workaround: CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash `configure' Invocation ====================== `configure' recognizes the following options to control how it operates. `--help' `-h' Print a summary of the options to `configure', and exit. `--version' `-V' Print the version of Autoconf used to generate the `configure' script, and exit. `--cache-file=FILE' Enable the cache: use and save the results of the tests in FILE, traditionally `config.cache'. FILE defaults to `/dev/null' to disable caching. `--config-cache' `-C' Alias for `--cache-file=config.cache'. `--quiet' `--silent' `-q' Do not print messages saying which checks are being made. To suppress all normal output, redirect it to `/dev/null' (any error messages will still be shown). `--srcdir=DIR' Look for the package's source code in directory DIR. Usually `configure' can determine that directory automatically. `configure' also accepts some other, not widely useful, options. Run `configure --help' for more details. ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/README�����������������������������������������������������������������������������0000644�0001750�0000144�00000015644�10605111734�013126� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������SkyEye-V1.2.x README yuchen@tsinghua.edu.cn 1 Install (just type below command) 1.1 on Linux/MinGW/CygWin $ make 1.2 on FreeBSD $ gmake 1.3 on BeOS $ cd utils/portable/beos/tap_driver $ make install $ cd ../../../../ $ export PATH=/boot/home/gnupro-3.4.3/bin:$PATH $ make NO_BFD=1 then the SkyEye binary code will be in binary/skyeye or binary/skyeye.exe (CygWin/MinGW) Options: To compile the binary as static, which allows easy distributions: $ make STATIC=1 You can enable various compile options on the command line. For example, to disable DBCT do the following: $ make NO_DBCT=1 To disable compiling with the LCD do the following: $ make NO_LCD=1 To disable compiling the network device support do the following: $ make NO_NET=1 You may wish to not compile with the BFD library, to create smaller, standalone binaries. $ make NO_BFD=1 2 Usage (just type below command,then skyeye will show usage information) $ ./binary/skyeye -h NOTICE: you should have a kernel(ELF format or Binary Image), a filesystem (according to OS), a skyeye config file(default is skyeye.conf) 3 Enjoy it! you can use skyeye-testsuit-v2.x or later to test SkyEye-V1.x or later 4 required packages: 4.1 on Linux - If you don't run "make NO_BFD=1" to compile SkyEye: binutils-dev(bfd) - LCD simulation by GTK+ implementation required: gtk+-2.0-dev pkg-config atk-dev pango-dev freetype2-dev glib-dev x11-dev 4.2 on MinGW/CygWin - At least: w32api - If you don't run "make NO_BFD=1" to compile SkyEye: binutils-dev(bfd) 4.3 on BeOS BeOS R5 Development Tools gnupro-3.4.3 5 Tested Environment X86-32: CygWin/MinGW gcc-3.4, gcc-4.1.2 Linux (Debian) gcc-3.3 gcc-3.4 gcc-2.95 gcc-4.0 (doesn't support DBCT) BeOS (R5.0.3, Exp-Dano) gcc-2.95 + gcc-3.4.3 X86-64: Linux (Fedra) gcc-3.4 for X86-64 (doesn't support DBCT) 6 Original SkyEye is originally derived from GDB/Armulator. Thanks David McCullough! Now files in Directory skyeye-v1/arch/arm/common are from GDB/Armulator package. 7. User Manual You can visit the following url to get its online version: http://www.skyeye.org/wiki/UserManual APPENDIX A: the content of skyeye.conf #-------------------------------------------------------------------------------- # memmap.conf and skyeye.conf are all skyeye's hardware configuration files. # memmap.conf is for skyeye-v0.2.5- # skyeye.conf is for skyeye-v0.2.5+ # usually you don't need to change them. # for example, a AT91's configuration file is shown below: #-------------------------------------------------------------------------------- # below is the cpu config info # cpu: maybe arm7tdmi or arm720t cpu: arm7tdmi #-------------------------------------------------------------------------------- # below is the machine(development board) config info # machine(develop board) maybe at91 or ep7312 mach: at91 #------------------------------------------------------------------------------- #NOTICE: this parameter is useless for skyeye-V0.3.1+ # have 7 memory bank (include RAM, ROM, mapped IO space) # below is the memory config info mem_num: 7 # map=M means ram/rom, map=I means mapped IO space, # type=RW means can be read or written, # type=R means read only, # addr=0x..... means the mem bank's beginning address, # size=0x..... means the mem bank's memory size, # file=... is the filesystem image file, used for uclinux4skyeye or armlinux4skyeye mem_bank: map=M, type=RW, addr=0x00000000, size=0x00004000 mem_bank: map=M, type=RW, addr=0x01000000, size=0x00400000 mem_bank: map=M, type=R, addr=0x01400000, size=0x00400000, file=./boot.rom mem_bank: map=M, type=RW, addr=0x02000000, size=0x00400000 mem_bank: map=M, type=RW, addr=0x02400000, size=0x00008000 mem_bank: map=M, type=RW, addr=0x04000000, size=0x00400000 mem_bank: map=I, type=RW, addr=0xf0000000, size=0x10000000 #now, add more options on mem_bank mem_bank: map=M, type=RW, addr=0x10000000, size=0x00000800, file=./loader.bin,boot=yes #start binary program at 0x100000000 #---------------------------------------------------------------------------------- # below is the net config info # # type: cs8900a, rtl8019, rtl8019_16, s3c4510b # mac=.... means the mac addr in simulated NIC, # ethmod=tuntap/vnet means the virtual driver used in host evnironment, # hostip=... means the ip address in host environment to interactive with skyeye. # format: type=xxxx mac=xx:xx:xx:xx:xx:xx ethmod=tuntap/vnet hostip=dd.dd.dd.dd # # *********NOTICE********** # If you run two more skyeyes at the same time, # please use different skyeye.conf for each skyeye instance, and only one # skyeye run first and related skyeye.conf content has hostip value: # ...... # net: ... ethmod=vnet, hostip=ddd.ddd.ddd.ddd # other skyeye.conf should has content(hostip[0] should be 0): # ...... # net: ... ethmod=vnet, hostip=0.ddd.ddd.ddd net: type=rtl8019, mac=0:4:3:2:1:f, ethmod=tuntap, hostip=10.0.0.1 #------------------------------------------------------------------------------------ # below is the uart config info # # mod: stdio, pipe(fd_in/fd_out), net # converter: dcc # # example: # uart: mod=stdio # uart: mod=stdio, converter=dcc # uart: fd_in=/dev/ttyS0, fd_out=/dev/ttyS0 # uart: mod=pipe, desc=/dev/ttyS0 # uart: mod=pipe, desc_in=/dev/tty8, desc_out=/dev/tty9 # uart: mod=net, desc_in=192.168.1.163:21, desc_out=192.168.1.163:1121 # # now you can use them to connect real serial port. # you can add an option to skyeye.conf as below: uart: fd_in=/dev/ttyS0, fd_out=/dev/ttyS0 #then use a terminal connect host's COM1, you can see the output in the terminal. #----------------------------------------------------------------------------------- #add log parameter which is used to recode the instr. flow and regs when #program are running. log: logon=0, logfile=/tmp/sk1.log, start=100000, end=200000 #logon = 0 or 1 0:doesn't log, 1 do log #logfile: the filename which have the log info #start: the start point of instruction flow to log, should >=0 #end: the end point of instructio flow to log #----------------------------------------------------------------- # below is the lcd config info # type: au1100, ep7312, pxa, s3c2410x, s3c44b0x # mod: gtk, win32, beos lcd: type=ep7312, mod=gtk #----------------------------------------------------------------- # below is the touchscreen config info touchscreen: type=skyeye, base=0xff00b000, size=0x20, int=17 #----------------------------------------------------------------- # below is the sound config info # It's recommended to turn on DBCT at the same time. # # example: # sound: type=s3c44b0x, mod=pcm, channels=2, bits_per_sample=16, samples_per_sec=22050 #----------------------------------------------------------------- # below is the flash config info # type: 28F128J3A, SST39LF160, SST39VF160, Am29LV160T-8, Am29LV160T-16, # Am29LV160B-8, Am29LV160B-16, Am29LV800T-8, Am29LV800T-16, # Am29LV800B-8, Am29LV800B-16 # dump: write to file when data written. # # example: # flash: type=Am29LV160T-16, base=0x00000000, size=0x02000000, dump=Am29.dump ��������������������������������������������������������������������������������������������skyeye-1.2.5_REL/configure.in�����������������������������������������������������������������������0000644�0001750�0000144�00000007454�11022744126�014560� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������# -*- Autoconf -*- # Process this file with autoconf to produce a configure script. AC_PREREQ(2.60) AC_INIT(SkyEye, 1.2.5, skyeye-developer@lists.gro.clinux.org, skyeye) AC_CANONICAL_SYSTEM AC_ARG_PROGRAM AM_INIT_AUTOMAKE AC_CONFIG_SRCDIR([utils/main/skyeye.c]) AC_CONFIG_HEADER([config.h]) # some common header path we should include them COMMON_INCLUDES="-I\$(top_srcdir)/utils/config -I\$(top_srcdir)/utils/main -I\$(top_srcdir)/utils/main -I\$(top_srcdir)/utils -I\$(top_srcdir)/device" AC_SUBST(COMMON_INCLUDES) # Checks for programs. AC_PROG_CXX AC_PROG_AWK AC_PROG_CC AC_PROG_MAKE_SET AC_PROG_CPP AC_PROG_RANLIB dnl according to host type ,we can select different macro case "${build}" in i[[3456789]]86-*-linux*) CFLAGS="" dbct=false ;; x86_64-*-*) CFLAGS="" dbct=false ;; i[[3456789]]86-*-mingw32*) CFLAGS="" dbct=false ;; i[[3456789]]86-*-beos*) CFLAGS="" dbct=false ;; *-*-cygwin*) CFLAGS="" dbct=false ;; esac AM_CONDITIONAL([DBCT], [test x$dbct = xtrue]) AC_ARG_ENABLE([lcd], [ --enable-lcd Enable lcd simulation], [case "${enableval}" in yes) lcd=true ;; no) lcd=false ;; *) AC_MSG_ERROR([bad value ${enableval} for --enable-lcd]) ;; esac],[lcd=false]) AM_CONDITIONAL([LCD], [test x$lcd = xtrue]) # Checks for libraries. # FIXME: Replace `main' with a function in `-ladvapi32': AC_CHECK_LIB([advapi32], [main]) # FIXME: Replace `main' with a function in `-lbe': AC_CHECK_LIB([be], [main]) # FIXME: Replace `main' with a function in `-lc': AC_CHECK_LIB([c], [main]) # FIXME: Replace `main' with a function in `-lgdi32': AC_CHECK_LIB([gdi32], [main]) # FIXME: Replace `main' with a function in `-liberty': AC_CHECK_LIB([iberty], [main]) # FIXME: Replace `main' with a function in `-lintl': AC_CHECK_LIB([intl], [main]) # FIXME: Replace `main' with a function in `-lkernel32': AC_CHECK_LIB([kernel32], [main]) # FIXME: Replace `main' with a function in `-lm': AC_CHECK_LIB([m], [main]) # FIXME: Replace `main' with a function in `-lmsvcrt': AC_CHECK_LIB([msvcrt], [main]) # FIXME: Replace `main' with a function in `-ln': AC_CHECK_LIB([n], [main]) # FIXME: Replace `main' with a function in `-lnet': AC_CHECK_LIB([net], [main]) # FIXME: Replace `main' with a function in `-lroot': AC_CHECK_LIB([root], [main]) # FIXME: Replace `main' with a function in `-lsocket': AC_CHECK_LIB([socket], [main]) # FIXME: Replace `main' with a function in `-luser32': AC_CHECK_LIB([user32], [main]) # FIXME: Replace `main' with a function in `-lwinmm': AC_CHECK_LIB([winmm], [main]) # FIXME: Replace `main' with a function in `-lws2_32': AC_CHECK_LIB([ws2_32], [main]) AC_CHECK_LIB([bfd], [bfd_openr]) # Checks for header files. AC_HEADER_STDC AC_CHECK_HEADERS([fcntl.h inttypes.h limits.h locale.h netdb.h netinet/in.h stddef.h stdint.h stdlib.h string.h sys/file.h sys/ioctl.h sys/socket.h sys/time.h termios.h unistd.h gtk/gtk.h bfd.h]) # Checks for typedefs, structures, and compiler characteristics. AC_HEADER_STDBOOL AC_C_CONST AC_C_INLINE AC_TYPE_INT16_T AC_TYPE_INT32_T AC_TYPE_INT64_T AC_TYPE_INT8_T AC_TYPE_OFF_T AC_TYPE_SIZE_T AC_TYPE_SSIZE_T AC_HEADER_TIME AC_STRUCT_TM AC_TYPE_UID_T AC_TYPE_UINT16_T AC_TYPE_UINT32_T AC_TYPE_UINT64_T AC_TYPE_UINT8_T AC_C_VOLATILE # Checks for library functions. AC_FUNC_ERROR_AT_LINE AC_PROG_GCC_TRADITIONAL AC_FUNC_MALLOC AC_FUNC_MEMCMP AC_FUNC_MKTIME AC_FUNC_MMAP AC_FUNC_REALLOC AC_FUNC_SELECT_ARGTYPES AC_TYPE_SIGNAL AC_FUNC_VPRINTF AC_CHECK_FUNCS([atexit bzero getpagesize gettimeofday memmove memset munmap select setlocale socket sqrt strcasecmp strchr strdup strerror strspn strtol strtoul]) AC_OUTPUT([Makefile arch/arm/Makefile arch/bfin/Makefile arch/coldfire/Makefile arch/mips/Makefile arch/ppc/Makefile device/Makefile utils/Makefile]) ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/�����������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023523233�013370� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/scripts/���������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015055� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/scripts/check-gcc.sh���������������������������������������������������������0000644�0001750�0000144�00000001247�10604226523�017234� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/sh # # Written by Anthony Lee 2007.03 # printf "Checking gcc ... " case $CC in *gcc*) ;; *) printf "IGNORE\n" exit 0 ;; esac if ( $CC -dumpversion > /dev/null 2>&1 ); then GCC_VERSION=`$CC -dumpversion` elif ( $CC --version > /dev/null 2>&1 ); then GCC_VERSION=`$CC --version` else GCC_VERSION=unknown fi case $GCC_VERSION in unknown|2.*) printf "FAILED\n\n" printf "*** You are using $CC, version $GCC_VERSION .\n" printf "*** To perform the compilation, we need gcc >= 3.x.x !!!\n" printf "*** Run \"make NO_GCC_CHECK=1\" instead to ignore it.\n\n" exit 1 ;; *) printf "OK ( `basename $CC` version: $GCC_VERSION )\n" exit 0 ;; esac ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/scripts/check-bfd.sh���������������������������������������������������������0000644�0001750�0000144�00000001570�10604560667�017244� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/sh # # Written by Anthony Lee 2007.03 # printf "Checking bfd library ... " case $CC in *gcc*) ;; *) # other compiler, should be checked manually. printf "IGNORE\n" exit 0 ;; esac SRC=" #include <stdlib.h> #include <bfd.h> int main(int argc, char **argv) { bfd *abfd = bfd_openr(NULL, NULL); return 0; } " PROG="check-bfd" OBJECT="${BINARY_DIR}${PROG}.o" TARGET="${BINARY_DIR}${PROG}${SUFFIX}" ERR_MESSAGE="*** It seems that you don't have bfd library. *** Run \"make NO_BFD=1\" instead to ignore it." if ! ( echo "$SRC" | $CC $EXTRA_CFLAGS -o "$OBJECT" -c -x c - > /dev/null 2>&1 ); then printf "FAILED\n\n" printf "$ERR_MESSAGE\n\n" exit 1 fi if ! ( $CC -o "$TARGET" "$OBJECT" $BFD_LIBS $EXTRA_LIBS > /dev/null 2>&1 ); then printf "FAILED\n\n" printf "$ERR_MESSAGE\n\n" rm -f "$OBJECT" exit 1 fi rm -f "$OBJECT" rm -f "$TARGET" printf "OK\n" exit 0 ����������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/scripts/check-bigendian.sh���������������������������������������������������0000644�0001750�0000144�00000002115�10604226523�020413� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/sh # # Written by Anthony Lee 2007.03 # case $CC in *gcc*) ;; *) # other compiler, should be checked manually. printf "IGNORE\n" exit 0 ;; esac SRC=" static unsigned int data[] = {0x42696745, 0x6e646961, 0x6e537973}; int main(int argc, char **argv) { unsigned int v = 0x12345678; unsigned char *s = (unsigned char*)&v; exit((s[0] == 0x12 && s[1] == 0x34 && s[2] == 0x56 && s[3] == 0x78) ? 0 : 1); }" PROG="check-bigendian" OBJECT="${BINARY_DIR}${PROG}.o" TARGET="${BINARY_DIR}${PROG}${SUFFIX}" if ! ( echo "$SRC" | $CC -o "$OBJECT" -c -x c - > /dev/null 2>&1 ); then printf "FAILED (compiling object)" exit 1 fi if test "x$CROSS_COMPILE" = "x"; then if ! ( $CC -o "$TARGET" "$OBJECT" > /dev/null 2>&1 ); then rm -f "$OBJECT" printf "FAILED (compiling program)" exit 1 fi if ! ( "$TARGET" > /dev/null 2>&1 ); then rm -f "$OBJECT" rm -f "$TARGET" printf "no\n" exit 1 fi elif ! ( grep "BigEndianSys" "$OBJECT" > /dev/null 2>&1 ); then rm -f "$OBJECT" rm -f "$TARGET" printf "no\n" exit 1 fi rm -f "$OBJECT" rm -f "$TARGET" printf "yes\n" exit 0 ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/scripts/check-x86-asm.sh�����������������������������������������������������0000644�0001750�0000144�00000001763�10665424110�017705� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/sh # # Written by Anthony Lee 2007.03 # printf "Checking whether the compiler supports x86 asm ... " case $CC in *gcc*) ;; *) # other compiler, should be checked manually. printf "IGNORE\n" exit 0 ;; esac SRC=" int main(int argc, char **argv) { int i = 1; __asm__ (\" \ pushl %%eax\n \ movl %0, %%eax\n \ subl \$1, %%eax\n \ movl %%eax, %0\n \ popl %%eax\" \ : \ : \"g\" (i) ); return i; }" PROG="check-x86-asm" OBJECT="${BINARY_DIR}${PROG}.o" TARGET="${BINARY_DIR}${PROG}${SUFFIX}" ERR_MESSAGE="*** It seems that the compiler don't support inline x86 AT&T ASM codes. *** Run \"make NO_DBCT=1\" instead to ignore it." if ! ( echo "$SRC" | $CC $EXTRA_CFLAGS -o "$OBJECT" -c -x c - > /dev/null 2>&1 ); then printf "FAILED\n\n" printf "$ERR_MESSAGE\n\n" exit 1 fi if ! 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maintainer-clean-generic mostlyclean mostlyclean-compile \ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \ uninstall-am # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/profile/���������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015026� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/profile/symbol.h�������������������������������������������������������������0000644�0001750�0000144�00000004636�11013045572�016523� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armsym.h -- ARMulator emulation macros: SA11x Instruction Emulator. Copyright (C) 2001 Princeton University. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef ARMSYM_H #define ARMSYM_H #include "armdefs.h" #include <config.h> #ifdef HAVE_LIBBFD struct sym_func { char *name; long long total_energy; // for all instances long long total_cycle; // for all instances int instances; // number of instances }; typedef struct sym_func SYM_FUNC; struct sym_funcinst { /* Function Info */ SYM_FUNC *func_symbol; ARMword func_start_addr; // the address at which this function starts ARMword ret_addr; // the PC at which we make sub-routine call /* Profiling Data */ float tenergy; long long tcycle; }; #define MAX_LEVEL 1024 struct sym_taskinst { ARMword task_id; // Actually is the pointer to Linux struct task_struct /* Task call stack */ struct sym_funcinst func_stack[MAX_LEVEL]; int level; /* Profiling Data */ float total_energy; long long total_cycle; /* link data */ struct sym_taskinst *next; }; typedef struct sym_funcinst FUNC_NODE; typedef struct sym_taskinst TASK_STACK; /***************************************************** Function declaration ******************************************************/ //void ARMul_InitSymTable(bfd *abfd); SYM_FUNC *ARMul_GetSym(ARMword address); void ARMul_ProfInit(ARMul_State *state); FUNC_NODE *ARMul_CreateChild(ARMul_State *state); void ARMul_DestroyChild(ARMul_State *state); void ARMul_CallCheck(ARMul_State *state, ARMword cur_pc, ARMword to_pc, ARMword instr); void ARMul_TaskSwitch(ARMul_State *state); ARMword ARMul_TaskCreate(ARMul_State *state); void ARMul_ReportEnergy(ARMul_State *state, FILE* pf); void ARMul_Consolidate(ARMul_State *state); #endif #endif ��������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/profile/symbol.c�������������������������������������������������������������0000644�0001750�0000144�00000012313�11013045572�016505� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armsym.c -- Main instruction emulation: SA11x Instruction Emulator. Copyright (C) 2001 Princeton University This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <config.h> #ifdef HAVE_LIBBFD /* we do a workaround for those platform without bfd library */ #include <assert.h> #include "bfd.h" #include <search.h> #include "symbol.h" /* * FIXME: GNU hash table isn't exist everywhere!!! */ static char itoa_tab[16] = {'0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'} ; static long storage_needed; static asymbol **symbol_table; static unsigned long number_of_symbols, kernel_number; /************************************************************************** This function read the symbol list and store into a table It then generates a hash table based on the value of function symbol and the data is the pointer to struct funcsym defined in armsym.h The GNU hash table is used. **************************************************************************/ /*************** * added by ksh ***************/ void init_symbol_table(char* filename) { long i,j, digit; ENTRY newentry, *oldentry; SYM_FUNC *symp; asymbol *symptr; int key; bfd *abfd; printf("call ARMul_InitSymTable,kernel filename is %s. \n",filename); if(!filename){ fprintf(stderr, "Can not get correct kernel filename!Maybe your skyeye.conf have something wrong!\n"); skyeye_exit(-1); } abfd = bfd_openr (filename, 0); if (!bfd_check_format(abfd, bfd_object)) { printf("Wrong format\n") ; exit(0); } storage_needed = bfd_get_symtab_upper_bound(abfd); if (storage_needed < 0){ printf("FAIL\n"); exit(0); } // <tktan> BUG200105221946 :symbol_table = (asymbol **) malloc (storage_needed); symbol_table = (asymbol **) malloc (storage_needed); number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); kernel_number = number_of_symbols; /* <tktan> BUG200106022219 */ if (number_of_symbols < 0){ printf("FAIL\n"); exit(0); } if (!hcreate(number_of_symbols << 1)) { printf("Not enough memory for hash table\n"); exit(0); } for (i = 0; i < number_of_symbols; i++) { symptr = symbol_table[i] ; key = symptr->value + symptr->section->vma; // adjust for section address if (((i<kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 ((i<kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654 (symbol_table[i]->flags & 0x10)) { // Is a function symbol // printf("%x %8x %s\n", symbol_table[i]->flags, key, symbol_table[i]->name); // *********************************************************** // This is converting the function symbol value to char string // and use it as a key in the GNU hash table // ******************************************************** newentry.key = (char *) malloc(9); for (j=0;j<8;j++) { newentry.key[j] = itoa_tab[((key) >> (j << 2)) & 0xf] ; } newentry.key[8] = 0 ; // ************************************************* // This is allocating memory for a struct funcsym // ************************************************* symp = (SYM_FUNC *) malloc(sizeof(SYM_FUNC)); newentry.data = (char *) symp; symp->name = (char *) symbol_table[i]->name ; symp->total_cycle = 0; symp->total_energy = 0; symp->instances = 0; // *********************************************** // Insert into hash table // ******************************************* /* <tktan> BUG200106022219 */ oldentry = hsearch(newentry, FIND) ; if (oldentry) { // was entered // printf("Duplicate Symbol: %x %s\n", key, symp->name); oldentry->data = (char *) symp ; } else if (!hsearch(newentry, ENTER)) { printf("Insufficient memory\n"); exit(0) ; } } } return; } /*************************************************************** This function get check the hash table for an entry If it exists, the corresponding pointer to the SYM_FUNC will be returned *************************************************************/ char *get_sym(ARMword address) { int j ; ENTRY entry, *ep; char text[9] ; SYM_FUNC *symp; //printf("GetSym %x\n", address); entry.key = text ; for (j=0;j<8;j++) { entry.key[j] = itoa_tab[(address >> (j << 2)) & 0xf] ; } entry.key[8] = 0 ; /*a bug need to fixed */ ep = hsearch(entry, FIND) ; if (ep != 0) { symp = (SYM_FUNC *) ep->data; return(symp->name); } else return(NULL); } #endif ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/profile/code_cov.c�����������������������������������������������������������0000644�0001750�0000144�00000007352�11006552446�016775� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* cov_prof.c - used to record the WRX action for memory address Copyright (C) 2008 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/08/2008 Michael.Kang <blackfin.kang@gmail.com> */ #include <stdio.h> #include <stdint.h> #include <stdlib.h> #include "skyeye_types.h" /** * pointer of memory allocated for code coverage */ static uint8_t * prof_mem; static int prof_start; static int prof_end; void cov_init(int start_addr, int end_addr){ int prof_size = end_addr - start_addr; prof_start = start_addr; prof_end = end_addr; /* we use four bits to record the WRX action for a 32 bit word */ int mem_alloc = (prof_size / 4) / 2; prof_mem = malloc(mem_alloc); if(!prof_mem) fprintf(stderr, "Can not alloc memory for code coverage, profiling is disabled.\n"); else printf("Begin do code coverage between 0x%x and 0x%x .\n", prof_start, prof_end); } /** * flags: 4 means read, 2 means write, 1 means eXecute * */ void cov_prof(int flags,WORD addr){ if(addr < prof_start || addr >= prof_end) return; int offset = (addr - prof_start) / 8; uint8_t * prof_addr = &prof_mem[offset] ; *prof_addr |= flags << ((addr - prof_start) % 8); //printf("addr=0x%x, flags=0x%x, offset=0x%x,(addr - prof_start)%8=0x%x\n", addr, flags, offset, (addr - prof_start)%8); return; } /** * deinitialization function */ void cov_fini(char * filename){ FILE * fp = fopen(filename, "w+"); if(!fp){ fprintf(stderr, "Warning: can not open file %s for code coverage\n", filename); return; } int offset = 0; char* str = malloc(32 * 2); /*we use 64 bytes to store coverage profile data for 32 words */ while(offset < ((prof_end - prof_start) / 8)){ sprintf(str," %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d", prof_mem[offset]&0x1, prof_mem[offset]&0x10 >> 4, prof_mem[offset+1]&0x1, prof_mem[offset+1]&0x10 >> 4, prof_mem[offset+2]&0x1, prof_mem[offset+2]&0x10 >> 4, prof_mem[offset+3]&0x1, prof_mem[offset+3]&0x10 >> 4, prof_mem[offset + 4]&0x1, prof_mem[offset + 4]&0x10 >> 4, prof_mem[offset + 5]&0x1, prof_mem[offset + 5]&0x10 >> 4, prof_mem[offset + 6]&0x1, prof_mem[offset + 6]&0x10 >> 4, prof_mem[offset + 7]&0x1, prof_mem[offset + 7]&0x10 >> 4, prof_mem[offset + 8]&0x1, prof_mem[offset + 8]&0x10 >> 4, prof_mem[offset + 9]&0x1, prof_mem[offset + 9]&0x10 >> 4, prof_mem[offset + 10]&0x1, prof_mem[offset + 10]&0x10 >> 4, prof_mem[offset + 11]&0x1, prof_mem[offset + 11]&0x10 >> 4, prof_mem[offset + 12]&0x1, prof_mem[offset + 12]&0x10 >> 4, prof_mem[offset + 13]&0x1, prof_mem[offset + 13]&0x10 >> 4, prof_mem[offset + 14]&0x1, prof_mem[offset + 14]&0x10 >> 4, prof_mem[offset + 15]&0x1, prof_mem[offset + 15]&0x10 >> 4 ); fprintf(fp, "%x : %s\n", (prof_start + (offset * 8)), str); offset += 16; /* we use one line to record the profiling data for 32 words. */ } fclose(fp); if(prof_mem) free(prof_mem); if(str) free(str); return; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/profile/code_cov.h�����������������������������������������������������������0000644�0001750�0000144�00000002345�11006365156�016777� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* cov_prof.h - some defination for code coverage Copyright (C) 2008 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/08/2008 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __CODE_COV_H__ #define __CODE_COV_H__ #define READ_FLAG 0x4 #define WRITE_FLAG 0x2 #define EXEC_FLAG 0x1 void cov_init(int start_addr, int end_addr); void cov_prof(int flags, WORD addr); void cov_fini(char * filename); #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/����������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014633� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_config.c�������������������������������������������������������0000644�0001750�0000144�00000014302�10555732132�017650� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_config.c - config file interface for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 3/21/2003 Add config file interface to skyeye. * Rename memmap.conf to skyeye.conf * walimis <walimi@peoplemail.com.cn> * */ #include "skyeye_defs.h" #include "skyeye_config.h" //chy 2005-07-30 extern char *skyeye_config_filename; //in skyeye.c //int skyeye_instr_debug=0; FILE *skyeye_logfd; /**/ int parse_line_unformatted (char *line) { #define MAX_PARAMS_LEN 40 char *ptr; unsigned i, string_i; char string[512]; char *params[MAX_PARAMS_LEN]; int num_params; int inquotes = 0; int comment = 0; int retval = 0; memset (params, 0, sizeof (params)); if (line == NULL) return 0; /*if passed nothing but whitespace, just return */ for (i = 0; i < strlen (line); i++) { if (!isspace (line[i])) break; } if (i >= strlen (line)) return 0; num_params = 0; ptr = strtok (line, ":"); while ((ptr) && (!comment)) { string_i = 0; for (i = 0; i < strlen (ptr); i++) { if (ptr[i] == '"') inquotes = !inquotes; else if ((ptr[i] == '#') && !inquotes) { comment = 1; break; } else { if (!isspace (ptr[i]) || inquotes) string[string_i++] = ptr[i]; } } string[string_i] = '\0'; if (string_i == 0) break; if (params[num_params] != NULL) { free (params[num_params]); params[num_params] = NULL; } if (num_params < MAX_PARAMS_LEN) { //chy 2003-08-21, only malloc string_i byte is error! //params[num_params] = malloc(string_i); params[num_params] = malloc ((string_i + 16) & 0xfffffff0); if (!params[num_params]) { printf ("SKYEYE:parse_line_unformatted: malloc params[%d] error\n", num_params); skyeye_exit (-1); } strncpy (params[num_params], string, string_i); params[num_params][string_i] = '\0'; num_params++; ptr = strtok (NULL, ","); } else { fprintf (stderr, "too many parameters, max is %d\n", MAX_PARAMS_LEN); } } /*end while */ /* for (i=0; i < MAX_PARAMS_LEN; i++) { if ( params[i] != NULL ) { if (i == 0) printf("****option: %s****\n", params[i]); else printf("params %d: %s\n", i, params[i]); } } */ retval = parse_line_formatted (num_params, ¶ms[0]); for (i = 0; i < MAX_PARAMS_LEN; i++) { if (params[i] != NULL) { free (params[i]); params[i] = NULL; } } return retval; } /*parse every line that has been formatted * return -1: if a option has exceeded it's max number or * option's do_option function has a error or * there is an unkonw option. * upper level function should print error and exit. * */ int parse_line_formatted (int num_params, const char *params[]) { int i; skyeye_option_t *sop = skyeye_options; int len = sizeof (skyeye_options) / sizeof (skyeye_option_t); int retval = 0; if (num_params < 1) return 0; for (i = 0; i < len; i++, sop++) { if (!strncmp (sop->name, params[0], MAX_OPTION_NAME)) { sop->do_num++; if (sop->do_num > sop->max_do_num) { /**/ fprintf (stderr, "\"%s\" option has exceeded max number %d!\n", params[0], sop->max_do_num); return -1; } else if (retval = sop->do_option (sop, num_params - 1, ¶ms[1]) < 0) { fprintf (stderr, "\"%s\" option parameter error!\n", params[0]); return retval; } else return retval; } } fprintf (stderr, "Unkonw option: %s\n", params[0]); return -1; /* unknow option specified */ } /* 2007-01-22 : SKYEYE4ECLIPSE from skyeye_options.c */ //chy 2004-12-05 for eclipse //#define SKYEYE4ECLIPSE #ifdef SKYEYE4ECLIPSE extern char *inferior_io_terminal; #endif //------------------------------ extern void usage(); extern void display_all_support(); int skyeye_read_config () { FILE *config_fd; char *ret; char line[MAX_STR]; //chy 2005-07-30 //char *config_file = DEFAULT_CONFIG_FILE; if (skyeye_config_filename == NULL) skyeye_config_filename = DEFAULT_CONFIG_FILE; strncpy (skyeye_config.config_file, skyeye_config_filename, MAX_FILE_NAME); if (config_fd = fopen (skyeye_config.config_file, "r")) { int retval = 0; int len = 0; do { ret = fgets (line, sizeof (line) - 1, config_fd); line[sizeof (line) - 1] = '\0'; len = strlen (line); if (len > 0) line[len - 1] = '\0'; if ((ret != NULL) && strlen (line)) { if (parse_line_unformatted (line) < 0) { retval = -1; break; // quit parsing after first error } } } while (!feof (config_fd)); /* 2007-01-18 added by Anthony Lee: for new uart device frame */ if(skyeye_config.uart.count == 0) { #ifndef SKYEYE4ECLIPSE char tmp[] = "uart: mod=stdio"; #else char tmp[1024]; snprintf(tmp, sizeof(tmp), "uart: mod=pipe, desc=%s", inferior_io_terminal, inferior_io_terminal); #endif if(parse_line_unformatted(tmp) < 0) retval = -1; } if (retval < 0) { fprintf (stderr, "skyeye_read_config: config file %s have errors!\n", skyeye_config.config_file); return -1; } } else { fprintf (stderr, "Failed to open skyeye config file %s in the same directory\n", skyeye_config.config_file); perror ("error"); usage (); display_all_support(); return -1; } //chy 2003-08-20 #if 0 //chy 2003-07-11: add log file skyeye_logfd = 0; skyeye_instr_debug = 1; if (skyeye_logfd = fopen ("/tmp/skyeyelog", "w+")) fprintf (stderr, "skyeye log file is /tmp/skyeyelog\n"); else { fprintf (stderr, "create skyeye log file failed, /tmp/skyeyelog\n"); perror ("error"); exit (0); } #endif return 0; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_config.h�������������������������������������������������������0000644�0001750�0000144�00000023042�11006365156�017656� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_config.h - config file interface for skyeye. Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* 4/02/2003 add net option * walimis <walimi@peoplemail.com.cn> * 3/21/2003 Add config file interface to skyeye. * Rename memmap.conf to skyeye.conf * Move some code from armmem.c. * walimis <walimi@peoplemail.com.cn> * 10/24/2005 add dbct test speed function * teawater <c7code-uc@yahoo.com.cn> * */ #ifndef __SKYEYE_CONFIG_H_ #define __SKYEYE_CONFIG_H_ #include "skyeye_types.h" #include "skyeye_options.h" #define DEFAULT_CONFIG_FILE "skyeye.conf" #define MAX_FILE_NAME 256 typedef struct { const char *cpu_arch_name; /*cpu architecture version name.e.g. armv4t */ const char *cpu_name; /*cpu name. e.g. arm7tdmi or arm720t */ uint32_t cpu_val; /*CPU value; also call MMU ID or processor id;see ARM Architecture Reference Manual B2-6 */ uint32_t cpu_mask; /*cpu_val's mask. */ uint32_t cachetype; /*this cpu has what kind of cache */ } cpu_config_t; typedef struct machine_config { const char *machine_name; /*e.g.at91,ep7312,clps711x */ void (*mach_init) (void * state, struct machine_config * this_mach); /*should be called when the machine reset */ uint32_t (*mach_io_read_byte) (void * state, uint32_t addr); void (*mach_io_write_byte) (void * state, uint32_t addr, uint32_t data); uint32_t (*mach_io_read_halfword) (void * state, uint32_t addr); void (*mach_io_write_halfword) (void * state, uint32_t addr, uint32_t data); uint32_t (*mach_io_read_word) (void * state, uint32_t addr); void (*mach_io_write_word) (void * state, uint32_t addr, uint32_t data); /*ywc 2005-03-30 */ uint32_t (*mach_flash_read_byte) (void * state, uint32_t addr); void (*mach_flash_write_byte) (void * state, uint32_t addr, uint32_t data); uint32_t (*mach_flash_read_halfword) (void * state, uint32_t addr); void (*mach_flash_write_halfword) (void * state, uint32_t addr, uint32_t data); uint32_t (*mach_flash_read_word) (void * state, uint32_t addr); void (*mach_flash_write_word) (void * state, uint32_t addr, uint32_t data); /* for I/O device * */ void (*mach_io_do_cycle) (void * state); void (*mach_io_reset) (void * state); /* io reset when init io */ void (*mach_update_int) (void * state); /* update interrupt pend bit */ void (*mach_set_intr) (u32 interrupt); /*set interrupt pending bit */ int (*mach_pending_intr) (u32 interrupt); /*test if interrupt is pending. 1: pending */ void (*mach_update_intr) (void *mach); /*update interrupt pending bit */ int (*mach_mem_read_byte) (void *mach, u32 addr, u32 * data); int (*mach_mem_write_byte) (void *mach, u32 addr, u32 data); /* FIXME! point to the current void. * */ void *state; /* FIXME! * we just temporarily put devices here * */ struct device_desc **devices; int dev_count; } machine_config_t; #define MAX_BANK 8 #define MAX_STR 1024 #define MEMTYPE_IO 0 #define MEMTYPE_RAM 1 #define MEMTYPE_ROM 2 /*ywc 2005-03-30*/ #define MEMTYPE_FLASH 3 /*ksh 2004-11-26,energy profile flag*/ typedef struct { char logfile[MAX_FILE_NAME]; char filename[MAX_FILE_NAME]; uint32_t energy_prof; } energy_config_t; /*net option*/ typedef struct { int state; // "on"=1,"off"=0, "on" means nic exist, "off" means nic don't exist unsigned char macaddr[6]; unsigned char hostip[4]; //the hostos ip addr, used in tuntap net device int ethmod; int fd; // the opend dev file handle int hubindex; //the index means the hub number, such as vnet0, vnet1... //nic functions int (*net_init) (int index, unsigned char *macaddr, unsigned char *hostip); //the index means nic index unsigned char (*net_output) (int if_fd, void * state, unsigned char startpage, unsigned short packet_len); void (*net_input) (int if_fd, void * state); } net_config_t; #define NET_MAXNICNUM_PER_HOST 4 /*uart option*/ /*add by walimis. 20030808*/ /* 2007-01-18 added by Anthony Lee: see "device/uart/skyeye_uart.h" */ #define MAX_UART_DEVICE_NUM 8 struct uart_device; typedef struct { /* 2007-01-18 modified by Anthony Lee: see "device/uart/skyeye_uart.h" */ int count; /* count of device */ struct uart_device *devs[MAX_UART_DEVICE_NUM]; /* list of device */ } uart_config_t; //chy 2003-08-20, used to log the instr®s states to log file typedef struct { FILE *log_fd; int logon; //log or not int memlogon; //log memory accesses or not unsigned long long start; //start clock unsigned long long end; //end clock unsigned long long length; //the max instr length of log file } log_config_t; /* some devices may have the same parameters. * type: device's type name * name: device's instance name * base: I/O or memory base address * size: size of I/O or memory. * interrupts: * */ typedef struct common_config { char *type; char *name; u32 base; u32 size; u32 interrupts[MAX_INTERRUPT]; } common_config_t; /*config file option struct*/ int do_dummy_option (); int do_arch_option (); int do_cpu_option (); int do_mach_option (); int do_mem_bank_option (); int do_net_option (); int do_energy_option (); int do_uart_option (); int do_lcd_option (); int do_flash_option (); int do_touchscreen_option (); int do_sound_option (); int do_nandflash_option(); int do_regfile_option();/* to set the values for regfile in skyeye.conf */ int do_load_addr_option(); /* to load elf file to another address */ int do_code_cov_option(); /* to profile code coverage */ /*ywc 2005-04-01*/ int do_dbct_option (); int do_log_option (); int do_step_disassemble_option (); //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED int do_dbct_test_speed_sec(); #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- #define MAX_OPTION_NAME 32 #define MAX_PARAM_NAME 32 typedef struct skyeye_option_t { char *name; int (*do_option) (struct skyeye_option_t * this_opion, int num_params, const char *params[]); int do_num; /*number of call do_option function */ int max_do_num; /*max number of call do_option function. where should we reset these values? */ } skyeye_option_t; typedef struct { char *arch_name; void (*init) (); void (*reset) (); void (*step_once) (); void (*set_pc) (WORD addr); WORD (*get_pc)(); //chy 2006-04-15 int (*ICE_write_byte) (WORD addr, uint8_t data); int (*ICE_read_byte)(WORD addr, uint8_t *pv); int (*parse_cpu) (const char *param[]); int (*parse_mach) (machine_config_t * mach, const char *param[]); int (*parse_mem) (int num_params, const char *params[]); int (*parse_regfile) (int num_params, const char *params[]); } arch_config_t; typedef struct code_cov_option code_cov_t; typedef struct { arch_config_t *arch; //cpu_config_t *cpu; machine_config_t *mach; //mem_config_t mem; //chy 2003-09-12, now support more io banks // ioaddr_config_t ioaddr; //used for ARMul_notIOaddr funciton net_config_t net[NET_MAXNICNUM_PER_HOST]; uart_config_t uart; log_config_t log; uint32_t start_address; /*ywc 2005-03-31, no_dbct used by Dynamic Binary Code Translation */ uint32_t no_dbct; /*ksh 2004-11-26,energy profile flag */ energy_config_t energy; char config_file[MAX_FILE_NAME]; code_cov_t code_cov; //oyangjian add here 2004-11-3 uint32_t can_step_disassemble; //teawater add for new tb manage function 2005.07.10---------------------------- uint32_t tb_tbt_size; uint32_t tb_tbp_size; //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED int dbct_test_speed_sec; #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- } skyeye_config_t; skyeye_config_t skyeye_config; static skyeye_option_t skyeye_options[] = { {"arch", do_arch_option, 0, 1}, {"cpu", do_cpu_option, 0, 1}, {"mach", do_mach_option, 0, 1}, /*mem option */ {"mem_bank", do_mem_bank_option, 0, MAX_BANK}, {"net", do_net_option, 0, 10}, {"energy", do_energy_option, 0, 1}, {"uart", do_uart_option, 0, MAX_UART_DEVICE_NUM}, {"lcd", do_lcd_option, 0, 1}, {"flash", do_flash_option, 0, 1}, {"nandflash",do_nandflash_option,0,1}, {"touchscreen", do_touchscreen_option, 0, 1}, {"sound", do_sound_option, 0, 1}, /*ywc 2005-04-01 */ //teawater add for new tb manage function 2005.07.10---------------------------- {"dbct", do_dbct_option, 0, 3}, /*log option */ {"log", do_log_option, 0, 3}, {"regfile", do_regfile_option, 0, 1}, {"load_addr", do_load_addr_option, 0, 3}, /* * this option can disassmebl the next c statement * with assemble code and may be have some usefull * */ {"step_disassemble", do_step_disassemble_option, 0, 1}, #ifdef DBCT_TEST_SPEED {"dbct_test_speed_sec", do_dbct_test_speed_sec, 0, 1}, #endif //DBCT_TEST_SPEED {"code_coverage", do_code_cov_option, 0, 1}, }; int skyeye_read_config (); #endif /*__SKYEYE_CONFIG_H_*/ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_arch.c���������������������������������������������������������0000644�0001750�0000144�00000003517�10577706467�017346� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_arch.c - all architecture definition for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "skyeye_arch.h" #include "skyeye_config.h" #include <stdlib.h> arch_config_t *skyeye_archs[MAX_SUPP_ARCH]; /* * register a supported arch to skyeye_archs */ void register_arch (arch_config_t * arch) { int i; for (i = 0; i < MAX_SUPP_ARCH; i++) { if (skyeye_archs[i] == NULL) { skyeye_archs[i] = arch; return; } } } extern void init_arm_arch (); extern void init_bfin_arch (); extern void init_coldfire_arch (); extern void init_mips_arch(); extern void init_ppc_arch(); void initialize_all_arch () { int i; for (i = 0; i < MAX_SUPP_ARCH; i++) { skyeye_archs[i] = NULL; } /* register arm_arch */ init_arm_arch (); /* register bfin_arch */ init_bfin_arch (); /* register mips_arch */ init_mips_arch (); /* register coldfire_arch */ init_coldfire_arch (); /* register ppc_arch */ init_ppc_arch(); } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_types.h��������������������������������������������������������0000644�0001750�0000144�00000002632�10572524543�017563� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_types.h - some data types definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __SKYEYE_TYPES_H #define __SKYEYE_TYPES_H #include <stdint.h> /*default machine word length */ #define WORD uint32_t typedef struct _arch_s { void (*init) (); void (*reset) (); void (*step_once) (); void (*set_pc)(WORD addr); WORD (*get_pc)(); //chy 2004-04-15 int (*ICE_write_byte) (WORD addr, uint8_t v); int (*ICE_read_byte)(WORD addr, uint8_t *pv); } generic_arch_t; #endif ������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_arch.h���������������������������������������������������������0000644�0001750�0000144�00000002213�10557302765�017332� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_arch.h - some generic arch definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __SKYEYE_ARCH_H__ #define __SKYEYE_ARCH_H__ /* the number of supported architecture */ #define MAX_SUPP_ARCH 8 #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_options.c������������������������������������������������������0000644�0001750�0000144�00000055132�11006365156�020104� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_options.c - skyeye config file options' functions Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* 08/20/2003 add log option function chenyu 4/02/2003 add net option function * walimis <walimi@peoplemail.com.cn> * 3/22/2003 add cpu, mem_num, mem_bank, arch, dummy option function * walimis <walimi@peoplemail.com.cn> * 10/24/2005 add dbct test speed function * teawater <c7code-uc@yahoo.com.cn> * */ #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include "skyeye_options.h" #include "skyeye_arch.h" #include "skyeye_config.h" #include "skyeye_arch.h" #include "skyeye_config.h" /* 2007-01-18 added by Anthony Lee: for new uart device frame */ #include "skyeye_uart.h" #include "skyeye_net.h" #include "skyeye_lcd.h" extern FILE *skyeye_logfd; int split_param (const char *param, char *name, char *value) { const char *src = param; char *dst = name; while (*src && (*src != '=')) *dst++ = *src++; *dst = '\0'; if (*src == '\0') { value = '\0'; return -1; } strcpy (value, src + 1); return 0; } /* we need init some options before read the option file. * now put them here. * */ /* 2007-01-22 : SKYEYE4ECLIPSE moved to skyeye_config.c */ int skyeye_option_init (skyeye_config_t * config) { /* 2007-01-18 added by Anthony Lee: for new uart device frame */ config->uart.count = 0; atexit(skyeye_uart_cleanup); /*ywc 2005-04-01 */ config->no_dbct = 1; /*default, dbct is off */ //teawater add for new tb manage function 2005.07.10---------------------------- config->tb_tbt_size = 0; #if DBCT config->tb_tbp_size = TB_TBP_DEFAULT; #else config->tb_tbp_size = 0; #endif } int do_dummy_option (skyeye_option_t * this_option, int num_params, const char *params[]) { return 0; }; /* parse "int" parameters. e.g. int=16:17*/ int get_interrupts (char value[], u32 * interrupts) { char *cur = value; char *next = value; int i = 0, end = 0; while ((*next != ':') && (*next != 0)) next++; while (*cur != 0) { if (*next != 0) { *next = '\0'; } else end = 1; interrupts[i] = strtoul (cur, NULL, 0); //printf("%s:%s\n", __FUNCTION__, cur); i++; if ((i > 4) || end == 1) return 0; cur = ++next; while ((*next != ':') && (*next != 0)) next++; } return 0; } /** * setup device option. * all device options may have common parameters. Here we handle these common parameters. * */ int setup_device_option (char *option_name, void *dev_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; struct common_config conf; int i; memset (&conf, 0, sizeof (conf)); conf.type = NULL; conf.name = NULL; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: \"%s\" has wrong parameter \"%s\".\n", option_name, name); if (!strncmp ("type", name, strlen (name))) { conf.type = strdup (value); } else if (!strncmp ("name", name, strlen (name))) { conf.name = strdup (value); } else if (!strncmp ("base", name, strlen (name))) { conf.base = strtoul (value, NULL, 0); } else if (!strncmp ("size", name, strlen (name))) { conf.size = strtoul (value, NULL, 0); } else if (!strncmp ("int", name, strlen (name))) { get_interrupts (value, conf.interrupts); } } setup_device (option_name, &conf, dev_option, skyeye_config.mach); if (conf.type) free (conf.type); if (conf.name) free (conf.name); return 0; } /* defined in skyeye_arch.c */ extern arch_config_t *skyeye_archs[]; int do_arch_option (skyeye_option_t * this_option, int num_params, const char *params[]) { int i; arch_config_t *arch = skyeye_config.arch; char *default_arch = "arm"; for (i = 0; i < MAX_SUPP_ARCH; i++) { if (skyeye_archs[i] == NULL) continue; if (!strncmp (params[0], skyeye_archs[i]->arch_name, MAX_PARAM_NAME)) { skyeye_config.arch = skyeye_archs[i]; SKYEYE_INFO ("arch: %s\n", skyeye_archs[i]->arch_name); return 0; } } SKYEYE_ERR ("Error: Unknowm architecture name \"%s\" or you use low version of skyeye?\n", params[0]); return -1; } int do_cpu_option (skyeye_option_t * this_option, int num_params, const char *params[]) { int ret; if (skyeye_config.arch == NULL) { /* If we don't set arch, we use "arm" as default. */ char *default_arch = "arm"; int i; for (i = 0; i < MAX_SUPP_ARCH; i++) { if (skyeye_archs[i] == NULL) continue; if (!strncmp (default_arch, skyeye_archs[i]->arch_name, MAX_PARAM_NAME)) { skyeye_config.arch = skyeye_archs[i]; SKYEYE_INFO ("arch: %s\n", skyeye_archs[i]->arch_name); } } if (skyeye_config.arch == NULL) { SKYEYE_ERR ("ERROR: No arch option found! Maybe you use low version of skyeye?\n"); skyeye_exit (-1); } } ret = skyeye_config.arch->parse_cpu (params); if (ret < 0) SKYEYE_ERR ("Error: Unkonw cpu name \"%s\"\n", params[0]); return ret; } int do_mach_option (skyeye_option_t * this_option, int num_params, const char *params[]) { int ret; machine_config_t *mach = skyeye_config.mach; ret = skyeye_config.arch->parse_mach (mach, params); if (ret < 0) { SKYEYE_ERR ("Error: Unkonw mach name \"%s\"\n", params[0]); } return ret; } int do_mem_bank_option (skyeye_option_t * this_option, int num_params, const char *params[]) { int ret; ret = skyeye_config.arch->parse_mem (num_params, params); if (ret < 0) { SKYEYE_ERR ("Error: Unkonw mem bank name \"%s\"\n", params[0]); } return ret; } int do_net_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i; struct net_option net_opt; unsigned char mac_addr[6]; unsigned char hip[4]; unsigned char *maddr, *ip; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) { SKYEYE_ERR ("Error: %s has wrong parameter \"%s\".\n", this_option->name, name); return -1; } if (!strncmp ("mac", name, strlen (name))) { sscanf (value, "%x:%x:%x:%x:%x:%x", &mac_addr[0], &mac_addr[1], &mac_addr[2], &mac_addr[3], &mac_addr[4], &mac_addr[5]); memcpy (net_opt.macaddr, mac_addr, 6); } else if (!strncmp ("hostip", name, strlen (name))) { /* FIXME: security problem, don't use sscanf later */ sscanf (value, "%d.%d.%d.%d", &hip[0], &hip[1], &hip[2], &hip[3]); memcpy (net_opt.hostip, hip, 4); } else if (!strncmp ("ethmod", name, strlen (name))) { if (!strncmp ("linux", value, strlen (value))) { net_opt.ethmod = NET_MOD_LINUX; } else if (!strncmp ("tuntap", value, strlen (value))) { net_opt.ethmod = NET_MOD_TUNTAP; } else if (!strncmp ("vnet", value, strlen (value))) { net_opt.ethmod = NET_MOD_VNET; } } } maddr = net_opt.macaddr; ip = net_opt.hostip; printf ("ethmod num=%d, mac addr=%x:%x:%x:%x:%x:%x, hostip=%d.%d.%d.%d\n", net_opt.ethmod, maddr[0], maddr[1], maddr[2], maddr[3], maddr[4], maddr[5], ip[0], ip[1], ip[2], ip[3]); setup_device_option (this_option->name, (void *) &net_opt, num_params, params); return 0; } /** * * energy option */ int do_energy_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, fd; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: energy has wrong parameter \"%s\".\n", name); if (!strncmp ("state", name, strlen (name))) { if (!strncmp ("on", value, strlen (value))) { skyeye_config.energy.energy_prof = 1; SKYEYE_INFO ("energy info: turn on energy!\n"); } else { skyeye_config.energy.energy_prof = 0; SKYEYE_INFO ("energy info: turn off energy!\n"); } } else if (!strncmp ("filename", name, strlen (name))) { strcpy (skyeye_config.energy.filename, value); skyeye_config.energy.filename[strlen (value)] = '\0'; } else if (!strncmp ("logfile", name, strlen (name))) { strcpy (skyeye_config.energy.logfile, value); skyeye_config.energy.logfile[strlen (value)] = '\0'; } } return 0; } /*uart option*/ int do_uart_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; /* 2007-01-18 added by Anthony Lee: for new uart device frame */ /* At default, if none options for uart were found, * the function named "skyeye_read_config()" from "utils/config/skyeye_config.c" would insert * a blank line in order to call this to make the uart simulation by standard input/output. */ struct uart_option uart_opt = {"", "", UART_SIM_STDIO, ""}; int i, only_desc = 0; for (i = 0; i < num_params; i++) { if (split_param(params[i], name, value) < 0) SKYEYE_ERR("Error: uart has wrong parameter \"%s\".\n", name); if (!strncmp("converter", name, strlen(name))) { memcpy(&uart_opt.converter[0], value, strlen(value) + 1); } if (!strncmp("mod", name, strlen(name))) { if (!strncmp ("stdio", value, strlen (value))) uart_opt.mod = UART_SIM_STDIO; else if (!strncmp ("pipe", value, strlen (value))) uart_opt.mod = UART_SIM_PIPE; else if (!strncmp ("net", value, strlen (value))) uart_opt.mod = UART_SIM_NET; } /* for old style */ if (!strncmp("fd_in", name, strlen(name))) { uart_opt.mod = UART_SIM_PIPE; memcpy(&uart_opt.desc_in[0], value, strlen(value) + 1); } else if (!strncmp("fd_out", name, strlen(name))) { uart_opt.mod = UART_SIM_PIPE; memcpy(&uart_opt.desc_out[0], value, strlen(value) + 1); } /* new style */ if (!strncmp("desc", name, strlen(name))) { only_desc = 1; memcpy(&uart_opt.desc_in[0], value, strlen(value) + 1); uart_opt.desc_out[0] = '\0'; } else if (only_desc == 0) { if (!strncmp("desc_in", name, strlen(name))) memcpy(&uart_opt.desc_in[0], value, strlen(value) + 1); else if (!strncmp("desc_out", name, strlen(name))) memcpy(&uart_opt.desc_out[0], value, strlen(value) + 1); } } skyeye_uart_setup(&uart_opt); return 0; } /* Anthony Lee 2006-09-07 */ static int lcd_mod_is_valid(int mod) { #ifdef GTK_LCD if(mod == LCD_MOD_GTK) return 1; #endif #ifdef WIN32_LCD if(mod == LCD_MOD_WIN32) return 1; #endif #ifdef BEOS_LCD if(mod == LCD_MOD_BEOS) return 1; #endif return 0; } /* Anthony Lee 2006-09-07 */ static int lcd_valid_mod(void) { #ifdef GTK_LCD return LCD_MOD_GTK; #else #ifdef WIN32_LCD return LCD_MOD_WIN32; #else #ifdef BEOS_LCD return LCD_MOD_BEOS; #else return LCD_MOD_NONE; #endif #endif #endif } /*chy 2004-03-11 lcd option*/ int do_lcd_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; struct lcd_option lcd_opt; int i, fd; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: lcd has wrong parameter \"%s\".\n", name); if (!strncmp ("mod", name, strlen (name))) { if (!strncmp ("gtk", value, strlen (value))) { lcd_opt.mod = LCD_MOD_GTK; } else if (!strncmp ("qt", value, strlen (value))) { lcd_opt.mod = LCD_MOD_QT; } else if (!strncmp ("x", value, strlen (value))) { lcd_opt.mod = LCD_MOD_X; } else if (!strncmp ("sdl", value, strlen (value))) { lcd_opt.mod = LCD_MOD_SDL; } else if (!strncmp ("win32", value, strlen (value))) { lcd_opt.mod = LCD_MOD_WIN32; } else if (!strncmp ("beos", value, strlen (value))) { lcd_opt.mod = LCD_MOD_BEOS; } } } if (lcd_mod_is_valid(lcd_opt.mod) == 0) lcd_opt.mod = lcd_valid_mod(); if (lcd_opt.mod == LCD_MOD_NONE) return 0; setup_device_option (this_option->name, (void *) &lcd_opt, num_params, params); return 0; } /*ywc 2005-04-01 dbct option*/ int do_dbct_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, fd; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: dbct has wrong parameter \"%s\".\n", name); if (!strncmp ("state", name, strlen (name))) { if (!strncmp ("on", value, strlen (value))) { skyeye_config.no_dbct = 0; #ifndef NO_DBCT SKYEYE_INFO ("dbct info: turn on dbct!\n"); #else SKYEYE_INFO ("dbct info: Note: DBCT not compiled in. This option will be ignored\n"); #endif } else { skyeye_config.no_dbct = 1; SKYEYE_INFO ("dbct info: turn off dbct!\n"); } } //teawater add for new tb manage function 2005.07.10---------------------------- if (!strncmp ("tbt", name, strlen (name))) { skyeye_config.tb_tbt_size = strtoul (value, NULL, 0); } if (!strncmp ("tbp", name, strlen (name))) { skyeye_config.tb_tbp_size = strtoul (value, NULL, 0); } } return 0; } //chy:2003-08-20 do_log option int do_log_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, fd, logon, memlogon; unsigned long long start, end, length; /*2004-08-09 chy init skyeye_config.log */ skyeye_config.log.log_fd = 0; skyeye_config.log.logon = 0; skyeye_config.log.memlogon = 0; skyeye_config.log.start = 0; skyeye_config.log.end = 0; skyeye_config.log.length = 0; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("log_info: Error: log has wrong parameter \"%s\".\n", name); if (!strncmp ("logon", name, strlen (name))) { sscanf (value, "%d", &logon); if (logon != 0 && logon != 1) SKYEYE_ERR ("log_info: Error logon value %d\n", logon); if (logon == 1) { SKYEYE_INFO ("log_info: log is on.\n"); } else { SKYEYE_INFO ("log_info: log is off.\n"); } skyeye_config.log.logon = logon; } else if (!strncmp ("memlogon", name, strlen (name))) { sscanf (value, "%d", &memlogon); if (memlogon != 0 && memlogon != 1) SKYEYE_ERR ("log_info: Error logon value %d\n", memlogon); if (memlogon == 1) { SKYEYE_INFO ("log_info: memory klog is on.\n"); } else { SKYEYE_INFO ("log_info: memory log is off.\n"); } skyeye_config.log.memlogon = memlogon; } else if (!strncmp ("logfile", name, strlen (name))) { if ((skyeye_logfd = fopen (value, "w+")) == NULL) { //SKYEYE_DBG("SkyEye Error when open log file %s\n", value); perror ("SkyEye: Error when open log file: "); skyeye_exit (-1); } skyeye_config.log.log_fd = skyeye_logfd; SKYEYE_INFO ("log_info:log file is %s, fd is 0x%x\n", value, skyeye_logfd); } else if (!strncmp ("start", name, strlen (name))) { start = strtoul (value, NULL, 0); skyeye_config.log.start = start; SKYEYE_INFO ("log_info: log start clock %llu\n", start); } else if (!strncmp ("end", name, strlen (name))) { end = strtoul (value, NULL, 0); skyeye_config.log.end = end; SKYEYE_INFO ("log_info: log end clock %llu\n", end); } else if (!strncmp ("length", name, strlen (name))) { sscanf (value, "%llu", &length); skyeye_config.log.length = length; SKYEYE_INFO ("log_info: log instr length %llu\n", length); } else SKYEYE_ERR ("Error: Unkonw cpu name \"%s\"\n", params[0]); } return 0; } /* * we can add this option using: * step_disassemble:on[ON|1] for open this option * step_disassemble:off[OFF|0] for disable this option * oyangjian add here */ int do_step_disassemble_option (skyeye_option_t * this_option, int num_params, const char *params[]) { int i; for (i = 0; i < num_params; i++) { printf ("step_disassemble state:%s\n", params[0]); if (!params[0]) { SKYEYE_ERR ("Error :usage: step_disassemble:on[off]"); return -1; } if (!strncmp (params[0], "on", 2) || !strncmp (params[0], "ON", 2)) { skyeye_config.can_step_disassemble = 1; return 0; } else if (!strncmp (params[0], "off", 3) || !strncmp (params[0], "OFF", 3)) { skyeye_config.can_step_disassemble = 0; return 0; } } SKYEYE_ERR ("Error: Unkonw cpu name \"%s\"\n", params[0]); return -1; } int do_flash_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; struct flash_option flash_opt; int i, fd; memset(&flash_opt, 0, sizeof(struct flash_option)); for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: flash has wrong parameter \"%s\".\n", name); if (!strncmp("dump", name, strlen(name))) { memcpy(&flash_opt.dump[0], value, strlen(value) + 1); } } SKYEYE_INFO ("flash: dump %s\n", flash_opt.dump[0] == 0 ? "none" : flash_opt.dump); setup_device_option (this_option->name, (void *) &flash_opt, num_params, params); return 0; } int do_nandflash_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; struct flash_option flash_opt; int i, fd; memset(&flash_opt, 0, sizeof(struct flash_option)); for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: flash has wrong parameter \"%s\".\n", name); if (!strncmp("dump", name, strlen(name))) { memcpy(&flash_opt.dump[0], value, strlen(value) + 1); } } SKYEYE_INFO ("nandflash: dump %s\n", flash_opt.dump[0] == 0 ? "none" : flash_opt.dump); setup_device_option (this_option->name, (void *) &flash_opt, num_params, params); return 0; } int do_touchscreen_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; struct touchscreen_option ts_opt; int i; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: touchscreen has wrong parameter \"%s\".\n", name); /* TODO */ } setup_device_option (this_option->name, (void*)&ts_opt, num_params, params); return 0; } int do_sound_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; struct sound_option snd_opt; int i; memset (&snd_opt, 0, sizeof(snd_opt)); for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: sound has wrong parameter \"%s\".\n", name); if (!strncmp ("mod", name, strlen (name))) { if (!strncmp ("pcm", value, strlen (value))) { snd_opt.mod = 1; /* SOUND_SIM_PCM */ } } if (!strncmp ("channels", name, strlen (name))) { sscanf (value, "%d", &snd_opt.channels); } if (!strncmp ("bits_per_sample", name, strlen (name))) { sscanf (value, "%d", &snd_opt.bits_per_sample); } if (!strncmp ("samples_per_sec", name, strlen (name))) { sscanf (value, "%d", &snd_opt.samples_per_sec); } } if (snd_opt.mod == 0) return 0; SKYEYE_INFO ("sound: channels:%d, bits_per_sample:%d, samples_per_sec:%d.\n", snd_opt.channels, snd_opt.bits_per_sample, snd_opt.samples_per_sec); setup_device_option (this_option->name, (void*)&snd_opt, num_params, params); return 0; } //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED int do_dbct_test_speed_sec(struct skyeye_option_t *this_opion, int num_params, const char *params[]) { if (num_params != 1) { goto error_out; } errno = 0; skyeye_config.dbct_test_speed_sec = strtol(params[0], NULL, 10); if (errno == ERANGE) { goto error_out; } printf("dbct_test_speed_sec %ld\n", skyeye_config.dbct_test_speed_sec); error_out: SKYEYE_ERR("Error :usage: step_disassemble: dbct_test_speed_sec\n"); return(-1); } #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- /* set values for some register */ int do_regfile_option (skyeye_option_t * this_option, int num_params, const char *params[]) { if(skyeye_config.arch && skyeye_config.arch->parse_regfile) skyeye_config.arch->parse_regfile(num_params, params); else SKYEYE_WARNING("regfile option is not implemented by current arch\n"); return 0; } /* set load address for elf image */ int do_load_addr_option (skyeye_option_t * this_option, int num_params, const char *params[]) { int i; char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; extern unsigned long load_base; extern unsigned long load_mask; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: sound has wrong parameter \"%s\".\n", name); if (!strncmp ("base", name, strlen (name))) { sscanf (value, "%x", &load_base); } else if (!strncmp ("mask", name, strlen (name))) { sscanf (value, "%x", &load_mask); } else SKYEYE_ERR ("Error: Unkonw load_addr option \"%s\"\n", params[i]); } printf("Your elf file will be load to: base address=0x%x,mask=0x%x\n", load_base, load_mask); return 0; } /** * code coverage option */ int do_code_cov_option (skyeye_option_t * this_option, int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, start, end; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: code coverage has wrong parameter \"%s\".\n", name); if (!strncmp ("state", name, strlen (name))) { if (!strncmp ("on", value, strlen (value))) { skyeye_config.code_cov.prof_on = 1; SKYEYE_INFO ("code coverage info: turn on profiling!\n"); } else { skyeye_config.code_cov.prof_on = 0; SKYEYE_INFO ("code coverage info: turn off profiling!\n"); } } else if (!strncmp ("filename", name, strlen (name))) { strcpy (skyeye_config.code_cov.prof_filename, value); skyeye_config.code_cov.prof_filename[strlen (value)] = '\0'; } else if (!strncmp ("start", name, strlen (name))) { start = strtoul (value, NULL, 0); skyeye_config.code_cov.start = start; SKYEYE_INFO ("log_info: log start clock %llu\n", start); } else if (!strncmp ("end", name, strlen (name))) { end = strtoul (value, NULL, 0); skyeye_config.code_cov.end = end; SKYEYE_INFO ("log_info: log end clock %llu\n", end); } } return 0; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_defs.h���������������������������������������������������������0000644�0001750�0000144�00000002650�10572524543�017340� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_defs.h - some nessisary header files for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/18/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __SKYEYE_DEFS_H__ #define __SKYEYE_DEFS_H__ #include <stdio.h> #include <stdlib.h> #include <errno.h> #include <sys/types.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include <unistd.h> #include <errno.h> #include <sys/stat.h> #include <fcntl.h> #include <stdint.h> #ifndef FALSE #define FALSE 0 #define TRUE 1 #endif #define LOW 0 #define HIGH 1 #define LOWHIGH 1 #define HIGHLOW 2 #endif ����������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/config/skyeye_options.h������������������������������������������������������0000644�0001750�0000144�00000003541�11006365156�020106� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_option.h - definitions of the device options structures. Copyright (C) 2004 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 05/16/2004 initial version * * walimis <wlm@student.dlut.edu.cn> * */ #ifndef __SKYEYE_OPTION_H_ #define __SKYEYE_OPTION_H_ #include "skyeye.h" #include "skyeye_device.h" struct uart_option { /* 2007-01-18 by Anthony Lee: for new uart device frame */ char desc_in[MAX_STR_NAME]; /* description of device, such as path etc. */ char desc_out[MAX_STR_NAME]; /* description of device, such as path etc. */ int mod; char converter[MAX_STR_NAME]; }; struct timer_option { }; struct net_option { unsigned char macaddr[6]; unsigned char hostip[4]; int ethmod; }; struct lcd_option { /* display mode. e.g. gtk, qt, X, sdl */ int mod; int width; int height; int depth; }; struct flash_option { char dump[MAX_STR_NAME]; }; struct touchscreen_option { }; struct sound_option { int mod; int channels; int bits_per_sample; int samples_per_sec; }; struct code_cov_option { int prof_on; char prof_filename[MAX_STR_NAME]; int start; int end; }; #endif /*__SKYEYE_OPTION_H_ */ ���������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/tools/�����������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014526� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/��������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015176� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/gettimeofday.c������������������������������������������������������0000644�0001750�0000144�00000002100�10572560524�020032� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* gettimeofday.c - portable gettimeofday function for skyeye Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/03/2007 initial version by Anthony Lee */ #include "gettimeofday.h" #ifndef HAVE_GETTIMEOFDAY #ifdef __MINGW32__ #include "./win32/gettimeofday.c" #endif /* __MINGW32__ */ #endif /* !HAVE_GETTIMEOFDAY */ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/���������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�016126� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/stdint.h�������������������������������������������������������0000644�0001750�0000144�00000000360�10600011124�017574� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef __SKYEYE_PORTABLE_BEOS_STDINT_H_ #define __SKYEYE_PORTABLE_BEOS_STDINT_H_ #include <inttypes.h> #include <limits.h> #ifndef INT32_MAX #define INT32_MAX INT_MAX #endif /* INT32_MAX */ #endif /* __SKYEYE_PORTABLE_BEOS_STDINT_H_*/ ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/tap_driver/����������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�020265� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/tap_driver/Makefile��������������������������������������������0000644�0001750�0000144�00000002167�10600011124�021724� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������ifneq ($(OSTYPE),beos) ### for cross-compile CC = /usr/local/bin/i586-beos-gcc KERNEL = /usr/local/i586-beos/lib/_KERNEL_ else KERNEL = /boot/develop/lib/x86/_KERNEL_ endif EXTRA_CFLAGS ?= CFLAGS = -O3 -no-fpic $(EXTRA_CFLAGS) OBJECTS = skyeye_tap.o skyeye_tap : $(OBJECTS) $(CC) -nostdlib $^ -o $@ $(KERNEL) all: skyeye_tap clean: -rm -f Makefile.dep -rm -f *.o -rm -f skyeye_tap ifeq ($(OSTYPE),beos) install: skyeye_tap -mkdir -p /boot/home/config/add-ons/kernel/drivers/bin -cp -f ./skyeye_tap /boot/home/config/add-ons/kernel/drivers/bin/skyeye_tap -mkdir -p /boot/home/config/add-ons/kernel/drivers/dev/net -ln -sf ../../bin/skyeye_tap /boot/home/config/add-ons/kernel/drivers/dev/net/skyeye_tap uninstall: -rm -f /boot/home/config/add-ons/kernel/drivers/dev/net/skyeye_tap -rm -f /boot/home/config/add-ons/kernel/drivers/bin/skyeye_tap else install: @echo "*** You don't need this when cross-compile." uninstall: @echo "*** You don't need this when cross-compile." endif .SUFFIXES: .c .o .c.o: $(CC) $(CFLAGS) -c $< -o $@ Makefile.dep: -$(CC) $(CFLAGS) -MM skyeye_tap.c > Makefile.dep -include Makefile.dep ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/tap_driver/README����������������������������������������������0000644�0001750�0000144�00000004652�10560650771�021173� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������SkyEye TAP --- A kernel driver for SkyEye's net simulation on BeOS Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Compile & Install the driver ============================ - Run the command "make install" within this directory to compile and install the driver. - Restart the network, then you'll get "/dev/net/skyeye_tap/0" on your system. Special on BeOS R5.0.x ====================== - You should get an addon for net_server, see below. - On BeOS R5.0.x, there are no "ifconfig", so you must manually set the IP address and net mask to be the correct value, for example: 10.0.0.1/255.255.255.0 How to compile the addon for net_server on BeOS R5.0.x ====================================================== - First you must download "Be Sample Code" from http://www.bebits.com/app/3019. - Then replace the lines like below in "sample-code/drivers/EtherPCI/Addon/ne2000pci.cpp" static const char TITLE[] = "Novell NE2000 compatible adapter (PCI) Sample"; static const char CONFIG[] = "ne2000pci"; static const char LINK[] = "/dev/net/etherpci"; with static const char TITLE[] = "SkyEye TAP Driver"; static const char CONFIG[] = "skyeye_tap"; static const char LINK[] = "/dev/net/skyeye_tap"; - Third, compile the project and rename the target's name("ne2000pci") to be "skyeye_tap". - At last, copy or move "skyeye_tap" that you renamed to "/boot/beos/system/add-ons/net_server/skyeye_tap" - Restart the net server and fit the IP/mask to be correct. How to write application like what I did with tuntap driver on Linux ==================================================================== - Please remember that the codes isn't comed from Linux, so there are diffrent. - See "device/net/skyeye_net_tap_beos.c" to find out how to write it. ��������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/tap_driver/skyeye_tap.h����������������������������������������0000644�0001750�0000144�00000003373�10560650771�022640� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_tap.h - A kernel driver for SkyEye's net simulation on BeOS Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 02/01/2007 written by Anthony Lee */ #ifndef __SKYEYE_TAP_BEOS_DRIVER_H__ #define __SKYEYE_TAP_BEOS_DRIVER_H__ #include <drivers/Drivers.h> #define SKYEYE_TAP_RX_PORT_NAME "SkyEye_Tap_RX" #define SKYEYE_TAP_TX_PORT_NAME "SkyEye_Tap_TX" #define SKYEYE_TAP_RX_PORT_FOR_USER SKYEYE_TAP_TX_PORT_NAME #define SKYEYE_TAP_TX_PORT_FOR_USER SKYEYE_TAP_RX_PORT_NAME #define SKYEYE_TAP_PORT_MSG_CODE 'snet' #define SKYEYE_TAP_DEVICE_NAME "net/skyeye_tap/0" #define SKYEYE_TAP_DEVICE "/dev/" SKYEYE_TAP_DEVICE_NAME #define SKYEYE_TAP_FRAME_SIZE 1560 enum { ETHER_GETADDR = B_DEVICE_OP_CODES_END, /* get ethernet address */ ETHER_INIT, /* set irq and port */ ETHER_NONBLOCK, /* set/unset nonblocking mode */ ETHER_ADDMULTI, /* add multicast addr */ ETHER_REMMULTI, /* rem multicast addr */ ETHER_SETPROMISC, /* set promiscuous */ ETHER_GETFRAMESIZE, /* get frame size */ }; #endif /* __SKYEYE_TAP_BEOS_DRIVER_H__ */ ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/tap_driver/skyeye_tap.c����������������������������������������0000644�0001750�0000144�00000024044�10561755240�022627� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_tap.c - A kernel driver for SkyEye's net simulation on BeOS Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 02/01/2007 written by Anthony Lee */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <stdarg.h> #include <bsd_mem.h> #include <support/SupportDefs.h> #include <kernel/OS.h> #include <drivers/KernelExport.h> #include "skyeye_tap.h" #define SKYEYE_TAP_DEBUG 0 #if SKYEYE_TAP_DEBUG #define DEBUG(x...) dprintf("[SKYEYE_TAP]: " __FUNCTION__ " --- " x) #else #define DEBUG(x...) (void)0 #endif #define PACKET_QUEUE_LENGTH 256 #define SKYEYE_TAP_MAC_ADDRESS "SkyEye" #define MAX_MULTI 32 static char *skyeye_tap_devs[] = {SKYEYE_TAP_DEVICE_NAME, NULL}; static int32 skyeye_tap_status = 0; typedef uint8 (mac_address)[6]; typedef struct skyeye_tap { int nonblocking; /* non-blocking mode */ int promisc; /* promisc mode */ uint32 nmulti; /* number of multicast addresses */ mac_address multi[MAX_MULTI]; /* multicast addresses */ sem_id ioLocker; /* io locker */ bool interrupted; /* interrupted system call */ int32 inrw; /* in read or write function */ port_id rxPort; /* port for receiving data from user */ port_id txPort; /* port for sending data to user */ } skyeye_tap; static status_t domulti(skyeye_tap *dev, uint8 *addr, bool add) { uint32 i, nmulti; status_t retVal; if((retVal = acquire_sem(dev->ioLocker)) != B_NO_ERROR) return retVal; if((nmulti = dev->nmulti) < MAX_MULTI || !add) { for(i = 0; i < nmulti; i++) { if(memcmp(&(dev->multi[i]), addr, 6) == 0) break; } if(i == nmulti && add) { memcpy(&(dev->multi[i]), addr, 6); dev->nmulti++; } else if(i < nmulti && !add) { if(i != nmulti - 1) memcpy(&dev->multi[i], &dev->multi[i + 1], (nmulti - i - 1) * 6); dev->nmulti--; } } else { retVal = B_ERROR; } release_sem_etc(dev->ioLocker, 1, 0); return retVal; } static bool check_packet(skyeye_tap *dev, uint8 *addr) { int i; if(addr == NULL) return false; if(dev->promisc) return true; if(memcmp(addr, SKYEYE_TAP_MAC_ADDRESS, 6) == 0) return true; if(memcmp(addr, "\xff\xff\xff\xff\xff\xff", 6) == 0) return true; for(i = 0; i < dev->nmulti; i++) if(memcmp(addr, &dev->multi[i], 6) == 0) return true; return false; } static int recv_packet(skyeye_tap *dev, void *buf, size_t buflen) { ssize_t bufSize = 0; int32 code; if(buf == NULL || acquire_sem(dev->ioLocker) != B_NO_ERROR) return -1; if((bufSize = port_buffer_size_etc(dev->rxPort, B_TIMEOUT, 1000)) >= 0) { if(read_port_etc(dev->rxPort, &code, buf, buflen, B_TIMEOUT, 1000) != bufSize || code != SKYEYE_TAP_PORT_MSG_CODE || buflen < 6 || !check_packet(dev, (uint8*)buf)) { DEBUG("Invalid packet, drop it.(code: 0x%x, buflen: %u, bufSize: %u)\n", code, buflen, bufSize); bufSize = 0; } else { DEBUG("Read %d bytes.\n", bufSize); } } else { DEBUG("port_buffer_size_etc() return B_GENERAL_ERROR_BASE+0x%x.\n", bufSize - B_GENERAL_ERROR_BASE); } release_sem_etc(dev->ioLocker, 1, 0); return(bufSize >= 0 && bufSize <= SKYEYE_TAP_FRAME_SIZE ? (int)bufSize : 0); } static int send_packet(skyeye_tap *dev, const void *buf, size_t buflen) { if(buf == NULL || buflen < 0 || buflen > SKYEYE_TAP_FRAME_SIZE) return -1; if(write_port_etc(dev->txPort, SKYEYE_TAP_PORT_MSG_CODE, buf, buflen, B_TIMEOUT, 1000) == B_OK) return (int)buflen; return 0; } static status_t open_hook(const char *name, uint32 flags, void **cookie) { skyeye_tap *dev; *cookie = NULL; /* device is not SkyEye Tap */ if(strcmp(skyeye_tap_devs[0], name) != 0) return EINVAL; /* open once */ if(atomic_or(&skyeye_tap_status, 1) & 1) return B_BUSY; /* allocate storage for the cookie */ if((*cookie = (dev = (skyeye_tap*)malloc(sizeof(skyeye_tap)))) == NULL) { atomic_and(&skyeye_tap_status, ~1); DEBUG("Failed to allocate memory for device!\n"); return B_NO_MEMORY; } bzero(dev, sizeof(skyeye_tap)); /* setup the cookie */ dev->rxPort = dev->txPort = -1; dev->ioLocker = -1; dev->interrupted = false; dev->inrw = 0; dev->promisc = 1; if((dev->rxPort = create_port(PACKET_QUEUE_LENGTH, SKYEYE_TAP_RX_PORT_NAME)) < 0 || (dev->txPort = create_port(PACKET_QUEUE_LENGTH, SKYEYE_TAP_TX_PORT_NAME)) < 0 || (dev->ioLocker = create_sem(1, "skyeye_tap_io")) < 0 || set_port_owner(dev->rxPort, B_SYSTEM_TEAM) != B_OK || set_port_owner(dev->txPort, B_SYSTEM_TEAM) != B_OK || set_sem_owner(dev->ioLocker, B_SYSTEM_TEAM) != B_OK) { if(dev->rxPort >= 0) delete_port(dev->rxPort); if(dev->txPort >= 0) delete_port(dev->txPort); if(dev->ioLocker >= 0) delete_sem(dev->ioLocker); free(dev); atomic_and(&skyeye_tap_status, ~1); DEBUG("Failed to create port/sem for RX/TX!\n"); *cookie = NULL; return B_ERROR; } DEBUG("dev = %x\n", dev); return B_NO_ERROR; } static status_t close_hook(void *data) { skyeye_tap *dev = (skyeye_tap*)data; DEBUG("dev = %x\n", dev); /* force pending reads and writes to terminate */ while(true) {if(acquire_sem(dev->ioLocker) == B_NO_ERROR) break;} dev->interrupted = true; close_port(dev->rxPort); close_port(dev->txPort); release_sem_etc(dev->ioLocker, 1, 0); while(dev->inrw != 0) { snooze(1000000); DEBUG("waiting for read/write to finish\n"); } atomic_and(&skyeye_tap_status, ~1); delete_sem(dev->ioLocker); return B_NO_ERROR; } static status_t free_hook(void *data) { DEBUG("dev = %x\n", data); free(data); return B_ERROR; } static status_t control_hook(void *data, uint32 msg, void *buf, size_t len) { skyeye_tap *dev = (skyeye_tap*)data; unsigned int sz; if(data == NULL) return B_ERROR; switch(msg) { case ETHER_INIT: DEBUG("ETHER_INIT\n"); return B_NO_ERROR; case ETHER_GETADDR: if(buf == NULL) return B_ERROR; DEBUG("GET_ADDR\n"); memcpy(buf, SKYEYE_TAP_MAC_ADDRESS, 6); return B_NO_ERROR; case ETHER_NONBLOCK: if(buf == NULL || acquire_sem(dev->ioLocker) != B_NO_ERROR) return B_ERROR; dev->nonblocking = *((int*)buf); DEBUG("NON_BLOCK %d\n", dev->nonblocking); release_sem_etc(dev->ioLocker, 1, 0); return B_NO_ERROR; case ETHER_ADDMULTI: case ETHER_REMMULTI: if(buf == NULL) return B_ERROR; DEBUG("DO_MULTI(%s) - %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", msg == ETHER_ADDMULTI ? "add" : "remove", *((uint8*)buf), *((uint8*)buf + 1), *((uint8*)buf + 2), *((uint8*)buf + 3), *((uint8*)buf + 4), *((uint8*)buf + 5)); return(domulti(data, (uint8*)buf, msg == ETHER_ADDMULTI)); case ETHER_SETPROMISC: if(buf == NULL || acquire_sem(dev->ioLocker) != B_NO_ERROR) return B_ERROR; dev->promisc = *((int*)buf); DEBUG("PROMISC %x\n", dev->promisc); release_sem_etc(dev->ioLocker, 1, 0); return B_NO_ERROR; case ETHER_GETFRAMESIZE: if(buf == NULL) return B_ERROR; sz = SKYEYE_TAP_FRAME_SIZE; DEBUG("GET_FRAMESIZE %u\n", sz); memcpy(buf, &sz, sizeof(sz)); return B_NO_ERROR; default: break; } return B_ERROR; } static status_t read_hook(void *data, off_t pos, void *buf, size_t *len) { skyeye_tap *dev = (skyeye_tap*)data; size_t buflen = *len; int packet_len = 0; status_t retVal = B_NO_ERROR; atomic_add(&dev->inrw, 1); while(true) { packet_len = recv_packet(dev, buf, buflen); if(acquire_sem(dev->ioLocker) != B_NO_ERROR) { atomic_add(&dev->inrw, -1); return B_INTERRUPTED; } if(dev->interrupted) { retVal = B_INTERRUPTED; break; } if(packet_len == 0 && dev->nonblocking == 0) { release_sem_etc(dev->ioLocker, 1, 0); snooze(100000); continue; } if(packet_len < 0) retVal = B_ERROR; break; } release_sem_etc(dev->ioLocker, 1, 0); atomic_add(&dev->inrw, -1); *len = (int)packet_len; return retVal; } static status_t write_hook(void *data, off_t pos, const void *buf, size_t *len) { skyeye_tap *dev = (skyeye_tap*)data; size_t buflen = *len; int packet_len = 0; status_t retVal = B_NO_ERROR; atomic_add(&dev->inrw, 1); while(true) { packet_len = send_packet(dev, buf, buflen); if(acquire_sem(dev->ioLocker) != B_NO_ERROR) { atomic_add(&dev->inrw, -1); return B_INTERRUPTED; } if(dev->interrupted) { retVal = B_INTERRUPTED; break; } if(packet_len == 0 && dev->nonblocking == 0) { release_sem_etc(dev->ioLocker, 1, 0); snooze(100000); continue; } if(packet_len < 0) retVal = B_ERROR; break; } release_sem_etc(dev->ioLocker, 1, 0); atomic_add(&dev->inrw, -1); *len = (size_t)packet_len; return retVal; } /* prototypes */ static device_hooks hooks = { open_hook, /* -> open entry point */ close_hook, /* -> close entry point */ free_hook, /* -> free entry point */ control_hook, /* -> control entry point */ read_hook, /* -> read entry point */ write_hook, /* -> write entry point */ NULL, /* -> select entry point */ NULL, /* -> deselect entry point */ NULL, /* -> readv */ NULL /* -> writev */ }; /* Initalize hardware */ _EXPORT status_t init_hardware(void) { return B_NO_ERROR; } /* Initalize driver */ _EXPORT status_t init_driver() { return B_NO_ERROR; } /* Uninitalize driver */ _EXPORT void uninit_driver(void) { } /* Publish devices */ _EXPORT const char** publish_devices(void) { return((const char **)skyeye_tap_devs); } /* Device hooks */ _EXPORT device_hooks *find_device(const char *name) { if(strcmp(skyeye_tap_devs[0], name) == 0) return(&hooks); return NULL; } _EXPORT int32 api_version = B_CUR_DRIVER_API_VERSION; _EXPORT void suspend_driver(void) { } _EXPORT void wake_driver(void) { } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/beos/usleep.c�������������������������������������������������������0000644�0001750�0000144�00000001747�10572524543�017617� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* usleep.c - portable usleep function for skyeye on BeOS Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/03/2007 written by Anthony Lee */ #include <kernel/OS.h> #include "utils/portable/usleep.h" int usleep(unsigned long usec) { snooze((bigtime_t)usec); return 0; } �������������������������skyeye-1.2.5_REL/utils/portable/beos/mman.c���������������������������������������������������������0000644�0001750�0000144�00000004402�10607460064�017235� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mman.c - portable mmap/munmap function for skyeye on BeOS Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 04/12/2007 Written by Anthony Lee */ #include <sys/types.h> #include <sys/stat.h> #include <unistd.h> #include <kernel/OS.h> #include "portable/mman.h" int getpagesize(void) { return B_PAGE_SIZE; } void* mmap(void *addr, size_t length, int prot, int flags, int fd, off_t offset) { area_id area; struct stat stat; ssize_t nBytes = 0, nRead; void *retVal = NULL; if ((flags & (MAP_FIXED | MAP_SHARED)) || ((prot & PROT_WRITE) && fd != -1) || length == 0) return MAP_FAILED; length = (length + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1); if ((area = create_area("none", &retVal, B_ANY_ADDRESS, length, B_NO_LOCK, B_READ_AREA | B_WRITE_AREA)) < 0) return MAP_FAILED; if (fd != -1) { if (fstat(fd, &stat) != 0 || offset >= stat.st_size || lseek(fd, offset, SEEK_SET) == (off_t)-1) goto err; while (nBytes < (ssize_t)length) { offset = lseek(fd, 0, SEEK_CUR); if (offset == (off_t)-1 || offset >= stat.st_size) break; nRead = read(fd, (void*)((char*)retVal + nBytes), length); if (nRead == -1) { nBytes = -1; break; } else { nBytes += nRead; } } if (nBytes == -1) goto err; } goto exit; err: delete_area(area); retVal = NULL; exit: return (retVal == NULL ? MAP_FAILED : retVal); } int munmap(void *addr, size_t length) { area_id area; if (addr == NULL || addr == MAP_FAILED) return -1; if ((area = area_for(addr)) < 0) return -1; return (delete_area(area) != B_OK ? -1 : 0); } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/mman.h��������������������������������������������������������������0000644�0001750�0000144�00000003323�10557622723�016321� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mman.h - portable mmap/munmap function for skyeye Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/30/2007 initial version by Anthony Lee */ #ifndef __SKYEYE_PORTABLE_MMAN_H__ #define __SKYEYE_PORTABLE_MMAN_H__ /* * The mmap/munmap function just for malloc large memory for skyeye. * When you found that the system don't support the mmap/munmap function, * please follow the mman.c to see how to write the portable function. */ #if !(defined(__MINGW32__) || defined(__BEOS__)) #include <sys/mman.h> #include <unistd.h> #define HAVE_MMAP_AND_MUNMAP #else #include <sys/types.h> enum { PROT_NONE = 0, PROT_EXEC = 1, PROT_READ = 2, PROT_WRITE = 4, }; enum { MAP_PRIVATE = 0, MAP_FIXED = 1, MAP_SHARED = 2, MAP_ANONYMOUS = 4, }; #define MAP_FAILED ((void*)-1) int getpagesize(void); void* mmap(void *addr, size_t length, int prot, int flags, int fd, off_t offset); int munmap(void *addr, size_t length); #endif #endif /* __SKYEYE_PORTABLE_MMAN_H__ */ �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/usleep.h������������������������������������������������������������0000644�0001750�0000144�00000002165�10572524543�016667� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* usleep.h - portable usleep function for skyeye Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/03/2007 initial version by Anthony Lee */ #ifndef __SKYEYE_USLEEP_H__ #define __SKYEYE_USLEEP_H__ #if !(defined(__MINGW32__) || defined(__BEOS__)) #include <unistd.h> #define HAVE_USLEEP #else int usleep(unsigned long usec); #endif #endif /* __SKYEYE_USLEEP_H__ */ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/win32/��������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�016140� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/win32/gettimeofday.c������������������������������������������������0000644�0001750�0000144�00000002531�10572524543�021005� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* gettimeofday.c - portable gettimeofday function for skyeye on Win32 Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/03/2007 written by Anthony Lee */ #include <windows.h> #include "utils/portable/gettimeofday.h" int gettimeofday(struct timeval *tv, struct timezone *tz) { FILETIME CurrentTime; __int64 cur_time; if(tv == NULL || tz != NULL) return -1; GetSystemTimeAsFileTime(&CurrentTime); cur_time = ((__int64)CurrentTime.dwHighDateTime << 32) + (__int64)CurrentTime.dwLowDateTime; cur_time -= 116444736000000000LL; cur_time /= 10LL; tv->tv_sec = (cur_time / 1000000LL); tv->tv_usec = (cur_time % 1000000LL); return 0; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/win32/usleep.c������������������������������������������������������0000644�0001750�0000144�00000002415�10572524543�017622� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* usleep.c - portable usleep function for skyeye on Win32 Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/03/2007 written by Anthony Lee */ #include <windows.h> #include "utils/portable/usleep.h" int usleep(unsigned long usec) { HANDLE timer = NULL; LARGE_INTEGER due; timer = CreateWaitableTimer(NULL, TRUE, NULL); if(timer == NULL) return -1; due.QuadPart = (-((__int64)usec)) * 10LL; if(!SetWaitableTimer(timer, &due, 0, NULL, NULL, 0)) { CloseHandle(timer); return -1; } WaitForSingleObject(timer, INFINITE); CloseHandle(timer); return 0; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/win32/mman.c��������������������������������������������������������0000644�0001750�0000144�00000003763�10607460064�017260� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mman.c - portable mmap/munmap function for skyeye on Win32 Copyright (C) 2007 Anthony Lee <don.anthony.lee+program@gmail.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 04/12/2007 Written by Anthony Lee */ #include <windows.h> #include "portable/mman.h" int getpagesize(void) { return 1024; } void* mmap(void *addr, size_t length, int prot, int flags, int fd, off_t offset) { HANDLE handle, file; DWORD nRead = 0; void *retVal = NULL; if ((flags & (MAP_FIXED | MAP_SHARED)) || ((prot & PROT_WRITE) && fd != -1) || !(fd == -1 || (file = (HANDLE)_get_osfhandle(fd)) != INVALID_HANDLE_VALUE) || length == 0) return MAP_FAILED; if ((handle = CreateFileMapping(INVALID_HANDLE_VALUE, NULL, PAGE_READWRITE, 0, (DWORD)length, NULL)) == NULL) return MAP_FAILED; if ((retVal = MapViewOfFile(handle, FILE_MAP_ALL_ACCESS, 0, 0, 0)) == NULL) goto exit; if (fd != -1) { if (SetFilePointer(file, (DWORD)offset, NULL, FILE_BEGIN) == INVALID_SET_FILE_POINTER) goto err; if (ReadFile(file, retVal, (DWORD)length, &nRead, NULL) == 0) goto err; } goto exit; err: UnmapViewOfFile(retVal); retVal = NULL; exit: CloseHandle(handle); return (retVal == NULL ? MAP_FAILED : retVal); } int munmap(void *addr, size_t length) { if (addr == NULL || addr == MAP_FAILED) return -1; return (UnmapViewOfFile(addr) == 0 ? -1 : 0); } �������������skyeye-1.2.5_REL/utils/portable/gettimeofday.h������������������������������������������������������0000644�0001750�0000144�00000003150�10577026755�020055� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* gettimeofday.h - portable gettimeofday function for skyeye Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/03/2007 initial version by Anthony Lee */ #ifndef __SKYEYE_GETTIMEOFDAY_H__ #define __SKYEYE_GETTIMEOFDAY_H__ #include <time.h> /* for gmtime */ #include <sys/time.h> /* for struct timeval */ #define HAVE_GETTIMEOFDAY #if defined(__MINGW32__) #include <_mingw.h> #if (__MINGW32_MAJOR_VERSION < 3) #undef HAVE_GETTIMEOFDAY #elif (__MINGW32_MAJOR_VERSION == 3 && __MINGW32_MINOR_VERSION < 10) #undef HAVE_GETTIMEOFDAY #endif #endif /* defined(__MINGW32__) */ #ifndef HAVE_GETTIMEOFDAY #if defined(__MINGW32__) /* we just use timeval, timezone is ignored. */ struct timezone { }; #endif /* defined(__MINGW32__) */ int gettimeofday(struct timeval *tv, struct timezone *tz); #endif /* HAVE_GETTIMEOFDAY */ #endif /* __SKYEYE_GETTIMEOFDAY_H__ */ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/usleep.c������������������������������������������������������������0000644�0001750�0000144�00000002136�10572524543�016660� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* usleep.c - portable usleep function for skyeye Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/03/2007 initial version by Anthony Lee */ #include "usleep.h" #ifndef HAVE_USLEEP #ifdef __MINGW32__ #include "./win32/usleep.c" #endif /* __MINGW32__ */ #ifdef __BEOS__ #include "./beos/usleep.c" #endif /* __BEOS__ */ #endif /* !HAVE_USLEEP */ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/portable/mman.c��������������������������������������������������������������0000644�0001750�0000144�00000004150�10607460064�016305� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mman.c - portable mmap/munmap function for skyeye Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/30/2007 initial version by Anthony Lee */ #include "mman.h" #define SKYEYE_MMAP_USE_MALLOC 0 #ifndef HAVE_MMAP_AND_MUNMAP #ifdef __BEOS__ #include "./beos/mman.c" #endif /* __BEOS__ */ #ifdef __MINGW32__ #include "./win32/mman.c" #endif /* __MINGW32__ */ #if SKYEYE_MMAP_USE_MALLOC #include <stdlib.h> #include <stdio.h> #include <unistd.h> int getpagesize(void) { return 1; } void* mmap(void *addr, size_t length, int prot, int flags, int fd, off_t offset) { if (flags == MAP_ANONYMOUS && length > 0) { void *retVal = malloc(length); if(retVal != NULL) return retVal; } else if (flags == MAP_PRIVATE && prot == PROT_READ && fd != -1 && length > 0) { ssize_t nBytes = 0; void *retVal = malloc(length); if (retVal != NULL) { if (lseek(fd, offset, SEEK_SET) != (off_t)-1) { while (nBytes < length && eof(fd) == 0) { ssize_t nRead = read(fd, (void*)((char*)retVal + nBytes), length); if (nRead == -1) { nBytes = -1; break; } else { nBytes += nRead; } } if (nBytes != -1) return retVal; } free(retVal); } } return MAP_FAILED; } int munmap(void *addr, size_t length) { if (addr == NULL || addr == MAP_FAILED) return -1; free(addr); return 0; } #endif /* SKYEYE_MMAP_USE_MALLOC */ #endif ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/share/�����������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014470� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/share/ansidecl.h�������������������������������������������������������������0000644�0001750�0000144�00000026133�10541455476�016453� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ANSI and traditional C compatability macros Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU C Library. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* ANSI and traditional C compatibility macros ANSI C is assumed if __STDC__ is #defined. Macro ANSI C definition Traditional C definition ----- ---- - ---------- ----------- - ---------- ANSI_PROTOTYPES 1 not defined PTR `void *' `char *' PTRCONST `void *const' `char *' LONG_DOUBLE `long double' `double' const not defined `' volatile not defined `' signed not defined `' VA_START(ap, var) va_start(ap, var) va_start(ap) Note that it is safe to write "void foo();" indicating a function with no return value, in all K+R compilers we have been able to test. For declaring functions with prototypes, we also provide these: PARAMS ((prototype)) -- for functions which take a fixed number of arguments. Use this when declaring the function. When defining the function, write a K+R style argument list. For example: char *strcpy PARAMS ((char *dest, char *source)); ... char * strcpy (dest, source) char *dest; char *source; { ... } VPARAMS ((prototype, ...)) -- for functions which take a variable number of arguments. Use PARAMS to declare the function, VPARAMS to define it. For example: int printf PARAMS ((const char *format, ...)); ... int printf VPARAMS ((const char *format, ...)) { ... } For writing functions which take variable numbers of arguments, we also provide the VA_OPEN, VA_CLOSE, and VA_FIXEDARG macros. These hide the differences between K+R <varargs.h> and C89 <stdarg.h> more thoroughly than the simple VA_START() macro mentioned above. VA_OPEN and VA_CLOSE are used *instead of* va_start and va_end. Immediately after VA_OPEN, put a sequence of VA_FIXEDARG calls corresponding to the list of fixed arguments. Then use va_arg normally to get the variable arguments, or pass your va_list object around. You do not declare the va_list yourself; VA_OPEN does it for you. Here is a complete example: int printf VPARAMS ((const char *format, ...)) { int result; VA_OPEN (ap, format); VA_FIXEDARG (ap, const char *, format); result = vfprintf (stdout, format, ap); VA_CLOSE (ap); return result; } You can declare variables either before or after the VA_OPEN, VA_FIXEDARG sequence. Also, VA_OPEN and VA_CLOSE are the beginning and end of a block. They must appear at the same nesting level, and any variables declared after VA_OPEN go out of scope at VA_CLOSE. Unfortunately, with a K+R compiler, that includes the argument list. You can have multiple instances of VA_OPEN/VA_CLOSE pairs in a single function in case you need to traverse the argument list more than once. For ease of writing code which uses GCC extensions but needs to be portable to other compilers, we provide the GCC_VERSION macro that simplifies testing __GNUC__ and __GNUC_MINOR__ together, and various wrappers around __attribute__. Also, __extension__ will be #defined to nothing if it doesn't work. See below. This header also defines a lot of obsolete macros: CONST, VOLATILE, SIGNED, PROTO, EXFUN, DEFUN, DEFUN_VOID, AND, DOTS, NOARGS. Don't use them. */ #ifndef _ANSIDECL_H #define _ANSIDECL_H 1 /* Every source file includes this file, so they will all get the switch for lint. */ /* LINTLIBRARY */ /* Using MACRO(x,y) in cpp #if conditionals does not work with some older preprocessors. Thus we can't define something like this: #define HAVE_GCC_VERSION(MAJOR, MINOR) \ (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR))) and then test "#if HAVE_GCC_VERSION(2,7)". So instead we use the macro below and test it against specific values. */ /* This macro simplifies testing whether we are using gcc, and if it is of a particular minimum version. (Both major & minor numbers are significant.) This macro will evaluate to 0 if we are not using gcc at all. */ #ifndef GCC_VERSION #define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) #endif /* GCC_VERSION */ #if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32) || (defined(__alpha) && defined(__cplusplus)) /* All known AIX compilers implement these things (but don't always define __STDC__). The RISC/OS MIPS compiler defines these things in SVR4 mode, but does not define __STDC__. */ /* eraxxon@alumni.rice.edu: The Compaq C++ compiler, unlike many other C++ compilers, does not define __STDC__, though it acts as if this was so. (Verified versions: 5.7, 6.2, 6.3, 6.5) */ #define ANSI_PROTOTYPES 1 #define PTR void * #define PTRCONST void *const #define LONG_DOUBLE long double #define PARAMS(ARGS) ARGS #define VPARAMS(ARGS) ARGS #define VA_START(VA_LIST, VAR) va_start(VA_LIST, VAR) /* variadic function helper macros */ /* "struct Qdmy" swallows the semicolon after VA_OPEN/VA_FIXEDARG's use without inhibiting further decls and without declaring an actual variable. */ #define VA_OPEN(AP, VAR) { va_list AP; va_start(AP, VAR); { struct Qdmy #define VA_CLOSE(AP) } va_end(AP); } #define VA_FIXEDARG(AP, T, N) struct Qdmy #undef const #undef volatile #undef signed /* inline requires special treatment; it's in C99, and GCC >=2.7 supports it too, but it's not in C89. */ #undef inline #if __STDC_VERSION__ > 199901L /* it's a keyword */ #else # if GCC_VERSION >= 2007 # define inline __inline__ /* __inline__ prevents -pedantic warnings */ # else # define inline /* nothing */ # endif #endif /* These are obsolete. Do not use. */ #ifndef IN_GCC #define CONST const #define VOLATILE volatile #define SIGNED signed #define PROTO(type, name, arglist) type name arglist #define EXFUN(name, proto) name proto #define DEFUN(name, arglist, args) name(args) #define DEFUN_VOID(name) name(void) #define AND , #define DOTS , ... #define NOARGS void #endif /* ! IN_GCC */ #else /* Not ANSI C. */ #undef ANSI_PROTOTYPES #define PTR char * #define PTRCONST PTR #define LONG_DOUBLE double #define PARAMS(args) () #define VPARAMS(args) (va_alist) va_dcl #define VA_START(va_list, var) va_start(va_list) #define VA_OPEN(AP, VAR) { va_list AP; va_start(AP); { struct Qdmy #define VA_CLOSE(AP) } va_end(AP); } #define VA_FIXEDARG(AP, TYPE, NAME) TYPE NAME = va_arg(AP, TYPE) /* some systems define these in header files for non-ansi mode */ #undef const #undef volatile #undef signed #undef inline #define const #define volatile #define signed #define inline #ifndef IN_GCC #define CONST #define VOLATILE #define SIGNED #define PROTO(type, name, arglist) type name () #define EXFUN(name, proto) name() #define DEFUN(name, arglist, args) name arglist args; #define DEFUN_VOID(name) name() #define AND ; #define DOTS #define NOARGS #endif /* ! IN_GCC */ #endif /* ANSI C. */ /* Define macros for some gcc attributes. This permits us to use the macros freely, and know that they will come into play for the version of gcc in which they are supported. */ #if (GCC_VERSION < 2007) # define __attribute__(x) #endif /* Attribute __malloc__ on functions was valid as of gcc 2.96. */ #ifndef ATTRIBUTE_MALLOC # if (GCC_VERSION >= 2096) # define ATTRIBUTE_MALLOC __attribute__ ((__malloc__)) # else # define ATTRIBUTE_MALLOC # endif /* GNUC >= 2.96 */ #endif /* ATTRIBUTE_MALLOC */ /* Attributes on labels were valid as of gcc 2.93. */ #ifndef ATTRIBUTE_UNUSED_LABEL # if (GCC_VERSION >= 2093) # define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED # else # define ATTRIBUTE_UNUSED_LABEL # endif /* GNUC >= 2.93 */ #endif /* ATTRIBUTE_UNUSED_LABEL */ #ifndef ATTRIBUTE_UNUSED #define ATTRIBUTE_UNUSED __attribute__ ((__unused__)) #endif /* ATTRIBUTE_UNUSED */ /* Before GCC 3.4, the C++ frontend couldn't parse attributes placed after the identifier name. */ #if ! defined(__cplusplus) || (GCC_VERSION >= 3004) # define ARG_UNUSED(NAME) NAME ATTRIBUTE_UNUSED #else /* !__cplusplus || GNUC >= 3.4 */ # define ARG_UNUSED(NAME) NAME #endif /* !__cplusplus || GNUC >= 3.4 */ #ifndef ATTRIBUTE_NORETURN #define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__)) #endif /* ATTRIBUTE_NORETURN */ /* Attribute `nonnull' was valid as of gcc 3.3. */ #ifndef ATTRIBUTE_NONNULL # if (GCC_VERSION >= 3003) # define ATTRIBUTE_NONNULL(m) __attribute__ ((__nonnull__ (m))) # else # define ATTRIBUTE_NONNULL(m) # endif /* GNUC >= 3.3 */ #endif /* ATTRIBUTE_NONNULL */ /* Attribute `pure' was valid as of gcc 3.0. */ #ifndef ATTRIBUTE_PURE # if (GCC_VERSION >= 3000) # define ATTRIBUTE_PURE __attribute__ ((__pure__)) # else # define ATTRIBUTE_PURE # endif /* GNUC >= 3.0 */ #endif /* ATTRIBUTE_PURE */ /* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL. This was the case for the `printf' format attribute by itself before GCC 3.3, but as of 3.3 we need to add the `nonnull' attribute to retain this behavior. */ #ifndef ATTRIBUTE_PRINTF #define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) ATTRIBUTE_NONNULL(m) #define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2) #define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3) #define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4) #define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5) #define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) #endif /* ATTRIBUTE_PRINTF */ /* Use ATTRIBUTE_NULL_PRINTF when the format specifier may be NULL. A NULL format specifier was allowed as of gcc 3.3. */ #ifndef ATTRIBUTE_NULL_PRINTF # if (GCC_VERSION >= 3003) # define ATTRIBUTE_NULL_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) # else # define ATTRIBUTE_NULL_PRINTF(m, n) # endif /* GNUC >= 3.3 */ # define ATTRIBUTE_NULL_PRINTF_1 ATTRIBUTE_NULL_PRINTF(1, 2) # define ATTRIBUTE_NULL_PRINTF_2 ATTRIBUTE_NULL_PRINTF(2, 3) # define ATTRIBUTE_NULL_PRINTF_3 ATTRIBUTE_NULL_PRINTF(3, 4) # define ATTRIBUTE_NULL_PRINTF_4 ATTRIBUTE_NULL_PRINTF(4, 5) # define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6) #endif /* ATTRIBUTE_NULL_PRINTF */ /* Attribute `sentinel' was valid as of gcc 3.5. */ #ifndef ATTRIBUTE_SENTINEL # if (GCC_VERSION >= 3005) # define ATTRIBUTE_SENTINEL __attribute__ ((__sentinel__)) # else # define ATTRIBUTE_SENTINEL # endif /* GNUC >= 3.5 */ #endif /* ATTRIBUTE_SENTINEL */ /* We use __extension__ in some places to suppress -pedantic warnings about GCC extensions. This feature didn't work properly before gcc 2.8. */ #if GCC_VERSION < 2008 #define __extension__ #endif #endif /* ansidecl.h */ �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/Makefile.am������������������������������������������������������������������0000644�0001750�0000144�00000001550�11006633144�015431� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������utils_config = config/skyeye_arch.c config/skyeye_config.c config/skyeye_options.c utils_debugger = debugger/arch_regdefs.c debugger/cf_regdefs.c debugger/mips_regdefs.c \ debugger/arm_regdefs.c debugger/gdbserver.c debugger/ppc_regdefs.c \ debugger/bfin_regdefs.c debugger/gdb_tracepoint.c debugger/skyeye2gdb.c utils_profile = profile/code_cov.c profile/symbol.c libutils_a_SOURCES = $(utils_config) $(utils_debugger) $(utils_profile) noinst_LIBRARIES = libutils.a DEFS = -DMODET -g -O2 -D_FILE_OFFSET_BITS=64 -DSTANDALONE -DDEFAULT_INLINE=0 INCLUDES = -I$(top_srcdir)/arch/arm/dbct/ -I$(top_srcdir)/device/uart/ -I$(top_srcdir)/device/net/ -I$(top_srcdir)/device/lcd -I$(top_srcdir)/arch/arm/common -I$(top_srcdir)/arch/arm/ -I$(top_srcdir)/arch/bfin/common -I$(top_srcdir)/arch/mips/common -I$(top_srcdir)/arch/ppc/common @COMMON_INCLUDES@ ��������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/main/������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014312� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/main/elf32.h�����������������������������������������������������������������0000644�0001750�0000144�00000005272�10642337630�015420� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * File header */ struct Elf32_Header { unsigned char e_ident[16]; uint16_t e_type; /* Relocatable=1, Executable=2 (+ some * more ..) */ uint16_t e_machine; /* Target architecture: MIPS=8 */ uint32_t e_version; /* Elf version (should be 1) */ uint32_t e_entry; /* Code entry point */ uint32_t e_phoff; /* Program header table */ uint32_t e_shoff; /* Section header table */ uint32_t e_flags; /* Flags */ uint16_t e_ehsize; /* ELF header size */ uint16_t e_phentsize; /* Size of one program segment * header */ uint16_t e_phnum; /* Number of program segment * headers */ uint16_t e_shentsize; /* Size of one section header */ uint16_t e_shnum; /* Number of section headers */ uint16_t e_shstrndx; /* Section header index of the * string table for section header * * names */ }; /* * Section header */ struct Elf32_Shdr { uint32_t sh_name; uint32_t sh_type; uint32_t sh_flags; uint32_t sh_addr; uint32_t sh_offset; uint32_t sh_size; uint32_t sh_link; uint32_t sh_info; uint32_t sh_addralign; uint32_t sh_entsize; }; /* * Program header */ struct Elf32_Phdr { uint32_t p_type; /* Segment type: Loadable segment = 1 */ uint32_t p_offset; /* Offset of segment in file */ uint32_t p_vaddr; /* Reqd virtual address of segment * when loading */ uint32_t p_paddr; /* Reqd physical address of * segment (ignore) */ uint32_t p_filesz; /* How many bytes this segment * occupies in file */ uint32_t p_memsz; /* How many bytes this segment * should occupy in * memory (when * * loading, expand the segment * by * concatenating enough zero * bytes to it) */ uint32_t p_flags; /* Flags: logical "or" of PF_ * constants below */ uint32_t p_align; /* Reqd alignment of segment in * memory */ }; /* * constants for Elf32_Phdr.p_flags */ #define PF_X 1 /* readable segment */ #define PF_W 2 /* writeable segment */ #define PF_R 4 /* executable segment */ /* * constants for indexing into Elf64_Header_t.e_ident */ #define EI_MAG0 0 #define EI_MAG1 1 #define EI_MAG2 2 #define EI_MAG3 3 #define EI_CLASS 4 #define EI_DATA 5 #define EI_VERSION 6 #define ELFMAG0 '\177' #define ELFMAG1 'E' #define ELFMAG2 'L' #define ELFMAG3 'F' #define ELFCLASS32 1 #define ELFCLASS64 2 #define PT_NULL 0 #define PT_LOAD 1 #define PT_DYNAMIC 2 #define PT_INTERP 3 #define PT_NOTE 4 #define ELFDATA2LSB 1 #define ELFDATA2MSB 2 #define EM_ARM 40 #define EM_BLACKFIN 106 #define EM_MIPS 8 #define EM_COLDFIRE 52 #define EM_PPC 20 ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/main/skyeye.c����������������������������������������������������������������0000644�0001750�0000144�00000051417�11006636055�016011� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /** * author chenyu <yuchen@tsinghua.edu.cn> * teawater <c7code-uc@yahoo.com.cn> add elf load function in 2005.08.30 */ #ifdef __CYGWIN__ #include <getopt.h> #else #include <unistd.h> #endif #include <signal.h> #include <stdio.h> #include <stdarg.h> #include <stdlib.h> #include <string.h> // Anthony Lee 2006-08-22 : for Win32API #ifdef __MINGW32__ #undef WORD #undef byte #include <windows.h> #endif #include "skyeye_types.h" #include "skyeye_defs.h" #include "skyeye_config.h" #include "skyeye_uart.h" #include "config.h" #include <setjmp.h> #include "code_cov.h" /** * A global variable , point to the current archtecture */ generic_arch_t *arch_instance; /** * name of current config file */ char *skyeye_config_filename = NULL; /* * the file description of log */ extern FILE *skyeye_logfd; int big_endian = 0; int global_argc; char **global_argv; int stop_simulator = 0; int debugmode = 0; jmp_buf ctrl_c_cleanup; static void base_termios_exit (void) { //tcsetattr (STDIN_FILENO, TCSANOW, &(state->base_termios)); } extern int init_register_type(); /** * Initialize all the gloval variable */ static int init () { static int done; int ret; if (!done) { done = 1; /*some option should init before read config. e.g. uart option. */ initialize_all_devices (); initialize_all_arch (); /* parse skyeye.conf to set skyeye_config */ skyeye_option_init (&skyeye_config); if((ret = skyeye_read_config()) < 0) return ret; /* we should check if some members of skyeye_config is initialized */ if(!skyeye_config.arch){ fprintf(stderr, "arch is not initialization or you have not provide arch option in skyeye.conf.\n"); skyeye_exit(-1); } if(!skyeye_config.mach){ fprintf(stderr, "mach is not initialization or you have not provide mach option in skyeye.conf.\n"); skyeye_exit(-1); } /* initialize register type for gdb server */ if((ret = init_register_type()) < 0) return ret;/* Failed to initialize register type */ arch_instance = (generic_arch_t *) malloc (sizeof (generic_arch_t)); if (!arch_instance) { printf ("malloc error!\n"); return -1; } arch_instance->init = skyeye_config.arch->init; arch_instance->reset = skyeye_config.arch->reset; arch_instance->step_once = skyeye_config.arch->step_once; arch_instance->set_pc = skyeye_config.arch->set_pc; arch_instance->get_pc = skyeye_config.arch->get_pc; arch_instance->ICE_write_byte = skyeye_config.arch->ICE_write_byte; arch_instance->ICE_read_byte = skyeye_config.arch->ICE_read_byte; arch_instance->init (); arch_instance->reset (); skyeye_uart_converter_setup(); if(skyeye_config.code_cov.prof_on) cov_init(skyeye_config.code_cov.start, skyeye_config.code_cov.end); } return 1; } #include "armemu.h" #include "skyeye2gdb.h" extern ARMul_State * state; extern struct SkyEye_ICE skyeye_ice; /** * step run for the simulator */ void sim_resume (int step) { /* workaround here: we have different run mode on arm */ if(!strcmp(skyeye_config.arch->arch_name, "arm")){ state->EndCondition = 0; stop_simulator = 0; if (step) { state->Reg[15] = ARMul_DoInstr (state); if (state->EndCondition == 0) { //chy 20050729 ???? printf ("error in sim_resume for state->EndCondition"); skyeye_exit (-1); } } else { state->NextInstr = RESUME; /* treat as PC change */ state->Reg[15] = ARMul_DoProg (state); } FLUSHPIPE; } /* other target simulator step run */ else { do { /* if we are in debugmode we will check ctrl+c and breakpoint */ if(debugmode){ int i; WORD addr; /* to detect if Ctrl+c is pressed.. */ if(remote_interrupt()) return; addr = arch_instance->get_pc(); for (i = 0;i < skyeye_ice.num_bps;i++){ if(skyeye_ice.bps[i] == addr) return; } /* for */ if (skyeye_ice.tps_status==TRACE_STARTED) { for (i=0;i<skyeye_ice.num_tps;i++) { if (((skyeye_ice.tps[i].tp_address==addr)&& (skyeye_ice.tps[i].status==TRACEPOINT_ENABLED))||(skyeye_ice.tps[i].status==TRACEPOINT_STEPPING)) { handle_tracepoint(i); } } } } /* if(debugmode) */ if (skyeye_config.log.logon >= 1) { WORD pc = arch_instance->get_pc(); if (pc >= skyeye_config.log.start && pc <= skyeye_config.log.end) { #if defined(HAVE_LIBBFD) && !defined(__MINGW32__) char * func_name = get_sym(pc); if(func_name) fprintf (skyeye_logfd,"\n in %s\n", func_name); #endif /* if (skyeye_config.log.logon >= 2) fprintf (skyeye_logfd, "pc=0x%x", pc); SKYEYE_OUTREGS (skyeye_logfd); if (skyeye_config.log.logon >= 3) SKYEYE_OUTMOREREGS (skyeye_logfd); */ } }/* if (skyeye_config.log.logon >= 1) */ /* do profiling for code coverage */ if (skyeye_config.code_cov.prof_on) cov_prof(EXEC_FLAG, arch_instance->get_pc()); arch_instance->step_once (); }while(!step); } } /** * add by michael.Kang, to load elf file to another address */ unsigned long load_base = 0x0; unsigned long load_mask = 0xffffffff; //teawater add for load elf 2005.07.31------------------------------------------ static inline void tea_write (uint32_t addr, uint8_t * buffer, int size) { int i,fault; addr = (addr & load_mask)|load_base; for (i = 0; i < size; i++) { if(arch_instance->ICE_write_byte) fault = arch_instance->ICE_write_byte (addr + i, buffer[i]); else fault = -1; if(fault) {printf("SKYEYE: tea_write error!!!\n");skyeye_exit(-1);} } } #ifndef HAVE_LIBBFD #include <elf32.h> #ifdef __MINGW32__ #include <io.h> #undef O_RDONLY #define O_RDONLY (_O_RDONLY | _O_BINARY) #define open(file, flags) _open(file, flags) #define close(fd) _close(fd) #endif /* __MINGW32__ */ static inline void tea_set(uint32_t addr, uint8_t value, int size) { int i,fault; addr = (addr & load_mask)|load_base; for (i = 0; i < size; i++) { fault=arch_instance->ICE_write_byte (addr + i, value); if(fault) {printf("SKYEYE: tea_set error!!!\n");skyeye_exit(-1);} } } /* These function convert little-endian ELF datatypes into host endianess values. */ #ifdef HOST_IS_BIG_ENDIAN uint16_t e2h16(uint16_t x) { if (big_endian) return x; return ((x & 0xff) << 8) | (x >> 8); } uint32_t e2h32(uint32_t x) { if (big_endian) return x; return ((x & 0xff) << 24) | (((x >> 8) & 0xff) << 16) | (((x >> 16) & 0xff) << 8) | (((x >> 24) & 0xff)); } #else uint16_t e2h16(uint16_t x) { if (!big_endian) return x; return ((x & 0xff) << 8) | (x >> 8); } uint32_t e2h32(uint32_t x) { if (!big_endian) return x; return ((x & 0xff) << 24) | (((x >> 8) & 0xff) << 16) | (((x >> 16) & 0xff) << 8) | (((x >> 24) & 0xff)); } #endif /* HOST_IS_BIG_ENDIAN */ static int elf32_checkFile(struct Elf32_Header *file) { if (file->e_ident[EI_MAG0] != ELFMAG0 || file->e_ident[EI_MAG1] != ELFMAG1 || file->e_ident[EI_MAG2] != ELFMAG2 || file->e_ident[EI_MAG3] != ELFMAG3) return -1; /* not an elf file */ if (file->e_ident[EI_CLASS] != ELFCLASS32) return -2; /* not 32-bit file */ switch (e2h16(file->e_machine)) { case EM_ARM: case EM_BLACKFIN: case EM_COLDFIRE: case EM_MIPS: case EM_PPC: break; default: return -3; } return 0; /* elf file looks OK */ } static int tea_load_exec(const char *file, int only_check_big_endian) { int ret = -1; int i; int tmp_fd; int r; struct Elf32_Header *elfFile; struct stat stat; struct Elf32_Phdr *segments; tmp_fd = open(file, O_RDONLY); if (tmp_fd == -1) { fprintf (stderr, "open %s error: %s\n", file, strerror(errno)); goto out; } fstat(tmp_fd, &stat); /* malloc */ elfFile = mmap(NULL, stat.st_size, PROT_READ, MAP_PRIVATE, tmp_fd, 0); if (elfFile == NULL || elfFile == MAP_FAILED) { fprintf (stderr, "mmap error: %s\n", strerror(errno)); goto out; } big_endian = (elfFile->e_ident[EI_DATA] == ELFDATA2MSB); if (only_check_big_endian) goto out; r = elf32_checkFile(elfFile); if (r != 0) { fprintf (stderr, "elf_checkFile failed: %d\n", r); goto out; } segments = (struct Elf32_Phdr*) (uintptr_t) (((uintptr_t) elfFile) + e2h32(elfFile->e_phoff)); for(i=0; i < e2h16(elfFile->e_phnum); i++) { /* Load that section */ uint32_t dest; char *src; size_t filesz = e2h32(segments[i].p_filesz); size_t memsz = e2h32(segments[i].p_memsz); dest = e2h32(segments[i].p_paddr); src = ((char*) elfFile) + e2h32(segments[i].p_offset); tea_write(dest, src, filesz); dest += filesz; tea_set(dest, 0, memsz - filesz); } if (skyeye_config.start_address == 0) { skyeye_config.start_address = e2h32(elfFile->e_entry); } ret = 0; out: if (tmp_fd != -1) close(tmp_fd); if (elfFile) munmap(elfFile, stat.st_size); return(ret); } #else //#ifndef HAVE_LIBBFD //teawater add for load elf 2005.07.31------------------------------------------ #include <bfd.h> static int tea_load_exec (const char *file, int only_check_big_endian) { int ret = -1; bfd *tmp_bfd = NULL; asection *s; char *tmp_str = NULL; /* open */ tmp_bfd = bfd_openr (file, NULL); if (tmp_bfd == NULL) { fprintf (stderr, "open %s error: %s\n", file, bfd_errmsg (bfd_get_error ())); goto out; } if (!bfd_check_format (tmp_bfd, bfd_object)) { /* FIXME:In freebsd, if bfd_errno is bfd_error_file_ambiguously_recognized, * though bfd can't recognize this format, we should try to load file.*/ if (bfd_get_error () != bfd_error_file_ambiguously_recognized) { fprintf (stderr, "check format of %s error: %s\n", file, bfd_errmsg (bfd_get_error ())); goto out; } } big_endian = bfd_big_endian(tmp_bfd); if (only_check_big_endian) goto out; printf ("exec file \"%s\"'s format is %s.\n", file, tmp_bfd->xvec->name); /* load the corresponding section to memory */ for (s = tmp_bfd->sections; s; s = s->next) { if (bfd_get_section_flags (tmp_bfd, s) & (SEC_LOAD)) { if (bfd_section_lma (tmp_bfd, s) != bfd_section_vma (tmp_bfd, s)) { printf ("load section %s: lma = 0x%08x (vma = 0x%08x) size = 0x%08x.\n", bfd_section_name (tmp_bfd, s), (unsigned int) bfd_section_lma (tmp_bfd, s), (unsigned int) bfd_section_vma (tmp_bfd, s), (unsigned int) bfd_section_size (tmp_bfd, s)); } else { printf ("load section %s: addr = 0x%08x size = 0x%08x.\n", bfd_section_name (tmp_bfd, s), (unsigned int) bfd_section_lma (tmp_bfd, s), (unsigned int) bfd_section_size (tmp_bfd, s)); } if (bfd_section_size (tmp_bfd, s) > 0) { tmp_str = (char *) malloc (bfd_section_size (tmp_bfd, s)); if (!tmp_str) { fprintf (stderr, "alloc memory to load session %s error.\n", bfd_section_name (tmp_bfd, s)); goto out; } if (!bfd_get_section_contents (tmp_bfd, s, tmp_str, 0, bfd_section_size (tmp_bfd, s))) { fprintf (stderr, "get session %s content error: %s\n", bfd_section_name (tmp_bfd, s), bfd_errmsg (bfd_get_error ())); goto out; } tea_write (bfd_section_vma (tmp_bfd, s), tmp_str, bfd_section_size (tmp_bfd, s)); free (tmp_str); tmp_str = NULL; } } else { printf ("not load section %s: addr = 0x%08x size = 0x%08x .\n", bfd_section_name (tmp_bfd, s), (unsigned int) bfd_section_vma (tmp_bfd, s), (unsigned int) bfd_section_size (tmp_bfd, s)); } } //set start address if (skyeye_config.start_address == 0) { skyeye_config.start_address = bfd_get_start_address (tmp_bfd); } ret = 0; out: if (tmp_str) free (tmp_str); if (tmp_bfd) bfd_close (tmp_bfd); return (ret); } #endif //#ifndef HAVE_LIBBFD //AJ2D-------------------------------------------------------------------------- void usage () { printf("%s\n",PACKAGE_STRING); printf("Bug report: %s\n", PACKAGE_BUGREPORT); printf ("Usage: skyeye [options] -e program [program args]\n"); printf ( "Default mode is STANDALONE mode\n"); printf ( "------------------------------------------------------------------\n"); printf ( "Options:\n"); //teawater add for load elf 2005.07.31------------------------------------------ printf ( "-e exec-file the (ELF executable format)kernel file name.\n"); printf ( "-l load_address,load_address_mask\n"); printf ( " Load ELF file to another address, not its entry.\n"); //AJ2D-------------------------------------------------------------------------- printf ( /* 2007-03-29 by Anthony Lee : for specify big endian when non ELF */ "-b specify the data type is big endian when non \"-e\" option.\n"); printf ( "-d in GDB Server mode (can be connected by GDB).\n"); printf ( "-c config-file the skyeye configure file name.\n"); printf ( "-h The SkyEye command options, and ARCHs and CPUs simulated.\n"); printf ( "------------------------------------------------------------------\n"); } extern machine_config_t bfin_machines[]; extern machine_config_t arm_machines[]; void display_all_support(){ int i; printf ( "----------- Architectures and CPUs simulated by SkyEye-------------\n"); printf ( "-------- ARM architectures ---------\n"); for(i = 0; i < 18; i++) printf("%s \n",arm_machines[i].machine_name); printf ("-------- BlackFin architectures ----\n"); for(i = 0; i < 2 ; i++) printf("%s \n",bfin_machines[i].machine_name); } void skyeye_exit(int ret) { /* * 2007-01-24 removed the term-io functions by Anthony Lee, * moved to "device/uart/skyeye_uart_stdio.c". */ exit( ret); } #ifdef __MINGW32__ static BOOL init_win32_socket() { WSADATA wsdData; if(WSAStartup(0x202, &wsdData) != 0 || LOBYTE(wsdData.wVersion) != 2 || HIBYTE(wsdData.wVersion) != 2) return FALSE; return TRUE; } static void cancel_win32_socket() { WSACleanup(); } #endif #ifndef __BEOS__ /* 2007-01-31 disabled by Anthony Lee on BeOS for multi-thread safe. */ void sigint_handler (int signum) { if(skyeye_config.code_cov.prof_on) cov_fini(skyeye_config.code_cov.prof_filename); longjmp (ctrl_c_cleanup, 1); } #endif /** * The main function of skyeye */ int main (int argc, char **argv) { int c; int index; int ret; //teawater add for load elf 2005.07.31------------------------------------------ char *exec_file = NULL; opterr = 0; /* * 2007-01-24 removed the term-io functions by Anthony Lee, * moved to "device/uart/skyeye_uart_stdio.c". */ #ifdef __MINGW32__ init_win32_socket(); atexit(cancel_win32_socket); #endif #ifndef __BEOS__ /* 2007-01-31 disabled by Anthony Lee on BeOS for multi-thread safe. */ if (setjmp (ctrl_c_cleanup) != 0) { goto exit_skyeye; } signal (SIGINT, sigint_handler); #endif while ((c = getopt (argc, argv, "be:dc:l:h")) != -1) //AJ2D-------------------------------------------------------------------------- switch (c) { //teawater add for load elf 2005.07.31------------------------------------------ case 'e': exec_file = optarg; break; //AJ2D-------------------------------------------------------------------------- case 'd': debugmode = 1; break; case 'h': usage (); display_all_support(); goto exit_skyeye; case 'c': skyeye_config_filename = optarg; break; case 'l': { char * tok = ","; char * str1 = strtok(optarg, tok); char * str2 = (char *)(optarg + strlen(str1) + 1); load_base = strtoul(str1, NULL, 16); load_mask = strtoul(str2, NULL, 16); } break; case 'b': big_endian = 1; break; case '?': if (isprint (optopt)) fprintf (stderr, "Unknown option `-%c'.\n", optopt); else fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt); ret=1; goto exit_skyeye; /* case 'v': display_all_support(); goto exit_skyeye; */ default: fprintf(stderr, "Default option .....\n"); ret=1; goto exit_skyeye; } if(exec_file == NULL){ printf ("\n\ **************************** WARNING **********************************\n\ If you want to run ELF image, you should use -e option to indicate\n\ your elf-format image filename. Or you only want to run binary image,\n\ you need to set the filename of the image and its entry in skyeye.conf.\n\ ***********************************************************************\n\n"); } if (skyeye_config_filename == NULL) skyeye_config_filename = DEFAULT_CONFIG_FILE; for (index = optind; index < argc; index++) printf ("Non-option argument %s\n", argv[index]); //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED { if (!dbct_test_speed_state) { //init timer struct itimerval value; struct sigaction act; dbct_test_speed_state = state; state->instr_count = 0; act.sa_handler = dbct_test_speed_sig; act.sa_flags = SA_RESTART; //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF #ifndef __CYGWIN__ if (sigaction(SIGVTALRM, &act, NULL) == -1) { #else if (sigaction(SIGALRM, &act, NULL) == -1) { #endif //__CYGWIN__ fprintf(stderr, "init timer error.\n"); goto exit_skyeye; } if (skyeye_config.dbct_test_speed_sec) { value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec; } else { value.it_value.tv_sec = DBCT_TEST_SPEED_SEC; } printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec); value.it_value.tv_usec = 0; value.it_interval.tv_sec = 0; value.it_interval.tv_usec = 0; #ifndef __CYGWIN__ if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) { #else if (setitimer(ITIMER_REAL, &value, NULL) == -1) { #endif //__CYGWIN__ fprintf(stderr, "init timer error.\n"); goto exit_skyeye; } } } #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- /* 2007-03-28 by Anthony Lee : check for big endian at first */ if (exec_file) tea_load_exec(exec_file, 1); if(big_endian) printf("Your elf file is big endian.\n"); else printf("Your elf file is little endian.\n"); /*do some initialization*/ if((ret = init ()) < 0) goto exit_skyeye; //teawater add for load elf 2005.07.31------------------------------------------ if (exec_file) { if (tea_load_exec (exec_file, 0)) { fprintf (stderr, "load \"%s\" error\n", exec_file); goto exit_skyeye; } #if defined(HAVE_LIBBFD) && !defined(__MINGW32__) /* get its symbol to debug */ init_symbol_table(exec_file); #endif } //AJ2D-------------------------------------------------------------------------- if (skyeye_config.start_address != 0){ unsigned long addr = (skyeye_config.start_address & load_mask)|load_base; arch_instance->set_pc (addr); printf ("start addr is set to 0x%08x by exec file.\n", (unsigned int) addr); } fflush(stdout); if (debugmode == 0) sim_resume (0); else{ printf ("debugmode= %d, filename = %s, server TCP port is 12345\n", debugmode, skyeye_config_filename); sim_debug (); } exit_skyeye: /* * 2007-01-24 removed the term-io functions by Anthony Lee, * moved to "device/uart/skyeye_uart_stdio.c". */ return ret; } #ifdef __MINGW32__ int _stdcall WinMain(HINSTANCE hInstance, HINSTANCE hPrevInstance, LPSTR lpCmdLine, int nCmdShow) { return main(__argc, __argv); } #endif // __MINGW32__ �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/main/setup.py����������������������������������������������������������������0000644�0001750�0000144�00000003211�10541455476�016044� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������from distutils.core import setup import py2exe from py2exe.build_exe import py2exe as BuildExe import os,sys def TixInfo(): import Tkinter import _tkinter tk=_tkinter.create() tcl_version=_tkinter.TCL_VERSION tk_version=_tkinter.TK_VERSION tix_version=tk.call("package","version","Tix") tcl_dir=tk.call("info","library") del tk, _tkinter, Tkinter return (tcl_version,tk_version,tix_version,tcl_dir) class myPy2Exe(BuildExe): def plat_finalize(self, modules, py_files, extensions, dlls): BuildExe.plat_finalize(self, modules, py_files, extensions, dlls) if "Tix" in modules: # Tix adjustments tcl_version,tk_version,tix_version,tcl_dir = TixInfo() tixdll="tix%s%s.dll"% (tix_version.replace(".",""), tcl_version.replace(".","")) tcldll="tcl%s.dll"%tcl_version.replace(".","") tkdll="tk%s.dll"%tk_version.replace(".","") dlls.add(os.path.join(sys.prefix,"DLLs",tixdll)) self.dlls_in_exedir.extend( [tcldll,tkdll,tixdll ] ) tcl_src_dir = os.path.split(tcl_dir)[0] tcl_dst_dir = os.path.join(self.lib_dir, "tcl") self.announce("Copying TIX files from %s..." % tcl_src_dir) self.copy_tree(os.path.join(tcl_src_dir, "tix%s" % tix_version), os.path.join(tcl_dst_dir, "tix%s" % tix_version)) opts={ 'py2exe':{ 'bundle_files':1 } } setup( script_args=['py2exe'], cmdclass={'py2exe':myPy2Exe}, windows=['ide.py'], options=opts, )���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/main/ide.py������������������������������������������������������������������0000644�0001750�0000144�00000064031�10541455476�015454� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������import os, os.path, sys, Tix from Tkconstants import * import traceback, tkMessageBox from Tkinter import * import subprocess import win32process import win32api class skyeye: cpu = "" board="" net = "" lcd = "" flash = "" map = "" type = "" addr = "" size = "" file = "" membank = [] memory_info = "" cpu_once = 0 device_once = 0 memory_once = 0 image_path = None conf_path = None run = None kill = None is_running = 0 skyeye_id = 0 def __init__(self, top): self.root = top self.build() def skyeye_mainmenu(self): top = self.root w = Tix.Frame(top, bd=2, relief=RAISED) file = Tix.Menubutton(w, text='File', underline=0, takefocus=0) view = Tix.Menubutton(w, text='Setting', underline=0, takefocus=0) project = Tix.Menubutton(w, text='Project', underline=0, takefocus=0) execute = Tix.Menubutton(w, text='Execute', underline=0, takefocus=0) tools = Tix.Menubutton(w, text='Tools', underline=0, takefocus=0) window = Tix.Menubutton(w, text='Window', underline=0, takefocus=0) help = Tix.Menubutton(w, text='Help', underline=0, takefocus=0) file.pack(side=LEFT) project.pack(side=LEFT) view.pack(side=LEFT) execute.pack(side=LEFT) tools.pack(side=LEFT) window.pack(side=LEFT) help.pack(side=RIGHT) file_m = Tix.Menu(file, tearoff=0) file['menu'] = file_m view_m = Tix.Menu(view, tearoff=0) view['menu'] = view_m project_m = Tix.Menu(project, tearoff=0) project['menu'] = project_m execute_m = Tix.Menu(execute, tearoff=0) execute['menu'] = execute_m tools_m = Tix.Menu(tools, tearoff=0) tools['menu'] = tools_m window_m = Tix.Menu(window, tearoff=0) window['menu'] = window_m help_m = Tix.Menu(help, tearoff=0) help['menu'] = help_m file_m.add_command(label='Open file', underline=1, command = self.file_openfile) file_m.add_command(label='Close file', underline=1, command = self.file_closefile) file_m.add_command(label='Exit', underline=1, command = self.file_exit) view_m.add_radiobutton(label='Cpu', underline =1, command = self.view_cpu) view_m.add_radiobutton(label='Device', underline =1, command = self.view_device) view_m.add_radiobutton(label='Memory', underline =1, command = self.view_memory) view_m.add_radiobutton(label='System Info', underline =1, command = self.view_info) project_m.add_command(label='New', underline =1, command = self.project_new) project_m.add_command(label='Save', underline =1, command = self.project_save) execute_m.add_command(label='Compile', underline =1, command = self.execute_compile) execute_m.add_command(label='Compile current file', underline =1, command = self.execute_compilecurrentfile) execute_m.add_command(label='Run', underline =1, command = self.execute_run) execute_m.add_command(label='Compile & Run', underline =1, command = self.execute_compileandrun) execute_m.add_command(label='Rebuild All', underline =1, command = self.execute_rebuildall) execute_m.add_command(label='Clean', underline =1, command = self.execute_clean) tools_m.add_command(label='Compiler Option', underline =1, command = self.tools_compileroption) tools_m.add_command(label='Linker Option', underline =1, command = self.tools_linkeroption) tools_m.add_command(label='Makefile Option', underline =1, command = self.tools_makefileoption) window_m.add_command(label='Max', underline=0, command=self.window_max) window_m.add_command(label='Restore', underline=0, command=self.window_restore) help_m.add_command(label='about',underline =0, command=self.help_about) return w def skyeye_body(self, str): top = self.root try: self.body.destroy() except: pass self.body = Tix.LabelFrame(top, label=str, labelside="acrosstop") self.body.pack(fill=Tix.BOTH, padx=8, pady=20) return self.body def skyeye_messagebox(self): top = self.root pane = Tix.LabelFrame(top, label='Message Area',labelside="acrosstop") text = Tix.ScrolledText(pane,height=100,scrollbar="y") text.text.insert(Tix.END,"Welcome to skyeye") text.pack(fill=Tix.BOTH, padx=8, pady=20) self.messagebox = text return pane def message(self, msg): self.messagebox.text.delete("0.0",Tix.END) self.messagebox.text.insert(Tix.END,msg) def build(self): root = self.root z = root.winfo_toplevel() z.wm_title('skyeye for windows') frame1 = self.skyeye_mainmenu() frame1.grid(row=0,sticky=N+W+E) frame2 = self.skyeye_messagebox() frame2.grid(row=2,sticky=S+W+E) self.welcome() self.message("hello renjie") def file_openfile(self): tmp = Tix.ExFileSelectBox(self.skyeye_body("Open file for reading"),command=self.file_openfile_command) tmp.pack(fill=Tix.BOTH, padx=8, pady=20) self.skyeye_redobody() def file_openfile_command(self,event=None): text = Tix.ScrolledText(self.skyeye_body("Reading file : %s"%str(event)),height=300,scrollbar="y") try: fd = open(str(event),"r") for x in fd.readlines(): text.text.insert(Tix.END,x) self.message("Open file <%s> for reading"%str(event)) except: self.message("Cannot open file: %s"%str(event)) text.pack(fill=Tix.BOTH, padx=8, pady=20) self.skyeye_redobody() def welcome(self): tmp = Tix.Label(self.skyeye_body("Welcome"),text="koodialar",height=30) tmp.pack(fill=Tix.BOTH, padx=8, pady=20) self.skyeye_redobody() def skyeye_redobody(self): self.body.grid(row=1,sticky=N+S+W+E) def file_closefile(self): self.welcome() def file_exit(self): self.destroy() self.message("File is closed") def view_cpu(self): self.message("You are now setting the cpu and mainboard information") if self.cpu_once == 1: self.cpu_board_ok() return cpu_list = ["arm","bfin"] board_list =["at91", "at91rm92", "clps7110", "clps9312", "cs89712" "ep7212", "ep9312", "lh79520", "lh79520-hardware", "lh79520-irqs", "lpc", "ns9750", "pxa", "s3c44b0", "s3c2410x", "s3c4510b", "sa1100", "serial_amba", "serial_amba_pl011", "sharp"] top = self.skyeye_body("Cpu & Mainboard") cpu = Tix.LabelFrame(top, label='Cpu',labelside="acrosstop",padx=5,pady=10) board = Tix.LabelFrame(top, label='Mainboard',labelside="acrosstop",padx=5,pady=10) cpu_s = Tix.OptionMenu(cpu, label="Cpu: ",command=self.cpu_select) board_s = Tix.OptionMenu(board, label="Mainboard: ",command=self.board_select) ok = Tix.Button(top, text="OK", command=self.cpu_board_ok) for x in cpu_list: cpu_s.add_command(x,label=x) for x in board_list: board_s.add_command(x,label=x) cpu_s.pack(padx=5,pady=10) cpu.grid(row = 0, column=0,padx=5,pady=10) board_s.pack(padx=5,pady=10) board.grid(row = 0, column=1,padx=5,pady=10) ok.grid(row=1, column=0, columnspan=2,padx=5,pady=10) self.skyeye_redobody() def cpu_select(self, event=None): self.cpu = str(event) self.message("Cpu <%s> is chosen"%str(event)) def board_select(self, event=None): self.board = str(event) self.message("Mainboard <%s> is chosen"%str(event)) def cpu_board_ok(self, event=None): self.cpu_once = 1 top = self.skyeye_body("Cpu & Mainboard") tmp = Tix.Frame(top) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Below are the information of Cpu and Mainboard:') b.grid( row =0 ,padx=5,pady=3,sticky=W+E) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='\tCpu\t\t: %s\n\tMainboard\t: %s'%(self.cpu,self.board)) b.grid( row =1 ,padx=5,pady=3,sticky=W+E) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Would you want to reset?') b.grid( row =2 ,padx=5,pady=3,sticky=W+E) reset = Tix.Button(tmp, text="OK", command=self.reset_cpu, width = 5, bg="red",fg="white") reset.grid( row = 3,padx=5,pady=3) tmp.grid(padx=5,pady=10) self.message("You choose:\n\tCpu\t\t: %s\n\tMainboard\t: %s"%(self.cpu,self.board)) self.skyeye_redobody() def reset_cpu(self): self.cpu_once = 0 self.view_cpu() def view_device(self): self.message("You are now setting the peripherial information") if self.device_once == 1: self.net_lcd_flash_ok() return net_list=["cs8900a", "rtl8091", "s3c4510b"] lcd_list=["ep7312", "pxa", "s3c2410"] flash_list=["ibm"] top = self.skyeye_body("Peripherial") net = Tix.LabelFrame(top,labelside="acrosstop",padx=5,pady=10) lcd = Tix.LabelFrame(top,labelside="acrosstop",padx=5,pady=10) flash = Tix.LabelFrame(top,labelside="acrosstop",padx=5,pady=10) self.net_v = Tix.StringVar() self.lcd_v = Tix.StringVar() self.flash_v = Tix.StringVar() net_s = Tix.Select(net, label='Net Adapter', allowzero=1, radio=1, orientation=Tix.VERTICAL, labelside=Tix.TOP, command=self.net_select, variable=self.net_v) lcd_s = Tix.Select(lcd, label='Lcd', allowzero=1, radio=1, orientation=Tix.VERTICAL, labelside=Tix.TOP, command=self.lcd_select, variable=self.lcd_v) flash_s = Tix.Select(flash, label='Flash', allowzero=1, radio=1, orientation=Tix.VERTICAL, labelside=Tix.TOP, command=self.flash_select, variable=self.flash_v) ok = Tix.Button(top, text="OK", command=self.net_lcd_flash_ok) for x in net_list: net_s.add(x,text=x) for x in lcd_list: lcd_s.add(x,text=x) for x in flash_list: flash_s.add(x,text=x) net_s.pack(padx=5,pady=10) net.grid(row = 0, column=0,padx=5,pady=10) lcd_s.pack(padx=5,pady=10) lcd.grid(row = 0, column=1,padx=5,pady=10) flash_s.pack(padx=5,pady=10) flash.grid(row = 0, column=2,padx=5,pady=10) ok.grid(row=1, column=1, columnspan=1,padx=5,pady=10) self.skyeye_redobody() def net_select(self,event=None,test=None): if str(test) != "0": self.net_tmp = self.net_v self.message("Net adapter <%s> is chosen"%str(event)) else: self.message("No net adapter is chosen") def lcd_select(self,event=None,test=None): if str(test) != "0": self.lcd_tmp = self.lcd_v self.message("Lcd <%s> is chosen"%str(event)) else: self.message("No Lcd is chosen") def flash_select(self,event=None,test=None): if str(test) != "0": self.flash_tmp = self.flash_v self.message("Flash <%s> is chosen"%str(event)) else: self.message("No Flash is chosen") def net_lcd_flash_ok(self,event=None): self.device_once = 1 top = self.skyeye_body("Peripherial") tmp = Tix.Frame(top) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Below are the information of peripherials:') b.grid( row =0 ,padx=5,pady=3,sticky=W+E) self.net = self.net_v.get()[2:-3] str = "" if self.net !="": str +="\tNet\t: %s\n"%self.net else: str +="\tNet\t: disabled\n" self.lcd = self.lcd_v.get()[2:-3] if self.lcd !="": str +="\tLcd\t: %s\n"%self.lcd else: str +="\tLcd\t: disabled\n" self.flash = self.flash_v.get()[2:-3] if self.flash !="": str +="\tFlash\t: %s\n"%self.flash else: str +="\tFlash\t: disabled\n" b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='%s'%str) b.grid( row =1 ,padx=5,pady=3,sticky=W+E) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Would you want to reset?') b.grid( row =2 ,padx=5,pady=3,sticky=W+E) reset = Tix.Button(tmp, text="OK", command=self.reset_device, width = 5, bg="red",fg="white") reset.grid( row = 3,padx=5,pady=3) tmp.grid(padx=5,pady=10) self.message("Peripherial information:\n"+str) self.skyeye_redobody() def reset_device(self): self.device_once = 0 self.view_device() def view_memory(self): self.message("You are now setting memory information") if self.memory_once == 1: self.memory_ok() return top = self.skyeye_body("Cpu & Mainboard") mem = Tix.Frame(top) b = Tix.Label(mem, text="Map :") map = Tix.OptionMenu(mem,command=self.memory_map) b.grid(row = 0, column = 0,padx=5,pady=3,sticky=W+E) map.grid(row = 0,column = 1, columnspan=2, padx=5,pady=3,sticky=W+E) b = Tix.Label(mem, text="Type :") type = Tix.OptionMenu(mem,command=self.memory_type) b.grid(row = 1, column = 0,padx=5,pady=3,sticky=W+E) type.grid(row = 1,column = 1, columnspan=2, padx=5,pady=3,sticky=W+E) b = Tix.Label(mem, text="'Addr :") addr = Tix.ComboBox(mem, editable=1, history=1,anchor=Tix.E,command=self.memory_addr) b.grid(row = 2, column = 0,padx=5,pady=3,sticky=W+E) addr.grid(row = 2,column = 1, columnspan=2, padx=5,pady=3,sticky=W+E) b = Tix.Label(mem, text="Size :") size = Tix.ComboBox(mem,editable=1, history=1,anchor=Tix.E,command=self.memory_size) b.grid(row = 3, column = 0,padx=5,pady=3,sticky=W+E) size.grid(row = 3,column = 1, columnspan=2, padx=5,pady=3,sticky=W+E) b = Tix.Label(mem, text="File :") file = Tix.FileEntry(mem,command=self.memory_file) b.grid(row = 4, column = 0,padx=5,pady=3,sticky=W+E) file.grid(row = 4,column = 1, columnspan=2, padx=5,pady=3,sticky=W+E) add = Tix.Button(top, text="Add", command=self.memory_add) reset = Tix.Button(top, text="Reset", command=self.memory_reset) ok = Tix.Button(top, text="OK",command=self.memory_ok) map.add_command("I",label="I") map.add_command("M",label="M") type.add_command("R",label="R") type.add_command("W",label="W") type.add_command("RW",label="RW") addr.insert(Tix.END,"0x00000000") size.insert(Tix.END,"0x00000000") mem.grid(row = 0, column = 0, columnspan=3,padx=5,pady=10,sticky=N+S+W+E) add.grid(row = 1, column = 0,padx=5,pady=10,sticky=W+E) reset.grid(row =1, column = 1,padx=5,pady=10,sticky=W+E) ok.grid(row =1, column = 2,padx=5,pady=10,sticky=W+E) self.skyeye_redobody() def memory_map(self,event=None): self.map = str(event) def memory_type(self,event=None): self.type = str(event) def memory_addr(self,event=None): self.addr = str(event) def memory_size(self,event=None): self.size = str(event) def memory_file(self,event=None): self.file = str(event) def memory_add(self,event=None): x = {} if self.map != "": x["map"] = self.map else: self.message("map is not filled yet") return if self.type != "": x["type"] = self.type else: self.message("map is not filled yet") return if self.addr != "": x["addr"] = self.addr else: self.message("address is not filled yet") return if self.size != "": x["size"] = self.size else: self.message("size is not filled yet") return x["file"] = self.file self.membank.append(x) str = "" for x in self.membank: str += "membank:" str += "map="+x["map"]+"," str += "type="+x["type"]+"," str += "addr="+x["addr"]+"," str += "size="+x["size"] if x["file"] != "": str += ",file="+x["file"] str += "\n" self.memory_info = str self.show_memory() def memory_reset(self,event=None): self.memory_info = "" self.membank = [] self.message("Memory information is reseted") def memory_ok(self,event=None): self.memory_once = 1 top = self.skyeye_body("Memory") tmp = Tix.Frame(top) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Below are the information of memory:') b.grid( row =0 ,padx=5,pady=3,sticky=W+E) str = "" for x in self.membank: str += "membank:" str += "map="+x["map"]+"," str += "type="+x["type"]+"," str += "addr="+x["addr"]+"," str += "size="+x["size"] if x["file"] != "": str += ",file="+x["file"] str += "\n" b = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='%s'%str) b.grid( row =1 ,padx=5,pady=3,sticky=W+E) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Would you want to reset?') b.grid( row =2 ,padx=5,pady=3,sticky=W+E) reset = Tix.Button(tmp, text="OK", command=self.reset_memory, width = 5, bg="red",fg="white") reset.grid( row = 3,padx=5,pady=3) tmp.grid(padx=5,pady=10) self.message("Memory information is :\n"+str) self.skyeye_redobody() def reset_memory(self): self.memory_once = 0 self.view_memory() def show_memory(self): self.message(self.memory_info) def view_info(self): top = self.skyeye_body("System information") tmp = Tix.Frame(top,padx=10,pady=15) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Below are the information of the whole system:') b.grid( row =0 ,padx=5,pady=3,sticky=W+E) str = "" str += "Cpu \t\t: %s\n"%self.cpu str += "Mainboard \t: %s\n"%self.board str += "Net \t\t: %s\n"%self.net str += "Lcd \t\t: %s\n"%self.lcd str += "Flash \t\t: %s\n"%self.flash for x in self.membank: str += "membank \t : " str += "map="+x["map"]+"," str += "type="+x["type"]+"," str += "addr="+x["addr"]+"," str += "size="+x["size"] if x["file"] != "": str += ",file="+x["file"] str += "\n" b = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='%s'%str) b.grid( row =1 ,padx=5,pady=3,sticky=W+E) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Would you want to reset ALL?') b.grid( row =2 ,padx=5,pady=3,sticky=W+E) reset = Tix.Button(tmp, text="OK", command=self.reset_all, width = 5, bg="red",fg="white") reset.grid( row = 3,padx=5,pady=3) tmp.grid(padx=5,pady=25) self.message("System information is :\n"+str) self.skyeye_redobody() def reset_all(self): self.cpu_once = 0 self.device_once = 0 self.memory_once = 0 self.cpu = "" self.board="" self.net = "" self.lcd = "" self.flash = "" self.map = "" self.type = "" self.addr = "" self.size = "" self.file = "" self.membank = [] self.memory_info = "" self.welcome() self.message("All information has been reset") def project_new(self): self.reset_all() self.message("A new project is open") def project_save(self): if self.cpu_once == 0: self.message("Cpu and Mainboard is not chosen yet") self.welcome() return if self.device_once == 0: self.message("Peripherial is not chosen yet") self.welcome() return if self.memory_once == 0: self.message("Memory is not chose yet") self.welcome() return try: tmp_fd = open("skyeye.conf.koo","w") except: self.message("./skyeye.conf.koo write failure") return top = self.skyeye_body("Write configuration file") tmp = Tix.Frame(top,padx=10,pady=25) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Below are the saved information:') b.grid( row =0 ,padx=5,pady=3,sticky=W+E) str = "cpu\t:" + self.cpu + "\n" str += "mach\t:"+ self.board + "\n" for x in self.membank: tmpp = "membank\t:map=" + x["map"] +",type=" +x["type"] + ",addr=" + x["addr"] + ",size=" + x["size"] if x["file"] != "": tmpp += ",file=" + x["file"] str += tmpp + "\n" if self.lcd != "": str += "lcd\t:state=on,type="+self.lcd+",mode=gtk\n" if self.net!= "": pass # i have to find one demo ... str += "dbct\t:state=on\n" b = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='%s'%str) b.grid( row =1 ,padx=5,pady=3,sticky=W+E) tmp_fd.write(str) tmp.grid(padx=5,pady=25) self.message("Information has been written to ./skyeye.conf.koo") self.skyeye_redobody() def execute_compile(self): pass def execute_compilecurrentfile(self): pass def execute_run(self): top = self.skyeye_body("Start running skyeye") tmp = Tix.Frame(top,padx=10,pady=15) b = Tix.Message(tmp, relief=Tix.FLAT, width=240, anchor=Tix.N, text='Below are the command to skyeye:') b.grid( row =0 ,padx=5,pady=15,sticky=W+E) tmp.grid(row =0,column =0,padx=5,pady=15,sticky=W+E) tmp = Tix.Frame(top,padx=10,pady=15) b = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='skyeye') b.grid( row =0 ,column =0,padx=5,pady=3,sticky=W+E) b = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='-e') b.grid( row =0 ,column =1,padx=5,pady=3,sticky=W+E) b = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='-c') b.grid( row =1 ,column =1,padx=5,pady=3,sticky=W+E) self.image_path = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='vmlinux') self.image_path.grid( row =0 ,column =2,padx=5,pady=3,sticky=W) self.conf_path = Tix.Message(tmp, relief=Tix.FLAT, width=440, anchor=Tix.N, text='skyeye.conf') self.conf_path.grid( row =1 ,column =2,padx=5,pady=3,sticky=W) file = Tix.FileEntry(tmp,command=self.image_path_do) file.grid( row = 0, column =3,padx=5,pady=3,sticky=W+E) file = Tix.FileEntry(tmp,command=self.conf_path_do) file.grid( row = 1, column =3,padx=5,pady=3,sticky=W+E) tmp.grid(row =1,column =0,padx=5,pady=10,sticky=W+E) tmp = Tix.Frame(top,padx=10,pady=15) tmp.grid(row =2,column =0,padx=5,pady=10,sticky=W+E) self.run = Tix.Button(tmp, text="Run", command=self.run_skyeye) self.kill = Tix.Button(tmp, text="Kill", command=self.kill_skyeye) self.kill.config(state=DISABLED) self.run.grid( row = 0, column =0,padx=5,pady=3,sticky=W+E) self.kill.grid( row = 0, column =1,padx=5,pady=3,sticky=W+E) self.skyeye_redobody() def image_path_do(self,event=None): if str(event) != "": self.image_path.config(text=str(event)) def conf_path_do(self,event=None): if str(event) != "": self.conf_path.config(text=str(event)) def run_skyeye(self): if self.is_running == 1: self.run.config(state=DISABLED) self.kill.config(bg="red",fg="white") return self.run.config(state=DISABLED) path = "skyeye.exe -e " + self.image_path["text"] + " -c " + self.conf_path["text"] try: skyeye_process = subprocess.Popen(path) self.skyeye_id = skyeye_process.pid self.kill.config(state=NORMAL) except: pass def kill_skyeye(self): handle = win32api.OpenProcess(1,0,self.skyeye_id) win32process.TerminateProcess(handle,0) self.is_running = 0 self.run.config(state=NORMAL) self.kill.config(state=DISABLED) def execute_compileandrun(self): pass def execute_rebuildall(self): pass def execute_clean(self): pass def tools_compileroption(self): pass def tools_linkeroption(self): pass def tools_makefileoption(self): pass def window_max(self): pass def window_restore(self): pass def help_about(self): print "in help about" def destroy (self): self.root.destroy() if __name__ == '__main__': try: root = Tix.Tk() test = skyeye(root) root.mainloop() except: pass�������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/main/skyeye.h����������������������������������������������������������������0000644�0001750�0000144�00000004061�10717060474�016013� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye.h - necessary definition for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 3/21/2003 init this file. * add debug macros. * walimis <walimi@peoplemail.com.cn> * */ #ifndef __SKYEYE_H_ #define __SKYEYE_H_ #include <string.h> #include <stdio.h> #ifdef __APPLE__ #include <libkern/OSByteOrder.h> #endif #define SKYEYE_DEBUG 0 #if SKYEYE_DEBUG #define SKYEYE_DBG(msg...) fprintf(stderr, ##msg) #else #define SKYEYE_DBG(msg...) #endif #define SKYEYE_INFO(msg...) fprintf(stderr, ##msg); #define SKYEYE_ERR(msg...) fprintf(stderr, ##msg); #define SKYEYE_WARNING(msg...) fprintf(stderr, ##msg); #ifndef i8 #define i8 char #define i16 short #define i32 int #define i64 long long #endif /*i8 */ #ifndef u8 #define u8 unsigned char #define u16 unsigned short #define u32 unsigned int #define u64 unsigned long long #endif /*u8 */ #ifndef min #define min(x,y) (((x) < (y)) ? (x) : (y)) #endif #ifndef max #define max(x,y) (((x) > (y)) ? (x) : (y)) #endif #ifndef NULL #define NULL ((void *)0) #endif #ifdef DEBUG #define d_msg log_msg #else #define d_msg(args...) #endif //chy 2006-04-24 extern void skyeye_exit(int ret); #define err_msg(fmt, args...) fprintf(stderr, "%s %d: %s %s " fmt, __FILE__, __LINE__, __FUNCTION__, \ strerror(errno), ## args) #endif /* __SKYEYE_H_ */ �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/��������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015152� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/skyeye2gdb.h��������������������������������������������������������0000644�0001750�0000144�00000003744�10602143035�017405� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������ /* debugger.h - necessary definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/04/2005 ksh <blackfin.kang@gmail.com> * */ #ifndef __SKYEYE2GDB_H__ #define __SKYEYE2GDB_H__ #include "gdb_tracepoint.h" //chy 2006-04-12 add ICE Simulation //chy 2006-04-12 define skyeye_ice struct #define MAX_BREAKPOINTS 16 #define MAX_TRACEPOINTS 16 #define MAX_ACTION_LENGTH 80 struct SkyEye_ICE{ unsigned int bps[MAX_BREAKPOINTS]; int num_bps; trace_status tps_status; // is tracing enabled or disabled ? tracepoint_def tps[MAX_TRACEPOINTS]; // tracepoints array int num_tps; frame_buffer *fb; // frames linked list int num_fb; frame_buffer *selected_fb; ro_region *ro_region_head; }; extern struct SkyEye_ICE skyeye_ice; struct register_defs{ char * name; int (*register_raw_size)(int x); int register_bytes; int (*register_byte)(int x); int num_regs; int max_register_raw_size; int endian_flag; int pc_regnum; int sp_regnum; int fp_regnum; int (*store_register)(int rn, unsigned char * memory); int (*fetch_register)(int rn, unsigned char * memory); }; typedef struct register_defs register_defs_t; #endif ����������������������������skyeye-1.2.5_REL/utils/debugger/bfin_regdefs.c������������������������������������������������������0000644�0001750�0000144�00000006667�10545723760�017773� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* bfin_regdefs.c - necessary blackfin definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/21/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "skyeye2gdb.h" #include "skyeye_defs.h" #include "bfin-sim.h" /* * 32:r0 32:r1 32:r2 32:r3 32:r4 32:r5 32:r6 32:r7 32:p0 32:p1 32:p2 32:p3 32:p4 32:p5 32:sp 32:fp 32:i0 32:i1 32:i2 32:i3 32:m0 32:m1 32:m2 32:m3 32:b0 32:b1 32:b2 32:b3 32:l0 32:l1 32:l2 32:l3 32:a0x 32:a0w 32:a1x 32:a1w 32:astat 32:rets 32:lc0 32:lt0 32:lb0 32:lc1 32:lt1 32:lb1 32:cycles 32:cycles2 32:usp 32:seqstat 32:syscfg 32:reti 32:retx 32:retn 32:rete 32:pc 32:cc 32:text_addr 32:text_end_addr 32:data_addr 32:fpdic_exec 32:fpdic_interp 32:ipend */ #define BFIN_NUM_REGS 61 static int bfin_register_raw_size(int x){ return 4; } static int bfin_register_byte(int x){ return (4 * x); } static int bfin_store_register(int x, unsigned char * memory){ uint32_t val = frommem(memory); if(x >= 0 && x < 16) DPREG(x) = val; else if(x == 45) RETSREG = val; else if(x == 49) RETIREG = val; else if(x == 50) RETXREG = val; else if(x == 51) RETNREG = val; else if(x == 52) RETEREG = val; else if(x == 53) PCREG = val; else if(x == 54) CCREG = val; else if(x >= 0 && x < BFIN_NUM_REGS) return 0; else return -1; } static int bfin_fetch_register(int x,unsigned char * memory){ uint32_t val; if(x >= 0 && x < 16) val = DPREG(x); else if(x == 45) val = RETSREG; else if(x == 49) val = RETIREG; else if(x == 50) val = RETXREG; else if(x == 51) val = RETNREG; else if(x == 52) val = RETEREG; else if(x == 53) val = PCREG; else if(x == 54) val = CCREG; else if(x >= 0 && x < BFIN_NUM_REGS) val = 0; else return -1; /* wrong register number */ tomem(memory, val); return 0; } static register_defs_t bfin_reg_defs; /* * register blackfin register type to the array */ void init_bfin_register_defs(void){ /* initialize the struct of blackfin register defination */ bfin_reg_defs.name = "blackfin"; bfin_reg_defs.register_raw_size = bfin_register_raw_size; bfin_reg_defs.register_bytes = BFIN_NUM_REGS * 4; bfin_reg_defs.register_byte = bfin_register_byte; bfin_reg_defs.num_regs = BFIN_NUM_REGS; bfin_reg_defs.max_register_raw_size = 4; bfin_reg_defs.store_register = bfin_store_register; bfin_reg_defs.fetch_register = bfin_fetch_register; register_reg_type(&bfin_reg_defs); } �������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/gdbserver.c���������������������������������������������������������0000644�0001750�0000144�00000065756�11006122272�017325� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* debugger: Remote server for GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "skyeye2gdb.h" #include "skyeye_types.h" #include <setjmp.h> #include <stdio.h> #include <string.h> #include <sys/file.h> #ifdef __BEOS__ #include <BeBuild.h> #endif //koodailar remove it for mingw 2005.12.18-------------------------------------- #ifndef __MINGW32__ // Anthony Lee 2007-02-02 : for BeOS R5.0.x #if (defined(__BEOS__) && B_BEOS_VERSION < 0x510) #include <net/socket.h> #define PF_INET AF_INET #else #include <sys/select.h> #include <netinet/in.h> #include <sys/socket.h> #include <netdb.h> #include <netinet/tcp.h> #include <sys/ioctl.h> #endif #endif //end -------------------------------------------------------------------------- #include <signal.h> #include <fcntl.h> // Anthony Lee 2006-08-22 : for WinSock2 #ifdef __MINGW32__ #undef WORD #undef byte #include <windows.h> #endif #if (defined(__MINGW32__) || (defined(__BEOS__) && B_BEOS_VERSION < 0x510)) #define Read(a, b, c) recv(a, b, c, 0) #define Write(a, b, c) send(a, b, c, 0) #define Close(a) closesocket(a) #else #define Read(a, b, c) read(a, b, c) #define Write(a, b, c) write(a, b, c) #define Close(a) close(a) #endif #undef DEBUG_RDI //#define DEBUG_RDI #ifdef DEBUG_RDI #define DBG_RDI(args...) printf(args) #else #define DBG_RDI(args...) #endif extern register_defs_t *current_reg_type; typedef unsigned long CORE_ADDR; #ifdef DEBUG_RDI int remote_debug = 1; #else int remote_debug = 0; #endif static int remote_desc; jmp_buf toplevel; int extended_protocol; int general_thread; int cont_thread; unsigned char *registers; struct SkyEye_ICE skyeye_ice; /* Open a connection to a remote debugger. NAME is the filename used for communication. */ void remote_open (char *name) { int save_fcntl_flags; char *port_str; int port; struct sockaddr_in sockaddr; int tmp; struct protoent *protoent; int tmp_desc; port_str = strchr (name, ':'); port = atoi (port_str + 1); #ifndef __MINGW32__ if ((tmp_desc = socket (PF_INET, SOCK_STREAM, 0)) < 0) perror ("Can't open socket"); #else if ((tmp_desc = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP)) == INVALID_SOCKET) perror("Can't open socket"); #endif /* Allow rapid reuse of this port. */ tmp = 1; setsockopt (tmp_desc, SOL_SOCKET, SO_REUSEADDR, (char *) &tmp, sizeof (tmp)); sockaddr.sin_family = PF_INET; sockaddr.sin_port = htons (port); sockaddr.sin_addr.s_addr = INADDR_ANY; if (bind (tmp_desc, (struct sockaddr *) &sockaddr, sizeof (sockaddr)) || listen (tmp_desc, 1)) perror ("Can't bind address"); tmp = sizeof (sockaddr); remote_desc = accept (tmp_desc, (struct sockaddr *) &sockaddr, &tmp); if (remote_desc == -1) perror ("Accept failed"); /* 2007-02-02 disabled on BeOS R5.0.x by Anthony Lee */ #if !(defined(__BEOS__) && B_BEOS_VERSION < 0x510) /* Enable TCP keep alive process. */ tmp = 1; setsockopt (tmp_desc, SOL_SOCKET, SO_KEEPALIVE, (char *) &tmp, sizeof (tmp)); /* Tell TCP not to delay small packets. This greatly speeds up interactive response. */ tmp = 1; setsockopt (remote_desc, 6 /* PROTO_TCP */ , TCP_NODELAY, (char *) &tmp, sizeof (tmp)); #endif Close (tmp_desc); /* No longer need this */ #ifndef __MINGW32__ signal (SIGPIPE, SIG_IGN); /* If we don't do this, then gdbserver simply exits when the remote side dies. */ #endif #if 0 //chy 20050729------------------- #if defined(F_SETFL) && defined (FASYNC) save_fcntl_flags = fcntl (remote_desc, F_GETFL, 0); fcntl (remote_desc, F_SETFL, save_fcntl_flags | FASYNC); disable_async_io (); #endif /* FASYNC */ #endif //chy 20050729------------------- fprintf (stderr, "Remote debugging using %s\n", name); } void remote_close () { Close (remote_desc); } /* Convert hex digit A to a number. */ static int fromhex (int a) { if (a >= '0' && a <= '9') return a - '0'; else if (a >= 'a' && a <= 'f') return a - 'a' + 10; else if (a >= 'A' && a <= 'F') return a - 'A' + 10; else perror ("Reply contains invalid hex digit"); } /* Convert number NIB to a hex digit. */ static int tohex (int nib) { if (nib < 10) return '0' + nib; else return 'a' + nib - 10; } /* Send a packet to the remote machine, with error checking. The data of the packet is in BUF. Returns >= 0 on success, -1 otherwise. */ int putpkt (char *buf) { int i; unsigned char csum = 0; char buf2[2000]; char buf3[1]; int cnt = strlen (buf); char *p; /* Copy the packet into buffer BUF2, encapsulating it and giving it a checksum. */ p = buf2; *p++ = '$'; for (i = 0; i < cnt; i++) { csum += buf[i]; *p++ = buf[i]; } *p++ = '#'; *p++ = tohex ((csum >> 4) & 0xf); *p++ = tohex (csum & 0xf); *p = '\0'; /* Send it over and over until we get a positive ack. */ do { int cc; if (Write (remote_desc, buf2, p - buf2) != p - buf2) { perror ("putpkt(write)"); return -1; } if (remote_debug) DBG_RDI ("putpkt (\"%s\"); [looking for ack]\n", buf2); cc = Read (remote_desc, buf3, 1); if (remote_debug) DBG_RDI ("[received '%c' (0x%x)]\n", buf3[0], buf3[0]); if (cc <= 0) { if (cc == 0) fprintf (stderr, "putpkt(read): Got EOF\n"); else perror ("putpkt(read)"); return -1; } } while (buf3[0] != '+'); return 1; /* Success! */ } /* 2007-02-02 disabled by Anthony Lee : not used */ #if 0 /* Come here when we get an input interrupt from the remote side. This interrupt should only be active while we are waiting for the child to do something. About the only thing that should come through is a ^C, which will cause us to send a SIGINT to the child. */ static void input_interrupt () { int cc; char c; cc = Read (remote_desc, &c, 1); if (cc != 1 || c != '\003') { fprintf (stderr, "input_interrupt, cc = %d c = %d\n", cc, c); return; } DBG_RDI ("SkyEye debugger: input_interrupt: get a ctrl-c\n"); skyeye_exit (-1); //kill (inferior_pid, SIGINT); } void enable_async_io () { signal (SIGIO, input_interrupt); } void disable_async_io () { signal (SIGIO, SIG_IGN); } #endif /* Returns next char from remote GDB. -1 if error. */ static int readchar () { static char buf[BUFSIZ]; static int bufcnt = 0; static char *bufp; if (bufcnt-- > 0) return *bufp++ & 0x7f; bufcnt = Read (remote_desc, buf, sizeof (buf)); if (bufcnt <= 0) { if (bufcnt == 0) fprintf (stderr, "readchar: Got EOF\n"); else perror ("readchar"); return -1; } bufp = buf; bufcnt--; return *bufp++ & 0x7f; } /* Read a packet from the remote machine, with error checking, and store it in BUF. Returns length of packet, or negative if error. */ int getpkt (char *buf) { char *bp; unsigned char csum, c1, c2; int c; while (1) { csum = 0; while (1) { c = readchar (); if (c == '$') break; if (remote_debug) DBG_RDI ("[getpkt: discarding char '%c']\n", c); if (c < 0) return -1; } bp = buf; while (1) { c = readchar (); if (c < 0) return -1; if (c == '#') break; *bp++ = c; csum += c; } *bp = 0; c1 = fromhex (readchar ()); c2 = fromhex (readchar ()); if (csum == (c1 << 4) + c2) break; fprintf (stderr, "Bad checksum, sentsum=0x%x, csum=0x%x, buf=%s\n", (c1 << 4) + c2, csum, buf); Write (remote_desc, "-", 1); } if (remote_debug) DBG_RDI ("getpkt (\"%s\"); [sending ack] \n", buf); Write (remote_desc, "+", 1); if (remote_debug) DBG_RDI ("[sent ack]\n"); return bp - buf; } void write_ok (char *buf) { buf[0] = 'O'; buf[1] = 'K'; buf[2] = '\0'; } void write_enn (char *buf) { buf[0] = 'E'; buf[1] = '0'; buf[2] = '1'; buf[3] = '\0'; } static void convert_int_to_ascii (char *from, char *to, int n) { int nib; char ch; while (n--) { ch = *from++; nib = ((ch & 0xf0) >> 4) & 0x0f; *to++ = tohex (nib); nib = ch & 0x0f; *to++ = tohex (nib); } *to++ = 0; } static void convert_ascii_to_int (char *from, char *to, int n) { int nib1, nib2; while (n--) { nib1 = fromhex (*from++); nib2 = fromhex (*from++); *to++ = (((nib1 & 0x0f) << 4) & 0xf0) | (nib2 & 0x0f); } } static char * outreg (int regno, char *buf) { int regsize = current_reg_type->register_raw_size(regno); *buf++ = tohex (regno >> 4); *buf++ = tohex (regno & 0xf); *buf++ = ':'; convert_int_to_ascii (®isters[current_reg_type->register_byte (regno)], buf, regsize); buf += 2 * regsize; *buf++ = ';'; return buf; } void prepare_resume_reply (char *buf, char status, unsigned char signo) { int nib; *buf++ = status; /* FIXME! Should be converting this signal number (numbered according to the signal numbering of the system we are running on) to the signal numbers used by the gdb protocol (see enum target_signal in gdb/target.h). */ nib = ((signo & 0xf0) >> 4); *buf++ = tohex (nib); nib = signo & 0x0f; *buf++ = tohex (nib); if (status == 'T') { buf = outreg (current_reg_type->pc_regnum, buf); buf = outreg (current_reg_type->fp_regnum, buf); buf = outreg (current_reg_type->sp_regnum, buf); } /* For W and X, we're done. */ *buf++ = 0; } static void decode_m_packet (char *from, CORE_ADDR * mem_addr_ptr, unsigned int *len_ptr) { int i = 0, j = 0; char ch; *mem_addr_ptr = *len_ptr = 0; while ((ch = from[i++]) != ',') { *mem_addr_ptr = *mem_addr_ptr << 4; *mem_addr_ptr |= fromhex (ch) & 0x0f; } for (j = 0; j < 4; j++) { if ((ch = from[i++]) == 0) break; *len_ptr = *len_ptr << 4; *len_ptr |= fromhex (ch) & 0x0f; } } static void decode_M_packet (char *from, CORE_ADDR * mem_addr_ptr, unsigned int *len_ptr, char *to) { int i = 0; char ch; *mem_addr_ptr = *len_ptr = 0; while ((ch = from[i++]) != ',') { *mem_addr_ptr = *mem_addr_ptr << 4; *mem_addr_ptr |= fromhex (ch) & 0x0f; } while ((ch = from[i++]) != ':') { *len_ptr = *len_ptr << 4; *len_ptr |= fromhex (ch) & 0x0f; } convert_ascii_to_int (&from[i++], to, *len_ptr); } static void decode_DP_playload (char * buffer, int tp_id, action *parent_action) { int i=0; char ch; action* current_action; unsigned int remaining_step; unsigned int pass_count,remaining_pass; unsigned int mask; unsigned offset, length; int base_reg; switch (buffer[i]) { case 'E': { i=i+2; remaining_step=0; while ((ch = buffer[i++]) != ':') { remaining_step = remaining_step << 4; remaining_step |= fromhex (ch) & 0x0f; } pass_count=0; while (((ch = buffer[i]) != '-') &&((ch = buffer[i]) != '\0')) { pass_count = pass_count << 4; pass_count |= fromhex (ch) & 0x0f; i++; } set_tracepoint_status(tp_id, TRACEPOINT_ENABLED); set_tracepoint_remaining_step(tp_id, remaining_step ); set_tracepoint_pass_count(tp_id, pass_count ); set_tracepoint_remaining_pass(tp_id, pass_count ); } break; case 'D': { i=i+2; remaining_step=0; while ((ch = buffer[i++]) != ':') { remaining_step = remaining_step << 4; remaining_step |= fromhex (ch) & 0x0f; } pass_count=0; while (((ch = buffer[i]) != '-') &&((ch = buffer[i]) != '\0')) { pass_count = pass_count << 4; pass_count |= fromhex (ch) & 0x0f; i++; } set_tracepoint_status(tp_id, TRACEPOINT_DISABLED); set_tracepoint_remaining_step(tp_id, remaining_step ); set_tracepoint_pass_count(tp_id, pass_count ); set_tracepoint_remaining_pass(tp_id, pass_count ); } break; case 'R': { i++; mask=0; while (((ch = buffer[i]) != '-') &&((ch = buffer[i]) != '\0')) { mask = mask << 4; mask |= fromhex (ch) & 0x0f; i++; } current_action = prepare_action(tp_id, parent_action); set_action_type (current_action, ACTION_COLLECT); set_action_data_type(current_action,COLLECT_REGISTERS); set_rc_action_mask(current_action, mask); } break; case 'M': { i++; //get base_reg if (buffer[i]=='-') { base_reg=-1; while ((ch = buffer[i++]) != ','); } else { base_reg=0; i++; while (((ch = buffer[i]) != ',') &&((ch = buffer[i]) != '\0')) { base_reg = base_reg << 4; base_reg |= fromhex (ch) & 0x0f; i++; } } //get offset offset=0; while (((ch = buffer[i]) != ',') &&((ch = buffer[i]) != '\0')) { offset = offset << 4; offset |= fromhex (ch) & 0x0f; i++; } //get_length length=0; i++; while (((ch = buffer[i]) != '-') &&((ch = buffer[i]) != '\0')) { length = length << 4; length |= fromhex (ch) & 0x0f; i++; } current_action = prepare_action(tp_id, parent_action); set_action_type (current_action, ACTION_COLLECT); set_action_data_type(current_action,COLLECT_MEMORY); set_mc_action_base_reg(current_action,base_reg); set_mc_action_offset(current_action,offset); set_mc_action_length(current_action,length); } break; case 'X': break; case 'S': { i++; current_action = prepare_action(tp_id, parent_action); set_action_type (current_action, ACTION_WHILE); set_wa_step_count(current_action,get_tracepoint_remaining_step(tp_id)); set_wa_remaining_steps(current_action,get_tracepoint_remaining_step(tp_id)); decode_DP_playload (&buffer[i], tp_id, current_action); } break; default :; } } static void decode_DP_packet(char * buffer, char * response) { int i=0; int cont=0; char ch; unsigned int tp_number =0; unsigned int tp_address=0; int tp_id=-1; //tp_id is the position of the tracepoint on the skyeye_ice.tps array if (buffer [0]=='-') { i=1; cont= 1; } //getting tp_number while ((ch = buffer[i++]) != ':') { tp_number = tp_number << 4; tp_number |= fromhex (ch) & 0x0f; } //getting tp_address while ((ch = buffer[i++]) != ':') { tp_address = tp_address << 4; tp_address |= fromhex (ch) & 0x0f; } if ((tp_id=find_tp_id (tp_number,tp_address))!=-1) { } else { tp_id=add_tracepoint (tp_number,tp_address); } decode_DP_playload (&buffer[i], tp_id, NULL); return; } static void decode_Frame_packet(char *buffer, char* response) { int i; char ch; unsigned int frame_number; unsigned int tracepoint_number; start_trace_focusing (); switch (buffer[0]) { case 'p': //pc { i=3; } break; case 't': //tdp { i=4; tracepoint_number=0; while ((ch = buffer[i]) != '\0') { tracepoint_number = tracepoint_number << 4; tracepoint_number |= fromhex (ch) & 0x0f; i++; } if (select_frame_buffer_by_tpn (tracepoint_number,&frame_number)) { sprintf (response,"F%xT%x",frame_number,tracepoint_number); } else { sprintf (response,"F-1"); } } break; case 'r': //range { i=6; } break; case 'o': //outside { i=8; } break; default: //a frame number or an error { i=0; frame_number=0; while ((ch = buffer[i]) != '\0') { frame_number = frame_number << 4; frame_number |= fromhex (ch) & 0x0f; i++; } //is it a tfind start none? if (frame_number==0xFFFFFFFF) { stop_trace_focusing (); sprintf (response,"OK"); }else { if (select_frame_buffer_by_fn (&tracepoint_number,frame_number)) { sprintf (response,"F%xT%x",frame_number,tracepoint_number); } else { sprintf (response,"F-1"); } } } } } static void decode_ro_packet (char *buffer,char *response) { char ch; int i; unsigned int *address; unsigned int start_address; unsigned int end_address; i=0; start_address=0; end_address=0; address = &start_address; while ((ch = buffer[i]) != '\0') { switch (ch) { case ',': { address=&end_address; i++; } break; case ':': { address = &start_address; add_ro_region(start_address, end_address); start_address=0; end_address=0; address=&start_address; i++; } break; default : { *address = *address << 4; *address |= fromhex (ch) & 0x0f; i++; } } } if ((ch==0)&&((start_address!=0)||(end_address!=0))) { add_ro_region(start_address, end_address); } sprintf(response,"OK"); } static int decode_Q_packet (char *buffer, char *response) { int i=0; //init if (buffer [i] !='T') //a valid trace request { return (0); }else { i=1; } switch (buffer [i]) { case 'i'://init { init_tracepoints(); write_ok (response); return (1); }; case 'S'://start or stop { if (buffer [i+2]=='a') //start { start_trace_recording(); write_ok (response); return (1); }else if (buffer [i+2]=='o') //stop { stop_trace_recording(); write_ok (response); return (1); }else { return (0); } }; break; case 'D'://DP { decode_DP_packet (&(buffer[i+3]),response); write_ok (response); return (1); } break; case 'F'://frame { decode_Frame_packet(&(buffer[i+6]),response); return (1); } break; case 'r': //ro { decode_ro_packet (&(buffer[i+3]),response); return (1); } default : { return (0); } } return (0); } void fetch_inferior_registers (int regno, unsigned char *memory) { if (regno == -1 || regno == 0) for (regno = 0; regno < current_reg_type->num_regs; regno++) current_reg_type->fetch_register (regno, &memory[current_reg_type->register_byte (regno)]); else current_reg_type->fetch_register (regno, &(memory[current_reg_type->register_byte (regno)])); } static void store_inferior_registers (int regno, unsigned char *memory) { if (regno == -1 || regno == 0) for (regno = 0; regno < current_reg_type->num_regs; regno++) current_reg_type->store_register (regno, &(memory[current_reg_type->register_byte (regno)])); else current_reg_type->store_register (regno, &(memory[current_reg_type->register_byte (regno)])); } int sim_debug () { static char own_buf[8000], mem_buf[8000]; char *p; char ch, status; int i = 0; unsigned char signal; unsigned int len,addr; CORE_ADDR mem_addr; int type,size; registers = (unsigned char *)malloc(current_reg_type->register_bytes); //chy 2006-04-12 init skyeye_ice skyeye_ice.num_bps=0; if (setjmp (toplevel)) { fprintf (stderr, "Exiting\n"); skyeye_exit (1); } while (1) { remote_open ("host:12345"); restart: setjmp (toplevel); while (getpkt (own_buf) > 0) { unsigned char sig; i = 0; ch = own_buf[i++]; switch (ch) { case 'd': remote_debug = !remote_debug; break; #if 0 // chy 2005-07-30 case '!': extended_protocol = 1; prepare_resume_reply (own_buf, status, signal); break; #endif //chy case '?': status = 'S'; signal = 5; prepare_resume_reply (own_buf, status, signal); break; #if 0 // chy 2005-07-30 case 'H': switch (own_buf[1]) { case 'g': general_thread = strtol (&own_buf[2], NULL, 16); write_ok (own_buf); fetch_inferior_registers (0); break; case 'c': cont_thread = strtol (&own_buf[2], NULL, 16); write_ok (own_buf); break; default: /* Silently ignore it so that gdb can extend the protocol without compatibility headaches. */ own_buf[0] = '\0'; break; } break; #endif //chy 2005-07-30 case 'g': if (get_trace_status() == TRACE_FOCUSING) trace_fetch_registers (-1, registers); else fetch_inferior_registers (-1, registers); convert_int_to_ascii (registers, own_buf, current_reg_type->register_bytes); break; case 'G': convert_ascii_to_int (&own_buf[1], registers, current_reg_type->register_bytes); store_inferior_registers (-1, registers); write_ok (own_buf); break; case 'm': decode_m_packet (&own_buf[1], &mem_addr, &len); if ((get_trace_status() == TRACE_FOCUSING) && (is_in_ro_region(mem_addr,len) == 0)) size = trace_read (mem_addr, mem_buf, len); else size = sim_read (mem_addr, mem_buf, len); if(size!=-1) convert_int_to_ascii (mem_buf, own_buf, len); else write_enn (own_buf); break; case 'M': decode_M_packet (&own_buf[1], &mem_addr, &len, mem_buf); //chy 2005-07-30 ARM_BREAKPOINT 0xe7ffdefe //bp_opcode_conv( (unsigned int) mem_addr, (unsigned int*)mem_buf ); //chy 2006-04-12 debug //printf("SKYEYE, debugger M addr 0x%x, word 0x%x, len 0x%x\n", mem_addr, *((unsigned int *)mem_buf), len); if (sim_write (mem_addr, mem_buf, len) == len) write_ok (own_buf); else write_enn (own_buf); break; case 'Q': if (decode_Q_packet (&own_buf[1], own_buf) == 0) own_buf[0] = '\0'; break; case 'q': switch (own_buf[1]) { case 'T': //Status if (get_trace_status() == TRACE_STARTED) { own_buf[0] = 'T'; own_buf[1] = '1'; own_buf[2] = '\0'; } else { own_buf[0] = 'T'; own_buf[1] = '0'; own_buf[2] = '\0'; } break; default: own_buf[0] = '\0'; break; } break; /* chy 2005-07-28 case 'q': switch (own_buf[1]) { case 'C': own_buf[0] = '\0'; break; case 'O': send_area(own_buf); break; default: own_buf[0] = '\0'; break; } break; case 'C': convert_ascii_to_int (own_buf + 1, &sig, 1); myresume (0, sig); signal = mywait (&status); prepare_resume_reply (own_buf, status, signal); break; case 'S': convert_ascii_to_int (own_buf + 1, &sig, 1); myresume (1, sig); signal = mywait (&status); prepare_resume_reply (own_buf, status, signal); break; chy */ case 'c': //chy 2005-07-30 //ARMul_DoProg (state); //sim_resume(0); gdbserver_cont(); prepare_resume_reply (own_buf, status, signal); break; case 's': //chy 2005-07-30 //sim_resume(1); //sim_step_debug(); //myresume (1, 0); //signal = mywait (&status); gdbserver_step(); prepare_resume_reply (own_buf, status, signal); break; case 'z': { p=&(own_buf[1]); type = strtoul(p, (char **)&p, 16); if (*p == ',') p++; addr = strtoul(p, (char **)&p, 16); if (*p == ',') p++; len = strtoul(p, (char **)&p, 16); //printf("SKYEYE:gdbserver z, type %d, addr %x, len %x\n",type, addr,len); if (type == 0 || type == 1) { if (sim_ice_breakpoint_remove(addr) < 0) goto remove_breakpoint_error; write_ok(own_buf); } else { remove_breakpoint_error: write_enn(own_buf); } } break; case 'Z': { p=&(own_buf[1]); type = strtoul(p, (char **)&p, 16); if (*p == ',') p++; addr = strtoul(p, (char **)&p, 16); if (*p == ',') p++; len = strtoul(p, (char **)&p, 16); //printf("SKYEYE:gdbserver Z, type %d, addr %x, len %x\n",type, addr,len); if (type == 0 || type == 1) { if (sim_ice_breakpoint_insert(addr) < 0) goto insert_breakpoint_error; write_ok(own_buf); } else { insert_breakpoint_error: write_enn(own_buf); } } break; #if 0 // chy 2005-07-30 case 'k': fprintf (stderr, "Killing inferior\n"); kill_inferior (); /* When using the extended protocol, we start up a new debugging session. The traditional protocol will exit instead. */ if (extended_protocol) { write_ok (own_buf); fprintf (stderr, "GDBserver restarting\n"); /* Wait till we are at 1st instruction in prog. */ //chy 20050729 go to restart //signal = start_inferior (&argv[2], &status); goto restart; break; } else { exit (0); break; } case 'T': if (mythread_alive (strtol (&own_buf[1], NULL, 16))) write_ok (own_buf); else write_enn (own_buf); break; case 'R': /* Restarting the inferior is only supported in the extended protocol. */ if (extended_protocol) { kill_inferior (); write_ok (own_buf); fprintf (stderr, "GDBserver restarting\n"); /* Wait till we are at 1st instruction in prog. */ //chy 20050729 go to restart //signal = start_inferior (&argv[2], &status); goto restart; break; } else { /* It is a request we don't understand. Respond with an empty packet so that gdb knows that we don't support this request. */ own_buf[0] = '\0'; break; } #endif //chy 2005-07-30 default: /* It is a request we don't understand. Respond with an empty packet so that gdb knows that we don't support this request. */ DBG_RDI(stderr,"unknown command: %c\n",ch); own_buf[0] = '\0'; break; } putpkt (own_buf); if (status == 'W') fprintf (stderr, "\nChild exited with status %d\n", sig); if (status == 'X') fprintf (stderr, "\nChild terminated with signal = 0x%x\n", sig); if (status == 'W' || status == 'X') { if (extended_protocol) { //chy 2005-07-30 fprintf (stderr, "CHY SkyEye: not Killing inferior\n"); //kill_inferior (); write_ok (own_buf); fprintf (stderr, "GDBserver restarting\n"); /* Wait till we are at 1st instruction in prog. */ //chy 20050729 go to restart //signal = start_inferior (&argv[2], &status); goto restart; break; } else { fprintf (stderr, "GDBserver exiting\n"); skyeye_exit (0); } } } /* We come here when getpkt fails. For the extended remote protocol we exit (and this is the only way we gracefully exit!). For the traditional remote protocol close the connection, and re-open it at the top of the loop. */ if (extended_protocol) { remote_close (); skyeye_exit (0); } else { fprintf (stderr, "Remote side has terminated connection. GDBserver will reopen the connection.\n"); remote_close (); } } } /* * stop when press Ctrl+c */ int remote_interrupt() { static fd_set rfds; static struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; FD_ZERO( &rfds ); FD_SET( remote_desc, &rfds ); if (select( remote_desc+1, &rfds, NULL, NULL, &tv ) == 1 ) { int n; static char buf[100]; n = Read( remote_desc, buf, sizeof(buf) ); if ( n > 0 ) DBG_RDI("Got async char"); if ( buf[0] == '\003' ) DBG_RDI(":Ctrl+C, interrupted.\n"); return 1; } return 0; } ������������������skyeye-1.2.5_REL/utils/debugger/arch_regdefs.c������������������������������������������������������0000644�0001750�0000144�00000005175�10607305623�017754� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* arm_regdefs.c - necessary arm definition for skyeye debugger Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "skyeye_arch.h" #include "skyeye_config.h" #include "skyeye2gdb.h" #include "skyeye_defs.h" register_defs_t *register_types[MAX_SUPP_ARCH]; void register_reg_type(register_defs_t * reg_type){ int i; for (i = 0; i < MAX_SUPP_ARCH; i++) { if (register_types[i] == NULL) { register_types[i] = reg_type; return; } } } extern void init_arm_register_defs(); extern void init_bfin_register_defs(); extern void init_mips_register_defs(); extern void init_cf_register_defs(); extern void init_ppc_register_defs(); extern skyeye_config_t skyeye_config; register_defs_t * current_reg_type; /* * Initializing all register type for supported architechtures */ int init_register_type(){ int i; if(!skyeye_config.arch){ fprintf(stderr,"architecture is not initialized.\n"); return -1; } for (i = 0; i < MAX_SUPP_ARCH; i++) { register_types[i] = NULL; } /* register arm_arch */ init_arm_register_defs (); /*register bfin_arch */ init_bfin_register_defs (); /* register mips_arch */ init_mips_register_defs (); /* register coldfire_arch */ init_cf_register_defs (); /* register ppc_arch */ init_ppc_register_defs (); for (i = 0; i < MAX_SUPP_ARCH; i++){ if(register_types[i] != NULL) if(!strcmp(skyeye_config.arch->arch_name, register_types[i]->name)) current_reg_type = register_types[i]; } if(!current_reg_type){ fprintf(stderr, " Can not find register type for current arch!\n"); return -1; } else return 0; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/gdb_tracepoint.c����������������������������������������������������0000644�0001750�0000144�00000050035�10602143035�020307� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* debugger.h - necessary definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "skyeye2gdb.h" #include <stdio.h> #include <stdlib.h> #include <string.h> extern void fetch_inferior_registers (int regno, unsigned char *memory); extern register_defs_t *current_reg_type; int add_tracepoint (unsigned int tp_number,unsigned int tp_address) { if (skyeye_ice.num_tps<MAX_TRACEPOINTS) { skyeye_ice.tps[skyeye_ice.num_tps].tp_address=tp_address; skyeye_ice.tps[skyeye_ice.num_tps].number=tp_number; set_tracepoint_status(skyeye_ice.num_tps, TRACEPOINT_DISABLED); skyeye_ice.tps[skyeye_ice.num_tps].pass_count=0; skyeye_ice.tps[skyeye_ice.num_tps].remaining_pass=0; skyeye_ice.tps[skyeye_ice.num_tps].remaining_step=0; skyeye_ice.num_tps++; return(skyeye_ice.num_tps-1); } else { return (-1); } } int find_tp_id (unsigned int tp_number,unsigned int tp_address) { int i; for (i=0;i<skyeye_ice.num_tps;i++) { if ((skyeye_ice.tps[i].number==tp_number)&&(skyeye_ice.tps[i].tp_address==tp_address)) return(i); } return(-1); } void set_tracepoint_status(int tp_id, tracepoint_status status) { skyeye_ice.tps[tp_id].status=status; } tracepoint_status get_tracepoint_status(int tp_id) { return (skyeye_ice.tps[tp_id].status); } void set_tracepoint_address(int tp_id, unsigned int address ) { skyeye_ice.tps[tp_id].tp_address=address; } unsigned int get_tracepoint_address(int tp_id) { return (skyeye_ice.tps[tp_id].tp_address); } void set_tracepoint_number(int tp_id, unsigned int number ) { skyeye_ice.tps[tp_id].number=number; } unsigned int get_tracepoint_number(int tp_id) { return (skyeye_ice.tps[tp_id].number); } void set_tracepoint_pass_count(int tp_id, unsigned int pass_count ) { skyeye_ice.tps[tp_id].pass_count=pass_count; } unsigned int get_tracepoint_pass_count(int tp_id) { return (skyeye_ice.tps[tp_id].pass_count); } void set_tracepoint_remaining_pass(int tp_id, unsigned int remaining_pass ) { skyeye_ice.tps[tp_id].remaining_pass=remaining_pass; } unsigned int get_tracepoint_remaining_pass(int tp_id) { return (skyeye_ice.tps[tp_id].remaining_pass); } void set_tracepoint_remaining_step(int tp_id, unsigned int remaining_step ) { skyeye_ice.tps[tp_id].remaining_step=remaining_step; } unsigned int get_tracepoint_remaining_step(int tp_id) { return (skyeye_ice.tps[tp_id].remaining_step); } void populate_default_action(action * current_action) { current_action->type=ACTION_UNASSIGNED; current_action->sibling=NULL; current_action->child=NULL; } action* prepare_action(int tp_id, action *parent_action) { action * current; if (parent_action==NULL) //we are not in a while-stepping case { if(skyeye_ice.tps[tp_id].actions ==NULL) { skyeye_ice.tps[tp_id].actions=(action *)malloc(sizeof(action)); populate_default_action(skyeye_ice.tps[tp_id].actions); return(skyeye_ice.tps[tp_id].actions); } else { current =skyeye_ice.tps[tp_id].actions; } } else { if(parent_action->child ==NULL) { parent_action->child=(action *)malloc(sizeof(action)); populate_default_action(parent_action->child); return(parent_action->child); } else { current =parent_action->child; } } while (current->sibling!=NULL) { current=current->sibling; } current->sibling=(action *)malloc(sizeof(action)); populate_default_action(current->sibling); return(current->sibling); } void set_action_type (action *action_p, action_type type) { action_p->type=type; } action_type get_action_type (action *action_p) { return (action_p->type); } void set_action_data_type(action *action_p, collect_action_type type ) { action_p->action_data.ca.type=type; } collect_action_type get_action_data_type(action *action_p) { return (action_p->action_data.ca.type); } void set_wa_step_count (action *action_p, unsigned int step_count) { action_p->action_data.wa.step_count=step_count; } unsigned int get_wa_step_count (action *action_p) { return (action_p->action_data.wa.step_count); } void set_wa_remaining_steps (action *action_p, unsigned int remaining_steps) { action_p->action_data.wa.remaining_steps=remaining_steps; } void set_rc_action_mask( action *action_p, unsigned int mask) { action_p->action_data.ca.description.rc.mask=mask; } void set_mc_action_base_reg(action *action_p, unsigned int base_reg) { action_p->action_data.ca.description.mc.base_reg=base_reg; } void set_mc_action_offset(action *action_p, unsigned int offset) { action_p->action_data.ca.description.mc.offset=offset; } void set_mc_action_length(action *action_p, unsigned int length) { action_p->action_data.ca.description.mc.length=length; } void delete_action (action * current_action) { //post fix iteration in a binary tree if (current_action->sibling!=NULL) { delete_action(current_action->sibling); current_action->sibling=NULL; } if (current_action->child!=NULL) { delete_action(current_action->child); current_action->child=NULL; } if ((current_action->sibling==NULL)&&(current_action->child==NULL)) { free(current_action); } } void clear_ro_regions(void) { ro_region * previous_ro_region ,*next_ro_region; if (skyeye_ice.ro_region_head!=NULL) { next_ro_region = skyeye_ice.ro_region_head; while(next_ro_region!=NULL) { previous_ro_region=next_ro_region; next_ro_region=next_ro_region->next; free(previous_ro_region); } skyeye_ice.ro_region_head=NULL; } } int is_in_ro_region(unsigned int addr, int length) { ro_region *current_ro_region; if (skyeye_ice.ro_region_head==NULL) { return 0; } current_ro_region=skyeye_ice.ro_region_head; while(current_ro_region!=NULL) { if ((current_ro_region->start <=addr)&&(current_ro_region->end >=addr+length)) { return (1); } current_ro_region=current_ro_region->next; } return (0); } void add_ro_region(unsigned int start, unsigned int end) { ro_region *current_ro_region; if (skyeye_ice.ro_region_head!=NULL) { current_ro_region=skyeye_ice.ro_region_head; while(current_ro_region->next !=NULL) { current_ro_region=current_ro_region->next; } current_ro_region->next=(ro_region *)malloc (sizeof(ro_region)); current_ro_region=current_ro_region->next; } else { skyeye_ice.ro_region_head=(ro_region *)malloc (sizeof(ro_region)); current_ro_region=skyeye_ice.ro_region_head; } current_ro_region->start=start; current_ro_region->end=end; current_ro_region->next=NULL; } void clear_collect_records(collect_record *head_record) { collect_record * previous_collect_record ,*next_collect_record; if (head_record!=NULL) { next_collect_record = head_record; while(next_collect_record!=NULL) { previous_collect_record=next_collect_record; next_collect_record=next_collect_record->next; free(previous_collect_record); } } } void clear_frame_buffers(void) { frame_buffer * previous_frame_buffer ,*next_frame_buffer; if (skyeye_ice.fb!=NULL) { next_frame_buffer = skyeye_ice.fb; while(next_frame_buffer!=NULL) { previous_frame_buffer=next_frame_buffer; next_frame_buffer=next_frame_buffer->next; clear_collect_records(previous_frame_buffer->head_record); free(previous_frame_buffer); } skyeye_ice.fb=NULL; skyeye_ice.num_fb =0; } } frame_buffer * add_frame_buffer ( void ) { frame_buffer * current_frame_buffer; current_frame_buffer = skyeye_ice.fb; if (skyeye_ice.fb ==NULL) { skyeye_ice.fb= (frame_buffer *)malloc (sizeof(frame_buffer)); current_frame_buffer=skyeye_ice.fb; } else { while (current_frame_buffer ->next !=NULL) { current_frame_buffer = current_frame_buffer ->next; } current_frame_buffer ->next =(frame_buffer *)malloc (sizeof(frame_buffer)); current_frame_buffer=current_frame_buffer ->next; } // set every thing to default current_frame_buffer->tp_number=0; current_frame_buffer->frame_number=skyeye_ice.num_fb; current_frame_buffer->head_record=NULL; current_frame_buffer->next=NULL; skyeye_ice.num_fb++; return (current_frame_buffer); } void trace_fetch_registers(int regno, unsigned char *memory) { collect_record *current_record; if(skyeye_ice.selected_fb!=NULL) { current_record=skyeye_ice.selected_fb->head_record; while (current_record!=NULL) { if (current_record->ca->type ==COLLECT_REGISTERS) { memcpy (memory,current_record->collect_data,current_record->collect_data_length); return; } else { current_record=current_record->next; } } } } int trace_read (unsigned int addr, unsigned char *buffer, int size) { collect_record *current_record; if(skyeye_ice.selected_fb!=NULL) { current_record=skyeye_ice.selected_fb->head_record; while (current_record!=NULL) { if (current_record->ca->type ==COLLECT_MEMORY) { if ((addr >=current_record->ca->description.mc.offset)&&(addr+size<=current_record->ca->description.mc.offset+current_record->ca->description.mc.length)) { memcpy (buffer,(current_record->collect_data)+(addr-current_record->ca->description.mc.offset),size); return (size); } else { current_record=current_record->next; } } else { current_record=current_record->next; } } } return (-1) ; } int select_frame_buffer_by_fn (int *tracepoint_number,int frame_number) { frame_buffer * current_fb; if ( frame_number >skyeye_ice.num_fb) { //the frame couldn't be found return (0); } else { skyeye_ice.selected_fb=skyeye_ice.fb; current_fb=skyeye_ice.selected_fb; while (current_fb !=NULL) { if (current_fb->frame_number==frame_number) { skyeye_ice.selected_fb=current_fb; *tracepoint_number=skyeye_ice.selected_fb->tp_number; return(1); } else { current_fb=current_fb->next; } } } return (0); } int select_frame_buffer_by_tpn (int tracepoint_number, int *frame_number) { frame_buffer * current_fb; if (skyeye_ice.selected_fb==NULL) { skyeye_ice.selected_fb=skyeye_ice.fb; } if (skyeye_ice.selected_fb ==NULL) return (0); current_fb=skyeye_ice.selected_fb->next; while (current_fb !=NULL) { if (current_fb->tp_number==tracepoint_number) { skyeye_ice.selected_fb=current_fb; *frame_number=skyeye_ice.selected_fb->frame_number; return(1); } else { current_fb=current_fb->next; } } return (0); } void do_action (unsigned int tp_id, action * current_action, frame_buffer * record_fb) { int size; unsigned char * buffer ; collect_record * current_collect_record; unsigned int base_reg_val; unsigned char *registers; //point to the lase record in the frame buffer if (record_fb==NULL) return; if (record_fb->head_record !=NULL) { current_collect_record =record_fb->head_record; while (current_collect_record->next !=NULL) { current_collect_record = current_collect_record->next; } current_collect_record->next = (collect_record *) malloc (sizeof (collect_record)); current_collect_record=current_collect_record->next; } else { record_fb->head_record = (collect_record *) malloc (sizeof (collect_record)); current_collect_record=record_fb->head_record; } if (current_action!=NULL) { switch (current_action->type) { case ACTION_COLLECT : { switch (current_action->action_data.ca.type) { case COLLECT_REGISTERS: { current_collect_record->collect_data= (char *)malloc (current_reg_type->register_bytes); fetch_inferior_registers (-1, current_collect_record ->collect_data); current_collect_record->collect_data_length=current_reg_type->register_bytes; current_collect_record->ca=&(current_action->action_data.ca); current_collect_record->next=NULL; } break; case COLLECT_MEMORY: { current_collect_record->collect_data= (char *)malloc(current_action->action_data.ca.description.mc.length); //should be the content of basereg if (current_action->action_data.ca.description.mc.base_reg == -1) { base_reg_val=0; } else { registers = (unsigned char *)malloc(current_reg_type->register_bytes); fetch_inferior_registers (current_action->action_data.ca.description.mc.base_reg, registers); base_reg_val=registers[current_reg_type->register_byte (current_action->action_data.ca.description.mc.base_reg)]; free (registers); } current_collect_record->collect_data_length=sim_read (base_reg_val+current_action->action_data.ca.description.mc.offset, current_collect_record->collect_data, current_action->action_data.ca.description.mc.length); current_collect_record->ca=&(current_action->action_data.ca); current_collect_record->next=NULL; } break;; case COLLECT_EXPRESSION : ; default : break; } } break; case ACTION_WHILE :; default : break; } } } void do_action_list (unsigned int tp_id, action* actions, frame_buffer * fb) { frame_buffer *current_frame_buffer; action * current_action; current_frame_buffer =fb; current_action =actions; while (current_action !=NULL) { switch (current_action->type) { case ACTION_COLLECT: { do_action(tp_id,current_action,current_frame_buffer); fprintf (stderr," tracepoint : %x, remaining pass : %x, action collect \n",skyeye_ice.tps[tp_id].number,skyeye_ice.tps[tp_id].remaining_pass); current_action=current_action->sibling; } break; case ACTION_WHILE: { if (current_action->action_data.wa.remaining_steps !=0) { set_tracepoint_status(tp_id, TRACEPOINT_STEPPING); current_action->action_data.wa.remaining_steps--; do_action_list(tp_id,current_action->child,current_frame_buffer); fprintf (stderr," tracepoint : %x, remaining pass : %x, action stepping \n",skyeye_ice.tps[tp_id].number,skyeye_ice.tps[tp_id].remaining_pass); } if (current_action->action_data.wa.remaining_steps ==0) { set_tracepoint_status(tp_id, TRACEPOINT_ENABLED); current_action->action_data.wa.remaining_steps=current_action->action_data.wa.step_count; fprintf (stderr," tracepoint : %x, action stepping end \n",skyeye_ice.tps[tp_id].number); } current_action=current_action->sibling; } break; } } } void handle_tracepoint(int tp_id) { action * current_action; frame_buffer *current_frame_buffer; if (get_tracepoint_status(tp_id)==TRACEPOINT_STEPPING) { //find the while stepping action current_action=skyeye_ice.tps[tp_id].actions; while (current_action->type!=ACTION_WHILE) { if (current_action->sibling !=NULL) { current_action=current_action->sibling; }else { return; } } current_frame_buffer= add_frame_buffer(); current_frame_buffer->tp_number=skyeye_ice.tps[tp_id].number; //current action is a while action do_action_list (tp_id,current_action,current_frame_buffer); return; } if (get_tracepoint_status(tp_id)==TRACEPOINT_ENABLED) { if (skyeye_ice.tps[tp_id].pass_count!=0) { if (skyeye_ice.tps[tp_id].remaining_pass!=0) { //decrease the remaining_pass skyeye_ice.tps[tp_id].remaining_pass--; } else { //remaining_pass ==0, don't collect tracess return; } } current_frame_buffer= add_frame_buffer(); current_frame_buffer->tp_number=skyeye_ice.tps[tp_id].number; do_action_list (tp_id,skyeye_ice.tps[tp_id].actions,current_frame_buffer); } } void clear_tracepoints(void) { int i; skyeye_ice.num_tps=0; for (i=0;i<MAX_TRACEPOINTS;i++) { if (skyeye_ice.tps[i].actions!=NULL) delete_action(skyeye_ice.tps[i].actions); skyeye_ice.tps[i].actions=NULL; } } void init_tracepoints () { clear_tracepoints(); skyeye_ice.tps_status=TRACE_STOPPED; clear_frame_buffers(); skyeye_ice.selected_fb=NULL; clear_ro_regions(); return; } void start_trace_recording () { skyeye_ice.tps_status=TRACE_STARTED; } void stop_trace_recording () { skyeye_ice.tps_status=TRACE_STOPPED; } void start_trace_focusing () { skyeye_ice.tps_status=TRACE_FOCUSING; } void stop_trace_focusing () { skyeye_ice.tps_status=TRACE_STARTED; skyeye_ice.selected_fb=NULL; } trace_status get_trace_status() { return(skyeye_ice.tps_status); } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/arm_regdefs.c�������������������������������������������������������0000644�0001750�0000144�00000005161�10571723266�017620� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* arm_regdefs.c - necessary arm definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "skyeye2gdb.h" #include "armdefs.h" #define ARM_NUM_REGS 26 #define CPSR_REGNUM 25 extern int bigendSig; extern ARMul_State * state; static int arm_register_raw_size(int x){ if(x > 15 && x < 24) return 12; else return 4; } static int arm_register_byte(int x){ if(x < 16) return (x*4); if(x > 15 && x < 24) return (16 * 4 + (x - 16)*12); if(x == 24) return (16 * 4 + 8 * 12); if(x == CPSR_REGNUM) return (16 * 4 + 8 * 12 + 4); } static int arm_store_register(int rn, unsigned long * memory){ bigendSig = state->bigendSig; if(rn == CPSR_REGNUM){ ARMul_SetCPSR(state, frommem(memory)); return 0; } if(rn < 16) ARMul_SetReg (state, state->Mode, rn, frommem (memory)); return 0; } static int arm_fetch_register(int rn, unsigned char * memory){ WORD regval; bigendSig = state->bigendSig; if (rn < 16) regval = ARMul_GetReg (state, state->Mode, rn); else if (rn == CPSR_REGNUM) /* FIXME: use PS_REGNUM from gdb/config/arm/tm-arm.h */ regval = ARMul_GetCPSR (state); else regval = 0x0; /* FIXME: should report an error */ tomem (memory, regval); return 0; } /* * register arm register type to the array */ void init_arm_register_defs(void){ static register_defs_t arm_reg_defs; arm_reg_defs.name = "arm"; arm_reg_defs.register_raw_size = arm_register_raw_size; arm_reg_defs.register_bytes = (16 * 4 + 12 * 8 + 4 + 4); arm_reg_defs.register_byte = arm_register_byte; arm_reg_defs.num_regs = ARM_NUM_REGS; arm_reg_defs.max_register_raw_size = 12; arm_reg_defs.store_register = arm_store_register; arm_reg_defs.fetch_register = arm_fetch_register; register_reg_type(&arm_reg_defs); } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/cf_regdefs.c��������������������������������������������������������0000644�0001750�0000144�00000006431�10600011124�017402� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* cf_regdefs.c - necessary coldfire definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ /* * refer to GDB_SOURCE/gdb/regformats/reg-m68k.dat 32:d0 32:d1 32:d2 32:d3 32:d4 32:d5 32:d6 32:d7 32:a0 32:a1 32:a2 32:a3 32:a4 32:a5 32:fp 32:sp 32:ps 32:pc 96:fp0 96:fp1 96:fp2 96:fp3 96:fp4 96:fp5 96:fp6 96:fp7 32:fpcontrol 32:fpstatus 32:fpiaddr */ #include "skyeye.h" #include "skyeye_defs.h" #include "skyeye2gdb.h" #include "skyeye_types.h" #include "arch/coldfire/common/memory.h" #define CF_NUM_REGS 29 extern struct _memory_core memory_core; static int cf_register_raw_size(int x){ if(x >= 0 && x < 18) return 4; if(x >= 18 && x < 26) return 12; if(x >=26 && x < 29) return 4; } static int cf_register_byte(int x){ if(x >= 0 && x < 18) return (4 * x); if(x >= 18 && x < 26) return (4*18 + (x-18)*12); if(x >= 26 && x < 29) return (4 * 18 + 8 * 12 + (x - 26) * 4); } static int cf_store_register(int rn, unsigned char * memory){ //SKYEYE_DBG("in %s\n",__FUNCTION__); WORD val = frommem(memory); if(0 <= rn && rn < 8) memory_core.d[rn] = val ; else if(8 <= rn && rn < 16 ) memory_core.a[rn-8] = val ; else if(16 == rn) memory_core.sr = val; else if(17 == rn) memory_core.pc = val; else if(rn >= 18 && rn < 29) ; /* Do nothing */ else return -1; return 0; } static int cf_fetch_register(int rn, unsigned char * memory){ WORD regval; if(0 <= rn && rn < 8) regval = memory_core.d[rn]; else if(8 <= rn && rn < 16 ) regval = memory_core.a[rn-8]; else if(16 == rn) regval = memory_core.sr; else if(17 == rn) regval = memory_core.pc; else if(rn >= 18 && rn < 29) regval = 0; else return -1; //SKYEYE_DBG("in %s, regval=%d,rn=%d\n",__FUNCTION__,regval,rn); tomem (memory, regval); return 0; } static register_defs_t cf_reg_defs; /* * register coldfire register type to the array */ void init_cf_register_defs(void){ cf_reg_defs.name = "coldfire"; cf_reg_defs.register_raw_size = cf_register_raw_size; cf_reg_defs.register_bytes = 4 * 18 + 12 * 8 + 4 * 3; cf_reg_defs.register_byte = cf_register_byte; cf_reg_defs.num_regs = CF_NUM_REGS; cf_reg_defs.max_register_raw_size = 12; cf_reg_defs.store_register = cf_store_register; cf_reg_defs.fetch_register = cf_fetch_register; cf_reg_defs.endian_flag = HIGH; register_reg_type(&cf_reg_defs); } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/skyeye2gdb.c��������������������������������������������������������0000644�0001750�0000144�00000007334�10572524543�017414� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye2gdb.c - necessary definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/04/2005 ksh <blacfin.kang@gmail.com> * */ #include "armdefs.h" #include "skyeye_types.h" #include "memory.h" #include "armemu.h" #include "skyeye2gdb.h" #include "skyeye_defs.h" #include <stdint.h> extern struct ARMul_State * state; extern struct _memory_core memory_core; extern register_defs_t * current_reg_type; extern generic_arch_t * arch_instance; int bigendSig; int frommem (unsigned char *memory) { bigendSig = current_reg_type->endian_flag; if (bigendSig == HIGH) { return (memory[0] << 24) | (memory[1] << 16) | (memory[2] << 8) | (memory[3] << 0); } else { return (memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | (memory[0] << 0); } } void tomem (unsigned char *memory, int val) { bigendSig = current_reg_type->endian_flag; if (bigendSig == HIGH) { memory[0] = val >> 24; memory[1] = val >> 16; memory[2] = val >> 8; memory[3] = val >> 0; } else { memory[3] = val >> 24; memory[2] = val >> 16; memory[1] = val >> 8; memory[0] = val >> 0; } } #if 0 ARMword ARMul_Debug (ARMul_State * state, ARMword pc ATTRIBUTE_UNUSED, ARMword instr ATTRIBUTE_UNUSED) { state->Emulate = STOP; stop_simulator = 1; return 1; } #endif //chy 2006-04-12 int sim_ice_breakpoint_insert(ARMword addr) { int i; for(i = 0; i < skyeye_ice.num_bps; i++) { if (skyeye_ice.bps[i] == addr) return 1; } if (skyeye_ice.num_bps >= MAX_BREAKPOINTS) return -1; skyeye_ice.bps[skyeye_ice.num_bps++] = addr; return 0; } int sim_ice_breakpoint_remove(ARMword addr) { int i; for(i = 0; i < skyeye_ice.num_bps; i++) { if (skyeye_ice.bps[i] == addr) goto found; } return 0; found: skyeye_ice.num_bps--; if (i < skyeye_ice.num_bps) skyeye_ice.bps[i] = skyeye_ice.bps[skyeye_ice.num_bps]; return 1; } int sim_write (ARMword addr, unsigned char *buffer, int size) { int i; int fault=0; for (i = 0; i < size; i++) { fault=arch_instance->ICE_write_byte(addr + i, buffer[i]); if(fault) return -1; } return size; } int sim_read (ARMword addr, unsigned char *buffer, int size) { int i; int fault = 0; unsigned char v; for (i = 0; i < size; i++) { fault = arch_instance->ICE_read_byte(addr + i, &v); if(fault) return -1; buffer[i]=v; } return size; } void gdbserver_cont(){ if(!strcmp(skyeye_config.arch->arch_name,"arm")){ //chy 2006-04-12 state->NextInstr = RESUME; /* treat as PC change */ state->Reg[15]=ARMul_DoProg (state); } else sim_resume(0); } void gdbserver_step(){ if(!strcmp(skyeye_config.arch->arch_name,"arm")){ //chy 2006004-12 state->NextInstr = RESUME; state->Reg[15]=ARMul_DoInstr (state); } else sim_resume(1); } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/gdb_tracepoint.h����������������������������������������������������0000644�0001750�0000144�00000011047�10602143035�020314� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* debugger.h - necessary definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _GDB_TRACEPOINT_H_ #define _GDB_TRACEPOINT_H_ typedef enum { ACTION_UNASSIGNED=0, ACTION_COLLECT =1, ACTION_WHILE }action_type; typedef enum { COLLECT_UNASSIGNED=0, COLLECT_REGISTERS =1, COLLECT_MEMORY, COLLECT_EXPRESSION }collect_action_type; typedef struct { unsigned int mask; }register_collect; typedef struct { int base_reg; unsigned int offset; unsigned int length; }memory_collect; typedef struct { int exp; //dummmy implementation }expression_collect; typedef struct { collect_action_type type; union { register_collect rc; memory_collect mc; expression_collect ec; } description; }collect_action; typedef struct { unsigned int step_count; unsigned int remaining_steps; }while_action; typedef struct t_action { action_type type; union { collect_action ca; while_action wa; } action_data; struct t_action *sibling; struct t_action *child; }action; typedef struct t_collect_record { collect_action *ca; char *collect_data; unsigned int collect_data_length; struct t_collect_record * next; }collect_record; typedef struct t_frame_buffer { unsigned int tp_number; unsigned int frame_number; collect_record *head_record; struct t_frame_buffer *next; }frame_buffer; typedef enum { TRACEPOINT_DISABLED =0, TRACEPOINT_ENABLED, TRACEPOINT_STEPPING, }tracepoint_status; typedef enum { TRACE_STARTED=0, TRACE_STOPPED, TRACE_FOCUSING, }trace_status; typedef struct { unsigned int tp_address; //address of the trace point unsigned int number; //the number assigned to the trace point action *actions; //tree of the actions to be executed tracepoint_status status; // unsigned int pass_count; //count of the total pass bey the tracepoint unsigned int remaining_pass;// remainig passes unsigned int remaining_step; //should'nt be in the while action ? }tracepoint_def; typedef struct t_ro_region { unsigned int start; unsigned int end; struct t_ro_region *next; }ro_region; int add_tracepoint (unsigned int tp_number,unsigned int tp_address); int find_tp_id (unsigned int tp_number,unsigned int tp_address); void set_tracepoint_address(int tp_id, unsigned int address ); void set_tracepoint_number(int tp_id, unsigned int number ); void set_tracepoint_status(int tp_id, tracepoint_status status); void set_tracepoint_pass_count(int tp_id, unsigned int pass_count ); void set_tracepoint_remaining_pass(int tp_id, unsigned int remaining_pass ); void set_tracepoint_remaining_step(int tp_id, unsigned int remaining_step ); unsigned int get_tracepoint_remaining_step(int tp_id); action* prepare_action(int tp_id, action *parent_action); void set_action_type (action *action_p, action_type type); void set_action_data_type(action *action_p, collect_action_type type ); void set_rc_action_mask( action *action_p, unsigned int mask); void set_wa_step_count (action *action_p, unsigned int step_count); void add_ro_region(unsigned int start, unsigned int end); int is_in_ro_region(unsigned int addr, int length); void trace_fetch_registers(int regno, unsigned char *memory); int trace_read (unsigned int addr, unsigned char *buffer, int size); int select_frame_buffer_by_tpn (int tracepoint_number, int *frame_number); int select_frame_buffer_by_fn (int *tracepoint_number, int frame_number); void handle_tracepoint(int i); void init_tracepoints (); void start_trace_recording (); void stop_trace_recording (); void start_trace_focusing (); void stop_trace_focusing (); #endif //_GDB_TRACEPOINT_H_ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/utils/debugger/ppc_regdefs.c�������������������������������������������������������0000644�0001750�0000144�00000007767�11001652420�017617� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ppc_regdefs.c - necessary ppc definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/21/2006 Michael.Kang <blackfin.kang@gmail.com> */ /* * according to GDB_SOURCE/gdb/regformats/ppc-reg.dat 32:r0 32:r1 32:r2 32:r3 32:r4 32:r5 32:r6 32:r7 32:r8 32:r9 32:r10 32:r11 32:r12 32:r13 32:r14 32:r15 32:r16 32:r17 32:r18 32:r19 32:r20 32:r21 32:r22 32:r23 32:r24 32:r25 32:r26 32:r27 32:r28 32:r29 32:r30 32:r31 64:f0 64:f1 64:f2 64:f3 64:f4 64:f5 64:f6 64:f7 64:f8 64:f9 64:f10 64:f11 64:f12 64:f13 64:f14 64:f15 64:f16 64:f17 64:f18 64:f19 64:f20 64:f21 64:f22 64:f23 64:f24 64:f25 64:f26 64:f27 64:f28 64:f29 64:f30 64:f31 32:pc 32:ps 32:cr 32:lr 32:ctr 32:xer 32:fpscr * in gdb internal, it seem that there is 72 register, need to dig more. */ #include <skyeye_defs.h> #include "skyeye2gdb.h" #include "ppc_cpu.h" extern PPC_CPU_State gCPU; static int ppc_register_raw_size(int x){ #if 0 if(x > 31 && x < 64) return 8; else #endif return 4; } static int ppc_register_byte(int x){ #if 0 if(x < 32) return (4 * x); else if(31 < x && x < 64) return (32 * 4 + (x - 32) * 8); else return (32 * 4 + 32 * 8 + (x - 64) * 4); #endif return 4 * x; } static int ppc_store_register(int rn, unsigned char * memory){ int v = frommem(memory); if(rn < 32) gCPU.gpr[rn] = v ; else if(rn > 31 && rn < 64) return 0; else{ switch(rn){ case 64: //NIA = v; gCPU.pc = v; break; case 65: gCPU.msr = v; //MSR = v; break; case 66: //CR = v; gCPU.cr = v; break; case 67: //LR = v; gCPU.lr = v; break; case 68: //CTR = v; gCPU.ctr = v; break; case 69: //XER = v; gCPU.xer = v; return; case 70: //FPSCR = v; gCPU.fpscr = v; break; case 71: break; default: fprintf(stderr,"Wrong reg number 0x%d in %s\n", rn, __FUNCTION__); return -1; } } return 0; } static int ppc_fetch_register(int rn, unsigned char * memory){ uint32_t v; if(rn < 32) v = gCPU.gpr[rn]; else if(rn > 31 && rn < 64) return 0; else{ switch(rn){ case 64: v = gCPU.pc; break; case 65: v = gCPU.msr; break; case 66: v = gCPU.cr; break; case 67: v = gCPU.lr; break; case 68: v = gCPU.ctr; break; case 69: v = gCPU.xer; break; case 70: v = gCPU.fpscr; break; default: v = 0; //fprintf(stderr,"Wrong reg number 0x%d in %s\n", rn, __FUNCTION__); //return -1; } } tomem (memory, v); return 0; } /* * register powerpc register type to the array */ void init_ppc_register_defs(void){ /* initialize the struct of powerpc register defination */ static register_defs_t ppc_reg_defs; ppc_reg_defs.name = "ppc"; ppc_reg_defs.register_raw_size = ppc_register_raw_size; ppc_reg_defs.register_bytes = 32 * 4 + 32 * 4 + 7 * 4; ppc_reg_defs.register_byte = ppc_register_byte; ppc_reg_defs.num_regs = 71; /* the total number of ppc register is 71 */ ppc_reg_defs.max_register_raw_size = 4; ppc_reg_defs.store_register = ppc_store_register; ppc_reg_defs.fetch_register = ppc_fetch_register; ppc_reg_defs.endian_flag = HIGH; register_reg_type(&ppc_reg_defs); } ���������skyeye-1.2.5_REL/utils/debugger/mips_regdefs.c������������������������������������������������������0000644�0001750�0000144�00000007122�10650022321�017766� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mips_regdefs.c - necessary mips definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/21/2006 Michael.Kang <blackfin.kang@gmail.com> */ /* * according to GDB_SOURCE/gdb/regformats/mips-reg.dat * 32:zero 32:at 32:v0 32:v1 32:a0 32:a1 32:a2 32:a3 32:t0 32:t1 32:t2 32:t3 32:t4 32:t5 32:t6 32:t7 32:s0 32:s1 32:s2 32:s3 32:s4 32:s5 32:s6 32:s7 32:t8 32:t9 32:k0 32:k1 32:gp 32:sp 32:s8 32:ra 32:sr 32:lo 32:hi 32:bad 32:cause 32:pc 32:f0 32:f1 32:f2 32:f3 32:f4 32:f5 32:f6 32:f7 32:f8 32:f9 32:f10 32:f11 32:f12 32:f13 32:f14 32:f15 32:f16 32:f17 32:f18 32:f19 32:f20 32:f21 32:f22 32:f23 32:f24 32:f25 32:f26 32:f27 32:f28 32:f29 32:f30 32:f31 32:fsr 32:fir 32:fp */ #include <skyeye_defs.h> #include "skyeye2gdb.h" #include <emul.h> static int mips_register_raw_size(int x){ return 32; } static int mips_register_byte(int x){ return 4 * x; } extern int bigendSig; extern MIPS_State* mstate; static int mips_store_register(int rn, unsigned char * memory){ uint32_t v = frommem(memory); if(rn >= 0 && rn < 32) mstate->gpr[rn] = v; else if(rn == 32)/* SR register of CP0 */ mstate->cp0[12] = v; else if(rn == 33) mstate->lo = v; else if(rn == 34) mstate->hi = v; else if(rn == 35) /* Bad Vaddr */ mstate->cp0[8] = v; else if(rn == 36) /* Cause */ mstate->cp0[13] = v; else if(rn == 37) mstate->pc = v; else if(rn >= 38 && rn < 70) mstate->fpr[rn] = v; else if(rn == 70 || rn == 71 || rn == 72) /* fsr, fir, fp */ ; /* do nothing */ return 0; } static int mips_fetch_register(int rn, unsigned char * memory){ uint32_t v; if(rn >= 0 && rn < 32) v = mstate->gpr[rn]; else if(rn == 32)/* SR register of CP0 */ v = mstate->cp0[12]; else if(rn == 33) v = mstate->lo; else if(rn == 34) v = mstate->hi; else if(rn == 35) /* Bad Vaddr */ v = mstate->cp0[8]; else if(rn == 36) /* Cause */ v = mstate->cp0[13]; else if(rn == 37) v = mstate->pc; else if(rn >= 38 && rn < 70) v = mstate->fpr[rn]; else if(rn == 70 || rn == 71 || rn == 72) /* fsr, fir, fp */ ; /* do nothing */ tomem (memory, v); return 0; } /* * register mips register type to the array */ void init_mips_register_defs(void){ /* initialize the struct of mips register defination */ static register_defs_t mips_reg_defs; mips_reg_defs.name = "mips"; mips_reg_defs.register_raw_size = mips_register_raw_size; mips_reg_defs.register_bytes = (32 + 6 + 32 + 3)*4; mips_reg_defs.register_byte = mips_register_byte; mips_reg_defs.num_regs = 73; /* the total number of mips register is 73 */ mips_reg_defs.max_register_raw_size = 4; mips_reg_defs.store_register = mips_store_register; mips_reg_defs.fetch_register = mips_fetch_register; register_reg_type(&mips_reg_defs); } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/install-sh�������������������������������������������������������������������������0000644�0001750�0000144�00000031600�11006120657�014235� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/sh # install - install a program, script, or datafile scriptversion=2006-10-14.15 # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the # following copyright and license. # # Copyright (C) 1994 X Consortium # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to # deal in the Software without restriction, including without limitation the # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or # sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 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������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/���������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�017313� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/convert.sh�����������������������������������������������0000644�0001750�0000144�00000000132�11006121114�021316� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/bash for i in `find ./ -name "*.c"` do sed '/TRACE/d' $i > temp cp temp $i done ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_unlk.c�������������������������������������������������0000644�0001750�0000144�00000003060�11006121114�020732� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Unlink (UNLK) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int UNLKTime=2; INSTRUCTION_2ARGS(UNLK, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address ARegister,Stack; unsigned int Result; UNLK_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&ARegister, 32, 1, Instr.Bits.Register)) return; if(!EA_GetFromPC(&Stack, 32, 1, 7)) return; /* Load the stack pointer from the A register */ EA_GetValue(&Result, &ARegister); EA_PutValue(&Stack, Result); /* Now pop a longword from the stack and set that to be the A register */ Result = Stack_Pop(32); EA_PutValue(&ARegister, Result); cycle(UNLKTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { UNLK_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "UNLK"); Addressing_Print(32, 1, Instr.Bits.Register, Arg1); Arg2[0]=0; return 0; } int unlk_5206_register(void) { instruction_register(0x4E58, 0xFFF8, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_div.c��������������������������������������������������0000644�0001750�0000144�00000016015�11006121114�020547� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* 4 formats for divide DIVS Word Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 0 | Register | 1 | 1 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ DIVU Word Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 0 | Register | 0 | 1 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ DIVS Long Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 |Register Dx| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |Register Dx| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ DIVU Long Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 |Register Dx| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |Register Dx| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 2 remainder formats: REMS Long format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 |Register Dx| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |Register Dw| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Note that this is the same as the DIVS format, when Dq==Dr, then it's DIVS, else, it's REMS REMU Long format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 |Register Dx| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |Register Dw| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Again, when Dq==Dr this is DIVU, else it's REMU REM <ea>y,Dw:Dx 32bit Dx / 32bit <ea>y => 32bit Dw */ int DIVSTime[8]={18, 20, 20, 20, 20, -1, -1, -1}; SKYEYE_DBGR_DEFAULT_CHANNEL(i_div); #define DIV_W_REGISTER(word) (((word)&0x0e00) >> 9) #define DIV_W_DIVS(word) (((word)&0x0100)) #define DIV_L_DX(word) (((word)&0x7000) >> 12) #define DIV_L_DW(word) (((word)&0x0007)) #define DIV_L_DIVS(word) (((word)&0x0800)) #define DIV_EAMODE(word) (((word)&0x0038) >> 3) #define DIV_EAREG(word) (((word)&0x0007)) static void execute(void) { struct _Address source, destination, remainder; unsigned long code[2]; unsigned long s, d, r; // printf("DIV executed!\n"); // printf("PC=%ld\n", memory_core.pc); Memory_RetrWordFromPC(&code[0]); if(code[0] & 0x8000) { /* word format */ // char overflow=0; if(!EA_GetFromPC(&source, 16, DIV_EAMODE(code[0]), DIV_EAREG(code[0]) )) return ; if(!EA_GetFromPC(&destination, 32, 0, DIV_W_REGISTER(code[0]))) return ; EA_GetValue(&s, &source); EA_GetValue(&d, &destination); if(DIV_W_DIVS(code[0])) { /* Signed operation */ SKYEYE_DBG("signed word divide %ld / %ld\n", (signed)d, (signed)s); //(signed)r = (signed)d % (signed)s; //(signed)d = (signed)d / (signed)s; signed r1 = (signed)r; signed d1 = (signed)d; signed s1 = (signed)s; r1 = d1 % s1; d1 = d1 / s1; r = r1; d = d1; s = s1; if((signed)d < 0 && ((d&0xffff0000) == 0xffff0000) ) { d &= 0x0000ffff; } SRBits->N = ((signed)d < 0) ? 1 : 0; } else { SKYEYE_DBG("signed word divide %lu / %lu\n", d,s); r = d % s; d = d / s; SRBits->N = 0; } SKYEYE_DBG(" (q=0x%08x, r=0x%08x)\n", d,r); if(d & 0xffff0000) { /* Overflow, result doesn't fit in 16 bits */ SRBits->N=0; SRBits->Z=0; SRBits->V=1; SKYEYE_DBG("overflow, q doesn't fit in 16 bits\n"); } else { d = ((r & 0x0000ffff) << 16) | (d & 0x0000ffff); SRBits->Z = ((d & 0x0000ffff) == 0) ? 1 : 0; SRBits->V = 0; SKYEYE_DBG("= 0x%08lx\n",d); EA_PutValue(&destination, d); } SRBits->C=0; } else { /* long format */ char result_negative = 0; // char overflow = 0; Memory_RetrWordFromPC(&code[1]); if(!EA_GetFromPC(&source, 32, DIV_EAMODE(code[0]), DIV_EAREG(code[0]) )) return; if(!EA_GetFromPC(&destination, 32, 0, DIV_L_DX(code[1]) )) return ; if(!EA_GetFromPC(&remainder, 32, 0, DIV_L_DW(code[1]) )) return ; EA_GetValue(&s, &source); EA_GetValue(&d, &destination); if(DIV_L_DIVS(code[1])) { SKYEYE_DBG("Signed long divide/remainder\n"); /* Turn source and dest into signed values */ result_negative = (s ^ d) & 0x8000000; if((signed)s < 0) s = -(signed)s; if((signed)d < 0) d = -(signed)d; } else { SKYEYE_DBG("unigned long divide/remainder\n"); } SKYEYE_DBG(" d=%08lx / s=0x%08lx (neg=%d)\n", d, s, result_negative ? 1 : 0); r = d % s; d = d / s; //if(result_negative) (signed)d = -(signed)d; signed d1 = -(signed)d; if(result_negative) d = d1; SKYEYE_DBG(" = d=%08lx : r=0x%08lx\n", d, r); if(DIV_L_DX(code[1]) != DIV_L_DW(code[1])) { /* REM operation */ SKYEYE_DBG("writing remainder\n"); EA_PutValue(&remainder, r); SRBits->N = 0; /* cannot have a negative remainder */ SRBits->Z = (r == 0) ? 1 : 0; } else { SKYEYE_DBG("writing quotient\n"); EA_PutValue(&destination, d); SRBits->N = result_negative ? 1 : 0; SRBits->Z = (d == 0) ? 1 : 0; } SRBits->C = 0; SRBits->V = 0; } SKYEYE_DBG("Done\n"); //FIXME:cycle(DIVSTime[cycle_EA(DIV_EAREG(code[0]),DIV_EAMODE(code[0]))]); return; } static long disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned long code[2]; Memory_RetrWordFromPC(&code[0]); Addressing_Print(32, DIV_EAMODE(code[0]), DIV_EAREG(code[0]),Arg1); if(code[0] & 0x8000) { /* word */ sprintf(Instruction, "DIV%c.W", DIV_W_DIVS(code[0]) ? 'S':'U'); Addressing_Print(32, 0, DIV_W_REGISTER(code[0]), Arg2); } else { char rem=0; Memory_RetrWordFromPC(&code[1]); Arg2[0] = 0; /* long */ if(DIV_L_DX(code[1]) != DIV_L_DW(code[1])) { rem=1; Addressing_Print(32, 0, DIV_L_DW(code[1]), Arg2); strcat(Arg2, ":"); } Addressing_Print(32, 0, DIV_L_DX(code[1]), &Arg2[strlen(Arg2)]); sprintf(Instruction, "%s%c.L", rem ? "REM" : "DIV", DIV_L_DIVS(code[1]) ? 'S':'U'); } return 0; } long div_5206e_register(void) { instruction_register(0x81C0, 0xF0C0, &execute, &disassemble); instruction_register(0x4C40, 0xFFC0, &execute, &disassemble); return 6; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/temp�����������������������������������������������������0000644�0001750�0000144�00000003264�11006121114�020203� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Move instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | Register | 0 | Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int MOVEQTime=1; INSTRUCTION_4ARGS(MOVEQ, unsigned Code2,4, unsigned Register,3, unsigned Code1,1, signed Data,8); static void execute(void) { struct _Address Destination; unsigned long SValue; MOVEQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); SValue=(unsigned long)Instr.Bits.Data; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_PutValue(&Destination, SValue); /* X - not affected N - set if result is -ve, cleared otherwise Z - set if result is zero, cleared otherwise V - always cleared C - always cleared */ /* Set the status register */ memory_core.sr &= 0xFFF0; SRBits->N = ((long)SValue < 0); SRBits->Z = (SValue == 0); cycle(MOVEQTime); return; } static long disassemble(char *Instruction, char *Arg1, char *Arg2) { MOVEQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "MOVEQ"); sprintf(Arg1, "#0x%02X", ((char)Instr.Bits.Data) & 0x000000FF); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } long moveq_5206_register(void) { instruction_register(0x7000, 0xF100, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_clr.c��������������������������������������������������0000644�0001750�0000144�00000003543�11006121114�020547� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Clear (CLR) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | Size | EAMode |EARegister | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int CLRTime[8]={ 1, 1, 1, 1, 1, 2, 1, -1}; INSTRUCTION_4ARGS(CLR, unsigned Code1,8, unsigned Size,2, unsigned EAMode,3, unsigned EARegister,3); const short CLR_SizeBits[4]={ 8 , 16 , 32 , 0 }; const char CLR_SizeStr[4]= {'B', 'W', 'L', '?'}; static void execute(void) { struct _Address Destination; CLR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.Size == 3) { SKYEYE_ERR("Invalid size=3", memory_core.pc); return; } if(!EA_GetFromPC(&Destination, CLR_SizeBits[(short)Instr.Bits.Size], Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_PutValue(&Destination, 0); /* X - Not affected N - Always Cleared Z - Always Set V - Always Cleared C - Always Cleared */ SRBits->N=0; SRBits->Z=1; SRBits->V=0; SRBits->C=0; cycle(CLRTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { CLR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "CLR.%c", CLR_SizeStr[(short)Instr.Bits.Size]); Addressing_Print(CLR_SizeBits[(short)Instr.Bits.Size], Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Arg2[0]=0; return 0; } int clr_5206_register(void) { instruction_register(0x4200, 0xFF00, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_swap.c�������������������������������������������������0000644�0001750�0000144�00000003232�11006121114�020734� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Swap register halves (SWAP) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int SWAPTime=1; INSTRUCTION_2ARGS(SWAP, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Destination; unsigned int DValue; unsigned int Tmp; SWAP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&DValue, &Destination); Tmp = (DValue << 16) & 0xFFFF0000; Tmp += (DValue >> 16) & 0x0000FFFF; EA_PutValue(&Destination, Tmp); /* X - Not affected N - Set if 32bits result is negative Z - Set if 32bit result is zero V - Always Cleared C - Always Cleared */ SRBits->N= ((int)Tmp < 0) ? 1 : 0; SRBits->Z= (Tmp == 0) ? 1 : 0; SRBits->V=0; SRBits->C=0; cycle(SWAPTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { SWAP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "SWAP"); Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Arg2[0]=0; return 0; } int swap_5206_register(void) { instruction_register(0x4840, 0xFFF8, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_rts.c��������������������������������������������������0000644�0001750�0000144�00000002312�11006121114�020570� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Return from Subroutine (RTS) */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int RTSTime=5; INSTRUCTION_1ARG(RTS, unsigned Code1,16); static void execute(void) { unsigned int dummy; /* Read the instruction with out storing it.. we already know what it is */ Memory_RetrWordFromPC(&dummy); /* Pop the PC from the A7 stack pointer */ memory_core.pc=Stack_Pop(32); cycle(RTSTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned int dummy; Memory_RetrWordFromPC(&dummy); sprintf(Instruction, "RTS"); Arg1[0]=0; Arg2[0]=0; return 0; } int rts_5206_register(void) { instruction_register(0x4E75, 0xFFFF, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_movexr.c�����������������������������������������������0000644�0001750�0000144�00000006026�11006121114�021306� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* MOVE to SR instruction * MOVE from SR instruction * MOVE to CCR instruction * MOVE from CCR instruction */ /* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVE to SR: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | Mode | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ MOVE from SR: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ MOVE to CCR: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | Mode | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ MOVE from CCR: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ INSTRUCTION_6ARGS(MOVEXR, unsigned Code2,5, unsigned To,1, unsigned Reg,1, unsigned Code1,3, unsigned Mode,3, unsigned Register,3); int MOVE2SRTime=1; /* Add +6 for non immediate EA */ int MOVEXRTime=1; static void execute(void) { struct _Address Source; unsigned int SValue; char CCR; MOVEXR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); CCR = Instr.Bits.To ^ Instr.Bits.Reg; if(!EA_GetFromPC(&Source, 16, Instr.Bits.Mode, Instr.Bits.Register)) return; if(CCR == 0 && !SRBits->S ) { /* User state, ptivilege violation */ exception_do_exception(8); return; } if(Instr.Bits.To) { EA_GetValue(&SValue, &Source); if(CCR == 0) { memory_core.sr = SValue; if( (Instr.Bits.Mode == 0x07) && (Instr.Bits.Register==0x04) ) cycle(MOVE2SRTime + 6); else cycle(MOVE2SRTime); } else { memory_core.sr = (memory_core.sr & 0xffffff00) | (SValue & 0x000000ff); cycle(MOVEXRTime); } } else { SValue = (unsigned int)((CCR==0) ? memory_core.sr : (memory_core.sr&0x000000ff) ); EA_PutValue(&Source, SValue); cycle(MOVEXRTime); } /* Don't play with the Status register any more :) */ return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { MOVEXR_Instr Instr; char CCR; Memory_RetrWordFromPC(&Instr.Code); CCR = Instr.Bits.To ^ Instr.Bits.Reg; sprintf(Instruction, "MOVE"); if(Instr.Bits.To) { char *ptr; ptr = Arg1; Arg1 = Arg2; Arg2 = ptr; } if(CCR) sprintf(Arg1, "CCR"); else sprintf(Arg1, "SR"); Addressing_Print(16, Instr.Bits.Mode, Instr.Bits.Register, Arg2); return 0; } int movexr_5206_register(void) { instruction_register(0x40C0, 0xF9C0, &execute, &disassemble); instruction_register(0x40C0, 0xF9C0, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_halt.c�������������������������������������������������0000644�0001750�0000144�00000002413�11006121114�020712� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* HALT instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int HALTTime=7; /* minimum time to halt per Sue Cozart */ INSTRUCTION_1ARG(HALT, unsigned Code,16); static void execute(void) { HALT_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(SRBits->S) { /* Supervisor State */ SKYEYE_ERR("Halting the processor:\n"); return; } else { /* User state */ /* FIXME: Generate an exception violation here */ } cycle(HALTTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { HALT_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "HALT"); Arg1[0]=0; Arg2[0]=0; return 0; } int halt_5206_register(void) { instruction_register(0x4AC8, 0xFFFF, &execute, &disassemble); return 1; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_mulu_l.c�����������������������������������������������0000644�0001750�0000144�00000005164�11006121114�021265� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Long Unsigned multiply (MULU.L) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | Register | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int MULLTime[8]={18, 20, 20, 20, 20, -1, -1, -1}; INSTRUCTION_3ARGS(MULU_L, unsigned Code1,10, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; char Register; unsigned int Instr2; MULU_L_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); Memory_RetrWordFromPC(&Instr2); Register=(Instr2 & 0x7000) >> 12; if(Instr.Bits.EAMode==1) { SKYEYE_ERR("May Not specify Address Register (Ay) for MULU.L"); return; } else if(Instr.Bits.EAMode==7) { SKYEYE_ERR("May Not specify Direct Addressing for MULU.L"); return; } if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 0, Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); /* FIXME: I'm not sure if this discards the upper 32 bits (as required in the spec) or if it does something FuNkY */ if(Instr2 & 0x0800) { /* Signed multiply */ Result = (int)(SValue) * (int)(DValue); } else { /* Unsigned multiply */ Result = (unsigned int)(SValue) * (unsigned int)(DValue); } /* Set the status register */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); EA_PutValue(&Destination, Result); cycle(MULLTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned int Instr2; char Register; MULU_L_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); Memory_RetrWordFromPC(&Instr2); Register=(Instr2 & 0x7000) >> 12; sprintf(Instruction, "MUL%c.L", (Instr2 & 0x0800) ? 'S' : 'U'); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Register, Arg2); return 0; } int mulu_l_5206_register(void) { instruction_register(0x4C00, 0xFFC0, &execute, &disassemble); return 2; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_cmp.c��������������������������������������������������0000644�0001750�0000144�00000003253�11006121114�020544� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Compare (CMP) instruction */ /* Format CMP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | Register | 0 | 1 | 0 | EAMode |EARegister | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int CMPTime[8]={ 1, 3, 3, 3, 3, 4, 3, 1}; INSTRUCTION_5ARGS(CMP, unsigned Code2,4, unsigned Register,3, unsigned Code1,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; CMP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = DValue - SValue; SR_Set(I_CMP, SValue, DValue, Result); cycle(CMPTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { CMP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "CMP.L"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int cmp_5206_register(void) { instruction_register(0xB080, 0xF1C0, &execute, &disassemble); return 1; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_cmpi.c�������������������������������������������������0000644�0001750�0000144�00000003416�11006121114�020716� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Compare immediate (CMPI) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Upper Word of Immediate Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Lower Word of Immediate Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int CMPITime=1; INSTRUCTION_2ARGS(CMPI, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; CMPI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 7, 4)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = DValue - SValue; /* Set the status register */ SR_Set(I_CMPI, SValue, DValue, Result); cycle(CMPITime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { CMPI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "CMPI.L"); Addressing_Print(32, 7, 4, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int cmpi_5206_register(void) { instruction_register(0x0C80, 0xFFF8, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_andi.c�������������������������������������������������0000644�0001750�0000144�00000004004�11006121114�020673� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* AND instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Upper Word of Immediate Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Lower Word of Immediate Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ANDITime=1; INSTRUCTION_2ARGS(ANDI, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; ANDI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 7, 4)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue & DValue; EA_PutValue(&Destination, Result); /* Set the status register * X - Not affected * N - Set if source is -ve, cleared otherwise * Z - Set if source is zero, cleared otherwise * V - always cleared * C - always cleared */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); cycle(ANDITime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ANDI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "ANDI.L"); Addressing_Print(32, 7, 4, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int andi_5206_register(void) { instruction_register(0x0280, 0xFFF8, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_ext.c��������������������������������������������������0000644�0001750�0000144�00000005016�11006121114�020564� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Sign Extend (EXT,EXTB) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 0 | 0 | OPmode | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int EXTTime=1; INSTRUCTION_4ARGS(EXT, unsigned Code2,7, unsigned OPMode,3, unsigned Code1,3, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int SValue, Result; EXT_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); if(Instr.Bits.OPMode==2) { /* Byte -> Word */ if(!EA_GetFromPC(&Destination, 16, 0, Instr.Bits.Register)) return; Result=(char)SValue; } else if(Instr.Bits.OPMode==3) { /* Word -> Long */ if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; Result=(short)SValue; EA_PutValue(&Destination, (short)SValue); } else if(Instr.Bits.OPMode==7) { /* Byte -> Long */ if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; Result=(char)SValue; } else { SKYEYE_ERR("Unknown opmode %d\n", Instr.Bits.OPMode); return; } EA_PutValue(&Destination, Result); /* Set the status register; * X - Not affected * N - Set if result is -ve, cleared otherwise * Z - Set if result is zero, cleared otherwise * V - always cleared * C - always cleared */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); cycle(EXTTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { EXT_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.OPMode==2) { /* Byte -> Word */ sprintf(Instruction, "EXT.W"); } else if(Instr.Bits.OPMode==3) { /* Word -> Long */ sprintf(Instruction, "EXT.L"); } else if(Instr.Bits.OPMode==7) { /* Byte -> Long */ sprintf(Instruction, "EXTB.L"); } else { SKYEYE_ERR("Unknown opmode\n"); } Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Arg2[0]=0; return 0; } int ext_5206_register(void) { instruction_register(0x4800, 0xFE38, &execute, &disassemble); instruction_register(0x4800, 0xFE38, &execute, &disassemble); return 2; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_5206.h�������������������������������������������������0000644�0001750�0000144�00000003454�11006121114�020371� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ int add_5206_register(void); int adda_5206_register(void); int addi_5206_register(void); int addq_5206_register(void); int addx_5206_register(void); int and_5206_register(void); int andi_5206_register(void); int asx_5206_register(void); int bcc_5206_register(void); int btst_5206_register(void); int clr_5206_register(void); int cmp_5206_register(void); int cmpa_5206_register(void); int cmpi_5206_register(void); int dc_5206_register(void); int eor_5206_register(void); int eori_5206_register(void); int ext_5206_register(void); int halt_5206_register(void); int illegal_5206_register(void); int jmp_5206_register(void); int jsr_5206_register(void); int lea_5206_register(void); int link_5206_register(void); int lsx_5206_register(void); int move_5206_register(void); int movec_5206_register(void); int movem_5206_register(void); int moveq_5206_register(void); int movexr_5206_register(void); int mulu_l_5206_register(void); int mul_w_5206_register(void); int neg_5206_register(void); int negx_5206_register(void); int nop_5206_register(void); int not_5206_register(void); int or_5206_register(void); int ori_5206_register(void); int pea_5206_register(void); int rte_5206_register(void); int rts_5206_register(void); int scc_5206_register(void); int stop_5206_register(void); int sub_5206_register(void); int suba_5206_register(void); int subi_5206_register(void); int subq_5206_register(void); int subx_5206_register(void); int swap_5206_register(void); int trap_5206_register(void); int trapf_5206_register(void); int tst_5206_register(void); int unlk_5206_register(void); ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_jmp.c��������������������������������������������������0000644�0001750�0000144�00000002710�11006121114�020550� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Jump (JMP) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | EAMode | EARegister| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int JMPTime[8]={-1, 3, -1, -1, 3, 4, 3, -1}; INSTRUCTION_3ARGS(JMP, unsigned Code1,10, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Destination; unsigned int DValue; JMP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetEA(&DValue, &Destination); /* Set the new PC */ memory_core.pc=DValue; cycle(JMPTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { JMP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "JMP"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Arg2[0]=0; return 0; } int jmp_5206_register(void) { instruction_register(0x4EC0, 0xFFC0, &execute, &disassemble); return 1; } ��������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_neg.c��������������������������������������������������0000644�0001750�0000144�00000002631�11006121114�020535� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Negate instruction (NEG) */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int NEGTime=1; INSTRUCTION_2ARGS(NEG, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Destination; unsigned int Result, DValue; NEG_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&DValue, &Destination); Result = 0 - DValue; /* Set the status register */ SR_Set(I_NEG, 0, DValue, Result); EA_PutValue(&Destination, Result); cycle(NEGTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { NEG_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "NEG.L"); Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Arg2[0]=0; return 0; } int neg_5206_register(void) { instruction_register(0x4480, 0xFFF8, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_stop.c�������������������������������������������������0000644�0001750�0000144�00000002762�11006121114�020756� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ /* FIXME: Unverified correct operation */ #include "coldfire.h" /* Stop (STOP) instruction */ /* MHM July 13, 2000 */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int STOPTime=3; INSTRUCTION_1ARG(STOP, unsigned Code1,16); static void execute(void) { struct _Address Source; unsigned int Result, SValue; STOP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 16, 7, 4)) return; EA_GetValue(&SValue, &Source); Result = SValue; /* Set the status register */ memory_core.sr=Result; /* Not quite finished yet */ cycle(STOPTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { STOP_Instr Instr; unsigned int SValue; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "STOP"); Memory_RetrWordFromPC(&SValue); sprintf(Arg1, "#$%08lx", SValue); Arg2[0]=0; /* Addressing_Print(32, 0, Instr.Bits.Register, Arg2); */ return 0; } int stop_5206_register(void) { instruction_register(0x4E72, 0xFFFF, &execute, &disassemble); return 1; } ��������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_addx.c�������������������������������������������������0000644�0001750�0000144�00000003243�11006121114�020704� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* AddX instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 1 |Register Dx| 1 | 1 | 0 | 0 | 0 | 0 |Register Dy| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ADDXTime=1; /* All the rest of the modes are not valid */ INSTRUCTION_4ARGS(ADDX, unsigned Code2,4, unsigned RegisterDx,3, unsigned Code1,6, unsigned RegisterDy,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; int Extend = SRBits->X; ADDX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.RegisterDy)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.RegisterDx)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue + DValue + Extend; SR_Set(I_ADDX, SValue, DValue, Result); EA_PutValue(&Destination, Result); cycle(ADDXTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ADDX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "ADDX.L"); Addressing_Print(32, 0, Instr.Bits.RegisterDy, Arg1); Addressing_Print(32, 0, Instr.Bits.RegisterDx, Arg2); return 0; } int addx_5206_register(void) { instruction_register(0xD180, 0xF1F8, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_jsr.c��������������������������������������������������0000644�0001750�0000144�00000003037�11006121114�020563� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Jump To Subroutine (JSR) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | EAMode | EARegister| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int JSRTime[8]={-1, 3, -1, -1, 3, 4, 3, -1}; INSTRUCTION_3ARGS(JSR, unsigned Code1,10, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Destination; unsigned int DValue; JSR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetEA(&DValue, &Destination); Stack_Push(32,memory_core.pc); /* Set the new PC */ memory_core.pc=DValue; /* Condition codes are not affected */ cycle(JSRTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { JSR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "JSR"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Arg2[0]=0; return 0; } int jsr_5206_register(void) { instruction_register(0x4E80, 0xFFC0, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_move.c�������������������������������������������������0000644�0001750�0000144�00000007742�11006121114�020742� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Move instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | Size | DRegister | DMode | SMode | SRegister | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ If the destination is an address register, then the condition codes are unaffected, and MOVEA designates this */ INSTRUCTION_6ARGS(MOVE, unsigned Code1,2, unsigned Size,2, unsigned DestRegister,3, unsigned DestMode,3, unsigned SourceMode,3, unsigned SourceRegister,3); const short MOVE_SizeBits[4]={ 0 , 8 , 32 , 16 }; const char MOVE_SizeStr[4]= {'?', 'B', 'L', 'W'}; int MOVE816Time[][7]= { {1,1,1,1,1,2,1}, {1,1,1,1,1,2,1}, {3,3,3,3,3,4,3}, {3,3,3,3,3,4,3}, {3,3,3,3,3,4,3}, {3,3,3,3,3,-1,-1}, {4,4,4,4,-1,-1,-1}, {3,3,3,3,-1,-1,-1}, {3,3,3,3,-1,-1,-1}, {3,3,3,3,3,-1,-1}, {4,4,4,4,-1,-1,-1}, {1,3,3,3,-1,-1,-1} }; int MOVE32Time[][7]= { {1,1,1,1,1,2,1}, {1,1,1,1,1,2,1}, {2,2,2,2,2,3,2}, {2,2,2,2,2,3,2}, {2,2,2,2,2,3,2}, {2,2,2,2,2,-1,-1}, {3,3,3,3,-1,-1,-1}, {2,2,2,2,-1,-1,-1}, {2,2,2,2,-1,-1,-1}, {2,2,2,2,2,-1,-1}, {3,3,3,3,-1,-1,-1}, {1,2,2,2,-1,-1,-1} }; static void execute(void) { struct _Address Source, Destination; unsigned int SValue; int cycle_source_ea=0, cycle_destination_ea=0; MOVE_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.Size==0) { SKYEYE_ERR("Invalid size in instruction, size=0\n"); return; } if(!EA_GetFromPC(&Source, MOVE_SizeBits[(short)Instr.Bits.Size], Instr.Bits.SourceMode, Instr.Bits.SourceRegister)) return; EA_GetValue(&SValue, &Source); if(!EA_GetFromPC(&Destination, MOVE_SizeBits[(short)Instr.Bits.Size], Instr.Bits.DestMode, Instr.Bits.DestRegister)) return; EA_PutValue(&Destination, SValue); /* X - not affected N - set if result is -ve, cleared otherwise Z - set if result is zero, cleared otherwise V - always cleared C - always cleared */ /* Set the status register */ if(Instr.Bits.DestMode != 1) { /* MOVE */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)SValue < 0); SRBits->Z = (SValue == 0); } else { /* MOVEA */ /* Destination is an address register, codes are unaffected */ } /* Do cycle counting */ cycle_source_ea = cycle_EA(Instr.Bits.SourceRegister, Instr.Bits.SourceMode); cycle_destination_ea = cycle_EA(Instr.Bits.DestRegister, Instr.Bits.DestMode); if(Instr.Bits.Size == 0x02) /* 32 bit */ cycle(MOVE32Time[cycle_source_ea][cycle_destination_ea]); else cycle(MOVE816Time[cycle_source_ea][cycle_destination_ea]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { MOVE_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); /* If dest is 'A' an size is (2) == 32 bit or (3)==16 bit, * then it's actually a MOVEA.L/W instruction */ if(Instr.Bits.DestMode == 1 && Instr.Bits.Size >= 2) sprintf(Instruction, "MOVEA.%c", MOVE_SizeStr[(short)Instr.Bits.Size]); else sprintf(Instruction, "MOVE.%c", MOVE_SizeStr[(short)Instr.Bits.Size]); Addressing_Print(MOVE_SizeBits[(short)Instr.Bits.Size], Instr.Bits.SourceMode, Instr.Bits.SourceRegister, Arg1); Addressing_Print(MOVE_SizeBits[(short)Instr.Bits.Size], Instr.Bits.DestMode, Instr.Bits.DestRegister, Arg2); return 0; } int move_5206_register(void) { /* Register once for each size, we don't want to decode an instruction * where the size specifier turns out to be 00 */ instruction_register(0x1000, 0xF000, &execute, &disassemble); instruction_register(0x2000, 0xF000, &execute, &disassemble); instruction_register(0x3000, 0xF000, &execute, &disassemble); instruction_register(0x3000, 0xF000, &execute, &disassemble); return 1; } ������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_pea.c��������������������������������������������������0000644�0001750�0000144�00000002771�11006121114�020536� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Push Effective Address (pea) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | EAMode | EARegister| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int PEATime[8]={-1, 2, -1, -1, 2, 3, 2, -1}; INSTRUCTION_3ARGS(PEA, unsigned Code1,10, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source; unsigned int SValue; PEA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); /* Retrive the effective address, not the value that the EA points to */ if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetEA(&SValue, &Source); Stack_Push(32,SValue); cycle(PEATime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { PEA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "PEA"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Arg2[0]=0; return 0; } int pea_5206_register(void) { instruction_register(0x4840, 0xFFC0, &execute, &disassemble); return 1; } �������skyeye-1.2.5_REL/arch/coldfire/instruction/i_trap.c�������������������������������������������������0000644�0001750�0000144�00000002340�11006121114�020727� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Trap instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | Vector | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int TRAPTime=15; INSTRUCTION_2ARGS(TRAP, unsigned Code1,12, unsigned Vector,4); static void execute(void) { TRAP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); /* this is done in the exception SRBits->T=0; SRBits->S=1; */ exception_do_exception(32+Instr.Bits.Vector); cycle(TRAPTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { TRAP_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "TRAP"); sprintf(Arg1, "#0x%02X", Instr.Bits.Vector); Arg2[0]=0; return 0; } int trap_5206_register(void) { instruction_register(0x4E40, 0xFFF0, &execute, &disassemble); return 1; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_not.c��������������������������������������������������0000644�0001750�0000144�00000002702�11006121114�020563� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* NOT instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 1 1 0 1 0 0 0 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int NOTTime=1; INSTRUCTION_2ARGS(NOT, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Destination; unsigned int Result, DValue; NOT_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&DValue, &Destination); Result = ~DValue; /* Set the status register */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); EA_PutValue(&Destination, Result); cycle(NOTTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { NOT_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "NOT.L"); Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Arg2[0]=0; return 0; } int not_5206_register(void) { instruction_register(0x4680, 0xFFF8, &execute, &disassemble); return 1; } ��������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_bcc.c��������������������������������������������������0000644�0001750�0000144�00000012575�11006121114�020523� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Branch Contitionally, Branch Always (BRA) and Branch To Subroutine (BSR) instructions */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 0 | Condition | 8-Bit displacement | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 16-Bit displacement if 8bit is 00 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int BRATime = 2; int BSRTime = 3; int BCCTime[] = { 3, 1, 2, 3 }; INSTRUCTION_3ARGS(BCC, unsigned Code1,4, unsigned Condition,4, signed Displacement,8); static void execute(void) { unsigned int Displacement; /* The PC for the branch contains the address of the BCC instruction _plus two_ */ unsigned int ReferencePC=memory_core.pc+2; BCC_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); Displacement=Instr.Bits.Displacement; if(Displacement==0) { Memory_RetrWordFromPC(&Displacement); Displacement = (short)Displacement; } switch(Instr.Bits.Condition) { case 0: /* BRA */ /* Do nothing, this is always true */ cycle(BRATime); goto i_bcc_do_branch; case 1: /* BSR */ /* Save the PC in the A7 stack pointer */ Stack_Push(32, memory_core.pc); cycle(BSRTime); goto i_bcc_do_branch; case 2: /* BHI */ /* Branch if not carry, or not zero */ if(!SRBits->C && !SRBits->Z) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 3: /* BLS */ /* Branch if low or same */ if(SRBits->C || SRBits->Z) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 4: /* BCC */ /* Branch if carry cleared */ if(!SRBits->C) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 5: /* BCS */ /* Branch if carry set */ if(SRBits->C) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 6: /* BNE */ /* Branch if they are not equal, ie Dest-Source != 0 */ if(!SRBits->Z) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 7: /* BEQ */ /* Don't branch if they are not equal */ if(SRBits->Z) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 8: /* BVC */ if(!SRBits->V) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 9: /* BVS */ if(SRBits->V) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 10: /* BPL */ if(!SRBits->N) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 11: /* BMI */ if(SRBits->N) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 12: /* BGE */ if((SRBits->N && SRBits->V) || (!SRBits->N && !SRBits->V)) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 13: /* BLT */ if((SRBits->N && !SRBits->V) || (!SRBits->N && SRBits->V)) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 14: /* BGT */ if((SRBits->N && SRBits->V && !SRBits->Z) || (!SRBits->N && !SRBits->V && !SRBits->Z)) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; case 15: /* BLE */ if((SRBits->Z) || (SRBits->N && !SRBits->V) || (!SRBits->N && SRBits->V)) { goto i_bcc_branch_taken; } goto i_bcc_branch_not_taken; default: SKYEYE_ERR("Unknown Condition Code 0x%02x\n", Instr.Bits.Condition); break; } SKYEYE_ERR("This should NOT happen!\n"); return; /* Set the new PC */ i_bcc_branch_taken: cycle(BCCTime[ (Displacement > 0) ? 2 : 0 ]); i_bcc_do_branch: memory_core.pc=ReferencePC+Displacement; return; i_bcc_branch_not_taken: cycle(BCCTime[ (Displacement > 0) ? 3 : 1 ]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned int ReferencePC=memory_core.pc+2; unsigned int Displacement; BCC_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); Displacement=Instr.Bits.Displacement; switch(Instr.Bits.Condition) { case 0: /* BRA */ sprintf(Instruction, "BRA"); break; case 1: /* BSR */ sprintf(Instruction, "BSR"); break; case 2: /* BHI */ sprintf(Instruction, "BHI"); break; case 3: /* BLS */ sprintf(Instruction, "BLS"); break; case 4: /* BCC */ sprintf(Instruction, "BCC"); break; case 5: /* BCS */ sprintf(Instruction, "BCS"); break; case 6: /* BNE */ sprintf(Instruction, "BNE"); break; case 7: /* BEQ */ sprintf(Instruction, "BEQ"); break; case 8: /* BVC */ sprintf(Instruction, "BVC"); break; case 9: /* BVS */ sprintf(Instruction, "BVS"); break; case 10: /* BPL */ sprintf(Instruction, "BPL"); break; case 11: /* BMI */ sprintf(Instruction, "BMI"); break; case 12: /* BGE */ sprintf(Instruction, "BGE"); break; case 13: /* BLT */ sprintf(Instruction, "BLT"); break; case 14: /* BGT */ sprintf(Instruction, "BGT"); break; case 15: /* BLE */ sprintf(Instruction, "BLE"); break; } if(Displacement==0) { Memory_RetrWordFromPC(&Displacement); Displacement = (short)Displacement; /* sprintf(&Instruction[3], ".W");*/ } /* else sprintf(&Instruction[3], ".B");*/ sprintf(Arg1, "0x%08lX", ReferencePC+Displacement); Arg2[0]=0; return 0; } int bcc_5206_register(void) { instruction_register(0x6000, 0xF000, &execute, &disassemble); return 3; } �����������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_ori.c��������������������������������������������������0000644�0001750�0000144�00000003366�11006121114�020563� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ /* FIXME: Unverified correct operation */ #include "coldfire.h" /* ORI Immediate (ORI) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ORITime=1; INSTRUCTION_2ARGS(ORI, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; ORI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 7, 4)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue | DValue; EA_PutValue(&Destination, Result); /* Set the status register * X - not affected * N - set it MSB or result is 1 * Z - set if result is zero * V,C always cleared */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); cycle(ORITime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ORI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "ORI.L"); Addressing_Print(32, 7, 4, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int ori_5206_register(void) { instruction_register(0x0080, 0xFFF8, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_movec.c������������������������������������������������0000644�0001750�0000144�00000007110�11006121114�021072� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* MoveC instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |A/D| Register | Control Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int MOVECTime=9; /* We are going to cheat here, and define this for the SECOND * word of the instr */ INSTRUCTION_3ARGS(MOVEC, unsigned AD,1, unsigned Register,3, unsigned ControlRegister,12); static void execute(void) { struct _Address Source; unsigned int SValue; MOVEC_Instr Instr; /* Get the instr, but we alreday know what it is */ Memory_RetrWordFromPC(&Instr.Code); /* Get the second word, that we care about */ Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, Instr.Bits.AD, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); if(SRBits->S) { /* Supervisor State */ switch(Instr.Bits.ControlRegister) { case 0x002: /* Cache Control Register */ memory_core.cacr = SValue; break; case 0x004: /* Access Control Register 0 */ SKYEYE_ERR("Storing 0x%08lx in the ACR0 is unimplemented!\n", SValue); break; case 0x005: /* Access Control Register 1 */ SKYEYE_ERR("Storing 0x%08lx in the ACR1 is unimplemented!\n", SValue); break; case 0x801: /* VBR */ memory_core.vbr = SValue; break; case 0x80F: /* Program Counter */ memory_core.pc = SValue; break; case 0xC00: /* ROM Base Address Register */ memory_core.rombar = SValue & 0xfffffc00; break; case 0xC04: /* SRAM Base Address Register */ memory_core.rambar = SValue & 0xfffffc00; break; case 0xC05: /**/ memory_core.rambar1 = SValue & 0xfffffc00; break; case 0xC0E: /**/ memory_core.mbar2 = SValue & 0xfffffc00; break; case 0xC0F: /* Module Base Address Register */ memory_core.mbar = SValue & 0xfffffc00; break; default: SKYEYE_ERR("Unimplemented Control register 0x%x\n", Instr.Bits.ControlRegister); break; } /* Condition code are not affected */ } else { /* User state */ /* FIXME: Generate an exception violation here */ } cycle(MOVECTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { MOVEC_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "MOVEC"); Addressing_Print(32, Instr.Bits.AD, Instr.Bits.Register, Arg1); switch(Instr.Bits.ControlRegister) { case 0x002: /* Cache Control Register */ sprintf(Arg2, "CACR"); break; case 0x004: /* Access Control Register 0 */ sprintf(Arg2, "ACR0"); break; case 0x005: /* Access Control Register 1 */ sprintf(Arg2, "ACR1"); break; case 0x801: /* VBR */ sprintf(Arg2, "VBR"); break; case 0x80F: /* Program Counter */ sprintf(Arg2, "PC"); break; case 0xC00: /* ROM Base Address Register */ sprintf(Arg2, "ROMBAR"); break; case 0xC04: /* SRAM Base Address Register */ sprintf(Arg2, "RAMBAR"); break; case 0xC0F: /* Module Base Address Register */ sprintf(Arg2, "MBAR"); break; default: sprintf(Arg2, "???"); break; } return 0; } int movec_5206_register(void) { instruction_register(0x4E7B, 0xFFFF, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_lsx.c��������������������������������������������������0000644�0001750�0000144�00000006512�11006121114�020574� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Logical Shift Left/Right LSL, LSR instructions */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 1 | 0 | Count/Reg | dr| 1 | 0 |i/r| 0 | 1 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int LSXTime=1; INSTRUCTION_7ARGS(LSX, unsigned Code3,4, unsigned CountReg,3, unsigned DR,1, unsigned Code2,2, unsigned IR,1, unsigned Code1,2, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; LSX_Instr Instr; int last_bit; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.IR==0) { /* Shift from count in instruction word */ SValue = Instr.Bits.CountReg; if(SValue == 0) SValue = 8; } else { if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.CountReg)) return; /* Get source, modulo 64 */ EA_GetValue(&SValue, &Source); SValue &= 0x0000003F; } if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&DValue, &Destination); if(SValue == 0) { SRBits->C = 0; Result = DValue; } else { last_bit = 0; if(Instr.Bits.DR==0) { /* Shift Right */ /* Catch if we are shifting the register clean, this * catchs any funny modulo arithmetic the native * hardware does with a shift */ if(SValue <= 32) last_bit = DValue & (0x1 << (SValue-1)); /* On x86, the instruction takes modulo 32, so a * shift by 0x20 actually shifts 0, and * 0x21 shifts 1, etc. but we want to be able * to shift everything out of the register */ Result = (SValue >= 32) ? 0 : (DValue >> SValue); } else { /* Shift Left */ if(SValue <= 32) last_bit = DValue & (0x80000000 >> (SValue-1)); Result = (SValue >= 32) ? 0 : (DValue << SValue); } SRBits->C = (last_bit) ? 1 : 0; SRBits->X = (last_bit) ? 1 : 0; } /* X - Set according to last bit shifted out of the operand; unaffected for shift count of 0 N - Set if result is -ve, cleared otherwise Z - Set if result is zero, cleared otherwise V - always cleared C - set according to the last bit shifted out of the operand; cleared for a shift count of 0 */ SRBits->N = ((int)Result < 0) ? 1 : 0; SRBits->Z = (Result == 0) ? 1 : 0; EA_PutValue(&Destination, Result); cycle(LSXTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { LSX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.DR==0) { /* Shift Right */ sprintf(Instruction, "LSR.L"); } else { /* Shift Left */ sprintf(Instruction, "LSL.L"); } if(Instr.Bits.IR==0) { /* Shift from count in instruction word */ int SValue = Instr.Bits.CountReg; if(SValue == 0) SValue = 8; sprintf(Arg1, "#0x%02lX", SValue); } else { sprintf(Arg1, "D%d", Instr.Bits.CountReg); } Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int lsx_5206_register(void) { instruction_register(0xE088, 0xF0D8, &execute, &disassemble); instruction_register(0xE088, 0xF0D8, &execute, &disassemble); return 2; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_scc.c��������������������������������������������������0000644�0001750�0000144�00000005521�11006121114�020535� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Set Conditionally */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 1 | Condition | 1 | 1 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ const char *code_mnemonic[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE"}; INSTRUCTION_4ARGS(SCC, unsigned Code2,4, unsigned Condition,4, unsigned Code1,5, unsigned Register,3); int SCCTime=1; static void execute(void) { struct _Address Destination; SCC_Instr Instr; unsigned char Result=0; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Destination, 8, 0, Instr.Bits.Register)) return; cycle(SCCTime); switch(Instr.Bits.Condition) { case 0: /* True */ Result=1; break; case 1: /* False */ break; case 2: /* SHI */ /* The docs say (!C or !Z), however processor seems to do * this: */ Result = SRBits->C || !SRBits->Z; break; case 3: /* SLS */ Result = SRBits->C || SRBits->Z; break; case 4: /* SCC */ Result = !SRBits->C; break; case 5: /* SCS */ Result = SRBits->C; break; case 6: /* SNE */ /* Set if they are not equal, ie Dest-Source != 0 */ Result = (!SRBits->Z); break; case 7: /* BEQ */ /* Don't set if they are not equal */ Result = (SRBits->Z); break; case 8: /* SVC */ Result = (!SRBits->V); break; case 9: /* SVS */ Result = SRBits->V; break; case 10: /* SPL */ Result = !SRBits->N; break; case 11: /* SMI */ Result = SRBits->N; break; case 12: /* SGE */ Result = ((SRBits->N && SRBits->V) || (!SRBits->N && !SRBits->V)); break; case 13: /* SLT */ Result = ((SRBits->N && !SRBits->V) || (!SRBits->N && SRBits->V)); break; case 14: /* SGT */ Result = ((SRBits->N && SRBits->V && !SRBits->Z) || (!SRBits->N && !SRBits->V && !SRBits->Z)); break; case 15: /* SLE */ Result = (SRBits->Z || (SRBits->N && !SRBits->V) || (!SRBits->N && SRBits->V) ); break; default: SKYEYE_ERR("Unknown Condition Code 0x%02x\n", Instr.Bits.Condition); return; } if(Result) Result = 0x000000FF; EA_PutValue(&Destination, Result); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { SCC_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "S%s", code_mnemonic[(int)Instr.Bits.Condition]); sprintf(Arg1, "D%d", Instr.Bits.Register); Arg2[0]=0; return 0; } int scc_5206_register(void) { instruction_register(0x50C0, 0xF0F8, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_suba.c�������������������������������������������������0000644�0001750�0000144�00000003326�11006121114�020720� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Subtract instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 1 | Register | 1 | 1 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int SUBATime[]={-1, 3, 3, 3, 3, 4, 3, -1 }; INSTRUCTION_5ARGS(SUBA, unsigned Code2,4, unsigned Register,3, unsigned Code1,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; SUBA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 1, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = DValue - SValue; /* Condition codes are not affected */ EA_PutValue(&Destination, Result); cycle(SUBATime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { SUBA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "SUBA.L"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 1, Instr.Bits.Register, Arg2); return 0; } int suba_5206_register(void) { instruction_register(0x91C0, 0xF1C0, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_link.c�������������������������������������������������0000644�0001750�0000144�00000004162�11006121114�020722� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Link and Allocate (LINK) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Displacement | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int LINKTime=2; INSTRUCTION_2ARGS(LINK, unsigned Code1,13, unsigned Register,3); static void execute(void) { unsigned int Displacement; struct _Address ARegister,Stack; unsigned int StackValue; LINK_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); Memory_RetrWordFromPC(&Displacement); Displacement = (short)Displacement; /* Get the A register, and push it to the stack */ if(!EA_GetFromPC(&ARegister, 32, 1, Instr.Bits.Register)) return; EA_GetValue(&StackValue, &ARegister); Stack_Push(32,StackValue); /* Now store the stack pointer in the register before modifying it */ if(!EA_GetFromPC(&Stack, 32, 1, 7)) return; EA_GetValue(&StackValue, &Stack); EA_PutValue(&ARegister, StackValue); /* Move the stack pointer Displacement bytes */ /* The displacement will be -ve, causes the SP to move down */ EA_PutValue(&Stack, StackValue + Displacement); cycle(LINKTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { LINK_Instr Instr; unsigned int Displacement; Memory_RetrWordFromPC(&Instr.Code); Memory_RetrWordFromPC(&Displacement); sprintf(Instruction, "LINK"); Addressing_Print(32, 1, Instr.Bits.Register, Arg1); /* Print manually because it uses negative numbers */ sprintf(Arg2, "#%hd", (short)Displacement); return 0; } int link_5206_register(void) { instruction_register(0x4E50, 0xFFF8, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_and.c��������������������������������������������������0000644�0001750�0000144�00000006102�11006121114�020523� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* AND instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 0 | Register | OPmode | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ANDTime[2][8]={{ 1, 3, 3, 3, 3, 4, 3, 1}, {-1, 3, 3, 3, 3, 4, 3, -1}}; INSTRUCTION_5ARGS(AND, unsigned Code1,4, unsigned Register,3, unsigned OPMode,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; AND_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.OPMode==2) { /* <EA>y & Dx */ if(Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for source"); return; } if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; } else if (Instr.Bits.OPMode==6) { /* Dy & <EA>x -> <EA>x */ if(Instr.Bits.EAMode==0) { SKYEYE_ERR("May not specify Dx for destination when source is Dx"); return; } else if (Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for destination when source is Dx"); return; } else if (Instr.Bits.EAMode==7 && Instr.Bits.EARegister==4) { SKYEYE_ERR("May not specify Immediate Addressing for destination"); return; } if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.Register)) return; if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; } else { SKYEYE_ERR("Unknown OPMode %d", Instr.Bits.OPMode); return; } EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue & DValue; EA_PutValue(&Destination, Result); /* Set the status register * X - Not affected * N - Set if source is -ve, cleared otherwise * Z - Set if source is zero, cleared otherwise * V - always cleared * C - always cleared */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); if (Instr.Bits.OPMode==2) cycle(ANDTime[0][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); else cycle(ANDTime[1][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { AND_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "AND.L"); if(Instr.Bits.OPMode==2) { /* <EA>y & Dx */ Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); } else { Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); } return 0; } int and_5206_register(void) { instruction_register(0xC000, 0xF000, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_lea.c��������������������������������������������������0000644�0001750�0000144�00000003212�11006121114�020521� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Load Effective Address (lea) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | ARegister | 1 | 1 | 1 | EAMode | EARegister| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int LEATime[8]={-1, 1, -1, -1, 1, 2, 1, -1}; INSTRUCTION_5ARGS(LEA, unsigned Code2,4, unsigned Register,3, unsigned Code1,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int SValue; LEA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 1, Instr.Bits.Register)) return; EA_GetEA(&SValue, &Source); /* Condition codes are not affected */ EA_PutValue(&Destination, SValue); cycle(LEATime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { LEA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "LEA"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 1, Instr.Bits.Register, Arg2); return 0; } int lea_5206_register(void) { instruction_register(0x41C0, 0xF1C0, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_dc.c���������������������������������������������������0000644�0001750�0000144�00000002272�11006121114�020353� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* DC.W */ /* Format ... well.. anything that any of the other instructions don't handle 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ INSTRUCTION_1ARG(DC, unsigned Code1,16); static void execute(void) { unsigned int dummy; /* Read the instruction, we already know what it is */ Memory_RetrWordFromPC(&dummy); /* Do an exception */ exception_do_exception(4); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned int dummy; Memory_RetrWordFromPC(&dummy); sprintf(Instruction, "DC.W"); sprintf(Arg1, "0x%04lx", dummy); Arg2[0]=0; return 0; } int dc_5206_register(void) { instruction_register(0x0000, 0x0000, &execute, &disassemble); return 0; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_cmpa.c�������������������������������������������������0000644�0001750�0000144�00000003325�11006121114�020705� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Compare address (CMPA) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | Register | 1 | 1 | 1 | EAMode |EARegister | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int CMPATime[8]={ 1, 3, 3, 3, 3, 4, 3, 1}; INSTRUCTION_5ARGS(CMPA, unsigned Code2,4, unsigned Register,3, unsigned Code1,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; CMPA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 1, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = DValue - SValue; /* Set the status register */ SR_Set(I_CMPA, SValue, DValue, Result); cycle(CMPATime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { CMPA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "CMPA.L"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 1, Instr.Bits.Register, Arg2); return 0; } int cmpa_5206_register(void) { instruction_register(0xB1C0, 0xF1C0, &execute, &disassemble); return 1; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/Makefile�������������������������������������������������0000644�0001750�0000144�00000001570�11006121114�020751� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������CROSS_COMPILE ?= EXTRA_CFLAGS ?= CC = $(CROSS_COMPILE)gcc CFLAGS = -Wall -fomit-frame-pointer -g -O2 -I../common -I../tracer $(EXTRA_CFLAGS) LD_R = $(CROSS_COMPILE)ld -r RM = rm -f LDFLAGS = BUILD = i.o C_SRCS = i_add.c i_adda.c i_addi.c i_addq.c i_addx.c i_and.c \ i_andi.c i_asx.c i_bcc.c i_btst.c i_clr.c i_cmp.c \ i_cmpa.c i_cmpi.c i_dc.c i_eor.c i_eori.c i_ext.c \ i_halt.c i_illegal.c i_jmp.c i_jsr.c i_lea.c \ i_link.c i_lsx.c i_move.c i_movec.c i_movem.c \ i_moveq.c i_movexr.c i_mulu_l.c i_mulu_w.c \ i_neg.c i_negx.c i_nop.c i_not.c i_or.c \ i_ori.c i_pea.c i_rte.c i_rts.c i_scc.c i_stop.c \ i_sub.c i_suba.c i_subi.c i_subq.c i_subx.c \ i_swap.c i_trap.c i_trapf.c i_tst.c i_unlk.c i_div.c OBJS = $(C_SRCS:.c=.o) all: $(BUILD) .c.o: $(CC) $(CFLAGS) -c $< clean: $(RM) $(OBJS) $(BUILD) $(BUILD): $(OBJS) $(LD_R) $(OBJS) -o $@ ����������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_negx.c�������������������������������������������������0000644�0001750�0000144�00000002652�11006121114�020730� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Negate with Excend (NEGX) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int NEGXTime=1; INSTRUCTION_2ARGS(NEGX, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Destination; unsigned int Result, DValue; NEGX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&DValue, &Destination); Result = 0 - DValue - (unsigned int)SRBits->X; SR_Set(I_NEGX, 0, DValue, Result); EA_PutValue(&Destination, Result); cycle(NEGXTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { NEGX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "NEGX.L"); Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Arg2[0]=0; return 0; } int negx_5206_register(void) { instruction_register(0x4080, 0xFFF8, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_nop.c��������������������������������������������������0000644�0001750�0000144�00000002231�11006121114�020554� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* No Operation (NOP) */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int NOPTime=3; INSTRUCTION_1ARG(NOP, unsigned Code1,16); static void execute(void) { unsigned int dummy; /* Read the instruction with out storing it.. we already know what it is */ Memory_RetrWordFromPC(&dummy); cycle(NOPTime); /* Everything takes some time...*/ return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned int dummy; Memory_RetrWordFromPC(&dummy); sprintf(Instruction, "NOP"); Arg1[0]=0; Arg2[0]=0; return 0; } int nop_5206_register(void) { instruction_register(0x4E71, 0xFFFF, &execute, &disassemble); return 1; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_add.c��������������������������������������������������0000644�0001750�0000144�00000005022�11006121114�020511� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Add instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 1 | Register | OPmode | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ADDTime[2][8]={{1, 3, 3, 3, 3, 4, 3, 1 }, {-1, 3, 3, 3, 3, 4, 3, -1 }}; INSTRUCTION_5ARGS(ADD, unsigned Code1,4, unsigned Register,3, unsigned OPMode,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; ADD_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.OPMode==2) { /* <EA>y + Dx */ if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; } else { /* Dy + <EA>x -> <EA>x */ if(Instr.Bits.EAMode==0) { SKYEYE_ERR("May not specify Dx for destination when source is Dx"); return; } else if (Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for destination when source is Dx"); return; } if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.Register)) return; if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; } EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue + DValue; SR_Set(I_ADD, SValue, DValue, Result); EA_PutValue(&Destination, Result); if(Instr.Bits.OPMode==2) /* <EA>y + Dx */ cycle(ADDTime[0][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); else cycle(ADDTime[1][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ADD_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "ADD.L"); if(Instr.Bits.OPMode==2) { /* <EA>y & Dx */ Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); } else { Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); } return 0; } int add_5206_register(void) { instruction_register(0xD000, 0xF000, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_subq.c�������������������������������������������������0000644�0001750�0000144�00000004327�11006121114�020742� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Subtract instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 1 | Data | 1 | 1 | 0 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int SUBQTime[]={1, 3, 3, 3, 3, 4, 3, -1}; INSTRUCTION_5ARGS(SUBQ, unsigned Code2,4, unsigned Data,3, unsigned Code1,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Destination; unsigned int Result, SValue, DValue; SUBQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); /* Instr.Data is the immedate data, 1-7 represents 1-7, 0 represents 8 */ SValue=Instr.Bits.Data; if(SValue==0) SValue = 8; if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(Instr.Bits.EAMode==7) { switch(Instr.Bits.EARegister) { case 2: SKYEYE_ERR("(d_16,PC) addressing mode invalid."); return; case 3: SKYEYE_ERR("(d_8,PC,Xn) addressing mode invalid."); return; case 4: SKYEYE_ERR("#<data> addressing mode invalid."); return; } } EA_GetValue(&DValue, &Destination); Result = DValue - SValue; /* Set the status register, the condition codes are unaffected when subtracting from an address register */ if(Instr.Bits.EAMode!=1) SR_Set(I_SUBQ, SValue, DValue, Result); else ; /* Address register */ EA_PutValue(&Destination, Result); cycle(SUBQTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { SUBQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "SUBQ.L"); sprintf(Arg1, "#0x%02X", (char)(Instr.Bits.Data == 0) ? 8 : Instr.Bits.Data); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); return 0; } int subq_5206_register(void) { instruction_register(0x5180, 0xF1C0, &execute, &disassemble); return 1; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_subx.c�������������������������������������������������0000644�0001750�0000144�00000003141�11006121114�020742� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* SubX instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 1 |Register Dx| 1 | 1 | 0 | 0 | 0 | 0 |Register Dy| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int SUBXTime=1; INSTRUCTION_4ARGS(SUBX, unsigned Code2,4, unsigned RegisterDx,3, unsigned Code1,6, unsigned RegisterDy,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; SUBX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.RegisterDy)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.RegisterDx)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = DValue - SValue - (int)SRBits->X; SR_Set(I_SUBX, SValue, DValue, Result); EA_PutValue(&Destination, Result); cycle(SUBXTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { SUBX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "SUBX.L"); Addressing_Print(32, 0, Instr.Bits.RegisterDy, Arg1); Addressing_Print(32, 0, Instr.Bits.RegisterDx, Arg2); return 0; } int subx_5206_register(void) { instruction_register(0x9180, 0xF1F8, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_illegal.c����������������������������������������������0000644�0001750�0000144�00000002214�11006121114�021372� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Generate Illegal Instruction (ILLEGAL) */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ INSTRUCTION_1ARG(ILLEGAL, unsigned Code,16); static void execute(void) { unsigned int dummy; /* Read the instruction with out storing it.. we already know what it is */ Memory_RetrWordFromPC(&dummy); exception_do_exception(4); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned int dummy; Memory_RetrWordFromPC(&dummy); sprintf(Instruction, "ILLEGAL"); Arg1[0]=0; Arg2[0]=0; return 0; } int illegal_5206_register(void) { instruction_register(0x4AFC, 0xFFFF, &execute, &disassemble); return 1; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_asx.c��������������������������������������������������0000644�0001750�0000144�00000005062�11006121114�020560� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Arithmetic Shift Left/Right ASL, ASR instructions */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 1 | 0 | Count/Reg | dr| 1 | 0 |i/r| 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ASXTime=1; INSTRUCTION_7ARGS(ASX, unsigned Code3,4, unsigned CountReg,3, unsigned DR,1, unsigned Code2,2, unsigned IR,1, unsigned Code1,2, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; ASX_Instr Instr; int x; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.IR==0) { /* Shift from count in instruction word */ SValue = Instr.Bits.CountReg; if(SValue == 0) SValue = 8; } else { if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.CountReg)) return; /* Get source, modulo 64 */ EA_GetValue(&SValue, &Source); SValue &= 0x0000003F; } if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&DValue, &Destination); Result = DValue; if(Instr.Bits.DR==0) { /* Shift Right */ for(x=0;x<SValue;x++) { SRBits->C = Result & 0x00000001; SRBits->X = Result & 0x00000001; Result >>= 1; if(Result & 0x40000000) Result |= 0x80000000; } } else { /* Shift Left */ for(x=0;x<SValue;x++) { SRBits->C = (Result & 0x80000000) ? 1 : 0; SRBits->X = (Result & 0x80000000) ? 1 : 0; Result <<= 1; } } SRBits->N=((signed int)Result<0) ? 1 : 0; SRBits->Z=(Result==0) ? 1 : 0; SRBits->V=0; EA_PutValue(&Destination, Result); cycle(ASXTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ASX_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.DR==0) { /* Shift Right */ sprintf(Instruction, "ASR.L"); } else { /* Shift Left */ sprintf(Instruction, "ASL.L"); } if(Instr.Bits.IR==0) { /* Shift from count in instruction word */ int SValue = Instr.Bits.CountReg; if(SValue == 0) SValue = 8; sprintf(Arg1, "#0x%02ld", SValue); } else { sprintf(Arg1, "D%d", Instr.Bits.CountReg); } Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int asx_5206_register(void) { instruction_register(0xE080, 0xF0D8, &execute, &disassemble); return 2; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_sub.c��������������������������������������������������0000644�0001750�0000144�00000005365�11006121114�020564� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Subtract instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 1 | Register | OPmode | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int SUBTime[2][8]={{1, 3, 3, 3, 3, 4, 3, 1 }, {-1, 3, 3, 3, 3, 4, 3, -1 }}; INSTRUCTION_5ARGS(SUB, unsigned Code1,4, unsigned Register,3, unsigned OPMode,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; SUB_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); /* printf("SUB: Register=%d, OPMode=%d, EAMode=%d, EARegister=%d\n", Register, OPMode, EAMode,EARegister);*/ if(Instr.Bits.OPMode==2) { /* <EA>y + Dx */ if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; } else if(Instr.Bits.OPMode==6) { /* Dy + <EA>x -> <EA>x */ if(Instr.Bits.EAMode==0) { SKYEYE_ERR("May not specify Dx for destination when source is Dx"); return; } else if(Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for destination when source is Dx"); return; } if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.Register)) return; if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; } else { SKYEYE_ERR("Unknown opcode %x\n", Instr.Bits.OPMode); return; } EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = DValue - SValue; /* Set the status register */ SR_Set(I_SUB, SValue, DValue, Result); EA_PutValue(&Destination, Result); if(Instr.Bits.OPMode==2) /* <EA>y + Dx */ cycle(SUBTime[0][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); else cycle(SUBTime[1][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { SUB_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "SUB.L"); if(Instr.Bits.OPMode==2) { /* <EA>y & Dx */ Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); } else { Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); } return 0; } int sub_5206_register(void) { instruction_register(0x9000, 0xF000, &execute, &disassemble); return 1; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_trapf.c������������������������������������������������0000644�0001750�0000144�00000004064�11006121114�021102� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Trapf instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | OpMode | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Optional Immediate Word | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Optional Immediate Word | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int TRAPFTime=1; INSTRUCTION_2ARGS(TRAPF, unsigned Code1,13, unsigned OpMode,3); static void execute(void) { TRAPF_Instr Instr; unsigned int dummy; Memory_RetrWordFromPC(&Instr.Code); switch(Instr.Bits.OpMode) { case 0x2: /* One extension word */ Memory_RetrWordFromPC(&dummy); break; case 0x3: /* Two extension words */ Memory_RetrLongWordFromPC(&dummy); break; case 0x4: /* No extension words */ break; default: SKYEYE_ERR("Invalid OpMode=%d\n", Instr.Bits.OpMode); break; } cycle(TRAPFTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { TRAPF_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); switch(Instr.Bits.OpMode) { case 0x2: /* One extension word */ sprintf(Instruction, "TRAPF.W"); Addressing_Print(16, 7, 4, Arg1); break; case 0x3: /* Two extension words */ sprintf(Instruction, "TRAPF.L"); Addressing_Print(32, 7, 4, Arg1); break; case 0x4: /* No extension words */ sprintf(Instruction, "TRAPF"); break; default: SKYEYE_ERR("Invalid OpMode=%d\n", Instr.Bits.OpMode); break; } Arg2[0]=0; return 0; } int trapf_5206_register(void) { instruction_register(0x51F8, 0xFFF8, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_btst.c�������������������������������������������������0000644�0001750�0000144�00000010555�11006121114�020744� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Bit Test (BTST) instruction */ /* Format, Bit number dynamic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | Register | 1 | OP | EAMode |EARegister | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Format, Bit number static (immediate data) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | OP | EAMode |EARegister | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Bit Number | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OP: 00 == BTST 01 == BCHG 10 == BCLR 11 == BSET */ INSTRUCTION_6ARGS(BTST, unsigned Code2,4, unsigned Register,3, unsigned Dynamic,1, unsigned OP,2, unsigned EAMode,3, unsigned EARegister,3); int BTSTTime[2][8]={{1, 3, 3, 3, 3, -1, -1, 1}, {2, 3, 3, 3, 3, 4, 3, -1}}; static void execute(void) { struct _Address Destination, BitNum; unsigned int DValue, BitNumValue; int mask; BTST_Instr Instr; /* If the destination is a data register, size is longword, else, * size is byte */ char size; /* Pull the instruction */ Memory_RetrWordFromPC(&Instr.Code); /* Do this after fetching the instruction */ size = (Instr.Bits.EAMode == 0) ? 32 : 8; /* Get the bit number FIRST, since the order of the opcode is * BTST [bit number] [EA offset] */ /* For dynamic (Dynamic==1) a data register is given, need 32 bits * from the register * For static (Dynamic==0) the bit number is the displacement * specified in the extension word, (8 bits from the PC) */ if(Instr.Bits.Dynamic == 1) { /* Dynamic, pull bit from a register */ if(!EA_GetFromPC(&BitNum, 32, 0, Instr.Bits.Register)) return; } else { /* Get the bit number from immediate data */ /* Magic happening here.... Remember, size 8 from the * PC skips the first byte, and only grabs the second * one of the word, so this is OK */ if(!EA_GetFromPC(&BitNum, 8, 7, 4)) return; } EA_GetValue(&BitNumValue, &BitNum); BitNumValue %= size; /* Longword for Data register, all others byte operation */ if(!EA_GetFromPC(&Destination, size, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetValue(&DValue, &Destination); mask = (0x1 << BitNumValue); /* Condition codes */ /* If the tested bit is 0, Z is set, else it is cleared */ /* Else, unchanged */ SRBits->Z = (DValue & mask) ? 0 : 1; switch(Instr.Bits.OP) { case 0: /* BTST */ /* leave the bit alone, short circuit to done */ return; case 1: /* BCHG */ /* Toggle the bit */ DValue = (DValue & ~mask) | (DValue ^ mask); break; case 2: /* BCLR */ /* Clear the bit */ DValue &= ~mask; break; case 3: /* BSET */ /* Set the bit */ DValue |= mask; break; } EA_PutValue(&Destination, DValue); if (Instr.Bits.Dynamic == 1) cycle(BTSTTime[0][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); else cycle(BTSTTime[1][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { BTST_Instr Instr; char size = (Instr.Bits.EAMode == 0) ? 32 : 8; Memory_RetrWordFromPC(&Instr.Code); switch(Instr.Bits.OP) { case 0: /* BTST */ /* sprintf(Instruction, "BTST%s", (size == 32) ? ".L" : ""); */ strcpy(Instruction, "BTST"); break; case 1: /* BCHG */ strcpy(Instruction, "BCHG"); break; case 2: /* BCLR */ strcpy(Instruction, "BCLR"); break; case 3: /* BSET */ strcpy(Instruction, "BSET"); break; } if(Instr.Bits.Dynamic == 1) Addressing_Print(32, 0, Instr.Bits.Register, Arg1); else Addressing_Print(8, 7, 4, Arg1); Addressing_Print(size, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); return 0; } int btst_5206_register(void) { /* Register both forms for the "same" instruction */ /* Dynamic */ instruction_register(0x0100, 0xF100, &execute, &disassemble); /* Static */ instruction_register(0x0800, 0xFF00, &execute, &disassemble); return 4; /* BTST, BCLR, BSET, BCHG */ } ���������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_addq.c�������������������������������������������������0000644�0001750�0000144�00000004317�11006121114�020700� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Add quick (ADDQ) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 1 | Data | 0 | 1 | 0 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ADDQTime[]={1, 3, 3, 3, 3, 4, 3, -1}; INSTRUCTION_5ARGS(ADDQ, unsigned Code2,4, unsigned Data,3, unsigned Code1,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Destination; unsigned int Result, SValue, DValue; ADDQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); /* Instr.Data is the immedate data, 1-7 represents 1-7, 0 represents 8 */ SValue=Instr.Bits.Data; if(SValue==0) SValue = 8; if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetValue(&DValue, &Destination); if(Instr.Bits.EAMode==7) { switch(Instr.Bits.EARegister) { case 2: SKYEYE_ERR("(d_16,PC) addressing mode invalid."); return; case 3: SKYEYE_ERR("(d_8,PC,Xn) addressing mode invalid."); return; case 4: SKYEYE_ERR("#<data> addressing mode invalid."); return; } } Result = SValue + DValue; /* The condition codes are not affected when the destation is an address register */ if(Instr.Bits.EAMode!=1) SR_Set(I_ADDQ, SValue, DValue, Result); else ; /* Destination is an address register */ EA_PutValue(&Destination, Result); cycle(ADDQTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ADDQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "ADDQ.L"); sprintf(Arg1, "#0x%02X", (Instr.Bits.Data == 0) ? 8 : Instr.Bits.Data); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); return 0; } int addq_5206_register(void) { instruction_register(0x5080, 0xF1C0, &execute, &disassemble); return 1; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_eor.c��������������������������������������������������0000644�0001750�0000144�00000005642�11006121114�020556� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ /* FIXME: Unverified correct operation */ #include "coldfire.h" /* EOR instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | Register | OPmode | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int EORTime[8]={1, 3, 3, 3, 3, 4, 3, -1}; INSTRUCTION_5ARGS(EOR, unsigned Code1,4, unsigned Register,3, unsigned OPMode,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; EOR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.OPMode==2) { /* <EA>y ^ Dx */ if(Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for source"); return; } if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; } else if (Instr.Bits.OPMode==6) { /* Dy & <EA>x -> <EA>x */ /* if(Instr.Bits.EAMode==0) { SKYEYE_ERR("May not specify Dx for destination when source is Dx"); return; } else if (Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for destination when source is Dx"); return; } else */ if (Instr.Bits.EAMode==7 && Instr.Bits.EARegister==4) { SKYEYE_ERR("May not specify Immediate Addressing for destination"); return; } if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.Register)) return; if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; } else { SKYEYE_ERR("Unknown OPMode %d", Instr.Bits.OPMode); return; } EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue ^ DValue; EA_PutValue(&Destination, Result); /* Set the status register * X - not affected * N - set if MSB or result is 1 * Z - set if result is zero * V,C always cleared */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); cycle(EORTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { EOR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "EOR.L"); if(Instr.Bits.OPMode==2) { /* <EA>y ^ Dx */ Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); } else { Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); } return 0; } int eor_5206_register(void) { instruction_register(0xB180, 0xF1C0, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_subi.c�������������������������������������������������0000644�0001750�0000144�00000003464�11006121114�020733� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Subtract Immediate (SUBI) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Upper Word of Immediate Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Lower Word of Immediate Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int SUBITime=1; INSTRUCTION_2ARGS(SUBI, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; SUBI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 7, 4)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = DValue - SValue; /* Set the status register */ SR_Set(I_SUBI, SValue, DValue, Result); EA_PutValue(&Destination, Result); cycle(SUBITime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { SUBI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "SUBI.L"); Addressing_Print(32, 7, 4, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int subi_5206_register(void) { instruction_register(0x0480, 0xFFF8, &execute, &disassemble); return 1; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_addi.c�������������������������������������������������0000644�0001750�0000144�00000003130�11006121114�020660� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Add Immediate (ADDI) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ADDITime=1; /* All the rest of the modes are not valid */ INSTRUCTION_2ARGS(ADDI, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; ADDI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 7, 4)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue + DValue; /* Set the status register */ SR_Set(I_ADDI, SValue, DValue, Result); EA_PutValue(&Destination, Result); cycle(ADDITime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ADDI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "ADDI.L"); Addressing_Print(32, 7, 4, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int addi_5206_register(void) { instruction_register(0x0680, 0xFFF8, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_tst.c��������������������������������������������������0000644�0001750�0000144�00000004247�11006121114�020603� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Test (TST) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | Size | EAMode |EARegister | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int TSTTime[8]={1, 3, 3, 3, 3, 4, 3, 1}; INSTRUCTION_4ARGS(TST, unsigned Code1,8, unsigned Size,2, unsigned EAMode,3, unsigned EARegister,3); const short TST_SizeBits[4]={ 8 , 16 , 32 , 0 }; const char TST_SizeStr[4]= {'B', 'W', 'L', '?'}; static void execute(void) { struct _Address Source; unsigned int SValue; TST_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.Size == 3) { SKYEYE_ERR("Invalid size=3"); return; } if(!EA_GetFromPC(&Source, TST_SizeBits[(short)Instr.Bits.Size], Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetValue(&SValue, &Source); /* Set the status register; * X - Not affected * N - Set if source is -ve, cleared otherwise * Z - Set if source is zero, cleared otherwise * V - always cleared * C - always cleared */ SRBits->N = ((int)SValue < 0); SRBits->Z = (SValue == 0); SRBits->V = 0; SRBits->C = 0; cycle(TSTTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { TST_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "TST.%c", TST_SizeStr[(short)Instr.Bits.Size]); Addressing_Print(TST_SizeBits[(short)Instr.Bits.Size], Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Arg2[0]=0; return 0; } int tst_5206_register(void) { /* This needs to be 3 registers, 4A[11xx]x is taken (ILLEGAL) :( */ instruction_register(0x4A00, 0xFFC0, &execute, &disassemble); instruction_register(0x4A40, 0xFFC0, &execute, &disassemble); instruction_register(0x4A80, 0xFFC0, &execute, &disassemble); return 1; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_eori.c�������������������������������������������������0000644�0001750�0000144�00000003322�11006121114�020720� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* EORI Immediate (EORI) instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Register | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int EORITime=1; INSTRUCTION_2ARGS(EORI, unsigned Code1,13, unsigned Register,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; EORI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, 7, 4)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue ^ DValue; EA_PutValue(&Destination, Result); /* Set the status register * X - not affected * N - set if MSB or result is 1 * Z - set if result is zero * V,C always cleared */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); cycle(EORITime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { EORI_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "EORI.L"); Addressing_Print(32, 7, 4, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int eori_5206_register(void) { instruction_register(0x0A80, 0xFFF8, &execute, &disassemble); return 1; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_moveq.c������������������������������������������������0000644�0001750�0000144�00000003257�11006121114�021120� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Move instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | Register | 0 | Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int MOVEQTime=1; INSTRUCTION_4ARGS(MOVEQ, unsigned Code2,4, unsigned Register,3, unsigned Code1,1, signed Data,8); static void execute(void) { struct _Address Destination; unsigned int SValue; MOVEQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); SValue=(unsigned int)Instr.Bits.Data; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_PutValue(&Destination, SValue); /* X - not affected N - set if result is -ve, cleared otherwise Z - set if result is zero, cleared otherwise V - always cleared C - always cleared */ /* Set the status register */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)SValue < 0); SRBits->Z = (SValue == 0); cycle(MOVEQTime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { MOVEQ_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "MOVEQ"); sprintf(Arg1, "#0x%02X", ((char)Instr.Bits.Data) & 0x000000FF); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int moveq_5206_register(void) { instruction_register(0x7000, 0xF100, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_mulu_w.c�����������������������������������������������0000644�0001750�0000144�00000005025�11006121114�021274� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Word Unsigned multiply (MUL.W) instruction */ /* Word Unsigned multiply (MULS.W) instruction */ /* Format for MUL.W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 0 | Register | 0 | 1 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Format for MULS.W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 0 | Register |U/S| 1 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int MULWTime[8]={9, 11, 11, 11, 11, 12, 11, 9}; INSTRUCTION_6ARGS(MUL_W, unsigned Code2,4, unsigned Register,3, unsigned US,1, unsigned Code1,2, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; MUL_W_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.EAMode==1) { SKYEYE_ERR("May Not specify Address Register (Ay) for MUL.W"); return; } if(!EA_GetFromPC(&Source, 16, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetValue(&SValue, &Source); if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; EA_GetValue(&DValue, &Destination); if(Instr.Bits.US == 0) { /* Unsigned */ Result = (unsigned short)(SValue&0x0000FFFF) * (unsigned short)(DValue&0x0000FFFF); } else { Result = (short)(SValue&0x0000FFFF) * (short)(DValue&0x0000FFFF); } /* Set the status register */ memory_core.sr &= 0xFF00; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); EA_PutValue(&Destination, Result); cycle(MULWTime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { MUL_W_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.US == 0) /* Unsigned */ sprintf(Instruction, "MULU.W"); else sprintf(Instruction, "MULS.W"); Addressing_Print(16, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); return 0; } int mul_w_5206_register(void) { instruction_register(0xC0C0, 0xF0C0, &execute, &disassemble); return 2; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_rte.c��������������������������������������������������0000644�0001750�0000144�00000002246�11006121114�020560� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Return from Exception (RTE) */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int RTETime=8; INSTRUCTION_1ARG(RTE, unsigned Code1,16); static void execute(void) { unsigned int dummy; /* Read the instruction with out storing it.. we already know what it is */ Memory_RetrWordFromPC(&dummy); exception_restore_from_stack_frame(); cycle(RTETime); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { unsigned int dummy; Memory_RetrWordFromPC(&dummy); sprintf(Instruction, "RTE"); Arg1[0]=0; Arg2[0]=0; return 0; } int rte_5206_register(void) { instruction_register(0x4E73, 0xFFFF, &execute, &disassemble); return 1; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_adda.c�������������������������������������������������0000644�0001750�0000144�00000003277�11006121114�020664� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Add instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 1 | Register | 1 | 1 | 1 | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ADDATime[]={-1, 3, 3, 3, 3, 4, 3, -1 }; INSTRUCTION_5ARGS(ADDA, unsigned Code2,4, unsigned Register,3, unsigned Code1,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; ADDA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 1, Instr.Bits.Register)) return; EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue + DValue; /* Status register is not affected */ EA_PutValue(&Destination, Result); cycle(ADDATime[cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { ADDA_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "ADDA.L"); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 1, Instr.Bits.Register, Arg2); return 0; } int adda_5206_register(void) { instruction_register(0xD1C0, 0xF1C0, &execute, &disassemble); return 1; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/instruction/i_or.c���������������������������������������������������0000644�0001750�0000144�00000005775�11006121114�020420� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* OR instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 0 | Register | OPmode | EA Mode |EA Register| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ int ORTime[2][8]={{1, 3, 3, 3, 3, 4, 3, 1}, {-1, 3, 3, 3, 3, 4, 3, -1}}; INSTRUCTION_5ARGS(OR, unsigned Code1,4, unsigned Register,3, unsigned OPMode,3, unsigned EAMode,3, unsigned EARegister,3); static void execute(void) { struct _Address Source,Destination; unsigned int Result, SValue, DValue; OR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); if(Instr.Bits.OPMode==2) { /* <EA>y | Dx */ if(Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for source"); return; } if(!EA_GetFromPC(&Source, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; if(!EA_GetFromPC(&Destination, 32, 0, Instr.Bits.Register)) return; } else if (Instr.Bits.OPMode==6) { /* Dy | <EA>x -> <EA>x */ if(Instr.Bits.EAMode==0) { SKYEYE_ERR("May not specify Dx for destination when source is Dx"); return; } else if (Instr.Bits.EAMode==1) { SKYEYE_ERR("May not specify Ax for destination when source is Dx"); return; } else if (Instr.Bits.EAMode==7 && Instr.Bits.EARegister==4) { SKYEYE_ERR("May not specify Immediate Addressing for destination"); return; } if(!EA_GetFromPC(&Source, 32, 0, Instr.Bits.Register)) return; if(!EA_GetFromPC(&Destination, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; } else { SKYEYE_ERR("Unknown OPMode %d", Instr.Bits.OPMode); return; } EA_GetValue(&SValue, &Source); EA_GetValue(&DValue, &Destination); Result = SValue | DValue; EA_PutValue(&Destination, Result); /* Set the status register * X - not affected * N - set it MSB or result is 1 * Z - set if result is zero * V,C always cleared */ memory_core.sr &= 0xFFF0; SRBits->N = ((int)Result < 0); SRBits->Z = (Result == 0); if (Instr.Bits.OPMode==2) cycle(ORTime[0][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); else cycle(ORTime[1][cycle_EA(Instr.Bits.EARegister,Instr.Bits.EAMode)]); return; } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { OR_Instr Instr; Memory_RetrWordFromPC(&Instr.Code); sprintf(Instruction, "OR.L"); if(Instr.Bits.OPMode==2) { /* <EA>y | Dx */ Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); Addressing_Print(32, 0, Instr.Bits.Register, Arg2); } else { Addressing_Print(32, 0, Instr.Bits.Register, Arg1); Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); } return 0; } int or_5206_register(void) { instruction_register(0x8000, 0xF000, &execute, &disassemble); return 1; } ���skyeye-1.2.5_REL/arch/coldfire/instruction/i_movem.c������������������������������������������������0000644�0001750�0000144�00000010213�11006121114�021102� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Movem instruction */ /* Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 0 | 0 | 1 | dr| 0 | 0 | 1 | 1 | EAMode | EARegister| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | A7..A0,D7...D0 Register List Mask | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ INSTRUCTION_5ARGS(MOVEM, unsigned Code2,5, unsigned Direction,1, unsigned Code1,4, unsigned EAMode,3, unsigned EARegister,3); int MOVEMTime=1; static void execute(void) { struct _Address Address; unsigned int AddressValue; MOVEM_Instr Instr; unsigned int RegisterListMask; short move_count; int x; Memory_RetrWordFromPC(&Instr.Code); Memory_RetrWordFromPC(&RegisterListMask); /* dr field: 0- register to memory 1- memory to register */ if(Instr.Bits.EAMode != 2 && Instr.Bits.EAMode != 5) { printf("MOVEM: EAMode 0x%02x is not allowed\n", Instr.Bits.EAMode); return; } /* Get the effective address */ if(!EA_GetFromPC(&Address, 32, Instr.Bits.EAMode, Instr.Bits.EARegister)) return; EA_GetEA(&AddressValue, &Address); move_count=0; if(Instr.Bits.Direction==0) { /* Registers to memory */ for(x=0;x<8;x++,RegisterListMask>>=1) { if(RegisterListMask & 0x0001) { /* Save this register */ Memory_Stor(32, AddressValue + (move_count*4), memory_core.d[x]); move_count++; } } for(x=8;x<16;x++,RegisterListMask>>=1) { if(RegisterListMask & 0x0001) { /* Save this register */ Memory_Stor(32, AddressValue + (move_count*4), memory_core.a[x-8]); move_count++; } } } else { /* Memory to registers */ for(x=0;x<8;x++,RegisterListMask>>=1) { if(RegisterListMask & 0x0001) { /* Retr this register */ Memory_Retr(&memory_core.d[x], 32, AddressValue + (move_count*4)); move_count++; } } for(x=8;x<16;x++,RegisterListMask>>=1) { if(RegisterListMask & 0x0001) { /* Retr this register */ Memory_Retr(&memory_core.a[x-8], 32, AddressValue + (move_count*4)); move_count++; } } } /* Condition codes are not affected */ cycle((MOVEMTime + move_count)); return; } static int movem_print(char *buffer, char reg, unsigned int reg_list) { int x; char n_printed = 0; char one_printed = 0; char *orignal_buffer = buffer; /* reg_list number 8 should be 0, so after the 8th register, we will * always write out the last string of registers (if any) */ for(x=0;x<9;x++,reg_list >>= 1) { if(reg_list & 1) { if(!n_printed) { /* Last one not printed, and this one needs it */ /* If at least one is printed, we need a comma */ if(one_printed) buffer += sprintf(buffer, ","); buffer += sprintf(buffer, "%c%d", reg, x); one_printed = 1; } n_printed++; } else { if(n_printed > 1) { buffer += sprintf(buffer, "-%c%d", reg, x-1); n_printed = 0; } } } return (buffer - orignal_buffer); } static int disassemble(char *Instruction, char *Arg1, char *Arg2) { MOVEM_Instr Instr; char *regStr; short size; unsigned int RegisterListMask; Memory_RetrWordFromPC(&Instr.Code); Memory_RetrWordFromPC(&RegisterListMask); sprintf(Instruction, "MOVEM.L"); if(Instr.Bits.Direction==0) { /* Registers to memory */ regStr = Arg1; Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg2); } else { Addressing_Print(32, Instr.Bits.EAMode, Instr.Bits.EARegister, Arg1); regStr = Arg2; } regStr[0]=0; /* RegisterListMask 1 for "yes", 0 for no A7 A6 A5 ... A1 A0 D7 D6 .... D1 D0 */ size = movem_print(regStr, 'D', RegisterListMask & 0x00FF); if(size && (RegisterListMask & 0xFF00)) { regStr += size; regStr += sprintf(regStr, "/"); } movem_print(regStr, 'A', (RegisterListMask & 0xFF00) >> 8); return 0; } int movem_5206_register(void) { instruction_register(0x48C0, 0xFBC0, &execute, &disassemble); return 1; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/tracer/��������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�016212� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/tracer/generated.channels.h������������������������������������������0000644�0001750�0000144�00000003133�10541455476�022136� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* We define TRACER_DECLARE(ch) so we can use this list more than once */ TRACER_DECLARE(ea) TRACER_DECLARE(exception) TRACER_DECLARE(handlers) TRACER_DECLARE(i) TRACER_DECLARE(i_add) TRACER_DECLARE(i_adda) TRACER_DECLARE(i_addi) TRACER_DECLARE(i_addq) TRACER_DECLARE(i_addx) TRACER_DECLARE(i_and) TRACER_DECLARE(i_andi) TRACER_DECLARE(i_asx) TRACER_DECLARE(i_bcc) TRACER_DECLARE(i_btst) TRACER_DECLARE(i_clr) TRACER_DECLARE(i_cmp) TRACER_DECLARE(i_cmpa) TRACER_DECLARE(i_cmpi) TRACER_DECLARE(i_dc) TRACER_DECLARE(i_div) TRACER_DECLARE(i_eor) TRACER_DECLARE(i_eori) TRACER_DECLARE(i_ext) TRACER_DECLARE(i_halt) TRACER_DECLARE(i_illegal) TRACER_DECLARE(i_jmp) TRACER_DECLARE(i_jsr) TRACER_DECLARE(i_lea) TRACER_DECLARE(i_link) TRACER_DECLARE(i_lsx) TRACER_DECLARE(i_move) TRACER_DECLARE(i_movec) TRACER_DECLARE(i_movem) TRACER_DECLARE(i_moveq) TRACER_DECLARE(i_movexr) TRACER_DECLARE(i_mulu_l) TRACER_DECLARE(i_mul_w) TRACER_DECLARE(i_neg) TRACER_DECLARE(i_negx) TRACER_DECLARE(i_nop) TRACER_DECLARE(i_not) TRACER_DECLARE(i_or) TRACER_DECLARE(i_ori) TRACER_DECLARE(i_pea) TRACER_DECLARE(i_rte) TRACER_DECLARE(i_rts) TRACER_DECLARE(isa) TRACER_DECLARE(i_scc) TRACER_DECLARE(i_stop) TRACER_DECLARE(i_sub) TRACER_DECLARE(i_suba) TRACER_DECLARE(i_subi) TRACER_DECLARE(i_subq) TRACER_DECLARE(i_subx) TRACER_DECLARE(i_swap) TRACER_DECLARE(i_trap) TRACER_DECLARE(i_trapf) TRACER_DECLARE(i_tst) TRACER_DECLARE(i_unlk) TRACER_DECLARE(main) TRACER_DECLARE(memory) TRACER_DECLARE(misc) TRACER_DECLARE(monitor) TRACER_DECLARE(network) TRACER_DECLARE(ram) TRACER_DECLARE(run) TRACER_DECLARE(serial) TRACER_DECLARE(sim) TRACER_DECLARE(timer) �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/tracer/Makefile������������������������������������������������������0000644�0001750�0000144�00000001035�10600011124�017642� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������CROSS_COMPILE ?= EXTRA_CFLAGS ?= TOPSRCDIR = .. BUILD = tracer.o C_SRCS = main.c CC = $(CROSS_COMPILE)gcc CFLAGS = -Wall -fomit-frame-pointer -g -O2 -I$(TOPSRCDIR) $(EXTRA_CFLAGS) LD_R = $(CROSS_COMPILE)ld -r RM = rm -f LDFLAGS = OBJS = $(C_SRCS:.c=.o) all: $(BUILD) .c.o: $(CC) $(CFLAGS) -c $< clean: $(RM) $(OBJS) $(BUILD) generated.channels.h: ./mktracech.sh .. distclean: $(RM) generated.channels.h $(BUILD): generated.channels.h $(OBJS) $(LD_R) $(OBJS) -o $@ # Deps tracer.o: generated.channels.h main.c tracer.h ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/tracer/README��������������������������������������������������������0000644�0001750�0000144�00000000421�10541455476�017112� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Notes: - The tracer subdir should be the first one build in a 'make'. It generates the channel header file, which is needed by tracer.h. - Delete the generated.channels.h file if you add a channel, and rebuild _everything_. Some channel numbers could have changed. �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/tracer/mktracech.sh��������������������������������������������������0000755�0001750�0000144�00000000601�10541455476�020532� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#!/bin/sh # Arg 1: Directory to start search in # We always output to current directory outfile="generated.channels.h" echo "/* We define TRACER_DECLARE(ch) so we can use this list more than once */" > $outfile find $1 -name \*.c -exec cat {} \; \ | grep TRACER_DEFAULT_CHANNEL\ | sed -e "s/TRACER_DEFAULT_CHANNEL/TRACER_DECLARE/"\ | sed -e "s/;.*$//" | sort | uniq >> $outfile �������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/tracer/tracer.h������������������������������������������������������0000644�0001750�0000144�00000003775�10541455476�017702� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/*************************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see ../LICENSE for more details */ /* */ /*************************************/ #ifndef TRACER_H #define TRACER_H /* THANKS: to the WINE project.. www.winehq.com.. for many ideas on how * to make this :) */ /* If you define TRACER_OFF in your code, it will compile out all the tracer * stuff for that source file */ #ifdef TRACER_OFF #undef TRACER_ENABLE #else #define TRACER_ENABLE #endif struct _TRACER_Info { char *Name; char Enabled; }; extern struct _TRACER_Info TRACER_Info[]; int tracer_printf(char *msg, ...); int tracer_setuptrace(char *str); #define TRACER_DECLARE(ch) TRACER_##ch, enum _TRACER_Channels { #include "generated.channels.h" TRACER_Last }; #undef TRACER_DECLARE #define __TPRINTF_DUMMY(x...) #define __TPRINTF(chnumber) if(TRACER_Info[chnumber].Enabled) \ tracer_printf("%s:%s(): ",TRACER_Info[chnumber].Name, \ __FUNCTION__),\ tracer_printf #ifdef TRACER_ENABLE #define TRACER_DEFAULT_CHANNEL(ch) static const enum _TRACER_Channels TRACER_default = TRACER_##ch #define TRACE __TPRINTF(TRACER_default) #define TRACE_(ch) __TPRINTF(TRACER_##ch) /* #define ERR tracer_printf("%s:%s(): ",TRACER_Info[TRACER_default].Name,__FUNCTION__);\ tracer_printf */ #define ERR tracer_printf("%s:%s(): ",__FILE__,__FUNCTION__);\ tracer_printf #define ERR_(ch) tracer_printf("%s:%s(): ",TRACER_Info[TRACER_##ch].Name,__FUNCTION__);\ tracer_printf #define IFTRACE (TRACER_Info[TRACER_default].Enabled) #define IFTRACE_(ch) (TRACER_Info[ch].Enabled) #else #define TRACER_DEFAULT_CHANNEL(ch) #define TRACE __TPRINTF_DUMMY #define TRACE_(ch) __TPRINTF_DUMMY #define ERR __TPRINTF_DUMMY #define ERR_(ch) __TPRINTF_DUMMY #define IFTRACE 0 #define IFTRACE_(ch) 0 #endif #endif ���skyeye-1.2.5_REL/arch/coldfire/tracer/main.c��������������������������������������������������������0000644�0001750�0000144�00000003241�10541455476�017325� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/*************************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see ../LICENSE for more details */ /* */ /*************************************/ /* THANKS: to the WINE project.. www.winehq.com.. for many ideas on how * to make this :) */ #include <stdio.h> #include <stdlib.h> #include <stdarg.h> #include <string.h> #include "tracer.h" #define TRACER_DECLARE(ch) {#ch,0}, struct _TRACER_Info TRACER_Info[] = { #include "generated.channels.h" {NULL,0} }; #undef TRACER_DECLARE int tracer_indent=0; int tracer_printf(char *msg, ...) { va_list Args; int x; /*f(*msg=='+') tracer_indent++;*/ /*f(*msg!=':') { printf("%02d:" tracer_indent); for(x=0;x<tracer_indent;x++) printf(" "); } */ va_start(Args,msg); x=vprintf(msg, Args); va_end(Args); /*f(*msg=='-') tracer_indent--;*/ return x; } int tracer_setuptrace(char *str) { char *s, *original_s; char *ptr; int x; char enable; if(!str) return 0; s = malloc(strlen(str) + 1); strcpy(s, str); original_s = s; while(1) { enable=1; ptr=strchr(s,','); if(ptr) *ptr=0; if(s[0] == '-') { enable=0; s++; } for(x=0;TRACER_Info[x].Name != NULL; x++) { if(strcmp(TRACER_Info[x].Name,s)==0 || strcmp("all",s)==0) { TRACER_Info[x].Enabled=enable; } } /* End of string, break. */ if(!ptr) break; s = ptr+1; } printf("Tracing ["); for(x=0;TRACER_Info[x].Name != NULL; x++) { if(TRACER_Info[x].Enabled) { printf(" %s ", TRACER_Info[x].Name); } } printf("]\n"); free(original_s); return 1; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/interp.c�������������������������������������������������������������0000644�0001750�0000144�00000047503�10541455476�016433� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* interp.c -- Simulator for Motorola 68HC11/68HC12 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, the GNU debugger. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sim-main.h" #include "sim-assert.h" #include "sim-hw.h" #include "sim-options.h" #include "hw-tree.h" #include "hw-device.h" #include "hw-ports.h" #include "elf32-m68hc1x.h" #ifndef MONITOR_BASE # define MONITOR_BASE (0x0C000) # define MONITOR_SIZE (0x04000) #endif static void sim_get_info (SIM_DESC sd, char *cmd); char *interrupt_names[] = { "reset", "nmi", "int", NULL }; #ifndef INLINE #if defined(__GNUC__) && defined(__OPTIMIZE__) #define INLINE __inline__ #else #define INLINE #endif #endif struct sim_info_list { const char *name; const char *device; }; struct sim_info_list dev_list_68hc11[] = { {"cpu", "/m68hc11"}, {"timer", "/m68hc11/m68hc11tim"}, {"sio", "/m68hc11/m68hc11sio"}, {"spi", "/m68hc11/m68hc11spi"}, {"eeprom", "/m68hc11/m68hc11eepr"}, {0, 0} }; struct sim_info_list dev_list_68hc12[] = { {"cpu", "/m68hc12"}, {"timer", "/m68hc12/m68hc12tim"}, {"sio", "/m68hc12/m68hc12sio"}, {"spi", "/m68hc12/m68hc12spi"}, {"eeprom", "/m68hc12/m68hc12eepr"}, {0, 0} }; /* Cover function of sim_state_free to free the cpu buffers as well. */ static void free_state (SIM_DESC sd) { if (STATE_MODULES (sd) != NULL) sim_module_uninstall (sd); sim_state_free (sd); } /* Give some information about the simulator. */ static void sim_get_info (SIM_DESC sd, char *cmd) { sim_cpu *cpu; cpu = STATE_CPU (sd, 0); if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-')) { int i; struct hw *hw_dev; struct sim_info_list *dev_list; const struct bfd_arch_info *arch; arch = STATE_ARCHITECTURE (sd); cmd++; if (arch->arch == bfd_arch_m68hc11) dev_list = dev_list_68hc11; else dev_list = dev_list_68hc12; for (i = 0; dev_list[i].name; i++) if (strcmp (cmd, dev_list[i].name) == 0) break; if (dev_list[i].name == 0) { sim_io_eprintf (sd, "Device '%s' not found.\n", cmd); sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n"); return; } hw_dev = sim_hw_parse (sd, dev_list[i].device); if (hw_dev == 0) { sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device); return; } hw_ioctl (hw_dev, 23, 0); return; } cpu_info (sd, cpu); interrupts_info (sd, &cpu->cpu_interrupts); } void sim_board_reset (SIM_DESC sd) { struct hw *hw_cpu; sim_cpu *cpu; const struct bfd_arch_info *arch; const char *cpu_type; cpu = STATE_CPU (sd, 0); arch = STATE_ARCHITECTURE (sd); /* hw_cpu = sim_hw_parse (sd, "/"); */ if (arch->arch == bfd_arch_m68hc11) { cpu->cpu_type = CPU_M6811; cpu_type = "/m68hc11"; } else { cpu->cpu_type = CPU_M6812; cpu_type = "/m68hc12"; } hw_cpu = sim_hw_parse (sd, cpu_type); if (hw_cpu == 0) { sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type); return; } cpu_reset (cpu); hw_port_event (hw_cpu, 3, 0); cpu_restart (cpu); } static int sim_hw_configure (SIM_DESC sd) { const struct bfd_arch_info *arch; struct hw *device_tree; sim_cpu *cpu; arch = STATE_ARCHITECTURE (sd); if (arch == 0) return 0; cpu = STATE_CPU (sd, 0); cpu->cpu_configured_arch = arch; device_tree = sim_hw_parse (sd, "/"); if (arch->arch == bfd_arch_m68hc11) { cpu->cpu_interpretor = cpu_interp_m6811; if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0) { /* Allocate core managed memory */ /* the monitor */ sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx", /* MONITOR_BASE, MONITOR_SIZE */ 0x8000, M6811_RAM_LEVEL, 0x8000); sim_do_commandf (sd, "memory region 0x000@%d,0x8000", M6811_RAM_LEVEL); sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F"); if (cpu->bank_start < cpu->bank_end) { sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000", cpu->bank_virtual, M6811_RAM_LEVEL); sim_hw_parse (sd, "/m68hc11/use_bank 1"); } } if (cpu->cpu_start_mode) { sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode); } if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0) { sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5"); sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio"); } if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0) { /* M68hc11 Timer configuration. */ sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim"); sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim"); } /* Create the SPI device. */ if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0) { sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi"); } if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0) { /* M68hc11 persistent ram configuration. */ sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256"); sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram"); sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified"); /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */ } if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0) { sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr"); } sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11"); sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11"); sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11"); sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11"); cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11"); } else { cpu->cpu_interpretor = cpu_interp_m6812; if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0) { /* Allocate core external memory. */ sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx", 0x8000, M6811_RAM_LEVEL, 0x8000); sim_do_commandf (sd, "memory region 0x000@%d,0x8000", M6811_RAM_LEVEL); if (cpu->bank_start < cpu->bank_end) { sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000", cpu->bank_virtual, M6811_RAM_LEVEL); sim_hw_parse (sd, "/m68hc12/use_bank 1"); } sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF"); } if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg")) { sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8"); sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1"); } if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0) { /* M68hc11 Timer configuration. */ sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim"); sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim"); } /* Create the SPI device. */ if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0) { sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi"); } if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0) { /* M68hc11 persistent ram configuration. */ sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192"); sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram"); sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified"); } if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0) { sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr"); } sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12"); sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12"); sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12"); sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12"); cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12"); } return 1; } /* Get the memory bank parameters by looking at the global symbols defined by the linker. */ static int sim_get_bank_parameters (SIM_DESC sd, bfd* abfd) { sim_cpu *cpu; int symsize; int symbol_count, i; unsigned size; asymbol** asymbols; asymbol** current; cpu = STATE_CPU (sd, 0); symsize = bfd_get_symtab_upper_bound (abfd); if (symsize < 0) { sim_io_eprintf (sd, "Cannot read symbols of program"); return 0; } asymbols = (asymbol **) xmalloc (symsize); symbol_count = bfd_canonicalize_symtab (abfd, asymbols); if (symbol_count < 0) { sim_io_eprintf (sd, "Cannot read symbols of program"); return 0; } size = 0; for (i = 0, current = asymbols; i < symbol_count; i++, current++) { const char* name = bfd_asymbol_name (*current); if (strcmp (name, BFD_M68HC11_BANK_START_NAME) == 0) { cpu->bank_start = bfd_asymbol_value (*current); } else if (strcmp (name, BFD_M68HC11_BANK_SIZE_NAME) == 0) { size = bfd_asymbol_value (*current); } else if (strcmp (name, BFD_M68HC11_BANK_VIRTUAL_NAME) == 0) { cpu->bank_virtual = bfd_asymbol_value (*current); } } free (asymbols); cpu->bank_end = cpu->bank_start + size; cpu->bank_shift = 0; for (; size > 1; size >>= 1) cpu->bank_shift++; return 0; } static int sim_prepare_for_program (SIM_DESC sd, bfd* abfd) { sim_cpu *cpu; int elf_flags = 0; cpu = STATE_CPU (sd, 0); if (abfd != NULL) { asection *s; if (bfd_get_flavour (abfd) == bfd_target_elf_flavour) elf_flags = elf_elfheader (abfd)->e_flags; cpu->cpu_elf_start = bfd_get_start_address (abfd); /* See if any section sets the reset address */ cpu->cpu_use_elf_start = 1; for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next) { if (s->flags & SEC_LOAD) { bfd_size_type size; size = bfd_get_section_size (s); if (size > 0) { bfd_vma lma; if (STATE_LOAD_AT_LMA_P (sd)) lma = bfd_section_lma (abfd, s); else lma = bfd_section_vma (abfd, s); if (lma <= 0xFFFE && lma+size >= 0x10000) cpu->cpu_use_elf_start = 0; } } } if (elf_flags & E_M68HC12_BANKS) { if (sim_get_bank_parameters (sd, abfd) != 0) sim_io_eprintf (sd, "Memory bank parameters are not initialized\n"); } } if (!sim_hw_configure (sd)) return SIM_RC_FAIL; /* reset all state information */ sim_board_reset (sd); return SIM_RC_OK; } SIM_DESC sim_open (SIM_OPEN_KIND kind, host_callback *callback, bfd *abfd, char **argv) { SIM_DESC sd; sim_cpu *cpu; sd = sim_state_alloc (kind, callback); cpu = STATE_CPU (sd, 0); SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); /* for compatibility */ current_alignment = NONSTRICT_ALIGNMENT; current_target_byte_order = BIG_ENDIAN; cpu_initialize (sd, cpu); if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) { free_state (sd); return 0; } /* getopt will print the error message so we just have to exit if this fails. FIXME: Hmmm... in the case of gdb we need getopt to call print_filtered. */ if (sim_parse_args (sd, argv) != SIM_RC_OK) { /* Uninstall the modules to avoid memory leaks, file descriptor leaks, etc. */ free_state (sd); return 0; } /* Check for/establish the a reference program image. */ if (sim_analyze_program (sd, (STATE_PROG_ARGV (sd) != NULL ? *STATE_PROG_ARGV (sd) : NULL), abfd) != SIM_RC_OK) { free_state (sd); return 0; } /* Establish any remaining configuration options. */ if (sim_config (sd) != SIM_RC_OK) { free_state (sd); return 0; } if (sim_post_argv_init (sd) != SIM_RC_OK) { /* Uninstall the modules to avoid memory leaks, file descriptor leaks, etc. */ free_state (sd); return 0; } if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK) { free_state (sd); return 0; } /* Fudge our descriptor. */ return sd; } void sim_close (SIM_DESC sd, int quitting) { /* shut down modules */ sim_module_uninstall (sd); /* Ensure that any resources allocated through the callback mechanism are released: */ sim_io_shutdown (sd); /* FIXME - free SD */ sim_state_free (sd); return; } void sim_set_profile (int n) { } void sim_set_profile_size (int n) { } /* Generic implementation of sim_engine_run that works within the sim_engine setjmp/longjmp framework. */ void sim_engine_run (SIM_DESC sd, int next_cpu_nr, /* ignore */ int nr_cpus, /* ignore */ int siggnal) /* ignore */ { sim_cpu *cpu; SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); cpu = STATE_CPU (sd, 0); while (1) { cpu_single_step (cpu); /* process any events */ if (sim_events_tickn (sd, cpu->cpu_current_cycle)) { sim_events_process (sd); } } } int sim_trace (SIM_DESC sd) { sim_resume (sd, 0, 0); return 1; } void sim_info (SIM_DESC sd, int verbose) { const char *cpu_type; const struct bfd_arch_info *arch; /* Nothing to do if there is no verbose flag set. */ if (verbose == 0 && STATE_VERBOSE_P (sd) == 0) return; arch = STATE_ARCHITECTURE (sd); if (arch->arch == bfd_arch_m68hc11) cpu_type = "68HC11"; else cpu_type = "68HC12"; sim_io_eprintf (sd, "Simulator info:\n"); sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type); sim_get_info (sd, 0); sim_module_info (sd, verbose || STATE_VERBOSE_P (sd)); } SIM_RC sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env) { return sim_prepare_for_program (sd, abfd); } void sim_set_callbacks (host_callback *p) { /* m6811_callback = p; */ } int sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) { sim_cpu *cpu; uint16 val; int size = 2; cpu = STATE_CPU (sd, 0); switch (rn) { case A_REGNUM: val = cpu_get_a (cpu); size = 1; break; case B_REGNUM: val = cpu_get_b (cpu); size = 1; break; case D_REGNUM: val = cpu_get_d (cpu); break; case X_REGNUM: val = cpu_get_x (cpu); break; case Y_REGNUM: val = cpu_get_y (cpu); break; case SP_REGNUM: val = cpu_get_sp (cpu); break; case PC_REGNUM: val = cpu_get_pc (cpu); break; case PSW_REGNUM: val = cpu_get_ccr (cpu); size = 1; break; case PAGE_REGNUM: val = cpu_get_page (cpu); size = 1; break; default: val = 0; break; } if (size == 1) { memory[0] = val; } else { memory[0] = val >> 8; memory[1] = val & 0x0FF; } return size; } int sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) { uint16 val; sim_cpu *cpu; cpu = STATE_CPU (sd, 0); val = *memory++; if (length == 2) val = (val << 8) | *memory; switch (rn) { case D_REGNUM: cpu_set_d (cpu, val); break; case A_REGNUM: cpu_set_a (cpu, val); return 1; case B_REGNUM: cpu_set_b (cpu, val); return 1; case X_REGNUM: cpu_set_x (cpu, val); break; case Y_REGNUM: cpu_set_y (cpu, val); break; case SP_REGNUM: cpu_set_sp (cpu, val); break; case PC_REGNUM: cpu_set_pc (cpu, val); break; case PSW_REGNUM: cpu_set_ccr (cpu, val); return 1; case PAGE_REGNUM: cpu_set_page (cpu, val); return 1; default: break; } return 2; } void sim_size (int s) { ; } void sim_do_command (SIM_DESC sd, char *cmd) { char *mm_cmd = "memory-map"; char *int_cmd = "interrupt"; sim_cpu *cpu; cpu = STATE_CPU (sd, 0); /* Commands available from GDB: */ if (sim_args_command (sd, cmd) != SIM_RC_OK) { if (strncmp (cmd, "info", sizeof ("info") - 1) == 0) sim_get_info (sd, &cmd[4]); else if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0)) sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n"); else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0) sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n"); else sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); } /* If the architecture changed, re-configure. */ if (STATE_ARCHITECTURE (sd) != cpu->cpu_configured_arch) sim_hw_configure (sd); } /* Halt the simulator after just one instruction */ static void has_stepped (SIM_DESC sd, void *data) { ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP); } /* Generic resume - assumes the existance of sim_engine_run */ void sim_resume (SIM_DESC sd, int step, int siggnal) { sim_engine *engine = STATE_ENGINE (sd); jmp_buf buf; int jmpval; ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); /* we only want to be single stepping the simulator once */ if (engine->stepper != NULL) { sim_events_deschedule (sd, engine->stepper); engine->stepper = NULL; } sim_module_resume (sd); /* run/resume the simulator */ engine->jmpbuf = &buf; jmpval = setjmp (buf); if (jmpval == sim_engine_start_jmpval || jmpval == sim_engine_restart_jmpval) { int last_cpu_nr = sim_engine_last_cpu_nr (sd); int next_cpu_nr = sim_engine_next_cpu_nr (sd); int nr_cpus = sim_engine_nr_cpus (sd); sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus); if (next_cpu_nr >= nr_cpus) next_cpu_nr = 0; /* Only deliver the siggnal ]sic] the first time through - don't re-deliver any siggnal during a restart. */ if (jmpval == sim_engine_restart_jmpval) siggnal = 0; /* Install the stepping event after having processed some pending events. This is necessary for HC11/HC12 simulator because the tick counter is incremented by the number of cycles the instruction took. Some pending ticks to process can still be recorded internally by the simulator and sim_events_preprocess will handle them. If the stepping event is inserted before, these pending ticks will raise the event and the simulator will stop without having executed any instruction. */ if (step) engine->stepper = sim_events_schedule (sd, 0, has_stepped, sd); #ifdef SIM_CPU_EXCEPTION_RESUME { sim_cpu* cpu = STATE_CPU (sd, next_cpu_nr); SIM_CPU_EXCEPTION_RESUME(sd, cpu, siggnal); } #endif sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal); } engine->jmpbuf = NULL; sim_module_suspend (sd); } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/Makefile.am����������������������������������������������������������0000644�0001750�0000144�00000003407�11006120402�016764� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������cf_mach = mach/skyeye_mach_mcf5249.c mach/skyeye_mach_mcf5272.c cf_comm = common/addressing.c common/cf_arch_interface.c common/exception.c common/i.c common/ram.c common/board.c common/cycle.c common/handlers.c common/memory.c cf_insn = instruction/i_adda.c instruction/i_dc.c instruction/i_movem.c instruction/i_scc.c \ instruction/i_add.c instruction/i_div.c instruction/i_moveq.c instruction/i_stop.c \ instruction/i_addi.c instruction/i_eor.c instruction/i_movexr.c instruction/i_suba.c \ instruction/i_addq.c instruction/i_eori.c instruction/i_mulu_l.c instruction/i_sub.c \ instruction/i_addx.c instruction/i_ext.c instruction/i_mulu_w.c instruction/i_subi.c \ instruction/i_and.c instruction/i_halt.c instruction/i_neg.c instruction/i_subq.c \ instruction/i_andi.c instruction/i_illegal.c instruction/i_negx.c instruction/i_subx.c \ instruction/i_asx.c instruction/i_jmp.c instruction/i_nop.c instruction/i_swap.c \ instruction/i_bcc.c instruction/i_jsr.c instruction/i_not.c instruction/i_trap.c \ instruction/i_btst.c instruction/i_lea.c instruction/i_or.c instruction/i_trapf.c \ instruction/i_clr.c instruction/i_link.c instruction/i_ori.c instruction/i_tst.c \ instruction/i_cmpa.c instruction/i_lsx.c instruction/i_pea.c instruction/i_unlk.c \ instruction/i_cmp.c instruction/i_move.c instruction/i_rte.c \ instruction/i_cmpi.c instruction/i_movec.c instruction/i_rts.c libcoldfire_a_SOURCES = $(cf_mach) $(cf_comm) $(cf_insn) noinst_LIBRARIES = libcoldfire.a DEFS = -g -O2 -D_FILE_OFFSET_BITS=64 -DSTANDALONE -DDEFAULT_INLINE=0 INCLUDES = -I./common -I$(top_srcdir)/utils/debugger -I$(top_srcdir)/device/uart @COMMON_INCLUDES@ ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/��������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�016222� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/memory.c������������������������������������������������������0000644�0001750�0000144�00000022650�10703156132�017711� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include <stdio.h> #include <stdlib.h> #include <string.h> /*#define TRACER_OFF*/ #include "coldfire.h" /* longword - (msb) 3 2 1 0 (lsb) * Big endian: * b3 b2 b1 b0 * Little endian: * b0 b1 b2 b3 */ /* External defs that need to be initialized */ struct _memory_core memory_core; struct _SR *SRBits = (struct _SR *)&memory_core.sr; /* memory core copy with values used when reset */ static struct _memory_core memory_core_reset_values; TRACER_DEFAULT_CHANNEL(memory); static struct _memory_module *memory_module = NULL; static int memory_module_count=0; static int memory_module_count_max=0; /* Make a list of pointers to segments. Note: we don't make a list of segments * directly, because some segments will want to save a pointer to themselves, * and they can't do that if we're realloc()ing the list as we add more items. */ struct _memory_segment_list_item { struct _memory_segment *seg; }; static struct _memory_segment_list_item *memory_segment_list = NULL; static int memory_segment_count=0; static int memory_segment_count_max=0; void memory_module_register(char *name, void (*setup)(struct _memory_segment *s)) { if(memory_module_count == memory_module_count_max) { memory_module_count_max += 4; memory_module = realloc(memory_module, sizeof(struct _memory_module) * memory_module_count_max); } memory_module[memory_module_count].name = strdup(name); memory_module[memory_module_count].setup = setup; memory_module_count++; } static unsigned int zero_register = 0; void memory_module_setup_segment(char *module_name, int base_register, int base, int len) { struct _memory_segment *s; struct _memory_segment_list_item *i; int x; char movable = 1; /* Setup the memory segment */ if(memory_segment_count == memory_segment_count_max) { memory_segment_count_max += 4; memory_segment_list = realloc(memory_segment_list, sizeof(struct _memory_segment_list_item) * memory_segment_count_max); } i = &memory_segment_list[memory_segment_count]; s = malloc(sizeof(struct _memory_segment)); i->seg = s; memset(s, 0, sizeof(struct _memory_segment)); s->base = base; s->base_register = base_register; /* The mask is the inverted length * len 0x100 == mask FFFFFF00 */ s->mask = ~(len - 1); /* Find the module, and run the module setup */ for(x=0;x<memory_module_count;x++) { if(strcasecmp(memory_module[x].name, module_name) == 0) { memory_module[x].setup(s); break; } } if(x==memory_module_count) { /* Not found */ printf("Could not find module for [%s]\n", module_name); } /* See if everything above registerd a base address register, if not * then give it the zero address */ if(s->base_register == NULL) { s->base_register = &zero_register; movable=0; } printf("0x%08lx -> 0x%08lx %s\n", *s->base_register + s->base, *s->base_register + s->base + ~s->mask, movable ? "(movable)" : ""); printf(" "); fflush(stdout); memory_segment_count++; } struct _memory_segment *memory_find_segment_for(unsigned int offset) { int x; struct _memory_segment_list_item *i; for(x=0,i=&memory_segment_list[0];x<memory_segment_count;x++,i++) { /* FIXME: optimize this by pre-calculation */ struct _memory_segment *s = i->seg; register unsigned int b = *s->base_register + s->base; if( (offset & s->mask) == b) { return s; } } return NULL; } static void memory_core_reset(void) { /* resetore default values */ memory_core.pc_instruction_begin = 0x0; memory_core.sr = memory_core_reset_values.sr; memory_core.vbr = memory_core_reset_values.vbr; memory_core.mbar = memory_core_reset_values.mbar; memory_core.rambar = memory_core_reset_values.rambar; memory_core.rombar = memory_core_reset_values.rombar; memory_core.pc = memory_core_reset_values.pc; memory_core.a[7] = memory_core_reset_values.a[7] & 0xFFFFFFF0; } void memory_core_set_reset_values(char *s) { int argc; char *argv[16]; int x; struct _reg{ char *name; unsigned int *ptr; } regs[] = { { "mbar", &memory_core_reset_values.mbar }, { "rombar", &memory_core_reset_values.rombar }, { "rambar", &memory_core_reset_values.rambar }, { "vbr", &memory_core_reset_values.vbr }, { "sr", &memory_core_reset_values.sr }, { "pc", &memory_core_reset_values.pc }, { "sp", &memory_core_reset_values.a[7] }, { NULL, NULL }}; for(x=0;x<argc;x+=2) { unsigned int value; int i; sscanf(argv[x+1], "%lx", &value); for(i=0; regs[i].name != NULL; i++) { if(strcasecmp(argv[x], regs[i].name) == 0) { *(regs[i].ptr) = value; } } } } void memory_reset(void) { int x; struct _memory_segment_list_item *i; memory_core_reset(); /* Write the rombar to the entries in the vector table */ for(x=0;x<256;x++) Memory_Stor(32, (x*4)+memory_core.vbr, memory_core.rombar); for(x=0,i=&memory_segment_list[0];x<memory_segment_count;x++,i++) { struct _memory_segment *s = i->seg; if(s->reset) s->reset(s); } #if 0 TRACE("finding memory length\n"); /* Detect the length of the memory */ x = ; while(1) { x += 0x100; if(!memory_seek(x)) { break; } } TRACE("length=0x%08lx\n", x); /* Start A7 pointing aligned at the end of memory */ memory_core.a[7]=(x & 0xFFFFFFF0) -4; #endif /* Fill out the values of the PC and the SP in the vector table */ Memory_Stor(32, memory_core.vbr, memory_core.a[7]); Memory_Stor(32, memory_core.vbr+4, memory_core.pc); } void Memory_Init(void) { /* First reset the core, this just sets the core regsters, useful * because the modules depend on some of the core registers, like * the rombar and the mbar (just so they print properly) */ memory_core_reset(); printf("Loading memory modules...\n"); ram_init(); /* timer_5206_init(); serial_5206_init(); sim_5206_init(); sim_5307_init(); isa_init(); */ } void Memory_DeInit(void) { int x; struct _memory_segment_list_item *i; for(x=0,i=&memory_segment_list[0];x<memory_segment_count;x++,i++) { struct _memory_segment *s = i->seg; s->fini(s); if(s->code) free(s->code); free(s); } free(memory_segment_list); } /* See if we can seek to address at offset */ char memory_seek(unsigned int offset) { struct _memory_segment *s; s = memory_find_segment_for(offset); return (s==NULL) ? 0 : 1; } /* Desc: Retrieves a value from the memory * Returns: 1 if successful, 0 if something bad happened * Notes: This always first retrieves a long into *Result, then it trims it down */ char Memory_Retr(unsigned int *Result, short Size, int Offset) { struct _memory_segment *s; unsigned int base_offset; s = memory_find_segment_for(Offset); if(s) { base_offset = (unsigned int)Offset - (*s->base_register + s->base); /* base_offset = (unsigned int)Offset & ~(s->base); */ return s->read(s, Result, Size, base_offset); } else{ if(Offset >= memory_core.mbar && Offset < (memory_core.mbar + memory_core.mbar_size)) return memory_core.mbar_read(Result, Size, (Offset - memory_core.mbar)); if(Offset >= memory_core.mbar2 && Offset < (memory_core.mbar2 + memory_core.mbar2_size)) return memory_core.mbar2_read(Result, Size, (Offset - memory_core.mbar2)); } /* Coulnd't find it in the tables */ printf("retr retr failed for size=%d, offset=0x%08lx, pc=0x%x\n", Size, Offset, memory_core.pc); skyeye_exit(1); return 0; } char Memory_Stor(short Size, int Offset, unsigned int Value) { struct _memory_segment *s; unsigned int base_offset; /* Value will be in whatever endianness the computer is */ s = memory_find_segment_for(Offset); if(s) { base_offset = (unsigned int)Offset - (*s->base_register + s->base); /* base_offset = (unsigned int)Offset & ~(s->base); */ return s->write(s, Size, base_offset, Value); } else{ if(Offset >= memory_core.mbar && Offset < (memory_core.mbar + memory_core.mbar_size)) return memory_core.mbar_write(Size, (Offset - memory_core.mbar), Value); if(Offset >= memory_core.mbar2 && Offset < (memory_core.mbar2 + memory_core.mbar2_size)) return memory_core.mbar2_write(Size, (Offset - memory_core.mbar2), Value); } /* Exception 2, access error */ printf("retr stor failed for size=%d, offset=0x%08lx, pc=0x%x\n", Size, Offset, memory_core.pc); skyeye_exit(1); return 0; } char Memory_RetrFromPC(unsigned int *Result, short Size) { char ReturnValue; switch(Size) { case 32: ReturnValue = Memory_Retr(Result, 32, memory_core.pc); memory_core.pc+=4; return ReturnValue; case 16: ReturnValue = Memory_Retr(Result, 16, memory_core.pc); memory_core.pc+=2; return ReturnValue; case 8: memory_core.pc+=1; /* Skip the first byte */ ReturnValue = Memory_Retr(Result, 8, memory_core.pc); memory_core.pc+=1; /* Go past the byte we just read */ return ReturnValue; } return 0; } void memory_update(void) { int x; struct _memory_segment_list_item *i; for(x=0, i=&memory_segment_list[0];x<memory_segment_count;x++,i++) { struct _memory_segment *s = i->seg; if(s->update) s->update(s); } } void memory_dump_segments(void) { int x; struct _memory_segment_list_item *i; for(x=0, i=&memory_segment_list[0];x<memory_segment_count;x++,i++) { struct _memory_segment *s = i->seg; printf("%s: @%p, base_reg=%p, base=0x%08lx, data=%p\n", s->name, s, s->base_register, s->base, s->data); } } ����������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/exception.c���������������������������������������������������0000644�0001750�0000144�00000014371�11006120657�020400� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ /*#define SKYEYE_DBGR_OFF*/ #include "coldfire.h" SKYEYE_DBGR_DEFAULT_CHANNEL(exception); static short exception_pending = 0; static unsigned int (*iack_func[8])(unsigned int interrupt_level) = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; void exception_check_and_handle(void) { int x; if(!exception_pending) return; SKYEYE_DBG("exception_pending = 0x%04x\n", exception_pending); /* if the mask is 7, do nothing, if the mask is 0, check * all interrupts 7->1, interrupts level 0 doesn't make sense * FIXME: can the coldfire fire an interrupt with priority 0 ? */ SKYEYE_DBG("currint interrupt mask is %d, checking 7->%d\n", SRBits->InterruptPriorityMask, SRBits->InterruptPriorityMask+1); for(x=7; x>=SRBits->InterruptPriorityMask+1; x--) { if(iack_func[x] != NULL) { unsigned int vector; SKYEYE_DBG("Found interrupt_level %d to do exception.\n", x); vector = (iack_func[x])(x); SKYEYE_DBG("iack_func returned vector %lu\n", vector); exception_push_stack_frame(vector); /* Set the new interrupt priority */ SRBits->InterruptPriorityMask = x; /* Set the Master/Interrupt bit to 0 */ SRBits->M = 0; SKYEYE_DBG(" Interrupt Priority mask is now %d\n", SRBits->InterruptPriorityMask); /* Do the RAW exception */ exception_do_raw_exception(vector); return; } } } void exception_post(unsigned int interrupt_level, unsigned int (*func)(unsigned int interrupt_level) ) { SKYEYE_DBG("Exception posted at interrupt level %d\n", interrupt_level); exception_pending |= (0x1 << interrupt_level); iack_func[interrupt_level] = func; } void exception_withdraw(unsigned int interrupt_level) { SKYEYE_DBG("Exception withdrawn at interrupt level %d\n", interrupt_level); if(iack_func[interrupt_level] == NULL) { SKYEYE_ERR("Attempting to withdraw interrupt level %d which is not set.\n", interrupt_level); } exception_pending &= ~(0x1 << interrupt_level); iack_func[interrupt_level] = NULL; } /* This table is for whether the PC should be set to the next instruction * after the fault, or the current instruction, this is only the first 16 * Vectors.. all others are '0' * * 0 = Next address 1 = Fault address */ static char exception_pc_location[16] = { 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0 }; void exception_push_stack_frame(short vector) { unsigned int PC_to_push = memory_core.pc; unsigned int stack_frame; /* Restore the PC to the fault address */ SKYEYE_DBG("pushing exception stack frame for exception vector=%d\n", vector); if(vector < 16) { if(exception_pc_location[vector] == 1) PC_to_push = memory_core.pc_instruction_begin; } /* See if we can read from SP-4 and SP-8 */ if(!memory_seek(memory_core.a[7]-4) || !memory_seek(memory_core.a[7]-8)) { /* Push won't fit */ printf("pushing to SP=0x%08lx for vector %d would cause an error\n", memory_core.a[7], vector); /* location of a known good stack pointer: * - 5206, the SP is in the MBAR, 32 bit offset #1 * */ Memory_Retr(&memory_core.a[7], 32, memory_core.vbr); printf("SP reset to 0x%08lx\n", memory_core.a[7]); /* Force return to monitor for debugging.*/ printf("Forcing Autovector Interrupt 7\n"); exception_push_stack_frame(31); //Monitor_HandleException(31); exception_restore_from_stack_frame(); } /* Stack Frame: * 31 27 25 17 15 0 * +--------+---------+-------------+---------+------------+ * | Format | FS[3:2] | Vector[7:0] | FS[1:0] | SR | * +--------+---------+-------------+---------+------------+ * | PC | * +-------------------------------------------------------+ */ /* Build the stack frame in a portable fashion */ stack_frame = ((0x4 | (memory_core.a[7] & 0x3)) << 28) | (0x0 << 26) | ((vector & 0xFF) << 18) | (0x0 << 16) | (memory_core.sr & 0xFFFF); SKYEYE_DBG("Pushing PC [0x%x] and StackFrame [0x%x]\n", PC_to_push, *(int *)&stack_frame); /* Align the stack to the next longword offset */ /* FIXME: I'm not convinced that this is correct memory_core.a[7] &= 0xfffffffc;*/ /* Push the PC to the stack */ Stack_Push(32, PC_to_push); /* Push the rest of the stack frame */ Stack_Push(32, *(int *)&stack_frame); } void exception_restore_from_stack_frame(void) { int frame; /* Pop the SR and PC off the stack */ frame = Stack_Pop(32); memory_core.sr = frame & 0x0000FFFF; memory_core.pc = Stack_Pop(32); /* Align the stack according to the format */ /* FIXME: I'm not convinced that this is correct memory_core.a[7] += (frame & 0x30000000 >> 28);*/ SKYEYE_DBG("Set SR=0x%08lx\n", memory_core.sr); SKYEYE_DBG("Set PC=0x%08lx\n", memory_core.pc); } int exception_do_raw_exception(short vector) { unsigned int offset=0; static struct _memory_segment *seg; /* Find the jump offset in the vbr */ SKYEYE_DBG("Doing Exception Vector=%d, vbr=0x%08lx\n", vector, memory_core.vbr); /* If this falis, we could go into an infinite loop, with an invalid * memory access exception */ if(!Memory_Retr(&offset, 32, memory_core.vbr + (vector*4))) return 0; SKYEYE_DBG("ISR is at 0x%08lx\n", offset); /* Assert the S bit, and clear the T bit */ SRBits->S = 1; SRBits->T = 0; /* If the offset is in the rom, (the base_register for the * segment the ISR is in is the address of the rombar) * then we'll ask the monitor to handle the exception */ seg = memory_find_segment_for(offset); if( seg->base_register == &memory_core.rombar) { /* Handler in rom, somwhere. Ask monitor to handle the * exception for us . * Monitor provides an alternative for every exception */ //Monitor_HandleException(vector); /* Restore the process for monitor, because it doens't * know how to do it */ exception_restore_from_stack_frame(); return 0; } memory_core.pc=offset; SKYEYE_DBG("Set PC to ISR offset [0x%x]\n", memory_core.pc); SKYEYE_DBG("Done\n"); return 0; } int exception_do_exception(short vector) { //return 0; exception_push_stack_frame(vector); return exception_do_raw_exception(vector); } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/addressing.c��������������������������������������������������0000644�0001750�0000144�00000031007�10541455476�020535� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include "coldfire.h" /* Addressing Mode Mode Register Dy 000 memory_core.dnum Ay 001 memory_core.anum (Ay) 010 memory_core.anum (Ay)+ 011 memory_core.anum -(Ay) 100 memory_core.anum (d16,Ay) 101 memory_core.anum (d8,Ay,Xi) 110 memory_core.anum (xxx).W 111 000 (xxx).L 111 001 #<data> 111 100 (d16,PC) 111 010 (d8,PC,Xi) 111 011 */ /* FUNCTION: Retrives the value in memory based on the supplied Mode and Register ARGS: Size=8,16,32, we are careful with this because an 8 bit retrive for a Dx, or Ax is the LSB, but for memory addressing, it is the 8 bits where the pointer is pointing to. Mode=the mode from the instruction Register=the register from the instruction EAValue=if true, we return the address.. not what is at the address... this means that we can't use Dx,Ay, and some others (because they don't have an EA RETURNS: The value requested, or the EA if EAValue is turned on COMMENTS: */ /* -------------------------------------*/ int Addressing_Print(short Size, char Mode, char Register, char *Str) { unsigned int Result=0; short Scale; struct _InstructionExtensionWord *EWordPtr = (void *)&Result; switch(Mode) { case 0: /* Dy */ sprintf(Str, "D%d", Register); break; case 1: /* Ay */ sprintf(Str, "A%d", Register); break; case 2: /* (Ay) */ sprintf(Str, "(A%d)", Register); break; case 3: /* (Ay)+ */ sprintf(Str, "(A%d)+", Register); break; case 4: /* -(Ay) */ sprintf(Str, "-(A%d)", Register); break; case 5: /* (d16,Ay) */ Memory_RetrWordFromPC(&Result); sprintf(Str, "%hd(A%d)",(short)Result,Register); break; case 6: /* (d8,Ax,Xi) */ Memory_RetrWordFromPC(&Result); if(EWordPtr->Scale == 0) Scale=1; else if(EWordPtr->Scale == 1) Scale=2; else if(EWordPtr->Scale == 2) Scale=4; else Scale=1; sprintf(Str, "%d(A%d,%c%d.L*%d)",EWordPtr->Displacement, Register, EWordPtr->AD ? 'A' : 'D', EWordPtr->Register, Scale); break; case 7: /* Direct modes */ switch(Register) { case 0: /* word addressing */ Memory_RetrWordFromPC(&Result); sprintf(Str, "(0x%04hX.W)", (short)Result); break; case 1: /* long addressing */ Memory_RetrLongWordFromPC(&Result); sprintf(Str, "(0x%08lX.L)", Result); break; case 2: /* (d16,PC) */ Memory_RetrWordFromPC(&Result); sprintf(Str, "%hd(PC)",(short)Result); break; case 3: /* (d8,PC,Xi) */ Memory_RetrWordFromPC(&Result); if(EWordPtr->Scale == 0) Scale=1; else if(EWordPtr->Scale == 1) Scale=2; else if(EWordPtr->Scale == 2) Scale=4; else Scale=1; sprintf(Str, "%d(PC,%c%d.L*%d)",EWordPtr->Displacement, EWordPtr->AD ? 'A' : 'D', EWordPtr->Register, Scale); break; case 4: if(Size==8) { Memory_RetrByteFromPC(&Result); /* if( (char)Result < 0) sprintf(Str, "#%d", (char)Result); else*/ sprintf(Str, "#0x%02lX", Result); } else if(Size==16) { Memory_RetrWordFromPC(&Result); /* if( (short)Result < 0) sprintf(Str, "#%d", (short)Result); else if((short)Result == 0) sprintf(Str, "#0"); else*/ sprintf(Str, "#0x%04lX", Result); } else if(Size==32) { Memory_RetrLongWordFromPC(&Result); /* if( (int)Result < 0) sprintf(Str, "#%ld", (int)Result); else*/ sprintf(Str, "#0x%08lX", Result); } break; default: sprintf(Str, "---"); break; } } return 0; } /* This gets an address, and all useful information about an address from * the PC. Once the address is retrieved, it can be used (multiple times) * to write to, read from, etc. This allows us to only need to access the * PC once during instruction operand fetch. So if the destionation is (say) * an immediate address, we already have it.. we don't need to do any PC * magic to reset it, and re-read the address. I don't know if this is * actally how the Coldfire works (what happens if you write to the address * you're fetching from.. does the board re-fetch the operand, or just use * the value of the address it pulled the source from?) */ /* It also lets us do things like auto increment, and autodecrement.. and * stores the original address in a place where we can use it again */ char EA_GetFromPC(struct _Address *Addr, short Size, char Mode, char Register) { struct _InstructionExtensionWord *EWordPtr = (struct _InstructionExtensionWord *)&Addr->Data; short Scale; Addr->Mode=Mode; Addr->Register=Register; Addr->Data=0; /* This is for storing operands that are in the instruction */ Addr->Address = 0xdeadbeef; Addr->Size=Size; #ifdef MEMORY_STATS /* FIXME: this could be moved to the EA_GetValue, GetEA, and PutValue functions, * it might give a more accurate representation there (some instructions do a direct * read from the PC if they know what they are reading, but usually they go through * the EA_* routines), and would let things be split into reads/writes. */ Stats_Build_EA(Register, Mode); #endif /* MEMORY_STATS */ switch(Mode) { case 0: /* Dy */ return 1; case 1: /* Ay */ return 1; case 2: /* (Ay) */ Addr->Address = memory_core.a[(int)Register]; return 1; case 3: /* (Ay)+ */ Addr->Address = memory_core.a[(int)Register]; memory_core.a[(int)Register]+=Size>>3; return 1; case 4: /* -(Ay) */ memory_core.a[(int)Register]-=Size>>3; Addr->Address = memory_core.a[(int)Register]; return 1; case 5: /* (d16,Ay) */ if(!Memory_RetrWordFromPC(&Addr->Data)) return 0; Addr->Address = memory_core.a[(int)Register]+(short)Addr->Data; return 1; case 6: /* (d8,An,Xi) */ if(!Memory_RetrWordFromPC(&Addr->Data)) return 0; if(EWordPtr->Scale == 0) Scale=1; else if(EWordPtr->Scale == 1) Scale=2; else if(EWordPtr->Scale == 2) Scale=4; else Scale=1; EWordPtr->Displacement, EWordPtr->AD ? "A" : "D", EWordPtr->Register, EWordPtr->AD ? memory_core.a[EWordPtr->Register] : memory_core.d[EWordPtr->Register], Addr->Address = memory_core.a[(int)Register] + EWordPtr->Displacement; /* EWordPtr->AD == 0 for memory_core.dister */ if(EWordPtr->AD==0) Addr->Address += memory_core.d[(int)EWordPtr->Register] * Scale; else Addr->Address += memory_core.a[(int)EWordPtr->Register] * Scale; return 1; case 7: /* Direct modes */ switch(Register) { case 0: /* word addressing */ if(!Memory_RetrWordFromPC(&Addr->Data)) return 0; Addr->Address = Addr->Data; return 1; case 1: /* long addressing */ if (!Memory_RetrLongWordFromPC(&Addr->Data)) return 0; Addr->Address = Addr->Data; return 1; case 2: /* (d16,PC) */ /* This uses the value of the PC as the address of the extenstion word, we are already there */ Addr->Address = memory_core.pc; /* Now alter the PC to get the extension word */ if(!Memory_RetrWordFromPC(&Addr->Data)) return 0; Addr->Address += (short)Addr->Data; return 1; case 3: /* (d8,PC,Xi) */ /* This uses the value of the PC as the address of the extenstion word, we are already there */ Addr->Address = memory_core.pc; /* Now alter the PC to get the extension word */ if(!Memory_RetrWordFromPC(&Addr->Data)) return 0; if(EWordPtr->Scale == 0) Scale=1; else if(EWordPtr->Scale == 1) Scale=2; else if(EWordPtr->Scale == 2) Scale=4; else Scale=1; EWordPtr->Displacement, EWordPtr->AD ? "A" : "D", EWordPtr->Register, EWordPtr->AD ? memory_core.a[EWordPtr->Register] : memory_core.d[EWordPtr->Register], Addr->Address += EWordPtr->Displacement; /* EWordPtr->AD == 0 for memory_core.dister */ if(EWordPtr->AD==0) Addr->Address += memory_core.d[(int)EWordPtr->Register] * Scale; else Addr->Address += memory_core.a[(int)EWordPtr->Register] * Scale; return 1; case 4: if(!Memory_RetrFromPC(&Addr->Data, Size)) return 0; Addr->Address = 0xdeadbeef; if(Size==8) { } else if(Size==16) { } else { } return 1; } /* Should never get here */ break; } return 0; } /* Takes an address, (that we build from EA_GetFromPC), and returns the * value associated with it (with proper masking of bits) * This sign extends the return so it can be used directly for math ops * or for negative compares without worrying about actual size */ char EA_GetValue(unsigned int *Result, struct _Address *Addr) { char ReturnValue = 1; switch(Addr->Mode) { case 0: /* Dy */ *Result = memory_core.d[(int)Addr->Register]; break; case 1: /* Ay */ *Result = memory_core.a[(int)Addr->Register]; break; case 2: /* (Ay) */ case 3: /* (Ay)+ */ case 4: /* -(Ay) */ case 5: /* (d16,Ay) */ case 6: /* (d8,An,Xi) */ ReturnValue = Memory_Retr(Result, Addr->Size,Addr->Address); break; case 7: /* Direct modes */ switch(Addr->Register) { case 0: /* word addressing */ case 1: /* long addressing */ case 2: /* (d16,PC) */ case 3: /* (d8,PC,Xi) */ ReturnValue = Memory_Retr(Result, Addr->Size,Addr->Address); break; case 4: *Result = Addr->Data; break; } break; } /* Now mask it through the size .. eg & 0x000000FF for 8bit, etc. */ if(Addr->Size & 0x0020) return 1; if(Addr->Size & 0x0010) *Result = (short)*Result; else *Result = (char)*Result; return ReturnValue; } /* This is used by instructions that play with effective addresses (EAs) * instead of getting the value at an addrss, we get the actual address */ char EA_GetEA(unsigned int *Result, struct _Address *Addr) { switch(Addr->Mode) { case 0: /* Dy */ case 1: /* Ay */ case 3: /* (Ay)+ */ case 4: /* -(Ay) */ //ERR("Can't get the EA of a register..\n"); return 0; case 2: /* (Ay) */ case 5: /* (d16,Ay) */ case 6: /* (d8,An,Xi) */ *Result = Addr->Address; break; case 7: /* Direct modes */ switch(Addr->Register) { case 0: /* word addressing */ case 1: /* long addressing */ case 2: /* (d16,PC) */ case 3: /* (d8,PC,Xi) */ *Result = Addr->Address; break; case 4: return 0; } break; } return 1; } /* Given a value, and an address, this puts that value */ void EA_PutValue(struct _Address *Addr, unsigned int Value) { /* Value is long, sign extended */ switch(Addr->Mode) { case 0: /* Dy */ /* Coldfire preserves the bits not written to when writing * to a D register */ if(Addr->Size & 0x0020) { memory_core.d[(int)Addr->Register] = Value; return; } else if(Addr->Size & 0x0010) { memory_core.d[(int)Addr->Register] &= 0xFFFF0000; memory_core.d[(int)Addr->Register] |= Value & 0x0000FFFF; return; } else { memory_core.d[(int)Addr->Register] &= 0xFFFFFF00; memory_core.d[(int)Addr->Register] |= Value & 0x000000FF; return; } return; case 1: /* Ay */ /* for both word and long writes to the A register, we * store the long sign extended value, but for byte writes, * we only overwrite the lowest byte. */ if(Addr->Size & 0x0030) { memory_core.a[(int)Addr->Register] = Value; return; /* } else if(Addr->Size & 0x0010) { memory_core.a[(int)Addr->Register] &= 0xFFFF0000; memory_core.a[(int)Addr->Register] |= Value & 0x0000FFFF; return;*/ } else { memory_core.a[(int)Addr->Register] &= 0xFFFFFF00; memory_core.a[(int)Addr->Register] |= Value & 0x000000FF; return; } return; case 2: /* (Ay) */ case 3: /* (Ay)+ */ case 4: /* -(Ay) */ case 5: /* (d16,Ay) */ case 6: /* (d8,An,Xi) */ if(Addr->Size & 0x0020); else if(Addr->Size & 0x0010) Value = (unsigned short)Value; else Value = (unsigned char)Value; Memory_Stor(Addr->Size,Addr->Address,Value); return; case 7: /* Direct modes */ switch(Addr->Register) { case 0: /* word addressing */ case 1: /* long addressing */ if(Addr->Size & 0x0020); else if(Addr->Size & 0x0010) Value = (unsigned short)Value; else Value = (unsigned char)Value; Memory_Stor(Addr->Size,Addr->Address,Value); return; case 2: /* (d16,PC) */ case 3: /* (d8,PC,Xi) */ case 4: //ERR("Can't write to the PC, go away.\n"); return; } /* Shouldn't get here */ break; } } void Stack_Push(short Size, unsigned int Value) { struct _Address Dest; EA_GetFromPC(&Dest, Size, 4, 7); EA_PutValue(&Dest, Value); } unsigned int Stack_Pop(short Size) { struct _Address Dest; unsigned int Value; EA_GetFromPC(&Dest, Size, 3, 7); EA_GetValue(&Value, &Dest); return Value; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/addressing.h��������������������������������������������������0000644�0001750�0000144�00000001733�10541455476�020545� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ struct _Address { short Size; char Mode; char Register; unsigned int Address; unsigned int Data; }; /*ng Addressing_Retr(short Size, char Mode, char Register, char EAValue); void Addressing_Stor(short Size, char Mode, char Register, long Value);*/ int Addressing_Print(short Size, char Mode, char Register, char *Str); char EA_GetFromPC(struct _Address *Addr, short Size, char Mode, char Register); char EA_GetValue(unsigned int *Result, struct _Address *Addr); char EA_GetEA(unsigned int *Result, struct _Address *Addr); /*long EA_GetAddress(struct _Address *Addr);*/ void EA_PutValue(struct _Address *Addr, unsigned int Value); void Stack_Push(short Size, unsigned int Value); unsigned int Stack_Pop(short Size); �������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/ram.c���������������������������������������������������������0000644�0001750�0000144�00000012443�11006120657�017157� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2002, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ /* RAM and ROM memory modules */ #include <stdio.h> #include <stdlib.h> #include <string.h> /*#define SKYEYE_DBGR_OFF*/ #include "coldfire.h" SKYEYE_DBGR_DEFAULT_CHANNEL(ram); void ram_init(void); static void ram_setup(struct _memory_segment *s); static void rom_setup(struct _memory_segment *s); static void ram_fini(struct _memory_segment *s); static char ram_read(struct _memory_segment *s, unsigned int *result, short size, unsigned int offset); static char ram_write(struct _memory_segment *s, short size, unsigned int offset, unsigned int value); static char rom_write(struct _memory_segment *s, short size, unsigned int offset, unsigned int value); static void rom_reset(struct _memory_segment *s); struct _mem_data { char *begin; char *end; int len; }; void ram_init(void) { memory_module_register("ram", &ram_setup); memory_module_register("rom", &rom_setup); } static void ram_setup(struct _memory_segment *s) { int len; struct _mem_data *mem; mem = malloc(sizeof(struct _mem_data)); /* Get the length, which is actually the mask + 1 */ len = (~s->mask) + 1; SKYEYE_DBG("len=%x\n", len); /* +3 for those long reads at EOM */ mem->begin=malloc((size_t)(len+3)); mem->end = mem->begin + len /* +3 -3 */; SKYEYE_DBG("end=%x\n", mem->end); mem->len = len; s->data = mem; /* Now set the functions to use */ s->fini = &ram_fini; s->read = &ram_read; s->write = &ram_write; s->reset = NULL; s->update = NULL; } static void rom_setup(struct _memory_segment *s) { ram_setup(s); s->write = &rom_write; s->reset = &rom_reset; } static void ram_fini(struct _memory_segment *s) { struct _mem_data *mem = (struct _mem_data *)s->data; free(mem->begin); free(s->name); free(s->data); } static void rom_reset(struct _memory_segment *s) { struct _mem_data *mem = (struct _mem_data *)s->data; int x; /* Map out the rom in bigendian */ SKYEYE_DBG("ROM setup with code_length=%d\n", s->code_len); for(x=0;x<s->code_len;x++) { SKYEYE_DBG(" code[%d] = 0x%02x\n", x, s->code[x]); } #ifdef UNALIGNED_ACCESS #ifndef WORDS_BIGENDIAN /* Put them in backards, starting at ram->end+3 */ for(x=0;x<s->code_len; x++) mem->end[3 - x] = s->code[x]; #else memcpy(mem->begin, s->code, s->code_len); #endif #else /* Endianness doesn't matter if we can't do unaligned * reads/writes. We just convert everything to big endian */ memcpy(mem->begin, s->code, s->code_len); #endif } static char ram_read(struct _memory_segment *s, unsigned int *result, short size, unsigned int offset) { struct _mem_data *mem = (struct _mem_data *)s->data; #ifdef UNALIGNED_ACCESS unsigned int *ptr; SKYEYE_DBG("size=%d, offset=0x%08lx\n", size, offset); #ifndef WORDS_BIGENDIAN ptr = (unsigned int *)(mem->end - offset); #else ptr = (unsigned int *)(mem->begin + offset); #endif *result = (*ptr) >> (32 - size); #else unsigned char *ptr = (unsigned char *)(mem->begin + offset); SKYEYE_DBG("mem->begin=0x%08lx size=%d, offset=0x%08lx, ptr=%p\n", mem->begin, size, offset, ptr); if(size == 32) *result = (*ptr<<24) | (*(ptr+1)<<16) | (*(ptr+2)<<8) | *(ptr+3); else if (size == 16) *result = (*ptr<< 8) | *(ptr+1); else *result = *ptr; #endif SKYEYE_DBG("result=0x%08lx\n", *result); return 1; } static char ram_write(struct _memory_segment *s, short size, unsigned int offset, unsigned int value) { #ifdef UNALIGNED_ACCESS void *ptr; unsigned int templ; #else unsigned char *ptr; #endif struct _mem_data *mem = (struct _mem_data *)s->data; SKYEYE_DBG("s=%p\n", s); SKYEYE_DBG("size=%d, offset=0x%08lx, value=0x%08lx\n", size, offset, value); /* Normal memory access */ #ifdef UNALIGNED_ACCESS #ifndef WORDS_BIGENDIAN ptr = (void *)(mem->end - offset); #else ptr = (void *)(mem->begin + offset); #endif SKYEYE_DBG("s=%p\n", s); SKYEYE_DBG("ptr=%p\n", ptr); SKYEYE_DBG("mem->end=%p\n", mem->end); if(size == 32) { *(unsigned int *)ptr = value; return 1; } else if (size == 0x0010) { /* *(unsigned short *)ptr = (unsigned short)(value & 0x0000FFFF);*/ memcpy(&templ, ptr, 4); templ &= 0x0000FFFF; templ |= (value << 16); memcpy(ptr, &templ, 4); return 1; } /* Else, 8 bits */ else { /* *(unsigned char *)ptr = (unsigned char)(value & 0x000000FF);*/ memcpy(&templ, ptr, 4); templ &= 0x00FFFFFF; templ |= (value << 24); memcpy(ptr, &templ, 4); return 1; } #else ptr = (unsigned char *)(mem->begin + offset); SKYEYE_DBG("s=%p\n", s); SKYEYE_DBG("ptr=%p\n", ptr); SKYEYE_DBG("mem->end=%p\n", mem->end); if(size == 32) { *ptr = (value >> 24) & 0xFF; *(ptr+1)= (value >> 16) & 0xFF; *(ptr+2)= (value >> 8) & 0xFF; *(ptr+3)= (value ) & 0xFF; return 1; } else if (size == 16) { *ptr = (value >> 8) & 0xFF; *(ptr+1)= (value ) & 0xFF; return 1; } else { *ptr = (value ) & 0xFF; return 1; } #endif /* memcpy(ptr, &templ, 4);*/ return 0; } static char rom_write(struct _memory_segment *s, short size, unsigned int offset, unsigned int value) { SKYEYE_ERR("size=%d, offset=0x%08lx, value=0x%08lx\n", size, offset, value); SKYEYE_ERR("Cannot write to ROM, go away.\n"); return 1; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/board.c�������������������������������������������������������0000644�0001750�0000144�00000004331�10541455476�017501� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <stdio.h> #include <string.h> #include <stdlib.h> #include "coldfire.h" /* Arnewsh memory map */ /* $00000000 - $01FFFFFF DRAM * $10000000 - $100003FF Internal module registers * $20000000 - $200001FF Internal SRAM * $30000000 - $300FFFFF 1Meg space for MC68HC901 * $40000000 - $400FFFFF 1Meg ISA bus area * $FFE00000 - $FFE3FFFF 256K flash rom */ static const char *arnewsh_config_data = "board \"Arnewsh\"\n" "cpu \"5206\"\n" "\n" "; DRAM is most likely to be accessed\n" "ram name=\"dram\", base=0x0, len=0x00400000\n" "\n" "; Default core register values\n" "reg VBR=0x0\n" "reg MBAR=0x10000000\n" "reg RAMBAR=0x20000000\n" "reg ROMBAR=0xFFE00000\n" "reg PC=0xFFE00000\n" "reg SP=0x00400000\n" "reg SR=0x2000\n" "\n" "; Then the SIM, the sim_init initializes the entire sim region, \n" "; so the timer and uart need to go first else we'll never send \n" "; read/writes into them \n" "; We also don't need the lengths, the modules know how long they are\n" "timer_5206 name=\"timer1\", base=MBAR+0x100, int=9\n" "timer_5206 name=\"timer2\", base=MBAR+0x120, int=10\n" "uart_5206 name=\"uart1\", base=MBAR+0x140, int=12\n" "uart_5206 name=\"uart2\", base=MBAR+0x180, int=13, code=00\n" "sim_5206 name=\"sim\", base=MBAR+0x0\n" "\n" "; Least likely to be accessed\n" "dummy name=ne2000, base=0x40000300, len=0x0100\n" "dummy name=isa, base=0x40000000, len=0x00100000\n" "rom name=rom, base=ROMBAR+0x0, len=0x00040000, \\\n" " code=70004e4f\n" "ram name=sram, base=RAMBAR+0x0, len=0x00000100\n"; struct _board_data board_data; struct _board_data *board_get_data(void) { return &board_data; } void board_init(void) { /* Setup global board data */ memset(&board_data, 0, sizeof(struct _board_data)); /* Set some defaults */ board_data.clock_speed = 25000000; board_data.cycle_count = 0; board_data.use_timer_hack = 0; board_data.trace_run = 0; board_data.cpu = CF_NULL; } void board_reset(void) { board_data.cycle_count = 0; memory_reset(); } void board_fini(void) { } void board_do_config(char *config_data) { char *ptr = config_data; char *next_ptr, *tmp_ptr; int argc; char *argv[3]; int num_memory_segments=0; /* printf("[%s]\n", config_data);*/ printf("\n"); } void board_setup(char *file) { } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/handlers.c����������������������������������������������������0000644�0001750�0000144�00000010233�11006120657�020173� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include <stdio.h> #include <stdarg.h> #include "coldfire.h" SKYEYE_DBGR_DEFAULT_CHANNEL(handlers); void SR_Set(short Instr, int Source, int Destination, int Result) { char Sm = (Source >= 0) ? 0 : 1; char Dm = (Destination >= 0) ? 0 : 1; char Rm = (Result >= 0) ? 0 : 1; short BackupSR = memory_core.sr; SKYEYE_DBG("Setting Source=0x%08lx, Destination=0x%08lx, Result=0x%08lx\n", Source, Destination, Result); SKYEYE_DBG("Sm=%d, Dm=%d, Rm=%d\n", Sm,Dm,Rm); /* Clear out the XNZVC */ memory_core.sr &= 0xFFE0; switch(Instr) { case I_ADDX: /* Z - cleared if result is non-zero, unchanged otherwise */ case I_ADD: case I_ADDI: case I_ADDQ: /* Set the status register */ /* X - Set to value of carry bit N - Set if result is -ve, cleared otherwise Z - Set if result is zero, cleared otherwise V - Set if an overflow occurs, cleared otherwise C - Set if a carry is generated, cleared otherwise */ if(Rm) memory_core.sr |= SR_N; if(Instr==I_ADDX) { if(Result) /* SR_Z will already be cleared */; else /* Restore the old one */ memory_core.sr |= (BackupSR & SR_Z); } else { if(Result==0) memory_core.sr |= SR_Z; } if((Sm && Dm && !Rm) || (!Sm && !Dm && Rm) ) memory_core.sr |= SR_V; if((Sm && Dm) || (!Rm && Dm) || (Sm && !Rm) ) { memory_core.sr |= SR_C; memory_core.sr |= SR_X; } break; case I_SUBX: /* Z - cleared if result is non-zero, unchanged otherwise */ case I_SUB: case I_SUBI: case I_SUBQ: /* Set the status register */ /* X - Set to value of carry bit N - Set if result is -ve, cleared otherwise Z - Set if result is zero, cleared otherwise V - Set if an overflow occurs, cleared otherwise C - Set if a borrow occurs, cleared otherwise */ if(Rm) memory_core.sr |= SR_N; if(Instr==I_SUBX) { if(Result) /* SR_Z will already be cleared */; else /* Restore the old one */ memory_core.sr |= (BackupSR & SR_Z); } else { if(Result==0) memory_core.sr |= SR_Z; } if((!Sm && Dm && !Rm) || (Sm && !Dm && Rm) ) memory_core.sr |= SR_V; if((Sm && !Dm) || (Rm && !Dm) || (Sm && Rm) ) { memory_core.sr |= SR_C; memory_core.sr |= SR_X; } break; case I_CMP: case I_CMPA: case I_CMPI: /* Set the status register * X - Not affected * N - Set if result is -ve, cleared otherwise * Z - Set if result is zero, cleared otherwise * V - Set if an overflow occurs, cleared otherwise * C - Set if a borrow occurs, cleared otherwise */ if(Rm) memory_core.sr |= SR_N; if(Result==0) memory_core.sr |= SR_Z; if((!Sm && Dm && !Rm) || (Sm && !Dm && Rm) ) memory_core.sr |= SR_V; if((Sm && !Dm) || (Rm && !Dm) || (Sm && Rm) ) memory_core.sr |= SR_C; /* Restore X */ memory_core.sr |= (BackupSR & SR_X); break; case I_NEG: /* X - Set to value of carry bit N - Set if result is -ve, cleared otherwise Z - Set if result is zero, cleared otherwise V - Set if an overflow occurs, cleared otherwise C - Cleared if the result is zero, set otherwise */ if(Rm) memory_core.sr |= SR_N; if(Result==0) memory_core.sr |= SR_Z; if(Dm && Rm) memory_core.sr |= SR_V; if(Dm || Rm) memory_core.sr |= (SR_C | SR_X); break; case I_NEGX: /* X - Set to value of carry bit N - Set if result is -ve, cleared otherwise Z - Cleared if the result is non-zero, unchanged otherwise V - Set if an overflow occurs, cleared otherwise C - Cleared if the result is zero, set otherwise */ if(Rm) memory_core.sr |= SR_N; if(Result==0) memory_core.sr |= (BackupSR & SR_Z); if(Dm && Rm) memory_core.sr |= SR_V; if(Dm || Rm) memory_core.sr |= (SR_C | SR_X); break; default: SKYEYE_ERR("Called with unknown instruction %d\n", Instr); break; } SKYEYE_DBG("X:%d, Neg:%d, Zero:%d, Overflow:%d, Carry:%d\n", (memory_core.sr&SR_X) >> 4,(memory_core.sr&SR_N) >> 3,(memory_core.sr&SR_Z) >> 2,(memory_core.sr&SR_V) >> 1, (memory_core.sr&SR_C)); return; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/coldfire.h����������������������������������������������������0000644�0001750�0000144�00000014104�11006120657�020170� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #ifndef __COLDFIRE_H__ #define __COLDFIRE_H__ #include <stdio.h> #include <string.h> #include "skyeye.h" struct _Instruction { void (*FunctionPtr)(void); unsigned short Code; unsigned short Mask; int (*DIFunctionPtr)(char *Instruction, char *Arg1, char *Arg2); }; /* This is ALWAYS cast into a longword, so we need to pad it to a longword */ struct _InstructionExtensionWord { #ifndef WORDS_BIGENDIAN signed Displacement:8; unsigned EV:1; unsigned Scale:2; unsigned WL:1; unsigned Register:3; unsigned AD:1; unsigned pad:16; #else unsigned pad:16; unsigned AD:1; unsigned Register:3; unsigned WL:1; unsigned Scale:2; unsigned EV:1; signed Displacement:8; #endif }; enum { I_ADD, I_ADDA, I_ADDI, I_ADDQ, I_ADDX, I_AND, I_ANDI, I_ASL, I_ASR, I_BCC, I_BCHG, I_BCLR, I_BRA, I_BSET, I_BSR, I_BTST, I_CLR, I_CMP, I_CMPA, I_CMPI, I_DIVS, I_DIVL, I_DIVU, I_DIVUL, I_EOR, I_EORI, I_EXT, I_JMP, I_JSR, I_LEA, I_LINK, I_LSR, I_LSL, I_MOVE, I_MOVEC, I_MOVEA, I_MOVEM, I_MOVEQ, I_MOVETOSR, I_MULS, I_MULU, I_NEG, I_NEGX, I_NOP, I_NOT, I_OR, I_ORI, I_RTE, I_RTS, I_SCC, I_SUB, I_SUBA, I_SUBI, I_SUBQ, I_SUBX, I_SWAP, I_TRAP, I_TRAPF, I_TST, I_UNLK, I_LAST }; enum _coldfire_cpu_id { CF_NULL, CF_5206, CF_5206e, CF_5276, CF_5307, CF_5407, CF_LAST }; #define INSTRUCTION_(I,A) \ typedef union _##I##_instr { \ struct _##I##_bits { \ A; \ } Bits; \ unsigned int Code; \ } I##_Instr #ifndef WORDS_BIGENDIAN #define INSTRUCTION_1ARG(I,A1,S1) \ INSTRUCTION_(I, A1:S1) #define INSTRUCTION_2ARGS(I,A1,S1,A2,S2) \ INSTRUCTION_(I, A2:S2; A1:S1) #define INSTRUCTION_3ARGS(I,A1,S1,A2,S2,A3,S3) \ INSTRUCTION_(I, A3:S3; A2:S2; A1:S1) #define INSTRUCTION_4ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4) \ INSTRUCTION_(I, A4:S4; A3:S3; A2:S2; A1:S1) #define INSTRUCTION_5ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4,A5,S5) \ INSTRUCTION_(I, A5:S5; A4:S4; A3:S3; A2:S2; A1:S1) #define INSTRUCTION_6ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4,A5,S5,A6,S6) \ INSTRUCTION_(I, A6:S6; A5:S5; A4:S4; A3:S3; A2:S2; A1:S1) #define INSTRUCTION_7ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4,A5,S5,A6,S6,A7,S7) \ INSTRUCTION_(I, A7:S7; A6:S6; A5:S5; A4:S4; A3:S3; A2:S2; A1:S1) #else #define INSTRUCTION_1ARG(I,A1,S1) \ INSTRUCTION_(I, unsigned pad:(32-S1); \ A1:S1) #define INSTRUCTION_2ARGS(I,A1,S1,A2,S2) \ INSTRUCTION_(I, unsigned pad:(32-S1-S2); \ A1:S1; A2:S2) #define INSTRUCTION_3ARGS(I,A1,S1,A2,S2,A3,S3) \ INSTRUCTION_(I, unsigned pad:(32-S1-S2-S3); \ A1:S1; A2:S2; A3:S3) #define INSTRUCTION_4ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4) \ INSTRUCTION_(I, unsigned pad:(32-S1-S2-S3-S4); \ A1:S1; A2:S2; A3:S3; A4:S4) #define INSTRUCTION_5ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4,A5,S5); \ INSTRUCTION_(I, unsigned pad:(32-S1-S2-S3-S4-S5); \ A1:S1; A2:S2; A3:S3; A4:S4; A5:S5) #define INSTRUCTION_6ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4,A5,S5,A6,S6)\ INSTRUCTION_(I, unsigned pad:(32-S1-S2-S3-S4-S5-S6); \ A1:S1; A2:S2; A3:S3; A4:S4; A5:S5; A6:S6) #define INSTRUCTION_7ARGS(I,A1,S1,A2,S2,A3,S3,A4,S4,A5,S5,A6,S6,A7,S7) \ INSTRUCTION_(I, unsigned pad:(32-S1-S2-S3-S4-S5-S6-S7); \ A1:S1; A2:S2; A3:S3; A4:S4; A5:S5; A6:S6; A7:S7) #endif #include "memory.h" #include "addressing.h" //#include "monitor/monitor.h" //#include "i_5206/i_5206.h" //#include "i_5206e/i_5206e.h" //#include "i_5307/i_5307.h" //#include "peripherals/peripherals.h" /* board.c -- definitions of various eval board layouts */ struct _board_data { char *cpu_id; unsigned int clock_speed; unsigned int cycle_count; unsigned int total_cycle_count; char use_timer_hack; char trace_run; enum _coldfire_cpu_id cpu; }; void board_init(void); void board_reset(void); void board_fini(void); void board_setup(char *file); struct _board_data *board_get_data(void); /* cycle.c */ void cycle(unsigned int number); int cycle_EA(short reg, short mode); /* exception.c -- exception generators */ int exception_do_raw_exception(short vector); int exception_do_exception(short vector); void exception_restore_from_stack_frame(void); void exception_push_stack_frame(short vector); void exception_post(unsigned int interrupt_level, unsigned int (*func)(unsigned int interrupt_level) ); void exception_withdraw(unsigned int interrupt_level); void exception_check_and_handle(void); /* handlers.c -- misc functions */ void SR_Set(short Instr, int Source, int Destination, int Result); /* i.c -- instructions */ void Instruction_Init(void); void instruction_register(unsigned short code, unsigned short mask, void (*execute)(void), int (*disassemble)(char *, char *, char *)); void Instruction_DeInit(void); struct _Instruction *Instruction_FindInstruction(unsigned short Instr); void instruction_register_instructions(void); /* misc.c -- Misc functions */ int arg_split(char **argv, char *buffer, int max_args); int arg_split_chars(char **argv, char *buffer, int max_args, char *split); /* network.c -- Network functions */ int network_setup_on_port(int *fd, unsigned short port); int network_check_accept(int *fd); /* run.c -- Running the core */ extern char Run_Exit; void Run(void); /* sim.c -- System Integration Module */ struct _sim_register { char *name; int offset; char width; char read; char write; int resetvalue; char *description; }; struct _sim { /* These are for peripherals to talk to the sim */ void (*interrupt_assert)(short number, short vector); void (*interrupt_withdraw)(short number); /* These are for the monitor to query SIM registers */ struct _sim_register *(*register_lookup_by_offset)(int offset); struct _sim_register *(*register_lookup_by_name)(char *name); }; void sim_register(struct _sim *sim_data); extern struct _sim *sim; /* #define TRACE(x,y,z) #define TRACE(x,y) #define TRACE(x) */ /* INSTRUCTION TIMING is firewalled inside profile.h */ //#include "profile.h" /* MEMORY_STATS is firewalled inside stats.h */ //#include "stats.h" #endif ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/Makefile������������������������������������������������������0000644�0001750�0000144�00000001256�10600011124�017657� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������CROSS_COMPILE ?= EXTRA_CFLAGS ?= CC = $(CROSS_COMPILE)gcc -g CFLAGS := $(CFLAGS) $(EXTRA_CFLAGS) coldfire:memory.o addressing.o i.o cycle.o handlers.o exception.o ../tracer/tracer.o board.o ram.o memory.o:memory.c $(CC) $(CFLAGS) -c -I../tracer memory.c addressing.o:addressing.c $(CC) $(CFLAGS) -c -I../tracer addressing.c i.o:i.c $(CC) $(CFLAGS) -c -I../tracer i.c cycle.o:cycle.c $(CC) $(CFLAGS) -c -I../tracer cycle.c handlers.o:handlers.c $(CC) $(CFLAGS) -c -I../tracer handlers.c exception.o:exception.c $(CC) $(CFLAGS) -c -I../tracer exception.c board.o:board.c $(CC) $(CFLAGS) -c -I../tracer board.c ram.o:ram.c $(CC) $(CFLAGS) -c -I../tracer ram.c clean: rm -f *.o ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/i.c�����������������������������������������������������������0000644�0001750�0000144�00000013302�11006536574�016634� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #include <stdlib.h> #include "coldfire.h" SKYEYE_DBGR_DEFAULT_CHANNEL(i); #define MALLOC_STEP 16 struct _Instruction *Instruction = NULL; short InstructionCount=0; struct _Instruction **instruction_cache = NULL; void Instruction_Init(void) { SKYEYE_DBG("Initializing...\n"); /* Ensure sanity */ Instruction = NULL; InstructionCount=0; instruction_cache = malloc(0x10000 * sizeof(void *)); if(!instruction_cache) printf("Could not allocate instruction cache\n"); SKYEYE_DBG("Done.\n"); } /* This is for sorting */ static int Instruction_CompareFunction(const void *A, const void *B) { /* Biggest mask first, this sorts backwards */ /* printf("Comparing %p and %p. Mask=%x %x\n", A, B, IA->Mask, IB->Mask);*/ return ( ((struct _Instruction *)B)->Mask - ((struct _Instruction *)A)->Mask ); } void instruction_register(unsigned short code, unsigned short mask, void (*execute)(void), int (*disassemble)(char *, char *, char *)) { struct _Instruction *InstrPtr; /* Check if any reallocating is necessary */ SKYEYE_DBG("Registering Code=0x%04hx Mask=0x%04hx\n", code, mask); if((InstructionCount % MALLOC_STEP)==0) { SKYEYE_DBG("Reallocing to %d bytes\n",(InstructionCount + MALLOC_STEP) * sizeof(struct _Instruction)); Instruction = realloc(Instruction, (InstructionCount + MALLOC_STEP) * sizeof(struct _Instruction)); } /* Add this instruction */ InstrPtr = &Instruction[InstructionCount]; InstrPtr->Code = code; InstrPtr->Mask = mask; InstrPtr->FunctionPtr = (void (*)(void))execute; InstrPtr->DIFunctionPtr = (int (*)(char *Instruction, char *Arg1, char *Arg2))disassemble; InstructionCount++; qsort(Instruction, InstructionCount, sizeof(struct _Instruction), &Instruction_CompareFunction); SKYEYE_DBG("Done\n"); } void Instruction_DeInit(void) { if(instruction_cache) free(instruction_cache); if(Instruction) free(Instruction); } /* Returns a pointer to the instruction that matches Instr * (Finds by matching Code and Mask) */ struct _Instruction *Instruction_LookupInstruction(unsigned short Instr) { int x; for(x=0;x<InstructionCount;x++) { if((Instr & Instruction[x].Mask) == Instruction[x].Code) { /* Return the instruction */ return &Instruction[x]; } } /* We should never get here.. the DC.W instruction, with * mask 0xFFFF will pick up all instructions */ //SKYEYE_ERR("Unknown instruction \n"); return NULL; } struct _Instruction *Instruction_FindInstruction(unsigned short Instr) { /* O(1) instruction lookup, instead of O(n) */ return instruction_cache[Instr]; /* O(n) instruction lookup, yuck. * return Instruction_LookupInstruction(Instr);*/ } void instruction_build_cache(void) { unsigned int x; if(!instruction_cache) { printf("Skipping instruction cache build, cache not allocated\n"); return; } printf("\tbuilding instruction cache... " ); fflush(stdout); for(x=0;x<0x10000;x++) { //printf("x=0x%x\n", x); instruction_cache[x] = Instruction_LookupInstruction(x); //Instruction_LookupInstruction(x); } printf("done.\n"); } void instruction_register_instructions(void) { int x=0; struct _board_data *bd = board_get_data(); switch(bd->cpu) { case CF_5206: printf(" (Motorola Coldfire 5206)\n"); printf("\tunimplemented instructions: CPUSHL PULSE WDDATA WDEBUG\n"); break; case CF_5206e: printf(" (Motorola Coldfire 5206e)\n"); printf("\tunimplemented instructions: CPUSHL PULSE WDDATA WDEBUG\n"); break; case CF_5307: printf(" (Motorola Coldfire 5307)\n"); printf("\tunimplemented instructions: CPUSHL PULSE WDDATA WDEBUG\n"); break; default: printf("\tUnknown processor type '%d'\n", bd->cpu); break; } /* Register intstructions */ x+=add_5206_register(); x+=adda_5206_register(); x+=addi_5206_register(); x+=addq_5206_register(); x+=addx_5206_register(); x+=and_5206_register(); x+=andi_5206_register(); x+=asx_5206_register(); x+=bcc_5206_register(); x+=btst_5206_register(); x+=clr_5206_register(); x+=cmp_5206_register(); x+=cmpa_5206_register(); x+=cmpi_5206_register(); x+=dc_5206_register(); x+=eor_5206_register(); x+=eori_5206_register(); x+=ext_5206_register(); x+=halt_5206_register(); x+=illegal_5206_register(); x+=jmp_5206_register(); x+=jsr_5206_register(); x+=lea_5206_register(); x+=link_5206_register(); x+=lsx_5206_register(); x+=move_5206_register(); x+=movec_5206_register(); x+=movem_5206_register(); x+=moveq_5206_register(); x+=movexr_5206_register(); x+=mulu_l_5206_register(); x+=mul_w_5206_register(); x+=neg_5206_register(); x+=negx_5206_register(); x+=nop_5206_register(); x+=not_5206_register(); x+=or_5206_register(); x+=ori_5206_register(); x+=pea_5206_register(); x+=rte_5206_register(); x+=rts_5206_register(); x+=scc_5206_register(); x+=stop_5206_register(); x+=sub_5206_register(); x+=suba_5206_register(); x+=subi_5206_register(); x+=subq_5206_register(); x+=subx_5206_register(); x+=swap_5206_register(); x+=trap_5206_register(); x+=trapf_5206_register(); x+=tst_5206_register(); x+=unlk_5206_register(); x+=div_5206e_register(); //if(bd->cpu >= CF_5206e) x+= div_5206e_register(); printf("\t%d instructions registered\n", x); if(x==0) { /* This could get interesting */ SKYEYE_ERR("No registered instructions, hmmm, something is wrong\n"); } instruction_build_cache(); /* for(x=0;x<InstructionCount;x++) { printf("Instr Code=0x%04x, Mask=0x%04x, Code&Mask=0x%04x\n", Instruction[x].Code, Instruction[x].Mask, Instruction[x].Code & Instruction[x].Mask) ; } */ } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/cf_arch_interface.c�������������������������������������������0000644�0001750�0000144�00000013301�11006120657�021777� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* cf_arch_interface.c - interface between simulation of coldfire to common utility Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifdef HAVE_UNISTD_H #include <unistd.h> #endif #include <stdio.h> #include <stdlib.h> #include <signal.h> #ifdef HAVE_LIBREADLINE #include <readline/readline.h> #endif #include "coldfire.h" #include "skyeye_config.h" char Run_Exit = 0; SKYEYE_DBGR_DEFAULT_CHANNEL(run); static int stop_now = 0; void coldfire_init_state(){ static int done = 0; if(!done){ done = 1; Memory_Init(); Instruction_Init(); instruction_register_instructions(); memory_module_setup_segment("ram",0,0x0,32*1024*1024); /* SRAM for 5272 */ memory_module_setup_segment("ram",0, 0x20000000, 4096); /* set supervisor mode */ SRBits->S = 1; memory_core.mbar = 0x10000000; memory_core.mbar2 = 0x80000000; memory_core.mbar_size = 0x1024; memory_core.mbar2_size = 0x1024; /*mach init */ skyeye_config.mach->mach_init (&memory_core, skyeye_config.mach); } } void coldfire_reset_state(){ } extern void mcf5249_io_do_cycle(); /* Execute a single instruction. */ void coldfire_step_once () { unsigned int Instr; struct _Instruction *InstructionPtr; #ifdef INSTRUCTION_PROFILE unsigned long long LowTime=0, HighTime=0; char Buffer[16]; #endif //while(!Run_Exit) { if(1){ SKYEYE_DBG("New cycle, PC=0x%08lx, SP=0x%08lx\n", memory_core.pc, memory_core.a[7]); /* printf("New cycle, PC=0x%08lx, SP=0x%08lx\n", memory_core.pc, memory_core.a[7]); */ /* Check for any pending exceptions */ exception_check_and_handle(); /* As we're coming back from an interrupt, check for exit */ //if(Run_Exit) break; /* Save the PC for the beginning of this instruction * This is useful for exceptions that reset the PC */ memory_core.pc_instruction_begin = memory_core.pc; /* Before we execute this instruction, catch a bad PC counter */ /* Get the instruction from memory */ if(!Memory_RetrWord(&Instr, memory_core.pc)) //continue; ; /* Look it up */ InstructionPtr = Instruction_FindInstruction(Instr); if(InstructionPtr==NULL) { //exception_do_exception(4); //continue; } else { /* Run the instruction */ (*InstructionPtr->FunctionPtr)(); } /* Now update anything that could cause an interrupt, so we * can catch it in the next cycle */ /* Call this, which will call an update * for things like the UARTs and Timers */ skyeye_config.mach->mach_io_do_cycle (&memory_core); } } static void coldfire_set_pc(WORD addr){ memory_core.pc = addr; } static WORD coldfire_get_pc(){ return (WORD)memory_core.pc; } //chy 2006-04-14 maybe changed in the future !!!??? static int coldfire_ICE_write_byte (WORD addr, uint8_t v) { Memory_StorByte(addr,v); return 0; } static int coldfire_ICE_read_byte(WORD addr, uint8_t *pv){ unsigned int v; int res; res = Memory_RetrByte(&v, addr); if (res == 1){ //success *pv=(unsigned char)v; return 0; //fault=0 }else{ return 1;//fault=1 } } static int coldfire_parse_cpu (cpu_config_t * cpu, const char *param[]) { } extern void mcf5249_mach_init(void * state, machine_config_t * mach); extern void mcf5272_mach_init(void * state, machine_config_t * mach); static machine_config_t coldfire_machines[] = { {"mcf5249", mcf5249_mach_init, NULL, NULL, NULL}, {"mcf5272", mcf5272_mach_init, NULL, NULL, NULL}, }; static int coldfire_parse_mach (machine_config_t * cpu, const char *params[]) { int i; for (i = 0; i < (sizeof (coldfire_machines) / sizeof (machine_config_t)); i++) { if (!strncmp (params[0], coldfire_machines[i].machine_name, MAX_PARAM_NAME)) { skyeye_config.mach = &coldfire_machines[i]; SKYEYE_INFO ("mach info: name %s, mach_init addr %p\n", skyeye_config.mach->machine_name, skyeye_config.mach->mach_init); return 0; } } SKYEYE_ERR ("Error: Unkonw mach name \"%s\"\n", params[0]); return -1; } static int coldfire_parse_mem(int num_params, const char *params[]){ //memory_module_setup_segment("ram",0,0x0,0x400000); } void init_coldfire_arch(){ static arch_config_t coldfire_arch; coldfire_arch.arch_name = "coldfire"; //coldfire_arch.pc = 0; coldfire_arch.init = coldfire_init_state; coldfire_arch.reset = coldfire_reset_state; coldfire_arch.set_pc = coldfire_set_pc; coldfire_arch.get_pc = coldfire_get_pc; coldfire_arch.step_once = coldfire_step_once; coldfire_arch.ICE_write_byte = coldfire_ICE_write_byte; coldfire_arch.ICE_read_byte = coldfire_ICE_read_byte; coldfire_arch.parse_cpu = coldfire_parse_cpu; coldfire_arch.parse_mach = coldfire_parse_mach; coldfire_arch.parse_mem = NULL; register_arch (&coldfire_arch); } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/memory.h������������������������������������������������������0000644�0001750�0000144�00000007123�10576443014�017722� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2000, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ #ifndef MEMORY_H #define MEMORY_H /* Memory definitions */ struct _memory_core { unsigned int pc; unsigned int pc_instruction_begin; unsigned int sr; unsigned int mbar; unsigned int mbar_size; unsigned int mbar2; unsigned int mbar2_size; unsigned int rambar; unsigned int rambar1; unsigned int rombar; unsigned int vbr; unsigned int cacr; unsigned int d[8]; unsigned int a[8]; char (*mbar_write)(short size, int offset, unsigned int value); char (*mbar_read)(unsigned int * result, short size, int offset); char (*mbar2_write)(short size, int offset, unsigned int value); char (*mbar2_read)(unsigned int * result, short size, int offset); }; /* Actually declared in memory.c */ extern struct _memory_core memory_core; struct _SR { #ifndef WORDS_BIGENDIAN unsigned C:1; unsigned V:1; unsigned Z:1; unsigned N:1; unsigned X:1; unsigned Unused:3; unsigned InterruptPriorityMask:3; unsigned Unused2:1; unsigned M:1; unsigned S:1; unsigned Unused3:1; unsigned T:1; unsigned pad:16; #else unsigned pad:16; unsigned T:1; unsigned Unused3:1; unsigned S:1; unsigned M:1; unsigned Unused2:1; unsigned InterruptPriorityMask:3; unsigned Unused:3; unsigned X:1; unsigned N:1; unsigned Z:1; unsigned V:1; unsigned C:1; #endif }; extern struct _SR *SRBits; void memory_reset(void); void Memory_Init(void); void Memory_DeInit(void); /* Memory seek */ char memory_seek(unsigned int offset); /* Memory retrive */ #define Memory_RetrLongWord(V,Offset) Memory_Retr(V,32,Offset) #define Memory_RetrWord(V,Offset) Memory_Retr(V,16,Offset) #define Memory_RetrByte(V,Offset) Memory_Retr(V,8,Offset) char Memory_Retr(unsigned int *Result, short Size, int Offset); /* Memory Store */ #define Memory_StorLongWord(Offset,Value) Memory_Stor(32,Offset,Value) #define Memory_StorWord(Offset,Value) Memory_Stor(16,Offset,Value) #define Memory_StorByte(Offset,Value) Memory_Stor(8,Offset,Value) char Memory_Stor(short Size, int Offset, unsigned int Value); /* Memory retrive, and update the PC */ #define Memory_RetrByteFromPC(V) Memory_RetrFromPC(V,8) #define Memory_RetrWordFromPC(V) Memory_RetrFromPC(V,16) #define Memory_RetrLongWordFromPC(V) Memory_RetrFromPC(V,32) char Memory_RetrFromPC(unsigned int *Result, short Size); void memory_update(void); enum { SR_C = 0x0001, SR_V = 0x0002, SR_Z = 0x0004, SR_N = 0x0008, SR_X = 0x0010 }; /* Memory modules */ struct _memory_segment { char *name; unsigned int base; unsigned int *base_register; unsigned int mask; unsigned short interrupt_line; char *code; unsigned int code_len; void (*fini)(struct _memory_segment *s); char (*read)(struct _memory_segment *s, unsigned int *result, short size, unsigned int offset); char (*write)(struct _memory_segment *s, short size, unsigned int offset, unsigned int value); void (*reset)(struct _memory_segment *s); void (*update)(struct _memory_segment *s); void *data; }; struct _memory_module { char *name; void (*setup)(struct _memory_segment *s); }; void memory_module_register(char *name, void (*setup)(struct _memory_segment *s)); //void memory_module_setup_segment(char *module_name, char *data); void memory_module_setup_segment(char *module_name, int base_register, int base, int len); struct _memory_segment *memory_find_segment_for(unsigned int offset); void memory_core_set_reset_values(char *s); void memory_dump_segments(void); #endif ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/common/cycle.c�������������������������������������������������������0000644�0001750�0000144�00000003617�10541455476�017517� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/**********************************/ /* */ /* Copyright 2003, David Grant */ /* */ /* see LICENSE for more details */ /* */ /**********************************/ /* August 2000: Matt Minnis * March 2003: David Grant -- Rewrote everything for speed */ #include <stdio.h> #include "coldfire.h" void cycle(unsigned int number) { extern struct _board_data board_data; if(number < 1) return; /* ignore 0 and -1 times since they are invalid */ board_data.cycle_count += number; return; } /* Lookup table for getting the right offset in the timing tables * in each instruction */ static short cycle_EA_lookup[] = { 0, 0, 1, 2, 3, 4, 5, 6, 6, 4, 5, 7 }; int cycle_EA(short reg, short mode) { if(mode == 7) return cycle_EA_lookup[reg+7]; return cycle_EA_lookup[mode]; } #ifdef explanation_of_what_the_above_routine_is_doing int MoveCycle_EA (int Register, int Mode) (These two are the same) int Cycle_EA (int Register, int Mode) { switch (Mode) /* Return value 0-7 for destination addressing. */ { case 0: return sDRD; /* Dy */ case 1: return sDRD; /* Ay */ case 2: return sARI; /* (Ay) */ case 3: return sARIPO; /* (Ay)+ */ case 4: return sARIPR; /* -(Ay) */ case 5: return sARID; /* (d16,Ay) */ case 6: return sARIIB; /* (d8,An,Xi) */ case 7: switch (Register) { case 0: return sAS; /* word addressing */ case 1: return sAS; /* long addressing */ case 2: return sARID; /* (d16,PC) */ case 3: return sARIIB; /* (d8,PC,Xi) */ case 4: return sIM; /* (d8,PC,Xi) */ } break; } /* This can cause a segfault, this returns an offset, returning -1 is bad (DG) */ return -1; /* Shouldn't get here */ } #endif �����������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/mach/����������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015642� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/mach/mcf5249.h�������������������������������������������������������0000644�0001750�0000144�00000002160�10571720100�017104� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mcf5249.c - necessary mcf5249 definition for skyeye debugger Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 02/28/2007 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __MCF5249_H__ #define __MCF5249_H__ #define CSAR 0 #define CSMR 1 #define CSCR 2 #endif ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/mach/skyeye_mach_mcf5249.c�������������������������������������������0000644�0001750�0000144�00000050666�10600011124�021466� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_mcf5249.c - implementation of Coldfire 5249 Processor Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/27/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include <stdint.h> #include <stdio.h> #include "../common/memory.h" #include "mcf5249.h" //#include "tracer.h" #include "skyeye_uart.h" typedef struct uart_s{ uint8_t * umr; uint8_t umr1; uint8_t umr2; uint32_t usr; uint32_t ucsr; uint8_t ucr; uint32_t urb; uint32_t utb; uint32_t uipcr; uint32_t uacr; uint32_t uisr; uint32_t uimr; uint32_t ubg1; uint32_t ubg2; uint32_t uip; uint32_t uivr; uint32_t uop1; uint32_t uop0; }uart_t; struct interrupt_ctl_s{ uint32_t icr[3]; /* tweleve icr */ uint32_t imr; uint32_t ipr; }interrupt_ctl_t; enum{ UMR = 0, USR, UCSR = 1, UCR = 2, URB = 3, UTB = 3, UIPCR = 4, UACR = 4, UISR = 5, UIMR = 5, UBG1 = 6, UBG2 = 6, UIVR = 12, UIP = 13, UOP1 = 14, UOP0 = 15 }; uint32_t uart[2][0x3c]; typedef struct cs_module_s{ uint16_t csar; uint32_t csmr; uint16_t cscr; }cs_module_t; typedef struct mcf5249_timer_s{ uint32_t tmr; uint32_t trr; uint32_t tcr; uint32_t tcn; uint32_t ter; }mcf5249_timer_t; typedef struct mcf5249_dma_s{ uint32_t ivr; }mcf5249_dma_t; typedef struct mcf5249_io_s{ cs_module_t cs_module[4]; unsigned int intbase; unsigned int pllcr; unsigned int ideconfig1; unsigned int ideconfig2; unsigned int dmaconfig; unsigned int dmaroute; unsigned int gpio_out; unsigned int gpio_en; unsigned int gpio_func; unsigned int gpio1_out; unsigned int gpio1_en; unsigned int gpio1_func; unsigned int iis2_config; unsigned int data_in_ctrl; unsigned char icr[12]; unsigned int ipr; unsigned int imr; mcf5249_dma_t dma[4]; mcf5249_timer_t timer[2]; uart_t uart[2]; }mcf5249_io_t; static mcf5249_io_t mcf5249_io; static char cs_module_write(short size, int offset, unsigned int value); static char cs_module_read(unsigned int *result, short size, int offset); static char timer_write(short size, int offset, unsigned int value); static char timer_read(unsigned int *result, short size, int offset); static char uart_write(short size, int offset, unsigned int value); static char uart_read(unsigned int *result, short size, int offset); static uint32_t uart_read_word(uint32_t offset, int uart_id){ return uart[uart_id][offset]; } static uint32_t uart_write_word(uint32_t offset, uint32_t value, int uart_id){ uart[uart_id][offset] = value; return 0; } /* static uint32_t timer_read_word(uint32_t offset, int timer_id){ return timer[uart_id][offset]; } static uint32_t timer_write_word(uint32_t offset, uint32_t value, int timer_id){ timer[timer_id][offset] = value; return 0; }*/ static char mcf5249_mbar_write(short size, int offset, unsigned int value){ switch(offset){ case 0x44: mcf5249_io.imr = value; return 1; case 0x84: mcf5249_io.cs_module[0].csmr = value; return 1; case 0x8c: mcf5249_io.cs_module[1].csmr = value; break; case 0x314: mcf5249_io.dma[0].ivr = value; break; default: if(offset >= 0x80 && offset <= 0xAE) return cs_module_write(size, offset, value); if(offset >= 0x4C && offset < 0x58){ int index = offset - 0x4C; mcf5249_io.icr[index] = value; return 1; } if((offset >= 0x140 && offset < 0x154) || (offset >= 0x180 && offset < 0x194)) return timer_write(size, offset, value); if((offset >= 0x1C0 && offset <= 0x1FC) || (offset >= 0x200 && offset <= 0x23C)) return uart_write(size, offset, value); fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char mcf5249_mbar2_write(short size, int offset, unsigned int value){ switch(offset){ case 0x4: mcf5249_io.gpio_out = value; break; case 0x8: mcf5249_io.gpio_en = value; break; case 0xC: mcf5249_io.gpio_func = value; break; case 0x14: mcf5249_io.iis2_config = value; break; case 0x30: mcf5249_io.data_in_ctrl = value; break; case 0xB4: mcf5249_io.gpio1_out = value; break; case 0xB8: mcf5249_io.gpio1_en = value; break; case 0xBC: mcf5249_io.gpio1_func = value; break; case 0x16b:/* INT Base*/ mcf5249_io.intbase = value; break; case 0x180: mcf5249_io.pllcr = value; break; case 0x18C: mcf5249_io.ideconfig1 = value; break; case 0x190: mcf5249_io.ideconfig2 = value; break; case 0x188: mcf5249_io.dmaroute = value; break; case 0x9F: mcf5249_io.dmaconfig = value; break; case 0x74: printf("Warning:register is not implemented\n"); break; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } static char mcf5249_mbar_read(unsigned int *result, short size, int offset){ switch(offset){ case 0x40: *result = mcf5249_io.ipr; break; case 0x44: *result = mcf5249_io.imr; break; default: if((offset >= 0x140 && offset < 0x154) || (offset >= 0x180 && offset < 0x194)) return timer_read(result, size, offset); if((offset >= 0x1C0 && offset <= 0x1FC) || (offset >= 0x200 && offset <= 0x23C)) return uart_read(result, size, offset); fprintf(stderr,"Error adress in %s,offset=%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } static char mcf5249_mbar2_read(unsigned int *result, short size, int offset){ switch(offset){ case 0x4: *result = mcf5249_io.gpio_out; break; case 0x8: *result = mcf5249_io.gpio_en; break; case 0xc: *result = mcf5249_io.gpio_func; break; /* GPIO1 read */ case 0xB4: *result = mcf5249_io.gpio1_out; break; case 0xB8: *result = mcf5249_io.gpio1_en; break; case 0xBC: *result = mcf5249_io.gpio1_func; break; case 0x180: *result = mcf5249_io.pllcr; return 1; default: fprintf(stderr,"Error adress in %s,offset=%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } /* Interrupts go from 0 -> 9 on the 5307, with the 7 external * autovector only interrupts defined in the autovector interrupt */ /* ICR: * +----+----+----+----+----+----+----+----+ * | av | xx | xx | int level | int pri | * +----+----+----+----+----+----+----+----+ * av -- autovectored, 1=yes * int level -- interrupt level, 0 -> 7 * int pri -- interrupt priority 11(high) -> 00 (low) */ #define ICR_LEVEL(icr) (((icr) & 0x1c) >> 2) #define ICR_PRI(icr) ((icr) & 0x02) #define ICR_AVEC(icr) ((icr) & 0x80) static unsigned int mcf5249_iack_func(unsigned int interrupt_level){ unsigned long vector=0; int x; mcf5249_io_t * io = &mcf5249_io; //TRACE("called for interrupt_level=%d\n", interrupt_level); /* Find the _pending_ interrupt with level == interrupt_level */ for(x = 1; x < 18; x++) { int icr_avec, icr_level, icr_pri; if(!((io->ipr >> x) & 0x1)){ //TRACE("sim input number %d is not pending.\n", x); continue; } /* icr_avec will be non-zero if it's autovectored, but * it will be different for each interrupt level */ if(x >= 8) { icr_avec = ICR_AVEC(io->icr[x-8]); icr_level = ICR_LEVEL(io->icr[x-8]); icr_pri = ICR_PRI(io->icr[x-8]); /* TRACE(" %d: ICR = 0x%02x (IL=%d,pri=%d,avec=%d)\n", x, io->icr[x-8], icr_level, icr_pri, icr_avec?1:0); */ /* printf("DBG:%d: ICR = 0x%02x (IL=%d,pri=%d,avec=%d)\n", x, io->icr[x-8], icr_level, icr_pri, icr_avec?1:0); */ } else { /* 0 - interrupt source returns vector * 1 - autovector */ //icr_avec = (io->avr & (0x1<<x) ); icr_level=x; icr_pri=0; /* TRACE(" %d: external int (lev=%d,pri=%d,avec=%d)\n", x, icr_level, icr_pri, icr_avec?1:0); */ /* FIXME: how the heck do we use the IRQPAR? */ } if(icr_level != interrupt_level) continue; if(icr_avec) { //TRACE(" This interrupt is autovectored, using autovector.\n"); //TRACE(" vector = 24 + interrupt level(%d) = %d\n", // icr_level, 24 + icr_level); vector = 24 + icr_level; } else { /* check if uart0 interrupt */ if(icr_level == ICR_LEVEL(io->icr[4])) vector = mcf5249_io.uart[0].uivr; else fprintf(stderr, "Not implement for non autovector in %s\n", __FUNCTION__); //TRACE(" Polling the device to get the vector number...\n"); //vector = interrupt_acknowledge[x]; //TRACE(" vector = %d\n", vector); //ERR("Not implement for non autovector"); } return vector; } //ERR("Inside iack_func, but no interrupt is waiting with level %d\n", interrupt_level); fprintf(stderr, "Inside iack_func, but no interrupt is waiting with level %d\n", interrupt_level); return 0; } static void interrupt_assert(short number){ mcf5249_io_t * io = &mcf5249_io; int level = ICR_LEVEL(io->icr[number - 8]); int mask = 0x1 << number; //TRACE("Posting interrupt Number=%d, Vector=%d\n", number, vector); /* Post an interrupt */ if(!(io->imr & mask )) { /* check if exist pending interrupt */ if(io->ipr & mask) { //TRACE("Already pending, not playing with registers further.\n"); return; } exception_post(level, &mcf5249_iack_func); io->ipr |= mask; return; } } static void interrupt_withdraw(short number){ short mask = (0x1 << number); mcf5249_io_t * io = &mcf5249_io; int icr_level = ICR_LEVEL(io->icr[number - 8]); if(!(io->imr & mask )) { //TRACE("Withdrawing interrupt Number=%d\n", number); if(! (io->ipr & mask) ) { /* This interrupt isn't pending, there's no * need to withdraw it further */ //TRACE("Interrupt wasn't pending, no need to withdraw.\n"); return; } /* Set us not pending */ io->ipr &= ~mask; exception_withdraw(icr_level); //TRACE("Done.\n"); return; } // TRACE("NOT Withdrawn, the interrupt is unmasked in the IMR\n"); return; } void mcf5249_io_do_cycle(){ int i; for(i = 0; i < 2; i++){ //mcf5249_timer_t * timer = &mcf5249_io.timer[i]; /* check if timer is enbaled */ if(mcf5249_io.timer[i].tmr & 0x1){ mcf5249_io.timer[i].tcn++; /* check if reference interrupt is enabled */ if((mcf5249_io.timer[i].tcn == mcf5249_io.timer[i].trr) && (mcf5249_io.timer[i].tmr & 0x10)) { //printf("KSDBG:tcn=0x%x,trr=0x%x\n", mcf5249_io.timer[i].tcn, mcf5249_io.timer[i].trr); /* set REF bit in TER */ mcf5249_io.timer[i].ter |= 0x2; interrupt_assert(9 + i); /* check if in restart mode */ if(mcf5249_io.timer[i].tmr & 0x8) mcf5249_io.timer[i].tcn = 0x0; } } } if(1){ /* UART FIFO full interrupt enabled */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0){ mcf5249_io.uart[0].urb = buf; /* set RXRDY bit in UISR */ mcf5249_io.uart[0].uisr |= 0x2; } /* set TXRDY bit in UISR */ mcf5249_io.uart[0].uisr |= 0x1; } /* check if UART Transmitter ready interrupt enabled */ if(!(mcf5249_io.ipr & 0xc)){ if((mcf5249_io.uart[0].uimr & mcf5249_io.uart[0].uisr)) interrupt_assert(0xc); } } static char cs_module_read(unsigned int *result, short size, int offset){ int index = offset - 0x80; int reg_no; if(index >= 0 && index <=8){ reg_no = index / 4; index = 0; } if(index >= 0xc && index <= 0x16){ reg_no = (index - 0xc)/ 4; index = 1; } if(index >= 0x18 && index <= 0x22){ reg_no = (index - 0x18)/4; index = 2; } if(index >= 0x24 && index <= 0x2e){ reg_no = (index - 0x24); index = 3; } switch(reg_no){ case CSAR: *result = mcf5249_io.cs_module[index].csar; return 1; case CSMR: *result = mcf5249_io.cs_module[index].csmr; return 1; case CSCR: *result = mcf5249_io.cs_module[index].cscr; return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char cs_module_write(short size, int offset, unsigned int value){ int index = offset - 0x80; int reg_no; if(index >= 0 && index <=8){ reg_no = index / 4; index = 0; } if(index >= 0xc && index <= 0x16){ reg_no = (index - 0xc)/ 4; index = 1; } if(index >= 0x18 && index <= 0x22){ reg_no = (index - 0x18)/4; index = 2; } if(index >= 0x24 && index <= 0x2e){ reg_no = (index - 0x24); index = 3; } switch(reg_no){ case CSAR: mcf5249_io.cs_module[index].csar = value; return 1; case CSMR: mcf5249_io.cs_module[index].csmr = value; return 1; case CSCR: mcf5249_io.cs_module[index].cscr = value; return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char timer_read(unsigned int *result, short size, int offset){ int index = (offset - 0x140) / 0x40; offset = offset - 0x140 - (index * 0x40); //printf("DBG: in %s, offset = 0x%x, value=0x%x\n", __FUNCTION__, offset, value); switch(offset){ case 0x0: *result = mcf5249_io.timer[index].tmr; return 1; case 0x4: *result = mcf5249_io.timer[index].trr; return 1; case 0x8: *result = mcf5249_io.timer[index].tcr; return 1; case 0xc: *result = mcf5249_io.timer[index].tcn; return 1; case 0x11: /* write one to clear the corresponding bit */ *result = mcf5249_io.timer[index].ter; /* clear the corresponding bit in ipr */ //mcf5249_io.ipr &= ~(0x1 << 9); interrupt_withdraw(index + 9); return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char timer_write(short size, int offset, unsigned int value){ int index = (offset - 0x140) / 0x40; offset = offset - 0x140 - (index * 0x40); //printf("DBG: in %s, offset = 0x%x, value=0x%x\n", __FUNCTION__, offset, value); switch(offset){ case 0x0: mcf5249_io.timer[index].tmr = value; return 1; case 0x4: mcf5249_io.timer[index].trr = value; return 1; case 0x8: mcf5249_io.timer[index].tcr = value; return 1; case 0xc: mcf5249_io.timer[index].tcn = value; return 1; case 0x11: /* write one to clear the corresponding bit */ mcf5249_io.timer[index].ter &= ~(value & 0x3); /* clear the corresponding bit in ipr */ //mcf5249_io.ipr &= ~(0x1 << 9); interrupt_withdraw(index + 9); return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char uart_read(unsigned int *result, short size, int offset){ int index; if(offset >= 0x1C0 && offset <= 0x1FC){ index = 0; offset = offset - 0x1C0; } if(offset >= 0x200 && offset <= 0x23C){ index = 1; offset = offset - 0x200; } /* extern struct _memory_core memory_core; if(offset != 0x4) printf("DBG: in %s, offset = 0x%x,PC=0x%x\n", __FUNCTION__, offset, memory_core.pc); */ switch(offset){ case 0x0: *result = mcf5249_io.uart[index].umr1; break; case 0x4: *result = mcf5249_io.uart[index].usr; break; case 0xC: *result = mcf5249_io.uart[index].urb; /* set FFULL bit in USR is zero */ mcf5249_io.uart[index].usr &= ~0x2; /* set RxRDY bit in USR is zero */ mcf5249_io.uart[index].usr &= ~0x1; /* check RXIRQ bit in UMR1 */ //if(mcf5249_io.uart[index].umr1 & 0x40) mcf5249_io.uart[index].uisr &= ~0x2; break; case 0x10: *result = mcf5249_io.uart[index].uipcr; break; case 0x14: *result = mcf5249_io.uart[index].uisr; mcf5249_io.uart[index].uisr = 0x0; interrupt_withdraw(12); break; case 0x18: *result = mcf5249_io.uart[index].ubg1; break; case 0x1C: *result = mcf5249_io.uart[index].ubg2; break; case 0x30: *result = mcf5249_io.uart[index].uivr; break; case 0x34: *result = mcf5249_io.uart[index].uip; break; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } static char uart_write(short size, int offset, unsigned int value){ int index, cmd; char tmp; if(offset >= 0x1C0 && offset <= 0x1FC){ index = 0; offset = offset - 0x1C0; } if(offset >= 0x200 && offset <= 0x23C){ index = 1; offset = offset - 0x200; } /* if(offset != 0xc) printf("DBG: in %s, offset = 0x%x, value=0x%x\n", __FUNCTION__, offset, value); */ switch(offset){ case 0x0: mcf5249_io.uart[index].umr1 = value; break; case 0x4: mcf5249_io.uart[index].ucsr = value; break; case 0x8: mcf5249_io.uart[index].ucr = value; if((value & 0x3) == 0x1) /* Receiver enable */ ; if(((value >> 2) & 0x3) == 0x1) /* Transmitter enable */ /* set TXRDY bit and TXEMP bit in usr */ mcf5249_io.uart[index].usr |= 0xc; cmd = (value >> 4) & 0x7; if (cmd == 0x4) /* Reset error status */ mcf5249_io.uart[index].usr &= 0xf; break; case 0xc: mcf5249_io.uart[index].utb = value; tmp = value & 0xff; skyeye_uart_write(-1, &tmp, 1, NULL); /* set TXRDY bit and TXEMP bit in usr */ mcf5249_io.uart[index].usr |= 0xc; /* set TXRDY bit in usr */ mcf5249_io.uart[index].uisr |= 0x1; break; case 0x10: mcf5249_io.uart[index].uacr = value; break; case 0x14: mcf5249_io.uart[index].uimr = value; break; case 0x18: mcf5249_io.uart[index].ubg1 = value; break; case 0x1C: mcf5249_io.uart[index].ubg2 = value; break; case 0x30: mcf5249_io.uart[index].uivr = value; break; case 0x38: mcf5249_io.uart[index].uop1 = value; break; case 0x3C: mcf5249_io.uart[index].uop0 = value; break; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } void mcf5249_mach_init(void * state, machine_config_t * mach){ struct _memory_core * core = (struct _memory_core *)state; machine_config_t * this_mach = mach; core->mbar_read = mcf5249_mbar_read; core->mbar_write = mcf5249_mbar_write; core->mbar2_read = mcf5249_mbar2_read; core->mbar2_write = mcf5249_mbar2_write; /* init io value */ /* init mach */ if (!this_mach) { exit (-1); } this_mach->mach_io_do_cycle = mcf5249_io_do_cycle; /* this_mach->mach_io_read_byte = mcf5249_io_read_byte; this_mach->mach_io_read_halfword = mcf5249_io_read_halfword; this_mach->mach_io_read_word = mcf5249_io_read_word; this_mach->mach_io_write_byte = mcf5249_io_write_byte; this_mach->mach_io_write_halfword = mcf5249_io_write_halfword; this_mach->mach_io_write_word = mcf5249_io_write_word; this_mach->mach_io_do_cycle = mcf5249_io_do_cycle; this_mach->mach_set_intr = mcf5249_set_int; */ } ��������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/mach/skyeye_mach_mcf5272.c�������������������������������������������0000644�0001750�0000144�00000051132�10717060474�021474� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_mcf5272.c - implementation of Coldfire 5272 Processor Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/27/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include <stdint.h> #include <stdio.h> #include "../common/memory.h" #include "mcf5272.h" //#include "tracer.h" #include "skyeye_uart.h" typedef struct uart_s{ uint8_t * umr; uint8_t umr1; uint8_t umr2; uint32_t usr; uint32_t ucsr; uint8_t ucr; uint32_t urb; uint32_t utb; uint32_t uipcr; uint32_t uacr; uint32_t uisr; uint32_t uimr; uint32_t ubg1; uint32_t ubg2; uint32_t ufpd; uint32_t uip; uint32_t uop1; uint32_t uop0; }uart_t; typedef struct cs_module_s{ uint16_t csar; uint32_t csmr; uint16_t cscr; }cs_module_t; typedef struct mcf5272_timer_s{ uint32_t tmr; uint32_t trr; uint32_t tcap; uint32_t tcn; uint32_t ter; }mcf5272_timer_t; typedef struct mcf5272_dma_s{ uint32_t ivr; }mcf5272_dma_t; typedef struct mcf5272_ethernet_s{ uint32_t ecr; uint32_t eir; uint32_t eimr; uint32_t rdar; uint32_t mscr; uint32_t mmfr; uint32_t rcr; uint32_t tcr; uint32_t htur; uint32_t htlr; uint32_t malr; uint32_t maur; uint32_t erdsr; uint32_t etdst; uint32_t emrbr; }mcf5272_ethernet_t; typedef struct mcf5272_io_s{ unsigned int scr; cs_module_t cs_module[4]; unsigned int intbase; unsigned int pllcr; unsigned int ideconfig1; unsigned int ideconfig2; unsigned int dmaconfig; unsigned int dmaroute; unsigned int pacnt; /* Port A Control (r/w) */ unsigned int paddr; /* Port A Direction (r/w) */ unsigned int padat; /* Port A Data (r/w) */ unsigned int pbcnt; /* Port B Control (r/w) */ unsigned int pbddr; /* Port B Direction (r/w) */ unsigned int pbdat; /* Port B Data (r/w) */ unsigned int pcddr; /* Port C Direction (r/w) */ unsigned int pcdat; /* Port C Data (r/w) */ unsigned int pdcnt; /* Port D Control (r/w) */ unsigned int iis2_config; unsigned int data_in_ctrl; unsigned int icr[4]; unsigned int isr; unsigned char pivr; unsigned int pmr; mcf5272_dma_t dma[4]; mcf5272_timer_t timer[4]; uart_t uart[2]; mcf5272_ethernet_t ether; }mcf5272_io_t; static mcf5272_io_t mcf5272_io; static char cs_module_write(short size, int offset, unsigned int value); static char cs_module_read(unsigned int *result, short size, int offset); static char timer_write(short size, int offset, unsigned int value); static char timer_read(unsigned int *result, short size, int offset); static char uart_write(short size, int offset, unsigned int value); static char uart_read(unsigned int *result, short size, int offset); static char mcf5272_mbar_write(short size, int offset, unsigned int value){ mcf5272_io_t * io = &mcf5272_io; switch(offset){ case MCFSIM_SCR: io->scr = value; break; case MCFSIM_PIVR: io->pivr = value; break; case 0xa: io->pmr = value; break; case MCFSIM_PBDDR: io->pbddr = value; break; case MCFSIM_PBCNT: io->pbcnt = value; break; case MCFSIM_PDCNT: io->pdcnt = value; break; case MCF_ECR: io->ether.ecr = value; break; case MCF_EIR: io->ether.eir = value; break; case MCF_EIMR: io->ether.eimr = value; break; case MCF_RDAR: io->ether.rdar = value; break; case MCF_MMFR: io->ether.mmfr = value; break; case MCF_MSCR: io->ether.mscr = value; break; case MCF_RCR: io->ether.rcr = value; break; case MCF_TCR: io->ether.tcr = value; break; case MCF_MALR: io->ether.malr = value; break; case MCF_MAUR: io->ether.maur = value; break; case MCF_HTUR: io->ether.htur = value; break; case MCF_HTLR: io->ether.htlr = value; break; case MCF_ERDSR: io->ether.erdsr = value; break; case MCF_ETDSR: io->ether.etdst = value; break; case MCF_EMRBR: io->ether.emrbr = value; break; default: if(offset >= 0x20 && offset <= 0x2C){ int index = (offset - 0x20) / 4; unsigned int old_value = mcf5272_io.icr[index]; int i; /* IPL is changed only when a 1 is written simultaneously to the corresponding PI bit */ for(i = 31; i > 0; i = i - 4) if((value >> i) & 0x1) old_value = (value & (0xf << (i - 3))) | (old_value & (~(0xf << (i - 3)))); mcf5272_io.icr[index] = old_value; return 1; } if((offset >= 0x200 && offset <= 0x272)) return timer_write(size, offset, value); if((offset >= 0x100 && offset <= 0x13C) || (offset >= 0x140 && offset <= 0x17C)) return uart_write(size, offset, value); #if 0 if(offset >= 0x80 && offset <= 0xAE) return cs_module_write(size, offset, value); if((offset >= 0x140 && offset < 0x154) || (offset >= 0x180 && offset < 0x194)) return timer_write(size, offset, value); if((offset >= 0x1C0 && offset <= 0x1FC) || (offset >= 0x200 && offset <= 0x23C)) return uart_write(size, offset, value); #endif fprintf(stderr,"Error adress in %s,offset=0x%x,pc=0x%x\n",__FUNCTION__,offset, memory_core.pc); skyeye_exit(-1); return 0; } } static char mcf5272_mbar2_write(short size, int offset, unsigned int value){ switch(offset){ #if 0 case 0x4: mcf5272_io.gpio_out = value; break; case 0x8: mcf5272_io.gpio_en = value; break; case 0xC: mcf5272_io.gpio_func = value; break; case 0x14: mcf5272_io.iis2_config = value; break; case 0x30: mcf5272_io.data_in_ctrl = value; break; case 0xB4: mcf5272_io.gpio1_out = value; break; case 0xB8: mcf5272_io.gpio1_en = value; break; case 0xBC: mcf5272_io.gpio1_func = value; break; case 0x16b:/* INT Base*/ mcf5272_io.intbase = value; break; case 0x180: mcf5272_io.pllcr = value; break; case 0x18C: mcf5272_io.ideconfig1 = value; break; case 0x190: mcf5272_io.ideconfig2 = value; break; case 0x188: mcf5272_io.dmaroute = value; break; case 0x9F: mcf5272_io.dmaconfig = value; break; case 0x74: printf("Warning:register is not implemented\n"); break; #endif default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } static char mcf5272_mbar_read(unsigned int *result, short size, int offset){ mcf5272_io_t * io = &mcf5272_io; switch(offset){ case MCFSIM_ISR: *result = io->isr; break; case MCFSIM_PBDDR: *result = io->pbddr; break; case MCFSIM_PBCNT: *result = io->pbcnt; break; case MCFSIM_PDCNT: *result = io->pdcnt; break; case MCF_MALR: *result = io->ether.malr; break; case MCF_MAUR: *result = io->ether.maur; break; default: if((offset >= 0x100 && offset <= 0x13C) || (offset >= 0x140 && offset <= 0x17C)) return uart_read(result, size, offset); if((offset >= 0x200 && offset < 0x270)) return timer_read(result, size, offset); if(offset >= 0x20 && offset <= 0x2C){ int index = offset - 0x20; return mcf5272_io.icr[index/4]; } fprintf(stderr,"Error adress in %s,offset=%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } static char mcf5272_mbar2_read(unsigned int *result, short size, int offset){ switch(offset){ /* case 0x4: *result = mcf5272_io.gpio_out; break; case 0x8: *result = mcf5272_io.gpio_en; break; case 0xc: *result = mcf5272_io.gpio_func; break; */ /* GPIO1 read */ #if 0 case 0xB4: *result = mcf5272_io.gpio1_out; break; case 0xB8: *result = mcf5272_io.gpio1_en; break; case 0xBC: *result = mcf5272_io.gpio1_func; break; case 0x180: *result = mcf5272_io.pllcr; return 1; #endif default: fprintf(stderr,"Error adress in %s,offset=%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } /* Interrupts go from 0 -> 9 on the 5307, with the 7 external * autovector only interrupts defined in the autovector interrupt */ /* ICR: * +----+----+----+----+----+----+----+----+ * | av | xx | xx | int level | int pri | * +----+----+----+----+----+----+----+----+ * av -- autovectored, 1=yes * int level -- interrupt level, 0 -> 7 * int pri -- interrupt priority 11(high) -> 00 (low) */ #define ICR_LEVEL(x) ((mcf5272_io.icr[(31 - x) / 8] >> (4 * (x % 8))) & 0x7) //#define ICR_PRI(icr) ((icr) & 0x02) //#define ICR_AVEC(icr) ((icr) & 0x80) static unsigned int mcf5272_iack_func(unsigned int interrupt_level){ unsigned long vector=0; int x; mcf5272_io_t * io = &mcf5272_io; //TRACE("called for interrupt_level=%d\n", interrupt_level); /* Find the _pending_ interrupt with level == interrupt_level */ /* INT1_IRQ has highest priority and SWTO_IRQ is lowest priority */ for(x = INT1_IRQ; x > SWTO_IRQ; x--) { int icr_avec, icr_level, icr_pri; if(!((io->isr >> x) & 0x1)){ continue; } icr_level = ICR_LEVEL(x); if(icr_level != interrupt_level) continue; /* see p163 of user manual of 5272 */ vector = (32 - x) | (io->pivr & 0xe0); /* if(x != 24) printf("DBG: in %s, vector=%d\n", __FUNCTION__, vector); */ return vector; } //ERR("Inside iack_func, but no interrupt is waiting with level %d\n", interrupt_level); fprintf(stderr, "Inside iack_func, but no interrupt is waiting with level %d\n", interrupt_level); return 0; } static void interrupt_assert(short number){ mcf5272_io_t * io = &mcf5272_io; int level = ICR_LEVEL(number);; /* if(number != 24) printf("DBG:Posting interrupt Number=%d, Level=%d\n", number, level); */ //TRACE("Posting interrupt Number=%d, Vector=%d\n", number, vector); /* Post an interrupt */ exception_post(level, &mcf5272_iack_func); io->isr |= 0x1 << number; return; } static void interrupt_withdraw(short number){ mcf5272_io_t * io = &mcf5272_io; int icr_level = ICR_LEVEL(number); io->isr &= ~(0x1 << number); /* if(number != 24) printf("DBG:in %s Number=%d, Level=%d\n", __FUNCTION__, number, icr_level); */ exception_withdraw(icr_level); //TRACE("Done.\n"); return; } void mcf5272_io_do_cycle(){ int i; for(i = 0; i < TIMER_NUM; i++){ //mcf5272_timer_t * timer = &mcf5272_io.timer[i]; /* check if timer is enbaled */ if(mcf5272_io.timer[i].tmr & 0x1){ mcf5272_io.timer[i].tcn++; /* check if reference interrupt is enabled */ if((mcf5272_io.timer[i].tcn == mcf5272_io.timer[i].trr) && (mcf5272_io.timer[i].tmr & 0x10)) { //printf("DBG:tcn=0x%x,trr=0x%x,i=%d\n", mcf5272_io.timer[i].tcn, mcf5272_io.timer[i].trr, i); /* set REF bit in TER */ mcf5272_io.timer[i].ter |= 0x2; interrupt_assert(TIMER0_IRQ - i); /* check if in restart mode */ if(mcf5272_io.timer[i].tmr & 0x8) mcf5272_io.timer[i].tcn = 0x0; } } } if(1){ /* UART FIFO full interrupt enabled */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0){ mcf5272_io.uart[0].urb = buf; /* set RXRDY bit in UISR */ mcf5272_io.uart[0].uisr |= 0x2; } /* set TXRDY bit in UISR */ mcf5272_io.uart[0].uisr |= 0x1; } /* check if UART Transmitter ready interrupt enabled */ if(!(mcf5272_io.isr & UART1_IRQ)){ if((mcf5272_io.uart[0].uimr & mcf5272_io.uart[0].uisr)) interrupt_assert(UART1_IRQ); } } static char cs_module_read(unsigned int *result, short size, int offset){ int index = offset - 0x80; int reg_no; if(index >= 0 && index <=8){ reg_no = index / 4; index = 0; } if(index >= 0xc && index <= 0x16){ reg_no = (index - 0xc)/ 4; index = 1; } if(index >= 0x18 && index <= 0x22){ reg_no = (index - 0x18)/4; index = 2; } if(index >= 0x24 && index <= 0x2e){ reg_no = (index - 0x24); index = 3; } switch(reg_no){ /* case CSAR: *result = mcf5272_io.cs_module[index].csar; return 1; case CSMR: *result = mcf5272_io.cs_module[index].csmr; return 1; case CSCR: *result = mcf5272_io.cs_module[index].cscr; return 1; */ default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char cs_module_write(short size, int offset, unsigned int value){ int index = offset - 0x80; int reg_no; if(index >= 0 && index <=8){ reg_no = index / 4; index = 0; } if(index >= 0xc && index <= 0x16){ reg_no = (index - 0xc)/ 4; index = 1; } if(index >= 0x18 && index <= 0x22){ reg_no = (index - 0x18)/4; index = 2; } if(index >= 0x24 && index <= 0x2e){ reg_no = (index - 0x24); index = 3; } switch(reg_no){ /* case CSAR: mcf5272_io.cs_module[index].csar = value; return 1; case CSMR: mcf5272_io.cs_module[index].csmr = value; return 1; case CSCR: mcf5272_io.cs_module[index].cscr = value; return 1; */ default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char timer_read(unsigned int *result, short size, int offset){ int index = (offset - 0x200) / 0x20; offset = offset % 0x20; //printf("DBG: in %s, offset = 0x%x", __FUNCTION__, offset); switch(offset){ case 0x0: *result = mcf5272_io.timer[index].tmr; return 1; case 0x4: *result = mcf5272_io.timer[index].trr; return 1; case 0x8: *result = mcf5272_io.timer[index].tcap; return 1; case 0xc: *result = mcf5272_io.timer[index].tcn; return 1; case 0x11: /* write one to clear the corresponding bit */ *result = mcf5272_io.timer[index].ter; /* clear the corresponding bit in ipr */ //mcf5272_io.ipr &= ~(0x1 << 9); interrupt_withdraw(TIMER0_IRQ - index); return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } } static char timer_write(short size, int offset, unsigned int value){ printf("DBG: in %s, offset = 0x%x, value=0x%x\n", __FUNCTION__, offset, value); int index = (offset - 0x200) / 0x20; offset = offset % 0x20; switch(offset){ case 0x0: mcf5272_io.timer[index].tmr = value; return 1; case 0x4: mcf5272_io.timer[index].trr = value; return 1; case 0x8: mcf5272_io.timer[index].tcap = value; return 1; case MCFTIMER_TCN: mcf5272_io.timer[index].tcn = value; return 1; case MCFTIMER_TER: /* write one to clear the corresponding bit */ mcf5272_io.timer[index].ter &= ~(value & 0x3); /* clear the corresponding bit in ipr */ //mcf5272_io.ipr &= ~(0x1 << 9); interrupt_withdraw(TIMER0_IRQ - index); return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); //skyeye_exit(-1); return 0; } } static char uart_read(unsigned int *result, short size, int offset){ int index; if(offset >= 0x100 && offset <= 0x13C){ index = 0; offset = offset - 0x100; } if(offset >= 0x140 && offset <= 0x17C){ index = 1; offset = offset - 0x140; } extern struct _memory_core memory_core; /* if(offset != 0x4) printf("DBG: in %s, offset = 0x%x,PC=0x%x\n", __FUNCTION__, offset, memory_core.pc); */ switch(offset){ case 0x0: *result = mcf5272_io.uart[index].umr1; break; case 0x4: *result = mcf5272_io.uart[index].usr; break; case 0xC: *result = mcf5272_io.uart[index].urb; /* set FFULL bit in USR is zero */ mcf5272_io.uart[index].usr &= ~0x2; /* set RxRDY bit in USR is zero */ mcf5272_io.uart[index].usr &= ~0x1; /* check RXIRQ bit in UMR1 */ //if(mcf5272_io.uart[index].umr1 & 0x40) mcf5272_io.uart[index].uisr &= ~0x2; break; case 0x10: *result = mcf5272_io.uart[index].uipcr; break; case 0x14: *result = mcf5272_io.uart[index].uisr; mcf5272_io.uart[index].uisr = 0x0; interrupt_withdraw(UART1_IRQ - index); break; case 0x18: *result = mcf5272_io.uart[index].ubg1; break; case 0x1C: *result = mcf5272_io.uart[index].ubg2; break; case 0x34: *result = mcf5272_io.uart[index].uip; break; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } static char uart_write(short size, int offset, unsigned int value){ int index, cmd; char tmp; if(offset >= 0x100 && offset <= 0x13C){ index = 0; offset = offset - 0x100; } if(offset >= 0x140 && offset <= 0x17C){ index = 1; offset = offset - 0x140; } /* if(offset != 0xc) printf("DBG: in %s, offset = 0x%x, value=0x%x\n", __FUNCTION__, offset, value); */ switch(offset){ case 0x0: mcf5272_io.uart[index].umr1 = value; break; case 0x4: mcf5272_io.uart[index].ucsr = value; break; case 0x8: mcf5272_io.uart[index].ucr = value; if((value & 0x3) == 0x1) /* Receiver enable */ ; if(((value >> 2) & 0x3) == 0x1) /* Transmitter enable */ /* set TXRDY bit and TXEMP bit in usr */ mcf5272_io.uart[index].usr |= 0xc; cmd = (value >> 4) & 0x7; if (cmd == 0x4) /* Reset error status */ mcf5272_io.uart[index].usr &= 0xf; break; case 0xc: mcf5272_io.uart[index].utb = value; tmp = value & 0xff; skyeye_uart_write(-1, &tmp, 1, NULL); /* set TXRDY bit and TXEMP bit in usr */ mcf5272_io.uart[index].usr |= 0xc; /* set TXRDY bit in usr */ mcf5272_io.uart[index].uisr |= 0x1; break; case 0x10: mcf5272_io.uart[index].uacr = value; break; case 0x14: mcf5272_io.uart[index].uimr = value; break; case 0x18: mcf5272_io.uart[index].ubg1 = value; break; case 0x1C: mcf5272_io.uart[index].ubg2 = value; break; case 0x30: mcf5272_io.uart[index].ufpd = value; break; case 0x38: mcf5272_io.uart[index].uop1 = value; break; case 0x3C: mcf5272_io.uart[index].uop0 = value; break; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1; } void mcf5272_mach_init(void * state, machine_config_t * mach){ struct _memory_core * core = (struct _memory_core *)state; machine_config_t * this_mach = mach; core->mbar_read = mcf5272_mbar_read; core->mbar_write = mcf5272_mbar_write; core->mbar2_read = mcf5272_mbar2_read; core->mbar2_write = mcf5272_mbar2_write; mcf5272_io.uart[0].usr |= 0xc; /* init io value */ /* fixme, workaround for uClinux */ mcf5272_io.pivr = 0x40; /* init mach */ if (!this_mach) { exit (-1); } this_mach->mach_io_do_cycle = mcf5272_io_do_cycle; #if 0 this_mach->mach_io_read_byte = mcf5272_io_read_byte; this_mach->mach_io_read_halfword = mcf5272_io_read_halfword; this_mach->mach_io_read_word = mcf5272_io_read_word; this_mach->mach_io_write_byte = mcf5272_io_write_byte; this_mach->mach_io_write_halfword = mcf5272_io_write_halfword; this_mach->mach_io_write_word = mcf5272_io_write_word; this_mach->mach_io_do_cycle = mcf5272_io_do_cycle; this_mach->mach_set_intr = mcf5272_set_int; #endif } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/coldfire/mach/mcf5272.h�������������������������������������������������������0000644�0001750�0000144�00000016473�10713063134�017121� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mcf5272.c - necessary mcf5272 definition for skyeye debugger Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 02/28/2007 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __MCF5272_H__ #define __MCF5272_H__ #define TIMER_NUM 4 #define TIMER0_IRQ 27 #define UART_NUM 2 #define UART1_IRQ 23 #define INT1_IRQ 31 #define SWTO_IRQ 4 /* * Define the TIMER register set addresses. */ #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ #define MCFTIMER_TCAP 0x08 /* Timer Capture reg (r/w) */ #define MCFTIMER_TCN 0x0c /* Timer Counter reg (r/w) */ #define MCFTIMER_TER 0x10 /* Timer Event reg (r/w) */ /* * Define the 5272 SIM register set addresses. */ #define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ #define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ #define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ #define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ #define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ #define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ #define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ #define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ #define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ #define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ #define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ #define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ #define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ #define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ #define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ #define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ #define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ #define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ #define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ #define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ #define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ #define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ #define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ #define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ #define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ #define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ #define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ #define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ #define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ #define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ #define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ #define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ #define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ #define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ #define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ #define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ #define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ #define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ #define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ #define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ #define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ #define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ #define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ #define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ #define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ #define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ #define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ #define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ /* * Bit definitions for 5272 ICRs */ /* Hereunder, PI = interrupt enable, IPL = int priority level */ /* IPL may only be written at the same time as PI is enabled */ #define MCFSIM_INT1PI 0x80000000 #define MCFSIM_INT1IPL(x) ((x & 0x7) << 28) #define MCFSIM_INT2PI 0x08000000 #define MCFSIM_INT2IPL(x) ((x & 0x7) << 24) #define MCFSIM_INT3PI 0x00800000 #define MCFSIM_INT3IPL(x) ((x & 0x7) << 20) #define MCFSIM_INT4PI 0x00080000 #define MCFSIM_INT4IPL(x) ((x & 0x7) << 16) #define MCFSIM_TMR0PI 0x00008000 #define MCFSIM_TMR0IPL(x) ((x & 0x7) << 12) #define MCFSIM_TMR1PI 0x00000800 #define MCFSIM_TMR1IPL(x) ((x & 0x7) << 8) #define MCFSIM_TMR2PI 0x00000080 #define MCFSIM_TMR2IPL(x) ((x & 0x7) << 4) #define MCFSIM_TMR3PI 0x00000008 #define MCFSIM_TMR3IPL(x) ((x & 0x7) << 0) /* Interrupt vectors for 5272: */ #define MCF_INT_SUPRIOUS 64 /* User Spurious Interrupt */ #define MCF_INT_INT1 65 /* External Interrupt Input 1 */ #define MCF_INT_INT2 66 /* External Interrupt Input 2 */ #define MCF_INT_INT3 67 /* External Interrupt Input 3 */ #define MCF_INT_INT4 68 /* External Interrupt Input 4 */ #define MCF_INT_TMR0 69 /* Timer 0 */ #define MCF_INT_TMR1 70 /* Timer 1 */ #define MCF_INT_TMR2 71 /* Timer 2 */ #define MCF_INT_TMR3 72 /* Timer 3 */ #define MCF_INT_UART1 73 /* UART 1 */ #define MCF_INT_UART2 74 /* UART 2 */ #define MCF_INT_PLIP 75 /* PLIC 2KHz Periodic */ #define MCF_INT_PLIA 76 /* PLIC Asynchronous */ #define MCF_INT_USB0 77 /* USB Endpoint 0 */ #define MCF_INT_USB1 78 /* USB Endpoint 1 */ #define MCF_INT_USB2 79 /* USB Endpoint 2 */ #define MCF_INT_USB3 80 /* USB Endpoint 3 */ #define MCF_INT_USB4 81 /* USB Endpoint 4 */ #define MCF_INT_USB5 82 /* USB Endpoint 5 */ #define MCF_INT_USB6 83 /* USB Endpoint 6 */ #define MCF_INT_USB7 84 /* USB Endpoint 7 */ #define MCF_INT_DMA 85 /* DMA Controller */ #define MCF_INT_ERx 86 /* Ethernet Receiver */ #define MCF_INT_ETx 87 /* Ethernet Transmitter */ #define MCF_INT_ENTC 88 /* Ethernet Module Non-time-critical */ #define MCF_INT_QSPI 89 /* Queued Serial Peripheral Interface */ #define MCF_INT_INT5 90 /* External Interrupt Input 5 */ #define MCF_INT_INT6 91 /* External Interrupt Input 6 */ #define MCF_INT_SWTO 92 /* Software Watchdog Timer Timeout */ #define MCF_INT_93 93 /* Reserved */ #define MCF_INT_94 94 /* Reserved */ #define MCF_INT_95 95 /* Reserved */ /* Ether netcard */ #define MCF_ECR 0x840 #define MCF_EIR 0x844 #define MCF_EIMR 0x848 #define MCF_RDAR 0x850 #define MCF_MMFR 0x880 #define MCF_MSCR 0x884 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�ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/Makefile.in��������������������������������������������������������������0000644�0001750�0000144�00000113434�11023514464�016176� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������# Makefile.in generated by automake 1.10 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006 Free Software Foundation, Inc. # This Makefile.in is free software; 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installdirs maintainer-clean \ maintainer-clean-generic mostlyclean mostlyclean-compile \ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \ uninstall-am # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/Makefile.am��������������������������������������������������������������0000644�0001750�0000144�00000001110�11006337414�016147� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������mips_mach = mach/skyeye_mach_au1100.c mach/skyeye_mach_nedved.c mips_comm = common/cache.c common/decoder.c common/icache.c common/mipsio.c common/tlb.c \ common/cp0.c common/emul.c common/interrupt.c common/mipsmem.c \ common/dcache.c common/exception.c common/mips_arch_interface.c common/multiply.c libmips_a_SOURCES = $(mips_mach) $(mips_comm) noinst_LIBRARIES = libmips.a DEFS = -g -O2 -D_FILE_OFFSET_BITS=64 -DSTANDALONE -DDEFAULT_INLINE=0 INCLUDES = -I./common -I$(top_srcdir)/utils/debugger -I$(top_srcdir)/device/uart @COMMON_INCLUDES@ ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015403� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/mipsio.c����������������������������������������������������������0000644�0001750�0000144�00000006426�10643717416�017100� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mipsio.c - necessary arm definition for skyeye debugger Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/07/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "types.h" #include "emul.h" #include "skyeye_config.h" extern MIPS_State *mstate; UInt32 mips_io_read_byte(UInt32 addr) { if (skyeye_config.mach->mach_io_read_byte) return skyeye_config.mach->mach_io_read_byte(mstate, addr); else{ fprintf(stderr, "io_read_byte is not initialized,in %s \n", __FUNCTION__); skyeye_exit(-1); return 0; /* never executed */ } } UInt32 mips_io_read_halfword(UInt32 addr) { if (skyeye_config.mach->mach_io_read_halfword) return skyeye_config.mach->mach_io_read_halfword(mstate, addr); else{ fprintf(stderr, "io_read_halfword is not initialized, in %s\n", __FUNCTION__); skyeye_exit(-1); return 0; /* never executed */ } } UInt32 mips_io_read_word(UInt32 addr) { if (skyeye_config.mach->mach_io_read_word) return skyeye_config.mach->mach_io_read_word(mstate, addr); else{ fprintf(stderr, "io_read_word is not initializedin %s\n", __FUNCTION__); skyeye_exit(-1); return 0; /* never executed */ } } UInt64 mips_io_read_doubleword(UInt32 addr) { fprintf(stderr, "io_read_doubleword is not initializedin %s\n", __FUNCTION__); skyeye_exit(-1); } void mips_io_write_byte(UInt32 addr, UInt32 data) { if (skyeye_config.mach->mach_io_write_byte) skyeye_config.mach->mach_io_write_byte(mstate, addr, data); else{ fprintf(stderr, "io_write_byte is not initializedin %s\n", __FUNCTION__); skyeye_exit(-1); } } void mips_io_write_halfword(UInt32 addr, UInt32 data) { if (skyeye_config.mach->mach_io_write_halfword) skyeye_config.mach->mach_io_write_halfword(mstate, addr, data); else{ fprintf(stderr, "io_write_halfword is not initializedin %s\n", __FUNCTION__); skyeye_exit(-1); } } void mips_io_write_word(UInt32 addr, UInt32 data) { if (skyeye_config.mach->mach_io_write_word) skyeye_config.mach->mach_io_write_word(mstate, addr, data); else{ fprintf(stderr, "io_write_word is not initializedin %s\n", __FUNCTION__); skyeye_exit(-1); } } void mips_io_write_doubleword(UInt32 addr, UInt32 data) { fprintf(stderr, "io_write_doubleword is not initializedin %s\n", __FUNCTION__); skyeye_exit(-1); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/inttypes.h��������������������������������������������������������0000644�0001750�0000144�00000006515�10600011124�017433� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _SKYEYE_MIPS_INTTYPES_H_ #define _SKYEYE_MIPS_INTTYPES_H_ #include <stdlib.h> #include "../../../utils/config/skyeye_types.h" /* This header defines a set of minimum-width integer types. There is no need * for fixed-width types, although in many places it may improve performance. * There are four minimum-width signed types Int8, Int16, Int32 and Int64, and * four corresponding unsigned types UInt8, UInt16, UInt32 and UInt64. * Currently, two models are supported, ANSI (use ANSI restrictions on types * up to 32 bit and some unportable 64 bit type) and SIM64 (32 bit integers * and 64 bit longs). The first is currently supported only on GCC and TenDRA * as well as any C99-compatible compilers. Note that all eight types MUST be * distinct, as they are frequently used in overload resolution. */ typedef signed char Int8; typedef unsigned char UInt8; typedef signed short Int16; typedef unsigned short UInt16; typedef signed int Int32; typedef unsigned int UInt32; typedef signed long long Int64; typedef unsigned long long UInt64; typedef UInt64 ClockValue; /* Useful multiplier suffixes */ #define KB 1024 #define MB 1024*KB #define GB 1024*MB #define TB 1024*GB /* Interfaces to ANSI # and ## preprocessing operators. The STR2() and * GLUE2() differ from STR() and GLUE() in that the later macro-expand the * arguments before applying the operator. */ #define STR2(x) #x #define STR(x) STR2(x) #define GLUE2(x,y) x##y #define GLUE(x,y) GLUE2(x, y) /* Two macros used to construct fixed-width constants from unsuffixed * literals. They serve two purposes: (1) to make it possible to define * portable 64 bit constants on 32 bit systems, and (2) to make huge constant * easier to read. */ #define C32(a,b) \ ((UInt32)((UInt32)GLUE2(0x,a) << 16 | (UInt32)GLUE2(0x,b))) #define C64(a,b,c,d) \ ((UInt64)((UInt64)(a) << 48 | (UInt64)(b) << 32 | \ (UInt64)(c) << 16 | (UInt64)(d))) #define is_power_of_two(x) \ ({ \ typeof((x)) _x = (x); \ ((x) & -(x)) == (x); \ }) #define round_down(x, size) (x & -(Int32)size) #define bitmask(n) ((UInt32)(1) << n) #define bitsmask(n, m) ((~(UInt32)0 ) >> (m) << (31 - (n) + (m)) >> (31 - (n))) #define bit(x, n) (((x) >> n) & 1) #define clear_bit(x, n) ((x) & ~bitmask(n)) #define set_bit(x, n) ((x) | bitmask(n)) #define bits(x, n, m) \ ({ \ UInt32 y = (x); \ y << (31 - (n)) >> (31 - (n) + (m)); \ }) #define clear_bits(x, n, m) ((x) & ~bitsmask((n), (m))) #define set_bits(x, n, m) ((x) | bitsmask((n), (m))) #define copy_bits(x, y, n, m) (clear_bits((x), (n), (m)) | (bits((y), ((n) - (m)), (int)0) << m)) #define zero_extend(x, n) (bits((x), (n) - 1, 0)) #define MulResult(x, y) \ {\ mstate->hi = (x);\ mstate->lo = (y);\ } #define multiply(a, b) \ {\ const int n = 8 * sizeof(typeof(a));\ UInt32 _x = (a), _y = (b);\ unsigned long long _z = _x * _y;\ MulResult(bits(_z, 2*n-1, n), bits(_z, n-1, 0));\ } #define DivResult(x,y) \ {\ mstate->lo = x;\ mstate->hi = y;\ } #define divide(a, b) \ {\ const size_t n = 8 * sizeof(typeof(a));\ if (n < sizeof(int)) {\ div_t r = div((int)(a), (int)(b));\ DivResult(r.quot, r.rem)\ }\ else if (n < sizeof(long)) {\ ldiv_t r = ldiv((long)(a), (long)(b));\ DivResult(r.quot, r.rem)\ }\ else {\ DivResult(a / b, a % b)\ }\ } #endif //end of _SKYEYE_MIPS_INTTYPES_H_ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/mipsdef.h���������������������������������������������������������0000644�0001750�0000144�00000002467�10541455476�017237� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _MIPSDEFS_H_ #define _MIPSDEFS_H_ #include <stdio.h> #include <stdlib.h> #include <errno.h> #include "inttypes.h" #define MAX_STR 1024 #define MAX_BANK 8 #define ROM_BANKS 16 typedef struct mips_mem_bank_s { UInt32 (*read_byte) (UInt32 addr); void (*write_byte) (UInt32 addr, UInt32 data); UInt32 (*read_halfword) (UInt32 addr); void (*write_halfword) (UInt32 addr, UInt32 data); UInt32 (*read_word) (UInt32 addr); void (*write_word) (UInt32 addr, UInt32 data); UInt64 (*read_doubleword) (UInt32 addr); //Maybe unusable for MIPS void (*write_doubleword) (UInt32 addr, UInt64 data); unsigned long addr, len; char filename[MAX_STR]; unsigned type; //chy 2003-09-21: maybe io,ram,rom }mips_mem_bank_t; typedef struct mips_mem_config_s { int bank_num; int current_num; //current num of bank mips_mem_bank_t mem_banks[MAX_BANK]; }mips_mem_config_t; typedef struct mips_mem_state_s { UInt32 *dram; UInt32 *rom[ROM_BANKS]; //Shi yang 2006-08-24 UInt32 rom_size[ROM_BANKS]; //teawater add for arm2x86 2004.12.04------------------------------------------- UInt8 *tbp[ROM_BANKS]; //translate block pointer struct tb_s *tbt[ROM_BANKS]; //translate block structure pointer //AJ2D-------------------------------------------------------------------------- }mips_mem_state_t; #endif //end of _MIPSDEF_H_ ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/dcache.c����������������������������������������������������������0000644�0001750�0000144�00000022257�10643717416�017007� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "emul.h" #include "stdio.h" // WARNING: currently, the memory access latencies are not simulated. // WARNING: currently, the effect of write buffers isn't simulated. // State information for the data cache. #define W_FLAG 1 #define CS_First 1 #define CS_Last 2 // Cache states -- unused on R4600/R4700, but needed for control_dcache(). #define CS_Invalid (0 << CS_First) #define CS_Shared (1 << CS_Last) #define CS_CleanExclusive (2 << CS_Last) #define CS_DirtyExclusive (3 << CS_Last) // Reset the L1 data cache. void reset_dcache(MIPS_State* mstate) { int i, j; for (i = 0; i < Dcache_sets; ++i) { for (j = 0; j < Dcache_assoc; ++j) { mstate->dcache.set[i].line[j].tag = bad_tag; mstate->dcache.set[i].line[j].state = CS_Invalid; //dcache.set[i].lru_init(); Dcache_lru_init(mstate->dcache.set[i].Dcache_lru); } } } // Perform a cache operation (for use by decode_cache()). void control_dcache(MIPS_State* mstate, VA va, PA pa, int op, int type) { if (type) return; // secondary cache not presents switch (op) { case 0: { // Index Writeback Invalidate. MIPSDCacheSet* set=&mstate->dcache.set[Dcache_index(va)]; MIPSDCacheLine*line=&set->line[Dcache_block(va)]; if (line->state & W_FLAG) { PA pa = (Dcache_index(va) << Dcache_index_first) | (line->tag << (Dcache_index_last + 1)); int j; for(j = 0; j < 4; j++) mips_mem_write(pa+8*j , line->data+j, 8); line->tag = bad_tag; line->state = CS_Invalid; } break; } case 1: { /* Index Load Tag. This cannot be implemented properly as I don't * store the tag for invalidated entries. */ break; } case 2: { /* Index Store Tag. The comment from (1) applies. As ``Index Load * Tag'' is not implemented, this may be left as a noop. */ break; } case 3: { // Create Dirty Exclusive. UInt32 tag = Dcache_tag(pa); MIPSDCacheSet* set= &mstate->dcache.set[Dcache_index(va)]; MIPSDCacheLine* line=&set->line[Dcache_block(va)]; if (line->tag != tag && (line->state & W_FLAG)) { // Write back current data. PA pa = (Dcache_index(va) << Dcache_index_first) |(line->tag << (Dcache_index_last + 1)); int j; for(j = 0; j < 4; j++) mips_mem_write(pa + 8 * j , line->data + j, 8); } line->tag = tag; line->state = CS_DirtyExclusive | (line->state & W_FLAG); break; } case 4: { // Hit Invalidate. UInt32 tag = Dcache_tag(pa); MIPSDCacheSet* set = &mstate->dcache.set[Dcache_index(va)]; MIPSDCacheLine* line=&set->line[Dcache_block(va)]; if (line->tag != tag && (line->state & W_FLAG)) { // Hit: invalidate the cache. line->tag = bad_tag; line->state = CS_Invalid; } else { // Miss: clear the CH bit in status register. } break; } case 5: { // Hit Writeback Invalidate. UInt32 tag = Dcache_tag(pa); MIPSDCacheSet* set = &mstate->dcache.set[Dcache_index(va)]; MIPSDCacheLine* line=&set->line[Dcache_block(va)]; if (line->tag == tag && (line->state & W_FLAG)) { PA pa = (Dcache_index(va) << Dcache_index_first) |(line->tag << (Dcache_index_last + 1)); int j; for (j = 0; j < 4; j++) mips_mem_write(pa + 8 * j , line->data + j, 8); } line->tag = bad_tag; line->state = CS_Invalid; break; } case 6: { // Hit Writeback. UInt32 tag = Dcache_tag(pa); MIPSDCacheSet* set = &mstate->dcache.set[Dcache_index(va)]; MIPSDCacheLine* line=&set->line[Dcache_block(va)]; if (line->tag == tag && (line->state & W_FLAG)) { // Write back current data. PA pa = (Dcache_index(va) << Dcache_index_first) | (line->tag << (Dcache_index_last + 1)); int j; for (j = 0; j < 4; j++) mips_mem_write(pa+8*j , line->data+j, 8); } line->tag = bad_tag; break; } case 7: // Hit Set Virtual. break; // secondary cache not present } } /* Perform a load from the virtual address (va). The address translation has * already been performed and the physical address is (pa). The coherency * algorithm to use is encoded in high-order bits of (pa) using the same * encoding as that of the xkphys address space region. It is a template * explicitely specialized for doubleword, word, halfword and byte, to improve * performance of the endianess correction algorithm, as well as minor * improvements steming from the fact that bit field extraction on variable * boundaries is slow. */ #if 0 void load(MIPS_State* mstate, VA va, PA pa, UInt32* x, int size) { // to generate the time out interrupt UInt32 addr = bits(pa, 31, 0); int i; int ca = coherency_algorithm(pa); if (ca == 0x5) { //Shi yang 2006-08-15 // A direct memory access. mips_mem_read(pa, x, size); return; } // A cached memory access. UInt32 index = Dcache_index(pa); //Shi yang 2006-08-15 UInt32 tag = Dcache_tag(pa); MIPSDCacheSet* set = &(mstate->dcache.set[index]); MIPSDCacheLine* line = &(set->line[0]); const PA line_mask = Dcache_line_size - 1; int j; for (j = 0; j < Dcache_assoc; ++j, ++line) { if (line->tag == tag) { Dcache_lru_touch(set->Dcache_lru,j); goto cache_hit; } } i = Dcache_lru_replace(mstate->dcache.set[index].Dcache_lru); line = &(mstate->dcache.set[index].line[i]); // Shi yang 2006-08-15 R3000's cache is write through cache. for(j = 0; j < 4; j++) mips_mem_read((pa & ~line_mask) + 8 * j , line->data + j, 8); line->tag = tag; Dcache_lru_touch(set->Dcache_lru, i); int offset; UInt32 cachelinedata; cachelinedata = line->data[(pa & line_mask) / 8]; cache_hit: /* Finally, fetch the data from the cache. * return swizzle<syscmd>(line->data[(pa & line_mask) / 8], va); */ switch (size) { case 1: { offset = (((UInt32) mstate->bigendSig * 3) ^ (va & 3)) << 3; //Shi yang 2006-08-18 *x = (cachelinedata >> offset) & 0xffL; break; } case 2: { offset = (((UInt32)mstate->bigendSig * 2) ^ (va & 2)) << 3; //Shi yang 2006-08-18 *x = (cachelinedata >> offset) & 0xffffL; break; } case 4: { *x = cachelinedata; break; } } } #endif void load(MIPS_State* mstate, VA va, PA pa, UInt32* x, int size) { // to generate the time out interrupt UInt32 addr = bits(pa, 31, 0); int i; // A direct memory access. return mips_mem_read(pa, x, size); } /* Store data to the virtual address (va). The address translation has already * been performed and the physical address is (pa). The coherency algorithm to * use is encoded in high-order bits of (pa) using the same encoding as that * of the xkphys address space region. It is a template explicitely * specialized for doubleword, word, halfword and byte, to improve performance * of the endianess correction algorithm, as well as minor improvements * steming from the fact that bit field extraction on variable boundaries is * slow. */ #if 0 void store(MIPS_State* mstate, UInt32 data, VA va, PA pa, int size) { UInt32 addr=bits(pa, 31, 0); UInt32 x = data; int ca = coherency_algorithm(pa); // Anthony Lee 2007-01-30 : no {} ??? if (ca == 0x5) //Shi yang uncached area mips_mem_write(pa, &data, size); return; //Shi yang 2006-08-28 // A cached memory access. UInt32 index = Dcache_index(pa); //Shi yang 2006-08-15 UInt32 tag = Dcache_tag(pa); MIPSDCacheSet* set = &(mstate->dcache.set[index]); MIPSDCacheLine* line = &(set->line[0]); const PA line_mask = Dcache_line_size - 1; int j; for (j = 0; j < Dcache_assoc; ++j, ++line) { if (line->tag == tag) { Dcache_lru_touch(set->Dcache_lru, j); goto cache_hit; } } int i; i = Dcache_lru_replace(mstate->dcache.set[index].Dcache_lru); //Replace cache line line = &(mstate->dcache.set[index].line[i]); line->tag = tag; Dcache_lru_touch(set->Dcache_lru, i); int offset; UInt32* cachelinedata; //Shi yang 2006-08-15 cachelinedata = &(line->data[(pa & line_mask) / 8]); cache_hit: /* Finally, fetch the data from the cache. * return swizzle<syscmd>(line->data[(pa & line_mask) / 8], va); */ switch (size) { case 1: { offset = (((UInt32) mstate->bigendSig * 3) ^ (va & 3)) << 3; //Shi yang 2006-08-18 *cachelinedata = clear_bits(*cachelinedata, offset, 0) | (x & 0xffL); //Shi yang 2006-08-15 Write cache line mips_mem_write(pa, &data, size); //Write memory break; } case 2: { offset = (((UInt32)mstate->bigendSig * 2) ^ (va & 2)) << 3; //Shi yang 2006-08-18 *cachelinedata = clear_bits(*cachelinedata, offset, 0) | (x & 0xffffL); mips_mem_write(pa, &data, size); break; } case 4: { *x = cachelinedata; mips_mem_write(pa, &data, size); break; } } } #endif /* * simple implementation for store function written by michael.kang */ void store(MIPS_State* mstate, UInt32 data, VA va, PA pa, int size) { UInt32 addr=bits(pa, 31, 0); UInt32 x = data; return mips_mem_write(pa, &data, size); } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/exception.c�������������������������������������������������������0000644�0001750�0000144�00000006204�11006337414�017556� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "emul.h" #include <stdio.h> /* Exception processing functions. Before handling the exception, these * functions check for a higher- priority exception occuring elsewhere in the * pipeline, and handle those instead if necessary. * Process a reset, soft reset and nmi exceptions as specified by the (events) * field. These are the highest-priority exceptions handled in the D pipeline * stage, so handling them is fairly easy. * * Where (sr) is cleared for a cold reset and set otherwise. * For both cold and soft reset, the caches and the TLB are also reset. * WARNING: Because resets and interrupts are detected in the D pipeline * stage, one instruction should complete before they are detected and the * interrupt is taken. This effect is currently NOT simulated: it is unlikely * that the detail will cause any problems as interrupts are typically driven * by a clock many times slower than the pipeline anyway. The same effect can * also be achieved by scheduling the interrupts one cycle after the actual * event time (for example, by ignoring the fact that the events are guranteed * to be invoked *after* the scheduled time.) */ void process_reset(MIPS_State* mstate) { mstate->now += 5; if (mstate->events & cold_reset_event) { mstate->cp0[Random] = tlb_size - 1; mstate->random_seed = mstate->now; reset_icache(mstate); reset_dcache(mstate); reset_tlb(mstate); } mstate->cp0[SR] = set_bit(mstate->cp0[SR], SR_BEV); mstate->pc = reset_vector_base + reset_vector; mstate->pipeline = nothing_special; enter_kernel_mode(mstate); mstate->events = 0; } /* Process a general exception. * * Because the IP field in the Cause register is actually stored in the * (events) word, Cause may be set directly to the exception code, adjusted * for exceptions in a branch-delay slot. Any additional changes to the * machine state are handled in inline wrappers on process_exception() (see * "koala.hh".) Exceptions are serviced when the corresponding instruction * enters the W pipeline stage: at this stage. Hence, there are always * exactly five dead clock cycles after an exception: these are simulated * simply by incrementing the clock by five. */ void process_exception(MIPS_State* mstate, UInt32 cause, int vec) { //fprintf(stderr, "KSDBG:in %s, vec=0x%x, cause=0x%x, ,v0=0x%x, pc=0x%x\n", __FUNCTION__, vec, cause, mstate->gpr[2], mstate->pc); mstate->now += 5; VA epc; if (!branch_delay_slot(mstate)) epc = mstate->pc; else { epc = mstate->pc - 4; cause = set_bit(cause, Cause_BD); } /* Set ExcCode to zero in Cause register */ mstate->cp0[Cause] &= 0xFFFFFF83; mstate->cp0[Cause] |= cause; if((cause == EXC_Sys) || (cause == EXC_TLBL) || (cause == EXC_TLBS)){ mstate->pipeline = branch_nodelay; } else{ mstate->pipeline = nothing_special; } mstate->cp0[EPC] = epc; mstate->pc = vec + (bit(mstate->cp0[SR], SR_BEV) ? general_vector_base : boot_vector_base); /* set EXL to one */ mstate->cp0[SR] |= 0x2; enter_kernel_mode(mstate); //fprintf(stderr, "End of %s,sr=0x%x,cause=0x%x\n", __FUNCTION__, mstate->cp0[SR], mstate->cp0[Cause]); } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/instr.h�����������������������������������������������������������0000644�0001750�0000144�00000017664�11006337414�016740� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _INSTR_H_ #define _INSTR_H_ #include "inttypes.h" // Instruction decoder functions. /* I-Type (Immediate) */ #define opcode(instr) bits(instr, 31, 26) #define rs(instr) bits(instr, 25, 21) #define rt(instr) bits(instr, 20, 16) #define sel(instr) bits(instr, 2, 0) //#define rd(instr) bits(instr, 15, 11) #define immediate(instr) bits(instr, 15, 0) // Some aliases for the above. #define base(instr) bits(instr, 25, 21) #define offset(instr) bits(instr, 15, 0) /* J-Type (Jump) */ #define target(instr) bits(instr, 25, 0) /* R-Type (Register) */ #define rd(instr) bits(instr, 15, 11) #define shamt(instr) bits(instr, 10, 6) #define funct(instr) bits(instr, 5, 0) /* COP1 (Floating Point) */ #define fmt(instr) bits(instr, 25, 21) #define ft(instr) bits(instr, 20, 16) #define fs(instr) bits(instr, 15, 11) #define fd(instr) bits(instr, 10, 6) #define function(instr) bits(instr, 5, 0) #define cond(instr) bits(instr, 3, 0) /* COPz (Coprocessor) */ #define cofun(instr) bits(instr, 24, 0) /* The (op) field */ #define SPECIAL 000 #define REGIMM 001 #define J 002 #define JAL 003 #define BEQ 004 #define BNE 005 #define BLEZ 006 #define BGTZ 007 #define ADDI 010 #define ADDIU 011 #define SLTI 012 #define SLTIU 013 #define ANDI 014 #define ORI 015 #define XORI 016 #define LUI 017 #define COP0 020 #define COP1 021 #define COP2 022 // reserved = 023, #define BEQL 024 #define BNEL 025 #define BLEZL 026 #define BGTZL 027 #define DADDI 030 #define DADDIU 031 #define LDL 032 #define LDR 033 #define SPECIAL2 034 // reserved = 034, // reserved = 035, // reserved = 036, // reserved = 037, #define LB 040 #define LH 041 #define LWL 042 #define LW 043 #define LBU 044 #define LHU 045 #define LWR 046 #define LWU 047 #define SB 050 #define SH 051 #define SWL 052 #define SW 053 #define SDL 054 #define SDR 055 #define SWR 056 #define CACHE 057 #define LL 060 #define LWC1 061 #define LWC2 062 #define PREF 063 // reserved = 063, #define LLD 064 #define LDC1 065 #define LDC2 066 #define LD 067 #define SC 070 #define SWC1 071 #define SWC2 072 // reserved = 073, #define SCD 074 #define SDC1 075 #define SDC2 076 #define SD 077 /* The (function) field when (op == SPECIAL) */ #define SLL 000 // reserved = 001, #define SRL 002 #define SRA 003 #define SLLV 004 // reserved = 005, #define SRLV 006 #define SRAV 007 #define JR 010 #define JALR 011 #define MOVZ 012 #define MOVN 013 // reserved = 012, // reserved = 013, #define SYSCALL 014 #define BREAK 015 // reserved = 016, #define SYNC 017 #define MFHI 020 #define MTHI 021 #define MFLO 022 #define MTLO 023 #define DSLLV 024 // reserved = 025, #define DSRLV 026 #define DSRAV 027 #define MULT 030 #define MULTU 031 #define DIV 032 #define DIVU 033 #define DMULT 034 #define DMULTU 035 #define DDIV 036 #define DDIVU 037 #define ADD 040 #define ADDU 041 #define SUB 042 #define SUBU 043 #define AND 044 #define OR 045 #define XOR 046 #define NOR 047 // reserved = 050, // reserved = 051, #define SLT 052 #define SLTU 053 #define DADD 054 #define DADDU 055 #define DSUB 056 #define DSUBU 057 #define TGE 060 #define TGEU 061 #define TLT 062 #define TLTU 063 #define TEQ 064 // reserved = 065, #define TNE 066 // reserved = 067, #define DSLL 070 // reserved = 071, #define DSRL 072 #define DSRA 073 #define DSLL32 074 // reserved = 075, #define DSRL32 076 #define DSRA32 077 /* The (rt) field when (op == REGIMM) */ #define BLTZ 000 #define BGEZ 001 #define BLTZL 002 #define BGEZL 003 // reserved = 004, // reserved = 005, // reserved = 006, // reserved = 007, #define TGEI 010 #define TGEIU 011 #define TLTI 012 #define TLTIU 013 #define TEQI 014 // reserved = 015, #define TNEI 016 // reserved = 017, #define BLTZAL 020 #define BGEZAL 021 #define BLTZALL 022 #define BGEZALL 023 // reserved = 024, // reserved = 025, // reserved = 026, // reserved = 027, // reserved = 030, // reserved = 031, // reserved = 032, // reserved = 033, // reserved = 034, // reserved = 035, // reserved = 036, // reserved = 037 /* The (rs) field of COPz rs instructions */ #define MFCz 000 #define DMFCz 001 #define CFCz 002 // reserved = 003, #define MTCz 004 #define DMTCz 005 #define CTCz 006 // reserved = 007, #define BCz 010 /* The (rt) field of COPz rt instructions */ #define BCzF 000 #define BCzT 001 #define BCzFL 002 #define BCzTL 003 /* CP0 (function) field */ #define TLBR 001 #define TLBWI 002 #define TLBWR 006 #define TLBP 010 #define RFE 020 //Shi yang 2006-08-08 #define ERET 030 #define WAIT 040 /* The (function) field */ #define MADD 000 #define FADD 000 #define FSUB 001 #define FMUL 002 #define FDIV 003 #define SQRT 004 #define ABS 005 #define MOV 006 #define NEG 007 #define ROUND_L 010 #define TRUNC_L 011 #define CEIL_L 012 #define FLOOR_L 013 #define ROUND_W 014 #define TRUNC_W 015 #define CEIL_W 016 #define FLOOR_W 017 // reserved = 020, // reserved = 021, // reserved = 022, // reserved = 023, // reserved = 024, // reserved = 025, // reserved = 026, // reserved = 027, // reserved = 030, // reserved = 031, // reserved = 032, // reserved = 033, // reserved = 034, // reserved = 035, // reserved = 036, // reserved = 037, #define CVT_S 040 #define CVT_D 041 // reserved = 042, // reserved = 043, #define CVT_W 044 #define CVT_L 045 // reserved = 046, // reserved = 047, // reserved = 050, // reserved = 051, // reserved = 052, // reserved = 053, // reserved = 054, // reserved = 055, // reserved = 056, // reserved = 057, #define C_F 060 #define C_UN 061 #define C_EQ 062 #define C_UEQ 063 #define C_OLT 064 #define C_ULT 065 #define C_OLE 066 #define C_ULE 067 #define C_SF 070 #define C_NGLE 071 #define C_SEQ 072 #define C_NGL 073 #define C_LT 074 #define C_NGE 075 #define C_LE 076 #define C_NGT 077 /* The (mt) field */ // 0-15 // Reserved #define S 16 // IEEE 754 single-precision floating-point #define D 17 // IEEE 754 double-precision floating-point // 18-19 // Reserved #define W 20 // 32-bit binary fixed-point #define L 21 // 64-bit binary fixed-point // 22-31 // Reserved /* The floating-point condition codes */ #define unordered 0 #define equal 1 #define less 2 #define signalling 3 #define CF 2 #endif //end of _INSTR_H_ ����������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/multiply.c��������������������������������������������������������0000644�0001750�0000144�00000002627�10541455476�017460� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "emul.h" // Perform long multiplication of x by y. extern MIPS_State * mstate; void multiply_UInt64(UInt64 u, UInt64 v) { UInt64 u0 = bits(u, 31, 0); UInt64 u1 = bits(u, 63, 32); UInt64 v0 = bits(v, 31, 0); UInt64 v1 = bits(v, 63, 32); UInt64 w0 = 0; UInt64 w1 = 0; UInt64 w2; UInt64 w3; UInt64 t, k; k = 0; // i == 0, j == 0 t = u0 * v0 + w0 + k; w0 = bits(t, 31, 0); k = bits(t, 63, 32); // i == 1, j == 0 t = u1 * v0 + w1 + k; w1 = bits(t, 31, 0); k = bits(t, 63, 32); w2 = k; k = 0; // i == 0, j == 1 t = u0 * v1 + w1 + k; w1 = bits(t, 31, 0); k = bits(t, 63, 32); // j == 1, i == 1 t = u1 * v1 + w2 + k; w2 = bits(t, 31, 0); k = bits(t, 63, 32); w3 = k; // Glue the bits back into full words. mstate->lo = w0 | (w1 << 32); mstate->hi = w2 | (w3 << 32); } void multiply_Int64(Int64 u, Int64 v) { // Compute the sign of the result; int neg; if (u < 0) { if (v < 0) { neg =0; v = -v; } else { neg = 1; } u = -u; } else { if (v < 0) { neg = 1; v = -v; } else { neg =0; } } multiply_UInt64((UInt64)u, (UInt64)v); if (neg) { mstate->lo = ~mstate->lo; mstate->hi = ~mstate->hi; if (++mstate->lo == 0) { ++mstate->hi; } } } ���������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/emul.h������������������������������������������������������������0000644�0001750�0000144�00000021655�11006337414�016536� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _EMUL_H_ #define _EMUL_H_ #include "cache.h" #include "cpu.h" /* 16 bit implementation and revision fields. The upper 8 bits are 0x20 * for R3000. The lower 8 bits should distinguish the * simulator. */ #define ImpRev 0x2070 /* Some instruction latencies. These are for R4600. On R4700, both all * four multiplication latencies are decreased by four cycles. */ #define mult_latency 10 #define multu_latency 10 #define div_latency 42 #define divu_latency 42 #define dmult_latency 12 #define dmultu_latency 12 #define ddiv_latency 74 #define ddivu_latency 74 /* Asynchronous event constants. Each interrupt source corresponds to a * single bit of the (events) word. Bits 8 through 16 correspond to * interrupts 0 through 7. Other bits represent the three reset exceptions * as follows: */ #define cold_reset_event (1 << 0) #define soft_reset_event (1 << 1) #define nmi_event (1 << 2) /* Cache of some strategic CPU mode bits. This shortcut is used to avoid * parsing of the somewhat convoluted Status register during address * translation and instruction decoding. */ #define xmode (1 << 0) // 64 bit mode ([USK]X & [usk]mode) #define cmode (1 << 1) // 32 bit (compatibility) mode (!xmode) #define bmode (1 << 2) // big-endian-cpu (big_endian_mem() ^ reverse_endian()) #define rmode (1 << 3) // reverse-endian (RE && umode) #define umode (1 << 4) // user mode #define smode (1 << 5) // supervisor mode #define kmode (1 << 6) // kernel mode /* Pipeline information. This is fairly ad hoc, but it is still useful */ #define nothing_special 0 // nothing special #define branch_delay 1 // current instruction in the branch-delay slot #define instr_addr_error 2 // instruction address error #define branch_nodelay 3 // syscall instruction or eret instruction /* Coprocessor 1 (FPU) simulator */ //static const char* condname[16]; #define FCR0 0 #define FP_Rev_Last 7 #define FP_Rev_First 0 #define FP_Imp_Last 15 #define FP_Imp_First 8 #define FCR31 31 #define FP_RM_Last 1 #define FP_RM_First 0 #define FP_Flag_Last 6 #define FP_Flag_First 2 #define FP_Enable_Last 11 #define FP_Enable_First 7 #define FP_Cause_Last 17 #define FP_Cause_First 12 #define FP_C 23 #define FP_FS 24 /* Software IEC/IEEE floating-point rounding mode */ #define float_round_nearest_even 0 #define float_round_to_zero 1 #define float_round_up 2 #define float_round_down 3 /* Software IEC/IEEE floating-point exception flags */ #define float_flag_inexact 1 #define float_flag_underflow 2 #define float_flag_overflow 4 #define float_flag_divbyzero 8 #define float_flag_invalid 16 #define float_flag_unimplemented 32 /* An invalid ASID bit used to mark unused TLB entries */ #define invalid_asid (1 << 6) //Shi yang 2006-08-08 /* An global ASID bit */ #define global_asid (1 << 6) //Shi yang 2006-08-08 /* Geometry of the TLB lookup map (see below.) */ #define log2_tlb_map_size 6 //Shi yang 2006-08-08 #define tlb_map_size (1 << log2_tlb_map_size) /* An invalid cache tag used to mark unused cache lines */ #define bad_tag ~(UInt32)0 /* An invalid ibuf tag used to marked unused icache buffers */ #define bad_ibuf_tag ~(VA)0 /* An invalid physical address returned by translate_vaddr() on cache * operations that specify an invalid address. */ #define bad_pa ~(PA)0 /* TLB access types, used to select the appropriate TLB miss handler */ #define instr_fetch 0 //instruction fetch #define data_load 1 //data load #define data_store 2 //data store #define cache_op 3 //cache operations (ignore errors) #define no_tracing 0 #define report_interrupts 1 #define report_exceptions 2 #define print_instructions 3 #define dump_gprs 4 /* The NOP guard */ #define catch_nops 128 /* if return 0, translate * 0 means find the correct PA * 1 means some TLB exception happened */ #define TLB_FAIL -1 #define TLB_SUCC 0 #define TLB_EXP 1 /* A TLB Entry structure */ typedef struct TLBEntry_s { struct TLBEntry_s* next; // the hash chain struct TLBEntry_s* prev; // the hash chain UInt16 page_mask; UInt32 hi; // VPN << 12 UInt32 lo_reg[2]; // EntryLo0 Int16 asid; // the ASID, sign bit set for global entries. UInt16 index; // TLB index UInt16 hash; // TLB map index }TLBEntry; /* The two-entry ITLB. Each entry maps a 4KB page */ typedef struct ITLBEntry_s { VA vpn; // virtual address page number (va / 4KB) PA pa; // physical address and the caching algorithm Int16 asid; // ASID and the global bit. }ITLBEntry; /* Although not in real hardware, we also cache the two most recent * I-cache accesses, as simulating cache lookups is slow, and as many as 8 * instructions can be fetched from one cache line. */ typedef struct ICacheBuffer_s { VA tag; // address of the cache shifted by log2_icache_line UInt32* line; // pointer to the ICache line. }ICacheBuffer; typedef struct MIPS_State_s{ // The register set. VA pc; // Program Counter UInt32 gpr[32]; // General Purpose Registers UInt32 fpr[32]; // Floating-Point General Purpose Registers UInt32 fir,fcsr; // Floating-point implementation register and control-status register UInt32 cp0[32]; // CP0 Registers UInt32 cp0_config1; UInt32 cp1[32]; // CP1 Registers UInt32 hi, lo; // Multiply and Divide Registers int ll_bit; // The Load-Linked Bit ClockValue now; int warm; //flag:warm_reset or cold_reset int nop_count; //nop instruction count // CPU state. Int16 asid; // same as the ASID field in EntryHi UInt16 events; // external events: this also replaces Cause[15:8]. UInt8 pipeline; // current instruction in the branch-delay slot UInt8 mode; // CPU mode int sync_bit; // true after executing the SYNC instruction. VA branch_target; // next PC when in the branch delay slot /* cp0[Random] is not updated on each clock cycle. Instead, its value is * updated when either cp0[Random] or cp0[Wired] is set, and the current * value is computed using the time elapsed since then. */ ClockValue random_seed; // Similary, we lazily compute the value of the Count register. ClockValue count_seed; // ITLB data. (lru_itlb) stores the index of the least-recently used entry. ITLBEntry itlb[2]; int lru_itlb; /* I-cache buffer data (lru_ibuf) stores the index of the least-recently * used entry (0 or 1). */ ICacheBuffer ibuf[2]; int lru_ibuf; int env; //The longjmp buffer used for handling exceptions. /* The TLB and L1 caches */ TLBEntry tlb[tlb_size]; ICache icache; DCache dcache; /* The TLB map used to simulate the direct-mapped TLB lookup. There's an * extra entry at the end that contains the hash chain of all unused TLB * entries (that way, there is always exactly (tlb_size) mappings in the * hash table). */ TLBEntry* tlb_map[tlb_map_size + 1]; int trace_level; // Finally, some configuration data. struct conf_t{ char* bus; int ec; char* ep; int be; int trace; } conf; unsigned bigendSig; int irq_pending; }MIPS_State; void reset(int warm); /* Interrupt delivery functions */ void deliver_cold_reset(MIPS_State* mstate); void deliver_soft_reset(MIPS_State* mstate); /* TLB operations */ void reset_tlb(MIPS_State* mstate); void dump_tlb(); TLBEntry* probe_tlb(MIPS_State* mstate, VA va); void set_tlb_entry(MIPS_State* mstate, int index); int translate_vaddr(MIPS_State* mstate, VA va, int type, PA *pa); /* Instruction cache operations */ void reset_icache(MIPS_State* mstate); void control_icache(MIPS_State* mstate, VA va, PA pa, int op, int type); Instr fetch(MIPS_State* mstate, VA va, PA pa); /* Data cache operations*/ void reset_dcache(MIPS_State* mstate); void control_dcache(MIPS_State* mstate, VA va, PA pa, int op, int type); UInt32 load_left(UInt32 x, VA va, int syscmd); // LDL, LWL UInt32 load_right(UInt32 x, VA va, int syscmd); // LDR, LWR void store_left(UInt32 x, VA va, int syscmd); // SDL, SWL void store_right(UInt32 x, VA va, int syscmd); // SDR, SWR /* Complete any pending memory operations */ //void sync(); void process_reset(MIPS_State* mstate); void process_exception(MIPS_State* mstate, UInt32 cause, int vec); /* Set the Coprocessor 0 timer interrupt */ void set_timer(); /* Coprocessor 0 register access. This is necessary as some registers * are computed on demand, and most registers have some read-only fields. */ UInt32 read_cp0(MIPS_State* mstate, int n, int sel) ; void write_cp0(MIPS_State* mstate, int n, UInt32 x); /* The main instruction decoder with satelite functions for some of the * more elaborate instructions. */ int decode(MIPS_State* mstate, Instr instr); int decode_cop0(MIPS_State* mstate, Instr instr); int decode_cop1(MIPS_State* mstate, Instr instr); int decode_cache(MIPS_State* mstate, Instr instr); int decode_ldc1(MIPS_State* mstate, Instr instr); int decode_lwc1(MIPS_State* mstate, Instr instr); int decode_sdc1(MIPS_State* mstate, Instr instr); int decode_swc1(MIPS_State* mstate, Instr instr); /* Some debugging help */ void dump_gpr_registers() ; void dump_fpr_registers() ; #endif //end of _EMUL_H__ �����������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/mips_arch_interface.c���������������������������������������������0000644�0001750�0000144�00000037720�11006337414�021554� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* Simulator for MIPS R3000 architecture. THIS SOFTWARE IS NOT COPYRIGHTED Cygnus offers the following for use in the public domain. Cygnus makes no warranty with regard to the software or it's performance and the user accepts the software "AS IS" with all faults. CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ #include "skyeye_config.h" #include "emul.h" #include <stdlib.h> #include "mipsdef.h" #include <stdio.h> MIPS_State* mstate; static char *arch_name = "mips"; mips_mem_config_t mips_mem_config; extern mips_mem_state_t mips_mem; extern FILE *skyeye_logfd; extern int trace_level; extern UInt8* mem_bunks; extern void mips_mem_reset (); extern UInt32 mips_real_read_byte (UInt32 addr); extern UInt32 mips_real_read_halfword (UInt32 addr); extern UInt32 mips_real_read_word (UInt32 addr); extern UInt64 mips_real_read_doubleword (UInt32 addr); extern void mips_real_write_byte (UInt32 addr, UInt32 data); extern void mips_real_write_halfword ( UInt32 addr, UInt32 data); extern void mips_real_write_word ( UInt32 addr, UInt32 data); extern void mips_real_write_doubleword ( UInt32 addr, UInt64 data); //IO address space extern UInt32 mips_io_read_byte (UInt32 addr); extern UInt32 mips_io_read_halfword (UInt32 addr); extern UInt32 mips_io_read_word (UInt32 addr); extern UInt64 mips_io_read_doubleword (UInt32 addr); extern void mips_io_write_byte (UInt32 addr, UInt32 data); extern void mips_io_write_halfword (UInt32 addr, UInt32 data); extern void mips_io_write_word (UInt32 addr, UInt32 data); extern void mips_io_write_doubleword (UInt32 addr, UInt64 data); //Flash address space extern UInt32 mips_flash_read_byte (UInt32 addr); extern UInt32 mips_flash_read_halfword (UInt32 addr); extern UInt32 mips_flash_read_word (UInt32 addr); extern UInt64 mips_flash_read_doubleword ( UInt32 addr); extern void mips_flash_write_byte (UInt32 addr, UInt32 data); extern void mips_flash_write_halfword (UInt32 addr, UInt32 data); extern void mips_flash_write_word (UInt32 addr, UInt32 data); extern void mips_flash_write_doubleword (UInt32 addr, UInt64 data); extern void mips_warn_write_byte (UInt32 addr, UInt32 data); extern void mips_warn_write_halfword (UInt32 addr, UInt32 data); extern void mips_warn_write_word (UInt32 addr, UInt32 data); extern mips_mem_bank_t* mips_bank_ptr (UInt32 addr); extern void mips_mem_write_byte (UInt32 phys_addr, UInt32 v); extern void mips_mem_write_halfword (UInt32 phys_addr, UInt32 v); extern void mips_mem_write_word (UInt32 phys_addr, UInt32 v); extern void mips_mem_write_doubleword (UInt64 phys_addr, UInt64 v); extern UInt32 mips_mem_read_byte (UInt32 phys_addr); extern UInt32 mips_mem_read_halfword (UInt32 phys_addr); extern UInt32 mips_mem_read_word (UInt32 phys_addr); extern UInt64 mips_mem_read_doubleword (UInt64 phys_addr); extern void mipsMul_WriteByte (MIPS_State* mstate, UInt32 vir_addr, UInt32 v); extern void mips_mmu_write_byte (MIPS_State* mstate, UInt32 vir_addr, UInt32 v); //chy 20060717 int SKYPRINTF(char * fmt,...) { return 0; } void mips_init_set(UInt32 addr, UInt8 value, int size) { } void mips_mem_read(UInt32 pa, UInt32 *data, int len) { /* if pa is located at kseg0 */ if(pa >= 0x80000000 && pa < 0xA0000000) pa = pa & ~0x80000000; /* if pa is located at kseg1 */ if(pa >= 0xA0000000 && pa < 0xC0000000) pa = pa & ~0xE0000000; //if(pa >= 0x14a1a0 && pa <= 0x14c000) // printf("###############read addr pa=0x%x,pc=0x%x\n", pa, mstate->pc); switch(len) { case 1: { *data = mips_mem_read_byte(pa); break; } case 2: { *data = mips_mem_read_halfword(pa); break; } case 4: { *data = mips_mem_read_word(pa); break; } default: break; } } void mips_mem_write(UInt32 pa, const UInt32* data, int len) { /* if pa is located at kseg0 */ if(pa >= 0x80000000 && pa < 0xA0000000) pa = pa & ~0x80000000; /* if pa is located at kseg1 */ if(pa >= 0xA0000000 && pa < 0xC0000000) pa = pa & ~0xE0000000; UInt32 addr = bits(pa, 31, 0); if(pa >= 0x14a1a0 && pa <= 0x14c000) printf("###############write addr pa=0x%x,pc=0x%x\n", addr, mstate->pc); switch(len) { case 1: { mips_mem_write_byte(pa, *data); break; } case 2: { mips_mem_write_halfword(pa, *data); break; } case 4: { mips_mem_write_word(pa, *data); break; } default: fprintf(stderr, "unimplemented write for size %d in %s\n", len, __FUNCTION__); break; } return; } static void init_icache() { int i; for(i = 0; i < Icache_log2_sets; i++) { Icache_lru_init(mstate->icache.set[i].Icache_lru); } } static void init_dcache() { int i; for(i = 0; i < Dcache_log2_sets; i++) { Dcache_lru_init(mstate->dcache.set[i].Dcache_lru); } } static void init_tlb() { int i; for(i = 0;i < tlb_map_size + 1; i++) { mstate->tlb_map[i] = NULL; } } static void mips_init_state() { set_bit(mstate->mode, 2); mstate = (MIPS_State* )malloc(sizeof(MIPS_State)); if (!mstate) { fprintf (stderr, "malloc error!\n"); skyeye_exit (-1); } mstate->warm = 0; mstate->conf.ec = 4; //I don't know what should it be. // set the little endian as the default mstate->bigendSig = 0; //Shi yang 2006-08-18 //No interrupt mstate->irq_pending = 0; mstate->cp0[SR] = 0x40004; init_icache(); init_dcache(); init_tlb(); /* mach init */ if(skyeye_config.mach->mach_init) skyeye_config.mach->mach_init (mstate, skyeye_config.mach); else{ fprintf(stderr, "skyeye arch is not initializd correctly.\n"); skyeye_exit(-1); } } static void mips_reset_state() { mips_mem_reset(); if (!mstate->warm) { memset(mstate->cp1, 0, sizeof(mstate->cp1[32])); memset(mstate->fpr, 0, sizeof(mstate->fpr[32])); mstate->count_seed = mstate->now; mstate->cp0[PRId] = ImpRev; //Fix me, Shi yang 2006-08-30 mstate->cp1[FCR0] = ImpRev; mstate->nop_count = 0; } mstate->ll_bit = 0; mstate->sync_bit = 0; // Deliver the reset exception. if (mstate->warm) deliver_soft_reset(mstate); else deliver_cold_reset(mstate); process_reset(mstate); } void mips_trigger_irq(MIPS_State* mstate) { VA epc; //Get the content of the cause register UInt32 cause = mstate->cp0[Cause]; //When the instruction is in the delay slot, we have to delay an instruction if (!branch_delay_slot(mstate)) epc = mstate->pc; else { epc = mstate->pc - 4; cause = set_bit(cause, Cause_BD); } mstate->cp0[Cause] = cause; mstate->cp0[EPC] = epc; //Change the pointer pc to deal with the interrupt handler if(bit(mstate->cp0[SR], SR_BEV) ) { mstate->pc = 0xbfc00380; } else { mstate->pc = 0x80000180; } mstate->pipeline = nothing_special; } static void mips_step_once() { mstate->gpr[0] = 0; /* Check for interrupts. In real hardware, these have a priority lower * than all exceptions, but simulating this effect is too hard to be * worth the effort (interrupts and resets are not meant to be * delivered accurately anyway.) */ if(mstate->irq_pending) { mips_trigger_irq(mstate); } /* Look up the ITLB. It's not clear from the manuals whether the ITLB * stores the ASIDs or not. I assume it does. ITLB has the same size * as in the real hardware, mapping two 4KB pages. Because decoding a * MIPS64 virtual address is far from trivial, ITLB and DTLB actually * improve the simulator's performance: something I cannot say about * caches and JTLB. */ PA pa; //Shi yang 2006-08-18 VA va; Instr instr; int next_state; va = mstate->pc; if(translate_vaddr(mstate, va, instr_fetch, &pa) == TLB_SUCC){ mips_mem_read(pa, &instr, 4); next_state = decode(mstate, instr); //skyeye_exit(-1); } else{ //fprintf(stderr, "Exception when get instruction!\n"); } /* NOTE: mstate->pipeline is also possibely set in decode function */ static int flag = 0; if(mstate->pc == 0x4001a0) flag = 0; if(flag) //fprintf(skyeye_logfd, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x, sp=0x%x, ra=0x%x,s1=0x%x, v0=0x%x\n", instr, pa, va, mstate->gpr[29], mstate->gpr[31],mstate->gpr[17], mstate->gpr[2]); fprintf(skyeye_logfd, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x, a0=0x%x, a1=0x%x, t0=0x%x, t1=0x%x, v0=0x%x, s8=0x%x\n", instr, pa, va, mstate->gpr[4], mstate->gpr[5], mstate->gpr[8], mstate->gpr[9], mstate->gpr[2], mstate->gpr[30]); //fprintf(skyeye_logfd, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x,v0=0x%x,t0=0x%x\n", instr, pa, va, mstate->gpr[2], mstate->gpr[8]); /*if(mips_mem.rom[0][(0x1179a00 >> 2)] != 0){ if(mips_mem.rom[0][(0x1179a00 >> 2)] != 0x81179b28) fprintf(stderr, "Value changed:0x81179a00 = 0x%x,pc=0x%x\n", mips_mem.rom[0][(0x1179a00 >> 2)],mstate->pc); }*/ switch (mstate->pipeline) { case nothing_special: mstate->pc += 4; break; case branch_delay: mstate->pc = mstate->branch_target; break; case instr_addr_error: process_address_error(mstate, instr_fetch, mstate->branch_target); case branch_nodelay: /* For syscall and TLB exp, we donot like to add pc */ mstate->pipeline = nothing_special; return; /* do nothing */ } mstate->pipeline = next_state; /* if interrupt is enabled? */ if((mstate->cp0[SR] & (1 << SR_IEC)) && (mstate-> cp0[SR] & 1 << SR_IM7)){ if(!(mstate->cp0[Cause] & 1 << Cause_IP7) && (!(mstate->cp0[SR] & 0x2))) { /* update counter value in cp0 */ mstate->cp0[Count]++; //fprintf(stderr, "counter=0x%x,pc=0x%x\n", mstate->cp0[Count], mstate->pc); /* if timer int is not mask and counter value is equal to compare value */ if(mstate->cp0[Count] >= mstate->cp0[Compare]){ /* Set counter interrupt bit in IP section of Cause register */ mstate->cp0[Cause] |= 1 << Cause_IP7; /* Set ExcCode to zero in Cause register */ process_exception(mstate, EXC_Int, common_vector); } } } skyeye_config.mach->mach_io_do_cycle (mstate); } static void mips_set_pc(UInt32 addr) { mstate->pc = addr; } static UInt32 mips_get_pc() { return mstate->pc; } static void mips_write_byte (WORD addr, uint8_t v) { mips_mem_write_byte (addr, v); } static void mips_write_byte64(UInt64 addr, UInt8 data) { } static unsigned char mips_read_byte64(UInt64 addr) { } extern void nedved_mach_init(void * state, machine_config_t * mach); extern void au1100_mach_init(void * state, machine_config_t * mach); extern void fulong_mach_init(void * state, machine_config_t * mach); static machine_config_t mips_machines[] = { {"nedved", nedved_mach_init, NULL, NULL, NULL}, {"au1100", au1100_mach_init, NULL, NULL, NULL}, }; static int mips_parse_cpu(const char* param[]) { return 1; } static int mips_parse_mach(machine_config_t * mach, const char* params[]) { int i; for (i = 0; i < (sizeof (mips_machines) / sizeof (machine_config_t)); i++) { if (!strncmp (params[0], mips_machines[i].machine_name, MAX_PARAM_NAME)) { skyeye_config.mach = &mips_machines[i]; SKYEYE_INFO ("mach info: name %s, mach_init addr %p\n", skyeye_config.mach->machine_name, skyeye_config.mach->mach_init); return 0; } } SKYEYE_ERR ("Error: Unkonw mach name \"%s\"\n", params[0]); return -1; } static int mips_parse_mem(int num_params, const char* params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, num; mips_mem_config_t *mc = &mips_mem_config; mips_mem_bank_t *mb = mc->mem_banks; mc->bank_num = mc->current_num++; num = mc->current_num - 1; /*mem_banks should begin from 0. */ mb[num].filename[0] = '\0'; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: mem_bank %d has wrong parameter \"%s\".\n", num, name); if (!strncmp ("map", name, strlen (name))) { if (!strncmp ("M", value, strlen (value))) { mb[num].read_byte = mips_real_read_byte; mb[num].write_byte = mips_real_write_byte; mb[num].read_halfword = mips_real_read_halfword; mb[num].write_halfword = mips_real_write_halfword; mb[num].read_word = mips_real_read_word; mb[num].write_word = mips_real_write_word; mb[num].read_doubleword = mips_real_read_doubleword; mb[num].write_doubleword = mips_real_write_doubleword; mb[num].type = MEMTYPE_RAM; } else if (!strncmp ("I", value, strlen (value))) { mb[num].read_byte = mips_io_read_byte; mb[num].write_byte = mips_io_write_byte; mb[num].read_halfword = mips_io_read_halfword; mb[num].write_halfword = mips_io_write_halfword; mb[num].read_word = mips_io_read_word; mb[num].write_word = mips_io_write_word; mb[num].read_doubleword = mips_io_read_doubleword; mb[num].write_doubleword = mips_io_write_doubleword; mb[num].type = MEMTYPE_IO; /*ywc 2005-03-30 */ } else if (!strncmp ("F", value, strlen (value))) { mb[num].read_byte = mips_flash_read_byte; mb[num].write_byte = mips_flash_write_byte; mb[num].read_halfword = mips_flash_read_halfword; mb[num].write_halfword = mips_flash_write_halfword; mb[num].read_word = mips_flash_read_word; mb[num].write_word = mips_flash_write_word; mb[num].read_doubleword = mips_flash_read_doubleword; mb[num].write_doubleword = mips_flash_write_doubleword; mb[num].type = MEMTYPE_FLASH; } else { SKYEYE_ERR ("Error: mem_bank %d \"%s\" parameter has wrong value \"%s\"\n", num, name, value); } } else if (!strncmp ("type", name, strlen (name))) { //chy 2003-09-21: process type if (!strncmp ("R", value, strlen (value))) { if (mb[num].type == MEMTYPE_RAM) mb[num].type = MEMTYPE_ROM; mb[num].write_byte = mips_warn_write_byte; mb[num].write_halfword = mips_warn_write_halfword; mb[num].write_word = mips_warn_write_word; } } else if (!strncmp ("addr", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].addr = strtoul (value, NULL, 16); else mb[num].addr = strtoul (value, NULL, 10); } else if (!strncmp ("size", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].len = strtoul (value, NULL, 16); else mb[num].len = strtoul (value, NULL, 10); } else if (!strncmp ("file", name, strlen (name))) { strncpy (mb[num].filename, value, strlen (value) + 1); } else if (!strncmp ("boot", name, strlen (name))) { /*this must be the last parameter. */ if (!strncmp ("yes", value, strlen (value))) skyeye_config.start_address = mb[num].addr; } else { SKYEYE_ERR ("Error: mem_bank %d has unknow parameter \"%s\".\n", num, name); } } return 0; } static int mips_ICE_read_byte(WORD addr, uint8_t *data){ mips_mem_read(addr, (UInt32 *)data, 1); return 0; } static int mips_ICE_write_byte(WORD addr, uint8_t data){ #if 1 extern mips_mem_bank_t *mips_global_mbp; /* if pa is located at kseg0 */ if(addr >= 0x80000000 && addr < 0xA0000000) addr = addr & ~0x80000000; /* if pa is located at kseg1 */ if(addr >= 0xA0000000 && addr < 0xC0000000) addr = addr & ~0xE0000000; uint8_t *temp; //get the memory bank of the address mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp ) { temp = &(mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks][(addr - mips_global_mbp->addr) >> 2]); temp += addr & 0x3; *temp = data ; } else { fprintf(stderr,"mips memory write error in %s, addr=0x%x,pc=0x%x..\n",__FUNCTION__,addr, mstate->pc); skyeye_exit(-1); } #endif // mips_mem_write(addr, &data, 1); return 0; } void init_mips_arch () { static arch_config_t mips_arch; mips_arch.arch_name = arch_name; mips_arch.init = mips_init_state; mips_arch.reset = mips_reset_state; mips_arch.step_once = mips_step_once; mips_arch.set_pc = mips_set_pc; mips_arch.get_pc = mips_get_pc; mips_arch.ICE_read_byte = mips_ICE_read_byte; mips_arch.ICE_write_byte = mips_ICE_write_byte; mips_arch.parse_cpu = mips_parse_cpu; mips_arch.parse_mach = mips_parse_mach; mips_arch.parse_mem = mips_parse_mem; register_arch (&mips_arch); } ������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/decoder.c���������������������������������������������������������0000644�0001750�0000144�00000076541�11006337414�017200� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "instr.h" #include "emul.h" #include <stdio.h> /* Anthony Lee: 2006-09-18 */ #ifdef __MINGW32__ #define sync() _flushall() #else #include <unistd.h> /* for sync() */ #endif extern FILE *skyeye_logfd; /* This monster of a switch statement decodes all CPU instructions. I've * decided against an explicit jump table, as such implementation both * increases the code size and introduced additional overhead to the inner * decoder loop. */ /* WARNING: The below code currently does not simulate any slips. * This should be fixed soon (it's fairly easy to simulate, too.) */ const char* regname[32] = { "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" }; int decode(MIPS_State* mstate, Instr instr) { switch (opcode(instr)) { case SPECIAL: { /* Special instructions, decoded using the (function) field */ switch (function(instr)) { case SLL: { // Shift Left Logical if (rd(instr)) { UInt32 x = mstate->gpr[rt(instr)]; int s = shamt(instr); x <<= s; mstate->gpr[rd(instr)] = x; } return nothing_special; } case SRL: { // Shift Right Logical UInt32 x = mstate->gpr[rt(instr)]; int s = shamt(instr); x >>= s; mstate->gpr[rd(instr)] = x; return nothing_special; } case SRA: { // Shift Right Arithmetic UInt32 x = mstate->gpr[rt(instr)]; int s = shamt(instr); x >>= s; mstate->gpr[rd(instr)] = sign_extend_UInt32(x, 32 - s); return nothing_special; } case SLLV: { UInt32 x = mstate->gpr[rt(instr)]; int s = bits(mstate->gpr[rs(instr)], 4, 0); x <<= s; //mstate->gpr[rd(instr)] = sign_extend_UInt32(x, 32 - s); mstate->gpr[rd(instr)] = x; return nothing_special; } case SRLV: { // Shift Right Logical Variable UInt32 x = mstate->gpr[rt(instr)]; int s = bits(mstate->gpr[rs(instr)], 4, 0); x >>= s; //mstate->gpr[rd(instr)] = sign_extend_UInt32(x, 32 - s); mstate->gpr[rd(instr)] = x; return nothing_special; } case SRAV: { // Shift Right Arithmetic Variable UInt32 x = mstate->gpr[rt(instr)]; int s = bits(mstate->gpr[rs(instr)], 4, 0); x >>= s; mstate->gpr[rd(instr)] = sign_extend_UInt32(x, 32 - s); return nothing_special; } case MOVZ: { if(!mstate->gpr[rt(instr)]) mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)]; return nothing_special; } case MOVN: { if(mstate->gpr[rt(instr)]) mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)]; return nothing_special; } case JR: { // Jump Register mstate->branch_target = mstate->gpr[rs(instr)]; if (mstate->pipeline == branch_delay) printf("Can't handle branch in branch delay slot\n"); return bits(mstate->branch_target, 1, 0) ? instr_addr_error : branch_delay; } case JALR: { // Jump And Link Register mstate->branch_target = mstate->gpr[rs(instr)]; if(rd(instr) != 31) mstate->gpr[rd(instr)] = mstate->pc + 8; else mstate->gpr[31] = mstate->pc + 8; if (mstate->pipeline == branch_delay) printf("Can't handle branch in branch delay slot\n"); return bits(mstate->branch_target, 1, 0) ? instr_addr_error : branch_delay; } case SYSCALL: { // System Call process_syscall(mstate); return nothing_special; } case BREAK: { //process_breakpoint(mstate); fprintf(stderr,"workaround for break instruction, pc=0x%x\n ", mstate->pc); return nothing_special; } case SYNC: { // Synchronize //Fix me Shi yang 2006-08-08 //process_reserved_instruction(mstate); return nothing_special; } case MFHI: { // Move From HI mstate->gpr[rd(instr)] = mstate->hi; return nothing_special; } case MTHI: { // Move To HI mstate->hi = mstate->gpr[rs(instr)]; return nothing_special; } case MFLO: { // Move From LO mstate->gpr[rd(instr)] = mstate->lo; return nothing_special; } case MTLO: { // Move To LO mstate->lo = mstate->gpr[rs(instr)]; return nothing_special; } case DSLLV: { // Doubleword Shift Left Logical Variable process_reserved_instruction(mstate); return nothing_special; } case DSRLV: { // Doubleword Shift Right Logical Variable process_reserved_instruction(mstate); return nothing_special; } case DSRAV: { // Doubleword Shift Right Arithmetic Variable process_reserved_instruction(mstate); return nothing_special; } case MULT: { // Multiply Int64 x = mstate->gpr[rs(instr)]; Int64 y = mstate->gpr[rt(instr)]; //multiply(x, y); long long z = x * y; mstate->hi = (z >> 32) & 0xFFFFFFFF; mstate->lo = z & 0xFFFFFFFF; return nothing_special; } case MULTU: { // Multiply Unsigned UInt64 x = mstate->gpr[rs(instr)]; UInt64 y = mstate->gpr[rt(instr)]; unsigned long long z = x * y; //multiply(x, y); mstate->hi = (z >> 32) & 0xFFFFFFFF; mstate->lo = z & 0xFFFFFFFF; return nothing_special; } case DIV: { // Divide Int32 y = (Int32) mstate->gpr[rt(instr)]; Int32 x = (Int32) mstate->gpr[rs(instr)]; divide_Int32(x, y); return nothing_special; } case DIVU: { UInt32 y = (UInt32) mstate->gpr[rt(instr)]; UInt32 x = (UInt32) mstate->gpr[rs(instr)]; divide_UInt32(x, y); return nothing_special; } case DMULT: { // Doubleword Multiply process_reserved_instruction(mstate); return nothing_special; } case DMULTU: { // Doubleword Multiply Unsigned process_reserved_instruction(mstate); return nothing_special; } case DDIV: { // Doubleword Divide process_reserved_instruction(mstate); return nothing_special; } case DDIVU: { // Doubleword Divide Unsigned process_reserved_instruction(mstate); return nothing_special; } case ADD: { // Add UInt32 x = mstate->gpr[rs(instr)]; UInt32 y = mstate->gpr[rt(instr)]; UInt32 z = x + y; // Overflow occurs is sign(x) == sign(y) != sign(z). if (bit(x ^ y, 31) == 0 && bit(x ^ z, 31) != 0) process_integer_overflow(mstate); mstate->gpr[rd(instr)] = z; return nothing_special; } case ADDU: { // Add Unsigned UInt32 x = mstate->gpr[rs(instr)]; UInt32 y = mstate->gpr[rt(instr)]; UInt32 z = x + y; mstate->gpr[rd(instr)] = z; return nothing_special; } case SUB: { // Subtract Int32 x = mstate->gpr[rs(instr)]; Int32 y = mstate->gpr[rt(instr)]; Int32 z = (UInt32)x - (UInt32)y; if ((y < 0 && z < x) || (y > 0 && z > x)) process_integer_overflow(); mstate->gpr[rd(instr)] = z; return nothing_special; } case SUBU: { // Subtract Unsigned UInt32 x = mstate->gpr[rs(instr)]; UInt32 y = mstate->gpr[rt(instr)]; mstate->gpr[rd(instr)] = x - y; return nothing_special; } case AND: { // And mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)] & mstate->gpr[rt(instr)]; return nothing_special; } case OR: { // Or mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)] | mstate->gpr[rt(instr)]; return nothing_special; } case XOR: { // Exclusive Or mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)] ^ mstate->gpr[rt(instr)]; return nothing_special; } case NOR: { // Nor mstate->gpr[rd(instr)] = ~((mstate->gpr[rs(instr)] | mstate->gpr[rt(instr)])); return nothing_special; } case SLT: { // Set On Less Than Int32 x = mstate->gpr[rs(instr)]; Int32 y = mstate->gpr[rt(instr)]; mstate->gpr[rd(instr)] = (x < y); return nothing_special; } case SLTU: { mstate->gpr[rd(instr)] = (mstate->gpr[rs(instr)] < mstate->gpr[rt(instr)]); return nothing_special; } case DADD: { // Doubleword Add process_reserved_instruction(mstate); return nothing_special; } case DADDU: { // Doubleword Add Unsigned process_reserved_instruction(mstate); return nothing_special; } case DSUB: { // Doubleword Subtract process_reserved_instruction(mstate); return nothing_special; } case DSUBU: { // Doubleword Subtract Unsigned process_reserved_instruction(mstate); return nothing_special; } case TGE: { // Trap If Greater Than Or Equal process_reserved_instruction(mstate); return nothing_special; } case TGEU: { // Trap If Greater Than Or Equal Unsigned process_reserved_instruction(mstate); return nothing_special; } case TLT: { // Trap If Less Than process_reserved_instruction(mstate); return nothing_special; } case TLTU: { // Trap If Less Than Unsigned process_reserved_instruction(mstate); return nothing_special; } case TEQ: { // Trap If Equal process_reserved_instruction(mstate); return nothing_special; } case TNE: { // Trap If Not Equal if( mstate->gpr[rs(instr)] != mstate->gpr[rt(instr)]) fprintf(stderr,"trap happened in %s at 0x%x.\n", __FUNCTION__, mstate->pc); //process_reserved_instruction(mstate); //skyeye_exit(-1); return nothing_special; } case DSLL: { // Doubleword Shift Left Logical process_reserved_instruction(mstate); return nothing_special; } case DSRL: { // Doubleword Shift Right Logical process_reserved_instruction(mstate); return nothing_special; } case DSRA: { // Doubleword Shift Right Arithmetic process_reserved_instruction(mstate); return nothing_special; } case DSLL32: { // Doubleword Shift Left Logical + 32 process_reserved_instruction(mstate); return nothing_special; } case DSRL32: { // Doubleword Shift Right Logical + 32 process_reserved_instruction(mstate); return nothing_special; } case DSRA32: { // Doubleword Shift Right Arithmetic + 32 process_reserved_instruction(mstate); return nothing_special; } default: // Reserved instruction process_reserved_instruction(mstate); return nothing_special; }// switch (function(instr)) { }//case SPECIAL: case REGIMM: { switch (rt(instr)) { case BLTZ: { // Branch On Less Than Zero Int32 x = mstate->gpr[rs(instr)]; if (x < 0) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot\n"); } return branch_delay; } case BGEZ: { // Branch On greater Than Zero Int32 x = mstate->gpr[rs(instr)]; if (x >= 0) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot\n"); } return branch_delay; } case BLTZL: { // Branch On Less Than Zero Likely return nothing_special; } case BGEZL: { // Branch On Greater Than Or Equal To Zero Likely return nothing_special; } case TGEI: { // Trap If Greater Than Or Equal Immediate return nothing_special; } case TGEIU: { // Trap If Greater Than Or Equal Immediate Unsigned return nothing_special; } case TLTI: { // Trap If Less Than Immediate return nothing_special; } case TLTIU: { // Trap If Less Than Immediate Unsigned return nothing_special; } case TEQI: { // Trap If Equal Immediate return nothing_special; } case TNEI: { // Trap If Not Equal Immediate return nothing_special; } case BLTZAL: { // Branch On Less Than Zero And Link Int32 x = mstate->gpr[rs(instr)]; mstate->gpr[31] = mstate->pc + 8; if (x < 0) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot\n"); } return branch_delay; } case BGEZAL: { // Branch On Greater Than Or Equal To Zero And Link Int32 x = mstate->gpr[rs(instr)]; mstate->gpr[31] = mstate->pc + 8; if (x >= 0) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot\n"); } return branch_delay; } case BLTZALL: { // Branch On Less Than Zero And Link Likely return nothing_special; } case BGEZALL: { // Branch On Greater Than Or Equal To Zero And Link Likely return nothing_special; } default: process_reserved_instruction(mstate); return nothing_special; //Fix me. Shi yang 2006-08-09 } }//case REGIMM: case J: { // Jump VA msb = clear_bits(mstate->pc + 4, 27, 0); mstate->branch_target = msb | (target(instr) << 2); if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot"); } return branch_delay; } case JAL: { // Jump And Link mstate->gpr[31] = mstate->pc + 8; VA msb = clear_bits(mstate->pc + 4, 27, 0); mstate->branch_target = msb | (target(instr) << 2); if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot"); } return branch_delay; } case BEQ: { // Branch On Equal if (mstate->gpr[rs(instr)] == mstate->gpr[rt(instr)]) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot"); } return branch_delay; } case BNE: { // Branch On Not Equal if (mstate->gpr[rs(instr)] != mstate->gpr[rt(instr)]) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot"); } return branch_delay; } case BLEZ: { // Branch On Less Than Or Equal To Zero Int32 x = mstate->gpr[rs(instr)]; if (x <= 0) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot"); } return branch_delay; } case BGTZ: { // Branch On Greater Than Zero Int32 x = mstate->gpr[rs(instr)]; if (x > 0) { VA off = sign_extend_UInt32(offset(instr), 16); mstate->branch_target = mstate->pc + 4 + (off << 2); } else { mstate->branch_target = mstate->pc + 8; } if (mstate->pipeline == branch_delay) { printf("Can't handle branch in branch delay slot"); } return branch_delay; } case ADDI: { // Add Immediate UInt32 x = mstate->gpr[rs(instr)]; UInt32 y = sign_extend_UInt32(immediate(instr), 16); UInt32 z = x + y; // Overflow occurs is sign(x) == sign(y) != sign(z). if (bit(x ^ y, 31) == 0 && bit(x ^ z, 31) != 0) process_integer_overflow(mstate); mstate->gpr[rt(instr)] = z; return nothing_special; } case ADDIU: { /* confused, signed or unsigned ?? */ // Add Immediate Unsigned UInt32 x = mstate->gpr[rs(instr)]; Int32 y = sign_extend_UInt32(immediate(instr), 16); UInt32 z = x + y; //fprintf(skyeye_logfd, "0x%d,0x%d,0x%d, in 0x%x\n", x ,y, z, mstate->pc); mstate->gpr[rt(instr)] = z; return nothing_special; } case SLTI: { // Set On Less Than Immediate Int32 x = mstate->gpr[rs(instr)]; Int32 y = sign_extend_UInt32(immediate(instr), 16); mstate->gpr[rt(instr)] = (x < y); return nothing_special; } case SLTIU: { // Set On Less Than Immediate Unsigned UInt32 x = mstate->gpr[rs(instr)]; UInt32 y = sign_extend_UInt32(immediate(instr), 16); mstate->gpr[rt(instr)] = (x < y); return nothing_special; } case ANDI: { // And Immediate UInt16 x = mstate->gpr[rs(instr)]; UInt16 imm = zero_extend(immediate(instr), 16); mstate->gpr[rt(instr)] = x & imm; //Shi yang 2006-08-31 return nothing_special; } case ORI: { // Or Immediate UInt32 x = mstate->gpr[rs(instr)]; //Shi yang 2006-08-09 UInt16 imm = immediate(instr); mstate->gpr[rt(instr)] = x | imm; return nothing_special; } case XORI: { // Exclusive Or Immediate UInt32 x = mstate->gpr[rs(instr)]; UInt32 imm = immediate(instr); mstate->gpr[rt(instr)] = x ^ imm; return nothing_special; } case LUI: { // Load Upper Immediate UInt32 imm = immediate(instr); imm <<= 16; mstate->gpr[rt(instr)] = imm; return nothing_special; } case COP0: { // Coprocessor 0 Operation return decode_cop0(mstate, instr); } case COP1: { return decode_cop1(mstate, instr); // Coprocessor 1 Operation //process_reserved_instruction(mstate); } case COP2: { // Coprocessor 2 Operation process_reserved_instruction(mstate); return nothing_special; } case PREF: { //fprintf(stderr, "PREF instruction,pc=0x%x\n",mstate->pc); return nothing_special; } case BEQL: { // Branch On Equal Likely process_reserved_instruction(mstate); return nothing_special; } case BNEL: { // Branch On Not Equal Likely process_reserved_instruction(mstate); return nothing_special; } case BLEZL: { process_reserved_instruction(mstate); return nothing_special; } case BGTZL: { // Branch On Greater Than Zero Likely process_reserved_instruction(mstate); return nothing_special; } case DADDI: { // Doubleword Add Immediate process_reserved_instruction(mstate); return nothing_special; } case DADDIU: { // Doubleword Add Immediate Unsigned process_reserved_instruction(mstate); return nothing_special; } case LDL: { // Load Doubleword Left process_reserved_instruction(mstate); return nothing_special; } case LDR: { // Load Doubleword Right process_reserved_instruction(mstate); return nothing_special; } case SPECIAL2: { switch (function(instr)) { case MADD: { UInt64 temp1 = mstate->hi << 32 + mstate->lo; UInt64 temp2 = mstate->gpr[rs(instr)] * mstate->gpr[rt(instr)] + temp1; mstate->hi = (temp2 >> 32) & (~0x0); mstate->lo = temp2 & (~0x0); return nothing_special; } case FMUL: { mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)] * mstate->gpr[rt(instr)]; return nothing_special; } case CVT_S://CLZ: { int i = 31; for(i; i >= 0;i--) if( mstate->gpr[rs(instr)] & (1 << i)) break; else continue; mstate->gpr[rd(instr)] = 31 - i; return nothing_special; } default: // Load Doubleword Right process_reserved_instruction(mstate); return nothing_special; } } case LB: { // Load Byte UInt32 x; UInt32 y = 0; if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC) return nothing_special; /* if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC){ return nothing_special; }*/ load(mstate, va, pa, &y, 1); x = sign_extend_UInt32(y & (0xff), 8); //Shi yang 2006-08-10, Sign extend mstate->gpr[rt(instr)] = x; return nothing_special; } case LH: { // Load Halfword if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; if (bit(va, 0)) //Check alignment process_address_error(data_load, va); PA pa; if(translate_vaddr(mstate,va, data_load, &pa) != TLB_SUCC) return nothing_special; //Shi yang 2006-08-10 UInt32 x; UInt32 y = 0; load(mstate, va, pa, &y, 2); x = sign_extend_UInt32(y & (0xffff), 16); //Shi yang 2006-08-10, Sign extend mstate->gpr[rt(instr)] = x; return nothing_special; } case LWL: { // Load Word Left if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC) return nothing_special; //Shi yang 2006-08-10 UInt32 mem; UInt32 y = 0; load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4); mem = y & (0xffffffff); UInt32 reg = mstate->gpr[rt(instr)]; int syscmd = bits(va, 1, 0); if (!big_endian_cpu(mstate)) syscmd ^= bitsmask(1, 0); reg = copy_bits(reg, mem, 31, syscmd * 8); mstate->gpr[rt(instr)] = reg; return nothing_special; } case LW: { // Load Word if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; if (bits(va, 1, 0)) //Check alignment process_address_error(mstate,data_load, va); PA pa; if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC) return nothing_special; //Shi yang 2006-08-10 UInt32 x; UInt32 y = 0; load(mstate, va, pa, &y, 4); mstate->gpr[rt(instr)] = y; return nothing_special; } case LBU: { // Load Byte Unsigned if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC) return nothing_special; //Shi yang 2006-08-10 UInt32 y = 0; UInt32 x; load(mstate, va, pa, &y, 1); x = y & 0xffL; //Shi yang 2006-08-25 mstate->gpr[rt(instr)] = x; return nothing_special; } case LHU: { // Load Halfword Unsigned if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; if (bit(va, 0)) //Check alignment process_address_error(mstate,data_load, va); PA pa; if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC) return nothing_special; //Shi yang 2006-08-10 UInt16 x; UInt32 y = 0; load(mstate, va, pa, &y, 2); x = y & 0xffffL; //Shi yang 2006-08-25 mstate->gpr[rt(instr)] = x; return nothing_special; } case LWR: { // Load Word Right if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate,va, data_load, &pa)) return nothing_special; //Shi yang 2006-08-10 UInt32 mem; UInt32 y = 0; load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4); mem = y & (0xffffffff); UInt32 reg = mstate->gpr[rt(instr)]; int syscmd = bits(va, 1, 0); if (big_endian_cpu(mstate)) syscmd ^= bitsmask(1, 0); reg = copy_bits(reg, bits(mem, 31, syscmd * 8), 31 - syscmd * 8, 0); mstate->gpr[rt(instr)] = reg; return nothing_special; } case LWU: { // Load Word Unsigned process_reserved_instruction(mstate); return nothing_special; } case SB: { // Store Byte if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate,va, data_store, &pa)) return nothing_special; //Shi yang 2006-08-10 store(mstate, mstate->gpr[rt(instr)], va, pa, 1); // Fix me: Shi yang 2006-08-10 return nothing_special; } case SH: { // Store Halfword if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; if (bit(va, 0)) //Check alignment process_address_error(mstate,data_store, va); PA pa; if(translate_vaddr(mstate, va, data_store, &pa)) return nothing_special; //Shi yang 2006-08-10 store(mstate, mstate->gpr[rt(instr)], va, pa, 2); //Fix me: Shi yang 2006-08-10 return nothing_special; } case SWL: { // Store Word Left if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate, va, data_store, &pa)) return nothing_special; //Shi yang 2006-08-10 UInt32 mem; UInt32 y = 0; load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4); mem = y & (0xffffffff); UInt32 reg = mstate->gpr[rt(instr)]; int syscmd = bits(va, 1, 0); if (!big_endian_cpu(mstate)) syscmd ^= bitsmask(1, 0); mem = copy_bits(mem, bits(reg, 31, syscmd * 8), 31 - syscmd * 8, 0); store(mstate, mem, round_down(va, 4), round_down(pa, 4), 4); //Fix me: Shi yang 2006-08-10 return nothing_special; } case SW: { // Store Word if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; if (bits(va, 1, 0)) //Check alignment { fprintf(stderr," in %s,address unaligned va=0x%x,pc=0x%x\n", __FUNCTION__, va, mstate->pc); skyeye_exit(-1); process_address_error(mstate,data_store, va); } PA pa; if(translate_vaddr(mstate,va, data_store, &pa) != TLB_SUCC) return nothing_special; //Shi yang 2006-08-10 store(mstate, mstate->gpr[rt(instr)], va, pa, 4); //Fix me: Shi yang 2006-08-10 return nothing_special; } case SDL: { // Store Doubleword Left process_reserved_instruction(mstate); return nothing_special; } case SDR: { // Store Doubleword Right process_reserved_instruction(mstate); return nothing_special; } case SWR: { // Store Word Right if (mstate->sync_bit) sync(); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate, va, data_store, &pa) != TLB_SUCC) return nothing_special; //Shi yang 2006-08-10 UInt32 mem; UInt32 y = 0; load(mstate,round_down(va, 4), round_down(pa, 4),&y,4); mem = y & (0xffffffff); UInt32 reg = mstate->gpr[rt(instr)]; int syscmd = bits(va, 1, 0); if (big_endian_cpu(mstate)) syscmd ^= bitsmask(1, 0); mem = copy_bits(mem, reg, 31, syscmd * 8); store(mstate, mem, round_down(va, 4), round_down(pa, 4), 4); //Fix me: Shi yang 2006-08-10 return nothing_special; } case CACHE: //Nedved's cache instruction. Shi yang 2006-08-24 { // Cache return nothing_special; } case LL: { // Load Linked //int va = mstate->gpr[base(instr)] + offset(instr); int va = mstate->gpr[base(instr)] + sign_extend_UInt32(offset(instr), 16); PA pa; if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC) return nothing_special; int data; mips_mem_read(pa, &data, 4); mstate->gpr[rt(instr)] = data; //process_reserved_instruction(mstate); return nothing_special; } case LWC1: { // Load Word to Coprocessor 1 return nothing_special; //Shi yang 2006-08-31 } case LWC2: { // Load Word to Coprocessor 2 process_reserved_instruction(mstate); return nothing_special; } case LLD: { // Load Linked Doubleword process_reserved_instruction(mstate); return nothing_special; } case LDC1: { // Load Doubleword To Coprocessor 1 process_reserved_instruction(mstate); return nothing_special; } case LDC2: { // Load Doubleword To Coprocessor 2 process_reserved_instruction(mstate); return nothing_special; } case LD: { // Load Doubleword process_reserved_instruction(mstate); return nothing_special; } case SC: { // Store Conditional //int va = mstate->gpr[base(instr)] + offset(instr); int va = mstate->gpr[base(instr)] + sign_extend_UInt32(offset(instr), 16); PA pa; if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC) return nothing_special; int data; data = mstate->gpr[rt(instr)]; /* if(mstate->pc == 0x8012a858){ fprintf(stderr, "In SC,data=0x%x,va=0x%x\n", data, va); if(va == 0x81179a00){ fprintf(stderr, "Write to %d\n",va); skyeye_exit(-1); } } */ mips_mem_write(pa, &data, 4); mstate->gpr[rt(instr)] = 1; //process_reserved_instruction(mstate); return nothing_special; } case SWC1: { // Store Word From Coprocessor 1 return nothing_special; //Shi yang 2006-08-31 } case SWC2: { // Store Word From Coprocessor 2 process_reserved_instruction(mstate); return nothing_special; } case SCD: { // Store Conditional process_reserved_instruction(mstate); return nothing_special; } case SDC1: { // Store Doubleword From Coprocessor 1 process_reserved_instruction(mstate); return nothing_special; } case SDC2: { // Store Doubleword From Coprocessor 2 process_reserved_instruction(mstate); return nothing_special; } case SD: { // Store Doubleword process_reserved_instruction(mstate); return nothing_special; } default: // Reserved instruction. process_reserved_instruction(mstate); return nothing_special; } } ���������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/interrupt.c�������������������������������������������������������0000644�0001750�0000144�00000000513�10541455476�017625� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "emul.h" /* Deliver external events. The (events) bitset is consulted synchronously at * appropriate places in the fetch-execute loop. */ void deliver_cold_reset(MIPS_State* mstate) { mstate->events |= cold_reset_event; } void deliver_soft_reset(MIPS_State* mstate) { mstate->events |= soft_reset_event; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/icache.c����������������������������������������������������������0000644�0001750�0000144�00000006536�10541455476�017020� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "emul.h" // Reset the L1 instruction cache. void reset_icache(MIPS_State* mstate) { int i, j; for (i = 0; i < Icache_sets; ++i) { for (j = 0; j < Icache_assoc; ++j) mstate->icache.set[i].line[j].tag = bad_tag; Icache_lru_init(mstate->icache.set[i].Icache_lru); } mstate->ibuf[0].tag = bad_ibuf_tag; mstate->ibuf[1].tag = bad_ibuf_tag; } // Perform a cache operation (for use by decode_cache()). void control_icache(MIPS_State* mstate, VA va, PA pa, int op, int type) { if (type) return; // secondary cache not presents switch (op) { case 0: { mstate->icache.set[Icache_index(va)].line[Icache_block(va)].tag = bad_tag; break; } case 1: { break; } case 2: { break; } case 4: { UInt32 tag = mstate->icache.set[Icache_index(va)].line[Icache_block(va)].tag; if (tag == Icache_tag(pa)) mstate->icache.set[Icache_index(va)].line[Icache_block(va)].tag = bad_tag; break; } case 5: { UInt32 tag = (UInt32) Icache_tag(pa); MIPSICacheSet* set=&mstate->icache.set[Icache_index(va)]; MIPSICacheLine *line=&set->line[Icache_block(va)]; const VA line_mask = Icache_line_size - 1; int j; for(j = 0; j < 4; j++) mips_mem_read((pa & ~line_mask)+8*j , line->data+j, 8); break; } case 6: // Hit Writeback. break; // secondary cache not present case 7: // Hit Set Virtual. break; // secondary cache not present default: // Everything else is ignored. break; } // In all cases, invalidate the ibufs. mstate->ibuf[0].tag = bad_ibuf_tag; mstate->ibuf[1].tag = bad_ibuf_tag; } /* Fetch an instruction from the virtual address (va). The address translation * has already been performed and the physical address is (pa). The coherency * algorithm to use is encoded in high-order bits of (pa) using the same * encoding as that of the xkphys address space region. */ // WARNING: currently, the memory access latencies are not simulated. Instr fetch(MIPS_State* mstate, VA va, PA pa) { int i; int ca = coherency_algorithm(pa); if (ca == 0x5) { //Shi yang 2006-08-15 // A direct memory access. UInt32 x; mips_mem_read(pa, &x, 4); return x; } // A cached memory access. UInt32 index = Icache_index(pa); UInt32 tag = Icache_tag(pa); MIPSICacheSet* set = &(mstate->icache.set[index]); MIPSICacheLine* line = &(set->line[0]); const PA line_mask = Icache_line_size - 1; // Find the correct entry in the set (if any). for (i = 0; i < Icache_assoc; ++i, ++line) { if (line->tag == tag) { Icache_lru_touch(set->Icache_lru,i); goto cache_hit; } } // Otherwise, we've got a cache miss. i = Icache_lru_replace(mstate->icache.set[index].Icache_lru); line = &(mstate->icache.set[index].line[i]); // Fill the cache line from the main memory. int j; for (j = 0; j < 4; j++) mips_mem_read((pa & ~line_mask) + 8 * j, line->data + j, 8); line->tag = tag; Icache_lru_touch(set->Icache_lru, i); cache_hit: // Finally, fetch the data from the cache. mstate->ibuf[mstate->lru_ibuf].tag = pa >> log2_icache_line; mstate->ibuf[mstate->lru_ibuf].line = line->data; mstate->lru_ibuf = !mstate->lru_ibuf; return swizzle_word(line->data[(pa & line_mask) / 8], va); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/types.h�����������������������������������������������������������0000644�0001750�0000144�00000002016�10541455476�016742� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _SKYEYE_MIPS_TYPES_H_ #define _SKYEYE_MIPS_TYPES_H_ #include "inttypes.h" /* Fundamental types */ typedef UInt32 VA; //Virtual address typedef UInt32 PA; //Physical address typedef UInt32 Instr; //Instruction /* Width of the MIPS address space. * static const int paddr_width = 36; */ #define paddr_width 32 /* Caching algorithm numbers */ #define noncoherent_write_through 0 #define noncoherent_write_allocate 1 #define uncached 2 #define noncoherent_write_back 3 #define exclusive 4 #define exclusive_on_write 5 #define update_on_write 6 /* Hardware data types */ #define byte 0 #define halfword 1 #define triplebyte 2 #define word 3 #define quintibyte 4 #define sextibyte 5 #define septibyte 6 #define doubleword 7 /* The caching algorithm is stored as part of the physical address, * using the same encoding as that of XKPHYS address space region. */ static int coherency_algorithm(PA pa) //Shi yang 2006-08-08 { return bits(pa, 31, 29); } #endif //end of _SKYEYE_MIPS_TYPES_H_ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/mipsmem.c���������������������������������������������������������0000644�0001750�0000144�00000026456�11006337414�017242� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "skyeye_config.h" #include "mipsdef.h" #include "emul.h" mips_mem_state_t mips_mem; mips_mem_bank_t *mips_global_mbp; //This is the memory banks congfigure variable extern mips_mem_config_t mips_mem_config; extern MIPS_State* mstate; extern FILE * skyeye_logfd; void mips_mem_reset () { int i, num, bank; FILE *f; unsigned char *p; long s; UInt32 swap; mips_mem_config_t *mc = &mips_mem_config; mips_mem_bank_t *mb = mc->mem_banks; num = mc->current_num; for (i = 0; i < num; i++) { bank = i; if (mips_mem.rom[bank]) free (mips_mem.rom[bank]); //chy 2003-09-21: if mem type =MEMTYPE_IO, we need not malloc space for it. mips_mem.rom_size[bank] = mb[bank].len; if (mb[bank].type != MEMTYPE_IO) { mips_mem.rom[bank] = malloc (mb[bank].len); if (!mips_mem.rom[bank]) { fprintf (stderr, "SKYEYE: mem_reset: Error allocating mem for bank number %d.\n", bank); exit (-1); } if (mb[bank].filename && (f = fopen (mb[bank].filename, "r"))) { if (fread (mips_mem.rom[bank], 1, mb[bank].len, f) <= 0) { perror ("fread"); fprintf (stderr, "Failed to load '%s'\n", mb[bank].filename); skyeye_exit (-1); } fclose (f); p = (char *) mips_mem.rom[bank]; s = 0; while (s < mips_mem.rom_size[bank]) { if (mstate->bigendSig == 1) /*big enddian? */ swap = ((UInt32) p[3]) | (((UInt32) p[2]) << 8) | (((UInt32) p[1]) << 16) | (((UInt32) p[0]) << 24); else swap = ((UInt32) p[0]) | (((UInt32) p[1]) << 8) | (((UInt32) p[2]) << 16) | (((UInt32) p[3]) << 24); *(UInt32 *) p = swap; p += 4; s += 4; } /*ywc 2004-03-30 */ if (mb[bank].type == MEMTYPE_FLASH) { printf ("Loaded FLASH %s\n", mb[bank].filename); } else if (mb[bank].type == MEMTYPE_RAM) { printf ("Loaded RAM %s\n", mb[bank].filename); } else if (mb[bank].type == MEMTYPE_ROM) { printf ("Loaded ROM %s\n", mb[bank].filename); } } else if (mb[bank].filename[0] != '\0') { perror (mb[bank].filename); fprintf (stderr, "bank %d, Couldn't open boot ROM %s - execution will " "commence with the debuger.\n", bank, mb[bank].filename); skyeye_exit (-1); } } } /*end for(i = 0;i < num; i++) */ } // the address used here is the physical address UInt32 mips_real_read_byte (UInt32 addr) { UInt32 data; UInt32 offset; // the data is stored in the rom place in bunk(mips_global_mbp - mips_mem_config->mem_banks), data = mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks][(addr - mips_global_mbp->addr) >> 2]; offset = (((UInt32) mstate->bigendSig * 3) ^ (addr & 3)) << 3; //Shi yang 2006-08-18 return (data >> offset) & 0xffL; } UInt32 mips_real_read_halfword (UInt32 addr) { UInt32 data; UInt32 offset; // the data is stored in the rom place in bunk(mips_global_mbp - mips_mem_config->mem_banks), data = mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks][(addr - mips_global_mbp-> addr) >> 2]; offset = (((UInt32) mstate->bigendSig * 2) ^ (addr & 2)) << 3; //Shi yang 2006-08-18 return ((data >> offset) & 0xffff); } UInt32 mips_real_read_word (UInt32 addr) { UInt32 data; UInt32 offset; data = mips_mem.rom[(mips_global_mbp - mips_mem_config.mem_banks)][(addr - mips_global_mbp-> addr) >> 2]; // fprintf(skyeye_logfd,"after real_read_word addr=0x%x,pc=0x%x, data=0x%x\n", addr, mstate->pc, mips_mem.rom[0][(0x3c5ed8 >> 2)]); return data; } UInt64 mips_real_read_doubleword (UInt32 addr) { UInt64 data; data = mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks][(addr - mips_global_mbp-> addr) >> 3]; return data ; } void mips_real_write_byte (UInt32 addr, UInt32 data) { UInt32 *temp; UInt32 offset; temp = &(mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks][(addr - mips_global_mbp->addr) >> 2]); offset = (((UInt32) mstate->bigendSig * 3) ^ (addr & 3)) << 3; //Shi yang 2006-08-18 *temp = (*temp & ~(0xffL << offset)) | ((data & 0xffL) << offset); } void mips_real_write_halfword ( UInt32 addr, UInt32 data) { UInt32 *temp; UInt32 offset; temp = &(mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks][(addr - mips_global_mbp-> addr) >> 2]); offset = (((UInt32) mstate->bigendSig * 2) ^ (addr & 2)) << 3; //Shi yang 2006-08-18 *temp = (*temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset); } void mips_real_write_word (UInt32 addr, UInt32 data) { UInt32 *temp; //fprintf(skyeye_logfd,"before addr=0x%x,pc=0x%x,data=0x%x\n", addr, mstate->pc, mips_mem.rom[0][(0x3c5ed8 >> 2)]); temp = &(mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks] [(addr - mips_global_mbp->addr) >> 2]); *temp = data; //fprintf(skyeye_logfd,"after addr=0x%x,pc=0x%x, data=0x%x\n", addr, mstate->pc, mips_mem.rom[0][(0x3c5ed8 >> 2)]); } void mips_real_write_doubleword ( UInt32 addr, UInt64 data) { mips_mem.rom[mips_global_mbp - mips_mem_config.mem_banks][(addr - mips_global_mbp->addr) >> 3] =data; } //Flash address space UInt32 mips_flash_read_byte (UInt32 addr) { return mips_real_read_byte(addr); } UInt32 mips_flash_read_halfword (UInt32 addr) { return mips_real_read_halfword(addr); } UInt32 mips_flash_read_word (UInt32 addr) { return mips_real_read_word(addr); } UInt64 mips_flash_read_doubleword (UInt32 addr) { return mips_real_read_doubleword(addr); } void mips_flash_write_byte (UInt32 addr, UInt32 data) { mips_real_write_byte(addr, data); } void mips_flash_write_halfword (UInt32 addr, UInt32 data) { mips_real_write_halfword(addr, data); } void mips_flash_write_word (UInt32 addr, UInt32 data) { mips_real_write_word(addr, data); } void mips_flash_write_doubleword (UInt32 addr, UInt64 data) { mips_real_write_doubleword(addr, data); } //these fuctions are used for warning void mips_warn_write_byte (UInt32 addr, UInt32 data) { fprintf (stderr, "SKYEYE: WARNING: illegal write byte to 0x%x of 0x%x @ 0x%x\n", addr, data, mstate->pc); } void mips_warn_write_halfword (UInt32 addr, UInt32 data) { fprintf (stderr, "SKYEYE: WARNING: illegal write halfword to 0x%x of 0x%x @ 0x%x\n", addr, data, mstate->pc); } void mips_warn_write_word (UInt32 addr, UInt32 data) { fprintf (stderr, "SKYEYE: WARNING: illegal write word to 0x%x of 0x%x @ 0x%x\n", addr, data, mstate->pc); } mips_mem_bank_t* mips_bank_ptr (UInt32 addr) { // chy 2005-01-06 add teawater's codes for speed,but I tested it, can not find the big improve // chy 2005-01-06 maybe some one examines below. now I commit teatwater's codes //mem_bank_t *mbp; //---------teawater add for arm2ia32 2004.12.04----------------- //mem_bank_t *mbp; static mips_mem_bank_t *mbp = NULL; if (mbp) { if ((mbp->addr <= addr) && ((addr - mbp->addr) < mbp->len)) return (mbp); } //printf("mem_bank: 0x%08x\n",mips_mem_config.mem_banks); //AJ2D---------------------------------------------------------- //search for the proper memory bank for (mbp = mips_mem_config.mem_banks; mbp->len; mbp++) if ((mbp->addr <= addr) && ((addr - mbp->addr) < mbp->len)) { //printf("mbp addr: 0x%08x, mbp len: 0x%08x, addr: 0x%08x\n",mbp->addr, mbp->len, addr); return (mbp); } return (NULL); } void mips_mem_write_byte (UInt32 phys_addr, UInt32 v) { //translate the physical address to the 32 bits UInt32 addr = bits(phys_addr, 31, 0); //get the memory bank of the address mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp && mips_global_mbp->write_byte) { mips_global_mbp->write_byte (addr, v); } else { fprintf(stderr,"mips memory write error in %s, addr=0x%x,pc=0x%x..\n",__FUNCTION__,addr, mstate->pc); skyeye_exit(-1); } } void mips_mem_write_halfword (UInt32 phys_addr, UInt32 v) { UInt32 addr = bits(phys_addr, 31, 0); mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp && mips_global_mbp->write_halfword) { /*ywc 2005-03-31 */ /*ywc 2005-04-22 move it to real_write_halfword */ /* if(!skyeye_config.no_dbct){ //teawater add for arm2x86 2005.03.18---------------------------------- tb_setdirty(state, addr, mbp); //AJ2D---------------------------------------------------------- } */ //mbp->write_halfword(state, addr, data); mips_global_mbp->write_halfword (addr, v); } else { fprintf(stderr,"mips memory write error in %s..\n",__FUNCTION__); skyeye_exit(-1); } } void mips_mem_write_word (UInt32 phys_addr, UInt32 v) { UInt32 addr = bits(phys_addr, 31, 0); mips_global_mbp = mips_bank_ptr (addr); //if (mbp && mbp->write_halfword){ if (mips_global_mbp && mips_global_mbp->write_word) { /*ywc 2005-03-31 */ /*ywc 2005-04-22 move it to real_write_halfword */ /* if(!skyeye_config.no_dbct){ //teawater add for arm2x86 2005.03.18---------------------------------- tb_setdirty(state, addr, mbp); //AJ2D---------------------------------------------------------- } */ //mbp->write_halfword(state, addr, data); mips_global_mbp->write_word (addr, v); } else { fprintf(stderr,"mips memory write error in %s,addr=0x%x, pc=0x%x..\n", __FUNCTION__, addr, mstate->pc); exit(-1); } } void mips_mem_write_doubleword (UInt64 phys_addr, UInt64 v) { UInt32 addr = bits(phys_addr, 31, 0); mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp && mips_global_mbp->write_doubleword) { /*ywc 2005-03-31 */ /*ywc 2005-04-22 move it to real_write_halfword */ /* if(!skyeye_config.no_dbct){ //teawater add for arm2x86 2005.03.18---------------------------------- tb_setdirty(state, addr, mbp); //AJ2D---------------------------------------------------------- } */ //mbp->write_halfword(state, addr, data); mips_global_mbp->write_doubleword (addr, v); } else { fprintf(stderr,"mips memory write error in %s..\n",__FUNCTION__); skyeye_exit(-1); } } UInt32 mips_mem_read_byte (UInt32 phys_addr) { UInt32 addr = bits(phys_addr, 31, 0); mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp && mips_global_mbp->read_byte) return mips_global_mbp->read_byte (addr); else { return 0; } } UInt32 mips_mem_read_halfword (UInt32 phys_addr) { UInt32 addr = bits(phys_addr,31,0); mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp && mips_global_mbp->read_halfword) return mips_global_mbp->read_halfword (addr); else { return 0; } } UInt32 mips_mem_read_word (UInt32 phys_addr) { UInt32 addr = bits(phys_addr, 31, 0); mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp && mips_global_mbp->read_word) return mips_global_mbp->read_word (addr); else { return 0; } } UInt64 mips_mem_read_doubleword (UInt64 phys_addr) { UInt32 addr = bits(phys_addr, 31, 0); mips_global_mbp = mips_bank_ptr (addr); if (mips_global_mbp && mips_global_mbp->read_doubleword) return mips_global_mbp->read_doubleword (addr); else { return 0; } } void mips_mmu_write_byte (MIPS_State* mstate, UInt32 vir_addr, UInt32 v) { //translate the virtual address to phsical address PA phys_addr ; if( translate_vaddr(mstate, (VA)vir_addr, data_store, &phys_addr) == TLB_SUCC) mips_mem_write_byte ((UInt32)phys_addr, v); } void mipsMul_WriteByte (MIPS_State* mstate, UInt32 vir_addr, UInt32 v) { mips_mmu_write_byte (mstate, vir_addr, v); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/tlb.c�������������������������������������������������������������0000644�0001750�0000144�00000013030�11006337414�016334� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <string.h> #include <stdio.h> #include "emul.h" extern MIPS_State* mstate; // Reset the Translation Lookaside Buffer. void reset_tlb(MIPS_State* mstate) { // Clear the TLB map. memset(mstate->tlb_map, 0, sizeof(mstate->tlb_map)); // Add all TLB entries to the last (otherwise unused) TLB chain. int i; for (i = 0; i < tlb_size; ++i) { mstate->tlb[i].asid = invalid_asid; mstate->tlb[i].index = i; mstate->tlb[i].hash = tlb_map_size; if (mstate->tlb_map[tlb_map_size]) mstate->tlb_map[tlb_map_size]->prev = &mstate->tlb[i]; mstate->tlb[i].next = mstate->tlb_map[tlb_map_size]; mstate->tlb[i].prev = 0; mstate->tlb_map[tlb_map_size] = &mstate->tlb[i]; } } // Set a TLB entry from EntryHi and EntryLo0. void set_tlb_entry(MIPS_State* mstate, int n) { int hash = tlb_hash(mstate->cp0[EntryHi]); if ((unsigned int)n >= tlb_size) return; // Remove entry from the current TLB hash chain. if (mstate->tlb[n].next) mstate->tlb[n].next->prev = mstate->tlb[n].prev; if (mstate->tlb[n].prev) mstate->tlb[n].prev->next = mstate->tlb[n].next; else mstate->tlb_map[mstate->tlb[n].hash] = mstate->tlb[n].next; // Set the new entry. //mstate->tlb[n].hi = (mstate->cp0[EntryHi] & bitsmask(11, 0)); //Shi yang 2006-08-11 mstate->tlb[n].hi = mstate->cp0[EntryHi] ;/* Use 8k map */ mstate->tlb[n].lo_reg[0] = mstate->cp0[EntryLo0]; mstate->tlb[n].lo_reg[1] = mstate->cp0[EntryLo1]; if (bit(mstate->cp0[EntryLo0], EntryLo_G)) mstate->tlb[n].asid = global_asid; else mstate->tlb[n].asid = bits(mstate->cp0[EntryHi], 11, 6); mstate->tlb[n].index = n; mstate->tlb[n].hash = hash; //printf("In %s,index=0x%x\n", __FUNCTION__, n); // Add the entry to the new TLB hash chain. if (mstate->tlb_map[hash]) mstate->tlb_map[hash]->prev = &mstate->tlb[n]; mstate->tlb[n].next = mstate->tlb_map[hash]; mstate->tlb[n].prev = 0; mstate->tlb_map[hash] = &mstate->tlb[n]; } /* The TLB lookup routine. MIPS TLBs are fully-associative, so we use a hash * table to look them up. Dynamic allocation of the TLB nodes isn't needed as * the number of entries is fixed. This is used only by translate_vaddr() and * the TLBP instruction. It returns a pointer to the TLB entry or 0 on a TLB * miss. */ TLBEntry * probe_tlb(MIPS_State* mstate, VA va) { int hash = tlb_hash(va); TLBEntry* e; //printf("In %s, hash=0x%x\n", __FUNCTION__, hash); for (e = mstate->tlb_map[hash]; e; e = e->next) { //if (asid_match(mstate->asid, e->asid) && (bit(e->lo, EntryLo_G) || va_match((va & (bitsmask(11, 0))), e->hi))) //Shi yang 2006-08-11 if((va >> 13) == (e->hi >> 13)){ //printf("In %s, tlb found, e.index=0x%x, e.hi=0x%x\n", __FUNCTION__, e->index, e->hi); return e; } } return NULL; } // Perform a full TLB lookup. int translate_vaddr(MIPS_State* mstate, VA va, int type, PA * pa) { UInt32 region_type; // one of SR_UX, SR_SX or SR_KX // Decode the virtual address. if ((vaddr_region(va) >= vaddr_region(kuseg)) && (vaddr_region(va) < vaddr_region(kseg0))) { //KUSEG's most significant three bits are 0xx /* The user region is valid in every mode, but we still have * to handle the 32/64 bit mode differences. */ region_type = KUSEG; } else if (vaddr_region(va) == vaddr_region(kseg0)) { //KSEG0's most significant three bits are 100 if (mstate->mode & umode) { //User mode access kernel space process_address_error(type, va); return TLB_FAIL; // shut up the compiler } else { // Proceed with the TLB lookup. region_type = KSEG0; va = va & ~0x80000000; *pa = va; return TLB_SUCC; } } else if (vaddr_region(va) == vaddr_region(kseg1)) { //KSEG1's most significant three bits are 101 if (mstate->mode & umode) { process_address_error(type, va); return TLB_FAIL; // shut up the compiler } else { // The physical address is already encoded. region_type = KSEG1; va = va & ~0xE0000000; *pa = va; return TLB_SUCC; } } else { if (mstate->mode & umode) { process_address_error(type, va); return TLB_FAIL; // shut up the compiler } else { // Proceed with the TLB lookup. region_type = KSEG2; } } //fprintf(stderr, "Warning:Can not find entry for mips tlb in %s,va=0x%x,pc=0x%x\n",__FUNCTION__, va, mstate->pc); // Now, we are ready to probe the TLB. TLBEntry* entry = probe_tlb(mstate, va); if (!entry){ process_tlb_refill(mstate, type, va); // TLB miss return TLB_EXP; /* */ } /* If odd,we use Lo 1 register, else use Lo 0 */ UInt32 lo = entry->lo_reg[(va >> 12) & 0x1]; // Filter TLB entries marked invalid. if (!(lo & 0x2)){ /*test Valid bit in lo of TLB */ //printf("In %s, invalid entry->lo=0x%x,va=0x%x,pc=0x%x\n", __FUNCTION__, lo, va, mstate->pc); //skyeye_exit(-1); process_tlb_invalid(mstate, type, va); // TLB invalid. return TLB_EXP; } // Fiter TLB entries marked read-only. if (type == data_store && !(lo & 0x4)){ //printf("In %s, tlb_modified exp!\n", __FUNCTION__); //process_tlb_modified(mstate, va); // TLB Modified exception. //return TLB_EXP; } // Finally, retrieve the mapping. //*pa = ((mstate->cp0[EntryLo0] & (bitsmask(11, 0))) | (va & (bitsmask(31, 12)))); //Shi yang 2006-08-11 /* we use 20 bit of lo , since we only implement 4k page map */ *pa = ((lo << 6) & 0xFFFFF000) | (va & 0xFFF); //printf("Get pa 0x%x by entry %d,entry.lo=0x%x,lo << 2=0x%x,va=0x%x\n", *pa, entry->index, lo, (lo << 6), va); return TLB_SUCC; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/emul.c������������������������������������������������������������0000644�0001750�0000144�00000023136�11006337414�016525� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "emul.h" /* mips_regdefs.c - necessary mips definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 07/06/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include <stdio.h> #include <stdlib.h> extern MIPS_State* mstate; /* Address decoder macros. * Bits 29, 30 and 31 of the virtual address select the user or kernel address spaces. */ int vaddr_region(VA va) { return bits(va, 31, 29); } int vaddr_compat_region(UInt32 va) { return bits(va, 31, 30); } int get_random(MIPS_State* mstate) //Fix me: Shi yang 2006-08-10 { int wired = mstate->cp0[Wired]; int free = tlb_size - wired; return (tlb_size - 1 - wired + (mstate->now - mstate->random_seed)) % free + wired; } void enter_kernel_mode(MIPS_State* mstate) { //copy_bits(mstate->cp0[SR], (bits(mstate->cp0[SR], 3, 0) << 2), 5, 2); //Shi yang 2006-08-10 //clear_bits(mstate->cp0[SR], 1, 0); //Enter kernel mode mstate->mode = kmode; } void leave_kernel_mode(MIPS_State* mstate) { copy_bits(mstate->cp0[SR], (bits(mstate->cp0[SR], 5, 2)), 3, 0); copy_bits(mstate->cp0[SR], (bits(mstate->cp0[SR], 3, 2) << 4), 5, 4); if (bit(mstate->cp0[SR], 1) == 0) mstate->mode |= kmode; //From kernel mode to kernel mode else mstate->mode = umode; //From kernel mode to user mode } /* An ASID is represented by a 16 bit integer that is either a positive * (non-zero) ASID, complemented if the G bit is also set. asid_match() * checks two ASIDs for equivalence. Yet another demonstration of the * versatility of exclusive-or. ;) */ int asid_match(Int16 asid1, Int16 asid2) { return (asid1 ^ asid2) <= 0; } /* Operations on the TLB lookup map. The map is a hash table indexed by a * hash value computed from the ASID and the bits of virtual page number * unaffected by any page mask. The result of the map lookup is a TLB * entry. The hash function doesn't provide an ideal distribution, but as * a minimum, it maintains a separate hash chain per ASID, and provides * good distribution at least for sparse address spaces. The hash table * always has an extra entry pointing to an invalid page. */ int tlb_hash(VA va) { return (bits(va, 31, 13) % tlb_map_size); } int va_match(VA va1, VA va2) { return !(va1 ^ va2); //Shi yang 2006-08-11 } // I-cache buffer operations. int ibuf_match(PA pa, PA tag) //Shi yang 2006-08-10 { return ((pa >> log2_icache_line) ^ tag) == 0; } // Some state information constants. int allow_xinstr(MIPS_State* mstate) { return mstate->mode & (kmode|xmode); } int branch_delay_slot(MIPS_State* mstate) //Shi yang 2006-08-10 { return mstate->pipeline == branch_delay; } void process_address_error(MIPS_State* mstate, int type, VA va) { int exc = (type == data_store) ? EXC_AdES : EXC_AdEL; mstate->cp0[BadVAddr] = va; process_exception(mstate, exc, common_vector); } void process_tlb_refill(MIPS_State* mstate, int type, VA va) { int exc = (type == data_store) ? EXC_TLBS : EXC_TLBL; int vec = tlb_refill_vector; mstate->cp0[BadVAddr] = va; mstate->cp0[Context] = copy_bits(mstate->cp0[Context], bits(mstate->cp0[BadVAddr], 31, 13), 20, 2); //Shi yang 2006-08-10 //mstate->cp0[EntryHi] = (va & (bitsmask(11, 0))) // | (bits(mstate->asid, 5, 0) << 6); mstate->cp0[EntryHi] = va & 0xFFFFE000; process_exception(mstate, exc, vec); } void process_tlb_invalid(MIPS_State* mstate, int type, VA va) { int exc = (type == data_store) ? EXC_TLBS : EXC_TLBL; mstate->cp0[BadVAddr] = va; mstate->cp0[Context] = copy_bits(mstate->cp0[Context], bits(mstate->cp0[BadVAddr], 31, 13), 20, 2); //Shi yang 2006-08-10 //mstate->cp0[EntryHi] = (va & (bitsmask(11, 0))) // | (bits(mstate->asid, 5, 0) << 6); mstate->cp0[EntryHi] = va & 0xFFFFE000; process_exception(mstate, exc, common_vector); } void process_tlb_modified(MIPS_State* mstate, VA va) { printf("In %s, va=0x%x\n", __FUNCTION__, va); mstate->cp0[BadVAddr] = va; mstate->cp0[Context] = copy_bits(mstate->cp0[Context], bits(mstate->cp0[BadVAddr], 31, 13), 20, 2); mstate->cp0[EntryHi] = va & 0xFFFFE000; process_exception(mstate, EXC_Mod, common_vector); } void process_bus_error(MIPS_State* mstate, int type) { int exc = (type == instr_fetch) ? EXC_IBE : EXC_DBE; process_exception(mstate, exc, common_vector); } void process_integer_overflow(MIPS_State* mstate) { process_exception(mstate,EXC_Ov, common_vector); } void process_trap(MIPS_State* mstate) { printf("Begin process_trap.\n"); process_exception(mstate, EXC_Tr, common_vector); } void process_syscall(MIPS_State* mstate) { //printf("syscall.\n"); process_exception(mstate, EXC_Sys, common_vector); } void process_breakpoint(MIPS_State* mstate) { process_exception(mstate, EXC_Bp, common_vector); } void process_reserved_instruction(MIPS_State* mstate) { fprintf(stderr,"In %s,pc=0x%x", __FUNCTION__, mstate->pc); skyeye_exit(-1); process_exception(mstate, EXC_RI, common_vector); } void process_coprocessor_unusable(MIPS_State* mstate, int c) { process_exception(mstate, EXC_CpU | (c << (Cause_CE_First)), common_vector); } void process_fp_exception(MIPS_State* mstate) { process_exception(mstate,EXC_FPE, common_vector); } void process_interrupt(MIPS_State* mstate) { process_exception(mstate,EXC_Int, common_vector); } /* Endianess parameters. The data received from the memory bus is always * in the host byte order, and uses host byte addressing. */ int big_endian_mem(MIPS_State* mstate) { return bit(mstate->cp0[Config], Config_BE); } int reverse_endian(MIPS_State* mstate) { return mstate->mode & rmode; } int big_endian_cpu(MIPS_State* mstate) { return mstate->mode & bmode; } UInt32 swizzle_word(UInt32 x, UInt32 addr) //Fix me: Shi yang { return x; //Shi yang 2006-08-18 } UInt8 swizzle_byte(UInt32 x, UInt32 addr) { int offset; offset = (((UInt32) mstate->bigendSig * 3) ^ (addr & 3)) << 3; //Shi yang 2006-08-18 return (x >> offset) & 0xffL; } UInt16 swizzle_doublebyte(UInt32 x, UInt32 addr) { int offset; offset = (((UInt32)mstate->bigendSig * 2) ^ (addr & 2)) << 3; //Shi yang 2006-08-18 return (x >> offset) & 0xffffL; } inline Int32 sign_extend_Int32(Int32 x, int n) { if (((Int32)-1 >> 1) < 0) { // Host platform does arithmetic right shifts. Int32 y = x; return y << (8 * sizeof(Int32) - n) >> (8 * sizeof(Int32) - n); } else if (n < 8 * sizeof(Int32)) { // We have to manually patch the high-order bits. if (bit(x, n - 1)) return set_bits(x, 8 * sizeof(Int32) - 1, n); else return clear_bits(x, 8 * sizeof(Int32) - 1, n); } } inline UInt32 sign_extend_UInt32(UInt32 x, int n) { if (((UInt32)-1 >> 1) < 0) { // Host platform does arithmetic right shifts. UInt32 y = x; return y << (8 * sizeof(UInt32) - n) >> (8 * sizeof(UInt32) - n); } else if (n < 8 * sizeof(UInt32)) { // We have to manually patch the high-order bits. if (bit(x, n - 1)) return set_bits(x, 8 * sizeof(UInt32) - 1, n); else return clear_bits(x, 8 * sizeof(UInt32) - 1, n); } } inline Int64 sign_extend_Int64(Int64 x, int n) { if (((Int64)-1 >> 1) < 0) { // Host platform does arithmetic right shifts. Int64 y = x; return y << (8 * sizeof(Int64) - n) >> (8 * sizeof(Int64) - n); } else if (n < 8 * sizeof(Int64)) { // We have to manually patch the high-order bits. if (bit(x, n - 1)) return set_bits(x, 8 * sizeof(Int64) - 1, n); else return clear_bits(x, 8 * sizeof(Int64) - 1, n); } } inline UInt64 sign_extend_UInt64(UInt64 x, int n) { if (((UInt64)-1 >> 1) < 0) { // Host platform does arithmetic right shifts. UInt64 y = x; return y << (8 * sizeof(UInt64) - n) >> (8 * sizeof(UInt64) - n); } else if (n < 8 * sizeof(UInt64)) { // We have to manually patch the high-order bits. if (bit(x, n - 1)) return set_bits(x, 8 * sizeof(UInt64) - 1, n); else return clear_bits(x, 8 * sizeof(UInt64) - 1, n); } } // Specialisations for 32 and 64 bit types. inline void divide_Int32(Int32 a, Int32 b) { if (32 <= sizeof(int)) { div_t r = div((int)(a), (int)(b)); DivResult(r.quot, r.rem); } else { ldiv_t r = ldiv((long)(a),(long)(b)); DivResult(r.quot, r.rem); } } inline void divide_UInt32(UInt32 a, UInt32 b) { if (32 < sizeof(long)) { ldiv_t r = ldiv((long)(a), (long)(b)); DivResult(r.quot, r.rem); } else { DivResult(a / b, a % b); } } inline void divide_Int64(Int64 a, Int64 b) { if (64 <= sizeof(long)) { ldiv_t r = ldiv((long)(a), (long)(b)); DivResult(r.quot, r.rem); } else if ((Int64)(-2) % (Int64)(3) < 0) // Hardware division rounds towards zero. DivResult(a / b, a % b) else { // Hardware division rounds towards negative infinity, so fix it. if ((a ^ b) >= 0) DivResult(a / b, a % b) else if (a < 0) DivResult(-(-a / b), -(-a % b)) else DivResult(-(a / -b), -(a % -b)) } } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/cache.c�����������������������������������������������������������0000644�0001750�0000144�00000001464�11006337414�016626� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "instr.h" #include "emul.h" int decode_cache(MIPS_State* mstate, Instr instr) //Use in Cache Instruction, it's unuseable in R3000 { // CP0 is usable in kernel mode or when the CU bit in SR is set. if (!(mstate->mode & kmode) && !bit(mstate->cp0[SR], SR_CU0)) process_coprocessor_unusable(mstate, 0); VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)]; PA pa; if(translate_vaddr(mstate, va, cache_op, &pa) != 0){ return nothing_special; } if (pa != bad_pa) { if (bit(instr, 16)) { // Control data cache. control_dcache(mstate, va, pa, bits(instr, 20, 18), bit(instr, 17)); } else { // Control instruction cache. control_icache(mstate, va, pa, bits(instr, 20, 18), bit(instr, 17)); } } return nothing_special; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/cp0.c�������������������������������������������������������������0000644�0001750�0000144�00000023243�11006337414�016244� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* cp0.c - read/write for cp0 register Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/21/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include "skyeye_config.h" #include "instr.h" #include "emul.h" #include <stdio.h> // Access to the System Coprocessor registers. extern FILE *skyeye_logfd; UInt32 read_cp0(MIPS_State* mstate, int n, int sel) { switch (n) { case Index: { #if 0 mstate->cp0[Index] = clear_bits(x, 30, 17); //Shi yang 2006-08-11 mstate->cp0[Index] = clear_bits(x, 7, 0); #endif //printf("In %s, Index,x=0x%x\n", __FUNCTION__, mstate->cp0[Index]); return mstate->cp0[Index]; } case Random: { return get_random(mstate); } case Count: { return mstate->cp0[Count] + ((mstate->now - mstate->count_seed) / 2); } case Cause: { //printf("KSDBG:read cause=0x%x, pc=0x%x\n", mstate->cp0[Cause], mstate->pc); return mstate->cp0[Cause]; //return mstate->cp0[Cause] | (mstate->events & bitsmask(Cause_IP_Last, Cause_IP_First)); } case EPC: { //fprintf(stderr, "read EPC, EPC = 0x%x, pc=0x%x\n", mstate->cp0[EPC], mstate->pc); return mstate->cp0[EPC]; } case PRId: { return 0x04030200; /* the id of au1200 */ } case Config: { if(sel) /* config1 */ return 0x3E63318a; /* config1 for au1200 */ else return 0x80008083; /* config0 for au1200 */ } default: return mstate->cp0[n]; } } void write_cp0(MIPS_State* mstate, int n, UInt32 x) { switch (n) { case Index: { #if 0 mstate->cp0[Index] = clear_bits(x, 30, 17); //Shi yang 2006-08-11 mstate->cp0[Index] = clear_bits(x, 7, 0); #endif mstate->cp0[Index] = x; //printf("In %s,Write Index,x=0x%x\n", __FUNCTION__, x); break; } case Random: //Random register is a read-only register { break; } case EntryLo0: { //mstate->cp0[EntryLo0] = clear_bits(x, 7, 0); //Shi yang 2006-08-11 mstate->cp0[EntryLo0] = x; //printf("In %s,Write lo,x=0x%x,pc=0x%x\n", __FUNCTION__, x, mstate->pc); break; } case EntryLo1: { //mstate->cp0[EntryLo0] = clear_bits(x, 7, 0); //Shi yang 2006-08-11 mstate->cp0[EntryLo1] = x; //printf("In %s,Write lo1,x=0x%x,pc=0x%x,\n", __FUNCTION__, x, mstate->pc); break; } case Context: { mstate->cp0[Context] = clear_bits(x, 1, 0); //Shi yang 2006-08-11 break; } case BadVAddr: //BadVAddr register is a read-only register { break; } case Count: { mstate->count_seed = mstate->now; mstate->cp0[Count] = x; mstate->now = mstate->now + (mstate->cp0[Compare] - (mstate->cp0[Count] + ((mstate->now - mstate->count_seed) / 2))) * 2; break; } case EntryHi: { mstate->asid = bits(x, 11, 6); //Shi yang 2006-08-11 mstate->cp0[EntryHi] = x & (bitsmask(5, 0) | bitsmask(vaddr_width - 1, 12) | bitsmask(11, 6)); break; } case Compare: { //fprintf(stderr, "KSDBG: in %s,write 0x%x to compare\n", __FUNCTION__, x); mstate->cp0[Compare] = x; mstate->events = clear_bit(mstate->events, 7 + Cause_IP_First); mstate->now = mstate->now + (mstate->cp0[Compare] - (mstate->cp0[Count] + ((mstate->now - mstate->count_seed) / 2))) * 2; mstate->cp0[Cause] &= 0xFFFF7FFF; /* clear IP bit in cause register for timer */ break; } case SR: { mstate->cp0[SR] = x & ~(bitsmask(27, 26) | bitsmask(24, 23) | bitsmask(7, 6)); //Shi yang 2006-08-11 //leave_kernel_mode(mstate); break; } case Cause: { //fprintf(stderr, "write cause, cause = 0x%x,pc=0x%x\n", x, mstate->pc); mstate->events |= x & bitsmask(Cause_IP1, Cause_IP0); break; } case EPC: { //fprintf(stderr, "write EPC, EPC = 0x%x, pc=0x%x\n", x, mstate->pc); mstate->cp0[EPC] = x; break; } case PRId: //PRId register is a read-only register { break; } default: printf("Reg=0x%x, not implemented instruction in %s\n",n, __FUNCTION__); break; } } int decode_cop0(MIPS_State* mstate, Instr instr) { // CP0 is usable in kernel more or when the CU bit in SR is set. if (!(mstate->mode & kmode) && !bit(mstate->cp0[SR], SR_CU0)) process_coprocessor_unusable(mstate, 0); /* Only COP0, MFC0 and MTC0 make sense, although the R3K * manuals say nothing about handling the others. */ if (bit(instr, 25)) { switch (funct(instr)) { case TLBR: { // Read Indexed TLB Entry TLBEntry* e = &mstate->tlb[bits(mstate->cp0[Index], 13, 6)]; //Shi yang 2006-08-11 mstate->cp0[EntryHi] = e->hi | (bits(e->asid, 5, 0) << 6); mstate->cp0[EntryLo0] = e->lo_reg[0]; mstate->cp0[EntryLo1] = e->lo_reg[1]; return nothing_special; } case TLBWI: { // Write Indexed TLB Entry //printf("TLBWI,index=0x%x, pc=0x%x\n", mstate->cp0[Index], mstate->pc); set_tlb_entry(mstate, mstate->cp0[Index]); //Shi yang 2006-08-11 return nothing_special; } case TLBWR: { // Write Random TLB Entry //printf("TLBWR,index=0x%x, pc=0x%x\n", get_random(mstate), mstate->pc); set_tlb_entry(mstate, get_random(mstate)); return nothing_special; } case TLBP: { // Probe TLB For Matching Entry VA va = mstate->cp0[EntryHi]; //printf("TLBP, va=0x%x\n", va); TLBEntry* e = probe_tlb(mstate, va); //printf("TLBP, index=0x%x\n", e->index); mstate->cp0[Index] = (e) ? e->index : bitmask(31); return nothing_special; } case RFE: //Shi yang 2006-08-11 { printf("RFE, return from exp, pc=0x%x\n", mstate->pc); // Exception Return leave_kernel_mode(mstate); return nothing_special; } case ERET: { mstate->cp0[SR] &= 0xFFFFFFFD; /* Set Exl bit to zero */ //fprintf(stderr, "ERET, return from exp, v0=0x%x, pc=0x%x,epc=0x%x\n", mstate->gpr[2], mstate->pc, mstate->cp0[EPC]); mstate->pc = mstate->cp0[EPC]; //fprintf(stderr, "ERET, return from exp, epc=0x%x\n", mstate->cp0[EPC]); if(mstate->cp0[Cause] & 1 << Cause_IP2) skyeye_config.mach->mach_set_intr(0);/* clear the corresponding interrupt status register */ mstate->pipeline = branch_nodelay; return nothing_special; } default: process_reserved_instruction(mstate); return nothing_special; } } else { switch (rs(instr)) { case MFCz: { // Move From System Control Coprocessor mstate->gpr[rt(instr)] = read_cp0(mstate, rd(instr), sel(instr)); return nothing_special; } case DMFCz: { // Doubleword Move From System Control Coprocessor process_reserved_instruction(mstate); return nothing_special; } case CFCz: { // Move Control From Coprocessor return nothing_special; } case MTCz: { // Move To System Control Coprocessor write_cp0(mstate, rd(instr), mstate->gpr[rt(instr)]); return nothing_special; } case DMTCz: { // Doubleword Move To System Control Coprocessor process_reserved_instruction(mstate); return nothing_special; } case CTCz: { process_reserved_instruction(mstate); // Move Control To Coprocessor return nothing_special; } case BCz: { // Branch On Coprocessor Condition switch (rt(instr)) { case BCzF: case BCzT: case BCzFL: case BCzTL: process_reserved_instruction(mstate); return nothing_special; default: process_reserved_instruction(mstate); return nothing_special; } } default: process_reserved_instruction(mstate); return nothing_special; } } return nothing_special; } int decode_cop1(MIPS_State* mstate, Instr instr) { //fprintf(stderr, "in %s\n", __FUNCTION__); // CP0 is usable in kernel more or when the CU bit in SR is set. if (!(mstate->mode & kmode) && !bit(mstate->cp0[SR], SR_CU0)) process_coprocessor_unusable(mstate, 0); /* Only COP0, MFC0 and MTC0 make sense, although the R3K * manuals say nothing about handling the others. */ switch (function(instr)){ case WAIT: return nothing_special; default: //process_reserved_instruction(mstate); break; } switch (fmt(instr)){ case CF: if(fs(instr) == 0) mstate->gpr[ft(instr)] = mstate->fir; else fprintf(stderr, "In %s, not implement for CFC1 instruction\n", __FUNCTION__); break; default: //process_reserved_instruction(mstate); fprintf(stderr, "In %s,not implement instruction 0x%x\n", __FUNCTION__, instr); break; } return nothing_special; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/cpu.h�������������������������������������������������������������0000644�0001750�0000144�00000017035�10541455476�016374� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _CPU_H_ #define _CPU_H_ #include "types.h" /* Cute macros for defining VA constants. Note that this doesn't conflict with * the VA type as the macro gets expanded only if followed by "(". */ #define TVA(a, b) C32(a, b) //Shi yang 2006-08-08 /* System Control Coprocessor (CP0) registers */ #define Index 0 #define Random 1 #define EntryLo0 2 #define EntryLo1 3 #define Context 4 #define PageMask 5 #define Wired 6 // reserved = 7, #define BadVAddr 8 #define Count 9 #define EntryHi 10 #define Compare 11 #define SR 12 #define Cause 13 #define EPC 14 #define PRId 15 #define Config 16 #define LLAddr 17 #define WatchLo 18 #define WatchHi 19 #define XContext 20 // reserved = 21, // reserved = 22, // reserved = 23, // reserved = 24, // reserved = 25, #define ECC 26 #define CacheErr 27 #define TagLo 28 #define TagHi 29 #define ErrorEPC 30 // reserved = 31 /* CP0 register layout. For single-bit fields, only one constant is * defined. For multi-bit fields, two constants are defined: one for the * first (least-significant) bit of the field, and one for the * most-significant bit. */ /* Index Register (0) */ #define Index_First 8 #define Index_Last 13 #define CPO_Index_P 31 /* Random Register (1) */ #define Random_First 8 #define Random_Last 13 /* EntryLo0 (2), and EntryLo1 (3) Registers */ #define EntryLo_G 8 #define EntryLo_V 9 #define EntryLo_D 10 #define EntryLo_N 11 #define EntryLo_PFN_First 12 #define EntryLo_PFN_Last 31 /* Context Register (4) */ #define Context_BadVPN_First 2 #define Context_BadVPN_Last 20 #define Context_PTEBase_First 21 #define Context_PTEBase_Last 31 /* PageMask Register (5) */ #define PageMask_First 13 #define CPO_PageMask_Last 24 /* Wired Register (6) */ #define Wired_First 0 #define Wired_Last 5 // Bad Virtual Address Register (BadVAddr) (8) // Count Register (9) /* EntryHi Register (CP0 Register 10) */ #define EntryHi_ASID_First 8 #define EntryHi_ASID_Last 11 #define EntryHi_VPN2_First 12 #define EntryHi_VPN2_Last 31 // Compare Register (11) /* SR Register (12) */ #define SR_IEC 0 #define SR_KUC 1 #define SR_IEP 2 #define SR_KUP 3 #define SR_IEO 4 #define SR_KUO 5 #define SR_IM0 8 #define SR_IM1 9 #define SR_IM2 10 #define SR_IM3 11 #define SR_IM4 12 #define SR_IM5 13 #define SR_IM6 14 #define SR_IM7 15 #define SR_IM_First 8 #define SR_IM_Last 15 #define SR_ISC 16 #define SR_SWC 17 #define SR_PZ 18 #define SR_CM 19 #define SR_PE 20 #define SR_TS 21 #define SR_BEV 22 #define SR_DS_First 16 #define SR_DS_Last 24 #define SR_CU0 28 #define SR_CU1 29 #define SR_CU2 30 #define SR_CU3 31 #define SR_CU_First 28 #define SR_CU_Last 31 /* Cause Register (13) */ #define Cause_ExcCode_First 2 #define Cause_ExcCode_Last 6 #define Cause_IP0 8 #define Cause_IP1 9 #define Cause_IP2 10 #define Cause_IP3 11 #define Cause_IP4 12 #define Cause_IP5 13 #define Cause_IP6 14 #define Cause_IP7 15 #define Cause_IP_First 8 #define Cause_IP_Last 15 #define Cause_CE_First 28 #define Cause_CE_Last 29 #define Cause_BD 31 // Exception Program Counter (EPC) Register (14) /* Processor Revision Identifier (PRId) Register (15) */ #define CPO_PRId_Rev_First 0 #define CPO_PRId_Rev_Last 7 #define CPO_PRId_Imp_First 8 #define CPO_Imp_Rev_Last 15 /* Config Register (16) */ #define Config_K0_First 0 #define Config_K0_Last 2 #define Config_CU 3 #define Config_DB 4 #define Config_IB 5 #define Config_DC_First 6 #define Config_DC_Last 8 #define Config_IC_First 9 #define Config_IC_Last 11 #define Config_EB 13 #define Config_EM 14 #define Config_BE 15 #define Config_SM 16 #define Config_SC 17 #define Config_EW_First 18 #define Config_EW_Last 19 #define Config_SW 20 #define Config_SS 21 #define Config_SB_First 22 #define Config_SB_Last 23 #define Config_EP_First 24 #define Config_EP_Last 27 #define Config_EC_First 28 #define Config_EC_Last 30 #define Config_CM 31 // Load Linked Address (LLAddr) Register (17) /* WatchLo (18) and WatchHi (19) Registers */ #define WatchLo_W 0 #define WatchLo_R 1 #define WatchLo_PAddr0_First 3 #define WatchLo_PAddr0_Last 31 #define WatchHi_PAddr1_First 0 #define WatchHi_PAddr1_Last 3 /* XContext Register (20) */ #define XContext_BadVPN2_First 4 #define XContext_BadVPN2_Last 30 #define XContext_R_First 31 #define XContext_R_Last 32 #define XContext_PTEBase_First 33 #define XContext_PTEBase_Last 63 /* Error Checking and Correcting (ECC) Register (26) */ #define ECC_First 0 #define ECC_Last 7 /* Cache Error (CacheErr) Register (27) */ #define CacheErr_PIdx_First 0 #define CacheErr_PIdx_Last 2 #define CacheErr_SIdx_First 3 #define CacheErr_SIdx_Last 21 #define CacheErr_EW 23 #define CacheErr_EI 24 #define CacheErr_EB 25 #define CacheErr_EE 26 #define CacheErr_ES 27 #define CacheErr_ET 28 #define CacheErr_ED 29 #define CacheErr_EC 30 #define CacheErr_ER 31 /* Cache Tag Registers [TagLo (28) and TagHi (29)] */ #define CacheTag_ECC_First 0 #define CacheTag_ECC_Last 6 #define CacheTag_VIndex_First 7 #define CacheTag_VIndex_Last 9 #define CacheTag_SState_First 10 #define CacheTag_SState_Last 12 #define CacheTag_STagLo_First 13 #define CacheTag_STagLo_Last 31 #define CacheTag_P 0 #define CacheTag_PState_First 6 #define CacheTag_PState_Last 7 #define CacheTag_PTagLo_First 8 #define CacheTag_PTagLo_Last 31 /* Error Exception Program Counter (Error EPC) Register (30) * Exception numbers. */ #define EXC_Int (0 << 2) // interrupt #define EXC_Mod (1 << 2) // TLB modified exception #define EXC_TLBL (2 << 2) // TLB exception (load or instruction fetch) #define EXC_TLBS (3 << 2) // TLB exception (store) #define EXC_AdEL (4 << 2) // Address error exception (load or fetch) #define EXC_AdES (5 << 2) // Address error exception (store) #define EXC_IBE (6 << 2) // Bus error exception (instruction fetch) #define EXC_DBE (7 << 2) // Bus error exception (load or store) #define EXC_Sys (8 << 2) // Syscall exception #define EXC_Bp (9 << 2) // Breakpoint exception #define EXC_RI (10 << 2) // Reserved instruction exception #define EXC_CpU (11 << 2) // Coprocessor Unusable exception #define EXC_Ov (12 << 2) // Arithmetic overflow exception #define EXC_Tr (13 << 2) // Trap exception #define EXC_VCEI (14 << 2) // Virtual Coherency Exception (I-cache) #define EXC_FPE (15 << 2) // Floating-Point exception // 16-22 // Reserved #define EXC_WATCH (23 << 2) // Reference to WatchHi/WatchLo address // 24-30 // Reserved #define EXC_VCED (31 << 2) // Virtual Coherency Exception (D-cache) /* Address space layout */ #define kseg2 0xC0000000 //TVA(0xC000,0x0000) //Shi yang 2006-08-09 #define kseg1 0xA0000000 //TVA(0xA000,0x0000) #define kseg0 0x80000000 //TVA(0x8000,0x0000) #define kuseg 0x00000000 //TVA(0x0000,0x0000) #define KUSEG 0 #define KSEG0 1 #define KSEG1 2 #define KSEG2 3 /* Exception vectors */ #define reset_vector_base 0xBFC00000 //TVA(0xBFC0,0x0000) #define general_vector_base 0x80000000 //TVA(0x8000,0x0000) #define boot_vector_base 0x80000000 //TVA(0x8000,0x0000) #define cache_error_vector_base 0xA0000000 //TVA(0xA000,0x0000) #define reset_vector 0x000 #define tlb_refill_vector 0x000 #define xtlb_refill_vector 0x080 #define cache_error_vector 0x100 #define common_vector 0x180 #endif //end of _CPU_H_ ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/common/cache.h�����������������������������������������������������������0000644�0001750�0000144�00000010077�10541455476�016647� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _CACHE_H_ #define _CACHE_H_ #include "types.h" /* This header describes a physically-indexed, physically-taged MIPS cache. * Both direct mapped and n-way set-associative caches are supported. The only * restriction is that all geometry parameters must be integer powers of 2. * Each line includes 32 bits of uninterpreted cache state. */ #define vaddr_width 32 //Shi yang 2006-08-28 /*the parameters of icache */ #define log2_icache_assoc 1 #define log2_icache_size 14 #define log2_icache_line 5 /* the parameters of dcache */ #define log2_dcache_assoc 1 #define log2_dcache_size 14 #define log2_dcache_line 5 #define write_buffers 0 #define tlb_size 48 #define kseg_end TVA(0xFFFF,0xFFFF) #define Icache_log2_sets (log2_icache_size - log2_icache_line - log2_icache_assoc) #define Icache_size (1 << log2_icache_size) #define Icache_assoc (1 << log2_icache_assoc) #define Icache_line_size (1 << log2_icache_line) #define Icache_sets (1 << log2_icache_size) #define Icache_index_first (log2_icache_line) #define Icache_index_last (Icache_log2_sets - 1 + Icache_index_first) //for dcache #define Dcache_log2_sets (log2_dcache_size - log2_dcache_line - log2_dcache_assoc) #define Dcache_size (1 << log2_dcache_size) #define Dcache_assoc (1 << log2_dcache_assoc) #define Dcache_line_size (1 << log2_dcache_line) #define Dcache_sets (1 << log2_dcache_size) #define Dcache_index_first (log2_dcache_line) #define Dcache_index_last (Dcache_log2_sets - 1 + Dcache_index_first) typedef struct MIPSICacheLine_s { UInt32 tag; UInt32 state; UInt32 data[(1 << log2_icache_line) / 8]; }MIPSICacheLine; typedef struct MIPSICacheSet_s { UInt8 Icache_lru[1 << log2_icache_assoc]; MIPSICacheLine line[1 << log2_icache_assoc]; }MIPSICacheSet; // Initialize the LRU data. static void Icache_lru_init(UInt8* Icache_lru) { UInt8 i; for (i = 0; i < (UInt8)Icache_assoc; ++i) Icache_lru[i] = i; } static int Icache_lru_replace(UInt8* Icache_lru) { return Icache_lru[Icache_assoc - 1]; } // Touch a cache line (mark it as most-recently used.) static void Icache_lru_touch(UInt8* Icache_lru, unsigned int n) { // Set lru[0] to n and shift the other values accordingly. if ((int)Icache_lru[0] != n) { unsigned int i; for (i = n; i; --i) Icache_lru[i] = Icache_lru[i - 1]; Icache_lru[0] = n; } } //define the type of mips icache typedef struct MIPSICache_s { MIPSICacheLine line; MIPSICacheSet set[Icache_size]; }ICache; static VA Icache_index(VA va) { return bits(va, Icache_index_last, Icache_index_first); } static VA Icache_block(VA va) { return bits(va, Icache_index_last + log2_icache_assoc, Icache_index_last + 1); } static PA Icache_tag(PA pa) { return bits(pa, paddr_width - 1, Icache_index_last + 1); } typedef struct MIPSDCacheLine_s { UInt32 tag; UInt32 state; UInt32 data[(1 << log2_dcache_line) / 8]; }MIPSDCacheLine; typedef struct MIPSDCacheSet_s { UInt8 Dcache_lru[1 << log2_dcache_assoc]; MIPSDCacheLine line[1 << log2_dcache_assoc]; }MIPSDCacheSet; typedef struct MIPSDCache_s { MIPSDCacheLine line; MIPSDCacheSet set[Dcache_size]; }DCache; // Initialize the LRU data. static void Dcache_lru_init(UInt8* Dcache_lru) { UInt8 i; for (i = 0; i <Dcache_assoc; ++i) Dcache_lru[i] = i; } static int Dcache_lru_replace(UInt8* Dcache_lru) { return Dcache_lru[Dcache_assoc - 1]; } // Touch a cache line (mark it as most-recently used.) static void Dcache_lru_touch(UInt8* Dcache_lru, int n) { // Set lru[0] to n and shift the other values accordingly. if (Dcache_lru[0] != n) { unsigned i; for (i = n; i; --i) Dcache_lru[i] = Dcache_lru[i - 1]; Dcache_lru[0] = n; } } static VA Dcache_index(VA va) { return bits(va, Dcache_index_last, Dcache_index_first); } static VA Dcache_block(VA va) { return bits(va, Dcache_index_last + log2_dcache_assoc, Dcache_index_last + 1); } static PA Dcache_tag(PA pa) { return bits(pa, paddr_width - 1, Dcache_index_last + 1); } #endif //end of _CACHE_H_ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/mach/��������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015023� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/mach/skyeye_mach_au1100.c������������������������������������������������0000644�0001750�0000144�00000034024�11006337414�020471� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_au1100.c - au1100 machine simulation Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/02/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include "skyeye_config.h" #include "../common/types.h" #include "../common/inttypes.h" #include "../common/emul.h" #include "../common/cpu.h" #include <stdio.h> #include <fcntl.h> #include <signal.h> /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" //#include "au1000.h" extern MIPS_State* mstate; typedef struct gpio_ctrl_s{ uint32_t sys_trioutrd; uint32_t sys_outrd; uint32_t sys_pininputen; uint32_t sys_outputclr; }gpio_ctrl_t; typedef volatile struct { /*00*/ u16 whoami; u16 reserved0; /*04*/ u16 status; u16 reserved1; /*08*/ u16 switches; u16 reserved2; /*0C*/ u16 resets; u16 reserved3; /*10*/ u16 pcmcia; u16 reserved4; /*14*/ u16 board; u16 reserved5; /*18*/ u16 disk_leds; u16 reserved6; /*1C*/ u16 system; u16 reserved7; /*20*/ u16 intclr; u16 reserved8; /*24*/ u16 intset; u16 reserved9; /*28*/ u16 intclr_mask; u16 reserved10; /*2C*/ u16 intset_mask; u16 reserved11; /*30*/ u16 sig_status; u16 reserved12; /*34*/ u16 int_status; u16 reserved13; /*38*/ u16 reserved14; u16 reserved15; /*3C*/ u16 reserved16; u16 reserved17; } bcsr_t; /* Clock Register Descriptions */ typedef struct sys_clock_s{ uint32_t sys_freqctrl0; uint32_t sys_freqctrl1; uint32_t sys_clksrc; uint32_t sys_cpupll; uint32_t sys_auxpll; uint32_t sys_toytrim; uint32_t sys_toywrite; uint32_t sys_toymatch0; uint32_t sys_toymatch1; uint32_t sys_toymatch2; uint32_t sys_cntrctrl; uint32_t sys_toyread; uint32_t sys_rtctrim; uint32_t sys_rtcwrite; uint32_t sys_rtmatch0; uint32_t sys_rtcmatch1; uint32_t sys_rtcmatch2; uint32_t sys_rtcread; }sys_clock_t; /* UART Controller */ typedef struct uart_s { uint32_t rxdata; uint32_t txdata; uint32_t inten; uint32_t intcause; uint32_t fifoctrl; uint32_t linectrl; uint32_t mdmctrl; uint32_t linestat; uint32_t mdmstat; uint32_t autoflow; uint32_t clkdiv; uint32_t enable; }au1100_uart_t; /* Interrupt Controller */ typedef struct int_ctrl_s { uint32_t cfg0rd; uint32_t cfg0set; uint32_t cfg0clr; uint32_t cfg1rd; uint32_t cfg1set; uint32_t cfg1clr; uint32_t cfg2rd; uint32_t cfg2set; uint32_t cfg2clr; uint32_t req0int; uint32_t srcrd; uint32_t srcset; uint32_t srcclr; uint32_t req1int; uint32_t assignrd; uint32_t assignset; uint32_t assignclr; uint32_t wakerd; uint32_t wakeset; uint32_t wakeclr; uint32_t maskrd; uint32_t maskset; uint32_t maskclr; uint32_t risingrd; uint32_t risingclr; uint32_t fallingrd; uint32_t fallingclr; uint32_t testbit; }int_ctrl_t; /* static bus controller */ typedef struct sb_ctrl_s{ uint32_t mem_stcfg[4]; uint32_t mem_sttime[4]; uint32_t mem_staddr[4]; }sb_ctrl_t ; typedef struct pm_ctrl_s{ uint32_t sys_powerctrl; }pm_ctrl_t; typedef struct au1100_io_s { au1100_uart_t uart[3]; int_ctrl_t int_ctrl[2]; sys_clock_t clock; gpio_ctrl_t gpio_ctrl; pm_ctrl_t pm; sb_ctrl_t sb_ctrl; bcsr_t bcsr; }au1100_io_t; static au1100_io_t io; static void update_int(){ if(io.int_ctrl[0].req0int & 0x1){ //printf("hardware int happened!\n"); mstate->cp0[Cause] |= 1 << Cause_IP2; process_exception(mstate, EXC_Int, common_vector); } } static void au1100_io_do_cycle (void * state) { #if 1 if (!(io.int_ctrl[0].req0int & 0x1)) { /* if we already in interrupt handler? */ /* UART receive interrupt enable */ int int_enable = io.int_ctrl[0].maskrd & 0x1; // UART interrupt enable if(!int_enable) return; struct timeval tv; unsigned char c; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &c, 1, &tv, NULL) > 0) { io.uart[0].rxdata = (int) c; io.uart[0].intcause |= 0x4; //Rx idle io.uart[0].intcause &= ~0x1; printf("SKYEYE: io_do_cycle set intcause = %x\n",io.uart[0].intcause); io.uart[0].linestat |= 0x01; //Data ready io.int_ctrl[0].req0int |= 0x1; } if (io.uart[0].inten & 0x2) { //printf("tx interrupt\n"); if (int_enable) io.int_ctrl[0].req0int |= 0x1; io.uart[0].intcause |= 0x2; io.uart[0].intcause &= ~0x1; io.uart[0].linestat |= 0x60; } update_int(); } #endif } /* au1100 uart read function */ static UInt32 au1100_uart_read_word(int index, void * state, UInt32 offset){ au1100_uart_t * uart_p = &io.uart[index]; UInt32 data; //printf("read offset=0x%x\n", offset); switch (offset) { case 0x0: data = uart_p->rxdata; uart_p->linestat &= ~0x1; break; case 0x4: data = uart_p->txdata; break; case 0x8: data = uart_p->inten; break; case 0xC: data = uart_p->intcause; /* Clear interrupt status of uart */ uart_p->intcause = (uart_p->intcause & ~0xF) | 0x1; break; case 0x10: data = uart_p->fifoctrl; break; case 0x14: data = uart_p->linectrl; break; case 0x18: data = uart_p->mdmctrl; break; case 0x1C: data = uart_p->linestat; //printf("read lsr, data=0x%x\n", data); break; case 0x20: data = uart_p->mdmstat; break; case 0x24: data = uart_p->autoflow; break; case 0x28: data = uart_p->clkdiv; break; case 0x100: data = uart_p->enable; break; default: fprintf(stderr, "I/O err in %s, offset=0x%x\n", __FUNCTION__, offset); skyeye_exit(-1); } return data; } static UInt32 au1100_io_read_byte(void * state, UInt32 addr) { UInt32 ret; MIPS_State * mstate = (MIPS_State *)state; switch (addr) { default: fprintf(stderr,"I/O err in %s, addr=0x%x, pc=0x%x\n", __FUNCTION__, addr, mstate->pc); //skyeye_exit(-1); } return ret; } static UInt32 au1100_io_read_halfword(void * state, UInt32 addr) { UInt32 ret; MIPS_State * mstate = (MIPS_State *)state; switch (addr) { default: fprintf(stderr, "I/O err in %s, addr=0x%xi, pc=0x%x\n", __FUNCTION__, addr, mstate->pc); skyeye_exit(-1); } return ret; } static UInt32 au1100_io_read_word(void * state, UInt32 addr) { UInt32 ret; MIPS_State * mstate = (MIPS_State *)state; /* uart write word */ if(addr >= 0x11100000 && addr <= (0x11400000 + 0x100)){ return au1100_uart_read_word((addr & 0x600000) >> 20, state, addr & 0xfff); } switch (addr) { case 0x11900014: ret = io.clock.sys_cntrctrl; break; case 0x1190003c: ret = io.pm.sys_powerctrl; break; case 0x11900060: ret = io.clock.sys_cpupll; break; case 0x14001000: ret = io.sb_ctrl.mem_stcfg[0]; break; case 0x10400054: ret = io.int_ctrl[0].req0int; break; case 0x11900110: //printf("read gpio\n"); break; case 0x1190002c: //printf("read gpio\n"); break; default: fprintf(stderr, "I/O err in %s, addr=0x%x, pc=0x%x\n", __FUNCTION__, addr, mstate->pc); //skyeye_exit(-1); } return ret; } static void au1100_io_write_byte(void * state, UInt32 addr, UInt32 data) { unsigned char c = data & 0xff; MIPS_State * mstate = (MIPS_State *)state; switch (addr) { default: fprintf(stderr, "I/O err in %s, addr=0x%x, pc=0x%x\n", __FUNCTION__, addr, mstate->pc); //skyeye_exit(-1); } } static void au1100_io_write_halfword(void * state, UInt32 addr, UInt32 data) { MIPS_State * mstate = (MIPS_State *)state; switch (addr) { case 0x19800028: io.bcsr.intclr_mask = data; break; case 0x19800020: io.bcsr.intclr = data; break; default: fprintf(stderr, "I/O err in %s, addr=0x%x,pc=0x%x\n", __FUNCTION__, addr, mstate->pc); skyeye_exit(-1); } } /* au1100 uart write function */ static void au1100_uart_write_word(int index, void * state, UInt32 offset, UInt32 data){ au1100_uart_t * uart_p = &io.uart[index]; //printf("KSDBG:in %s, offset=0x%x\n", __FUNCTION__, offset); switch (offset) { case 0x0: uart_p->rxdata = data; break; case 0x4: { char c = data & 0xff; uart_p->txdata = data; skyeye_uart_write(index, &c, 1, NULL); uart_p->linestat |= 0x60; break; } case 0x8: uart_p->inten = data; break; case 0xC: uart_p->intcause = data; break; case 0x10: uart_p->fifoctrl = data; break; case 0x14: uart_p->linectrl = data; break; case 0x18: uart_p->mdmctrl = data; break; case 0x1C: uart_p->linestat = data; break; case 0x20: uart_p->mdmstat = data; break; case 0x24: uart_p->autoflow = data; break; case 0x28: uart_p->clkdiv = data; break; case 0x100: uart_p->enable = data; break; default: fprintf(stderr, "I/O err in %s, offset=0x%x\n", __FUNCTION__, offset); skyeye_exit(-1); } } static void au1100_ic_write_word(int index, void * state, UInt32 offset, UInt32 data){ int_ctrl_t * int_ctrl_p = &io.int_ctrl[index]; MIPS_State * curr_state = (MIPS_State*)state; switch (offset) { case 0x40: int_ctrl_p->cfg0set = data; break; case 0x44: int_ctrl_p->cfg0clr = data; break; case 0x48: int_ctrl_p->cfg1set = data; break; case 0x4C: int_ctrl_p->cfg1clr = data; break; case 0x50: int_ctrl_p->cfg2set = data; break; case 0x54: int_ctrl_p->cfg2clr = data; break; case 0x58: int_ctrl_p->srcset = data; break; case 0x5C: int_ctrl_p->srcclr = data; break; case 0x60: int_ctrl_p->assignset = data; break; case 0x64: int_ctrl_p->assignclr = data; break; case 0x68: int_ctrl_p->wakeset = data; break; case 0x6C: int_ctrl_p->wakeclr = data; break; case 0x70: /* Maskset */ int_ctrl_p->maskrd |= data; //printf("maskset=0x%x\n",data); break; case 0x74: /* Maskclr */ /* W1C, write 1 to clear */ int_ctrl_p->maskrd &= ~data; //printf("maskclr=0x%x\n", data); break; case 0x78: /* W1C */ int_ctrl_p->risingclr = data; //printf("risingclr=0x%x\n", data); break; case 0x7C: int_ctrl_p->fallingclr = data; //printf("fallingclr=0x%x\n", data); break; case 0x80: int_ctrl_p->testbit = data; break; default: fprintf(stderr, "I/O err in %s, offset=0x%x\n", __FUNCTION__, offset); skyeye_exit(-1); } } static void au1100_io_write_word(void * state, UInt32 addr, UInt32 data) { MIPS_State * curr_state = (MIPS_State*)state; /* Interrupt controller 0 write word */ if(addr >= 0x10400000 && addr <= (0x10400000 + 0x80)) { au1100_ic_write_word(0,state, addr - 0x10400000, data); return; } /* Interrupt controller 1 write word */ if(addr >= 0x11800000 && addr <= (0x11800000 + 0x80)){ au1100_ic_write_word(1, state, addr - 0x11800000, data); return; } /* uart write word */ if(addr >= 0x11100000 && addr <= (0x11400000 + 0x100)){ au1100_uart_write_word((addr & 0x600000) > 20, state, addr & 0x1ff, data); return; } switch (addr) { case 0x11900004: io.clock.sys_toywrite = data; break; case 0x11900000: io.clock.sys_toytrim = data; break; case 0x11900014: io.clock.sys_cntrctrl = data; break; case 0x11900020: io.clock.sys_freqctrl0 = data; break; case 0x11900024: io.clock.sys_freqctrl1 = data; break; case 0x11900028: io.clock.sys_clksrc = data; break; case 0x1190003c: io.pm.sys_powerctrl = data; break; case 0x11900044: io.clock.sys_rtctrim = data; break; case 0x11900060: io.clock.sys_cpupll = data; break; case 0x11900064: io.clock.sys_auxpll = data; break; case 0x11900110: io.gpio_ctrl.sys_pininputen = data; break; case 0x11700008: //printf("gpio write\n"); break; case 0x11900100: //printf("gpio write\n"); break; case 0x1190002c: //printf("gpio write\n"); break; default: fprintf(stderr, "I/O err in %s, addr=0x%x,pc=0x%x\n", __FUNCTION__, addr, curr_state->pc); //skyeye_exit(-1); } } static void au1100_update_intr(machine_config_t *mach) { } static void au1100_set_intr(UInt32 irq) { io.int_ctrl[0].req0int = irq; } void au1100_mach_init (void * state, machine_config_t * this_mach) { io.uart[0].linestat = 0x20; /* according to 8250 uart spec, this bit should be THRE */ /*init io value */ io.clock.sys_cpupll = 0x10; /*init mach */ if (!this_mach) { fprintf(stderr, "Memory have not been allocated for mach.\n"); skyeye_exit (-1); } this_mach->mach_io_read_byte = au1100_io_read_byte; this_mach->mach_io_read_halfword = au1100_io_read_halfword; this_mach->mach_io_read_word = au1100_io_read_word; this_mach->mach_io_write_byte = au1100_io_write_byte; this_mach->mach_io_write_halfword = au1100_io_write_halfword; this_mach->mach_io_write_word = au1100_io_write_word; this_mach->mach_io_do_cycle = au1100_io_do_cycle; this_mach->mach_set_intr = au1100_set_intr; this_mach->mach_update_intr = au1100_update_intr; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/mach/skyeye_mach_nedved.c������������������������������������������������0000644�0001750�0000144�00000024450�11012326044�021023� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "skyeye_config.h" #include "../common/types.h" #include "../common/inttypes.h" #include "../common/emul.h" #include "../common/cpu.h" #include <stdio.h> #include <fcntl.h> #include <signal.h> /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" /* Timer Controller */ #define RTC_INIT_REG1 0xb8300000 /* Initial value */ #define RTC_COMPARE1 0xb8300004 /* 0 forever */ #define RTC_INIT_REG2 0xb8300008 #define RTC_COMPARE2 0xb830000c #define RTC_COUNTER1 0xb8300010 /* Initial value sub 1 per ms */ #define RTC_COUNTER2 0xb8300014 #define RTC_CONTROL1 0xb8300018 /* Ack timer interrupt */ #define RTC_CONTROL2 0xb830001c /* Interrupt Controller */ #define INC_ISR 0xb8200000 #define INC_IMR 0xb8200004 /* UART Controller */ #define UART_BAUDRATE 0xb8500000 /* 1byte */ #define UART_CHAR 0xb8500004 /* 1byte */ #define INC_PCI_A (1<<0) #define INC_PCI_B (1<<1) #define INC_PCI_C (1<<2) #define INC_PCI_D (1<<3) #define INC_PCITBD1 (1<<4) #define INC_PCITBD2 (1<<5) #define INC_PCITBD3 (1<<6) #define INC_PCITBD4 (1<<7) #define INC_DMA1 (1<<8) #define INC_DMA2 (1<<9) #define INC_UART_RX (1<<10) #define INC_UART_TX (1<<11) #define INC_USB (1<<12) #define INC_USBTBD (1<<13) #define INC_TIMER1 (1<<14) #define INC_TIMER2 (1<<15) #define INC_PM1 (1<<16) #define INC_PM2 (1<<17) #define MIPS_CP0_STATUS_IMASK 0x0000FF00 extern MIPS_State *mstate; typedef struct uart_s { UInt32 uart_baudrate; UInt32 uart_char; }uart_t; typedef struct rtc_s { UInt32 timer_initreg1; UInt32 timer_compare1; UInt32 timer_initreg2; UInt32 timer_compare2; UInt32 timer_counter1; UInt32 timer_counter2; UInt32 timer_controlreg1; UInt32 timer_controlreg2; UInt32 timer_refreshreg; }rtc_t; typedef struct intc_s { UInt32 isr; UInt32 imr; }intc_t; typedef struct nedved_io_s { uart_t uart; rtc_t timer; intc_t intc; }nedved_io_t; static nedved_io_t io; void mips_update_irq_flag_fast(MIPS_State* mstate) { mstate->irq_pending = 0; UInt32 sreg_mask, imask; sreg_mask = (1 << SR_IEC); //Shi yang 2006-08-18 if((mstate->cp0[SR] & sreg_mask) == (1 << SR_IEC)) { imask = mstate->cp0[SR] & MIPS_CP0_STATUS_IMASK; if(((mstate->cp0[Cause]) & imask) && (io.intc.imr & io.intc.isr)) mstate->irq_pending = 1; } } static void nedved_io_do_cycle () { io.timer.timer_counter1--; if (io.timer.timer_counter1 == io.timer.timer_compare1) { io.timer.timer_counter1 = io.timer.timer_initreg1; io.intc.isr |= INC_TIMER1; } if (io.uart.uart_char == 0) io.intc.isr |= INC_UART_RX;//UART TX IRQ if (io.uart.uart_char != 0) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; //printf("\nUART RX IRQ before skyeye_uart_read\n"); if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { //printf ("\nUART RX IRQ\n"); io.uart.uart_char = buf; io.intc.isr |= INC_UART_TX; //UART RX IRQ } } mips_update_irq_flag_fast(mstate); } static UInt32 nedved_io_read_byte(UInt32 addr) { UInt32 ret; switch (addr) { case RTC_INIT_REG1: ret = io.timer.timer_initreg1 & 0xff; break; case RTC_COMPARE1: ret = io.timer.timer_compare1 & 0xff; break; case RTC_INIT_REG2: ret = io.timer.timer_initreg2 & 0xff; break; case RTC_COMPARE2: ret = io.timer.timer_compare2 & 0xff; break; case RTC_COUNTER1: ret = io.timer.timer_counter1 & 0xff; break; case RTC_COUNTER2: ret = io.timer.timer_counter2 & 0xff; break; case RTC_CONTROL1: ret = io.timer.timer_controlreg1 & 0xff; break; case RTC_CONTROL2: ret = io.timer.timer_controlreg2 & 0xff; break; case INC_IMR: ret = io.intc.imr & 0xff; break; case INC_ISR: ret = io.intc.isr & 0xff; break; case UART_BAUDRATE: ret = io.uart.uart_baudrate & 0xff; break; case UART_CHAR: ret = io.uart.uart_char & 0xff; if (ret != 0) { io.intc.isr &= ~INC_UART_TX; } break; default: break; } return ret; } static UInt32 nedved_io_read_halfword(UInt32 addr) { UInt32 ret; switch (addr) { case RTC_INIT_REG1: ret = io.timer.timer_initreg1 & 0xffff; break; case RTC_COMPARE1: ret = io.timer.timer_compare1 & 0xffff; break; case RTC_INIT_REG2: ret = io.timer.timer_initreg2 & 0xffff; break; case RTC_COMPARE2: ret = io.timer.timer_compare2 & 0xffff; break; case RTC_COUNTER1: ret = io.timer.timer_counter1 & 0xffff; break; case RTC_COUNTER2: ret = io.timer.timer_counter2 & 0xffff; break; case RTC_CONTROL1: ret = io.timer.timer_controlreg1 & 0xffff; break; case RTC_CONTROL2: ret = io.timer.timer_controlreg2 & 0xffff; break; case INC_IMR: ret = io.intc.imr & 0xffff; break; case INC_ISR: ret = io.intc.isr & 0xffff; break; case UART_BAUDRATE: ret = io.uart.uart_baudrate & 0xffff; break; case UART_CHAR: ret = io.uart.uart_char & 0xffff; break; default: break; } return ret; } static UInt32 nedved_io_read_word(UInt32 addr) { UInt32 ret; switch (addr) { case RTC_INIT_REG1: ret = io.timer.timer_initreg1; break; case RTC_COMPARE1: ret = io.timer.timer_compare1; break; case RTC_INIT_REG2: ret = io.timer.timer_initreg2; break; case RTC_COMPARE2: ret = io.timer.timer_compare2; break; case RTC_COUNTER1: ret = io.timer.timer_counter1; break; case RTC_COUNTER2: ret = io.timer.timer_counter2; break; case RTC_CONTROL1: ret = io.timer.timer_controlreg1; break; case RTC_CONTROL2: ret = io.timer.timer_controlreg2; break; case INC_IMR: ret = io.intc.imr; break; case INC_ISR: ret = io.intc.isr; break; case UART_BAUDRATE: ret = io.uart.uart_baudrate; break; case UART_CHAR: ret = io.uart.uart_char; if (ret != 0) { io.intc.isr &= ~INC_UART_TX; } break; default: break; } return ret; } static void nedved_io_write_byte(UInt32 addr, UInt32 data) { unsigned char c = data & 0xff; switch (addr) { case RTC_INIT_REG1: io.timer.timer_initreg1 = copy_bits(io.timer.timer_initreg1, data, 7, 0); break; case RTC_COMPARE1: io.timer.timer_compare1 = copy_bits(io.timer.timer_compare1, data, 7, 0); break; case RTC_INIT_REG2: io.timer.timer_initreg2 = copy_bits(io.timer.timer_initreg2, data, 7, 0); break; case RTC_COMPARE2: io.timer.timer_compare2 = copy_bits(io.timer.timer_compare2, data, 7, 0); break; case RTC_COUNTER1: io.timer.timer_counter1 = copy_bits(io.timer.timer_counter1, data, 7, 0); break; case RTC_COUNTER2: io.timer.timer_counter2 = copy_bits(io.timer.timer_counter2, data, 7, 0); break; case RTC_CONTROL1: io.timer.timer_controlreg1 = copy_bits(io.timer.timer_controlreg1, data, 7, 0); break; case RTC_CONTROL2: io.timer.timer_controlreg2 = copy_bits(io.timer.timer_controlreg2, data, 7, 0); break; case INC_IMR: io.intc.imr = copy_bits(io.intc.imr, data, 7, 0); break; case INC_ISR: io.intc.isr = copy_bits(io.intc.isr, data, 7, 0); break; case UART_BAUDRATE: io.uart.uart_baudrate = copy_bits(io.uart.uart_baudrate, data, 7, 0); break; case UART_CHAR: io.intc.isr &= ~INC_UART_RX; //Buffer is full io.uart.uart_char = copy_bits(io.uart.uart_char, data, 7, 0); /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.intc.isr |= INC_UART_RX; //Buffer is empty break; defalut: break; } } static void nedved_io_write_halfword(UInt32 addr, UInt32 data) { switch (addr) { case RTC_INIT_REG1: io.timer.timer_initreg1 = copy_bits(io.timer.timer_initreg1, data, 15, 0); break; case RTC_COMPARE1: io.timer.timer_compare1 = copy_bits(io.timer.timer_compare1, data, 15, 0); break; case RTC_INIT_REG2: io.timer.timer_initreg2 = copy_bits(io.timer.timer_initreg2, data, 15, 0); break; case RTC_COMPARE2: io.timer.timer_compare2 = copy_bits(io.timer.timer_compare2, data, 15, 0); break; case RTC_COUNTER1: io.timer.timer_counter1 = copy_bits(io.timer.timer_counter1, data, 15, 0); break; case RTC_COUNTER2: io.timer.timer_counter2 = copy_bits(io.timer.timer_counter2, data, 15, 0); break; case RTC_CONTROL1: io.timer.timer_controlreg1 = copy_bits(io.timer.timer_controlreg1, data, 15, 0); break; case RTC_CONTROL2: io.timer.timer_controlreg2 = copy_bits(io.timer.timer_controlreg2, data, 15, 0); break; case INC_IMR: io.intc.imr = copy_bits(io.intc.imr, data, 15, 0); break; case INC_ISR: io.intc.isr = copy_bits(io.intc.isr, data, 15, 0); break; case UART_BAUDRATE: io.uart.uart_baudrate = copy_bits(io.uart.uart_baudrate, data, 15, 0); break; case UART_CHAR: io.uart.uart_char = copy_bits(io.uart.uart_char, data, 15, 0); break; defalut: break; } } static void nedved_io_write_word(UInt32 addr, UInt32 data) { switch (addr) { case RTC_INIT_REG1: io.timer.timer_initreg1 = data; io.timer.timer_counter1 = data; break; case RTC_COMPARE1: io.timer.timer_compare1 = data; break; case RTC_INIT_REG2: io.timer.timer_initreg2 = data; break; case RTC_COMPARE2: io.timer.timer_compare2 = data; break; case RTC_COUNTER1: io.timer.timer_counter1 = data; break; case RTC_COUNTER2: io.timer.timer_counter2 = data; break; case RTC_CONTROL1: io.timer.timer_controlreg1 = data; break; case RTC_CONTROL2: io.timer.timer_controlreg2 = data; break; case INC_IMR: io.intc.imr = data; break; case INC_ISR: io.intc.isr = data; break; case UART_BAUDRATE: io.uart.uart_baudrate = data; break; case UART_CHAR: io.uart.uart_char = data; break; defalut: break; } } static void nedved_set_int(UInt32 irq) { } void nedved_mach_init (void * state, machine_config_t * this_mach) { /*init io value */ io.intc.isr = 0x0 | INC_UART_RX; io.intc.imr = 0x0; io.uart.uart_char = 0x0; /*init mach */ if (!this_mach) { exit (-1); } this_mach->mach_io_read_byte = nedved_io_read_byte; this_mach->mach_io_read_halfword = nedved_io_read_halfword; this_mach->mach_io_read_word = nedved_io_read_word; this_mach->mach_io_write_byte = nedved_io_write_byte; this_mach->mach_io_write_halfword = nedved_io_write_halfword; this_mach->mach_io_write_word = nedved_io_write_word; this_mach->mach_io_do_cycle = nedved_io_do_cycle; this_mach->mach_set_intr = nedved_set_int; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/mips/mach/au1000.h������������������������������������������������������������0000644�0001750�0000144�00000174737�10647556640�016152� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1k CPU. * * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ /* * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp */ #ifndef _AU1000_H_ #define _AU1000_H_ #ifndef _LANGUAGE_ASSEMBLY #include <linux/delay.h> #include <asm/io.h> /* cpu pipeline flush */ void static inline au_sync(void) { __asm__ volatile ("sync"); } void static inline au_sync_udelay(int us) { __asm__ volatile ("sync"); udelay(us); } void static inline au_sync_delay(int ms) { __asm__ volatile ("sync"); mdelay(ms); } void static inline au_writeb(u8 val, unsigned long reg) { *(volatile u8 *)(reg) = val; } void static inline au_writew(u16 val, unsigned long reg) { *(volatile u16 *)(reg) = val; } void static inline au_writel(u32 val, unsigned long reg) { *(volatile u32 *)(reg) = val; } static inline u8 au_readb(unsigned long reg) { return (*(volatile u8 *)reg); } static inline u16 au_readw(unsigned long reg) { return (*(volatile u16 *)reg); } static inline u32 au_readl(unsigned long reg) { return (*(volatile u32 *)reg); } static __inline__ int au_ffz(unsigned int x) { if ((x = ~x) == 0) return 32; return __ilog2(x & -x); } /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ static __inline__ int au_ffs(int x) { return __ilog2(x & -x) + 1; } /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); extern unsigned long get_au1x00_uart_baud_base(void); extern void set_au1x00_lcd_clock(void); extern unsigned int get_au1x00_lcd_clock(void); /* * Every board describes its IRQ mapping with this table. */ typedef struct au1xxx_irqmap { int im_irq; int im_type; int im_request; } au1xxx_irq_map_t; /* * init_IRQ looks for a table with this name. */ extern au1xxx_irq_map_t au1xxx_irq_map[]; #endif /* !defined (_LANGUAGE_ASSEMBLY) */ #ifdef CONFIG_PM /* no CP0 timer irq */ #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) #else #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) #endif /* * SDRAM Register Offsets */ #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) #define MEM_SDMODE0 (0x0000) #define MEM_SDMODE1 (0x0004) #define MEM_SDMODE2 (0x0008) #define MEM_SDADDR0 (0x000C) #define MEM_SDADDR1 (0x0010) #define MEM_SDADDR2 (0x0014) #define MEM_SDREFCFG (0x0018) #define MEM_SDPRECMD (0x001C) #define MEM_SDAUTOREF (0x0020) #define MEM_SDWRMD0 (0x0024) #define MEM_SDWRMD1 (0x0028) #define MEM_SDWRMD2 (0x002C) #define MEM_SDSLEEP (0x0030) #define MEM_SDSMCKE (0x0034) /* * MEM_SDMODE register content definitions */ #define MEM_SDMODE_F (1<<22) #define MEM_SDMODE_SR (1<<21) #define MEM_SDMODE_BS (1<<20) #define MEM_SDMODE_RS (3<<18) #define MEM_SDMODE_CS (7<<15) #define MEM_SDMODE_TRAS (15<<11) #define MEM_SDMODE_TMRD (3<<9) #define MEM_SDMODE_TWR (3<<7) #define MEM_SDMODE_TRP (3<<5) #define MEM_SDMODE_TRCD (3<<3) #define MEM_SDMODE_TCL (7<<0) #define MEM_SDMODE_BS_2Bank (0<<20) #define MEM_SDMODE_BS_4Bank (1<<20) #define MEM_SDMODE_RS_11Row (0<<18) #define MEM_SDMODE_RS_12Row (1<<18) #define MEM_SDMODE_RS_13Row (2<<18) #define MEM_SDMODE_RS_N(N) ((N)<<18) #define MEM_SDMODE_CS_7Col (0<<15) #define MEM_SDMODE_CS_8Col (1<<15) #define MEM_SDMODE_CS_9Col (2<<15) #define MEM_SDMODE_CS_10Col (3<<15) #define MEM_SDMODE_CS_11Col (4<<15) #define MEM_SDMODE_CS_N(N) ((N)<<15) #define MEM_SDMODE_TRAS_N(N) ((N)<<11) #define MEM_SDMODE_TMRD_N(N) ((N)<<9) #define MEM_SDMODE_TWR_N(N) ((N)<<7) #define MEM_SDMODE_TRP_N(N) ((N)<<5) #define MEM_SDMODE_TRCD_N(N) ((N)<<3) #define MEM_SDMODE_TCL_N(N) ((N)<<0) /* * MEM_SDADDR register contents definitions */ #define MEM_SDADDR_E (1<<20) #define MEM_SDADDR_CSBA (0x03FF<<10) #define MEM_SDADDR_CSMASK (0x03FF<<0) #define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) /* * MEM_SDREFCFG register content definitions */ #define MEM_SDREFCFG_TRC (15<<28) #define MEM_SDREFCFG_TRPM (3<<26) #define MEM_SDREFCFG_E (1<<25) #define MEM_SDREFCFG_RE (0x1ffffff<<0) #define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC) #define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM) #define MEM_SDREFCFG_REF_N(N) (N) #endif /***********************************************************************/ /* * Au1550 SDRAM Register Offsets */ /***********************************************************************/ #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) #define MEM_SDMODE0 (0x0800) #define MEM_SDMODE1 (0x0808) #define MEM_SDMODE2 (0x0810) #define MEM_SDADDR0 (0x0820) #define MEM_SDADDR1 (0x0828) #define MEM_SDADDR2 (0x0830) #define MEM_SDCONFIGA (0x0840) #define MEM_SDCONFIGB (0x0848) #define MEM_SDSTAT (0x0850) #define MEM_SDERRADDR (0x0858) #define MEM_SDSTRIDE0 (0x0860) #define MEM_SDSTRIDE1 (0x0868) #define MEM_SDSTRIDE2 (0x0870) #define MEM_SDWRMD0 (0x0880) #define MEM_SDWRMD1 (0x0888) #define MEM_SDWRMD2 (0x0890) #define MEM_SDPRECMD (0x08C0) #define MEM_SDAUTOREF (0x08C8) #define MEM_SDSREF (0x08D0) #define MEM_SDSLEEP MEM_SDSREF #endif /* * Physical base addresses for integrated peripherals */ #ifdef CONFIG_SOC_AU1000 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 #define DMA0_PHYS_ADDR 0x14002000 #define DMA1_PHYS_ADDR 0x14002100 #define DMA2_PHYS_ADDR 0x14002200 #define DMA3_PHYS_ADDR 0x14002300 #define DMA4_PHYS_ADDR 0x14002400 #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 #define IC0_PHYS_ADDR 0x10400000 #define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 #define IRDA_PHYS_ADDR 0x10300000 #define MAC0_PHYS_ADDR 0x10500000 #define MAC1_PHYS_ADDR 0x10510000 #define MACEN_PHYS_ADDR 0x10520000 #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 #define UART0_PHYS_ADDR 0x11100000 #define UART1_PHYS_ADDR 0x11200000 #define UART2_PHYS_ADDR 0x11300000 #define UART3_PHYS_ADDR 0x11400000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 #define SYS_PHYS_ADDR 0x11900000 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /********************************************************************/ #ifdef CONFIG_SOC_AU1500 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 #define DMA0_PHYS_ADDR 0x14002000 #define DMA1_PHYS_ADDR 0x14002100 #define DMA2_PHYS_ADDR 0x14002200 #define DMA3_PHYS_ADDR 0x14002300 #define DMA4_PHYS_ADDR 0x14002400 #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 #define IC0_PHYS_ADDR 0x10400000 #define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 #define MAC0_PHYS_ADDR 0x11500000 #define MAC1_PHYS_ADDR 0x11510000 #define MACEN_PHYS_ADDR 0x11520000 #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 #define UART0_PHYS_ADDR 0x11100000 #define UART3_PHYS_ADDR 0x11400000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL #define PCI_IO_PHYS_ADDR 0x500000000ULL #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /********************************************************************/ #ifdef CONFIG_SOC_AU1100 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 #define DMA0_PHYS_ADDR 0x14002000 #define DMA1_PHYS_ADDR 0x14002100 #define DMA2_PHYS_ADDR 0x14002200 #define DMA3_PHYS_ADDR 0x14002300 #define DMA4_PHYS_ADDR 0x14002400 #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 #define IC0_PHYS_ADDR 0x10400000 #define SD0_PHYS_ADDR 0x10600000 #define SD1_PHYS_ADDR 0x10680000 #define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 #define IRDA_PHYS_ADDR 0x10300000 #define MAC0_PHYS_ADDR 0x10500000 #define MACEN_PHYS_ADDR 0x10520000 #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 #define UART0_PHYS_ADDR 0x11100000 #define UART1_PHYS_ADDR 0x11200000 #define UART3_PHYS_ADDR 0x11400000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define LCD_PHYS_ADDR 0x15000000 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /***********************************************************************/ #ifdef CONFIG_SOC_AU1550 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 #define IC0_PHYS_ADDR 0x10400000 #define IC1_PHYS_ADDR 0x11800000 #define USBH_PHYS_ADDR 0x14020000 #define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 #define MAC0_PHYS_ADDR 0x10500000 #define MAC1_PHYS_ADDR 0x10510000 #define MACEN_PHYS_ADDR 0x10520000 #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 #define UART0_PHYS_ADDR 0x11100000 #define UART1_PHYS_ADDR 0x11200000 #define UART3_PHYS_ADDR 0x11400000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define DDMA_PHYS_ADDR 0x14002000 #define PE_PHYS_ADDR 0x14008000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 #define PSC2_PHYS_ADDR 0x10A00000 #define PSC3_PHYS_ADDR 0x10B00000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL #define PCI_IO_PHYS_ADDR 0x500000000ULL #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /***********************************************************************/ #ifdef CONFIG_SOC_AU1200 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 #define AES_PHYS_ADDR 0x10300000 #define CIM_PHYS_ADDR 0x14004000 #define IC0_PHYS_ADDR 0x10400000 #define IC1_PHYS_ADDR 0x11800000 #define USBM_PHYS_ADDR 0x14020000 #define USBH_PHYS_ADDR 0x14020100 #define UART0_PHYS_ADDR 0x11100000 #define UART1_PHYS_ADDR 0x11200000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define DDMA_PHYS_ADDR 0x14002000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 #define SD0_PHYS_ADDR 0x10600000 #define SD1_PHYS_ADDR 0x10680000 #define LCD_PHYS_ADDR 0x15000000 #define SWCNT_PHYS_ADDR 0x1110010C #define MAEFE_PHYS_ADDR 0x14012000 #define MAEBE_PHYS_ADDR 0x14010000 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 #define MEM_STADDR0 0xB4001008 #define MEM_STCFG1 0xB4001010 #define MEM_STTIME1 0xB4001014 #define MEM_STADDR1 0xB4001018 #define MEM_STCFG2 0xB4001020 #define MEM_STTIME2 0xB4001024 #define MEM_STADDR2 0xB4001028 #define MEM_STCFG3 0xB4001030 #define MEM_STTIME3 0xB4001034 #define MEM_STADDR3 0xB4001038 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) #define MEM_STNDCTL 0xB4001100 #define MEM_STSTAT 0xB4001104 #define MEM_STNAND_CMD (0x0) #define MEM_STNAND_ADDR (0x4) #define MEM_STNAND_DATA (0x20) #endif /* Interrupt Controller 0 */ #define IC0_CFG0RD 0xB0400040 #define IC0_CFG0SET 0xB0400040 #define IC0_CFG0CLR 0xB0400044 #define IC0_CFG1RD 0xB0400048 #define IC0_CFG1SET 0xB0400048 #define IC0_CFG1CLR 0xB040004C #define IC0_CFG2RD 0xB0400050 #define IC0_CFG2SET 0xB0400050 #define IC0_CFG2CLR 0xB0400054 #define IC0_REQ0INT 0xB0400054 #define IC0_SRCRD 0xB0400058 #define IC0_SRCSET 0xB0400058 #define IC0_SRCCLR 0xB040005C #define IC0_REQ1INT 0xB040005C #define IC0_ASSIGNRD 0xB0400060 #define IC0_ASSIGNSET 0xB0400060 #define IC0_ASSIGNCLR 0xB0400064 #define IC0_WAKERD 0xB0400068 #define IC0_WAKESET 0xB0400068 #define IC0_WAKECLR 0xB040006C #define IC0_MASKRD 0xB0400070 #define IC0_MASKSET 0xB0400070 #define IC0_MASKCLR 0xB0400074 #define IC0_RISINGRD 0xB0400078 #define IC0_RISINGCLR 0xB0400078 #define IC0_FALLINGRD 0xB040007C #define IC0_FALLINGCLR 0xB040007C #define IC0_TESTBIT 0xB0400080 /* Interrupt Controller 1 */ #define IC1_CFG0RD 0xB1800040 #define IC1_CFG0SET 0xB1800040 #define IC1_CFG0CLR 0xB1800044 #define IC1_CFG1RD 0xB1800048 #define IC1_CFG1SET 0xB1800048 #define IC1_CFG1CLR 0xB180004C #define IC1_CFG2RD 0xB1800050 #define IC1_CFG2SET 0xB1800050 #define IC1_CFG2CLR 0xB1800054 #define IC1_REQ0INT 0xB1800054 #define IC1_SRCRD 0xB1800058 #define IC1_SRCSET 0xB1800058 #define IC1_SRCCLR 0xB180005C #define IC1_REQ1INT 0xB180005C #define IC1_ASSIGNRD 0xB1800060 #define IC1_ASSIGNSET 0xB1800060 #define IC1_ASSIGNCLR 0xB1800064 #define IC1_WAKERD 0xB1800068 #define IC1_WAKESET 0xB1800068 #define IC1_WAKECLR 0xB180006C #define IC1_MASKRD 0xB1800070 #define IC1_MASKSET 0xB1800070 #define IC1_MASKCLR 0xB1800074 #define IC1_RISINGRD 0xB1800078 #define IC1_RISINGCLR 0xB1800078 #define IC1_FALLINGRD 0xB180007C #define IC1_FALLINGCLR 0xB180007C #define IC1_TESTBIT 0xB1800080 /* Interrupt Configuration Modes */ #define INTC_INT_DISABLED 0 #define INTC_INT_RISE_EDGE 0x1 #define INTC_INT_FALL_EDGE 0x2 #define INTC_INT_RISE_AND_FALL_EDGE 0x3 #define INTC_INT_HIGH_LEVEL 0x5 #define INTC_INT_LOW_LEVEL 0x6 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 /* Interrupt Numbers */ /* Au1000 */ #ifdef CONFIG_SOC_AU1000 #define AU1000_UART0_INT 0 #define AU1000_UART1_INT 1 /* au1000 */ #define AU1000_UART2_INT 2 /* au1000 */ #define AU1000_UART3_INT 3 #define AU1000_SSI0_INT 4 /* au1000 */ #define AU1000_SSI1_INT 5 /* au1000 */ #define AU1000_DMA_INT_BASE 6 #define AU1000_TOY_INT 14 #define AU1000_TOY_MATCH0_INT 15 #define AU1000_TOY_MATCH1_INT 16 #define AU1000_TOY_MATCH2_INT 17 #define AU1000_RTC_INT 18 #define AU1000_RTC_MATCH0_INT 19 #define AU1000_RTC_MATCH1_INT 20 #define AU1000_RTC_MATCH2_INT 21 #define AU1000_IRDA_TX_INT 22 /* au1000 */ #define AU1000_IRDA_RX_INT 23 /* au1000 */ #define AU1000_USB_DEV_REQ_INT 24 #define AU1000_USB_DEV_SUS_INT 25 #define AU1000_USB_HOST_INT 26 #define AU1000_ACSYNC_INT 27 #define AU1000_MAC0_DMA_INT 28 #define AU1000_MAC1_DMA_INT 29 #define AU1000_I2S_UO_INT 30 /* au1000 */ #define AU1000_AC97C_INT 31 #define AU1000_GPIO_0 32 #define AU1000_GPIO_1 33 #define AU1000_GPIO_2 34 #define AU1000_GPIO_3 35 #define AU1000_GPIO_4 36 #define AU1000_GPIO_5 37 #define AU1000_GPIO_6 38 #define AU1000_GPIO_7 39 #define AU1000_GPIO_8 40 #define AU1000_GPIO_9 41 #define AU1000_GPIO_10 42 #define AU1000_GPIO_11 43 #define AU1000_GPIO_12 44 #define AU1000_GPIO_13 45 #define AU1000_GPIO_14 46 #define AU1000_GPIO_15 47 #define AU1000_GPIO_16 48 #define AU1000_GPIO_17 49 #define AU1000_GPIO_18 50 #define AU1000_GPIO_19 51 #define AU1000_GPIO_20 52 #define AU1000_GPIO_21 53 #define AU1000_GPIO_22 54 #define AU1000_GPIO_23 55 #define AU1000_GPIO_24 56 #define AU1000_GPIO_25 57 #define AU1000_GPIO_26 58 #define AU1000_GPIO_27 59 #define AU1000_GPIO_28 60 #define AU1000_GPIO_29 61 #define AU1000_GPIO_30 62 #define AU1000_GPIO_31 63 #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 #define UART2_ADDR 0xB1300000 #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap #define USB_HOST_CONFIG 0xB017fffc #define AU1000_ETH0_BASE 0xB0500000 #define AU1000_ETH1_BASE 0xB0510000 #define AU1000_MAC0_ENABLE 0xB0520000 #define AU1000_MAC1_ENABLE 0xB0520004 #define NUM_ETH_INTERFACES 2 #endif /* CONFIG_SOC_AU1000 */ /* Au1500 */ #ifdef CONFIG_SOC_AU1500 #define AU1500_UART0_INT 0 #define AU1000_PCI_INTA 1 /* au1500 */ #define AU1000_PCI_INTB 2 /* au1500 */ #define AU1500_UART3_INT 3 #define AU1000_PCI_INTC 4 /* au1500 */ #define AU1000_PCI_INTD 5 /* au1500 */ #define AU1000_DMA_INT_BASE 6 #define AU1000_TOY_INT 14 #define AU1000_TOY_MATCH0_INT 15 #define AU1000_TOY_MATCH1_INT 16 #define AU1000_TOY_MATCH2_INT 17 #define AU1000_RTC_INT 18 #define AU1000_RTC_MATCH0_INT 19 #define AU1000_RTC_MATCH1_INT 20 #define AU1000_RTC_MATCH2_INT 21 #define AU1500_PCI_ERR_INT 22 #define AU1000_USB_DEV_REQ_INT 24 #define AU1000_USB_DEV_SUS_INT 25 #define AU1000_USB_HOST_INT 26 #define AU1000_ACSYNC_INT 27 #define AU1500_MAC0_DMA_INT 28 #define AU1500_MAC1_DMA_INT 29 #define AU1000_AC97C_INT 31 #define AU1000_GPIO_0 32 #define AU1000_GPIO_1 33 #define AU1000_GPIO_2 34 #define AU1000_GPIO_3 35 #define AU1000_GPIO_4 36 #define AU1000_GPIO_5 37 #define AU1000_GPIO_6 38 #define AU1000_GPIO_7 39 #define AU1000_GPIO_8 40 #define AU1000_GPIO_9 41 #define AU1000_GPIO_10 42 #define AU1000_GPIO_11 43 #define AU1000_GPIO_12 44 #define AU1000_GPIO_13 45 #define AU1000_GPIO_14 46 #define AU1000_GPIO_15 47 #define AU1500_GPIO_200 48 #define AU1500_GPIO_201 49 #define AU1500_GPIO_202 50 #define AU1500_GPIO_203 51 #define AU1500_GPIO_20 52 #define AU1500_GPIO_204 53 #define AU1500_GPIO_205 54 #define AU1500_GPIO_23 55 #define AU1500_GPIO_24 56 #define AU1500_GPIO_25 57 #define AU1500_GPIO_26 58 #define AU1500_GPIO_27 59 #define AU1500_GPIO_28 60 #define AU1500_GPIO_206 61 #define AU1500_GPIO_207 62 #define AU1500_GPIO_208_215 63 /* shortcuts */ #define INTA AU1000_PCI_INTA #define INTB AU1000_PCI_INTB #define INTC AU1000_PCI_INTC #define INTD AU1000_PCI_INTD #define UART0_ADDR 0xB1100000 #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap #define USB_HOST_CONFIG 0xB017fffc #define AU1500_ETH0_BASE 0xB1500000 #define AU1500_ETH1_BASE 0xB1510000 #define AU1500_MAC0_ENABLE 0xB1520000 #define AU1500_MAC1_ENABLE 0xB1520004 #define NUM_ETH_INTERFACES 2 #endif /* CONFIG_SOC_AU1500 */ /* Au1100 */ #ifdef CONFIG_SOC_AU1100 #define AU1100_UART0_INT 0 #define AU1100_UART1_INT 1 #define AU1100_SD_INT 2 #define AU1100_UART3_INT 3 #define AU1000_SSI0_INT 4 #define AU1000_SSI1_INT 5 #define AU1000_DMA_INT_BASE 6 #define AU1000_TOY_INT 14 #define AU1000_TOY_MATCH0_INT 15 #define AU1000_TOY_MATCH1_INT 16 #define AU1000_TOY_MATCH2_INT 17 #define AU1000_RTC_INT 18 #define AU1000_RTC_MATCH0_INT 19 #define AU1000_RTC_MATCH1_INT 20 #define AU1000_RTC_MATCH2_INT 21 #define AU1000_IRDA_TX_INT 22 #define AU1000_IRDA_RX_INT 23 #define AU1000_USB_DEV_REQ_INT 24 #define AU1000_USB_DEV_SUS_INT 25 #define AU1000_USB_HOST_INT 26 #define AU1000_ACSYNC_INT 27 #define AU1100_MAC0_DMA_INT 28 #define AU1100_GPIO_208_215 29 #define AU1100_LCD_INT 30 #define AU1000_AC97C_INT 31 #define AU1000_GPIO_0 32 #define AU1000_GPIO_1 33 #define AU1000_GPIO_2 34 #define AU1000_GPIO_3 35 #define AU1000_GPIO_4 36 #define AU1000_GPIO_5 37 #define AU1000_GPIO_6 38 #define AU1000_GPIO_7 39 #define AU1000_GPIO_8 40 #define AU1000_GPIO_9 41 #define AU1000_GPIO_10 42 #define AU1000_GPIO_11 43 #define AU1000_GPIO_12 44 #define AU1000_GPIO_13 45 #define AU1000_GPIO_14 46 #define AU1000_GPIO_15 47 #define AU1000_GPIO_16 48 #define AU1000_GPIO_17 49 #define AU1000_GPIO_18 50 #define AU1000_GPIO_19 51 #define AU1000_GPIO_20 52 #define AU1000_GPIO_21 53 #define AU1000_GPIO_22 54 #define AU1000_GPIO_23 55 #define AU1000_GPIO_24 56 #define AU1000_GPIO_25 57 #define AU1000_GPIO_26 58 #define AU1000_GPIO_27 59 #define AU1000_GPIO_28 60 #define AU1000_GPIO_29 61 #define AU1000_GPIO_30 62 #define AU1000_GPIO_31 63 #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap #define USB_HOST_CONFIG 0xB017fffc #define AU1100_ETH0_BASE 0xB0500000 #define AU1100_MAC0_ENABLE 0xB0520000 #define NUM_ETH_INTERFACES 1 #endif /* CONFIG_SOC_AU1100 */ #ifdef CONFIG_SOC_AU1550 #define AU1550_UART0_INT 0 #define AU1550_PCI_INTA 1 #define AU1550_PCI_INTB 2 #define AU1550_DDMA_INT 3 #define AU1550_CRYPTO_INT 4 #define AU1550_PCI_INTC 5 #define AU1550_PCI_INTD 6 #define AU1550_PCI_RST_INT 7 #define AU1550_UART1_INT 8 #define AU1550_UART3_INT 9 #define AU1550_PSC0_INT 10 #define AU1550_PSC1_INT 11 #define AU1550_PSC2_INT 12 #define AU1550_PSC3_INT 13 #define AU1000_TOY_INT 14 #define AU1000_TOY_MATCH0_INT 15 #define AU1000_TOY_MATCH1_INT 16 #define AU1000_TOY_MATCH2_INT 17 #define AU1000_RTC_INT 18 #define AU1000_RTC_MATCH0_INT 19 #define AU1000_RTC_MATCH1_INT 20 #define AU1000_RTC_MATCH2_INT 21 #define AU1550_NAND_INT 23 #define AU1550_USB_DEV_REQ_INT 24 #define AU1550_USB_DEV_SUS_INT 25 #define AU1550_USB_HOST_INT 26 #define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT #define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT #define AU1000_USB_HOST_INT AU1550_USB_HOST_INT #define AU1550_MAC0_DMA_INT 27 #define AU1550_MAC1_DMA_INT 28 #define AU1000_GPIO_0 32 #define AU1000_GPIO_1 33 #define AU1000_GPIO_2 34 #define AU1000_GPIO_3 35 #define AU1000_GPIO_4 36 #define AU1000_GPIO_5 37 #define AU1000_GPIO_6 38 #define AU1000_GPIO_7 39 #define AU1000_GPIO_8 40 #define AU1000_GPIO_9 41 #define AU1000_GPIO_10 42 #define AU1000_GPIO_11 43 #define AU1000_GPIO_12 44 #define AU1000_GPIO_13 45 #define AU1000_GPIO_14 46 #define AU1000_GPIO_15 47 #define AU1550_GPIO_200 48 #define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205 #define AU1500_GPIO_16 50 #define AU1500_GPIO_17 51 #define AU1500_GPIO_20 52 #define AU1500_GPIO_21 53 #define AU1500_GPIO_22 54 #define AU1500_GPIO_23 55 #define AU1500_GPIO_24 56 #define AU1500_GPIO_25 57 #define AU1500_GPIO_26 58 #define AU1500_GPIO_27 59 #define AU1500_GPIO_28 60 #define AU1500_GPIO_206 61 #define AU1500_GPIO_207 62 #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 /* shortcuts */ #define INTA AU1550_PCI_INTA #define INTB AU1550_PCI_INTB #define INTC AU1550_PCI_INTC #define INTD AU1550_PCI_INTD #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap #define USB_OHCI_LEN 0x00060000 #define USB_HOST_CONFIG 0xB4027ffc #define AU1550_ETH0_BASE 0xB0500000 #define AU1550_ETH1_BASE 0xB0510000 #define AU1550_MAC0_ENABLE 0xB0520000 #define AU1550_MAC1_ENABLE 0xB0520004 #define NUM_ETH_INTERFACES 2 #endif /* CONFIG_SOC_AU1550 */ #ifdef CONFIG_SOC_AU1200 #define AU1200_UART0_INT 0 #define AU1200_SWT_INT 1 #define AU1200_SD_INT 2 #define AU1200_DDMA_INT 3 #define AU1200_MAE_BE_INT 4 #define AU1200_GPIO_200 5 #define AU1200_GPIO_201 6 #define AU1200_GPIO_202 7 #define AU1200_UART1_INT 8 #define AU1200_MAE_FE_INT 9 #define AU1200_PSC0_INT 10 #define AU1200_PSC1_INT 11 #define AU1200_AES_INT 12 #define AU1200_CAMERA_INT 13 #define AU1000_TOY_INT 14 #define AU1000_TOY_MATCH0_INT 15 #define AU1000_TOY_MATCH1_INT 16 #define AU1000_TOY_MATCH2_INT 17 #define AU1000_RTC_INT 18 #define AU1000_RTC_MATCH0_INT 19 #define AU1000_RTC_MATCH1_INT 20 #define AU1000_RTC_MATCH2_INT 21 #define AU1200_NAND_INT 23 #define AU1200_GPIO_204 24 #define AU1200_GPIO_205 25 #define AU1200_GPIO_206 26 #define AU1200_GPIO_207 27 #define AU1200_GPIO_208_215 28 // Logical OR of 208:215 #define AU1200_USB_INT 29 #define AU1000_USB_HOST_INT AU1200_USB_INT #define AU1200_LCD_INT 30 #define AU1200_MAE_BOTH_INT 31 #define AU1000_GPIO_0 32 #define AU1000_GPIO_1 33 #define AU1000_GPIO_2 34 #define AU1000_GPIO_3 35 #define AU1000_GPIO_4 36 #define AU1000_GPIO_5 37 #define AU1000_GPIO_6 38 #define AU1000_GPIO_7 39 #define AU1000_GPIO_8 40 #define AU1000_GPIO_9 41 #define AU1000_GPIO_10 42 #define AU1000_GPIO_11 43 #define AU1000_GPIO_12 44 #define AU1000_GPIO_13 45 #define AU1000_GPIO_14 46 #define AU1000_GPIO_15 47 #define AU1000_GPIO_16 48 #define AU1000_GPIO_17 49 #define AU1000_GPIO_18 50 #define AU1000_GPIO_19 51 #define AU1000_GPIO_20 52 #define AU1000_GPIO_21 53 #define AU1000_GPIO_22 54 #define AU1000_GPIO_23 55 #define AU1000_GPIO_24 56 #define AU1000_GPIO_25 57 #define AU1000_GPIO_26 58 #define AU1000_GPIO_27 59 #define AU1000_GPIO_28 60 #define AU1000_GPIO_29 61 #define AU1000_GPIO_30 62 #define AU1000_GPIO_31 63 #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 #define USB_UOC_BASE 0x14020020 #define USB_UOC_LEN 0x20 #define USB_OHCI_BASE 0x14020100 #define USB_OHCI_LEN 0x100 #define USB_EHCI_BASE 0x14020200 #define USB_EHCI_LEN 0x100 #define USB_UDC_BASE 0x14022000 #define USB_UDC_LEN 0x2000 #define USB_MSR_BASE 0xB4020000 #define USB_MSR_MCFG 4 #define USBMSRMCFG_OMEMEN 0 #define USBMSRMCFG_OBMEN 1 #define USBMSRMCFG_EMEMEN 2 #define USBMSRMCFG_EBMEN 3 #define USBMSRMCFG_DMEMEN 4 #define USBMSRMCFG_DBMEN 5 #define USBMSRMCFG_GMEMEN 6 #define USBMSRMCFG_OHCCLKEN 16 #define USBMSRMCFG_EHCCLKEN 17 #define USBMSRMCFG_UDCCLKEN 18 #define USBMSRMCFG_PHYPLLEN 19 #define USBMSRMCFG_RDCOMB 30 #define USBMSRMCFG_PFEN 31 #endif /* CONFIG_SOC_AU1200 */ #define AU1000_LAST_INTC0_INT 31 #define AU1000_LAST_INTC1_INT 63 #define AU1000_MAX_INTR 63 #define INTX 0xFF /* not valid */ /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) #define SYS_CNTRL_E1S (1<<23) #define SYS_CNTRL_T1S (1<<20) #define SYS_CNTRL_M21 (1<<19) #define SYS_CNTRL_M11 (1<<18) #define SYS_CNTRL_M01 (1<<17) #define SYS_CNTRL_C1S (1<<16) #define SYS_CNTRL_BP (1<<14) #define SYS_CNTRL_EN1 (1<<13) #define SYS_CNTRL_BT1 (1<<12) #define SYS_CNTRL_EN0 (1<<11) #define SYS_CNTRL_BT0 (1<<10) #define SYS_CNTRL_E0 (1<<8) #define SYS_CNTRL_E0S (1<<7) #define SYS_CNTRL_32S (1<<5) #define SYS_CNTRL_T0S (1<<4) #define SYS_CNTRL_M20 (1<<3) #define SYS_CNTRL_M10 (1<<2) #define SYS_CNTRL_M00 (1<<1) #define SYS_CNTRL_C0S (1<<0) /* Programmable Counter 0 Registers */ #define SYS_TOYTRIM (SYS_BASE + 0) #define SYS_TOYWRITE (SYS_BASE + 4) #define SYS_TOYMATCH0 (SYS_BASE + 8) #define SYS_TOYMATCH1 (SYS_BASE + 0xC) #define SYS_TOYMATCH2 (SYS_BASE + 0x10) #define SYS_TOYREAD (SYS_BASE + 0x40) /* Programmable Counter 1 Registers */ #define SYS_RTCTRIM (SYS_BASE + 0x44) #define SYS_RTCWRITE (SYS_BASE + 0x48) #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) #define SYS_RTCMATCH1 (SYS_BASE + 0x50) #define SYS_RTCMATCH2 (SYS_BASE + 0x54) #define SYS_RTCREAD (SYS_BASE + 0x58) /* I2S Controller */ #define I2S_DATA 0xB1000000 #define I2S_DATA_MASK (0xffffff) #define I2S_CONFIG 0xB1000004 #define I2S_CONFIG_XU (1<<25) #define I2S_CONFIG_XO (1<<24) #define I2S_CONFIG_RU (1<<23) #define I2S_CONFIG_RO (1<<22) #define I2S_CONFIG_TR (1<<21) #define I2S_CONFIG_TE (1<<20) #define I2S_CONFIG_TF (1<<19) #define I2S_CONFIG_RR (1<<18) #define I2S_CONFIG_RE (1<<17) #define I2S_CONFIG_RF (1<<16) #define I2S_CONFIG_PD (1<<11) #define I2S_CONFIG_LB (1<<10) #define I2S_CONFIG_IC (1<<9) #define I2S_CONFIG_FM_BIT 7 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) #define I2S_CONFIG_TN (1<<6) #define I2S_CONFIG_RN (1<<5) #define I2S_CONFIG_SZ_BIT 0 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) #define I2S_CONTROL 0xB1000008 #define I2S_CONTROL_D (1<<1) #define I2S_CONTROL_CE (1<<0) /* USB Host Controller */ #ifndef USB_OHCI_LEN #define USB_OHCI_LEN 0x00100000 #endif #ifndef CONFIG_SOC_AU1200 /* USB Device Controller */ #define USBD_EP0RD 0xB0200000 #define USBD_EP0WR 0xB0200004 #define USBD_EP2WR 0xB0200008 #define USBD_EP3WR 0xB020000C #define USBD_EP4RD 0xB0200010 #define USBD_EP5RD 0xB0200014 #define USBD_INTEN 0xB0200018 #define USBD_INTSTAT 0xB020001C #define USBDEV_INT_SOF (1<<12) #define USBDEV_INT_HF_BIT 6 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) #define USBDEV_INT_CMPLT_BIT 0 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) #define USBD_CONFIG 0xB0200020 #define USBD_EP0CS 0xB0200024 #define USBD_EP2CS 0xB0200028 #define USBD_EP3CS 0xB020002C #define USBD_EP4CS 0xB0200030 #define USBD_EP5CS 0xB0200034 #define USBDEV_CS_SU (1<<14) #define USBDEV_CS_NAK (1<<13) #define USBDEV_CS_ACK (1<<12) #define USBDEV_CS_BUSY (1<<11) #define USBDEV_CS_TSIZE_BIT 1 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) #define USBDEV_CS_STALL (1<<0) #define USBD_EP0RDSTAT 0xB0200040 #define USBD_EP0WRSTAT 0xB0200044 #define USBD_EP2WRSTAT 0xB0200048 #define USBD_EP3WRSTAT 0xB020004C #define USBD_EP4RDSTAT 0xB0200050 #define USBD_EP5RDSTAT 0xB0200054 #define USBDEV_FSTAT_FLUSH (1<<6) #define USBDEV_FSTAT_UF (1<<5) #define USBDEV_FSTAT_OF (1<<4) #define USBDEV_FSTAT_FCNT_BIT 0 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) #define USBD_ENABLE 0xB0200058 #define USBDEV_ENABLE (1<<1) #define USBDEV_CE (1<<0) #endif /* !CONFIG_SOC_AU1200 */ /* Ethernet Controllers */ /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 #define MAC_RX_ENABLE (1<<2) #define MAC_TX_ENABLE (1<<3) #define MAC_DEF_CHECK (1<<5) #define MAC_SET_BL(X) (((X)&0x3)<<6) #define MAC_AUTO_PAD (1<<8) #define MAC_DISABLE_RETRY (1<<10) #define MAC_DISABLE_BCAST (1<<11) #define MAC_LATE_COL (1<<12) #define MAC_HASH_MODE (1<<13) #define MAC_HASH_ONLY (1<<15) #define MAC_PASS_ALL (1<<16) #define MAC_INVERSE_FILTER (1<<17) #define MAC_PROMISCUOUS (1<<18) #define MAC_PASS_ALL_MULTI (1<<19) #define MAC_FULL_DUPLEX (1<<20) #define MAC_NORMAL_MODE 0 #define MAC_INT_LOOPBACK (1<<21) #define MAC_EXT_LOOPBACK (1<<22) #define MAC_DISABLE_RX_OWN (1<<23) #define MAC_BIG_ENDIAN (1<<30) #define MAC_RX_ALL (1<<31) #define MAC_ADDRESS_HIGH 0x4 #define MAC_ADDRESS_LOW 0x8 #define MAC_MCAST_HIGH 0xC #define MAC_MCAST_LOW 0x10 #define MAC_MII_CNTRL 0x14 #define MAC_MII_BUSY (1<<0) #define MAC_MII_READ 0 #define MAC_MII_WRITE (1<<1) #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) #define MAC_MII_DATA 0x18 #define MAC_FLOW_CNTRL 0x1C #define MAC_FLOW_CNTRL_BUSY (1<<0) #define MAC_FLOW_CNTRL_ENABLE (1<<1) #define MAC_PASS_CONTROL (1<<2) #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) #define MAC_VLAN1_TAG 0x20 #define MAC_VLAN2_TAG 0x24 /* Ethernet Controller Enable */ #define MAC_EN_CLOCK_ENABLE (1<<0) #define MAC_EN_RESET0 (1<<1) #define MAC_EN_TOSS (0<<2) #define MAC_EN_CACHEABLE (1<<3) #define MAC_EN_RESET1 (1<<4) #define MAC_EN_RESET2 (1<<5) #define MAC_DMA_RESET (1<<6) /* Ethernet Controller DMA Channels */ #define MAC0_TX_DMA_ADDR 0xB4004000 #define MAC1_TX_DMA_ADDR 0xB4004200 /* offsets from MAC_TX_RING_ADDR address */ #define MAC_TX_BUFF0_STATUS 0x0 #define TX_FRAME_ABORTED (1<<0) #define TX_JAB_TIMEOUT (1<<1) #define TX_NO_CARRIER (1<<2) #define TX_LOSS_CARRIER (1<<3) #define TX_EXC_DEF (1<<4) #define TX_LATE_COLL_ABORT (1<<5) #define TX_EXC_COLL (1<<6) #define TX_UNDERRUN (1<<7) #define TX_DEFERRED (1<<8) #define TX_LATE_COLL (1<<9) #define TX_COLL_CNT_MASK (0xF<<10) #define TX_PKT_RETRY (1<<31) #define MAC_TX_BUFF0_ADDR 0x4 #define TX_DMA_ENABLE (1<<0) #define TX_T_DONE (1<<1) #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) #define MAC_TX_BUFF0_LEN 0x8 #define MAC_TX_BUFF1_STATUS 0x10 #define MAC_TX_BUFF1_ADDR 0x14 #define MAC_TX_BUFF1_LEN 0x18 #define MAC_TX_BUFF2_STATUS 0x20 #define MAC_TX_BUFF2_ADDR 0x24 #define MAC_TX_BUFF2_LEN 0x28 #define MAC_TX_BUFF3_STATUS 0x30 #define MAC_TX_BUFF3_ADDR 0x34 #define MAC_TX_BUFF3_LEN 0x38 #define MAC0_RX_DMA_ADDR 0xB4004100 #define MAC1_RX_DMA_ADDR 0xB4004300 /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 #define RX_FRAME_LEN_MASK 0x3fff #define RX_WDOG_TIMER (1<<14) #define RX_RUNT (1<<15) #define RX_OVERLEN (1<<16) #define RX_COLL (1<<17) #define RX_ETHER (1<<18) #define RX_MII_ERROR (1<<19) #define RX_DRIBBLING (1<<20) #define RX_CRC_ERROR (1<<21) #define RX_VLAN1 (1<<22) #define RX_VLAN2 (1<<23) #define RX_LEN_ERROR (1<<24) #define RX_CNTRL_FRAME (1<<25) #define RX_U_CNTRL_FRAME (1<<26) #define RX_MCAST_FRAME (1<<27) #define RX_BCAST_FRAME (1<<28) #define RX_FILTER_FAIL (1<<29) #define RX_PACKET_FILTER (1<<30) #define RX_MISSED_FRAME (1<<31) #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) #define MAC_RX_BUFF0_ADDR 0x4 #define RX_DMA_ENABLE (1<<0) #define RX_T_DONE (1<<1) #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) #define MAC_RX_BUFF1_STATUS 0x10 #define MAC_RX_BUFF1_ADDR 0x14 #define MAC_RX_BUFF2_STATUS 0x20 #define MAC_RX_BUFF2_ADDR 0x24 #define MAC_RX_BUFF3_STATUS 0x30 #define MAC_RX_BUFF3_ADDR 0x34 /* UARTS 0-3 */ #define UART_BASE UART0_ADDR #ifdef CONFIG_SOC_AU1200 #define UART_DEBUG_BASE UART1_ADDR #else #define UART_DEBUG_BASE UART3_ADDR #endif #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ #define UART_IER 8 /* Interrupt Enable Register */ #define UART_IIR 0xC /* Interrupt ID Register */ #define UART_FCR 0x10 /* FIFO Control Register */ #define UART_LCR 0x14 /* Line Control Register */ #define UART_MCR 0x18 /* Modem Control Register */ #define UART_LSR 0x1C /* Line Status Register */ #define UART_MSR 0x20 /* Modem Status Register */ #define UART_CLK 0x28 /* Baud Rate Clock Divider */ #define UART_MOD_CNTRL 0x100 /* Module Control */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ /* * These are the definitions for the Line Control Register */ #define UART_LCR_SBC 0x40 /* Set break control */ #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ #define UART_LCR_EPAR 0x10 /* Even parity select */ #define UART_LCR_PARITY 0x08 /* Parity Enable */ #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ /* * These are the definitions for the Line Status Register */ #define UART_LSR_TEMT 0x40 /* Transmitter empty */ #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define UART_LSR_BI 0x10 /* Break interrupt indicator */ #define UART_LSR_FE 0x08 /* Frame error indicator */ #define UART_LSR_PE 0x04 /* Parity error indicator */ #define UART_LSR_OE 0x02 /* Overrun error indicator */ #define UART_LSR_DR 0x01 /* Receiver data ready */ /* * These are the definitions for the Interrupt Identification Register */ #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ #define UART_IIR_MSI 0x00 /* Modem status interrupt */ #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ /* * These are the definitions for the Interrupt Enable Register */ #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ /* * These are the definitions for the Modem Control Register */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ #define UART_MCR_RTS 0x02 /* RTS complement */ #define UART_MCR_DTR 0x01 /* DTR complement */ /* * These are the definitions for the Modem Status Register */ #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ #define UART_MSR_RI 0x40 /* Ring Indicator */ #define UART_MSR_DSR 0x20 /* Data Set Ready */ #define UART_MSR_CTS 0x10 /* Clear to Send */ #define UART_MSR_DDCD 0x08 /* Delta DCD */ #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ #define UART_MSR_DDSR 0x02 /* Delta DSR */ #define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ /* SSIO */ #define SSI0_STATUS 0xB1600000 #define SSI_STATUS_BF (1<<4) #define SSI_STATUS_OF (1<<3) #define SSI_STATUS_UF (1<<2) #define SSI_STATUS_D (1<<1) #define SSI_STATUS_B (1<<0) #define SSI0_INT 0xB1600004 #define SSI_INT_OI (1<<3) #define SSI_INT_UI (1<<2) #define SSI_INT_DI (1<<1) #define SSI0_INT_ENABLE 0xB1600008 #define SSI_INTE_OIE (1<<3) #define SSI_INTE_UIE (1<<2) #define SSI_INTE_DIE (1<<1) #define SSI0_CONFIG 0xB1600020 #define SSI_CONFIG_AO (1<<24) #define SSI_CONFIG_DO (1<<23) #define SSI_CONFIG_ALEN_BIT 20 #define SSI_CONFIG_ALEN_MASK (0x7<<20) #define SSI_CONFIG_DLEN_BIT 16 #define SSI_CONFIG_DLEN_MASK (0x7<<16) #define SSI_CONFIG_DD (1<<11) #define SSI_CONFIG_AD (1<<10) #define SSI_CONFIG_BM_BIT 8 #define SSI_CONFIG_BM_MASK (0x3<<8) #define SSI_CONFIG_CE (1<<7) #define SSI_CONFIG_DP (1<<6) #define SSI_CONFIG_DL (1<<5) #define SSI_CONFIG_EP (1<<4) #define SSI0_ADATA 0xB1600024 #define SSI_AD_D (1<<24) #define SSI_AD_ADDR_BIT 16 #define SSI_AD_ADDR_MASK (0xff<<16) #define SSI_AD_DATA_BIT 0 #define SSI_AD_DATA_MASK (0xfff<<0) #define SSI0_CLKDIV 0xB1600028 #define SSI0_CONTROL 0xB1600100 #define SSI_CONTROL_CD (1<<1) #define SSI_CONTROL_E (1<<0) /* SSI1 */ #define SSI1_STATUS 0xB1680000 #define SSI1_INT 0xB1680004 #define SSI1_INT_ENABLE 0xB1680008 #define SSI1_CONFIG 0xB1680020 #define SSI1_ADATA 0xB1680024 #define SSI1_CLKDIV 0xB1680028 #define SSI1_ENABLE 0xB1680100 /* * Register content definitions */ #define SSI_STATUS_BF (1<<4) #define SSI_STATUS_OF (1<<3) #define SSI_STATUS_UF (1<<2) #define SSI_STATUS_D (1<<1) #define SSI_STATUS_B (1<<0) /* SSI_INT */ #define SSI_INT_OI (1<<3) #define SSI_INT_UI (1<<2) #define SSI_INT_DI (1<<1) /* SSI_INTEN */ #define SSI_INTEN_OIE (1<<3) #define SSI_INTEN_UIE (1<<2) #define SSI_INTEN_DIE (1<<1) #define SSI_CONFIG_AO (1<<24) #define SSI_CONFIG_DO (1<<23) #define SSI_CONFIG_ALEN (7<<20) #define SSI_CONFIG_DLEN (15<<16) #define SSI_CONFIG_DD (1<<11) #define SSI_CONFIG_AD (1<<10) #define SSI_CONFIG_BM (3<<8) #define SSI_CONFIG_CE (1<<7) #define SSI_CONFIG_DP (1<<6) #define SSI_CONFIG_DL (1<<5) #define SSI_CONFIG_EP (1<<4) #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) #define SSI_CONFIG_BM_HI (0<<8) #define SSI_CONFIG_BM_LO (1<<8) #define SSI_CONFIG_BM_CY (2<<8) #define SSI_ADATA_D (1<<24) #define SSI_ADATA_ADDR (0xFF<<16) #define SSI_ADATA_DATA (0x0FFF) #define SSI_ADATA_ADDR_N(N) (N<<16) #define SSI_ENABLE_CD (1<<1) #define SSI_ENABLE_E (1<<0) /* IrDA Controller */ #define IRDA_BASE 0xB0300000 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00) #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) #define IR_RING_SIZE (IRDA_BASE+0x0C) #define IR_RING_PROMPT (IRDA_BASE+0x10) #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) #define IR_INT_CLEAR (IRDA_BASE+0x18) #define IR_CONFIG_1 (IRDA_BASE+0x20) #define IR_RX_INVERT_LED (1<<0) #define IR_TX_INVERT_LED (1<<1) #define IR_ST (1<<2) #define IR_SF (1<<3) #define IR_SIR (1<<4) #define IR_MIR (1<<5) #define IR_FIR (1<<6) #define IR_16CRC (1<<7) #define IR_TD (1<<8) #define IR_RX_ALL (1<<9) #define IR_DMA_ENABLE (1<<10) #define IR_RX_ENABLE (1<<11) #define IR_TX_ENABLE (1<<12) #define IR_LOOPBACK (1<<14) #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) #define IR_SIR_FLAGS (IRDA_BASE+0x24) #define IR_ENABLE (IRDA_BASE+0x28) #define IR_RX_STATUS (1<<9) #define IR_TX_STATUS (1<<10) #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) #define IR_CONFIG_2 (IRDA_BASE+0x3C) #define IR_MODE_INV (1<<0) #define IR_ONE_PIN (1<<1) #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) /* GPIO */ #define SYS_PINFUNC 0xB190002C #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ /* Au1100 Only */ #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ /* Au1550 Only. Redefines lots of pins */ #define SYS_PF_PSC2_MASK (7 << 17) #define SYS_PF_PSC2_AC97 (0) #define SYS_PF_PSC2_SPI (0) #define SYS_PF_PSC2_I2S (1 << 17) #define SYS_PF_PSC2_SMBUS (3 << 17) #define SYS_PF_PSC2_GPIO (7 << 17) #define SYS_PF_PSC3_MASK (7 << 20) #define SYS_PF_PSC3_AC97 (0) #define SYS_PF_PSC3_SPI (0) #define SYS_PF_PSC3_I2S (1 << 20) #define SYS_PF_PSC3_SMBUS (3 << 20) #define SYS_PF_PSC3_GPIO (7 << 20) #define SYS_PF_PSC1_S1 (1 << 1) #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 Only */ #ifdef CONFIG_SOC_AU1200 #define SYS_PINFUNC_DMA (1<<31) #define SYS_PINFUNC_S0A (1<<30) #define SYS_PINFUNC_S1A (1<<29) #define SYS_PINFUNC_LP0 (1<<28) #define SYS_PINFUNC_LP1 (1<<27) #define SYS_PINFUNC_LD16 (1<<26) #define SYS_PINFUNC_LD8 (1<<25) #define SYS_PINFUNC_LD1 (1<<24) #define SYS_PINFUNC_LD0 (1<<23) #define SYS_PINFUNC_P1A (3<<21) #define SYS_PINFUNC_P1B (1<<20) #define SYS_PINFUNC_FS3 (1<<19) #define SYS_PINFUNC_P0A (3<<17) #define SYS_PINFUNC_CS (1<<16) #define SYS_PINFUNC_CIM (1<<15) #define SYS_PINFUNC_P1C (1<<14) #define SYS_PINFUNC_U1T (1<<12) #define SYS_PINFUNC_U1R (1<<11) #define SYS_PINFUNC_EX1 (1<<10) #define SYS_PINFUNC_EX0 (1<<9) #define SYS_PINFUNC_U0R (1<<8) #define SYS_PINFUNC_MC (1<<7) #define SYS_PINFUNC_S0B (1<<6) #define SYS_PINFUNC_S0C (1<<5) #define SYS_PINFUNC_P0B (1<<4) #define SYS_PINFUNC_U0T (1<<3) #define SYS_PINFUNC_S1B (1<<2) #endif #define SYS_TRIOUTRD 0xB1900100 #define SYS_TRIOUTCLR 0xB1900100 #define SYS_OUTPUTRD 0xB1900108 #define SYS_OUTPUTSET 0xB1900108 #define SYS_OUTPUTCLR 0xB190010C #define SYS_PINSTATERD 0xB1900110 #define SYS_PININPUTEN 0xB1900110 /* GPIO2, Au1500, Au1550 only */ #define GPIO2_BASE 0xB1700000 #define GPIO2_DIR (GPIO2_BASE + 0) #define GPIO2_OUTPUT (GPIO2_BASE + 8) #define GPIO2_PINSTATE (GPIO2_BASE + 0xC) #define GPIO2_INTENABLE (GPIO2_BASE + 0x10) #define GPIO2_ENABLE (GPIO2_BASE + 0x14) /* Power Management */ #define SYS_SCRATCH0 0xB1900018 #define SYS_SCRATCH1 0xB190001C #define SYS_WAKEMSK 0xB1900034 #define SYS_ENDIAN 0xB1900038 #define SYS_POWERCTRL 0xB190003C #define SYS_WAKESRC 0xB190005C #define SYS_SLPPWR 0xB1900078 #define SYS_SLEEP 0xB190007C /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 #define SYS_FC_FRDIV2_BIT 22 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) #define SYS_FC_FE2 (1<<21) #define SYS_FC_FS2 (1<<20) #define SYS_FC_FRDIV1_BIT 12 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) #define SYS_FC_FE1 (1<<11) #define SYS_FC_FS1 (1<<10) #define SYS_FC_FRDIV0_BIT 2 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) #define SYS_FC_FE0 (1<<1) #define SYS_FC_FS0 (1<<0) #define SYS_FREQCTRL1 0xB1900024 #define SYS_FC_FRDIV5_BIT 22 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) #define SYS_FC_FE5 (1<<21) #define SYS_FC_FS5 (1<<20) #define SYS_FC_FRDIV4_BIT 12 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) #define SYS_FC_FE4 (1<<11) #define SYS_FC_FS4 (1<<10) #define SYS_FC_FRDIV3_BIT 2 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) #define SYS_FC_FE3 (1<<1) #define SYS_FC_FS3 (1<<0) #define SYS_CLKSRC 0xB1900028 #define SYS_CS_ME1_BIT 27 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) #define SYS_CS_DE1 (1<<26) #define SYS_CS_CE1 (1<<25) #define SYS_CS_ME0_BIT 22 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) #define SYS_CS_DE0 (1<<21) #define SYS_CS_CE0 (1<<20) #define SYS_CS_MI2_BIT 17 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) #define SYS_CS_DI2 (1<<16) #define SYS_CS_CI2 (1<<15) #ifdef CONFIG_SOC_AU1100 #define SYS_CS_ML_BIT 7 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) #define SYS_CS_DL (1<<6) #define SYS_CS_CL (1<<5) #else #define SYS_CS_MUH_BIT 12 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) #define SYS_CS_DUH (1<<11) #define SYS_CS_CUH (1<<10) #define SYS_CS_MUD_BIT 7 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) #define SYS_CS_DUD (1<<6) #define SYS_CS_CUD (1<<5) #endif #define SYS_CS_MIR_BIT 2 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) #define SYS_CS_DIR (1<<1) #define SYS_CS_CIR (1<<0) #define SYS_CS_MUX_AUX 0x1 #define SYS_CS_MUX_FQ0 0x2 #define SYS_CS_MUX_FQ1 0x3 #define SYS_CS_MUX_FQ2 0x4 #define SYS_CS_MUX_FQ3 0x5 #define SYS_CS_MUX_FQ4 0x6 #define SYS_CS_MUX_FQ5 0x7 #define SYS_CPUPLL 0xB1900060 #define SYS_AUXPLL 0xB1900064 /* AC97 Controller */ #define AC97C_CONFIG 0xB0000000 #define AC97C_RECV_SLOTS_BIT 13 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) #define AC97C_XMIT_SLOTS_BIT 3 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) #define AC97C_SG (1<<2) #define AC97C_SYNC (1<<1) #define AC97C_RESET (1<<0) #define AC97C_STATUS 0xB0000004 #define AC97C_XU (1<<11) #define AC97C_XO (1<<10) #define AC97C_RU (1<<9) #define AC97C_RO (1<<8) #define AC97C_READY (1<<7) #define AC97C_CP (1<<6) #define AC97C_TR (1<<5) #define AC97C_TE (1<<4) #define AC97C_TF (1<<3) #define AC97C_RR (1<<2) #define AC97C_RE (1<<1) #define AC97C_RF (1<<0) #define AC97C_DATA 0xB0000008 #define AC97C_CMD 0xB000000C #define AC97C_WD_BIT 16 #define AC97C_READ (1<<7) #define AC97C_INDEX_MASK 0x7f #define AC97C_CNTRL 0xB0000010 #define AC97C_RS (1<<1) #define AC97C_CE (1<<0) /* Secure Digital (SD) Controller */ #define SD0_XMIT_FIFO 0xB0600000 #define SD0_RECV_FIFO 0xB0600004 #define SD1_XMIT_FIFO 0xB0680000 #define SD1_RECV_FIFO 0xB0680004 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) #define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr /* All of our structures, like pci resource, have 32 bit members. * Drivers are expected to do an ioremap on the PCI MEM resource, but it's * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM * addresses. For PCI IO, it's simpler because we get to do the ioremap * ourselves and then adjust the device's resources. */ #define Au1500_EXT_CFG 0x600000000ULL #define Au1500_EXT_CFG_TYPE1 0x680000000ULL #define Au1500_PCI_IO_START 0x500000000ULL #define Au1500_PCI_IO_END 0x5000FFFFFULL #define Au1500_PCI_MEM_START 0x440000000ULL #define Au1500_PCI_MEM_END 0x44FFFFFFFULL #define PCI_IO_START (Au1500_PCI_IO_START + 0x1000) #define PCI_IO_END (Au1500_PCI_IO_END) #define PCI_MEM_START (Au1500_PCI_MEM_START) #define PCI_MEM_END (Au1500_PCI_MEM_END) #define PCI_FIRST_DEVFN (0<<3) #define PCI_LAST_DEVFN (19<<3) #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff /* * Borrowed from the PPC arch: * The following macro is used to lookup irqs in a standard table * format for those PPC systems that do not already have PCI * interrupts properly routed. */ /* FIXME - double check this from asm-ppc/pci-bridge.h */ #define PCI_IRQ_TABLE_LOOKUP \ ({ long _ctl_ = -1; \ if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ _ctl_; }) #else /* Au1000 and Au1100 and Au1200 */ /* don't allow any legacy ports probing */ #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff #define PCI_IO_START 0 #define PCI_IO_END 0 #define PCI_MEM_START 0 #define PCI_MEM_END 0 #define PCI_FIRST_DEVFN 0 #define PCI_LAST_DEVFN 0 #endif #ifndef _LANGUAGE_ASSEMBLY typedef volatile struct { /* 0x0000 */ u32 toytrim; /* 0x0004 */ u32 toywrite; /* 0x0008 */ u32 toymatch0; /* 0x000C */ u32 toymatch1; /* 0x0010 */ u32 toymatch2; /* 0x0014 */ u32 cntrctrl; /* 0x0018 */ u32 scratch0; /* 0x001C */ u32 scratch1; /* 0x0020 */ u32 freqctrl0; /* 0x0024 */ u32 freqctrl1; /* 0x0028 */ u32 clksrc; /* 0x002C */ u32 pinfunc; /* 0x0030 */ u32 reserved0; /* 0x0034 */ u32 wakemsk; /* 0x0038 */ u32 endian; /* 0x003C */ u32 powerctrl; /* 0x0040 */ u32 toyread; /* 0x0044 */ u32 rtctrim; /* 0x0048 */ u32 rtcwrite; /* 0x004C */ u32 rtcmatch0; /* 0x0050 */ u32 rtcmatch1; /* 0x0054 */ u32 rtcmatch2; /* 0x0058 */ u32 rtcread; /* 0x005C */ u32 wakesrc; /* 0x0060 */ u32 cpupll; /* 0x0064 */ u32 auxpll; /* 0x0068 */ u32 reserved1; /* 0x006C */ u32 reserved2; /* 0x0070 */ u32 reserved3; /* 0x0074 */ u32 reserved4; /* 0x0078 */ u32 slppwr; /* 0x007C */ u32 sleep; /* 0x0080 */ u32 reserved5[32]; /* 0x0100 */ u32 trioutrd; #define trioutclr trioutrd /* 0x0104 */ u32 reserved6; /* 0x0108 */ u32 outputrd; #define outputset outputrd /* 0x010C */ u32 outputclr; /* 0x0110 */ u32 pinstaterd; #define pininputen pinstaterd } AU1X00_SYS; static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE; #endif /* Processor information base on prid. * Copied from PowerPC. */ #ifndef _LANGUAGE_ASSEMBLY struct cpu_spec { /* CPU is matched via (PRID & prid_mask) == prid_value */ unsigned int prid_mask; unsigned int prid_value; char *cpu_name; unsigned char cpu_od; /* Set Config[OD] */ unsigned char cpu_bclk; /* Enable BCLK switching */ }; extern struct cpu_spec cpu_specs[]; extern struct cpu_spec *cur_cpu_spec[]; #endif #endif ���������������������������������skyeye-1.2.5_REL/arch/bfin/�������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023523236�014066� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/Makefile.in��������������������������������������������������������������0000644�0001750�0000144�00000051130�11023514464�016136� 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�ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������bfin_mach = mach/bf533_io.c mach/bf537_io.c bfin_comm = common/bfin_arch_interface.c common/bfin-dis.c common/iomem.c libbfin_a_SOURCES = $(bfin_mach) $(bfin_comm) noinst_LIBRARIES = libbfin.a INCLUDES = -I./common -I./mach -I$(top_srcdir)/utils/debugger -I$(top_srcdir)/device/uart @COMMON_INCLUDES@ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015351� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/sysname.h���������������������������������������������������������0000644�0001750�0000144�00000013740�10571721153�017220� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* sysname.c - definition for linux system call Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/21/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __SYSNAME_H__ #define __SYSNAME_H__ char * sys_name[] = { "NONE", " __NR_exit ", " __NR_fork ", " __NR_read ", " __NR_write ", " __NR_open ", " __NR_close ", " __NR_waitpid ", " __NR_creat ", " __NR_link ", " __NR_unlink ", " __NR_execve ", " __NR_chdir ", " __NR_time ", " __NR_mknod ", " __NR_chmod ", " __NR_chown ", " __NR_dump ", " __NR_oldstat ", " __NR_lseek ", " __NR_getpid ", " __NR_mount ", " __NR_umount ", " __NR_setuid ", " __NR_getuid ", " __NR_stime ", " __NR_ptrace ", " __NR_alarm ", " __NR_oldfstat ", " __NR_pause ", " __NR_utime ", " __NR_stty ", " __NR_gtty ", " __NR_access ", " __NR_nice ", " __NR_ftime ", " __NR_sync ", " __NR_kill ", " __NR_rename ", " __NR_mkdir ", " __NR_rmdir ", " __NR_dup ", " __NR_pipe ", " __NR_times ", " __NR_prof ", " __NR_brk ", " __NR_setgid ", " __NR_getgid ", " __NR_signal ", " __NR_geteuid ", " __NR_getegid ", " __NR_acct ", " __NR_umount2 ", " __NR_lock ", " __NR_ioctl ", " __NR_fcntl ", " __NR_mpx ", " __NR_setpgid ", " __NR_ulimit ", " __NR_oldolduname ", " __NR_umask ", " __NR_chroot ", " __NR_ustat ", " __NR_dup2 ", " __NR_getppid ", " __NR_getpgrp ", " __NR_setsid ", " __NR_sigaction ", " __NR_sgetmask ", " __NR_ssetmask ", " __NR_setreuid ", " __NR_setregid ", " __NR_sigsuspend ", " __NR_sigpending ", " __NR_sethostname ", " __NR_setrlimit ", " __NR_old_getrlimit ", " __NR_getrusage ", " __NR_gettimeofday ", " __NR_settimeofday ", " __NR_getgroups ", " __NR_setgroups ", " __NR_select ", " __NR_symlink ", " __NR_oldlstat ", " __NR_readlink ", " __NR_uselib ", " __NR_swapon ", " __NR_reboot ", " __NR_readdir ", " __NR_mmap ", " __NR_munmap ", " __NR_truncate ", " __NR_ftruncate ", " __NR_fchmod ", " __NR_fchown ", " __NR_getpriority ", " __NR_setpriority ", " __NR_profil ", " __NR_statfs ", " __NR_fstatfs ", " __NR_ioperm ", " __NR_socketcall ", " __NR_syslog ", " __NR_setitimer ", " __NR_getitimer ", " __NR_stat ", " __NR_lstat ", " __NR_fstat ", " __NR_olduname ", "NONE", " __NR_vhangup ", "NONE", "NONE", " __NR_wait4 ", " __NR_swapoff ", " __NR_sysinfo ", " __NR_ipc ", " __NR_fsync ", " __NR_sigreturn ", " __NR_clone ", " __NR_setdomainname ", " __NR_uname ", " __NR_cacheflush ", " __NR_adjtimex ", " __NR_mprotect ", " __NR_sigprocmask ", " __NR_create_module ", " __NR_init_module ", " __NR_delete_module ", " __NR_get_kernel_syms ", " __NR_quotactl ", " __NR_getpgid ", " __NR_fchdir ", " __NR_bdflush ", " __NR_sysfs ", " __NR_personality ", " __NR_afs_syscall ", /* Syscall for Andrew File System */ " __NR_setfsuid ", " __NR_setfsgid ", " __NR__llseek ", " __NR_getdents ", " __NR__newselect ", " __NR_flock ", " __NR_msync ", " __NR_readv ", " __NR_writev ", " __NR_getsid ", " __NR_fdatasync ", " __NR__sysctl ", " __NR_mlock ", " __NR_munlock ", " __NR_mlockall ", " __NR_munlockall ", " __NR_sched_setparam ", " __NR_sched_getparam ", " __NR_sched_setscheduler ", " __NR_sched_getscheduler ", " __NR_sched_yield ", " __NR_sched_get_priority_max ", " __NR_sched_get_priority_min ", " __NR_sched_rr_get_interval ", " __NR_nanosleep ", " __NR_mremap ", " __NR_setresuid ", " __NR_getresuid ", " __NR_query_module ", " __NR_poll ", " __NR_nfsservctl ", " __NR_setresgid ", " __NR_getresgid ", " __NR_prctl ", " __NR_rt_sigreturn ", " __NR_rt_sigaction ", " __NR_rt_sigprocmask ", " __NR_rt_sigpending ", " __NR_rt_sigtimedwait ", " __NR_rt_sigqueueinfo ", " __NR_rt_sigsuspend ", " __NR_pread ", " __NR_pwrite ", " __NR_lchown ", " __NR_getcwd ", " __NR_capget ", " __NR_capset ", " __NR_sigaltstack ", " __NR_sendfile ", " __NR_getpmsg ", " __NR_putpmsg ", " __NR_vfork ", " __NR_getrlimit ", " __NR_mmap2 ", " __NR_truncate64 ", " __NR_ftruncate64 ", " __NR_stat64 ", " __NR_lstat64 ", " __NR_fstat64 ", " __NR_chown32 ", " __NR_getuid32 ", " __NR_getgid32 ", " __NR_geteuid32 ", " __NR_getegid32 ", " __NR_setreuid32 ", " __NR_setregid32 ", " __NR_getgroups32 ", " __NR_setgroups32 ", " __NR_fchown32 ", " __NR_setresuid32 ", " __NR_getresuid32 ", " __NR_setresgid32 ", " __NR_getresgid32 ", " __NR_lchown32 ", " __NR_setuid32 ", " __NR_setgid32 ", " __NR_setfsuid32 ", " __NR_setfsgid32 ", " __NR_pivot_root ", " __NR_mincore ", " __NR_madvise ", " __NR_getdents64 ", " __NR_fcntl64 ", " __NR_gettid ", " __NR_readahead ", " __NR_setxattr ", " __NR_lsetxattr ", " __NR_fsetxattr ", " __NR_getxattr ", " __NR_lgetxattr ", " __NR_fgetxattr ", " __NR_listxattr ", " __NR_llistxattr ", " __NR_flistxattr ", " __NR_removexattr ", " __NR_lremovexattr ", " __NR_fremovexattr ", " __NR_tkill ", " __NR_sendfile64 ", " __NR_futex ", " __NR_sched_setaffinity ", " __NR_sched_getaffinity ", " __NR_set_thread_area ", " __NR_get_thread_area ", " __NR_io_setup ", " __NR_io_destroy ", " __NR_io_getevents ", " __NR_io_submit ", " __NR_io_cancel ", " __NR_fadvise64 ", " __NR_exit_group ", " __NR_lookup_dcookie ", " __NR_syscall " }; #endif ��������������������������������skyeye-1.2.5_REL/arch/bfin/common/mem_map.h���������������������������������������������������������0000644�0001750�0000144�00000003101�10557302136�017142� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mem_map.h - memory map of bf533 Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/12/2007 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __MEM_MAP_H__ #define __MEM_MAP_H__ #define IO_START 0xffc00000 #define IO_END 0xffffffff #define ISRAM_SIZE 0x14000 #define ISRAM_START 0xFFA00000 #define ISRAM_END (ISRAM_START+ISRAM_SIZE) #define DSRAM_SIZE 0x18000 #define DSRAM_START 0xFF800000 #define DSRAM_END (DSRAM_START+DSRAM_SIZE) //psw 061606 scratchpad #define SSRAM_SIZE 0x1000 #define SSRAM_START 0xFFB00000 #define SSRAM_END (SSRAM_START+SSRAM_SIZE) #define BANK0_START 0x20000000 #define BANK3_END 0x20400000 #define SDRAM_START 0x0 #define SDRAM_END 0x08000000 #define SDRAM_SIZE (SDRAM_END-SDRAM_START) #endif ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/bfin-dis.c��������������������������������������������������������0000644�0001750�0000144�00000431256�10642320132�017224� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * Copyright (c) 2000, 2001 Analog Devices Inc. * Copyright (c) 2003 Metrowerks * */ #include <stdio.h> #include <stdlib.h> #include <string.h> #include <signal.h> #include "opcode/bfin.h" #define M_S2RND 1 #define M_T 2 #define M_W32 3 #define M_FU 4 #define M_TFU 6 #define M_IS 8 #define M_ISS2 9 #define M_IH 11 #define M_IU 12 #ifndef PRINTF #define PRINTF printf #endif #ifndef EXIT #define EXIT skyeye_exit #endif typedef int TIword; #define HOST_LONG_WORD_SIZE (sizeof(long)*8) #define XFIELD(w,p,s) (((w)&((1<<(s))-1)<<(p))>>(p)) #define SIGNEXTEND(v, n) (((bs32)v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n))) #include "bfin-sim.h" #include "iomem.h" /* For dealing with parallel instructions, we must avoid changing our register file until all parallel insns have been simulated. This queue of stores can be used to delay a modification. @@@ Should go and convert all 32 bit insns to use this. */ struct store { bu32 *addr; bu32 val; }; struct store stores[10]; int n_stores; #define STORE(X,Y) do { \ stores[n_stores].addr = &(X); \ stores[n_stores++].val = (Y); \ } while (0) static __attribute__ ((noreturn)) void unhandled_instruction (void) { printf ("\nolderpc=%x,oldpc=%x\n,pc=0x%x,iw0=0x%x,iw1=0x%x\n", OLDERPCREG, OLDPCREG, PCREG, get_word (saved_state.memory, PCREG), get_word (saved_state.memory, PCREG + 2)); raise (SIGILL); fprintf (stderr, "unhandled instruction ... aborting\n"); abort (); } static void setflags_nz (bu32 val) { saved_state.az = val == 0; saved_state.an = val >> 31; } static void setflags_logical (bu32 val) { setflags_nz (val); saved_state.ac0 = 0; saved_state.v = 0; } static bu32 ashiftrt (bu32 val, int cnt) { int real_cnt = cnt > 32 ? 32 : cnt; bu32 sgn = ~((val >> 31) - 1); int sgncnt = 32 - real_cnt; if (sgncnt > 16) sgn <<= 16, sgncnt -= 16; sgn <<= sgncnt; if (real_cnt > 16) val >>= 16, real_cnt -= 16; val >>= real_cnt; val |= sgn; saved_state.an = val >> 31; saved_state.az = val == 0; /* @@@ */ saved_state.v = 0; return val; } static bu32 lshiftrt (bu32 val, int cnt) { int real_cnt = cnt > 32 ? 32 : cnt; if (real_cnt > 16) val >>= 16, real_cnt -= 16; val >>= real_cnt; saved_state.an = val >> 31; saved_state.az = val == 0; saved_state.v = 0; return val; } static bu32 lshift (bu32 val, int cnt) { int real_cnt = cnt > 32 ? 32 : cnt; if (real_cnt > 16) val <<= 16, real_cnt -= 16; val <<= real_cnt; saved_state.an = val >> 31; saved_state.az = val == 0; saved_state.v = 0; return val; } static bu32 add32 (bu32 a, bu32 b, int carry) { int flgs = a >> 31; int flgo = b >> 31; bu32 v = a + b; int flgn = v >> 31; int overflow = (flgs ^ flgn) & (flgo ^ flgn); saved_state.an = flgn; saved_state.vs |= overflow; saved_state.v = overflow; saved_state.v_internal |= overflow; saved_state.az = v == 0; if (carry) saved_state.ac0 = ~a < b; return v; } static bu32 sub32 (bu32 a, bu32 b, int carry) { int flgs = a >> 31; int flgo = b >> 31; bu32 v = a - b; int flgn = v >> 31; int overflow = (flgs ^ flgo) & (flgn ^ flgs); saved_state.an = flgn; saved_state.vs |= overflow; saved_state.v = overflow; saved_state.v_internal |= overflow; saved_state.az = v == 0; if (carry) saved_state.ac0 = b <= a; return v; } static bu32 min32 (bu32 a, bu32 b) { int val = a; if ((bs32) a > (bs32) b) val = b; setflags_nz (val); saved_state.v = 0; return val; } static bu32 max32 (bu32 a, bu32 b) { int val = a; if ((bs32) a < (bs32) b) val = b; setflags_nz (val); saved_state.v = 0; return val; } static bu32 add_and_shift (bu32 a, bu32 b, int shift) { int v; saved_state.v_internal = 0; v = add32 (a, b, 0); while (shift-- > 0) { int x = v >> 30; if (x == 1 || x == 2) saved_state.v_internal = 1; v <<= 1; } saved_state.v = saved_state.v_internal; saved_state.vs |= saved_state.v; return v; } typedef enum { c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4, c_imm4, c_uimm4s4, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_uimm5, c_imm6, c_imm7, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, c_uimm16, c_pcrel24, } const_forms_t; static struct { char *name; int nbits; char reloc; char issigned; char pcrel; char scale; char offset; char negative; char positive; } constant_formats[] = { { "0", 0, 0, 1, 0, 0, 0, 0, 0}, { "1", 0, 0, 1, 0, 0, 0, 0, 0}, { "4", 0, 0, 1, 0, 0, 0, 0, 0}, { "2", 0, 0, 1, 0, 0, 0, 0, 0}, { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0}, { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0}, { "imm3", 3, 0, 1, 0, 0, 0, 0, 0}, { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0}, { "imm4", 4, 0, 1, 0, 0, 0, 0, 0}, { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1}, { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0}, { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1}, { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0}, { "imm5", 5, 0, 1, 0, 0, 0, 0, 0}, { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0}, { "imm6", 6, 0, 1, 0, 0, 0, 0, 0}, { "imm7", 7, 0, 1, 0, 0, 0, 0, 0}, { "imm8", 8, 0, 1, 0, 0, 0, 0, 0}, { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0}, { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0}, { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0}, { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0}, { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0}, { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0}, { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0}, { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0}, { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0}, { "imm16", 16, 0, 1, 0, 0, 0, 0, 0}, { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0}, { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0}, { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0}, { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0}, { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0}, { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0},}; static bu32 fmtconst (const_forms_t cf, bu32 x, bu32 pc) { if (0 && constant_formats[cf].reloc) { bu32 ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits) : x) + constant_formats[cf].offset) << constant_formats[cf].scale); if (constant_formats[cf].pcrel) ea += pc; // outf->print_address_func (ea, outf); return ea; } /* negative constants have an implied sign bit */ if (constant_formats[cf].negative) { int nb = constant_formats[cf].nbits + 1; x = x | (1 << constant_formats[cf].nbits); x = SIGNEXTEND (x, nb); } else if (constant_formats[cf].issigned) x = SIGNEXTEND (x, constant_formats[cf].nbits); x += constant_formats[cf].offset; x <<= constant_formats[cf].scale; return x; } #undef SIGNEXTEND #undef HOST_LONG_WORD_SIZE #define HOST_LONG_WORD_SIZE (sizeof(int)*8) #define SIGNEXTEND(v, n) (((long)(v) << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n))) enum machine_registers { REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w, REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, REG_AZ, REG_AN, REG_AC, REG_AV0, REG_AV1, REG_AQ, REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0, REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3, REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, REG_LASTREG, }; enum reg_class { rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext, rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs, rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2, rc_sysregs3, rc_allregs, LIM_REG_CLASSES }; static char *reg_names[] = { "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", "A0.x", "A1.x", "A0.w", "A1.w", "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3", "AZ", "AN", "AC", "AV0", "AV1", "AQ", "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0", "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L", "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L", "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H", "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H", "LASTREG", 0 }; #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......") /* RL(0..7) */ static enum machine_registers decode_dregs_lo[] = { REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, }; #define dregs_lo(x) REGNAME(decode_dregs_lo[(x) & 7]) /* RH(0..7) */ static enum machine_registers decode_dregs_hi[] = { REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, }; #define dregs_hi(x) REGNAME(decode_dregs_hi[(x) & 7]) /* R(0..7) */ static enum machine_registers decode_dregs[] = { REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, }; #define dregs(x) REGNAME(decode_dregs[(x) & 7]) /* R BYTE(0..7) */ static enum machine_registers decode_dregs_byte[] = { REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7, }; #define dregs_byte(x) REGNAME(decode_dregs_byte[(x) & 7]) /* R1:0 - R3:2 - R5:4 - R7:6 - */ static enum machine_registers decode_dregs_pair[] = { REG_R1_0, REG_LASTREG, REG_R3_2, REG_LASTREG, REG_R5_4, REG_LASTREG, REG_R7_6, REG_LASTREG, }; #define dregs_pair(x) REGNAME(decode_dregs_pair[(x) & 7]) /* P(0..5) SP FP */ static enum machine_registers decode_pregs[] = { REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, }; #define pregs(x) REGNAME(decode_pregs[(x) & 7]) /* SP FP */ static enum machine_registers decode_spfp[] = { REG_SP, REG_FP, }; #define spfp(x) REGNAME(decode_spfp[(x) & 1]) /* [dregs_lo dregs_hi] */ static enum machine_registers decode_dregs_hilo[] = { REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, }; #define dregs_hilo(x,i) REGNAME(decode_dregs_hilo[((i)<<3)|x]) /* A0x A1x */ static enum machine_registers decode_accum_ext[] = { REG_A0x, REG_A1x, }; #define accum_ext(x) REGNAME(decode_accum_ext[(x) & 1]) /* A0w A1w */ static enum machine_registers decode_accum_word[] = { REG_A0w, REG_A1w, }; #define accum_word(x) REGNAME(decode_accum_word[(x) & 1]) /* A0 A1 */ static enum machine_registers decode_accum[] = { REG_A0, REG_A1, }; #define accum(x) REGNAME(decode_accum[(x) & 1]) /* I(0..3) */ static enum machine_registers decode_iregs[] = { REG_I0, REG_I1, REG_I2, REG_I3, }; #define iregs(x) REGNAME(decode_iregs[(x) & 3]) /* M(0..3) */ static enum machine_registers decode_mregs[] = { REG_M0, REG_M1, REG_M2, REG_M3, }; #define mregs(x) REGNAME(decode_mregs[(x) & 3]) /* B(0..3) */ static enum machine_registers decode_bregs[] = { REG_B0, REG_B1, REG_B2, REG_B3, }; #define bregs(x) REGNAME(decode_bregs[(x) & 3]) /* L(0..3) */ static enum machine_registers decode_lregs[] = { REG_L0, REG_L1, REG_L2, REG_L3, }; #define lregs(x) REGNAME(decode_lregs[(x) & 3]) /* dregs pregs */ static enum machine_registers decode_dpregs[] = { REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, }; #define dpregs(x) REGNAME(decode_dpregs[(x) & 15]) /* [dregs pregs] */ static enum machine_registers decode_gregs[] = { REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, }; #define gregs(x,i) REGNAME(decode_gregs[((i)<<3)|x]) /* [dregs pregs (iregs mregs) (bregs lregs)] */ static enum machine_registers decode_regs[] = { REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, }; #define regs(x,i) REGNAME(decode_regs[((i)<<3)|x]) /* [dregs pregs (iregs mregs) (bregs lregs) Low Half] */ static enum machine_registers decode_regs_lo[] = { REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, }; #define regs_lo(x,i) REGNAME(decode_regs_lo[((i)<<3)|x]) /* [dregs pregs (iregs mregs) (bregs lregs) High Half] */ static enum machine_registers decode_regs_hi[] = { REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_LH2, REG_MH3, REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, }; #define regs_hi(x,i) REGNAME(decode_regs_hi[((i)<<3)|x]) /* AZ AN AC AV0 AV1 - AQ - - - - - - - - - - - - - - - - - - - - - - - - - */ static enum machine_registers decode_statbits[] = { REG_AZ, REG_AN, REG_AC, REG_AV0, REG_AV1, REG_LASTREG, REG_AQ, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, }; /*static enum machine_registers decode_statbits[] = { REG_AZ, REG_AN, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG, REG_AV0, REG_LASTREG, REG_AV1, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_V, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, };*/ #define statbits(x) REGNAME(decode_statbits[(x) & 31]) /* sftreset omode excause emucause idle_req hwerrcause */ static enum machine_registers decode_ignore_bits[] = { REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, }; #define ignore_bits(x) REGNAME(decode_ignore_bits[(x) & 7]) /* CC */ static enum machine_registers decode_ccstat[] = { REG_CC, }; #define ccstat(x) REGNAME(decode_ccstat[(x) & 0]) /* LC0 LC1 */ static enum machine_registers decode_counters[] = { REG_LC0, REG_LC1, }; #define counters(x) REGNAME(decode_counters[(x) & 1]) /* A0x A0w A1x A1w GP - ASTAT RETS */ static enum machine_registers decode_dregs2_sysregs1[] = { REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS, }; #define dregs2_sysregs1(x) REGNAME(decode_dregs2_sysregs1[(x) & 7]) /* - - - - - - - - */ static enum machine_registers decode_open[] = { REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, }; #define open(x) REGNAME(decode_open[(x) & 7]) /* LC0 LT0 LB0 LC1 LT1 LB1 CYCLES CYCLES2 */ static enum machine_registers decode_sysregs2[] = { REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, }; #define sysregs2(x) REGNAME(decode_sysregs2[(x) & 7]) /* USP SEQSTAT SYSCFG RETI RETX RETN RETE - */ static enum machine_registers decode_sysregs3[] = { REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_LASTREG, }; #define sysregs3(x) REGNAME(decode_sysregs3[(x) &7]) /* [dregs pregs (iregs mregs) (bregs lregs) dregs2_sysregs1 open sysregs2 sysregs3] */ static enum machine_registers decode_allregs[] = { REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_LASTREG, }; #define allregs(x,i) REGNAME(decode_allregs[((i)<<3)|x]) #define uimm16s4(x) fmtconst(c_uimm16s4, x, 0) #define pcrel4(x) fmtconst(c_pcrel4, x, pc) #define pcrel8(x) fmtconst(c_pcrel8, x, pc) #define pcrel8s4(x) fmtconst(c_pcrel8s4, x, pc) #define pcrel10(x) fmtconst(c_pcrel10, x, pc) #define pcrel12(x) fmtconst(c_pcrel12, x, pc) #define negimm5s4(x) fmtconst(c_negimm5s4, x, 0) #define rimm16(x) fmtconst(c_rimm16, x, 0) #define huimm16(x) fmtconst(c_huimm16, x, 0) #define imm16(x) fmtconst(c_imm16, x, 0) #define uimm2(x) fmtconst(c_uimm2, x, 0) #define uimm3(x) fmtconst(c_uimm3, x, 0) #define luimm16(x) fmtconst(c_luimm16, x, 0) #define uimm4(x) fmtconst(c_uimm4, x, 0) #define uimm5(x) fmtconst(c_uimm5, x, 0) #define imm16s2(x) fmtconst(c_imm16s2, x, 0) #define uimm8(x) fmtconst(c_uimm8, x, 0) #define imm16s4(x) fmtconst(c_imm16s4, x, 0) #define uimm4s2(x) fmtconst(c_uimm4s2, x, 0) #define uimm4s4(x) fmtconst(c_uimm4s4, x, 0) #define lppcrel10(x) fmtconst(c_lppcrel10, x, pc) #define imm3(x) fmtconst(c_imm3, x, 0) #define imm4(x) fmtconst(c_imm4, x, 0) #define uimm8s4(x) fmtconst(c_uimm8s4, x, 0) #define imm5(x) fmtconst(c_imm5, x, 0) #define imm6(x) fmtconst(c_imm6, x, 0) #define imm7(x) fmtconst(c_imm7, x, 0) #define imm8(x) fmtconst(c_imm8, x, 0) #define pcrel24(x) fmtconst(c_pcrel24, x, pc) #define uimm16(x) fmtconst(c_uimm16, x, 0) /* (arch.pm)arch_disassembler_functions */ //#define notethat(x) printf("%s",x) #define notethat(x) //#define OUTS(p,txt) unhandled_instruction () #define OUTS(p,txt) static int * get_allreg (int grp, int reg) { int fullreg = (grp << 3) | reg; /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_LASTREG */ switch (fullreg >> 2) { case 0: case 1: return &DREG (reg); break; case 2: case 3: return &PREG (reg); break; case 4: return &IREG (reg & 3); break; case 5: return &MREG (reg & 3); break; case 6: return &BREG (reg & 3); break; case 7: return &LREG (reg & 3); break; default: //printf("fullreg=%x,group=%d\n",fullreg,fullreg >> 2); switch (fullreg) { case 0x20: return &A0XREG; case 0x21: return &A0WREG; case 0x22: return &A1XREG; case 0x23: return &A1WREG; case 0x26: return &ASTATREG; case 0x27: return &saved_state.rets; case 0x30: return &saved_state.lc[0]; case 0x31: return &saved_state.lt[0]; case 0x32: return &saved_state.lb[0]; case 0x33: return &saved_state.lc[1]; case 0x34: return &saved_state.lt[1]; case 0x35: return &saved_state.lb[1]; case 0x38: return &saved_state.usp; case 0x39: return &saved_state.syscfg; case 0x3a: return &SEQSTATREG; case 0x3b: return &RETIREG; case 0x3c: return &RETXREG; case 0x3d: return &RETNREG; case 0x3e: return &RETEREG; //printf("reg_syscfg\n"); } printf ("invalid register,fullreg=%x\n", fullreg); return 0; } } static void amod0 (int s0, int x0, bu32 pc) { if (s0 == 0 && x0 == 0) { notethat ("(NS)"); return; } else if (s0 == 1 && x0 == 0) { notethat ("(S)"); OUTS (outf, "(S)"); return; } else if (s0 == 0 && x0 == 1) { notethat ("(CO)"); OUTS (outf, "(CO)"); return; } else if (s0 == 1 && x0 == 1) { notethat ("(SCO)"); OUTS (outf, "(SCO)"); return; } else goto illegal_instruction; illegal_instruction: return; } static void amod1 (int s0, int x0, bu32 pc) { if (s0 == 0 && x0 == 0) { //notethat ("(NS)"); //OUTS (outf, "(NS)"); return; } else if (s0 == 1 && x0 == 0) { //notethat ("(S)"); // OUTS (outf, "(S)"); return; } else goto illegal_instruction; illegal_instruction: return; } static void macmod_accm (int mod, bu32 pc) { if (mod == 0) { notethat (""); return; } else if (mod == 8) { notethat ("(IS)"); OUTS (outf, "(IS)"); return; } else if (mod == 4) { notethat ("(FU)"); OUTS (outf, "(FU)"); return; } else if (mod == 3) { notethat ("(W32)"); OUTS (outf, "(W32)"); return; } else goto illegal_instruction; illegal_instruction: return; } static void searchmod (int r0, bu32 pc) { if (r0 == 0) { notethat ("GT"); OUTS (outf, "GT"); return; } else if (r0 == 1) { notethat ("GE"); OUTS (outf, "GE"); return; } else if (r0 == 2) { notethat ("LT"); OUTS (outf, "LT"); return; } else if (r0 == 3) { notethat ("LE"); OUTS (outf, "LE"); return; } else goto illegal_instruction; illegal_instruction: return; } static void mxd_mod (int mod, bu32 pc) { if (mod == 0) { notethat (""); return; } else if (mod == 1) { notethat ("(M)"); OUTS (outf, "(M)"); return; } else goto illegal_instruction; illegal_instruction: return; } static void aligndir (int r0, bu32 pc) { if (r0 == 0) { notethat (""); return; } else if (r0 == 1) { notethat ("(R)"); OUTS (outf, "(R)"); return; } else goto illegal_instruction; illegal_instruction: return; } /* Perform a multiplication, sign- or zero-extending the result to 64 bit. */ static bu64 decode_multfunc (int h0, int h1, int src0, int src1, int mmod, int MM) { bu32 s0 = DREG (src0), s1 = DREG (src1); bu32 sgn0, sgn1; bu32 val; bu64 val1; if (h0) s0 >>= 16; if (h1) s1 >>= 16; s0 &= 0xffff; s1 &= 0xffff; sgn0 = -(s0 & 0x8000); sgn1 = -(s1 & 0x8000); if (MM) s0 |= sgn0; else switch (mmod) { case 0: case M_S2RND: case M_T: case M_IS: case M_ISS2: case M_IH: s0 |= sgn0; s1 |= sgn1; break; case M_FU: case M_IU: case M_TFU: break; default: abort (); } val = s0 * s1; /* Perform shift correction if appropriate for the mode. */ if (mmod == 0 || mmod == M_T || mmod == M_S2RND) { if (val == 0x40000000) val = 0x7fffffff; else val <<= 1; } val1 = val; if (mmod == 0 || mmod == M_IS || mmod == M_T || mmod == M_S2RND || mmod == M_ISS2 || mmod == M_IH) val1 |= -(val1 & 0x80000000); return val1; } static bu32 saturate_s32 (bu64 val) { if ((bs64) val < -0x80000000ll) return 0x80000000; if ((bs64) val > 0x7fffffff) return 0x7fffffff; return val; } static bu32 saturate_s16 (bu64 val) { if ((bs64) val < -0x8000ll) return 0x8000; if ((bs64) val > 0x7fff) return 0x7fff; return val; } static bu32 saturate_u32 (bu64 val) { if (val > 0xffffffff) return 0xffffffff; return val; } static bu32 saturate_u16 (bu64 val) { if (val > 0xffff) return 0xffff; return val; } static bu64 rnd16 (bu64 val) { bu64 sgnbits = val & 0xff00000000000000ull; /* @@@ Should honour rounding mode. Can this overflow? */ val += 0x8000; val >>= 16; return val | sgnbits; } static bu64 trunc16 (bu64 val) { bu64 sgnbits = val & 0xff00000000000000ull; val >>= 16; return val | sgnbits; } /* Extract a 16 or 32 bit value from a 64 bit multiplication result. These 64 bits must be sign- or zero-extended properly from the source we want to extract, either a 32 bit multiply or a 40 bit accumulator. */ static bu32 extract_mult (bu64 res, int mmod, int fullword) { if (fullword) switch (mmod) { case 0: case M_IS: return saturate_s32 (res); case M_FU: return saturate_u32 (res); case M_S2RND: case M_ISS2: return saturate_s32 (res << 1); default: abort (); } else switch (mmod) { case 0: case M_IH: return saturate_s16 (rnd16 (res)); case M_IS: return saturate_s16 (res); case M_FU: return saturate_u16 (rnd16 (res)); case M_IU: return saturate_u16 (res); case M_T: return saturate_s16 (trunc16 (res)); case M_TFU: return saturate_u16 (trunc16 (res)); case M_S2RND: return saturate_s16 (rnd16 (res << 1)); case M_ISS2: return saturate_s16 (res << 1); default: abort (); } } static bu32 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, int mmod, int MM, int fullword) { bu64 *accum = which ? &A1REG : &A0REG; bu64 acc = *accum & 0xFFFFFFFFFFull; /* Sign extend accumulator if necessary. */ if (mmod == 0 || mmod == M_T || mmod == M_IS || mmod == M_ISS2 || mmod == M_S2RND) acc |= -(acc & 0x80000000); if (op != 3) { bu64 res = decode_multfunc (h0, h1, src0, src1, mmod, MM); /* Perform accumulation. */ switch (op) { case 0: *accum = res; break; case 1: *accum = acc + res; break; case 2: *accum = acc - res; break; } /* Saturate. */ switch (mmod) { case 0: case M_T: case M_IS: case M_ISS2: case M_S2RND: if ((bs64) * accum < -0x8000000000ll) *accum = -0x8000000000ull; else if ((bs64) * accum >= 0x7fffffffffll) *accum = 0x7fffffffffull; break; case M_TFU: case M_FU: case M_IU: if (*accum > 0xFFFFFFFFFFull) *accum = 0xFFFFFFFFFFull; break; default: abort (); } acc = *accum; } return extract_mult (acc, mmod, fullword); } static void decode_ProgCtrl_0 (bu16 iw0) { /* ProgCtrl +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int poprnd = ((iw0 >> 0) & 0xf); int prgfunc = ((iw0 >> 4) & 0xf); //PRINTF("\npoprud=%x,prgfunc=%x\n",poprnd,prgfunc); if (prgfunc == 0 && poprnd == 0) { //notethat ("NOP"); //PRINTF("NULL meory,pc=0x%x\n",PCREG); // fprintf(PF,"##############################NOP,pc=%x\n",PCREG); PCREG += 2; return; } else if (prgfunc == 1 && poprnd == 0) { //notethat ("RTS"); //PRINTF("DEBUG:pc = 0x%x\n",saved_state.rets); PCREG = RETSREG; return; } else if (prgfunc == 1 && poprnd == 1) { //PRINTF("DEBUG33\n"); //notethat ("RTI"); //OUTS (outf, "RTI"); /*0 is meaningless */ PCREG = RETIREG; /*clear global int bit in ipend */ saved_state.enable_int (); /*clear the responding pending bit */ saved_state.clear_int (0); //did_jump = 1; return; } else if (prgfunc == 1 && poprnd == 2) { notethat ("RTX"); OUTS (outf, "RTX"); //unhandled_instruction (); //fprintf(PF,"RTX\n"); /*clear global int bit in ipend */ saved_state.enable_int (); /*clear the responding pending bit */ saved_state.clear_int (0); PCREG = RETXREG; return; } else if (prgfunc == 1 && poprnd == 3) { notethat ("RTN"); OUTS (outf, "RTN"); unhandled_instruction (); PCREG = RETNREG; return; } else if (prgfunc == 1 && poprnd == 4) { notethat ("RTE"); OUTS (outf, "RTE"); unhandled_instruction (); PCREG = RETEREG; return; } else if (prgfunc == 2 && poprnd == 0) { notethat ("IDLE"); OUTS (outf, "IDLE"); //unhandled_instruction (); PCREG += 2; return; } else if (prgfunc == 2 && poprnd == 3) { // PRINTF("DEBUG22\n"); //notethat ("CSYNC"); //OUTS (outf, "CSYNC"); PCREG += 2; return; } else if (prgfunc == 2 && poprnd == 4) { // PRINTF("DEBUG11\n"); //notethat ("SSYNC"); //PRINTF("SSYNC"); //OUTS (outf, "SSYNC"); PCREG += 2; return; } else if (prgfunc == 2 && poprnd == 5) { notethat ("EMUEXCPT"); OUTS (outf, "EMUEXCPT"); unhandled_instruction (); PCREG += 2; return; } else if (prgfunc == 3) { // notethat ("CLI dregs"); // OUTS (outf, "CLI "); //OUTS (outf, dregs (poprnd)); saved_state.cli (&DREG (poprnd)); PCREG += 2; return; } else if (prgfunc == 4) { //notethat ("STI dregs"); // OUTS (outf, "STI"); // OUTS (outf, dregs (poprnd)); saved_state.sti (&DREG (poprnd)); PCREG += 2; return; } else if (prgfunc == 5) { notethat ("JUMP ( pregs )"); PCREG = PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 6) { notethat ("CALL ( pregs )"); saved_state.rets = PCREG + 2; PCREG = PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 7) { notethat ("CALL ( PC + pregs )"); saved_state.rets = PCREG + 2; PCREG = PCREG + PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 8) { notethat ("JUMP ( PC + pregs )"); PCREG = PCREG + PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 9) { extern int raise_flag; notethat ("RAISE uimm4"); //bfin_trap (); saved_state.set_int (poprnd); raise_flag = 1; PCREG += 2; return; } else if (prgfunc == 10) { notethat ("EXCPT uimm4"); if (uimm4 (poprnd) == 1) { //raise_exception(SIGTRAP); // single step exception dont increment PCREG ... PCREG += 2; return; } else { //fprintf(stderr, "unhandled exception1\n"); OUTS (outf, "EXCPT "); OUTS (outf, uimm4 (poprnd)); //fprintf(PF,"System call :pc=0x%x,oldpc=0x%x,olderpc=0x%x,EXCPT %x\n",PCREG,OLDPCREG,OLDERPCREG,uimm4 (poprnd)); saved_state.set_int (3); SEQSTATREG = SEQSTATREG & 0xffffffc0 + poprnd & 0x3f; //unhandled_instruction (); PCREG += 2; return; } } else if (prgfunc == 11) { notethat ("TESTSET ( pregs )"); OUTS (outf, "TESTSET "); OUTS (outf, "("); OUTS (outf, pregs (poprnd)); OUTS (outf, ")"); unhandled_instruction (); PCREG += 2; return; } else unhandled_instruction (); } #define NOT_IMP {fprintf(stderr,"pc=0x%x,p0=0x%x,p1=0x%x,not implemented cache ops \n",PCREG,PREG(0),PREG(1)); } static void decode_CaCTRL_0 (bu16 iw0) { /* CaCTRL +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int a = ((iw0 >> 5) & 0x1); int reg = ((iw0 >> 0) & 0x7); int op = ((iw0 >> 3) & 0x3); if (a == 0 && op == 0) { notethat ("PREFETCH [ pregs ]"); OUTS (outf, "PREFETCH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "]"); NOT_IMP; PCREG += 2; return; } else if (a == 0 && op == 1) { notethat ("FLUSHINV [ pregs ]"); OUTS (outf, "FLUSHINV"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "]"); NOT_IMP; PCREG += 2; return; } else if (a == 0 && op == 2) { notethat ("FLUSH [ pregs ]"); OUTS (outf, "FLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); NOT_IMP; OUTS (outf, "]"); PCREG += 2; return; } else if (a == 0 && op == 3) { notethat ("IFLUSH [ pregs ]"); OUTS (outf, "IFLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "]"); //unhandled_instruction (); NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 0) { notethat ("PREFETCH [ pregs ++ ]"); OUTS (outf, "PREFETCH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; //NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 1) { notethat ("FLUSHINV [ pregs ++ ]"); OUTS (outf, "FLUSHINV"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; //NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 2) { notethat ("FLUSH [ pregs ++ ]"); OUTS (outf, "FLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 3) { notethat ("IFLUSH [ pregs ++ ]"); OUTS (outf, "IFLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; NOT_IMP; PCREG += 2; return; } else unhandled_instruction (); } static void decode_PushPopReg_0 (bu16 iw0) { /* PushPopReg +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int grp = ((iw0 >> 3) & 0x7); int reg = ((iw0 >> 0) & 0x7); int W = ((iw0 >> 6) & 0x1); int *whichreg = get_allreg (grp, reg); if (whichreg == 0) { unhandled_instruction (); } if (W == 0) { bu32 word; notethat ("allregs = [ SP ++ ]"); *whichreg = get_long (saved_state.memory, PREG (6)); if (whichreg == &RETIREG) { /*disable the global int bit,until RTI is executed!Or other int maybe overwrite reti */ saved_state.disable_int (); } if (whichreg == &ASTATREG) { /*at the same time,restore CCREG */ CCREG = (ASTATREG & 0x20) >> 5; AZFLAG = ASTATREG & 0x1; AQFLAG = ASTATREG & 0x40 >> 6; //fprintf(PF,"pc=%x,restore cc=%x,SP=0x%x,astat=%x\n\n",PCREG,CCREG,PREG(6),ASTATREG); } PREG (6) += 4; } else { bu32 word; notethat ("[ -- SP ] = allregs"); PREG (6) -= 4; if (whichreg == &RETIREG) { /*enable the global int bit */ saved_state.enable_int (); } if (whichreg == &ASTATREG) { /*at the same time,save CCREG */ ASTATREG = AZFLAG ? (ASTATREG | 0x1) : (ASTATREG & (~0x1)); ASTATREG = CCREG ? (ASTATREG | 0x20) : (ASTATREG & (~0x20)); ASTATREG = AQFLAG ? (ASTATREG | 0x40) : (ASTATREG & (~0x40)); //fprintf(PF,"\npc=%x,save cc=%x,SP=0x%x,astat=%x\n",PCREG,CCREG,PREG(6),ASTATREG); } put_long (saved_state.memory, PREG (6), *whichreg); } /* if(PCREG >= 0x000087f8,PCREG <= 0x88cc) printf("iw0=0x%x,pc=0x%x\n",iw0,PCREG); */ PCREG += 2; return; } static void decode_PushPopMultiple_0 (bu16 iw0) { /* PushPopMultiple +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int p = ((iw0 >> 7) & 0x1); int pr = ((iw0 >> 0) & 0x7); int d = ((iw0 >> 8) & 0x1); int dr = ((iw0 >> 3) & 0x7); int W = ((iw0 >> 6) & 0x1); int i; bu32 sp = PREG (6); if (d == 0 && p == 0) unhandled_instruction (); if (p && imm5 (pr) > 5) unhandled_instruction (); if (W == 1) { if (d) for (i = dr; i < 8; i++) { sp -= 4; put_long (saved_state.memory, sp, DREG (i)); } if (p) for (i = pr; i < 6; i++) { sp -= 4; put_long (saved_state.memory, sp, PREG (i)); } } else { if (p) for (i = 5; i >= pr; i--) { PREG (i) = get_long (saved_state.memory, sp); sp += 4; } if (d) for (i = 7; i >= dr; i--) { DREG (i) = get_long (saved_state.memory, sp); sp += 4; } } PREG (6) = sp; PCREG += 2; return; } static void decode_ccMV_0 (bu16 iw0) { /* ccMV +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src = ((iw0 >> 0) & 0x7); int dst = ((iw0 >> 3) & 0x7); int s = ((iw0 >> 6) & 0x1); int d = ((iw0 >> 7) & 0x1); int T = ((iw0 >> 8) & 0x1); int cond = T ? CCREG : !CCREG; if (cond) GREG (dst, d) = GREG (src, s); PCREG += 2; return; } static void decode_CCflag_0 (bu16 iw0) { /* CCflag +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int x = ((iw0 >> 0) & 0x7); int y = ((iw0 >> 3) & 0x7); int I = ((iw0 >> 10) & 0x1); int opc = ((iw0 >> 7) & 0x7); int G = ((iw0 >> 6) & 0x1); if (opc > 4) { if (opc == 5 && I == 0 && G == 0) { notethat ("CC = A0 == A1"); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "=="); OUTS (outf, "A1"); unhandled_instruction (); PCREG += 2; return; } else if (opc == 6 && I == 0 && G == 0) { notethat ("CC = A0 < A1"); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "<"); OUTS (outf, "A1"); unhandled_instruction (); PCREG += 2; return; } else if (opc == 7 && I == 0 && G == 0) { notethat ("CC = A0 <= A1"); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "<="); OUTS (outf, "A1"); unhandled_instruction (); PCREG += 2; return; } } else { int issigned = opc < 3; bu32 srcop = G ? PREG (x) : DREG (x); bu32 dstop = I ? (issigned ? imm3 (y) : uimm3 (y)) : G ? PREG (y) : DREG (y); int flgs = srcop >> 31; int flgo = dstop >> 31; bu32 result = srcop - dstop; int flgn = result >> 31; int overflow = (flgs ^ flgo) & (flgn ^ flgs); saved_state.az = result == 0; saved_state.an = flgn; saved_state.ac0 = srcop < dstop; switch (opc) { case 0: /* == */ CCREG = saved_state.az; break; case 1: /* <, signed */ CCREG = (flgn && !overflow) || (!flgn && overflow); break; case 2: /* <=, signed */ CCREG = (flgn && !overflow) || (!flgn && overflow) || saved_state.az; break; case 3: /* <, unsigned */ CCREG = saved_state.ac0; break; case 4: /* <=, unsigned */ CCREG = saved_state.ac0 | saved_state.az; break; } PCREG += 2; return; } } static void decode_CC2dreg_0 (bu16 iw0) { /* CC2dreg +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int reg = ((iw0 >> 0) & 0x7); int op = ((iw0 >> 3) & 0x3); if (op == 0) { notethat ("dregs = CC"); DREG (reg) = CCREG; } else if (op == 1) { notethat ("CC = dregs"); CCREG = DREG (reg) != 0; } else if (op == 3) { notethat ("CC =! CC"); CCREG = !CCREG; } else unhandled_instruction (); PCREG += 2; } static void decode_CC2stat_0 (bu16 iw0) { /* CC2stat +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int cbit = ((iw0 >> 0) & 0x1f); int D = ((iw0 >> 7) & 0x1); int op = ((iw0 >> 5) & 0x3); int *pval; switch (cbit) { case 0: pval = &saved_state.az; break; case 1: pval = &saved_state.an; break; case 6: pval = &saved_state.aq; break; case 12: pval = &saved_state.ac0; break; case 13: pval = &saved_state.ac1; break; case 16: pval = &saved_state.av0; break; case 17: pval = &saved_state.av0s; break; case 18: pval = &saved_state.av1; break; case 19: pval = &saved_state.av1s; break; case 24: pval = &saved_state.v; break; case 25: pval = &saved_state.vs; break; default: unhandled_instruction (); } if (D == 0) switch (op) { case 0: CCREG = *pval; break; case 1: CCREG |= *pval; break; case 2: CCREG &= *pval; break; case 3: CCREG ^= *pval; break; } else switch (op) { case 0: *pval = CCREG; break; case 1: *pval |= CCREG; break; case 2: *pval &= CCREG; break; case 3: *pval ^= CCREG; break; } PCREG += 2; } static void decode_BRCC_0 (bu16 iw0, bu32 pc) { /* BRCC +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int B = ((iw0 >> 10) & 0x1); int T = ((iw0 >> 11) & 0x1); int offset = ((iw0 >> 0) & 0x3ff); /* B is just the branch predictor hint - we can ignore it. */ notethat ("IF CC JUMP pcrel10"); if (CCREG == T) { PCREG += pcrel10 (offset); did_jump = 1; } else PCREG += 2; return; } static void decode_UJUMP_0 (bu16 iw0, bu32 pc) { /* UJUMP +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 1 | 0 |.offset........................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int offset = ((iw0 >> 0) & 0xfff); notethat ("JUMP.S pcrel12"); PCREG += pcrel12 (offset); did_jump = 1; } static void decode_REGMV_0 (bu16 iw0) { /* REGMV +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src = ((iw0 >> 0) & 0x7); int gs = ((iw0 >> 6) & 0x7); int dst = ((iw0 >> 3) & 0x7); int gd = ((iw0 >> 9) & 0x7); int *srcreg = get_allreg (gs, src); int *dstreg = get_allreg (gd, dst); if (srcreg == 0 || dstreg == 0) { printf ("srcreg=%x,dstreg=%x\n", srcreg, dstreg); unhandled_instruction (); } *dstreg = *srcreg; PCREG += 2; return; } static void decode_ALU2op_0 (bu16 iw0) { /* ALU2op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src = ((iw0 >> 3) & 0x7); int opc = ((iw0 >> 6) & 0xf); int dst = ((iw0 >> 0) & 0x7); if (opc == 0) { notethat ("dregs >>>= dregs"); DREG (dst) = ashiftrt (DREG (dst), DREG (src)); } else if (opc == 1) { notethat ("dregs >>= dregs"); DREG (dst) = lshiftrt (DREG (dst), DREG (src)); } else if (opc == 2) { notethat ("dregs <<= dregs"); DREG (dst) = lshift (DREG (dst), DREG (src)); } else if (opc == 3) { notethat ("dregs *= dregs"); DREG (dst) *= DREG (src); } else if (opc == 4) { notethat ("dregs = (dregs + dregs) << 1"); DREG (dst) = add_and_shift (DREG (dst), DREG (src), 1); } else if (opc == 5) { notethat ("dregs = (dregs + dregs) << 2"); DREG (dst) = add_and_shift (DREG (dst), DREG (src), 2); } else if (opc == 8) { notethat ("DIVQ (dregs , dregs)"); OUTS (outf, "DIVQ"); OUTS (outf, "("); OUTS (outf, dregs (dst)); OUTS (outf, ","); OUTS (outf, dregs (src)); OUTS (outf, ")"); /*thanks to jie , I understand the DIVQ instn */ DREG (src) <<= 16; if (AQFLAG) DREG (dst) = DREG (dst) + DREG (src); else DREG (dst) = DREG (dst) - DREG (src); AQFLAG = ((DREG (dst) & 0x80000000) >> 31) ^ ((DREG (src) & 0x80000000) >> 31); DREG (dst) <<= 1; if (AQFLAG == 0) DREG (dst) += 1; DREG (src) >>= 16; PCREG += 2; return; } else if (opc == 9) { notethat ("DIVS (dregs , dregs)"); OUTS (outf, "DIVS"); OUTS (outf, "("); OUTS (outf, dregs (dst)); OUTS (outf, ","); OUTS (outf, dregs (src)); OUTS (outf, ")"); /*thanks to jie , I understand the DIVQ instn */ AQFLAG = ((DREG (dst) & 0x80000000) >> 31) ^ ((DREG (src) & 0x80000000) >> 31); /*DREG(src) <<= 16; if(AQFLAG) DREG(dst) = DREG(dst) + DREG(src); else DREG(dst) = DREG(dst) - DREG(src); DREG(src) >>= 16; */ DREG (dst) <<= 1; if (AQFLAG == 0) DREG (dst) += 1; PCREG += 2; return; } else if (opc == 10) { notethat ("dregs = dregs_lo (X)"); DREG (dst) = (bs32) (bs16) DREG (src); setflags_logical (DREG (dst)); } else if (opc == 11) { notethat ("dregs = dregs_lo (Z)"); DREG (dst) = (bu32) (bu16) DREG (src); setflags_logical (DREG (dst)); } else if (opc == 12) { notethat ("dregs = dregs_byte (X)"); DREG (dst) = (bs32) (bs8) DREG (src); setflags_logical (DREG (dst)); } else if (opc == 13) { notethat ("dregs = dregs_byte (Z)"); DREG (dst) = (bu32) (bu8) DREG (src); setflags_logical (DREG (dst)); } else if (opc == 14) { bu32 val = DREG (src); notethat ("dregs = - dregs"); DREG (dst) = -val; setflags_nz (DREG (dst)); if (val == 0x80000000) { saved_state.v = saved_state.vs = 1; } /* @@@ Documentation isn't entirely clear about av0 and av1. */ } else if (opc == 15) { notethat ("dregs = ~ dregs"); DREG (dst) = ~DREG (src); setflags_logical (DREG (dst)); } else unhandled_instruction (); PCREG += 2; return; } static void decode_PTR2op_0 (bu16 iw0) { /* PTR2op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src = ((iw0 >> 3) & 0x7); int opc = ((iw0 >> 6) & 0x7); int dst = ((iw0 >> 0) & 0x7); if (opc == 0) PREG (dst) -= PREG (src); else if (opc == 1) PREG (dst) = PREG (src) << 2; else if (opc == 3) PREG (dst) = PREG (src) >> 2; else if (opc == 4) PREG (dst) = PREG (src) >> 1; else if (opc == 5) { notethat ("pregs += pregs ( BREV )"); unhandled_instruction (); OUTS (outf, pregs (dst)); OUTS (outf, "+="); OUTS (outf, pregs (src)); OUTS (outf, "("); OUTS (outf, "BREV"); OUTS (outf, ")"); } else if (opc == 6) PREG (dst) = (PREG (dst) + PREG (src)) << 1; else if (opc == 7) PREG (dst) = (PREG (dst) + PREG (src)) << 2; else unhandled_instruction (); PCREG += 2; return; } static void decode_LOGI2op_0 (bu16 iw0) { /* LOGI2op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src = ((iw0 >> 3) & 0x1f); int opc = ((iw0 >> 8) & 0x7); int dst = ((iw0 >> 0) & 0x7); if (opc == 0) { notethat ("CC = ! BITTST ( dregs , uimm5 )"); CCREG = (~DREG (dst) >> uimm5 (src)) & 1; } else if (opc == 1) { notethat ("CC = BITTST ( dregs , uimm5 )"); CCREG = (DREG (dst) >> uimm5 (src)) & 1; } else if (opc == 2) { notethat ("BITSET ( dregs , uimm5 )"); DREG (dst) |= 1 << uimm5 (src); setflags_logical (DREG (dst)); } else if (opc == 3) { notethat ("BITTGL ( dregs , uimm5 )"); DREG (dst) ^= 1 << uimm5 (src); setflags_logical (DREG (dst)); } else if (opc == 4) { notethat ("BITCLR ( dregs , uimm5 )"); DREG (dst) &= ~(1 << uimm5 (src)); setflags_logical (DREG (dst)); } else if (opc == 5) { notethat ("dregs >>>= uimm5"); DREG (dst) = ashiftrt (DREG (dst), uimm5 (src)); } else if (opc == 6) { notethat ("dregs >>= uimm5"); DREG (dst) = lshiftrt (DREG (dst), uimm5 (src)); } else if (opc == 7) { notethat ("dregs <<= uimm5"); DREG (dst) = lshift (DREG (dst), uimm5 (src)); } PCREG += 2; return; } static void decode_COMP3op_0 (bu16 iw0) { /* COMP3op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src0 = ((iw0 >> 0) & 0x7); int src1 = ((iw0 >> 3) & 0x7); int opc = ((iw0 >> 9) & 0x7); int dst = ((iw0 >> 6) & 0x7); if (opc == 0) { notethat ("dregs = dregs + dregs"); DREG (dst) = add32 (DREG (src0), DREG (src1), 1); } else if (opc == 1) { notethat ("dregs = dregs - dregs"); DREG (dst) = sub32 (DREG (src0), DREG (src1), 1); } else if (opc == 2) { notethat ("dregs = dregs & dregs"); DREG (dst) = DREG (src0) & DREG (src1); setflags_logical (DREG (dst)); } else if (opc == 3) { notethat ("dregs = dregs | dregs"); DREG (dst) = DREG (src0) | DREG (src1); setflags_logical (DREG (dst)); } else if (opc == 4) { notethat ("dregs = dregs ^ dregs"); DREG (dst) = DREG (src0) ^ DREG (src1); setflags_logical (DREG (dst)); } else if (opc == 5) /* If src0 == src1 this is disassembled as a shift by 1, but this distinction doesn't matter for our purposes. */ PREG (dst) = PREG (src0) + PREG (src1); else if (opc == 6) PREG (dst) = PREG (src0) + (PREG (src1) << 1); else if (opc == 7) PREG (dst) = PREG (src0) + (PREG (src1) << 2); PCREG += 2; return; } static void decode_COMPI2opD_0 (bu16 iw0) { /* COMPI2opD +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int isrc = ((iw0 >> 3) & 0x7f); int dst = ((iw0 >> 0) & 0x7); int op = ((iw0 >> 10) & 0x1); if (op == 0) DREG (dst) = imm7 (isrc); else if (op == 1) DREG (dst) = add32 (DREG (dst), imm7 (isrc), 1); PCREG += 2; return; } static void decode_COMPI2opP_0 (bu16 iw0) { /* COMPI2opP +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src = ((iw0 >> 3) & 0x7f); int dst = ((iw0 >> 0) & 0x7); int op = ((iw0 >> 10) & 0x1); if (op == 0) PREG (dst) = imm7 (src); else if (op == 1) PREG (dst) += imm7 (src); PCREG += 2; return; } static void decode_LDSTpmod_0 (bu16 iw0) { /* LDSTpmod +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int aop = ((iw0 >> 9) & 0x3); int idx = ((iw0 >> 3) & 0x7); int ptr = ((iw0 >> 0) & 0x7); int reg = ((iw0 >> 6) & 0x7); int W = ((iw0 >> 11) & 0x1); bu32 addr, val; if (aop == 1 && W == 0 && idx == ptr) { notethat ("dregs_lo = W [ pregs ]"); addr = PREG (ptr); val = get_word (saved_state.memory, addr); STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | val); PCREG += 2; return; } else if (aop == 2 && W == 0 && idx == ptr) { notethat ("dregs_hi = W [ pregs ]"); addr = PREG (ptr); val = get_word (saved_state.memory, addr); STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (val << 16)); PCREG += 2; return; } else if (aop == 1 && W == 1 && idx == ptr) { notethat ("W [ pregs ] = dregs_lo"); addr = PREG (ptr); put_word (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else if (aop == 2 && W == 1 && idx == ptr) { notethat ("W [ pregs ] = dregs_hi"); addr = PREG (ptr); put_word (saved_state.memory, addr, DREG (reg) >> 16); PCREG += 2; return; } else if (aop == 0 && W == 0) { notethat ("dregs = [ pregs ++ pregs ]"); addr = PREG (ptr); val = get_long (saved_state.memory, addr); STORE (DREG (reg), val); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else if (aop == 1 && W == 0) { notethat ("dregs_lo = W [ pregs ++ pregs ]"); addr = PREG (ptr); val = get_word (saved_state.memory, addr); STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | val); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else if (aop == 2 && W == 0) { notethat ("dregs_hi = W [ pregs ++ pregs ]"); addr = PREG (ptr); val = get_word (saved_state.memory, addr); STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (val << 16)); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else if (aop == 3 && W == 0) { notethat ("dregs = W [ pregs ++ pregs ] (Z)"); addr = PREG (ptr); val = get_word (saved_state.memory, addr); STORE (DREG (reg), val); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else if (aop == 3 && W == 1) { notethat ("dregs = W [ pregs ++ pregs ] (X)"); addr = PREG (ptr); val = get_word (saved_state.memory, addr); STORE (DREG (reg), (bs32) (bs16) val); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else if (aop == 0 && W == 1) { notethat ("[ pregs ++ pregs ] = dregs"); addr = PREG (ptr); put_long (saved_state.memory, addr, DREG (reg)); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else if (aop == 1 && W == 1) { notethat (" W [ pregs ++ pregs ] = dregs_lo"); addr = PREG (ptr); put_word (saved_state.memory, addr, DREG (reg)); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else if (aop == 2 && W == 1) { notethat (" W[ pregs ++ pregs ] = dregs_hi"); addr = PREG (ptr); put_word (saved_state.memory, addr, DREG (reg) >> 16); STORE (PREG (ptr), addr + PREG (idx)); PCREG += 2; return; } else unhandled_instruction (); } static void decode_dagMODim_0 (bu16 iw0) { /* dagMODim +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int i = ((iw0 >> 0) & 0x3); int br = ((iw0 >> 7) & 0x1); int m = ((iw0 >> 2) & 0x3); int op = ((iw0 >> 4) & 0x1); if (op == 0 && br == 1) { notethat ("iregs += mregs ( BREV )"); OUTS (outf, iregs (i)); OUTS (outf, "+="); OUTS (outf, mregs (m)); OUTS (outf, "("); OUTS (outf, "BREV"); OUTS (outf, ")"); unhandled_instruction (); PCREG += 2; return; } else if (op == 0) { notethat ("iregs += mregs"); OUTS (outf, iregs (i)); OUTS (outf, "+="); OUTS (outf, mregs (m)); unhandled_instruction (); PCREG += 2; return; } else if (op == 1) { notethat ("iregs -= mregs"); OUTS (outf, iregs (i)); OUTS (outf, "-="); OUTS (outf, mregs (m)); unhandled_instruction (); PCREG += 2; return; } else unhandled_instruction (); } static void decode_dagMODik_0 (bu16 iw0) { /* dagMODik +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int i = ((iw0 >> 0) & 0x3); int op = ((iw0 >> 2) & 0x3); if (op == 0) { notethat ("iregs += 2"); OUTS (outf, iregs (i)); OUTS (outf, "+="); OUTS (outf, "2"); unhandled_instruction (); PCREG += 2; return; } else if (op == 1) { notethat ("iregs -= 2"); unhandled_instruction (); OUTS (outf, iregs (i)); OUTS (outf, "-="); OUTS (outf, "2"); PCREG += 2; return; } else if (op == 2) { notethat ("iregs += 4"); unhandled_instruction (); OUTS (outf, iregs (i)); OUTS (outf, "+="); OUTS (outf, "4"); PCREG += 2; return; } else if (op == 3) { notethat ("iregs -= 4"); unhandled_instruction (); OUTS (outf, iregs (i)); OUTS (outf, "-="); OUTS (outf, "4"); PCREG += 2; return; } else unhandled_instruction (); } static void decode_dspLDST_0 (bu16 iw0) { /* dspLDST +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int aop = ((iw0 >> 7) & 0x3); int i = ((iw0 >> 3) & 0x3); int m = ((iw0 >> 5) & 0x3); int reg = ((iw0 >> 0) & 0x7); int W = ((iw0 >> 9) & 0x1); bu32 addr; if (aop == 0 && W == 0 && m == 0) { notethat ("dregs = [ iregs ++ ]"); addr = IREG (i); STORE (IREG (i), addr + 4); STORE (DREG (reg), get_long (saved_state.memory, addr)); PCREG += 2; return; } else if (aop == 0 && W == 0 && m == 1) { notethat ("dregs_lo = W [ iregs ++ ]"); addr = IREG (i); STORE (IREG (i), addr + 2); STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | get_word (saved_state. memory, addr)); PCREG += 2; return; } else if (aop == 0 && W == 0 && m == 2) { notethat ("dregs_hi = W [ iregs ++ ]"); addr = IREG (i); STORE (IREG (i), addr + 2); STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (get_word (saved_state.memory, addr) << 16)); PCREG += 2; return; } else if (aop == 1 && W == 0 && m == 0) { notethat ("dregs = [ iregs -- ]"); addr = IREG (i); STORE (IREG (i), addr - 4); STORE (DREG (reg), get_long (saved_state.memory, addr)); PCREG += 2; return; } else if (aop == 1 && W == 0 && m == 1) { notethat ("dregs_lo = W [ iregs -- ]"); addr = IREG (i); STORE (IREG (i), addr - 2); STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | get_word (saved_state. memory, addr)); PCREG += 2; return; } else if (aop == 1 && W == 0 && m == 2) { notethat ("dregs_hi = W [ iregs -- ]"); addr = IREG (i); STORE (IREG (i), addr - 2); STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (get_word (saved_state.memory, addr) << 16)); PCREG += 2; return; } else if (aop == 2 && W == 0 && m == 0) { notethat ("dregs = [ iregs ]"); addr = IREG (i); STORE (DREG (reg), get_long (saved_state.memory, addr)); PCREG += 2; return; } else if (aop == 2 && W == 0 && m == 1) { notethat ("dregs_lo = W [ iregs ]"); addr = IREG (i); STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | get_word (saved_state. memory, addr)); PCREG += 2; return; } else if (aop == 2 && W == 0 && m == 2) { notethat ("dregs_hi = W [ iregs ]"); addr = IREG (i); STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (get_word (saved_state.memory, addr) << 16)); PCREG += 2; return; } else if (aop == 0 && W == 1 && m == 0) { notethat ("[ iregs ++ ] = dregs"); addr = IREG (i); STORE (IREG (i), addr + 4); put_long (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else if (aop == 0 && W == 1 && m == 1) { notethat ("W [ iregs ++ ] = dregs_lo"); addr = IREG (i); STORE (IREG (i), addr + 2); put_word (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else if (aop == 0 && W == 1 && m == 2) { notethat ("W [ iregs ++ ] = dregs_hi"); addr = IREG (i); STORE (IREG (i), addr + 2); put_word (saved_state.memory, addr, DREG (reg) >> 16); PCREG += 2; return; } else if (aop == 1 && W == 1 && m == 0) { notethat ("[ iregs -- ] = dregs"); addr = IREG (i); STORE (IREG (i), addr - 4); put_long (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else if (aop == 1 && W == 1 && m == 1) { notethat ("W [ iregs -- ] = dregs_lo"); addr = IREG (i); STORE (IREG (i), addr - 2); put_word (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else if (aop == 1 && W == 1 && m == 2) { notethat ("W [ iregs -- ] = dregs_hi"); addr = IREG (i); STORE (IREG (i), addr - 2); put_word (saved_state.memory, addr, DREG (reg) >> 16); PCREG += 2; return; } else if (aop == 2 && W == 1 && m == 0) { notethat ("[ iregs ] = dregs"); addr = IREG (i); put_long (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else if (aop == 2 && W == 1 && m == 1) { notethat (" W [ iregs ] = dregs_lo"); addr = IREG (i); put_word (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else if (aop == 2 && W == 1 && m == 2) { notethat (" W [ iregs ] = dregs_hi"); addr = IREG (i); put_word (saved_state.memory, addr, DREG (reg) >> 16); PCREG += 2; return; } else if (aop == 3 && W == 0) { notethat ("dregs = [ iregs ++ mregs ]"); addr = IREG (i); STORE (IREG (i), addr + MREG (m)); STORE (DREG (reg), get_long (saved_state.memory, addr)); PCREG += 2; return; } else if (aop == 3 && W == 1) { notethat ("[ iregs ++ mregs ] = dregs"); addr = IREG (i); STORE (IREG (i), addr + MREG (m)); put_long (saved_state.memory, addr, DREG (reg)); PCREG += 2; return; } else unhandled_instruction (); } static void decode_LDST_0 (bu16 iw0) { /* LDST +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int aop = ((iw0 >> 7) & 0x3); int Z = ((iw0 >> 6) & 0x1); int sz = ((iw0 >> 10) & 0x3); int reg = ((iw0 >> 0) & 0x7); int ptr = ((iw0 >> 3) & 0x7); int W = ((iw0 >> 9) & 0x1); // printf("\n\niw0=%x\n\n",iw0); if (aop == 3) unhandled_instruction (); if (W == 0) { if (aop != 2 && sz == 0 && Z == 1) if (ptr == reg) unhandled_instruction (); if (sz == 0 && Z == 0) { notethat ("dregs = [ pregs ]"); DREG (reg) = get_long (saved_state.memory, PREG (ptr)); } else if (sz == 0 && Z == 1) { notethat ("pregs = [ pregs ]"); PREG (reg) = get_long (saved_state.memory, PREG (ptr)); } else if (sz == 1 && Z == 0) { notethat ("dregs = W [ pregs ] (z)"); DREG (reg) = get_word (saved_state.memory, PREG (ptr)); } else if (sz == 1 && Z == 1) { notethat ("dregs = W [ pregs ] (X)"); DREG (reg) = (bs32) (bs16) get_word (saved_state.memory, PREG (ptr)); } else if (sz == 2 && Z == 0) { notethat ("dregs = B [ pregs ] (Z)"); DREG (reg) = get_byte (saved_state.memory, PREG (ptr)); //if(aop == 0) // PREG(ptr) = PREG(ptr) + 1; } else if (sz == 2 && Z == 1) { notethat ("dregs = B [ pregs ] (X)"); DREG (reg) = (bs32) (bs8) get_byte (saved_state.memory, PREG (ptr)); //if(aop == 0) // PREG(ptr) ++; } if (aop == 0) PREG (ptr) += sz == 0 ? 4 : sz == 1 ? 2 : 1; if (aop == 1) PREG (ptr) -= sz == 0 ? 4 : sz == 1 ? 2 : 1; } else { if (sz != 0 && Z == 1) unhandled_instruction (); if (sz == 0 && Z == 0) { notethat ("[ pregs ] = dregs"); put_long (saved_state.memory, PREG (ptr), DREG (reg)); } else if (sz == 0 && Z == 1) { notethat ("[ pregs ] = pregs"); put_long (saved_state.memory, PREG (ptr), PREG (reg)); } else if (sz == 1 && Z == 0) { notethat ("W [ pregs ] = dregs"); put_word (saved_state.memory, PREG (ptr), DREG (reg)); } else if (sz == 2 && Z == 0) { notethat ("B [ pregs ] = dregs"); put_byte (saved_state.memory, PREG (ptr), DREG (reg)); } if (aop == 0) PREG (ptr) += sz == 0 ? 4 : sz == 1 ? 2 : 1; if (aop == 1) PREG (ptr) -= sz == 0 ? 4 : sz == 1 ? 2 : 1; } PCREG += 2; return; } static void decode_LDSTiiFP_0 (bu16 iw0) { /* LDSTiiFP +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int reg = ((iw0 >> 0) & 0xf); int offset = ((iw0 >> 4) & 0x1f); int W = ((iw0 >> 9) & 0x1); bu32 ea = PREG (7) + negimm5s4 (offset); if (W == 0) DPREG (reg) = get_long (saved_state.memory, ea); else put_long (saved_state.memory, ea, DPREG (reg)); PCREG += 2; return; } static void decode_LDSTii_0 (bu16 iw0) { /* LDSTii +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int reg = ((iw0 >> 0) & 0x7); int ptr = ((iw0 >> 3) & 0x7); int offset = ((iw0 >> 6) & 0xf); int op = ((iw0 >> 10) & 0x3); int W = ((iw0 >> 12) & 0x1); bu32 ea = PREG (ptr) + (op == 0 || op == 3 ? uimm4s4 (offset) : uimm4s2 (offset)); if (W == 1 && op == 2) unhandled_instruction (); if (W == 0) { if (op == 0) { notethat ("dregs = [ pregs + uimm4s4 ]"); DREG (reg) = get_long (saved_state.memory, ea); } else if (op == 1) { notethat ("dregs = W [ pregs + uimm4s2 ] (Z)"); DREG (reg) = get_word (saved_state.memory, ea); } else if (op == 2) { notethat ("dregs = W [ pregs + uimm4s2 ] (X)"); DREG (reg) = (bs32) (bs16) get_word (saved_state.memory, ea); } else if (op == 3) { notethat ("pregs = [ pregs + uimm4s4 ]"); PREG (reg) = get_long (saved_state.memory, ea); } } else { if (op == 0) { notethat ("[ pregs + uimm4s4 ] = dregs"); put_long (saved_state.memory, ea, DREG (reg)); } else if (op == 1) { notethat ("W [ pregs + uimm4s2 ] = dregs"); put_word (saved_state.memory, ea, DREG (reg)); } else if (op == 3) { notethat ("[ pregs + uimm4s4 ] = pregs"); put_long (saved_state.memory, ea, PREG (reg)); } } PCREG += 2; } static void decode_LoopSetup_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* LoopSetup +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| |.reg...........| - | - |.eoffset...............................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int rop = ((iw0 >> 5) & 0x3); int soffset = ((iw0 >> 0) & 0xf); int c = ((iw0 >> 4) & 0x1); int eoffset = ((iw1 >> 0) & 0x3ff); int reg = ((iw1 >> 12) & 0xf); if (rop == 0) { notethat ("LSETUP ( pcrel4 , lppcrel10 ) counters"); saved_state.lt[c] = PCREG + pcrel4 (soffset); saved_state.lb[c] = PCREG + lppcrel10 (eoffset); PCREG += 4; return; } else if (rop == 1) { notethat ("LSETUP ( pcrel4 , lppcrel10 ) counters = pregs"); saved_state.lt[c] = PCREG + pcrel4 (soffset); saved_state.lb[c] = PCREG + lppcrel10 (eoffset); saved_state.lc[c] = PREG (reg); PCREG += 4; return; } else if (rop == 3) { notethat ("LSETUP ( pcrel4 , lppcrel10 ) counters = pregs >> 1"); saved_state.lt[c] = PCREG + pcrel4 (soffset); saved_state.lb[c] = PCREG + lppcrel10 (eoffset); saved_state.lc[c] = PREG (reg) >> 1; PCREG += 4; return; } else unhandled_instruction (); } static void decode_LDIMMhalf_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* LDIMMhalf +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| |.hword.........................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int H = ((iw0 >> 6) & 0x1); int grp = ((iw0 >> 3) & 0x3); int Z = ((iw0 >> 7) & 0x1); int S = ((iw0 >> 5) & 0x1); int hword = ((iw1 >> 0) & 0xffff); int reg = ((iw0 >> 0) & 0x7); if (H == 0 && S == 1 && Z == 0) { int *pval = get_allreg (grp, reg); notethat ("regs = imm16 (x)"); *pval = imm16 (hword); } else if (H == 0 && S == 0 && Z == 1) { int *pval = get_allreg (grp, reg); notethat ("regs = luimm16 (Z)"); *pval = luimm16 (hword); } else if (H == 0 && S == 0 && Z == 0) { int *pval = get_allreg (grp, reg); notethat ("regs_lo = luimm16"); *pval &= 0xFFFF0000; *pval |= luimm16 (hword); } else if (H == 1 && S == 0 && Z == 0) { int *pval = get_allreg (grp, reg); notethat ("regs_hi = huimm16"); *pval &= 0xFFFF; *pval |= luimm16 (hword) << 16; } else unhandled_instruction (); PCREG += 4; return; } static void decode_CALLa_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* CALLa +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| |.lsw...........................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int S = ((iw0 >> 8) & 0x1); int lsw = ((iw1 >> 0) & 0xffff); int msw = ((iw0 >> 0) & 0xff); if (S == 1) { notethat ("CALL pcrel24"); saved_state.rets = PCREG + 4; } else notethat ("JUMP.L pcrel24"); /* fixme, workaround for bf537 instruction: call _real_start; */ if((msw == 0x0) && (lsw == 0x1f) && (PCREG == 0x113e)) PCREG += 4; else PCREG += pcrel24 (((msw) << 16) | (lsw)); // printf("\ncall or jump is 0x%x\n",PCREG); } static void decode_LDSTidxI_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* LDSTidxI +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| |.offset........................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int Z = ((iw0 >> 8) & 0x1); int sz = ((iw0 >> 6) & 0x3); int reg = ((iw0 >> 0) & 0x7); int ptr = ((iw0 >> 3) & 0x7); int offset = ((iw1 >> 0) & 0xffff); int W = ((iw0 >> 9) & 0x1); if (sz == 3) unhandled_instruction (); if (W == 0) { if (sz == 0 && Z == 0) { notethat ("dregs = [ pregs + imm16s4 ]"); DREG (reg) = get_long (saved_state.memory, PREG (ptr) + imm16s4 (offset)); } else if (sz == 0 && Z == 1) { notethat ("pregs = [ pregs + imm16s4 ]"); PREG (reg) = get_long (saved_state.memory, PREG (ptr) + imm16s4 (offset)); } else if (sz == 1 && Z == 0) { notethat ("dregs = W [ pregs + imm16s2 ] (Z)"); DREG (reg) = get_word (saved_state.memory, PREG (ptr) + imm16s2 (offset)); } else if (sz == 1 && Z == 1) { notethat ("dregs = W [ pregs + imm16s2 ] (X)"); DREG (reg) = (bs32) (bs16) get_word (saved_state.memory, PREG (ptr) + imm16s2 (offset)); } else if (sz == 2 && Z == 0) { notethat ("dregs = B [ pregs + imm16 ] (Z)"); DREG (reg) = get_byte (saved_state.memory, PREG (ptr) + imm16 (offset)); } else if (sz == 2 && Z == 1) { notethat ("dregs = B [ pregs + imm16 ] (X)"); DREG (reg) = (bs32) (bs8) get_byte (saved_state.memory, PREG (ptr) + imm16 (offset)); } } else { if (sz != 0 && Z != 0) unhandled_instruction (); if (sz == 0 && Z == 0) { notethat ("[ pregs + imm16s4 ] = dregs"); put_long (saved_state.memory, PREG (ptr) + imm16s4 (offset), DREG (reg)); } else if (sz == 0 && Z == 1) { notethat ("[ pregs + imm16s4 ] = pregs"); put_long (saved_state.memory, PREG (ptr) + imm16s4 (offset), PREG (reg)); } else if (sz == 1 && Z == 0) { notethat ("W [ pregs + imm16s2 ] = dregs"); put_word (saved_state.memory, PREG (ptr) + imm16s2 (offset), DREG (reg)); } else if (sz == 2 && Z == 0) { notethat ("B [ pregs + imm16 ] = dregs"); put_byte (saved_state.memory, PREG (ptr) + imm16 (offset), DREG (reg)); } } PCREG += 4; return; } static void decode_linkage_0 (bu16 iw0, bu16 iw1) { /* linkage +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| |.framesize.....................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int R = ((iw0 >> 0) & 0x1); int framesize = ((iw1 >> 0) & 0xffff); if (R == 0) { bu32 sp = PREG (6); notethat ("LINK uimm16s4"); sp -= 4; put_long (saved_state.memory, sp, saved_state.rets); sp -= 4; put_long (saved_state.memory, sp, PREG (7)); PREG (7) = sp; sp -= uimm16s4 (framesize); PREG (6) = sp; } else { /* Restore SP from FP. */ bu32 sp = PREG (7); notethat ("UNLINK"); PREG (7) = get_long (saved_state.memory, sp); sp += 4; saved_state.rets = get_long (saved_state.memory, sp); sp += 4; PREG (6) = sp; } PCREG += 4; return; } static void decode_dsp32mac_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* dsp32mac +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int op1 = ((iw0 >> 0) & 0x3); int w1 = ((iw0 >> 2) & 0x1); int P = ((iw0 >> 3) & 0x1); int MM = ((iw0 >> 4) & 0x1); int mmod = ((iw0 >> 5) & 0xf); int M = ((iw0 >> 11) & 0x1); int w0 = ((iw1 >> 13) & 0x1); int src1 = ((iw1 >> 0) & 0x7); int src0 = ((iw1 >> 3) & 0x7); int dst = ((iw1 >> 6) & 0x7); int h10 = ((iw1 >> 9) & 0x1); int h00 = ((iw1 >> 10) & 0x1); int op0 = ((iw1 >> 11) & 0x3); int h11 = ((iw1 >> 14) & 0x1); int h01 = ((iw1 >> 15) & 0x1); bu32 res0, res1; if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) unhandled_instruction (); if (op1 == 3 && MM) unhandled_instruction (); if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) unhandled_instruction (); if (w1 == 1 || op1 != 3) res1 = decode_macfunc (1, op1, h01, h11, src0, src1, mmod, MM, P); if (w0 == 1 || op0 != 3) res0 = decode_macfunc (0, op0, h00, h10, src0, src1, mmod, 0, P); if (w0) { if (P) DREG (dst) = res0; else { if (res0 & 0xffff0000) abort (); DREG (dst) = (DREG (dst) & 0xFFFF0000) | res0; } } if (w1) { if (P) DREG (dst + 1) = res1; else { if (res1 & 0xffff0000) abort (); DREG (dst) = (DREG (dst) & 0xFFFF) | (res1 << 16); } } PCREG += 4; } static void decode_dsp32mult_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* dsp32mult +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int op1 = ((iw0 >> 0) & 0x3); int w1 = ((iw0 >> 2) & 0x1); int P = ((iw0 >> 3) & 0x1); int MM = ((iw0 >> 4) & 0x1); int mmod = ((iw0 >> 5) & 0xf); int M = ((iw0 >> 11) & 0x1); int src1 = ((iw1 >> 0) & 0x7); int src0 = ((iw1 >> 3) & 0x7); int dst = ((iw1 >> 6) & 0x7); int h10 = ((iw1 >> 9) & 0x1); int h00 = ((iw1 >> 10) & 0x1); int op0 = ((iw1 >> 11) & 0x3); int w0 = ((iw1 >> 13) & 0x1); int h01 = ((iw1 >> 15) & 0x1); int h11 = ((iw1 >> 14) & 0x1); bu32 res0, res1; if (w1 == 0 && w0 == 0) unhandled_instruction (); if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) unhandled_instruction (); if (w1) { bu64 r = decode_multfunc (h01, h11, src0, src1, mmod, MM); res1 = extract_mult (r, mmod, P); } if (w0) { bu64 r = decode_multfunc (h00, h10, src0, src1, mmod, 0); res0 = extract_mult (r, mmod, P); } if (w0) { if (P) DREG (dst) = res0; else { if (res0 & 0xFFFF0000) abort (); DREG (dst) = (DREG (dst) & 0xFFFF0000) | res0; } } if (w1) { if (P) DREG (dst + 1) = res1; else { if (res1 & 0xFFFF0000) abort (); DREG (dst) = (DREG (dst) & 0xFFFF) | (res1 << 16); } } PCREG += 4; } static void decode_dsp32alu_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* dsp32alu +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int aop = ((iw1 >> 14) & 0x3); int s = ((iw1 >> 13) & 0x1); int HL = ((iw0 >> 5) & 0x1); int x = ((iw1 >> 12) & 0x1); int src0 = ((iw1 >> 3) & 0x7); int src1 = ((iw1 >> 0) & 0x7); int dst0 = ((iw1 >> 9) & 0x7); int aopcde = ((iw0 >> 0) & 0x1f); int dst1 = ((iw1 >> 6) & 0x7); int M = ((iw0 >> 11) & 0x1); /* if(M) printf("KSDBG:iw1=0x%x,iw0=0x%x,pc=0x%x,insn@pc=0x%x\n",iw1,iw0,PCREG,get_long(saved_state.memory, PCREG)); */ if (aop == 0 && aopcde == 9 && HL == 0 && s == 0) { notethat ("A0.L = dregs_lo"); unhandled_instruction (); OUTS (outf, "A0.L"); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0) { notethat ("A1.H = dregs_hi"); unhandled_instruction (); OUTS (outf, "A1.H"); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); PCREG += 4; return; } else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0) { notethat ("A1.L = dregs_lo"); unhandled_instruction (); OUTS (outf, "A1.L"); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0) { notethat ("A0.H = dregs_hi"); unhandled_instruction (); OUTS (outf, "A0.H"); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); PCREG += 4; return; } else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5) { notethat ("dregs_hi = dregs - dregs (RND20)"); unhandled_instruction (); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND20"); OUTS (outf, ")"); PCREG += 4; return; } else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5) { notethat ("dregs_hi = dregs + dregs (RND20)"); unhandled_instruction (); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND20"); OUTS (outf, ")"); PCREG += 4; return; } else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5) { notethat ("dregs_lo = dregs - dregs (RND12)"); unhandled_instruction (); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND12"); OUTS (outf, ")"); PCREG += 4; return; } else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5) { notethat ("dregs_lo = dregs + dregs (RND12)"); unhandled_instruction (); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND12"); OUTS (outf, ")"); PCREG += 4; return; } else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5) { notethat ("dregs_lo = dregs - dregs (RND20)"); unhandled_instruction (); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND20"); OUTS (outf, ")"); PCREG += 4; return; } else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5) { notethat ("dregs_hi = dregs + dregs (RND12)"); unhandled_instruction (); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND12"); OUTS (outf, ")"); PCREG += 4; return; } else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5) { notethat ("dregs_lo = dregs + dregs (RND20)"); OUTS (outf, dregs_lo (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND20"); OUTS (outf, ")"); PCREG += 4; return; } else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5) { notethat ("dregs_hi = dregs - dregs (RND12)"); unhandled_instruction (); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-"); OUTS (outf, dregs (src1)); OUTS (outf, "("); OUTS (outf, "RND12"); OUTS (outf, ")"); PCREG += 4; return; } else if (HL == 1 && aop == 0 && aopcde == 2) { notethat ("dregs_hi = dregs_lo + dregs_lo amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); OUTS (outf, "+"); OUTS (outf, dregs_lo (src1)); OUTS (outf, " "); amod1 (s, x, pc); unhandled_instruction(); PCREG += 4; return; } else if (HL == 1 && aop == 1 && aopcde == 2) { notethat ("dregs_hi = dregs_lo + dregs_hi amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); OUTS (outf, "+"); OUTS (outf, dregs_hi (src1)); OUTS (outf, " "); // printf("KSDBG:hlh\n"); // printf("%x,%x,%x,%x,",( DREG(src0)&0xffff ),(DREG(src1)>>16) ,( ( ( DREG(src0)&0xffff ) + (DREG(src1)>>16) )<<16),(DREG(dst0)&0xffff)); if(s == 0 && x == 0) DREG (dst0) = (((DREG (src0) & 0xffff) + (DREG (src1) >> 16)) << 16) + (DREG (dst0) & 0xffff); else unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 1 && aop == 2 && aopcde == 2) { notethat ("dregs_hi = dregs_hi + dregs_lo amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "+"); OUTS (outf, dregs_lo (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 1 && aop == 3 && aopcde == 2) { notethat ("dregs_hi = dregs_hi + dregs_hi amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "+"); OUTS (outf, dregs_hi (src1)); OUTS (outf, " "); amod1 (s, x, pc); unhandled_instruction (); PCREG += 4; return; } else if (HL == 0 && aop == 0 && aopcde == 3) { notethat ("dregs_lo = dregs_lo - dregs_lo amod1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); OUTS (outf, "-"); OUTS (outf, dregs_lo (src1)); unhandled_instruction (); OUTS (outf, " "); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aop == 1 && aopcde == 3) { notethat ("dregs_lo = dregs_lo - dregs_hi amod1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); OUTS (outf, "-"); OUTS (outf, dregs_hi (src1)); unhandled_instruction (); OUTS (outf, " "); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aop == 3 && aopcde == 2) { notethat ("dregs_lo = dregs_hi + dregs_hi amod1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "+"); OUTS (outf, dregs_hi (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 1 && aop == 0 && aopcde == 3) { notethat ("dregs_hi = dregs_lo - dregs_lo amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); OUTS (outf, "-"); OUTS (outf, dregs_lo (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 1 && aop == 1 && aopcde == 3) { notethat ("dregs_hi = dregs_lo - dregs_hi amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); OUTS (outf, "-"); OUTS (outf, dregs_hi (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 1 && aop == 2 && aopcde == 3) { notethat ("dregs_hi = dregs_hi - dregs_lo amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "-"); OUTS (outf, dregs_lo (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 1 && aop == 3 && aopcde == 3) { notethat ("dregs_hi = dregs_hi - dregs_hi amod1"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "-"); OUTS (outf, dregs_hi (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aop == 2 && aopcde == 2) { notethat ("dregs_lo = dregs_hi + dregs_lo amod1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "+"); OUTS (outf, dregs_lo (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aop == 1 && aopcde == 2) { notethat ("dregs_lo = dregs_lo + dregs_hi amod1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); OUTS (outf, "+"); OUTS (outf, dregs_hi (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aop == 2 && aopcde == 3) { notethat ("dregs_lo = dregs_hi - dregs_lo amod1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "-"); OUTS (outf, dregs_lo (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aop == 3 && aopcde == 3) { notethat ("dregs_lo = dregs_hi - dregs_hi amod1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src0)); OUTS (outf, "-"); OUTS (outf, dregs_hi (src1)); OUTS (outf, " "); unhandled_instruction (); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aop == 0 && aopcde == 2) { //notethat ("dregs_lo = dregs_lo + dregs_lo amod1"); //OUTS (outf, dregs_lo (dst0)); //OUTS (outf, "="); //OUTS (outf, dregs_lo (src0)); //OUTS (outf, "+"); //OUTS (outf, dregs_lo (src1)); //OUTS (outf, " "); //printf("DEBUG55,s0=%x,s1=%x,d0=%x,or1=%x,sum2=%x\n",DREG(src0)&0xffff,DREG(src1)&0xffff,DREG(dst0)&0xffff0000,(DREG(src0)&0xffff) + (DREG(src1)&0xffff), DREG(src0)&0xffff + DREG(src1)&0xffff + DREG(dst0)&0xffff0000); DREG (dst0) = (DREG (src0) & 0xffff) + (DREG (src1) & 0xffff) + (DREG (dst0) & 0xffff0000); //amod1 (s, x, pc); PCREG += 4; return; } else if (aop == 0 && aopcde == 9 && s == 1) { notethat ("A0 = dregs"); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, dregs (src0)); unhandled_instruction (); PCREG += 4; return; } else if (aop == 3 && aopcde == 11 && s == 0) { notethat ("A0 -= A1"); OUTS (outf, "A0"); OUTS (outf, "-="); OUTS (outf, "A1"); unhandled_instruction (); PCREG += 4; return; } else if (aop == 3 && aopcde == 11 && s == 1) { notethat ("A0 -= A1 (W32)"); OUTS (outf, "A0"); OUTS (outf, "-="); OUTS (outf, "A1"); OUTS (outf, "(W32)"); unhandled_instruction (); PCREG += 4; return; } else if (aop == 3 && aopcde == 22 && HL == 1) { notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (TH , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2M"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "TH"); unhandled_instruction (); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 3 && aopcde == 22 && HL == 0) { notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (TL , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2M"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, "TL"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 2 && aopcde == 22 && HL == 1) { notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (RNDH , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2M"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); unhandled_instruction (); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "RNDH"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 2 && aopcde == 22 && HL == 0) { notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (RNDL , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2M"); OUTS (outf, "("); OUTS (outf, dregs (src0)); unhandled_instruction (); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "RNDL"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 1 && aopcde == 22 && HL == 1) { notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (TH , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, "TH"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 1 && aopcde == 22 && HL == 0) { notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (TL , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); unhandled_instruction (); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "TL"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 0 && aopcde == 22 && HL == 1) { notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (RNDH , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); unhandled_instruction (); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "RNDH"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 0 && aopcde == 22 && HL == 0) { notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (RNDL , aligndir)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP2P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "RNDL"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 0 && s == 0 && aopcde == 8) { notethat ("A0 = 0"); saved_state.a0 = 0; PCREG += 4; return; } else if (aop == 0 && s == 1 && aopcde == 8) { notethat ("A0 = A0 (S)"); unhandled_instruction (); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "(S)"); PCREG += 4; return; } else if (aop == 1 && s == 0 && aopcde == 8) { notethat ("A1 = 0"); saved_state.a1 = 0; PCREG += 4; return; } else if (aop == 1 && s == 1 && aopcde == 8) { notethat ("A1 = A1 (S)"); OUTS (outf, "A1"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "A1"); OUTS (outf, "(S)"); PCREG += 4; return; } else if (aop == 2 && s == 0 && aopcde == 8) { notethat ("A1 = A0 = 0"); saved_state.a1 = saved_state.a0 = 0; PCREG += 4; return; } else if (aop == 2 && s == 1 && aopcde == 8) { notethat ("A1 = A1 (S) , A0 = A0 (S)"); OUTS (outf, "A1"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A1"); OUTS (outf, "(S)"); OUTS (outf, ","); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "(S)"); PCREG += 4; return; } else if (aop == 3 && s == 0 && aopcde == 8) { notethat ("A0 = A1"); OUTS (outf, "A0"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A1"); PCREG += 4; return; } else if (aop == 3 && s == 1 && aopcde == 8) { notethat ("A1 = A0"); OUTS (outf, "A1"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A0"); PCREG += 4; return; } else if (aop == 1 && aopcde == 9 && s == 0) { notethat ("A0.x = dregs_lo"); OUTS (outf, "A0.x"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (aop == 1 && HL == 0 && aopcde == 11) { notethat ("dregs_lo = ( A0 += A1 )"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, "A0"); OUTS (outf, "+="); OUTS (outf, "A1"); OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 3 && HL == 0 && aopcde == 16) { notethat ("A1 = ABS A1, A0 = ABS A0"); OUTS (outf, "A1"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "ABS"); OUTS (outf, "A0"); OUTS (outf, ","); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "ABS"); OUTS (outf, "A0"); PCREG += 4; return; } else if (aop == 0 && aopcde == 23 && HL == 1) { notethat ("dregs = BYTEOP3P ( dregs_pair , dregs_pair ) (HI , R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "BYTEOP3P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "HI"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 3 && aopcde == 9 && s == 0) { notethat ("A1.x = dregs_lo"); OUTS (outf, "A1.x"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (aop == 1 && HL == 1 && aopcde == 16) { notethat ("A1 = ABS A1"); OUTS (outf, "A1"); OUTS (outf, "="); OUTS (outf, "ABS"); unhandled_instruction (); OUTS (outf, "A1"); PCREG += 4; return; } else if (aop == 0 && HL == 1 && aopcde == 16) { notethat ("A1 = ABS A0"); OUTS (outf, "A1"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "ABS"); OUTS (outf, "A0"); PCREG += 4; return; } else if (aop == 2 && aopcde == 9 && s == 1) { notethat ("A1 = dregs"); OUTS (outf, "A1"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, dregs (src0)); PCREG += 4; return; } else if (HL == 0 && aop == 3 && aopcde == 12) { notethat ("dregs_lo = dregs (RND)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, dregs (src0)); OUTS (outf, "(RND)"); PCREG += 4; return; } else if (aop == 1 && HL == 0 && aopcde == 16) { notethat ("A0 = ABS A1"); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "ABS"); unhandled_instruction (); OUTS (outf, "A1"); PCREG += 4; return; } else if (aop == 0 && HL == 0 && aopcde == 16) { notethat ("A0 = ABS A0"); OUTS (outf, "A0"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "ABS"); OUTS (outf, "A0"); PCREG += 4; return; } else if (aop == 3 && HL == 0 && aopcde == 15) { notethat ("dregs = - dregs (V)"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "-"); OUTS (outf, dregs (src0)); OUTS (outf, "(V)"); PCREG += 4; return; } else if (aop == 1 && HL == 1 && aopcde == 11) { notethat ("dregs_hi = ( A0 += A1 )"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, "("); OUTS (outf, "A0"); unhandled_instruction (); OUTS (outf, "+="); OUTS (outf, "A1"); OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 2 && aopcde == 11 && s == 0) { notethat ("A0 += A1"); OUTS (outf, "A0"); OUTS (outf, "+="); unhandled_instruction (); OUTS (outf, "A1"); PCREG += 4; return; } else if (aop == 2 && aopcde == 11 && s == 1) { notethat ("A0 += A1 (W32)"); OUTS (outf, "A0"); OUTS (outf, "+="); OUTS (outf, "A1"); unhandled_instruction (); OUTS (outf, "(W32)"); PCREG += 4; return; } else if (aop == 3 && HL == 0 && aopcde == 14) { notethat ("A1 = - A1 , A0 = - A0"); OUTS (outf, "A1"); OUTS (outf, "="); OUTS (outf, "-"); OUTS (outf, "A1"); OUTS (outf, ","); unhandled_instruction (); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "-"); OUTS (outf, "A0"); PCREG += 4; return; } else if (HL == 1 && aop == 3 && aopcde == 12) { notethat ("dregs_hi = dregs (RND)"); OUTS (outf, dregs_hi (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "(RND)"); PCREG += 4; return; } else if (aop == 0 && aopcde == 23 && HL == 0) { notethat ("dregs = BYTEOP3P ( dregs_pair , dregs_pair ) (LO , R)"); unhandled_instruction (); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP3P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "LO"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 0 && HL == 0 && aopcde == 14) { notethat ("A0 = - A0"); OUTS (outf, "A0"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "-"); OUTS (outf, "A0"); PCREG += 4; return; } else if (aop == 1 && HL == 0 && aopcde == 14) { notethat ("A0 = - A1"); unhandled_instruction (); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "-"); OUTS (outf, "A1"); PCREG += 4; return; } else if (aop == 0 && HL == 1 && aopcde == 14) { notethat ("A1 = - A0"); OUTS (outf, "A1"); OUTS (outf, "="); OUTS (outf, "-"); OUTS (outf, "A0"); unhandled_instruction (); PCREG += 4; return; } else if (aop == 1 && HL == 1 && aopcde == 14) { notethat ("A1 = - A1"); OUTS (outf, "A1"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "-"); OUTS (outf, "A1"); PCREG += 4; return; } else if (aop == 0 && aopcde == 12) { notethat ("dregs_hi=dregs_lo=SIGN(dregs_hi)*dregs_hi + SIGN(dregs_lo)*dregs_lo)"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "SIGN"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs_hi (src0)); OUTS (outf, ")"); OUTS (outf, "*"); OUTS (outf, dregs_hi (src1)); OUTS (outf, "+"); OUTS (outf, "SIGN"); OUTS (outf, "("); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); OUTS (outf, "*"); OUTS (outf, dregs_lo (src1)); OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 2 && aopcde == 0) { notethat ("dregs = dregs -|+ dregs amod0"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-|+"); OUTS (outf, dregs (src1)); OUTS (outf, " "); unhandled_instruction(); amod0 (s, x, pc); PCREG += 4; return; } else if (aop == 1 && aopcde == 12) { notethat ("dregs = A1.L + A1.H , dregs = A0.L + A0.H"); OUTS (outf, dregs (dst1)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A1.L"); OUTS (outf, "+"); OUTS (outf, "A1.H"); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "A0.L"); OUTS (outf, "+"); OUTS (outf, "A0.H"); unhandled_instruction(); PCREG += 4; return; } else if (aop == 2 && aopcde == 4) { notethat ("dregs = dregs + dregs , dregs = dregs - dregs amod1"); OUTS (outf, dregs (dst1)); OUTS (outf, "="); OUTS (outf, dregs (src0)); unhandled_instruction (); OUTS (outf, "+"); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-"); OUTS (outf, dregs (src1)); OUTS (outf, " "); amod1 (s, x, pc); PCREG += 4; return; } else if (HL == 0 && aopcde == 1) { notethat ("dregs = dregs +|+ dregs , dregs = dregs -|- dregs (amod0, amod2)"); OUTS (outf, dregs (dst1)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+|+"); OUTS (outf, dregs (src1)); OUTS (outf, ","); unhandled_instruction (); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-|-"); OUTS (outf, dregs (src1)); if (s == 1 && x == 0 && aop == 2) OUTS (outf, "(S, ASR)"); else if (s == 1 && x == 0 && aop == 3) OUTS (outf, "(S, ASL)"); else if (s == 0 && x == 0 && aop == 2) OUTS (outf, "(ASR)"); else if (s == 0 && x == 0 && aop == 3) OUTS (outf, "(ASL)"); else OUTS (outf, ""); PCREG += 4; return; } else if (aop == 0 && aopcde == 11) { notethat ("dregs = ( A0 += A1 )"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "("); OUTS (outf, "A0"); OUTS (outf, "+="); OUTS (outf, "A1"); OUTS (outf, ")"); unhandled_instruction(); PCREG += 4; return; } else if (aop == 0 && aopcde == 10) { notethat ("dregs_lo = A0.x"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "A0.x"); PCREG += 4; return; } else if (aop == 1 && aopcde == 10) { notethat ("dregs_lo = A1.x"); OUTS (outf, dregs_lo (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A1.x"); PCREG += 4; return; } else if (aop == 1 && aopcde == 0) { notethat ("dregs = dregs +|- dregs amod0"); unhandled_instruction (); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+|-"); OUTS (outf, dregs (src1)); OUTS (outf, " "); amod0 (s, x, pc); PCREG += 4; return; } else if (aop == 3 && aopcde == 0) { notethat ("dregs = dregs -|- dregs amod0"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-|-"); OUTS (outf, dregs (src1)); unhandled_instruction (); OUTS (outf, " "); amod0 (s, x, pc); PCREG += 4; return; } else if (aop == 1 && aopcde == 4) { notethat ("dregs = dregs - dregs amod1"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-"); //unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, " "); amod1 (s, x, pc); DREG (dst0) = DREG (src0) - DREG (src1); PCREG += 4; return; } else if (aop == 0 && aopcde == 17) { notethat ("dregs = A1 + A0, dregs = A1 - A0 amod1"); OUTS (outf, dregs (dst1)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A1"); OUTS (outf, "+"); OUTS (outf, "A0"); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "A1"); OUTS (outf, "-"); OUTS (outf, "A0"); OUTS (outf, " "); amod1 (s, x, pc); PCREG += 4; return; } else if (aop == 1 && aopcde == 17) { notethat ("dregs = A0 + A1, dregs = A0 - A1 amod1"); OUTS (outf, dregs (dst1)); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "+"); OUTS (outf, "A1"); unhandled_instruction (); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "-"); OUTS (outf, "A1"); OUTS (outf, " "); amod1 (s, x, pc); PCREG += 4; return; } else if (aop == 0 && aopcde == 18) { notethat ("SAA ( dregs_pair , dregs_pair ) aligndir"); OUTS (outf, "SAA"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); unhandled_instruction (); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ") "); aligndir (s, pc); PCREG += 4; return; } else if (aop == 3 && aopcde == 18) { unhandled_instruction (); notethat ("DISALGNEXCPT"); OUTS (outf, "DISALGNEXCPT"); PCREG += 4; return; } else if (aop == 0 && aopcde == 20) { notethat ("dregs = BYTEOP1P ( dregs_pair , dregs_pair ) aligndir"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "BYTEOP1P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ") "); aligndir (s, pc); PCREG += 4; return; } else if (aop == 1 && aopcde == 20) { notethat ("dregs = BYTEOP1P ( dregs_pair , dregs_pair ) (T, R)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "BYTEOP1P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); unhandled_instruction (); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "T"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 0 && aopcde == 21) { notethat ("( dregs , dregs ) = BYTEOP16P ( dregs_pair , dregs_pair ) aligndir"); OUTS (outf, "("); OUTS (outf, dregs (dst1)); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, ")"); OUTS (outf, "="); OUTS (outf, "BYTEOP16P"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ") "); aligndir (s, pc); PCREG += 4; return; } else if (aop == 1 && aopcde == 21) { notethat ("( dregs , dregs ) = BYTEOP16M ( dregs_pair , dregs_pair ) aligndir"); OUTS (outf, "("); OUTS (outf, dregs (dst1)); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, ")"); OUTS (outf, "="); OUTS (outf, "BYTEOP16M"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1 - 1)); OUTS (outf, ") "); aligndir (s, pc); PCREG += 4; return; } else if (aop == 2 && aopcde == 7) { bu32 val = DREG (src0); notethat ("dregs = ABS dregs"); if (val >> 31) val = -val; /* @@@ The manual is talking about saturation. Check what the hardware does when it gets 0x80000000. */ setflags_logical (val); DREG (dst0) = val; PCREG += 4; return; } else if (aop == 1 && aopcde == 7) { notethat ("dregs = MIN ( dregs , dregs )"); DREG (dst0) = min32 (DREG (src0), DREG (src1)); PCREG += 4; return; } else if (aop == 0 && aopcde == 7) { notethat ("dregs = MAX ( dregs , dregs )"); DREG (dst0) = max32 (DREG (src0), DREG (src1)); PCREG += 4; return; } else if (aop == 2 && aopcde == 6) { notethat ("dregs = ABS dregs (V)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "ABS"); OUTS (outf, dregs (src0)); OUTS (outf, "(V)"); PCREG += 4; return; } else if (aop == 1 && aopcde == 6) { notethat ("dregs = MIN ( dregs , dregs ) (V)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "MIN"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ")(V)"); PCREG += 4; return; } else if (aop == 0 && aopcde == 6) { notethat ("dregs = MAX ( dregs , dregs ) (V)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "MAX"); OUTS (outf, "("); OUTS (outf, dregs (src0)); unhandled_instruction (); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ")(V)"); PCREG += 4; return; } else if (HL == 1 && aopcde == 1) { notethat ("dregs = dregs +|- dregs, dregs = dregs -|+ dregs (amod0, amod2)"); OUTS (outf, dregs (dst1)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+|-"); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "-|+"); OUTS (outf, dregs (src1)); if (s == 1 && x == 0 && aop == 2) OUTS (outf, "(S, ASR)"); else if (s == 1 && x == 0 && aop == 3) OUTS (outf, "(S, ASL)"); else if (s == 0 && x == 0 && aop == 2) OUTS (outf, "(ASR)"); else if (s == 0 && x == 0 && aop == 3) OUTS (outf, "(ASL)"); else OUTS (outf, ""); PCREG += 4; return; } else if (aop == 0 && aopcde == 4) { notethat ("dregs = dregs + dregs amod1"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+"); OUTS (outf, dregs (src1)); OUTS (outf, " "); unhandled_instruction(); amod1 (s, x, pc); PCREG += 4; return; } else if (aop == 0 && aopcde == 0) { notethat ("dregs = dregs +|+ dregs amod0"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src0)); OUTS (outf, "+|+"); OUTS (outf, dregs (src1)); OUTS (outf, " "); //unhandled_instruction(); DREG(dst0) = (DREG(src0)&0xffff0000 + DREG(src1)&0xffff0000)&0xffff0000 + (DREG(src0)&0xffff + DREG(src1)&0xffff)&0xffff; amod0 (s, x, pc); PCREG += 4; return; } else if (aop == 0 && aopcde == 24) { notethat ("dregs = BYTEPACK ( dregs , dregs )"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "BYTEPACK"); OUTS (outf, "("); OUTS (outf, dregs (src0)); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ")"); PCREG += 4; return; } else if (aop == 1 && aopcde == 24) { notethat ("( dregs , dregs ) = BYTEUNPACK dregs_pair aligndir"); OUTS (outf, "("); OUTS (outf, dregs (dst1)); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, ")"); OUTS (outf, "="); OUTS (outf, "BYTEUNPACK"); OUTS (outf, dregs (src0)); OUTS (outf, ":"); OUTS (outf, imm5 (src0 - 1)); OUTS (outf, " "); aligndir (s, pc); PCREG += 4; return; } else if (aopcde == 13) { notethat ("( dregs , dregs ) = SEARCH dregs (searchmod)"); OUTS (outf, "("); OUTS (outf, dregs (dst1)); OUTS (outf, ","); OUTS (outf, dregs (dst0)); OUTS (outf, ")"); OUTS (outf, "="); OUTS (outf, "SEARCH"); OUTS (outf, dregs (src0)); OUTS (outf, "("); searchmod (aop, pc); OUTS (outf, ")"); PCREG += 4; return; } else unhandled_instruction (); } static void decode_dsp32shift_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* dsp32shift +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src0 = ((iw1 >> 3) & 0x7); int src1 = ((iw1 >> 0) & 0x7); int sop = ((iw1 >> 14) & 0x3); int dst0 = ((iw1 >> 9) & 0x7); int M = ((iw0 >> 11) & 0x1); int sopcde = ((iw0 >> 0) & 0x1f); int HLs = ((iw1 >> 12) & 0x3); if (HLs == 0 && sop == 0 && sopcde == 0) { notethat ("dregs_lo = ASHIFT dregs_lo BY dregs_lo"); OUTS (outf, dregs_lo (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, dregs_lo (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (HLs == 1 && sop == 0 && sopcde == 0) { notethat ("dregs_lo = ASHIFT dregs_hi BY dregs_lo"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "ASHIFT"); OUTS (outf, dregs_hi (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (HLs == 2 && sop == 0 && sopcde == 0) { notethat ("dregs_hi = ASHIFT dregs_lo BY dregs_lo"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); unhandled_instruction (); OUTS (outf, dregs_lo (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (HLs == 3 && sop == 0 && sopcde == 0) { notethat ("dregs_hi = ASHIFT dregs_hi BY dregs_lo"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, dregs_hi (src1)); OUTS (outf, "BY"); unhandled_instruction (); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (HLs == 0 && sop == 1 && sopcde == 0) { notethat ("dregs_lo = ASHIFT dregs_lo BY dregs_lo (S)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, dregs_lo (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "("); unhandled_instruction (); OUTS (outf, "S"); OUTS (outf, ")"); PCREG += 4; return; } else if (HLs == 1 && sop == 1 && sopcde == 0) { notethat ("dregs_lo = ASHIFT dregs_hi BY dregs_lo (S)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); unhandled_instruction (); OUTS (outf, dregs_hi (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "(S)"); PCREG += 4; return; } else if (HLs == 2 && sop == 1 && sopcde == 0) { notethat ("dregs_hi = ASHIFT dregs_lo BY dregs_lo (S)"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, dregs_lo (src1)); unhandled_instruction (); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "(S)"); PCREG += 4; return; } else if (HLs == 3 && sop == 1 && sopcde == 0) { notethat ("dregs_hi = ASHIFT dregs_hi BY dregs_lo (S)"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); unhandled_instruction (); OUTS (outf, dregs_hi (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "(S)"); PCREG += 4; return; } else if (HLs == 0 && sop == 2 && sopcde == 0) { notethat ("dregs_lo = LSHIFT dregs_lo BY dregs_lo"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "LSHIFT"); unhandled_instruction (); OUTS (outf, dregs_lo (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (HLs == 1 && sop == 2 && sopcde == 0) { notethat ("dregs_lo = LSHIFT dregs_hi BY dregs_lo"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "LSHIFT"); OUTS (outf, dregs_hi (src1)); unhandled_instruction (); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (HLs == 2 && sop == 2 && sopcde == 0) { notethat ("dregs_hi = LSHIFT dregs_lo BY dregs_lo"); OUTS (outf, dregs_hi (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "LSHIFT"); OUTS (outf, dregs_lo (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (HLs == 3 && sop == 2 && sopcde == 0) { notethat ("dregs_hi = LSHIFT dregs_hi BY dregs_lo"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, "LSHIFT"); unhandled_instruction (); OUTS (outf, dregs_hi (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 2 && sopcde == 3 && HLs == 1) { notethat ("A1 = ROT A1 BY dregs_lo"); OUTS (outf, "A1"); OUTS (outf, "="); OUTS (outf, "ROT"); unhandled_instruction (); OUTS (outf, "A1"); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 0 && sopcde == 3 && HLs == 0) { notethat ("A0 = ASHIFT A0 BY dregs_lo"); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "ASHIFT"); unhandled_instruction (); OUTS (outf, "A0"); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 0 && sopcde == 3 && HLs == 1) { notethat ("A1 = ASHIFT A1 BY dregs_lo"); OUTS (outf, "A1"); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, "A1"); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 1 && sopcde == 3 && HLs == 0) { notethat ("A0 = LSHIFT A0 BY dregs_lo"); OUTS (outf, "A0"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "LSHIFT"); OUTS (outf, "A0"); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 1 && sopcde == 3 && HLs == 1) { notethat ("A1 = LSHIFT A1 BY dregs_lo"); OUTS (outf, "A1"); OUTS (outf, "="); OUTS (outf, "LSHIFT"); unhandled_instruction (); OUTS (outf, "A1"); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 2 && sopcde == 3 && HLs == 0) { notethat ("A0 = ROT A0 BY dregs_lo"); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "ROT"); OUTS (outf, "A0"); OUTS (outf, "BY"); unhandled_instruction (); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 1 && sopcde == 1) { notethat ("dregs = ASHIFT dregs BY dregs_lo (V, S)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "("); OUTS (outf, "V,S)"); PCREG += 4; return; } else if (sop == 0 && sopcde == 1) { notethat ("dregs = ASHIFT dregs BY dregs_lo (V)"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, dregs (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "(V)"); PCREG += 4; return; } else if (sop == 0 && sopcde == 2) { notethat ("dregs = ASHIFT dregs BY dregs_lo"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, dregs (src1)); unhandled_instruction (); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 1 && sopcde == 2) { notethat ("dregs = ASHIFT dregs BY dregs_lo (S)"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "ASHIFT"); OUTS (outf, dregs (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "(S)"); PCREG += 4; return; } else if (sop == 2 && sopcde == 2) { notethat ("dregs = SHIFT dregs BY dregs_lo"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "SHIFT"); OUTS (outf, dregs (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 3 && sopcde == 2) { notethat ("dregs = ROT dregs BY dregs_lo"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "ROT"); OUTS (outf, dregs (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); PCREG += 4; return; } else if (sop == 2 && sopcde == 1) { notethat ("dregs = SHIFT dregs BY dregs_lo (V)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "SHIFT"); OUTS (outf, dregs (src1)); OUTS (outf, "BY"); OUTS (outf, dregs_lo (src0)); OUTS (outf, "(V)"); PCREG += 4; return; } else if (sop == 0 && sopcde == 4) { notethat ("dregs = PACK ( dregs_lo , dregs_lo )"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); DREG(dst0) = ((0xffff & DREG(src0)) << 16)| ((0xffff) & DREG(src1)); OUTS (outf, "PACK"); //unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs_lo (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 1 && sopcde == 4) { notethat ("dregs = PACK ( dregs_lo , dregs_hi )"); DREG(dst0) = ((0xffff & DREG(src0)) << 16)| (((0xffff0000) & DREG(src1)) >> 16); OUTS (outf, dregs (dst0)); //unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "PACK"); OUTS (outf, "("); OUTS (outf, dregs_lo (src1)); OUTS (outf, ","); OUTS (outf, dregs_hi (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 2 && sopcde == 4) { notethat ("dregs = PACK ( dregs_hi , dregs_lo )"); DREG(dst0) = (0xffff0000 & DREG(src0))| (0xffff & DREG(src1)); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "PACK"); //unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs_hi (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 3 && sopcde == 4) { notethat ("dregs = PACK ( dregs_hi , dregs_hi )"); DREG(dst0) = (0xffff0000 & DREG(src0))| (((0xffff0000) & DREG(src1)) >> 16); OUTS (outf, dregs (dst0)); OUTS (outf, "="); //unhandled_instruction (); OUTS (outf, "PACK"); OUTS (outf, "("); OUTS (outf, dregs_hi (src1)); OUTS (outf, ","); OUTS (outf, dregs_hi (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 0 && sopcde == 5) { notethat ("dregs_lo = SIGNBITS dregs"); OUTS (outf, dregs_lo (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "SIGNBITS"); OUTS (outf, dregs (src1)); PCREG += 4; return; } else if (sop == 1 && sopcde == 5) { notethat ("dregs_lo = SIGNBITS dregs_lo"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "SIGNBITS"); OUTS (outf, dregs_lo (src1)); unhandled_instruction (); PCREG += 4; return; } else if (sop == 2 && sopcde == 5) { notethat ("dregs_lo = SIGNBITS dregs_hi"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "SIGNBITS"); OUTS (outf, dregs_hi (src1)); unhandled_instruction (); PCREG += 4; return; } else if (sop == 0 && sopcde == 6) { notethat ("dregs_lo = SIGNBITS A0"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "SIGNBITS"); unhandled_instruction (); OUTS (outf, "A0"); PCREG += 4; return; } else if (sop == 1 && sopcde == 6) { notethat ("dregs_lo = SIGNBITS A1"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "SIGNBITS"); OUTS (outf, "A1"); PCREG += 4; return; } else if (sop == 3 && sopcde == 6) { notethat ("dregs_lo = ONES dregs"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "ONES"); unhandled_instruction (); OUTS (outf, dregs (src1)); PCREG += 4; return; } else if (sop == 0 && sopcde == 7) { notethat ("dregs_lo = EXPADJ (dregs , dregs_lo)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "EXPADJ ("); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 1 && sopcde == 7) { notethat ("dregs_lo = EXPADJ (dregs , dregs_lo) (V)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "EXPADJ ("); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ") (V)"); PCREG += 4; return; } else if (sop == 2 && sopcde == 7) { notethat ("dregs_lo = EXPADJ (dregs_lo , dregs_lo)"); unhandled_instruction (); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "EXPADJ ("); OUTS (outf, dregs_lo (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 3 && sopcde == 7) { notethat ("dregs_lo = EXPADJ (dregs_hi , dregs_lo)"); OUTS (outf, dregs_lo (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "EXPADJ ("); OUTS (outf, dregs_hi (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 0 && sopcde == 8) { notethat ("BITMUX (dregs , dregs , A0) (ASR)"); OUTS (outf, "BITMUX ("); OUTS (outf, dregs (src0)); unhandled_instruction (); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, "A0 )"); OUTS (outf, "(ASR)"); PCREG += 4; return; } else if (sop == 1 && sopcde == 8) { notethat ("BITMUX (dregs , dregs , A0) (ASL)"); OUTS (outf, "BITMUX ("); OUTS (outf, dregs (src0)); unhandled_instruction (); OUTS (outf, ","); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, "A0 )"); OUTS (outf, "(ASL)"); PCREG += 4; return; } else if (sop == 0 && sopcde == 9) { notethat ("dregs_lo = VIT_MAX (dregs) (ASL)"); OUTS (outf, dregs_lo (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "VIT_MAX ("); OUTS (outf, dregs (src1)); OUTS (outf, ") (ASL)"); PCREG += 4; return; } else if (sop == 1 && sopcde == 9) { notethat ("dregs_lo = VIT_MAX (dregs) (ASR)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "VIT_MAX ("); OUTS (outf, dregs (src1)); OUTS (outf, ") (ASR)"); PCREG += 4; return; } else if (sop == 2 && sopcde == 9) { notethat ("dregs = VIT_MAX ( dregs , dregs ) (ASL)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "VIT_MAX"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs (src0)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "ASL"); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 3 && sopcde == 9) { notethat ("dregs = VIT_MAX ( dregs , dregs ) (ASR)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "VIT_MAX"); OUTS (outf, "("); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs (src0)); OUTS (outf, ")"); OUTS (outf, "("); OUTS (outf, "ASR"); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 0 && sopcde == 10) { notethat ("dregs = EXTRACT ( dregs , dregs_lo ) (Z)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "EXTRACT"); OUTS (outf, "("); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ") (Z)"); PCREG += 4; return; } else if (sop == 1 && sopcde == 10) { notethat ("dregs = EXTRACT ( dregs , dregs_lo ) (X)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "EXTRACT"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); OUTS (outf, "(X)"); PCREG += 4; return; } else if (sop == 2 && sopcde == 10) { notethat ("dregs = DEPOSIT ( dregs , dregs )"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "DEPOSIT"); OUTS (outf, "("); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 3 && sopcde == 10) { notethat ("dregs = DEPOSIT ( dregs , dregs ) (X)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, "DEPOSIT"); OUTS (outf, "("); unhandled_instruction (); OUTS (outf, dregs (src1)); OUTS (outf, ","); OUTS (outf, dregs (src0)); OUTS (outf, ")"); OUTS (outf, "(X)"); PCREG += 4; return; } else if (sop == 0 && sopcde == 11) { notethat ("dregs_lo = CC = BXORSHIFT ( A0 , dregs )"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "BXORSHIFT"); OUTS (outf, "("); OUTS (outf, "A0"); OUTS (outf, ","); unhandled_instruction (); OUTS (outf, dregs (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 1 && sopcde == 11) { notethat ("dregs_lo = CC = BXOR (A0 , dregs)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "BXOR"); OUTS (outf, "(A0"); unhandled_instruction (); OUTS (outf, ","); OUTS (outf, dregs (src0)); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 0 && sopcde == 12) { notethat ("A0 = BXORSHIFT ( A0 , A1 , CC )"); OUTS (outf, "A0"); OUTS (outf, "="); OUTS (outf, "BXORSHIFT"); OUTS (outf, "("); unhandled_instruction (); OUTS (outf, "A0"); OUTS (outf, ","); OUTS (outf, "A1 ,"); OUTS (outf, "CC"); OUTS (outf, ")"); PCREG += 4; return; } else if (sop == 1 && sopcde == 12) { notethat ("dregs_lo = CC = BXOR (A0 , A1 , CC)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "BXOR"); OUTS (outf, "( A0"); OUTS (outf, ","); OUTS (outf, "A1 ,"); OUTS (outf, "CC )"); PCREG += 4; return; } else if (sop == 0 && sopcde == 13) { notethat ("dregs = ALIGN8 ( dregs , dregs )"); DREG (dst0) = (DREG (src1) << 24) | (DREG (src0) >> 8); PCREG += 4; return; } else if (sop == 1 && sopcde == 13) { notethat ("dregs = ALIGN16 ( dregs , dregs )"); DREG (dst0) = (DREG (src1) << 16) | (DREG (src0) >> 16); PCREG += 4; return; } else if (sop == 2 && sopcde == 13) { notethat ("dregs = ALIGN24 ( dregs , dregs )"); DREG (dst0) = (DREG (src1) << 8) | (DREG (src0) >> 24); PCREG += 4; return; } else unhandled_instruction (); } static void decode_dsp32shiftimm_0 (bu16 iw0, bu16 iw1, bu32 pc) { /* dsp32shiftimm +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| |.sop...|.HLs...|.dst0......|.immag.................|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int src1 = ((iw1 >> 0) & 0x7); int sop = ((iw1 >> 14) & 0x3); int immag = ((iw1 >> 3) & 0x3f); int newimmag = (-(iw1 >> 3) & 0x3f); int dst0 = ((iw1 >> 9) & 0x7); int M = ((iw0 >> 11) & 0x1); int sopcde = ((iw0 >> 0) & 0x1f); int HLs = ((iw1 >> 12) & 0x3); if (HLs == 0 && sop == 0 && sopcde == 0) { notethat ("dregs_lo = dregs_lo << uimm5"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, dregs_lo (src1)); OUTS (outf, "<<"); OUTS (outf, uimm5 (immag)); PCREG += 4; return; } else if (HLs == 1 && sop == 0 && sopcde == 0) { notethat ("dregs_lo = dregs_hi << uimm5"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src1)); OUTS (outf, "<<"); OUTS (outf, uimm5 (immag)); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 2 && sop == 0 && sopcde == 0) { notethat ("dregs_hi = dregs_lo << uimm5"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src1)); OUTS (outf, "<<"); OUTS (outf, uimm5 (immag)); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 3 && sop == 0 && sopcde == 0) { notethat ("dregs_hi = dregs_hi << uimm5"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src1)); OUTS (outf, "<<"); OUTS (outf, uimm5 (immag)); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 0 && sop == 1 && sopcde == 0) { notethat ("dregs_lo = dregs_lo << imm5 (S)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src1)); OUTS (outf, " << "); OUTS (outf, imm5 (immag)); OUTS (outf, "(S)"); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 1 && sop == 1 && sopcde == 0) { notethat ("dregs_lo = dregs_hi << imm5 (S)"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src1)); OUTS (outf, " << "); OUTS (outf, imm5 (immag)); OUTS (outf, "(S)"); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 2 && sop == 1 && sopcde == 0) { notethat ("dregs_hi = dregs_lo << imm5 (S)"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src1)); OUTS (outf, " << "); OUTS (outf, imm5 (immag)); OUTS (outf, "(S)"); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 3 && sop == 1 && sopcde == 0) { notethat ("dregs_hi = dregs_hi << imm5 (S)"); OUTS (outf, dregs_hi (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src1)); OUTS (outf, " << "); OUTS (outf, imm5 (immag)); OUTS (outf, "(S)"); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 0 && sop == 2 && sopcde == 0) { notethat ("dregs_lo = dregs_lo >> uimm5"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_lo (src1)); OUTS (outf, ">>"); unhandled_instruction (); OUTS (outf, uimm5 (newimmag)); PCREG += 4; return; } else if (HLs == 1 && sop == 2 && sopcde == 0) { notethat ("dregs_lo = dregs_hi >> uimm5"); OUTS (outf, dregs_lo (dst0)); OUTS (outf, "="); OUTS (outf, dregs_hi (src1)); OUTS (outf, ">>"); OUTS (outf, uimm5 (newimmag)); unhandled_instruction (); PCREG += 4; return; } else if (HLs == 2 && sop == 2 && sopcde == 0) { notethat ("dregs_hi = dregs_lo >> uimm5"); OUTS (outf, dregs_hi (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs_lo (src1)); OUTS (outf, ">>"); OUTS (outf, uimm5 (newimmag)); PCREG += 4; return; } else if (HLs == 3 && sop == 2 && sopcde == 0) { notethat ("dregs_hi = dregs_hi >> uimm5"); OUTS (outf, dregs_hi (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs_hi (src1)); OUTS (outf, ">>"); OUTS (outf, uimm5 (newimmag)); PCREG += 4; return; } else if (sop == 2 && sopcde == 3 && HLs == 1) { notethat ("A1 = ROT A1 BY imm6"); OUTS (outf, "A1"); OUTS (outf, "="); OUTS (outf, "ROT"); unhandled_instruction (); OUTS (outf, "A1"); OUTS (outf, "BY"); OUTS (outf, imm6 (immag)); PCREG += 4; return; } else if (sop == 0 && sopcde == 3 && HLs == 0) { notethat ("A0 = A0 << imm6"); OUTS (outf, "A0"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "<<"); OUTS (outf, imm6 (immag)); PCREG += 4; return; } else if (sop == 0 && sopcde == 3 && HLs == 1) { notethat ("A1 = A1 << imm6"); OUTS (outf, "A1"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "A1"); OUTS (outf, "<<"); OUTS (outf, imm6 (immag)); PCREG += 4; return; } else if (sop == 1 && sopcde == 3 && HLs == 0) { notethat ("A0 = A0 >> imm6"); OUTS (outf, "A0"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "A0"); OUTS (outf, ">>"); OUTS (outf, imm6 (newimmag)); PCREG += 4; return; } else if (sop == 1 && sopcde == 3 && HLs == 1) { notethat ("A1 = A1 >> imm6"); OUTS (outf, "A1"); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, "A1"); OUTS (outf, ">>"); OUTS (outf, imm6 (newimmag)); PCREG += 4; return; } else if (sop == 2 && sopcde == 3 && HLs == 0) { notethat ("A0 = ROT A0 BY imm6"); OUTS (outf, "A0"); OUTS (outf, "="); unhandled_instruction (); OUTS (outf, "ROT"); OUTS (outf, "A0"); OUTS (outf, "BY"); OUTS (outf, imm6 (immag)); PCREG += 4; return; } else if (sop == 1 && sopcde == 1) { notethat ("dregs = dregs >>> uimm5 (V, S)"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs (src1)); OUTS (outf, " >>> "); OUTS (outf, imm5 (-immag)); OUTS (outf, " (V, "); OUTS (outf, "S)"); PCREG += 4; return; } else if (sop == 2 && sopcde == 1) { notethat ("dregs = dregs >> uimm5 (V)"); OUTS (outf, dregs (dst0)); OUTS (outf, "="); OUTS (outf, dregs (src1)); OUTS (outf, " >> "); //DREG(dst0) = DREG(src1) >> uimm5(newimmag); //fprintf(stderr,"KSDBG:DREG(dst0)=0x%x(%d),DREG(src1)=0x%x(%d)\n",DREG(dst0),dst0,DREG(src1),src1); if(newimmag >> 5){ /* 2's complement,fixme,I just extract 4 bit */ int imm; imm = ((0x3f - newimmag)+1) & 0xf; //fprintf(stderr,"KSDBG:dregs(0x%x) = dregs(0x%x) << %d (V)",DREG(dst0),DREG(src1),imm); DREG(dst0) = ((DREG(src1) << imm)&0xffff) |((DREG(src1)&0xffff0000) << imm); } else DREG(dst0) = ((DREG(src1)&0xffff)>>uimm5(newimmag)) |((DREG(src1) >> uimm5(newimmag))&0xffff0000); //fprintf(stderr,"KSDBG:dregs(0x%x) = dregs(0x%x) >> uimm5 (V),uimm5=%d\n", DREG(dst0), DREG(src1), uimm5(newimmag)); //unhandled_instruction (); OUTS (outf, uimm5 (newimmag)); OUTS (outf, " (V)"); PCREG += 4; return; } else if (sop == 0 && sopcde == 1) { notethat ("dregs = dregs << imm5 (V)"); fprintf(stderr,"KSDBG:dregs = dregs << uimm5 (V)"); OUTS (outf, dregs (dst0)); //unhandled_instruction (); //DREG(dst0) = DREG(src1) << imm5(immag); DREG(dst0) = (DREG(src1)&0xffff << imm5(immag)) |(DREG(src1)&0xffff0000 << imm5(immag)); OUTS (outf, "="); OUTS (outf, dregs (src1)); OUTS (outf, " << "); OUTS (outf, imm5 (immag)); OUTS (outf, " (V)"); PCREG += 4; return; } else if (sop == 1 && sopcde == 2) { notethat ("dregs = dregs << imm6 (S)"); OUTS (outf, dregs (dst0)); unhandled_instruction (); OUTS (outf, "="); OUTS (outf, dregs (src1)); OUTS (outf, "<<"); OUTS (outf, imm6 (immag)); OUTS (outf, "("); OUTS (outf, "S)"); PCREG += 4; return; } else if (sop == 2 && sopcde == 2) { int count = imm6 (newimmag); notethat ("dregs = dregs >> imm6"); if (count < 0) DREG (dst0) = lshift (DREG (src1), -count); else DREG (dst0) = lshiftrt (DREG (src1), count); if(count == 0) DREG(dst0) = DREG(src1); PCREG += 4; return; } else if (sop == 3 && sopcde == 2) { int t = imm6 (immag); notethat ("dregs = ROT dregs BY imm6"); /* Reduce everything to rotate left. */ if (t < 0) t += 33; if (t > 0) { int oldcc = CCREG; bu32 srcval = DREG (src1); bu32 result; result = t == 32 ? 0 : srcval << t; result |= t == 1 ? 0 : srcval >> (33 - t); result |= oldcc << (t - 1); DREG (dst0) = result; CCREG = (srcval >> (32 - t)) & 1; } if (t == 0) DREG(dst0) = DREG(src1); PCREG += 4; return; } else if (sop == 0 && sopcde == 2) { int count = imm6 (newimmag); notethat ("dregs = dregs >>> imm6"); if (count < 0) DREG (dst0) = lshift (DREG (src1), -count); else DREG (dst0) = ashiftrt (DREG (src1), count); PCREG += 4; return; } else unhandled_instruction (); } static void decode_psedoDEBUG_0 (bu16 iw0) { /* psedoDEBUG +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int grp = ((iw0 >> 3) & 0x7); int fn = ((iw0 >> 6) & 0x3); int reg = ((iw0 >> 0) & 0x7); if (reg == 0 && fn == 3) { notethat ("DBG A0"); OUTS (outf, "DBG"); unhandled_instruction (); OUTS (outf, "A0"); PCREG += 2; return; } else if (reg == 1 && fn == 3) { notethat ("DBG A1"); unhandled_instruction (); OUTS (outf, "DBG"); OUTS (outf, "A1"); PCREG += 2; return; } else if (reg == 3 && fn == 3) { notethat ("ABORT"); OUTS (outf, "ABORT"); unhandled_instruction (); PCREG += 2; return; } else if (reg == 4 && fn == 3) { notethat ("HLT"); OUTS (outf, "HLT"); unhandled_instruction (); PCREG += 2; return; } else if (reg == 5 && fn == 3) { notethat ("DBGHALT"); OUTS (outf, "DBGHALT"); unhandled_instruction (); PCREG += 2; return; } else if (reg == 6 && fn == 3) { notethat ("DBGCMPLX ( dregs )"); OUTS (outf, "DBGCMPLX"); OUTS (outf, "("); OUTS (outf, dregs (grp)); unhandled_instruction (); OUTS (outf, ")"); PCREG += 2; return; } else if (reg == 7 && fn == 3) { notethat ("DBG"); OUTS (outf, "DBG"); unhandled_instruction (); PCREG += 2; return; } else if (grp == 0 && fn == 2) { notethat ("OUTC dregs"); OUTS (outf, "OUTC"); unhandled_instruction (); OUTS (outf, dregs (reg)); PCREG += 2; return; } else if (fn == 0) { notethat ("DBG allregs"); unhandled_instruction (); OUTS (outf, "DBG"); OUTS (outf, allregs (reg, grp)); PCREG += 2; return; } else if (fn == 1) { notethat ("PRNT allregs"); unhandled_instruction (); OUTS (outf, "PRNT"); OUTS (outf, allregs (reg, grp)); PCREG += 2; return; } else unhandled_instruction (); } static void decode_psedoOChar_0 (bu16 iw0) { /* psedoOChar +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int ch = ((iw0 >> 0) & 0xff); notethat ("OUTC uimm8"); unhandled_instruction (); OUTS (outf, "OUTC"); OUTS (outf, uimm8 (ch)); PCREG += 2; return; } static void decode_psedodbg_assert_0 (bu16 iw0, bu16 iw1) { /* psedodbg_assert +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...| |.expected......................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int expected = ((iw1 >> 0) & 0xffff); int dbgop = ((iw0 >> 3) & 0x7); int regtest = ((iw0 >> 0) & 0x7); if (dbgop == 0) { notethat ("DBGA ( dregs_lo , uimm16 )"); OUTS (outf, "DBGA"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs_lo (regtest)); OUTS (outf, ","); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); PCREG += 4; return; } else if (dbgop == 1) { notethat ("DBGA ( dregs_hi , uimm16 )"); unhandled_instruction (); OUTS (outf, "DBGA"); OUTS (outf, "("); OUTS (outf, dregs_hi (regtest)); OUTS (outf, ","); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); PCREG += 4; return; } else if (dbgop == 2) { notethat ("DBGAL ( dregs , uimm16 )"); OUTS (outf, "DBGAL"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs (regtest)); OUTS (outf, ","); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); PCREG += 4; return; } else if (dbgop == 3) { notethat ("DBGAH ( dregs , uimm16 )"); OUTS (outf, "DBGAH"); unhandled_instruction (); OUTS (outf, "("); OUTS (outf, dregs (regtest)); OUTS (outf, ","); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); PCREG += 4; return; } else unhandled_instruction (); } static void _interp_insn_bfin (bu32 pc) { bu8 buf[4]; bu16 iw0 = get_word (saved_state.memory, pc); bu16 iw1 = get_word (saved_state.memory, pc + 2); if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) { /* MNOP. */ PCREG += 4; return; } if ((iw0 & 0xFF00) == 0x0000) decode_ProgCtrl_0 (iw0); else if ((iw0 & 0xFFC0) == 0x0240) decode_CaCTRL_0 (iw0); else if ((iw0 & 0xFF80) == 0x0100) decode_PushPopReg_0 (iw0); else if ((iw0 & 0xFE00) == 0x0400) decode_PushPopMultiple_0 (iw0); else if ((iw0 & 0xFE00) == 0x0600) decode_ccMV_0 (iw0); else if ((iw0 & 0xF800) == 0x0800) decode_CCflag_0 (iw0); else if ((iw0 & 0xFFE0) == 0x0200) decode_CC2dreg_0 (iw0); else if ((iw0 & 0xFF00) == 0x0300) decode_CC2stat_0 (iw0); else if ((iw0 & 0xF000) == 0x1000) decode_BRCC_0 (iw0, pc); else if ((iw0 & 0xF000) == 0x2000) decode_UJUMP_0 (iw0, pc); else if ((iw0 & 0xF000) == 0x3000) decode_REGMV_0 (iw0); else if ((iw0 & 0xFC00) == 0x4000) decode_ALU2op_0 (iw0); else if ((iw0 & 0xFE00) == 0x4400) decode_PTR2op_0 (iw0); else if (((iw0 & 0xF800) == 0x4800)) decode_LOGI2op_0 (iw0); else if (((iw0 & 0xF000) == 0x5000)) decode_COMP3op_0 (iw0); else if (((iw0 & 0xF800) == 0x6000)) decode_COMPI2opD_0 (iw0); else if (((iw0 & 0xF800) == 0x6800)) decode_COMPI2opP_0 (iw0); else if (((iw0 & 0xF000) == 0x8000)) decode_LDSTpmod_0 (iw0); else if (((iw0 & 0xFF60) == 0x9E60)) decode_dagMODim_0 (iw0); else if (((iw0 & 0xFFF0) == 0x9F60)) decode_dagMODik_0 (iw0); else if (((iw0 & 0xFC00) == 0x9C00)) decode_dspLDST_0 (iw0); else if (((iw0 & 0xF000) == 0x9000)) decode_LDST_0 (iw0); else if (((iw0 & 0xFC00) == 0xB800)) decode_LDSTiiFP_0 (iw0); else if (((iw0 & 0xE000) == 0xA000)) decode_LDSTii_0 (iw0); else if (((iw0 & 0xFF80) == 0xE080) && ((iw1 & 0x0C00) == 0x0000)) decode_LoopSetup_0 (iw0, iw1, pc); else if (((iw0 & 0xFF00) == 0xE100) && ((iw1 & 0x0000) == 0x0000)) decode_LDIMMhalf_0 (iw0, iw1, pc); else if (((iw0 & 0xFE00) == 0xE200) && ((iw1 & 0x0000) == 0x0000)) decode_CALLa_0 (iw0, iw1, pc); else if (((iw0 & 0xFC00) == 0xE400) && ((iw1 & 0x0000) == 0x0000)) decode_LDSTidxI_0 (iw0, iw1, pc); else if (((iw0 & 0xFFFE) == 0xE800) && ((iw1 & 0x0000) == 0x0000)) decode_linkage_0 (iw0, iw1); else if (((iw0 & 0xF600) == 0xC000) && ((iw1 & 0x0000) == 0x0000)) decode_dsp32mac_0 (iw0, iw1, pc); else if (((iw0 & 0xF600) == 0xC200) && ((iw1 & 0x0000) == 0x0000)) decode_dsp32mult_0 (iw0, iw1, pc); else if (((iw0 & 0xF7C0) == 0xC400) && ((iw1 & 0x0000) == 0x0000)) decode_dsp32alu_0 (iw0, iw1, pc); else if (((iw0 & 0xF7E0) == 0xC600) && ((iw1 & 0x01C0) == 0x0000)) decode_dsp32shift_0 (iw0, iw1, pc); else if (((iw0 & 0xF7E0) == 0xC680) && ((iw1 & 0x0000) == 0x0000)) decode_dsp32shiftimm_0 (iw0, iw1, pc); else if (((iw0 & 0xFF00) == 0xF800)) decode_psedoDEBUG_0 (iw0); else if (((iw0 & 0xFF00) == 0xF900)) decode_psedoOChar_0 (iw0); else if (((iw0 & 0xFFC0) == 0xF000) && ((iw1 & 0x0000) == 0x0000)) decode_psedodbg_assert_0 (iw0, iw1); else { unhandled_instruction (); } } void interp_insn_bfin (bu32 pc) { int i; bu16 iw0 = get_word (saved_state.memory, pc); int is_multiinsn = ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS) && ((iw0 & 0xe800) != 0xe800 /* not Linkage */ )); n_stores = 0; _interp_insn_bfin (pc); // Proper display of multiple issue instructions if (is_multiinsn) { _interp_insn_bfin (pc + 4); _interp_insn_bfin (pc + 6); } for (i = 0; i < n_stores; i++) *stores[i].addr = stores[i].val; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/un-syscall.h������������������������������������������������������0000644�0001750�0000144�00000001414�10541455476�017637� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������ /* !!! DANGER !!! This was copied from newlib. */ #define SYS_exit 1 #define SYS_fork 2 #define SYS_read 3 #define SYS_write 4 #define SYS_open 5 #define SYS_close 6 #define SYS_wait4 7 #define SYS_creat 8 #define SYS_link 9 #define SYS_unlink 10 #define SYS_execv 11 #define SYS_chdir 12 #define SYS_mknod 14 #define SYS_chmod 15 #define SYS_chown 16 #define SYS_lseek 19 #define SYS_getpid 20 #define SYS_isatty 21 #define SYS_fstat 22 #define SYS_time 23 #define SYS_ARG 24 #define SYS_stat 38 #define SYS_pipe 42 #define SYS_execve 59 #define SYS_truncate 129 #define SYS_ftruncate 130 #define SYS_argc 172 #define SYS_argnlen 173 #define SYS_argn 174 #define SYS_utime 201 /* not really a system call */ #define SYS_wait 202 /* nor is this */ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/bfin_io.h���������������������������������������������������������0000644�0001750�0000144�00000000347�10541455476�017156� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "types.h" bu8 io_read_byte (bu32 addr); bu16 io_read_word (bu32 addr); bu32 io_read_long (bu32 addr); void io_write_byte (bu32 addr, bu8 v); void io_write_word (bu32 addr, bu16 v); void io_write_long (bu32 addr, bu32 v); �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/syscall.h���������������������������������������������������������0000755�0001750�0000144�00000001503�10541455476�017221� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This file is copied from newlib. Do not edit this alone. */ #define SYS_exit 1 #define SYS_fork 2 #define SYS_read 3 #define SYS_write 4 #define SYS_open 5 #define SYS_close 6 #define SYS_wait4 7 #define SYS_creat 8 #define SYS_link 9 #define SYS_unlink 10 #define SYS_execv 11 #define SYS_chdir 12 #define SYS_mknod 14 #define SYS_chmod 15 #define SYS_chown 16 #define SYS_lseek 19 #define SYS_getpid 20 #define SYS_isatty 21 #define SYS_fstat 22 #define SYS_time 23 #define SYS_kill 24 #define SYS_stat 38 #define SYS_pipe 42 #define SYS_execve 59 #define SYS_truncate 129 #define SYS_ftruncate 130 #define SYS_argc 172 /* == 0xAC, for Argument Count :-) */ #define SYS_argnlen 173 #define SYS_argn 174 #define SYS_utime 201 /* not really a system call */ #define SYS_wait 202 /* nor is this */ ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/types.h�����������������������������������������������������������0000644�0001750�0000144�00000002402�10571721153�016676� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* types.h - necessary type definition for blackfin simulation Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef _TYPES_H #define _TYPES_H typedef unsigned char bu8; typedef unsigned short bu16; typedef unsigned int bu32; typedef unsigned long long bu64; typedef signed char bs8; typedef short bs16; typedef int bs32; typedef long long bs64; #endif ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/iomem.c�����������������������������������������������������������0000644�0001750�0000144�00000017202�10642320132�016626� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* iomem.c - implementation of read/write function for blackfin simulation Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "bfin-sim.h" #include "types.h" #include "mem_map.h" #include <signal.h> #include <skyeye_config.h> bu32 get_long (unsigned char *memory, bu32 addr); //#define IO_ERR {printf("\n%s io error!addr=0x%x\n",__FUNCTION__,addr);exit(-1);} #define IO_ERR {printf("\n%s io error!addr=0x%x,pc=0x%x,oldpc=0x%x,sp=0x%x,insn@pc=0x%x\n",__FUNCTION__,addr,PCREG,OLDPCREG,SPREG,get_long(saved_state.memory,PCREG));exit(-1);} static void isram_write_word (bu32 addr, bu16 v) { int offset = addr - ISRAM_START; //saved_state.isram[offset] = (bu16)v; saved_state.isram[offset] = v; saved_state.isram[offset + 1] = v >> 8; } static bu16 isram_read_word (bu32 addr) { int offset = addr - ISRAM_START; //return (bu16)(saved_state.isram[offset]); return saved_state.isram[offset] | (saved_state. isram[offset + 1] << 8); } static void isram_write_byte (bu32 addr, bu8 v) { int offset = addr - ISRAM_START; saved_state.isram[offset] = v; } static bu8 isram_read_byte (bu32 addr) { int offset = addr - ISRAM_START; return saved_state.isram[offset]; } static bu32 isram_read_long (bu32 addr) { int offset = addr - ISRAM_START; //printf("ssram_read_long addr %p\n",addr); //return (bu16)(saved_state.ssram[offset]); return (saved_state.isram[offset] | (saved_state.isram[offset + 1] << 8) | (saved_state.isram[offset + 2] << 16) | (saved_state.isram[offset + 3] << 24) ); } //PSW scratch pad ram 061606 static void ssram_write_long (bu32 addr, bu32 v) { int offset = addr - SSRAM_START; //printf("ssram_write_long addr %p\n",addr); //saved_state.ssram[offset] = (bu16)v; saved_state.ssram[offset] = v; saved_state.ssram[offset + 1] = v >> 8; saved_state.ssram[offset + 2] = v >> 16; saved_state.ssram[offset + 3] = v >> 24; } static bu32 ssram_read_long (bu32 addr) { int offset = addr - SSRAM_START; //printf("ssram_read_long addr %p\n",addr); //return (bu16)(saved_state.ssram[offset]); return (saved_state.ssram[offset] | (saved_state.ssram[offset + 1] << 8) | (saved_state.ssram[offset + 2] << 16) | (saved_state.ssram[offset + 3] << 24) ); } static void ssram_write_word (bu32 addr, bu16 v) { int offset = addr - SSRAM_START; //printf("ssram_write_word addr %p\n",addr); //saved_state.ssram[offset] = (bu16)v; saved_state.ssram[offset] = v; saved_state.ssram[offset + 1] = v >> 8; } static bu16 ssram_read_word (bu32 addr) { int offset = addr - SSRAM_START; //printf("ssram_read_word addr %p\n",addr); //return (bu16)(saved_state.ssram[offset]); return saved_state.ssram[offset] | (saved_state. ssram[offset + 1] << 8); } static void ssram_write_byte (bu32 addr, bu8 v) { int offset = addr - SSRAM_START; //printf("ssram_read_byte addr %p\n",addr); saved_state.ssram[offset] = v; } static bu8 ssram_read_byte (bu32 addr) { int offset = addr - SSRAM_START; //printf("ssram_read_byte addr %p\n",addr); return saved_state.ssram[offset]; } static void dsram_write_byte (bu32 addr, bu8 v) { int offset = addr - DSRAM_START; saved_state.dsram[offset] = v; } static bu8 dsram_read_byte (bu32 addr) { int offset = addr - DSRAM_START; return saved_state.dsram[offset]; } void put_byte (unsigned char *memory, bu32 addr, bu8 v) { if ((addr >= IO_START) && (addr < IO_END)) { skyeye_config.mach->mach_io_write_byte (&saved_state, addr, v); } else if (addr >= ISRAM_START && addr < ISRAM_END) { isram_write_byte (addr, v); } else if (addr >= DSRAM_START && addr < DSRAM_END) { dsram_write_byte (addr, v); } // PSW 061606 else if (addr >= SSRAM_START && addr < SSRAM_END) { ssram_write_byte (addr, v); } else if (addr >= SDRAM_START && addr < SDRAM_END) { memory[addr] = v; } else if (addr >= BANK0_START && addr < BANK3_END) { } else { IO_ERR; exit(-1); } } void put_word (unsigned char *memory, bu32 addr, bu16 v) { if ((addr >= IO_START) && (addr < IO_END)) { skyeye_config.mach->mach_io_write_halfword (&saved_state, addr, v); } else if (addr >= ISRAM_START && addr < ISRAM_END) { IO_ERR; } // PSW 061606 else if (addr >= SSRAM_START && addr < SSRAM_END) { ssram_write_word (addr, v); } else if (addr >= SDRAM_START && addr < SDRAM_END) { //memory[addr] = (bu16)v; memory[addr] = v; memory[addr + 1] = v >> 8; } else { IO_ERR; } } void put_long (unsigned char *memory, bu32 addr, bu32 v) { if ((addr > IO_START) && (addr < IO_END)) { skyeye_config.mach->mach_io_write_word (&saved_state, addr, v); } // PSW 061606 else if (addr >= SSRAM_START && addr < SSRAM_END) { ssram_write_long (addr, v); } else if (addr >= SDRAM_START && addr < SDRAM_END) { //memory[addr] = (bu32)v; memory[addr] = v; memory[addr + 1] = v >> 8; memory[addr + 2] = v >> 16; memory[addr + 3] = v >> 24; } else { IO_ERR; } } bu8 get_byte (unsigned char *memory, bu32 addr) { if ((addr >= IO_START) && (addr < IO_END)) { return skyeye_config.mach->mach_io_read_byte (&saved_state, addr); } else if (addr >= ISRAM_START && addr < ISRAM_END) { return isram_read_byte (addr); } else if (addr >= DSRAM_START && addr < DSRAM_END) { return dsram_read_byte (addr); } // PSW 061606 else if (addr >= SSRAM_START && addr < SSRAM_END) { return ssram_read_byte (addr); } else if (addr >= SDRAM_START && addr < SDRAM_END) return memory[addr]; else { IO_ERR; } } bu16 get_word (unsigned char *memory, bu32 addr) { if ((addr >= IO_START) && (addr < IO_END)) { return skyeye_config.mach->mach_io_read_halfword (&saved_state, addr); } else if (addr >= ISRAM_START && addr < ISRAM_END) { return isram_read_word (addr); } //PSW 061606 else if (addr >= SSRAM_START && addr < SSRAM_END) { return ssram_read_word (addr); } else if (addr >= SDRAM_START && addr < SDRAM_END) { //return (bu16)(memory[addr]); return memory[addr] | (memory[addr + 1] << 8); } else { IO_ERR; } } bu32 get_long (unsigned char *memory, bu32 addr) { if ((addr >= IO_START) && (addr < IO_END)) { return skyeye_config.mach->mach_io_read_word (&saved_state, addr); } else if (addr >= ISRAM_START && addr < ISRAM_END) { return isram_read_long (addr); } //PSW 061606 else if (addr >= SSRAM_START && addr < SSRAM_END) { return ssram_read_long (addr); } else if (addr >= SDRAM_START && addr < SDRAM_END) { //return (bu32)(memory[addr]); return (memory[addr] | (memory[addr + 1] << 8) | (memory[addr + 2] << 16) | (memory[addr + 3] << 24)); } else { IO_ERR; } } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/opcode/�����������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�016622� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/opcode/bfin.h�����������������������������������������������������0000755�0001750�0000144�00000121116�10541455476�017741� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#if !defined(BFIN_OPCODES_H_HD9837U0U9I27E902702DYHCXH2D79218D701D) #define BFIN_OPCODES_H_HD9837U0U9I27E902702DYHCXH2D79218D701D /* * * This file contains the bitfield defines * for the Blackfin opcodes * * (c) 03/2004 Martin Strubel <hackfin@section5.ch> * */ /* Common to all DSP32 instructions. */ #define BIT_MULTI_INS 0x0800 /* This just sets the multi instruction bit of a DSP32 instruction. */ #define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS; /* DSP instructions (32 bit) */ /* dsp32mac +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_src1; int mask_src1; int bits_src0; int mask_src0; int bits_dst; int mask_dst; int bits_h10; int mask_h10; int bits_h00; int mask_h00; int bits_op0; int mask_op0; int bits_w0; int mask_w0; int bits_h11; int mask_h11; int bits_h01; int mask_h01; int bits_op1; int mask_op1; int bits_w1; int mask_w1; int bits_P; int mask_P; int bits_MM; int mask_MM; int bits_mmod; int mask_mmod; int bits_code2; int mask_code2; int bits_M; int mask_M; int bits_code; int mask_code; } DSP32Mac; #define DSP32Mac_opcode 0xc0000000 #define DSP32Mac_src1_bits 0 #define DSP32Mac_src1_mask 0x7 #define DSP32Mac_src0_bits 3 #define DSP32Mac_src0_mask 0x7 #define DSP32Mac_dst_bits 6 #define DSP32Mac_dst_mask 0x7 #define DSP32Mac_h10_bits 9 #define DSP32Mac_h10_mask 0x1 #define DSP32Mac_h00_bits 10 #define DSP32Mac_h00_mask 0x1 #define DSP32Mac_op0_bits 11 #define DSP32Mac_op0_mask 0x3 #define DSP32Mac_w0_bits 13 #define DSP32Mac_w0_mask 0x1 #define DSP32Mac_h11_bits 14 #define DSP32Mac_h11_mask 0x1 #define DSP32Mac_h01_bits 15 #define DSP32Mac_h01_mask 0x1 #define DSP32Mac_op1_bits 16 #define DSP32Mac_op1_mask 0x3 #define DSP32Mac_w1_bits 18 #define DSP32Mac_w1_mask 0x1 #define DSP32Mac_p_bits 19 #define DSP32Mac_p_mask 0x1 #define DSP32Mac_MM_bits 20 #define DSP32Mac_MM_mask 0x1 #define DSP32Mac_mmod_bits 21 #define DSP32Mac_mmod_mask 0xf #define DSP32Mac_code2_bits 25 #define DSP32Mac_code2_mask 0x3 #define DSP32Mac_M_bits 27 #define DSP32Mac_M_mask 0x1 #define DSP32Mac_code_bits 28 #define DSP32Mac_code_mask 0xf #define init_DSP32Mac \ { \ DSP32Mac_opcode, \ DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ DSP32Mac_p_bits, DSP32Mac_p_mask, \ DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ DSP32Mac_M_bits, DSP32Mac_M_mask, \ DSP32Mac_code_bits, DSP32Mac_code_mask \ }; /* dsp32mult +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ */ typedef DSP32Mac DSP32Mult; #define DSP32Mult_opcode 0xc2000000 #define init_DSP32Mult \ { \ DSP32Mult_opcode, \ DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ DSP32Mac_p_bits, DSP32Mac_p_mask, \ DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ DSP32Mac_M_bits, DSP32Mac_M_mask, \ DSP32Mac_code_bits, DSP32Mac_code_mask \ }; /* dsp32alu +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_src1; int mask_src1; int bits_src0; int mask_src0; int bits_dst1; int mask_dst1; int bits_dst0; int mask_dst0; int bits_x; int mask_x; int bits_s; int mask_s; int bits_aop; int mask_aop; int bits_aopcde; int mask_aopcde; int bits_HL; int mask_HL; int bits_dontcare; int mask_dontcare; int bits_code2; int mask_code2; int bits_M; int mask_M; int bits_code; int mask_code; } DSP32Alu; #define DSP32Alu_opcode 0xc4000000 #define DSP32Alu_src1_bits 0 #define DSP32Alu_src1_mask 0x7 #define DSP32Alu_src0_bits 3 #define DSP32Alu_src0_mask 0x7 #define DSP32Alu_dst1_bits 6 #define DSP32Alu_dst1_mask 0x7 #define DSP32Alu_dst0_bits 9 #define DSP32Alu_dst0_mask 0x7 #define DSP32Alu_x_bits 12 #define DSP32Alu_x_mask 0x1 #define DSP32Alu_s_bits 13 #define DSP32Alu_s_mask 0x1 #define DSP32Alu_aop_bits 14 #define DSP32Alu_aop_mask 0x3 #define DSP32Alu_aopcde_bits 16 #define DSP32Alu_aopcde_mask 0x1f #define DSP32Alu_HL_bits 21 #define DSP32Alu_HL_mask 0x1 #define DSP32Alu_dontcare_bits 22 #define DSP32Alu_dontcare_mask 0x7 #define DSP32Alu_code2_bits 25 #define DSP32Alu_code2_mask 0x3 #define DSP32Alu_M_bits 27 #define DSP32Alu_M_mask 0x1 #define DSP32Alu_code_bits 28 #define DSP32Alu_code_mask 0xf #define init_DSP32Alu \ { \ DSP32Alu_opcode, \ DSP32Alu_src1_bits, DSP32Alu_src1_mask, \ DSP32Alu_src0_bits, DSP32Alu_src0_mask, \ DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \ DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \ DSP32Alu_x_bits, DSP32Alu_x_mask, \ DSP32Alu_s_bits, DSP32Alu_s_mask, \ DSP32Alu_aop_bits, DSP32Alu_aop_mask, \ DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \ DSP32Alu_HL_bits, DSP32Alu_HL_mask, \ DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \ DSP32Alu_code2_bits, DSP32Alu_code2_mask, \ DSP32Alu_M_bits, DSP32Alu_M_mask, \ DSP32Alu_code_bits, DSP32Alu_code_mask \ }; /* dsp32shift +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_src1; int mask_src1; int bits_src0; int mask_src0; int bits_dst1; int mask_dst1; int bits_dst0; int mask_dst0; int bits_HLs; int mask_HLs; int bits_sop; int mask_sop; int bits_sopcde; int mask_sopcde; int bits_dontcare; int mask_dontcare; int bits_code2; int mask_code2; int bits_M; int mask_M; int bits_code; int mask_code; } DSP32Shift; #define DSP32Shift_opcode 0xc6000000 #define DSP32Shift_src1_bits 0 #define DSP32Shift_src1_mask 0x7 #define DSP32Shift_src0_bits 3 #define DSP32Shift_src0_mask 0x7 #define DSP32Shift_dst1_bits 6 #define DSP32Shift_dst1_mask 0x7 #define DSP32Shift_dst0_bits 9 #define DSP32Shift_dst0_mask 0x7 #define DSP32Shift_HLs_bits 12 #define DSP32Shift_HLs_mask 0x3 #define DSP32Shift_sop_bits 14 #define DSP32Shift_sop_mask 0x3 #define DSP32Shift_sopcde_bits 16 #define DSP32Shift_sopcde_mask 0x1f #define DSP32Shift_dontcare_bits 21 #define DSP32Shift_dontcare_mask 0x3 #define DSP32Shift_code2_bits 23 #define DSP32Shift_code2_mask 0xf #define DSP32Shift_M_bits 27 #define DSP32Shift_M_mask 0x1 #define DSP32Shift_code_bits 28 #define DSP32Shift_code_mask 0xf #define init_DSP32Shift \ { \ DSP32Shift_opcode, \ DSP32Shift_src1_bits, DSP32Shift_src1_mask, \ DSP32Shift_src0_bits, DSP32Shift_src0_mask, \ DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \ DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \ DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \ DSP32Shift_sop_bits, DSP32Shift_sop_mask, \ DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \ DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \ DSP32Shift_code2_bits, DSP32Shift_code2_mask, \ DSP32Shift_M_bits, DSP32Shift_M_mask, \ DSP32Shift_code_bits, DSP32Shift_code_mask \ }; /* dsp32shiftimm +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| |.sop...|.HLs...|.dst0......|.immag.................|.src1......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_src1; int mask_src1; int bits_immag; int mask_immag; int bits_dst0; int mask_dst0; int bits_HLs; int mask_HLs; int bits_sop; int mask_sop; int bits_sopcde; int mask_sopcde; int bits_dontcare; int mask_dontcare; int bits_code2; int mask_code2; int bits_M; int mask_M; int bits_code; int mask_code; } DSP32ShiftImm; #define DSP32ShiftImm_opcode 0xc6800000 #define DSP32ShiftImm_src1_bits 0 #define DSP32ShiftImm_src1_mask 0x7 #define DSP32ShiftImm_immag_bits 3 #define DSP32ShiftImm_immag_mask 0x3f #define DSP32ShiftImm_dst0_bits 9 #define DSP32ShiftImm_dst0_mask 0x7 #define DSP32ShiftImm_HLs_bits 12 #define DSP32ShiftImm_HLs_mask 0x3 #define DSP32ShiftImm_sop_bits 14 #define DSP32ShiftImm_sop_mask 0x3 #define DSP32ShiftImm_sopcde_bits 16 #define DSP32ShiftImm_sopcde_mask 0x1f #define DSP32ShiftImm_dontcare_bits 21 #define DSP32ShiftImm_dontcare_mask 0x3 #define DSP32ShiftImm_code2_bits 23 #define DSP32ShiftImm_code2_mask 0xf #define DSP32ShiftImm_M_bits 27 #define DSP32ShiftImm_M_mask 0x1 #define DSP32ShiftImm_code_bits 28 #define DSP32ShiftImm_code_mask 0xf #define init_DSP32ShiftImm \ { \ DSP32ShiftImm_opcode, \ DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \ DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \ DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \ DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \ DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \ DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \ DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \ DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \ DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \ DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \ }; /* LOAD / STORE */ /* LDSTidxI +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| |.offset........................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_offset; int mask_offset; int bits_reg; int mask_reg; int bits_ptr; int mask_ptr; int bits_sz; int mask_sz; int bits_Z; int mask_Z; int bits_W; int mask_W; int bits_code; int mask_code; } LDSTidxI; #define LDSTidxI_opcode 0xe4000000 #define LDSTidxI_offset_bits 0 #define LDSTidxI_offset_mask 0xffff #define LDSTidxI_reg_bits 16 #define LDSTidxI_reg_mask 0x7 #define LDSTidxI_ptr_bits 19 #define LDSTidxI_ptr_mask 0x7 #define LDSTidxI_sz_bits 22 #define LDSTidxI_sz_mask 0x3 #define LDSTidxI_Z_bits 24 #define LDSTidxI_Z_mask 0x1 #define LDSTidxI_W_bits 25 #define LDSTidxI_W_mask 0x1 #define LDSTidxI_code_bits 26 #define LDSTidxI_code_mask 0x3f #define init_LDSTidxI \ { \ LDSTidxI_opcode, \ LDSTidxI_offset_bits, LDSTidxI_offset_mask, \ LDSTidxI_reg_bits, LDSTidxI_reg_mask, \ LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \ LDSTidxI_sz_bits, LDSTidxI_sz_mask, \ LDSTidxI_Z_bits, LDSTidxI_Z_mask, \ LDSTidxI_W_bits, LDSTidxI_W_mask, \ LDSTidxI_code_bits, LDSTidxI_code_mask \ }; /* LDST +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_ptr; int mask_ptr; int bits_Z; int mask_Z; int bits_aop; int mask_aop; int bits_W; int mask_W; int bits_sz; int mask_sz; int bits_code; int mask_code; } LDST; #define LDST_opcode 0x9000 #define LDST_reg_bits 0 #define LDST_reg_mask 0x7 #define LDST_ptr_bits 3 #define LDST_ptr_mask 0x7 #define LDST_Z_bits 6 #define LDST_Z_mask 0x1 #define LDST_aop_bits 7 #define LDST_aop_mask 0x3 #define LDST_W_bits 9 #define LDST_W_mask 0x1 #define LDST_sz_bits 10 #define LDST_sz_mask 0x3 #define LDST_code_bits 12 #define LDST_code_mask 0xf #define init_LDST \ { \ LDST_opcode, \ LDST_reg_bits, LDST_reg_mask, \ LDST_ptr_bits, LDST_ptr_mask, \ LDST_Z_bits, LDST_Z_mask, \ LDST_aop_bits, LDST_aop_mask, \ LDST_W_bits, LDST_W_mask, \ LDST_sz_bits, LDST_sz_mask, \ LDST_code_bits, LDST_code_mask \ }; /* LDSTii +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_ptr; int mask_ptr; int bits_offset; int mask_offset; int bits_op; int mask_op; int bits_W; int mask_W; int bits_code; int mask_code; } LDSTii; #define LDSTii_opcode 0xa000 #define LDSTii_reg_bit 0 #define LDSTii_reg_mask 0x7 #define LDSTii_ptr_bit 3 #define LDSTii_ptr_mask 0x7 #define LDSTii_offset_bit 6 #define LDSTii_offset_mask 0xf #define LDSTii_op_bit 10 #define LDSTii_op_mask 0x3 #define LDSTii_W_bit 12 #define LDSTii_W_mask 0x1 #define LDSTii_code_bit 13 #define LDSTii_code_mask 0x7 #define init_LDSTii \ { \ LDSTii_opcode, \ LDSTii_reg_bit, LDSTii_reg_mask, \ LDSTii_ptr_bit, LDSTii_ptr_mask, \ LDSTii_offset_bit, LDSTii_offset_mask, \ LDSTii_op_bit, LDSTii_op_mask, \ LDSTii_W_bit, LDSTii_W_mask, \ LDSTii_code_bit, LDSTii_code_mask \ }; /* LDSTiiFP +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_offset; int mask_offset; int bits_W; int mask_W; int bits_code; int mask_code; } LDSTiiFP; #define LDSTiiFP_opcode 0xb800 #define LDSTiiFP_reg_bits 0 #define LDSTiiFP_reg_mask 0xf #define LDSTiiFP_offset_bits 4 #define LDSTiiFP_offset_mask 0x1f #define LDSTiiFP_W_bits 9 #define LDSTiiFP_W_mask 0x1 #define LDSTiiFP_code_bits 10 #define LDSTiiFP_code_mask 0x3f #define init_LDSTiiFP \ { \ LDSTiiFP_opcode, \ LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \ LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \ LDSTiiFP_W_bits, LDSTiiFP_W_mask, \ LDSTiiFP_code_bits, LDSTiiFP_code_mask \ }; /* dspLDST +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_i; int mask_i; int bits_m; int mask_m; int bits_aop; int mask_aop; int bits_W; int mask_W; int bits_code; int mask_code; } DspLDST; #define DspLDST_opcode 0x9c00 #define DspLDST_reg_bits 0 #define DspLDST_reg_mask 0x7 #define DspLDST_i_bits 3 #define DspLDST_i_mask 0x3 #define DspLDST_m_bits 5 #define DspLDST_m_mask 0x3 #define DspLDST_aop_bits 7 #define DspLDST_aop_mask 0x3 #define DspLDST_W_bits 9 #define DspLDST_W_mask 0x1 #define DspLDST_code_bits 10 #define DspLDST_code_mask 0x3f #define init_DspLDST \ { \ DspLDST_opcode, \ DspLDST_reg_bits, DspLDST_reg_mask, \ DspLDST_i_bits, DspLDST_i_mask, \ DspLDST_m_bits, DspLDST_m_mask, \ DspLDST_aop_bits, DspLDST_aop_mask, \ DspLDST_W_bits, DspLDST_W_mask, \ DspLDST_code_bits, DspLDST_code_mask \ }; /* LDSTpmod +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_ptr; int mask_ptr; int bits_idx; int mask_idx; int bits_reg; int mask_reg; int bits_aop; int mask_aop; int bits_W; int mask_W; int bits_code; int mask_code; } LDSTpmod; #define LDSTpmod_opcode 0x8000 #define LDSTpmod_ptr_bits 0 #define LDSTpmod_ptr_mask 0x7 #define LDSTpmod_idx_bits 3 #define LDSTpmod_idx_mask 0x7 #define LDSTpmod_reg_bits 6 #define LDSTpmod_reg_mask 0x7 #define LDSTpmod_aop_bits 9 #define LDSTpmod_aop_mask 0x3 #define LDSTpmod_W_bits 11 #define LDSTpmod_W_mask 0x1 #define LDSTpmod_code_bits 12 #define LDSTpmod_code_mask 0xf #define init_LDSTpmod \ { \ LDSTpmod_opcode, \ LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \ LDSTpmod_idx_bits, LDSTpmod_idx_mask, \ LDSTpmod_reg_bits, LDSTpmod_reg_mask, \ LDSTpmod_aop_bits, LDSTpmod_aop_mask, \ LDSTpmod_W_bits, LDSTpmod_W_mask, \ LDSTpmod_code_bits, LDSTpmod_code_mask \ }; //////////////////////////////////////////////////////////////////////////// /* LOGI2op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_dst; int mask_dst; int bits_src; int mask_src; int bits_opc; int mask_opc; int bits_code; int mask_code; } LOGI2op; #define LOGI2op_opcode 0x4800 #define LOGI2op_dst_bits 0 #define LOGI2op_dst_mask 0x7 #define LOGI2op_src_bits 3 #define LOGI2op_src_mask 0x1f #define LOGI2op_opc_bits 8 #define LOGI2op_opc_mask 0x7 #define LOGI2op_code_bits 11 #define LOGI2op_code_mask 0x1f #define init_LOGI2op \ { \ LOGI2op_opcode, \ LOGI2op_dst_bits, LOGI2op_dst_mask, \ LOGI2op_src_bits, LOGI2op_src_mask, \ LOGI2op_opc_bits, LOGI2op_opc_mask, \ LOGI2op_code_bits, LOGI2op_code_mask \ }; /* ALU2op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_dst; int mask_dst; int bits_src; int mask_src; int bits_opc; int mask_opc; int bits_code; int mask_code; } ALU2op; #define ALU2op_opcode 0x4000 #define ALU2op_dst_bits 0 #define ALU2op_dst_mask 0x7 #define ALU2op_src_bits 3 #define ALU2op_src_mask 0x7 #define ALU2op_opc_bits 6 #define ALU2op_opc_mask 0xf #define ALU2op_code_bits 10 #define ALU2op_code_mask 0x3f #define init_ALU2op \ { \ ALU2op_opcode, \ ALU2op_dst_bits, ALU2op_dst_mask, \ ALU2op_src_bits, ALU2op_src_mask, \ ALU2op_opc_bits, ALU2op_opc_mask, \ ALU2op_code_bits, ALU2op_code_mask \ }; /* BRCC +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_offset; int mask_offset; int bits_B; int mask_B; int bits_T; int mask_T; int bits_code; int mask_code; } BRCC; #define BRCC_opcode 0x1000 #define BRCC_offset_bits 0 #define BRCC_offset_mask 0x3ff #define BRCC_B_bits 10 #define BRCC_B_mask 0x1 #define BRCC_T_bits 11 #define BRCC_T_mask 0x1 #define BRCC_code_bits 12 #define BRCC_code_mask 0xf #define init_BRCC \ { \ BRCC_opcode, \ BRCC_offset_bits, BRCC_offset_mask, \ BRCC_B_bits, BRCC_B_mask, \ BRCC_T_bits, BRCC_T_mask, \ BRCC_code_bits, BRCC_code_mask \ }; /* UJUMP +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 1 | 0 |.offset........................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_offset; int mask_offset; int bits_code; int mask_code; } UJump; #define UJump_opcode 0x2000 #define UJump_offset_bits 0 #define UJump_offset_mask 0xfff #define UJump_code_bits 12 #define UJump_code_mask 0xf #define init_UJump \ { \ UJump_opcode, \ UJump_offset_bits, UJump_offset_mask, \ UJump_code_bits, UJump_code_mask \ }; /* ProgCtrl +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_poprnd; int mask_poprnd; int bits_prgfunc; int mask_prgfunc; int bits_code; int mask_code; } ProgCtrl; #define ProgCtrl_opcode 0x0000 #define ProgCtrl_poprnd_bits 0 #define ProgCtrl_poprnd_mask 0xf #define ProgCtrl_prgfunc_bits 4 #define ProgCtrl_prgfunc_mask 0xf #define ProgCtrl_code_bits 8 #define ProgCtrl_code_mask 0xff #define init_ProgCtrl \ { \ ProgCtrl_opcode, \ ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \ ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \ ProgCtrl_code_bits, ProgCtrl_code_mask \ }; /* CALLa +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| |.lsw...........................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_addr; int mask_addr; int bits_S; int mask_S; int bits_code; int mask_code; } CALLa; #define CALLa_opcode 0xe2000000 #define CALLa_addr_bits 0 #define CALLa_addr_mask 0xffffff #define CALLa_S_bits 24 #define CALLa_S_mask 0x1 #define CALLa_code_bits 25 #define CALLa_code_mask 0x7f #define init_CALLa \ { \ CALLa_opcode, \ CALLa_addr_bits, CALLa_addr_mask, \ CALLa_S_bits, CALLa_S_mask, \ CALLa_code_bits, CALLa_code_mask \ }; /* pseudoDEBUG +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_grp; int mask_grp; int bits_fn; int mask_fn; int bits_code; int mask_code; } PseudoDbg; #define PseudoDbg_opcode 0xf800 #define PseudoDbg_reg_bits 0 #define PseudoDbg_reg_mask 0x7 #define PseudoDbg_grp_bits 3 #define PseudoDbg_grp_mask 0x7 #define PseudoDbg_fn_bits 6 #define PseudoDbg_fn_mask 0x3 #define PseudoDbg_code_bits 8 #define PseudoDbg_code_mask 0xff #define init_PseudoDbg \ { \ PseudoDbg_opcode, \ PseudoDbg_reg_bits, PseudoDbg_reg_mask, \ PseudoDbg_grp_bits, PseudoDbg_grp_mask, \ PseudoDbg_fn_bits, PseudoDbg_fn_mask, \ PseudoDbg_code_bits, PseudoDbg_code_mask \ }; /* PseudoDbg_assert +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...| |.expected......................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_expected; int mask_expected; int bits_regtest; int mask_regtest; int bits_dbgop; int mask_dbgop; int bits_dontcare; int mask_dontcare; int bits_code; int mask_code; } PseudoDbg_Assert; #define PseudoDbg_Assert_opcode 0xf0000000 #define PseudoDbg_Assert_expected_bits 0 #define PseudoDbg_Assert_expected_mask 0xffff #define PseudoDbg_Assert_regtest_bits 16 #define PseudoDbg_Assert_regtest_mask 0x7 #define PseudoDbg_Assert_dbgop_bits 19 #define PseudoDbg_Assert_dbgop_mask 0x7 #define PseudoDbg_Assert_dontcare_bits 22 #define PseudoDbg_Assert_dontcare_mask 0x1f #define PseudoDbg_Assert_code_bits 27 #define PseudoDbg_Assert_code_mask 0x1f #define init_PseudoDbg_Assert \ { \ PseudoDbg_Assert_opcode, \ PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \ PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \ PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \ PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \ PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \ }; /* CaCTRL +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_op; int mask_op; int bits_a; int mask_a; int bits_code; int mask_code; } CaCTRL; #define CaCTRL_opcode 0x0240 #define CaCTRL_reg_bits 0 #define CaCTRL_reg_mask 0x7 #define CaCTRL_op_bits 3 #define CaCTRL_op_mask 0x3 #define CaCTRL_a_bits 5 #define CaCTRL_a_mask 0x1 #define CaCTRL_code_bits 6 #define CaCTRL_code_mask 0x3fff #define init_CaCTRL \ { \ CaCTRL_opcode, \ CaCTRL_reg_bits, CaCTRL_reg_mask, \ CaCTRL_op_bits, CaCTRL_op_mask, \ CaCTRL_a_bits, CaCTRL_a_mask, \ CaCTRL_code_bits, CaCTRL_code_mask \ }; /* PushPopMultiple +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_pr; int mask_pr; int bits_dr; int mask_dr; int bits_W; int mask_W; int bits_p; int mask_p; int bits_d; int mask_d; int bits_code; int mask_code; } PushPopMultiple; #define PushPopMultiple_opcode 0x0400 #define PushPopMultiple_pr_bits 0 #define PushPopMultiple_pr_mask 0x7 #define PushPopMultiple_dr_bits 3 #define PushPopMultiple_dr_mask 0x7 #define PushPopMultiple_W_bits 6 #define PushPopMultiple_W_mask 0x1 #define PushPopMultiple_p_bits 7 #define PushPopMultiple_p_mask 0x1 #define PushPopMultiple_d_bits 8 #define PushPopMultiple_d_mask 0x1 #define PushPopMultiple_code_bits 8 #define PushPopMultiple_code_mask 0x1 #define init_PushPopMultiple \ { \ PushPopMultiple_opcode, \ PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \ PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \ PushPopMultiple_W_bits, PushPopMultiple_W_mask, \ PushPopMultiple_p_bits, PushPopMultiple_p_mask, \ PushPopMultiple_d_bits, PushPopMultiple_d_mask, \ PushPopMultiple_code_bits, PushPopMultiple_code_mask \ }; /* PushPopReg +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_grp; int mask_grp; int bits_W; int mask_W; int bits_code; int mask_code; } PushPopReg; #define PushPopReg_opcode 0x0100 #define PushPopReg_reg_bits 0 #define PushPopReg_reg_mask 0x7 #define PushPopReg_grp_bits 3 #define PushPopReg_grp_mask 0x7 #define PushPopReg_W_bits 6 #define PushPopReg_W_mask 0x1 #define PushPopReg_code_bits 7 #define PushPopReg_code_mask 0x1ff #define init_PushPopReg \ { \ PushPopReg_opcode, \ PushPopReg_reg_bits, PushPopReg_reg_mask, \ PushPopReg_grp_bits, PushPopReg_grp_mask, \ PushPopReg_W_bits, PushPopReg_W_mask, \ PushPopReg_code_bits, PushPopReg_code_mask, \ }; /* linkage +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| |.framesize.....................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_framesize; int mask_framesize; int bits_R; int mask_R; int bits_code; int mask_code; } Linkage; #define Linkage_opcode 0xe8000000 #define Linkage_framesize_bits 0 #define Linkage_framesize_mask 0xffff #define Linkage_R_bits 16 #define Linkage_R_mask 0x1 #define Linkage_code_bits 17 #define Linkage_code_mask 0x7fff #define init_Linkage \ { \ Linkage_opcode, \ Linkage_framesize_bits, Linkage_framesize_mask, \ Linkage_R_bits, Linkage_R_mask, \ Linkage_code_bits, Linkage_code_mask \ }; /* LoopSetup +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| |.reg...........| - | - |.eoffset...............................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_eoffset; int mask_eoffset; int bits_dontcare; int mask_dontcare; int bits_reg; int mask_reg; int bits_soffset; int mask_soffset; int bits_c; int mask_c; int bits_rop; int mask_rop; int bits_code; int mask_code; } LoopSetup; #define LoopSetup_opcode 0xe0800000 #define LoopSetup_eoffset_bits 0 #define LoopSetup_eoffset_mask 0x3ff #define LoopSetup_dontcare_bits 10 #define LoopSetup_dontcare_mask 0x3 #define LoopSetup_reg_bits 12 #define LoopSetup_reg_mask 0xf #define LoopSetup_soffset_bits 16 #define LoopSetup_soffset_mask 0xf #define LoopSetup_c_bits 20 #define LoopSetup_c_mask 0x1 #define LoopSetup_rop_bits 21 #define LoopSetup_rop_mask 0x3 #define LoopSetup_code_bits 23 #define LoopSetup_code_mask 0x1ff #define init_LoopSetup \ { \ LoopSetup_opcode, \ LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \ LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \ LoopSetup_reg_bits, LoopSetup_reg_mask, \ LoopSetup_soffset_bits, LoopSetup_soffset_mask, \ LoopSetup_c_bits, LoopSetup_c_mask, \ LoopSetup_rop_bits, LoopSetup_rop_mask, \ LoopSetup_code_bits, LoopSetup_code_mask \ }; /* LDIMMhalf +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| |.hword.........................................................| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned int opcode; int bits_hword; int mask_hword; int bits_reg; int mask_reg; int bits_grp; int mask_grp; int bits_S; int mask_S; int bits_H; int mask_H; int bits_Z; int mask_Z; int bits_code; int mask_code; } LDIMMhalf; #define LDIMMhalf_opcode 0xe1000000 #define LDIMMhalf_hword_bits 0 #define LDIMMhalf_hword_mask 0xffff #define LDIMMhalf_reg_bits 16 #define LDIMMhalf_reg_mask 0x7 #define LDIMMhalf_grp_bits 19 #define LDIMMhalf_grp_mask 0x3 #define LDIMMhalf_S_bits 21 #define LDIMMhalf_S_mask 0x1 #define LDIMMhalf_H_bits 22 #define LDIMMhalf_H_mask 0x1 #define LDIMMhalf_Z_bits 23 #define LDIMMhalf_Z_mask 0x1 #define LDIMMhalf_code_bits 24 #define LDIMMhalf_code_mask 0xff #define init_LDIMMhalf \ { \ LDIMMhalf_opcode, \ LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \ LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \ LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \ LDIMMhalf_S_bits, LDIMMhalf_S_mask, \ LDIMMhalf_H_bits, LDIMMhalf_H_mask, \ LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \ LDIMMhalf_code_bits, LDIMMhalf_code_mask \ }; /* CC2dreg +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_reg; int mask_reg; int bits_op; int mask_op; int bits_code; int mask_code; } CC2dreg; #define CC2dreg_opcode 0x0200 #define CC2dreg_reg_bits 0 #define CC2dreg_reg_mask 0x7 #define CC2dreg_op_bits 3 #define CC2dreg_op_mask 0x3 #define CC2dreg_code_bits 5 #define CC2dreg_code_mask 0x7fff #define init_CC2dreg \ { \ CC2dreg_opcode, \ CC2dreg_reg_bits, CC2dreg_reg_mask, \ CC2dreg_op_bits, CC2dreg_op_mask, \ CC2dreg_code_bits, CC2dreg_code_mask \ }; /* PTR2op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_dst; int mask_dst; int bits_src; int mask_src; int bits_opc; int mask_opc; int bits_code; int mask_code; } PTR2op; #define PTR2op_opcode 0x4400 #define PTR2op_dst_bits 0 #define PTR2op_dst_mask 0x7 #define PTR2op_src_bits 3 #define PTR2op_src_mask 0x7 #define PTR2op_opc_bits 6 #define PTR2op_opc_mask 0x7 #define PTR2op_code_bits 9 #define PTR2op_code_mask 0x7f #define init_PTR2op \ { \ PTR2op_opcode, \ PTR2op_dst_bits, PTR2op_dst_mask, \ PTR2op_src_bits, PTR2op_src_mask, \ PTR2op_opc_bits, PTR2op_opc_mask, \ PTR2op_code_bits, PTR2op_code_mask \ }; /* COMP3op +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_src0; int mask_src0; int bits_src1; int mask_src1; int bits_dst; int mask_dst; int bits_opc; int mask_opc; int bits_code; int mask_code; } COMP3op; #define COMP3op_opcode 0x5000 #define COMP3op_src0_bits 0 #define COMP3op_src0_mask 0x7 #define COMP3op_src1_bits 3 #define COMP3op_src1_mask 0x7 #define COMP3op_dst_bits 6 #define COMP3op_dst_mask 0x7 #define COMP3op_opc_bits 9 #define COMP3op_opc_mask 0x7 #define COMP3op_code_bits 12 #define COMP3op_code_mask 0xf #define init_COMP3op \ { \ COMP3op_opcode, \ COMP3op_src0_bits, COMP3op_src0_mask, \ COMP3op_src1_bits, COMP3op_src1_mask, \ COMP3op_dst_bits, COMP3op_dst_mask, \ COMP3op_opc_bits, COMP3op_opc_mask, \ COMP3op_code_bits, COMP3op_code_mask \ }; /* ccMV +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_src; int mask_src; int bits_dst; int mask_dst; int bits_s; int mask_s; int bits_d; int mask_d; int bits_T; int mask_T; int bits_code; int mask_code; } CCmv; #define CCmv_opcode 0x0600 #define CCmv_src_bits 0 #define CCmv_src_mask 0x7 #define CCmv_dst_bits 3 #define CCmv_dst_mask 0x7 #define CCmv_s_bits 6 #define CCmv_s_mask 0x1 #define CCmv_d_bits 7 #define CCmv_d_mask 0x1 #define CCmv_T_bits 8 #define CCmv_T_mask 0x1 #define CCmv_code_bits 9 #define CCmv_code_mask 0x7f #define init_CCmv \ { \ CCmv_opcode, \ CCmv_src_bits, CCmv_src_mask, \ CCmv_dst_bits, CCmv_dst_mask, \ CCmv_s_bits, CCmv_s_mask, \ CCmv_d_bits, CCmv_d_mask, \ CCmv_T_bits, CCmv_T_mask, \ CCmv_code_bits, CCmv_code_mask \ }; /* CCflag +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_x; int mask_x; int bits_y; int mask_y; int bits_G; int mask_G; int bits_opc; int mask_opc; int bits_I; int mask_I; int bits_code; int mask_code; } CCflag; #define CCflag_opcode 0x0800 #define CCflag_x_bits 0 #define CCflag_x_mask 0x7 #define CCflag_y_bits 3 #define CCflag_y_mask 0x7 #define CCflag_G_bits 6 #define CCflag_G_mask 0x1 #define CCflag_opc_bits 7 #define CCflag_opc_mask 0x7 #define CCflag_I_bits 10 #define CCflag_I_mask 0x1 #define CCflag_code_bits 11 #define CCflag_code_mask 0x1f #define init_CCflag \ { \ CCflag_opcode, \ CCflag_x_bits, CCflag_x_mask, \ CCflag_y_bits, CCflag_y_mask, \ CCflag_G_bits, CCflag_G_mask, \ CCflag_opc_bits, CCflag_opc_mask, \ CCflag_I_bits, CCflag_I_mask, \ CCflag_code_bits, CCflag_code_mask, \ }; /* CC2stat +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_cbit; int mask_cbit; int bits_op; int mask_op; int bits_D; int mask_D; int bits_code; int mask_code; } CC2stat; #define CC2stat_opcode 0x0300 #define CC2stat_cbit_bits 0 #define CC2stat_cbit_mask 0x1f #define CC2stat_op_bits 5 #define CC2stat_op_mask 0x3 #define CC2stat_D_bits 7 #define CC2stat_D_mask 0x1 #define CC2stat_code_bits 8 #define CC2stat_code_mask 0xff #define init_CC2stat \ { \ CC2stat_opcode, \ CC2stat_cbit_bits, CC2stat_cbit_mask, \ CC2stat_op_bits, CC2stat_op_mask, \ CC2stat_D_bits, CC2stat_D_mask, \ CC2stat_code_bits, CC2stat_code_mask \ }; /* REGMV +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_src; int mask_src; int bits_dst; int mask_dst; int bits_gs; int mask_gs; int bits_gd; int mask_gd; int bits_code; int mask_code; } RegMv; #define RegMv_opcode 0x3000 #define RegMv_src_bits 0 #define RegMv_src_mask 0x7 #define RegMv_dst_bits 3 #define RegMv_dst_mask 0x7 #define RegMv_gs_bits 6 #define RegMv_gs_mask 0x7 #define RegMv_gd_bits 9 #define RegMv_gd_mask 0x7 #define RegMv_code_bits 12 #define RegMv_code_mask 0xf #define init_RegMv \ { \ RegMv_opcode, \ RegMv_src_bits, RegMv_src_mask, \ RegMv_dst_bits, RegMv_dst_mask, \ RegMv_gs_bits, RegMv_gs_mask, \ RegMv_gd_bits, RegMv_gd_mask, \ RegMv_code_bits, RegMv_code_mask \ }; /* COMPI2opD +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_dst; int mask_dst; int bits_src; int mask_src; int bits_op; int mask_op; int bits_code; int mask_code; } COMPI2opD; #define COMPI2opD_opcode 0x6000 #define COMPI2opD_dst_bits 0 #define COMPI2opD_dst_mask 0x7 #define COMPI2opD_src_bits 3 #define COMPI2opD_src_mask 0x7f #define COMPI2opD_op_bits 10 #define COMPI2opD_op_mask 0x1 #define COMPI2opD_code_bits 11 #define COMPI2opD_code_mask 0x1f #define init_COMPI2opD \ { \ COMPI2opD_opcode, \ COMPI2opD_dst_bits, COMPI2opD_dst_mask, \ COMPI2opD_src_bits, COMPI2opD_src_mask, \ COMPI2opD_op_bits, COMPI2opD_op_mask, \ COMPI2opD_code_bits, COMPI2opD_code_mask \ }; /* COMPI2opP +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef COMPI2opD COMPI2opP; #define COMPI2opP_opcode 0x6800 #define COMPI2opP_dst_bits 0 #define COMPI2opP_dst_mask 0x7 #define COMPI2opP_src_bits 3 #define COMPI2opP_src_mask 0x7f #define COMPI2opP_op_bits 10 #define COMPI2opP_op_mask 0x1 #define COMPI2opP_code_bits 11 #define COMPI2opP_code_mask 0x1f #define init_COMPI2opP \ { \ COMPI2opP_opcode, \ COMPI2opP_dst_bits, COMPI2opP_dst_mask, \ COMPI2opP_src_bits, COMPI2opP_src_mask, \ COMPI2opP_op_bits, COMPI2opP_op_mask, \ COMPI2opP_code_bits, COMPI2opP_code_mask \ }; /* dagMODim +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_i; int mask_i; int bits_m; int mask_m; int bits_op; int mask_op; int bits_code2; int mask_code2; int bits_br; int mask_br; int bits_code; int mask_code; } DagMODim; #define DagMODim_opcode 0x9e60 #define DagMODim_i_bits 0 #define DagMODim_i_mask 0x3 #define DagMODim_m_bits 2 #define DagMODim_m_mask 0x3 #define DagMODim_op_bits 4 #define DagMODim_op_mask 0x1 #define DagMODim_code2_bits 5 #define DagMODim_code2_mask 0x3 #define DagMODim_br_bits 7 #define DagMODim_br_mask 0x1 #define DagMODim_code_bits 8 #define DagMODim_code_mask 0xff #define init_DagMODim \ { \ DagMODim_opcode, \ DagMODim_i_bits, DagMODim_i_mask, \ DagMODim_m_bits, DagMODim_m_mask, \ DagMODim_op_bits, DagMODim_op_mask, \ DagMODim_code2_bits, DagMODim_code2_mask, \ DagMODim_br_bits, DagMODim_br_mask, \ DagMODim_code_bits, DagMODim_code_mask \ }; /* dagMODik +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ typedef struct { unsigned short opcode; int bits_i; int mask_i; int bits_op; int mask_op; int bits_code; int mask_code; } DagMODik; #define DagMODik_opcode 0x9f60 #define DagMODik_i_bits 0 #define DagMODik_i_mask 0x3 #define DagMODik_op_bits 2 #define DagMODik_op_mask 0x3 #define DagMODik_code_bits 3 #define DagMODik_code_mask 0xfff #define init_DagMODik \ { \ DagMODik_opcode, \ DagMODik_i_bits, DagMODik_i_mask, \ DagMODik_op_bits, DagMODik_op_mask, \ DagMODik_code_bits, DagMODik_code_mask \ }; #endif //BFIN_OPCODES_H_HD9837U0U9I27E902702DYHCXH2D79218D701D ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/mach.h������������������������������������������������������������0000644�0001750�0000144�00000001001�10541455476�016445� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef MACH_H #define MACH_H #include "types.h" typedef struct mach { bu8 (*io_read_byte) (bu32 addr); bu16 (*io_read_word) (bu32 addr); bu32 (*io_read_long) (bu32 addr); void (*io_write_byte) (bu32 addr, bu8 v); void (*io_write_word) (bu32 addr, bu16 v); void (*io_write_long) (bu32 addr, bu32 v); void (*io_do_cycle) (void); void (*clear_int) (bu32 irq); void (*set_int) (bu32 irq); void (*disable_int) (); void (*enable_int) (); void (*sti) (bu32 dreg); void (*cli) (bu32 dreg); } mach_t; #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/sim-bfin.h��������������������������������������������������������0000755�0001750�0000144�00000005124�10541455476�017256� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* Common target dependent code for GDB on BFIN systems. Copyright 2002, 2003 Free Software Foundation, Inc. This file is part of GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* Register numbers of various important registers. Note that some of these values are "real" register numbers, and correspond to the general registers of the machine, and some are "phony" register numbers which are too large to be actual register numbers as far as the user is concerned but do serve to get the desired values when passed to read_register. */ enum gdb_regnum { BFIN_SYSCFG_REGNUM = 0, //BFIN_ORIGR0_REGNUM, BFIN_R0_REGNUM, BFIN_R1_REGNUM, BFIN_R2_REGNUM, BFIN_R3_REGNUM, BFIN_R4_REGNUM, BFIN_R5_REGNUM, BFIN_R6_REGNUM, BFIN_R7_REGNUM, BFIN_P0_REGNUM, BFIN_P1_REGNUM, BFIN_P2_REGNUM, BFIN_P3_REGNUM, BFIN_P4_REGNUM, BFIN_P5_REGNUM, BFIN_FP_REGNUM, BFIN_SP_REGNUM, BFIN_I0_REGNUM, BFIN_I1_REGNUM, BFIN_I2_REGNUM, BFIN_I3_REGNUM, BFIN_M0_REGNUM, BFIN_M1_REGNUM, BFIN_M2_REGNUM, BFIN_M3_REGNUM, BFIN_L0_REGNUM, BFIN_L1_REGNUM, BFIN_L2_REGNUM, BFIN_L3_REGNUM, BFIN_B0_REGNUM, BFIN_B1_REGNUM, /* START MODIFIER REGISTER */ BFIN_B2_REGNUM, /* END MODIFIER REGISTER */ BFIN_B3_REGNUM, BFIN_A0_DOT_X_REGNUM, BFIN_AO_DOT_W_REGNUM, BFIN_A1_DOT_X_REGNUM, BFIN_A1_DOT_W_REGNUM, BFIN_LC0_REGNUM, BFIN_LC1_REGNUM, BFIN_LT0_REGNUM, BFIN_LT1_REGNUM, BFIN_LB0_REGNUM, BFIN_LB1_REGNUM, BFIN_ASTAT_REGNUM, BFIN_RESERVED_REGNUM, BFIN_RETS_REGNUM, /* Subroutine address register */ BFIN_PC_REGNUM, /*actually RETI pc will be in ORIG_PC */ BFIN_RETX_REGNUM, BFIN_RETN_REGNUM, BFIN_RETE_REGNUM, BFIN_SEQSTAT_REGNUM, BFIN_IPEND_REGNUM, /* Subroutine address register */ BFIN_ORIGPC_REGNUM, /* Subroutine address register */ BFIN_EXTRA1, /* Extra "registers" for hacks 1. address of .text */ BFIN_EXTRA2, BFIN_EXTRA3, // LAST ENTRY SHOULD NOT BE CHANGED BFIN_NUM_REGS /* 0 index, so this entry is size */ }; ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/iomem.h�����������������������������������������������������������0000644�0001750�0000144�00000000612�10541455476�016652� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef __BFIN_IOMEM_H #define __BFIN_IOMEM_H #include "types.h" void put_byte (unsigned char *memory, bu32 addr, bu8 v); void put_word (unsigned char *memory, bu32 addr, bu16 v); void put_long (unsigned char *memory, bu32 addr, bu32 v); bu8 get_byte (unsigned char *memory, bu32 addr); bu16 get_word (unsigned char *memory, bu32 addr); bu32 get_long (unsigned char *memory, bu32 addr); #endif ����������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/dma.h�������������������������������������������������������������0000644�0001750�0000144�00000002577�10571721153�016310� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* dma.h - necessary arm definition for skyeye debugger Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __DMA_H__ #define __DMA_H__ #define BF533_MDMA_D0 8 #define BF533_MDMA_S0 9 #define BF533_MDMA_D1 10 #define BF533_MDMA_S1 11 #define BF537_MDMA_D0 0xc #define BF537_MDMA_S0 0xd #define BF537_MDMA_D1 0xe #define BF537_MDMA_S1 0xf #define START_ADDR 0x1 #define DMA_CONFIG 0x2 #define X_COUNT 0x4 #define X_MODIFY 0x5 #define Y_COUNT 0x6 #define Y_MODIFY 0x7 #endif ���������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/bfin_arch_interface.c���������������������������������������������0000644�0001750�0000144�00000016726�11006337514�021474� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* THIS SOFTWARE IS NOT COPYRIGHTED Cygnus offers the following for use in the public domain. Cygnus makes no warranty with regard to the software or it's performance and the user accepts the software "AS IS" with all faults. CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ /* * written by Michael.Kang */ #ifdef __MINGW32__ #include <windows.h> #endif #include <signal.h> #ifdef HAVE_UNISTD_H #include <unistd.h> #endif #include "bfin-sim.h" #include "mem_map.h" #include "skyeye_types.h" #include "skyeye_config.h" //#include "bfin_defs.h" #define NONCACHE 0 saved_state_type saved_state; static char * arch_name = "blackfin"; static void sim_size () { if (!saved_state.memory) saved_state.memory = (unsigned char *) malloc (SDRAM_SIZE); if (!saved_state.dsram) saved_state.dsram = (unsigned char *) malloc (DSRAM_SIZE); if (!saved_state.isram) saved_state.isram = (unsigned char *) malloc (ISRAM_SIZE); // PSW 061606 if (!saved_state.ssram) saved_state.ssram = (unsigned char *) malloc (SSRAM_SIZE); if (!saved_state.memory) { fprintf (stderr, "Not enough VM for simulation of RAM\n"); } } void bfin_init_state () { /* mach_t *p_mach; printf ("begin init emulator()\n"); p_mach = malloc (sizeof (mach_t)); init_bf533_mach (p_mach);*/ /*malloc memory */ sim_size (); /*mach init */ skyeye_config.mach->mach_init (&saved_state, skyeye_config.mach); //saved_state.p_mach = p_mach; } void bfin_reset_state () { /*fixme */ saved_state.usp = 0x1000000; SPREG = saved_state.usp; saved_state.pc = 0x0; } /* Set by an instruction emulation function if we performed a jump. */ int did_jump; int raise_flag ; static tmp_flag = 0; /* Execute a single instruction. */ static void bfin_step_once () { OLDERPCREG = OLDPCREG; OLDPCREG = PCREG; did_jump = 0; interp_insn_bfin (PCREG); /* @@@ Not sure how the hardware really behaves when the last insn of a loop is a jump. */ if (!did_jump) { if (LC1REG && OLDPCREG == LB1REG && --LC1REG) PCREG = LT1REG; else if (LC0REG && OLDPCREG == LB0REG && --LC0REG) PCREG = LT0REG; } if(raise_flag > 0) raise_flag = 0; else skyeye_config.mach->mach_io_do_cycle (&saved_state); } static void bfin_set_pc (WORD addr) { PCREG = (bu32) addr; } static WORD bfin_get_pc(){ return PCREG; } cpu_config_t bfin_cpu[] = { {"bf533", "bf533", 0xffffffff, 0xfffffff0, NONCACHE} , {NULL,NULL,0,0,0} }; //chy 2006-04-15 static int bfin_ICE_write_byte (WORD addr, uint8_t v) { put_byte (saved_state.memory, addr, (bu8) v); return 0; } static int bfin_ICE_read_byte(WORD addr, uint8_t * pv){ *pv = (unsigned char)get_byte(saved_state.memory, addr); return 0; } static int bfin_parse_cpu (cpu_config_t * cpu, const char *param[]) { } extern void bf533_mach_init(void * state, machine_config_t * mach); extern void bf537_mach_init(void * state, machine_config_t * mach); machine_config_t bfin_machines[] = { {"bf533", bf533_mach_init, NULL, NULL, NULL}, {"bf537", bf537_mach_init, NULL, NULL, NULL}, }; static int bfin_parse_mach (machine_config_t * cpu, const char *params[]) { int i; for (i = 0; i < (sizeof (bfin_machines) / sizeof (machine_config_t)); i++) { if (!strncmp (params[0], bfin_machines[i].machine_name, MAX_PARAM_NAME)) { skyeye_config.mach = &bfin_machines[i]; SKYEYE_INFO ("mach info: name %s, mach_init addr %p\n", skyeye_config.mach->machine_name, skyeye_config.mach->mach_init); return 0; } } SKYEYE_ERR ("Error: Unkonw mach name \"%s\"\n", params[0]); return -1; } static int bfin_parse_mem(int num_params, const char* params[]) { #if 0 char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, num; bfin_mem_config_t *mc = &bfin_mem_config; bfin_mem_bank_t *mb = mc->mem_banks; mc->bank_num = mc->current_num++; num = mc->current_num - 1; /*mem_banks should begin from 0. */ mb[num].filename[0] = '\0'; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: mem_bank %d has wrong parameter \"%s\".\n", num, name); if (!strncmp ("map", name, strlen (name))) { if (!strncmp ("M", value, strlen (value))) { mb[num].read_byte = bfin_real_read_byte; mb[num].write_byte = bfin_real_write_byte; mb[num].read_halfword = bfin_real_read_halfword; mb[num].write_halfword = bfin_real_write_halfword; mb[num].read_word = bfin_real_read_word; mb[num].write_word = bfin_real_write_word; mb[num].read_doubleword = bfin_real_read_doubleword; mb[num].write_doubleword = bfin_real_write_doubleword; mb[num].type = MEMTYPE_RAM; } else if (!strncmp ("I", value, strlen (value))) { mb[num].read_byte = bfin_io_read_byte; mb[num].write_byte = bfin_io_write_byte; mb[num].read_halfword = bfin_io_read_halfword; mb[num].write_halfword = bfin_io_write_halfword; mb[num].read_word = bfin_io_read_word; mb[num].write_word = bfin_io_write_word; mb[num].read_doubleword = bfin_io_read_doubleword; mb[num].write_doubleword = bfin_io_write_doubleword; mb[num].type = MEMTYPE_IO; /*ywc 2005-03-30 */ } else if (!strncmp ("F", value, strlen (value))) { mb[num].read_byte = bfin_flash_read_byte; mb[num].write_byte = bfin_flash_write_byte; mb[num].read_halfword = bfin_flash_read_halfword; mb[num].write_halfword = bfin_flash_write_halfword; mb[num].read_word = bfin_flash_read_word; mb[num].write_word = bfin_flash_write_word; mb[num].read_doubleword = bfin_flash_read_doubleword; mb[num].write_doubleword = bfin_flash_write_doubleword; mb[num].type = MEMTYPE_FLASH; } else { SKYEYE_ERR ("Error: mem_bank %d \"%s\" parameter has wrong value \"%s\"\n", num, name, value); } } else if (!strncmp ("type", name, strlen (name))) { //chy 2003-09-21: process type if (!strncmp ("R", value, strlen (value))) { if (mb[num].type == MEMTYPE_RAM) mb[num].type = MEMTYPE_ROM; mb[num].write_byte = bfin_warn_write_byte; mb[num].write_halfword = bfin_warn_write_halfword; mb[num].write_word = bfin_warn_write_word; } } else if (!strncmp ("addr", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].addr = strtoul (value, NULL, 16); else mb[num].addr = strtoul (value, NULL, 10); } else if (!strncmp ("size", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].len = strtoul (value, NULL, 16); else mb[num].len = strtoul (value, NULL, 10); } else if (!strncmp ("file", name, strlen (name))) { strncpy (mb[num].filename, value, strlen (value) + 1); } else if (!strncmp ("boot", name, strlen (name))) { /*this must be the last parameter. */ if (!strncmp ("yes", value, strlen (value))) skyeye_config.start_address = mb[num].addr; } else { SKYEYE_ERR ("Error: mem_bank %d has unknow parameter \"%s\".\n", num, name); } } #endif return 0; } void init_bfin_arch () { static arch_config_t bfin_arch; bfin_arch.arch_name = arch_name; bfin_arch.init = bfin_init_state; bfin_arch.reset = bfin_reset_state; bfin_arch.step_once = bfin_step_once; bfin_arch.set_pc = bfin_set_pc; bfin_arch.get_pc = bfin_get_pc; bfin_arch.ICE_write_byte = bfin_ICE_write_byte; bfin_arch.ICE_read_byte = bfin_ICE_read_byte; bfin_arch.parse_cpu = bfin_parse_cpu; bfin_arch.parse_mach = bfin_parse_mach; bfin_arch.parse_mem = bfin_parse_mem; register_arch (&bfin_arch); } ������������������������������������������skyeye-1.2.5_REL/arch/bfin/common/bfin-sim.h��������������������������������������������������������0000644�0001750�0000144�00000005371�10642320132�017235� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef __BFIN_SIM_H_ #define __BFIN_SIM_H_ #include "types.h" #include <stdio.h> enum { EMU_MODE = 1, SUPER_MODE, USR_MODE }; #define MAXBANKS 5 typedef struct { bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4]; bu64 a0, a1; bu32 lt[2], lc[2], lb[2]; int ac0, ac0_copy, ac1, an, aq; int av0, av0s, av1, av1s, az, cc, v, v_copy, vs; int v_internal; bu32 syscfg; bu32 usp, old_sp; bu32 pc, rets, reti, retx, retn, rete; int mode; bu32 astat, seqstat; bu32 oldpc; bu32 olderpc; unsigned char *insn_end; int ticks; int stalls; int memstalls; int cycles; int insts; int prevlock; int thislock; int exception; int end_of_registers; int msize; #define PROFILE_FREQ 1 #define PROFILE_SHIFT 2 unsigned short *profile_hist; unsigned char *memory; unsigned char *dsram; unsigned char *isram; unsigned char *ssram; //PSW 061606 added scratchpad // struct mem_bank *bank; int xyram_select, xram_start, yram_start; unsigned char *xmem; unsigned char *ymem; unsigned char *xmem_offset; unsigned char *ymem_offset; unsigned int bfd_mach; //mach_t *p_mach; void (*sti)(bu32 * dreg); void (*cli)(bu32 * dreg); void (*disable_int)(); void (*enable_int)(); void (*clear_int)(int); void (*set_int)(int); } saved_state_type; extern saved_state_type saved_state; #define DREG(x) saved_state.dpregs[x] #define DPREG(x) saved_state.dpregs[x] #define GREG(x,i) DPREG ((x) | (i << 3)) #define PREG(x) saved_state.dpregs[x + 8] #define SPREG (PREG(6)) #define FPREG (PREG(7)) #define USPREG saved_state.usp #define RETIREG saved_state.reti #define IREG(x) saved_state.iregs[x] #define LREG(x) saved_state.lregs[x] #define MREG(x) saved_state.mregs[x] #define BREG(x) saved_state.bregs[x] #define A0REG saved_state.a0 #define A0XREG ((bu32 *)(&saved_state.a0))[0] #define A0WREG ((bu32 *)(&saved_state.a0))[1] #define A1REG saved_state.a1 #define A1XREG ((bu32 *)(&saved_state.a1))[0] #define A1WREG ((bu32 *)(&saved_state.a1))[1] #define CCREG saved_state.cc #define PCREG saved_state.pc #define LC0REG saved_state.lc[0] #define LT0REG saved_state.lt[0] #define LB0REG saved_state.lb[0] #define LC1REG saved_state.lc[1] #define LT1REG saved_state.lt[1] #define LB1REG saved_state.lb[1] #define RETSREG saved_state.rets #define RETIREG saved_state.reti #define RETNREG saved_state.retn #define RETXREG saved_state.retx #define RETEREG saved_state.rete #define PCREG saved_state.pc #define USPREG saved_state.usp #define ASTATREG saved_state.astat #define SEQSTATREG saved_state.seqstat #define OLDPCREG saved_state.oldpc #define OLDERPCREG saved_state.olderpc #define OLDSPREG saved_state.old_sp #define MODE saved_state.mode #define AQFLAG saved_state.aq #define AZFLAG saved_state.az extern int did_jump; typedef struct { } bfin_sim_info; #endif �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/mach/��������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014771� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/mach/bf537_io.c����������������������������������������������������������0000644�0001750�0000144�00000103632�10642350651�016471� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* bf537_io.c - implementation of bf537 simulation. Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option.) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "bfin-sim.h" #include "types.h" #include "bf533_io.h" #include "dma.h" #include "bf533_irq.h" #include "skyeye_config.h" #include <stdio.h> #include <fcntl.h> #include <signal.h> extern void dma_mem_cpy (unsigned int src, unsigned int dst, int size); /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" #define DEBUG 0 #if DEBUG #define DBG_PRINT(a...) printf(##a) #else #define DBG_PRINT(a...) #endif #define IO_ERR {printf("\n%s bf537_io.error!!!addr=0x%x,pc=0x%x\n",__FUNCTION__,addr,PCREG);raise (SIGILL);} #define MALLOC_ERR {printf("\n%s malloc error!\n",__FUNCTION__);skyeye_exit(-1);} #define UART0_RX_IRQ 11 #define UART0_TX_IRQ 12 /*declare the device bf537_io.functbf537_io.s*/ declare_device (uart) declare_device (wd) declare_device (core_int) declare_device (dma) declare_device (dpmc) declare_device (deu) declare_device (ebiu) declare_device (sic) declare_device (l1mem) declare_device (l1dmem) declare_device (rtc) declare_device (tbuf) declare_device (core_timer) declare_device (pf) declare_device (port) declare_device (eth) static void handle_irq (); static void bf537_disable_int (); static void bf537_enable_int (); typedef struct uart { bu16 rbr; bu16 thr; bu16 ier; bu16 iir; bu16 fcr; bu16 lcr; bu16 lsr; bu16 msr; bu16 scr; bu16 dll; bu16 dlh; bu16 gctl; } bf537_uart_t; static int uart_outfd; typedef struct dma_channel { bu32 next_desc_ptr; bu32 start_addr; bu32 x_count; bu32 x_modify; bu32 y_count; bu32 y_modify; bu32 curr_desc_ptr; bu32 curr_addr; bu32 irq_status; bu32 peripheral_map; bu32 curr_x_count; bu32 curr_y_count; } bf537_dma_channel_t; typedef struct l1mem { bu32 reg[L1MEM_IO_SIZE / 4]; } bf537_l1mem_t; typedef struct l1dmem { bu32 reg[L1DMEM_IO_SIZE / 4]; } bf537_l1dmem_t; typedef struct dma { bu16 tc_per; bu16 tc_cnt; bu32 bf537_dma_channel[16][14]; } bf537_dma_t; typedef struct ebiu { bu16 amgctl; bu16 ambctl0; bu16 ambctl1; bu16 sdgctl; bu16 sdbctl; bu16 sdrrc; bu16 sdstat; } bf537_ebiu_t; typedef struct core_int { bu32 evt[16]; bu32 imask; bu32 ipend; bu32 iprio; bu32 ilat; } bf537_core_int_t; typedef struct wd { bu16 ctl; bu32 cnt; bu32 stat; } bf537_wd_t; typedef struct tbuf { bu32 ctrl; bu32 stat; bu32 rix; bu32 rsel; bu32 wix; bu32 wsel; bu32 dbuf[16]; bu32 sbuf[16]; } bf537_tbuf_t; typedef struct deu { bu32 dspid; } bf537_deu_t; typedef struct dpmc { bu16 pll_ctl; bu16 pll_stat; bu16 pll_lockcnt; bu16 vr_ctl; bu16 pll_div; } bf537_dpmc_t; typedef struct sic { bu32 swrst; bu32 syscr; bu32 sic_imask; bu32 sic_iar[4]; bu32 sic_isr; bu32 sic_iwr; } bf537_sic_t; typedef struct rtc { bu32 stat; bu32 ictl; bu32 istat; bu32 swcnt; bu32 alarm; bu32 pren; } bf537_rtc_t; typedef struct core_timer { bu32 tcntl; bu32 tperio; bu32 tscale; bu32 tcount; } bf537_core_timer_t; typedef struct pf { bu32 fio_flag_d; bu32 fio_flag_c; bu32 fio_flag_s; bu32 fio_dir; bu32 fio_polar; bu32 fio_maska_c; bu32 fio_maskb_c; bu32 fio_inen; } bf537_pf_t; typedef struct bf537_port_s{ bu16 portf_fer; bu16 port_mux; }bf537_port_t; typedef struct bf537_eth_s{ bu32 emac_systat; }bf537_eth_t; typedef struct bf537_io { bf537_uart_t uart; /* Receive data register */ bf537_dma_t dma; bf537_ebiu_t ebiu; bf537_core_int_t core_int; bf537_wd_t wd; bf537_deu_t deu; bf537_dpmc_t dpmc; bf537_sic_t sic; bf537_l1mem_t l1mem; bf537_l1dmem_t l1dmem; bf537_rtc_t rtc; bf537_core_timer_t core_timer; bf537_pf_t pf; bf537_tbuf_t tbuf; bf537_port_t port; bf537_eth_t eth; } bf537_io_t; static bf537_io_t bf537_io; /*also be called by raise inst and except*/ static void bf537_set_int (int irq) { if(irq != CORE_TIMER_IRQ & irq != 0) //fprintf(PF,"####################irq=%d,in %s\n",irq,__FUNCTION__); ; //if ((bf537_io.core_int.imask | 0x1f) & (1 << irq)) { //if(irq != CORE_TIMER_IRQ & irq != 0) // fprintf(PF,"####################irq=%d,in %s\n",irq,__FUNCTION__); /*set the corresponding int bit to 1 in ilat */ bf537_io.core_int.ilat |= (1 << irq); //} } static void bf537_clear_int (int irq_no_use) { int irq; //fprintf(PF,"KSDBG:begin in %s,ipend=0x%x,ilat=0x%x,SPREG=0x%x,irq=%d\n",__FUNCTION__, bf537_io.core_int.ipend,bf537_io.core_int.ilat, SPREG, irq); /*fix me, trigger the corresponding int according to some prio check, */ for (irq = 0; irq < 16; irq++) { /* check there is a pending int for clear */ if ((bf537_io.core_int.ipend >> irq) & 0x1) { /*clear the int bit */ bf537_io.core_int.ipend &= ~(1 << irq); /*clear corresponding int in the device */ if (irq == CORE_TIMER_IRQ) { bf537_io.core_timer.tcntl &= ~0x8; } if (bf537_io.core_int.ipend == 0x0) { /*There is no interrupt to handle, switch mode */ //fprintf(PF,"KSDBG:mode switch,SPREG=0x%x,USPREG=0x%x\n",SPREG,USPREG); MODE = USR_MODE; OLDSPREG = SPREG; SPREG = USPREG; } else ; //fprintf(PF,"KSDBG:in super mode,ipend=0x%x,SPREG=0x%x,irq=%d\n",bf537_io.core_int.ipend, SPREG, irq); return; } } //fprintf(PF,"KSDBG:end in %s,ipend=0x%x,SPREG=0x%x,irq=%d\n",__FUNCTION__, bf537_io.core_int.ipend, SPREG, irq); } static void handle_irq () { int irq = 0; if (OLDPCREG < 0x1000) { printf ("in %s,pc=%x,jump to 0x%x,olderpc=0x%x\n", __FUNCTION__, PCREG, OLDPCREG, OLDERPCREG); raise (SIGINT); } /*if global int is disabled,just return */ if (bf537_io.core_int.ipend & 0x10) { return; } /*fix me, trigger the corresponding int according to some prbf537_io.check, */ for (irq = 0; irq < 16; irq++) { if (((bf537_io.core_int.ilat&(bf537_io.core_int.imask|0x1f)) >> irq) & 0x1) { if (irq != CORE_TIMER_IRQ) //fprintf (PF, // "# in %s begin,irq=%d,pc=0x%x,ipend=0x%x,RETI=0x%x\n", // __FUNCTION__, irq, PCREG, bf537_io.core_int.ipend, RETIREG); /*current there is a higher or equal prbf537_io.ity pending int for handle,wait until it finish */ if(bf537_io.core_int.ipend&(~((~0x0) << irq))) return; /* set ipend bit , and clear ilat */ bf537_io.core_int.ilat &= ~(1 << irq); bf537_io.core_int.ipend |= (1 << irq); /*now if did_jump in interp.c is set, the following code is executed twice,maybe it not make something wrong */ if (LC1REG && OLDPCREG == LB1REG && --LC1REG) { //printf("int in the end of loop,PC=%x\n",PCREG); PCREG = LT1REG; } else if (LC0REG && OLDPCREG == LB0REG && --LC0REG) { //printf("int in the end of loop,PC=%x\n",PCREG); PCREG = LT0REG; } /*clear corresponding int in the device */ if (irq == CORE_TIMER_IRQ) { //return; bf537_io.core_timer.tcntl &= ~0x8; // fprintf(PF,"##Timer IRQ:PC=0x%x,\n",PCREG); } else { //fprintf (PF, "## Other IRQ:irq=%d,\n", irq); } /* switch mode */ if (MODE == USR_MODE) { MODE = SUPER_MODE; USPREG = SPREG; SPREG = OLDSPREG; } /*save pc to reti,jump to the corresponding vector */ if (irq == EXCEPT_IRQ) { //fprintf (PF, // "##System Call:PC=0x%x, sys_number=%d,ipend=0x%x\n", // PCREG, PREG (0), // bf537_io.core_int.ipend); saved_state.retx = PCREG; } else { saved_state.reti = PCREG; } PCREG = bf537_io.core_int.evt[irq]; if (irq != CORE_TIMER_IRQ) ; //fprintf (PF, // "## in %s end,irq=%d,pc=0x%x,ipend=0x%x\n", // __FUNCTION__, irq, PCREG, bf537_io.core_int.ipend); /*at the same time , disable global int for protecting reti */ bf537_disable_int (); return; } } } static void bf537_disable_int () { //printf("in %s\n",__FUNCTION__); bf537_io.core_int.ipend |= 0x10; } static void bf537_enable_int () { //printf("in %s\n",__FUNCTION__); bf537_io.core_int.ipend &= ~0x10; } static void bf537_cli (bu32 * dreg) { *dreg = bf537_io.core_int.imask; //printf("cli,%x\n",*dreg); bf537_io.core_int.imask = 0x1f; } static void bf537_sti (bu32 * dreg) { //printf("sti,%x\n",*dreg); bf537_io.core_int.imask = *dreg; } #define BF537_HZ 50 static void bf537_io_do_cycle (void * state) { static int sclk_count = 0; static int timer_count = BF537_HZ; //if (PCREG >= 0x7480048){ // fprintf(PF,"KSDBG:begin,pc=0x%x,insn@pc=0x%x,sp=0x%x,usp=0x%x,ipend=0x%x\n",(PCREG), get_long(saved_state.memory, PCREG), SPREG,USPREG,bf537_io.core_int.ipend); //} sclk_count++; /*if global int is disabled */ /* if(sclk_count == bf537_io.core_timer.tscale+1){ sclk_count = 0; bf537_io.core_timer.tcount--; if(bf537_io.core_timer.tcount == 0){ bf537_set_int(CORE_TIMER_IRQ); bf537_io.core_timer.tcount = bf537_io.core_timer.tperbf537_io.; } } */ if (sclk_count == bf537_io.core_timer.tscale + 1) { sclk_count = 0; timer_count--; if (timer_count == 0) { timer_count = BF537_HZ; /*if previs timer int handle is not finished , this int is lost */ /*If core_timer enabled? */ if ((bf537_io.core_timer.tcntl & 0x2)) { bf537_io.core_timer.tcntl |= 0x8; bf537_set_int (CORE_TIMER_IRQ); } } } if ((bf537_io.sic.sic_imask & 0x1000) && (bf537_io.uart.ier & 0x2)) { //printf("\nUART TX IRQ\n"); bf537_set_int (((bf537_io.sic.sic_iar[1] & 0xf0000) >> 16) + 7); bf537_io.uart.iir = 0x2; bf537_io.sic.sic_isr |= 0x1000; } if (!(bf537_io.uart.lsr & 0x1)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; //printf("\nUART RX IRQ before skyeye_uart_read\n"); if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { //printf ("\nUART RX IRQ,getchar=%c\n",buf); //printf("%c",buf); //putchar(buf); bf537_io.uart.rbr = buf; /*set DR bit in LSR */ bf537_io.uart.lsr |= 0x1; //printf("\nUART RX IRQ getchar\n"); } } if ((bf537_io.sic.sic_imask & 0x800) && (bf537_io.uart.ier & 0x1) && (bf537_io.uart.lsr & 0x1)) { bf537_io.uart.iir = 0x4; bf537_io.sic.sic_isr |= 0x800; bf537_set_int (((bf537_io.sic.sic_iar[1] & 0xf000) >> 12) + 7); } handle_irq (); } static bu8 bf537_io_read_byte (void * p_state, bu32 addr) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { return dma_read_byte (addr); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { return uart_read_byte (addr); } else { IO_ERR; } } } static bu16 bf537_io_read_word (void * state, bu32 addr) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { return dma_read_word (addr); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { return uart_read_word (addr); } else if (addr >= DPMC_IO_START_ADDR && addr < DPMC_IO_END_ADDR) { return dpmc_read_word (addr); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { return ebiu_read_word (addr); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { return rtc_read_word (addr); } else if (addr >= PF_IO_START_ADDR && addr < PF_IO_END_ADDR) { return pf_read_word (addr); } else if (addr >= PORT_IO_START_ADDR && addr <= PORT_IO_END_ADDR){ return port_read_word (addr); } else { IO_ERR; } } } static bu32 bf537_io_read_long (void * state, bu32 addr) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { return dma_read_long (addr); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { return uart_read_long (addr); } else if (addr >= DEU_IO_START_ADDR && addr < DEU_IO_END_ADDR) { return deu_read_long (addr); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { return ebiu_read_long (addr); } else if (addr >= SIC_IO_START_ADDR && addr < SIC_IO_END_ADDR) { return sic_read_long (addr); } else if (addr >= L1MEM_IO_START_ADDR && addr < L1MEM_IO_END_ADDR) { return l1mem_read_long (addr); } else if (addr >= L1DMEM_IO_START_ADDR && addr < L1DMEM_IO_END_ADDR) { return l1dmem_read_long (addr); } else if (addr >= CORE_INT_IO_START_ADDR && addr < CORE_INT_IO_END_ADDR) { return core_int_read_long (addr); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { return rtc_read_long (addr); } else if (addr >= CORE_TIMER_IO_START_ADDR && addr < CORE_TIMER_IO_END_ADDR) { return core_timer_read_long (addr); } else if (addr >= TBUF_IO_START_ADDR && addr < TBUF_IO_END_ADDR) { return tbuf_read_long (addr); } else if (addr >= PORT_IO_START_ADDR && addr <= PORT_IO_END_ADDR){ return port_read_long (addr); } else if(addr >= ETH_IO_START_ADDR && addr <= ETH_IO_END_ADDR){ return eth_read_long (addr); } else { IO_ERR; } } } static void bf537_io_write_byte (void * state, bu32 addr, bu8 v) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { dma_write_byte (addr, v); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { uart_write_byte (addr, v); } else { IO_ERR; } } return; } static void bf537_io_write_word (void * state, bu32 addr, bu16 v) { if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { dma_write_word (addr, v); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { uart_write_word (addr, v); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { ebiu_write_word (addr, v); } else if (addr >= WD_IO_START_ADDR && addr < WD_IO_END_ADDR) { wd_write_word (addr, v); } else if (addr >= DPMC_IO_START_ADDR && addr < DPMC_IO_END_ADDR) { dpmc_write_word (addr, v); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { rtc_write_word (addr, v); } else if (addr >= PF_IO_START_ADDR && addr < PF_IO_END_ADDR) { pf_write_word (addr, v); } else if (addr >= PORT_IO_START_ADDR && addr <= PORT_IO_END_ADDR){ port_write_word (addr, v); } else { IO_ERR; } return; } static void bf537_io_write_long (void * state, bu32 addr, bu32 v) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { dma_write_long (addr, v); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { uart_write_long (addr, v); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { ebiu_write_long (addr, v); } else if (addr >= CORE_INT_IO_START_ADDR && addr < CORE_INT_IO_END_ADDR) { core_int_write_long (addr, v); } else if (addr >= SIC_IO_START_ADDR && addr < SIC_IO_END_ADDR) { sic_write_long (addr, v); } else if (addr >= L1MEM_IO_START_ADDR && addr < L1MEM_IO_END_ADDR) { l1mem_write_long (addr, v); } else if (addr >= L1DMEM_IO_START_ADDR && addr < L1DMEM_IO_END_ADDR) { l1dmem_write_long (addr, v); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { rtc_write_long (addr, v); } else if (addr >= CORE_TIMER_IO_START_ADDR && addr < CORE_TIMER_IO_END_ADDR) { core_timer_write_long (addr, v); } else if (addr >= TBUF_IO_START_ADDR && addr < TBUF_IO_END_ADDR) { tbuf_write_long (addr, v); } else if(addr >= ETH_IO_START_ADDR && addr <= ETH_IO_END_ADDR){ eth_write_long (addr, v); } else { IO_ERR; } } return; } static bu16 uart_read_word (bu32 addr) { bu16 data; //printf("bf537_uart_read,addr=%x\n",addr); bu32 offset = addr - UART_IO_START_ADDR; /* if(offset != 0 && offset != 0x14 && offset != 0xc && offset!=0x4) printf("###############offset=0x%x\n",offset); */ static int read_num = 0; switch (offset) { case 0x0: // RbR if (bf537_io.uart.lcr & 0x80) { data = bf537_io.uart.dlh; } if (read_num == 0) { read_num = 1; return 'k'; } if (read_num == 1) { bf537_io.uart.lsr &= ~0x1; bf537_io.sic.sic_isr &= ~0x800; data = bf537_io.uart.rbr & 0xff; //bf537_io.uart.iir = 0x1; read_num = 0; //fprintf (PF, "*****read rbr=%x,pc=%x,isr=%x\n", data, // PCREG, bf537_io.sic.sic_isr); } break; case 0x4: // ier if (bf537_io.uart.lcr & 0x80) data = bf537_io.uart.dlh; else data = bf537_io.uart.ier; break; case 0x8: // iir data = bf537_io.uart.iir; //printf("read iir=%x,pc=%x\n",data,PCREG); bf537_io.uart.iir = 0x1; break; case 0xc: // lcr data = bf537_io.uart.lcr; break; case 0x10: // MCR data = 0x0; break; case 0x14: // LSR data = bf537_io.uart.lsr; //printf("read lsr=%x,pc=%x\n",data,PCREG); break; case 0x1c: // SCR data = bf537_io.uart.lcr; break; case 0x24: // SCR data = bf537_io.uart.gctl; break; default: IO_ERR; DBG_PRINT ("uart_read(%s=0x%08x)\n", "uart_reg", addr); break; } return (data); } static void uart_write_word (bu32 addr, bu16 data) { bu32 offset = addr - UART_IO_START_ADDR; /* if(offset != 0 && offset != 0xc) printf("in %s,offset=%x,value = %x\n", __FUNCTION__, offset,data); */ switch (offset) { case 0x0: // THR { unsigned char c = data & 0xff; /*There is no TSR ,so we set TEMT and THRE together */ bf537_io.uart.lsr |= 0x60; bf537_io.sic.sic_isr &= ~0x1000; bf537_io.uart.iir = 0x1; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } break; case 0x4: //FCR /*just walkaround code to open uart */ if (bf537_io.uart.lcr & 0x80) { bf537_io.uart.dlh = data; } else { bf537_io.uart.ier = data; /*generate RX interrupt */ if (data & 0x1) { } /*generate TX interrupt */ if (data & 0x2) { } } break; case 0xc: // SCR bf537_io.uart.lcr = data; break; case 0x24: bf537_io.uart.gctl = data; break; default: IO_ERR; //printf("%c", data); fflush(stdout); DBG_PRINT ("uart_write(%s=0x%08x)\n", "uart_reg", addr); break; } } static bu32 uart_read_long (bu32 addr) { bu16 ret; IO_ERR; return ret; } static void uart_write_long (bu32 addr, bu32 value) { uart_write_word(addr, (value & 0xffff)); //IO_ERR; return; } static bu8 uart_read_byte (bu32 addr) { bu8 ret; IO_ERR; return ret; } static void uart_write_byte (bu32 addr, bu8 value) { IO_ERR; return; } static bu16 ebiu_read_word (bu32 addr) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: return bf537_io.ebiu.amgctl; case 4: return bf537_io.ebiu.ambctl0; case 8: return bf537_io.ebiu.ambctl1; case 0x10: return bf537_io.ebiu.sdgctl; case 0x1c: return bf537_io.ebiu.sdstat; default: IO_ERR; } return; } static bu32 ebiu_read_long (bu32 addr) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: return bf537_io.ebiu.amgctl; case 4: return bf537_io.ebiu.ambctl0; case 8: return bf537_io.ebiu.ambctl1; case 0x10: return bf537_io.ebiu.sdgctl; default: IO_ERR; } return; } static void ebiu_write_long (bu32 addr, bu32 v) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: bf537_io.ebiu.amgctl = v; break; case 4: bf537_io.ebiu.ambctl0 = v; break; case 8: bf537_io.ebiu.ambctl1 = v; break; case 0x10: bf537_io.ebiu.sdgctl = v; break; default: IO_ERR; } return; } static void ebiu_write_word (bu32 addr, bu16 v) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: bf537_io.ebiu.amgctl = v; break; case 4: bf537_io.ebiu.ambctl0 = v; break; case 8: bf537_io.ebiu.ambctl1 = v; break; case 0x18: bf537_io.ebiu.sdrrc = v; break; default: IO_ERR; } return; } static bu8 dma_read_byte (bu32 addr) { bu8 ret = 0; IO_ERR; return ret; } static void dma_write_byte (bu32 addr, bu8 value) { IO_ERR; /* int channel = addr&0x3c0; int offset = (addr&0x3f)>>2; bf537_io.dma.bf537_dma_channel[channel][offset] = value; */ return; } static bu16 dma_read_word (bu32 addr) { bu16 ret; int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; ret = bf537_io.dma.bf537_dma_channel[channel][offset]; return ret; } static void dma_write_word (bu32 addr, bu16 value) { int i; int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; DBG_PRINT("\nIn %s,channel=0x%x,offset = %x,value=%x\n",__FUNCTION__, channel,offset,value); switch (offset) { case 0x2: /* CONFIG */ bf537_io.dma.bf537_dma_channel[channel][offset] = value; if (!(value & 0x1)) break; if (channel == BF537_MDMA_D0) { unsigned int src = bf537_io.dma.bf537_dma_channel[BF537_MDMA_S0][START_ADDR]; unsigned int dst = bf537_io.dma.bf537_dma_channel[BF537_MDMA_D0][START_ADDR]; short x_modify = (short)bf537_io.dma.bf537_dma_channel[BF537_MDMA_D0][X_MODIFY]; unsigned int size = bf537_io.dma.bf537_dma_channel[BF537_MDMA_D0][X_COUNT] * \ abs(x_modify); /* if two-demisbf537_io. is used */ if(bf537_io.dma.bf537_dma_channel[BF537_MDMA_D0][DMA_CONFIG] & 0x10){ size = size * bf537_io.dma.bf537_dma_channel[BF537_MDMA_D0][Y_COUNT] * \ bf537_io.dma.bf537_dma_channel[BF537_MDMA_D0][Y_MODIFY]; } /* if 16 width is used */ if((((bf537_io.dma.bf537_dma_channel[BF537_MDMA_D0][DMA_CONFIG] & 0xc) >> 2)) == 0x1){ size = size / 2; } i = size; //mem_cpy(start_addr,end_addr,size); /*work around code for dma copy to isram */ /* if (dst >= 0xffa00000) { return; }*/ /***************************************/ DBG_PRINT ( "DMA copy begin from 0x%x to 0x%x,size=0x%x\n", src, dst, size); for (; i >= 0; i--) { if(x_modify > 0) put_byte (saved_state.memory, dst++, get_byte (saved_state.memory, src++)); else put_byte (saved_state.memory, dst--, get_byte (saved_state.memory, src--)); } } break; default: bf537_io.dma.bf537_dma_channel[channel][offset] = value; break; } return; } static bu32 dma_read_long (bu32 addr) { bu32 ret; int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; ret = bf537_io.dma.bf537_dma_channel[channel][offset]; return ret; } static void dma_write_long (bu32 addr, bu32 value) { int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; DBG_PRINT("\nIn %s channel=0x%x,offset = %x,value=%x\n",__FUNCTION__,channel,offset,value); bf537_io.dma.bf537_dma_channel[channel][offset] = value; return; } static void core_int_write_long (bu32 addr, bu32 v) { int offset = addr - CORE_INT_IO_START_ADDR; //printf("%x,%x\n",addr,v); switch (offset) { case 0x104: bf537_io.core_int.imask = (v | 0x1f) & 0xffff; break; case 0x108: bf537_io.core_int.ipend = v; break; case 0x10c: bf537_io.core_int.ilat = v; //printf("write ilat %x\n",v); break; case 0x110: bf537_io.core_int.iprio= v; break; default: if (offset >= 0 && offset < 0x100) { bf537_io.core_int.evt[offset >> 2] = v; return; } IO_ERR; } } static bu32 core_int_read_long (bu32 addr) { int offset = addr - CORE_INT_IO_START_ADDR; bu32 ret; //printf("read %x\n",offset); switch (offset) { case 0x104: ret = (bf537_io.core_int.imask | 0x1f) & 0xffff; break; case 0x108: ret = bf537_io.core_int.ipend; break; case 0x10c: ret = bf537_io.core_int.ilat; //printf("read ilat %x",ret); break; case 0x110: ret = bf537_io.core_int.iprio; break; default: if (offset >= 0 && offset < 0x100) { ret = bf537_io.core_int.evt[offset >> 2]; return ret; } IO_ERR; } return ret; } static void wd_write_word (bu32 addr, bu16 v) { int offset = addr - WD_IO_START_ADDR; switch (offset) { case 0x0: bf537_io.wd.ctl = v; break; case 0x4: bf537_io.wd.cnt = v; break; case 0x8: bf537_io.wd.stat = v; break; default: IO_ERR; } } static bu32 deu_read_long (bu32 addr) { int offset = addr - DEU_IO_START_ADDR; switch (offset) { case 0x0: return bf537_io.deu.dspid; default: IO_ERR; } } static bu16 dpmc_read_word (bu32 addr) { int offset = addr - DPMC_IO_START_ADDR; bu16 ret; switch (offset) { case 0x0: ret = bf537_io.dpmc.pll_ctl; break; case 0x4: ret = bf537_io.dpmc.pll_div; break; case 0x8: ret = bf537_io.dpmc.vr_ctl; break; case 0xc: ret = bf537_io.dpmc.pll_stat; /*PLL_LOCKED is set */ break; case 0x10: ret = bf537_io.dpmc.pll_lockcnt; break; default: IO_ERR; } return ret; } static void dpmc_write_word (bu32 addr, bu16 v) { int offset = addr - DPMC_IO_START_ADDR; switch (offset) { case 0x0: bf537_io.dpmc.pll_ctl = v; break; case 0x4: bf537_io.dpmc.pll_div = v; break; case 0x8: bf537_io.dpmc.vr_ctl = v; break; case 0xc: bf537_io.dpmc.pll_stat = v; break; case 0x10: bf537_io.dpmc.pll_lockcnt = v; break; default: IO_ERR; } return; } static bu32 tbuf_read_long (bu32 addr) { int offset = addr - TBUF_IO_START_ADDR; switch (offset) { case 0: return bf537_io.tbuf.ctrl; case 4: return bf537_io.tbuf.stat; case 0x100: if (bf537_io.tbuf.rsel == 1) { bf537_io.tbuf.rsel = 0; if (bf537_io.tbuf.rix >= 16) bf537_io.tbuf.rix = 0; return bf537_io.tbuf.sbuf[bf537_io.tbuf.rix]; } else { bf537_io.tbuf.rsel = 1; return bf537_io.tbuf.dbuf[bf537_io.tbuf.rix++]; } break; default: IO_ERR; break; } return 0; } static void tbuf_write_long (bu32 addr, bu32 v) { int offset = addr - TBUF_IO_START_ADDR; switch (offset) { case 0: bf537_io.tbuf.ctrl = v; break; case 4: bf537_io.tbuf.stat = v; break; case 0x100: if (bf537_io.tbuf.wsel == 1) { bf537_io.tbuf.wsel = 0; if (bf537_io.tbuf.wix >= 16) bf537_io.tbuf.wix = 0; bf537_io.tbuf.sbuf[bf537_io.tbuf.wix] = v; } else { bf537_io.tbuf.wsel = 1; bf537_io.tbuf.dbuf[bf537_io.tbuf.wix++] = v; } break; default: IO_ERR; break; } return ; } static bu32 sic_read_long (bu32 addr) { int offset = addr - SIC_IO_START_ADDR; bu32 ret; switch (offset) { case 0x0: ret = bf537_io.sic.swrst; break; case 0x4: ret = bf537_io.sic.syscr; break; case 0xc: ret = bf537_io.sic.sic_imask; //printf("KSDBG:read imask ret= %x\n",ret); break; case 0x20: ret = bf537_io.sic.sic_isr; //printf("read sic_isr 0x%x\n",ret); break; case 0x24: ret = bf537_io.sic.sic_iwr; break; default: if (offset >= 0x10 && offset <= 0x1c) { ret = bf537_io.sic.sic_iar[(offset - 0x10) >> 2]; return ret; } IO_ERR; } return ret; } static void sic_write_long (bu32 addr, bu32 v) { int offset = addr - SIC_IO_START_ADDR; switch (offset) { case 0x24: bf537_io.sic.sic_iwr = v; break; case 0xc: //printf("KSDBG:write sic_imask v=%x\n",v); bf537_io.sic.sic_imask = v; break; default: if (offset >= 0x10 && offset <= 0x1c) { bf537_io.sic.sic_iar[(offset - 0x10) >> 2] = v; return; } IO_ERR; } } static void l1mem_write_long (bu32 addr, bu32 v) { int offset = addr - L1MEM_IO_START_ADDR; int pos = offset >> 2; switch (pos) { default: bf537_io.l1mem.reg[pos] = v; break; } } static bu32 l1mem_read_long (bu32 addr) { int offset = addr - L1MEM_IO_START_ADDR; int pos = offset >> 2; bu32 ret; switch (pos) { default: ret = bf537_io.l1mem.reg[pos]; } return ret; } static void l1dmem_write_long (bu32 addr, bu32 v) { int offset = addr - L1DMEM_IO_START_ADDR; int pos = offset >> 2; switch (pos) { default: bf537_io.l1dmem.reg[pos]; break; } } static void rtc_write_word (bu32 addr, bu16 v) { int offset = addr - RTC_IO_START_ADDR; switch (offset) { case 0x4: bf537_io.rtc.ictl = v; return; case 0x14: bf537_io.rtc.pren = v; /*set write complete bit to one */ bf537_io.rtc.istat |= 0x8000; return; case 0x8: bf537_io.rtc.istat = v; return; default: IO_ERR; } } static bu16 rtc_read_word (bu32 addr) { int offset = addr - RTC_IO_START_ADDR; bu16 ret; switch (offset) { case 0x14: ret = bf537_io.rtc.pren; break; case 0x8: ret = bf537_io.rtc.istat; /*clear write complete bit */ bf537_io.rtc.istat &= ~0x8000; break; default: IO_ERR; } return ret; } static void rtc_write_long (bu32 addr, bu32 v) { int offset = addr - RTC_IO_START_ADDR; switch (offset) { case 0x0: bf537_io.rtc.stat = v; return; case 0x10: bf537_io.rtc.alarm = v; return; default: IO_ERR; } } static bu32 rtc_read_long (bu32 addr) { int offset = addr - RTC_IO_START_ADDR; bu32 ret; switch (offset) { case 0x0: ret = bf537_io.rtc.stat; break; default: IO_ERR; } return ret; } static bu32 l1dmem_read_long (bu32 addr) { int offset = addr - L1DMEM_IO_START_ADDR; int pos = offset >> 2; bu32 ret; switch (pos) { default: ret = bf537_io.l1dmem.reg[pos]; break; } return ret; } static void core_timer_write_long (bu32 addr, bu32 v) { int offset = addr - CORE_TIMER_IO_START_ADDR; //printf("offset=%x",offset); switch (offset) { case 0x0: bf537_io.core_timer.tcntl = v; /*not sure core_int is open at this time */ if (bf537_io.core_timer.tcntl & 0x2) { bf537_io.core_int.imask |= 1 << CORE_TIMER_IRQ; } break; case 0x4: bf537_io.core_timer.tperio = v; break; case 0x8: bf537_io.core_timer.tscale = v; break; case 0xc: bf537_io.core_timer.tcount = v; break; default: IO_ERR; } return; } static bu32 core_timer_read_long (bu32 addr) { int offset = addr - CORE_TIMER_IO_START_ADDR; bu32 ret; switch (offset) { case 0x0: ret = bf537_io.core_timer.tcntl; break; case 0x4: ret = bf537_io.core_timer.tperio; break; case 0x8: ret = bf537_io.core_timer.tscale; break; case 0xc: ret = bf537_io.core_timer.tcount; break; default: IO_ERR; } return ret; } static bu16 pf_read_word (bu32 addr) { int offset = addr - PF_IO_START_ADDR; bu32 ret; switch (offset) { case 0x30: ret = bf537_io.pf.fio_dir; break; case 0x40: ret = bf537_io.pf.fio_inen; break; default: IO_ERR; } return ret; } static void pf_write_word (bu32 addr, bu16 v) { int offset = addr - PF_IO_START_ADDR; switch (offset) { case 0x4: bf537_io.pf.fio_flag_c = v; return; case 0x8: bf537_io.pf.fio_flag_s = v; return; case 0x14: bf537_io.pf.fio_maska_c = v; return; case 0x24: bf537_io.pf.fio_maskb_c = v; return; case 0x30: bf537_io.pf.fio_dir = v; return; case 0x10: // Flag Mask Interrupt A Register (set directly) case 0x38: // Flag Source Sensitivity Register case 0x40: // Flag Input Enable Register return; default: IO_ERR; } } static bu16 port_read_word(bu32 addr){ uint32_t offset = addr - PORT_IO_START_ADDR; switch(offset){ case 0x0: return bf537_io.port.portf_fer; case 0xc: return bf537_io.port.port_mux; default: IO_ERR; } } static void port_write_word(bu32 addr, bu16 v){ uint32_t offset = addr - PORT_IO_START_ADDR; switch(offset){ case 0x0: bf537_io.port.portf_fer = v; return; case 0xc: bf537_io.port.port_mux = v; return; default: IO_ERR; } } static bu32 port_read_long(bu32 addr){ IO_ERR; return -1; } static bu32 eth_read_long(bu32 addr){ uint32_t offset = addr - ETH_IO_START_ADDR; switch(offset){ case 0x64: return bf537_io.eth.emac_systat; default: IO_ERR; } } static void eth_write_long(bu32 addr, bu32 v){ uint32_t offset = addr - ETH_IO_START_ADDR; switch(offset){ case 0x64: bf537_io.eth.emac_systat = v; return; default: IO_ERR; } } void bf537_mach_init (void * curr_state, machine_config_t * this_mach) { saved_state_type *p_state; /*init bf537_io. value */ bf537_io.dpmc.pll_div = 0x0005; bf537_io.dpmc.pll_ctl = 0x1400; bf537_io.dpmc.pll_lockcnt = 0x0200; bf537_io.dpmc.pll_stat = 0x00a2; bf537_io.core_int.ipend = 0x11; /*at the beginning,global int is disabled and we are in Reset exception */ bf537_io.core_int.imask = 0x1f; bf537_io.core_int.ilat = 0x0; /**/ bf537_io.sic.sic_isr = 0x0; bf537_io.uart.lcr = 0x0; bf537_io.uart.dll = 0x0001; bf537_io.uart.ier = 0x0; bf537_io.uart.iir = 0x1; bf537_io.uart.lsr = 0x60; bf537_io.tbuf.ctrl = 0; bf537_io.tbuf.stat = 0; bf537_io.tbuf.rix = 0; bf537_io.tbuf.rsel = 0; bf537_io.tbuf.wix = 0; bf537_io.tbuf.wsel = 0; /*init mach */ if (!this_mach) { skyeye_exit (-1); } this_mach->mach_io_read_byte = bf537_io_read_byte; this_mach->mach_io_read_halfword = bf537_io_read_word; this_mach->mach_io_read_word = bf537_io_read_long; this_mach->mach_io_write_byte = bf537_io_write_byte; this_mach->mach_io_write_halfword = bf537_io_write_word; this_mach->mach_io_write_word = bf537_io_write_long; this_mach->mach_io_do_cycle = bf537_io_do_cycle; this_mach->mach_set_intr = bf537_set_int; p_state = (saved_state_type *)curr_state; p_state->disable_int = bf537_disable_int; p_state->enable_int = bf537_enable_int; p_state->clear_int = bf537_clear_int; p_state->sti = bf537_sti; p_state->cli = bf537_cli; p_state->set_int = bf537_set_int; } ������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/mach/bf533_irq.h���������������������������������������������������������0000644�0001750�0000144�00000002137�10571721153�016654� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* bf533_irq.h - irq for blackfin simulation Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __BF533_IRQ_H__ #define __BF533_IRQ_H__ #define CORE_TIMER_IRQ 6 #define EXCEPT_IRQ 3 #endif ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/mach/bf533_io.c����������������������������������������������������������0000644�0001750�0000144�00000100172�11012326044�016450� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* bf533_io.c - implementation of bf533 machine simulation Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "bfin-sim.h" #include "types.h" #include "bf533_io.h" #include "dma.h" #include "bf533_irq.h" #include "skyeye_config.h" #include <stdio.h> #include <fcntl.h> #include <signal.h> extern void dma_mem_cpy (unsigned int src, unsigned int dst, int size); /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" #define DEBUG 0 #if DEBUG #define DBG_PRINT(a...) printf(##a) #else #define DBG_PRINT(a...) #endif #define IO_ERR {printf("\n%s io error!!!addr=0x%x,pc=0x%x\n",__FUNCTION__,addr,PCREG);raise (SIGILL);} #define MALLOC_ERR {printf("\n%s malloc error!\n",__FUNCTION__);skyeye_exit(-1);} /*declare the device io functions*/ declare_device (uart) declare_device (wd) declare_device (core_int) declare_device (dma) declare_device (dpmc) declare_device (deu) declare_device (ebiu) declare_device (sic) declare_device (l1mem) declare_device (l1dmem) declare_device (rtc) declare_device (tbuf) declare_device (core_timer) declare_device (pf) static void handle_irq (); static void bf533_disable_int (); static void bf533_enable_int (); typedef struct uart { bu16 rbr; bu16 thr; bu16 ier; bu16 iir; bu16 fcr; bu16 lcr; bu16 lsr; bu16 msr; bu16 scr; bu16 dll; bu16 dlh; bu16 gctl; } bf533_uart_t; static int uart_outfd; typedef struct dma_channel { bu32 next_desc_ptr; bu32 start_addr; bu32 x_count; bu32 x_modify; bu32 y_count; bu32 y_modify; bu32 curr_desc_ptr; bu32 curr_addr; bu32 irq_status; bu32 peripheral_map; bu32 curr_x_count; bu32 curr_y_count; } bf533_dma_channel_t; typedef struct l1mem { bu32 reg[L1MEM_IO_SIZE / 4]; } bf533_l1mem_t; typedef struct l1dmem { bu32 reg[L1DMEM_IO_SIZE / 4]; } bf533_l1dmem_t; typedef struct dma { bu16 tc_per; bu16 tc_cnt; bu32 bf533_dma_channel[12][16]; } bf533_dma_t; typedef struct ebiu { bu16 amgctl; bu16 ambctl0; bu16 ambctl1; bu16 sdgctl; bu16 sdbctl; bu16 sdrrc; bu16 sdstat; } bf533_ebiu_t; typedef struct core_int { bu32 evt[16]; bu32 imask; bu32 ipend; bu32 iprio; bu32 ilat; } bf533_core_int_t; typedef struct wd { bu16 ctl; bu32 cnt; bu32 stat; } bf533_wd_t; typedef struct tbuf { bu32 ctrl; bu32 stat; bu32 rix; bu32 rsel; bu32 wix; bu32 wsel; bu32 dbuf[16]; bu32 sbuf[16]; } bf533_tbuf_t; typedef struct deu { bu32 dspid; } bf533_deu_t; typedef struct dpmc { bu16 pll_ctl; bu16 pll_stat; bu16 pll_lockcnt; bu16 vr_ctl; bu16 pll_div; } bf533_dpmc_t; typedef struct sic { bu32 swrst; bu32 syscr; bu32 sic_imask; bu32 sic_iar[3]; bu32 sic_isr; bu32 sic_iwr; } bf533_sic_t; typedef struct rtc { bu32 stat; bu32 ictl; bu32 istat; bu32 swcnt; bu32 alarm; bu32 pren; } bf533_rtc_t; typedef struct core_timer { bu32 tcntl; bu32 tperiod; bu32 tscale; bu32 tcount; } bf533_core_timer_t; typedef struct pf { bu32 fio_flag_d; bu32 fio_flag_c; bu32 fio_flag_s; bu32 fio_dir; bu32 fio_polar; bu32 fio_maska_c; bu32 fio_maskb_c; bu32 fio_inen; } bf533_pf_t; typedef struct bf533_io { bf533_uart_t uart; /* Receive data register */ bf533_dma_t dma; bf533_ebiu_t ebiu; bf533_core_int_t core_int; bf533_wd_t wd; bf533_deu_t deu; bf533_dpmc_t dpmc; bf533_sic_t sic; bf533_l1mem_t l1mem; bf533_l1dmem_t l1dmem; bf533_rtc_t rtc; bf533_core_timer_t core_timer; bf533_pf_t pf; bf533_tbuf_t tbuf; } bf533_io_t; static bf533_io_t io; /*also be called by raise inst and except*/ static void bf533_set_int (int irq) { //if(irq != CORE_TIMER_IRQ & irq != 0) //fprintf(PF,"####################irq=%d,in %s\n",irq,__FUNCTION__); //if ((io.core_int.imask | 0x1f) & (1 << irq)) { //if(irq != CORE_TIMER_IRQ & irq != 0) // fprintf(PF,"####################irq=%d,in %s\n",irq,__FUNCTION__); /*set the corresponding int bit to 1 in ilat */ io.core_int.ilat |= (1 << irq); //} } static void bf533_clear_int (int irq_no_use) { int irq; //fprintf(PF,"KSDBG:begin in %s,ipend=0x%x,ilat=0x%x,SPREG=0x%x,irq=%d\n",__FUNCTION__, io.core_int.ipend,io.core_int.ilat, SPREG, irq); /*fix me, trigger the corresponding int according to some prio check, */ for (irq = 0; irq < 16; irq++) { /* check there is a pending int for clear */ if ((io.core_int.ipend >> irq) & 0x1) { /*clear the int bit */ io.core_int.ipend &= ~(1 << irq); /*clear corresponding int in the device */ if (irq == CORE_TIMER_IRQ) { io.core_timer.tcntl &= ~0x8; } if (io.core_int.ipend == 0x0) { /*There is no interrupt to handle, switch mode */ //fprintf(PF,"KSDBG:mode switch,SPREG=0x%x,USPREG=0x%x\n",SPREG,USPREG); MODE = USR_MODE; OLDSPREG = SPREG; SPREG = USPREG; } else ; //fprintf(PF,"KSDBG:in super mode,ipend=0x%x,SPREG=0x%x,irq=%d\n",io.core_int.ipend, SPREG, irq); return; } } //fprintf(PF,"KSDBG:end in %s,ipend=0x%x,SPREG=0x%x,irq=%d\n",__FUNCTION__, io.core_int.ipend, SPREG, irq); } static void handle_irq () { int irq = 0; if (OLDPCREG < 0x1000) { printf ("in %s,pc=%x,jump to 0x%x,olderpc=0x%x\n", __FUNCTION__, PCREG, OLDPCREG, OLDERPCREG); raise (SIGINT); } /*if global int is disabled,just return */ if (io.core_int.ipend & 0x10) { return; } /*fix me, trigger the corresponding int according to some prio check, */ for (irq = 0; irq < 16; irq++) { if (((io.core_int.ilat&(io.core_int.imask|0x1f)) >> irq) & 0x1) { if (irq != CORE_TIMER_IRQ) ; //fprintf (PF, // "# in %s begin,irq=%d,pc=0x%x,ipend=0x%x,RETI=0x%x\n", // __FUNCTION__, irq, PCREG, io.core_int.ipend, RETIREG); /*current there is a higher or equal priority pending int for handle,wait until it finish */ if(io.core_int.ipend&(~((~0x0) << irq))) return; /* set ipend bit , and clear ilat */ io.core_int.ilat &= ~(1 << irq); io.core_int.ipend |= (1 << irq); /*now if did_jump in interp.c is set, the following code is executed twice,maybe it not make something wrong */ if (LC1REG && OLDPCREG == LB1REG && --LC1REG) { //printf("int in the end of loop,PC=%x\n",PCREG); PCREG = LT1REG; } else if (LC0REG && OLDPCREG == LB0REG && --LC0REG) { //printf("int in the end of loop,PC=%x\n",PCREG); PCREG = LT0REG; } /*clear corresponding int in the device */ if (irq == CORE_TIMER_IRQ) { //return; io.core_timer.tcntl &= ~0x8; // fprintf(PF,"##Timer IRQ:PC=0x%x,\n",PCREG); } else { //fprintf (PF, "## Other IRQ:irq=%d,\n", irq); } /* switch mode */ if (MODE == USR_MODE) { MODE = SUPER_MODE; USPREG = SPREG; SPREG = OLDSPREG; } /*save pc to reti,jump to the corresponding vector */ if (irq == EXCEPT_IRQ) { //fprintf (PF, // "##System Call:PC=0x%x, sys_number=%d,ipend=0x%x\n", // PCREG, PREG (0), // io.core_int.ipend); saved_state.retx = PCREG; } else { saved_state.reti = PCREG; } PCREG = io.core_int.evt[irq]; if (irq != CORE_TIMER_IRQ) //fprintf (PF, // "## in %s end,irq=%d,pc=0x%x,ipend=0x%x\n", // __FUNCTION__, irq, PCREG, io.core_int.ipend); /*at the same time , disable global int for protecting reti */ bf533_disable_int (); return; } } } static void bf533_disable_int () { //printf("in %s\n",__FUNCTION__); io.core_int.ipend |= 0x10; } static void bf533_enable_int () { //printf("in %s\n",__FUNCTION__); io.core_int.ipend &= ~0x10; } static void bf533_cli (bu32 * dreg) { *dreg = io.core_int.imask; //printf("cli,%x\n",*dreg); io.core_int.imask = 0x1f; } static void bf533_sti (bu32 * dreg) { //printf("sti,%x\n",*dreg); io.core_int.imask = *dreg; } #define BF533_HZ 50 static UART_OPEN = 0; static void bf533_io_do_cycle () { static int sclk_count = 0; static int uart_tx_count = 0; //if (PCREG >= 0x7480048){ // fprintf(PF,"KSDBG:pc=0x%x,insn@pc=0x%x,sp=0x%x,usp=0x%x,ipend=0x%x\n",(PCREG-0x7480044), get_long(saved_state.memory, PCREG), SPREG,USPREG,io.core_int.ipend); //}*/ sclk_count++; /*if global int is disabled */ /* if(sclk_count == io.core_timer.tscale+1){ sclk_count = 0; io.core_timer.tcount--; if(io.core_timer.tcount == 0){ bf533_set_int(CORE_TIMER_IRQ); io.core_timer.tcount = io.core_timer.tperiod; } } */ if (sclk_count == io.core_timer.tscale + 1) { sclk_count = 0; if ( io.core_timer.tcntl & 0x2 ) { io.core_timer.tcount--; if (io.core_timer.tcount == 0) { io.core_timer.tcount = io.core_timer.tperiod / 10; /*if previous timer int handle is not finished , this int is lost */ /*If core_timer enabled? */ if ((io.core_timer.tcntl & 0x2) && ! (io.core_timer.tcntl & 0x8) ) { io.core_timer.tcntl |= 0x8; bf533_set_int (CORE_TIMER_IRQ); uart_tx_count++; } } } } if ((io.sic.sic_imask & 0x8000) && (io.uart.ier & 0x2)) { // printf("\nUART TX IRQ\n"); bf533_set_int (((io.sic.sic_iar[1] & 0xf0000000) >> 28) + 7); io.uart.iir = 0x2; io.sic.sic_isr |= 0x8000; uart_tx_count = 0; } if (!(io.uart.lsr & 0x1)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; //printf("\nUART RX IRQ before skyeye_uart_read\n"); if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { //printf ("\nUART RX IRQ,getchar=%c\n",buf); //printf("%c",buf); //putchar(buf); io.uart.rbr = buf; /*set DR bit in LSR */ io.uart.lsr |= 0x1; //printf("\nUART RX IRQ getchar\n"); } } if ((io.sic.sic_imask & 0x4000) && (io.uart.ier & 0x1) && (io.uart.lsr & 0x1)) { io.uart.iir = 0x4; io.sic.sic_isr |= 0x4000; bf533_set_int (((io.sic.sic_iar[1] & 0xf000000) >> 24) + 7); } /* fprintf(PF,"KSDBG:in super mode,ipend=0x%x,SPREG=0x%x,irq=%d\n",io.core_int.ipend, SPREG, irq); */ handle_irq (); } static bu8 bf533_io_read_byte (void * state, bu32 addr) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { return dma_read_byte (addr); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { return uart_read_byte (addr); } else { IO_ERR; } } } static bu16 bf533_io_read_word (void * state, bu32 addr) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { return dma_read_word (addr); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { return uart_read_word (addr); } else if (addr >= DPMC_IO_START_ADDR && addr < DPMC_IO_END_ADDR) { return dpmc_read_word (addr); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { return ebiu_read_word (addr); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { return rtc_read_word (addr); } else if (addr >= PF_IO_START_ADDR && addr < PF_IO_END_ADDR) { return pf_read_word (addr); } else { IO_ERR; } } } static bu32 bf533_io_read_long (void * state, bu32 addr) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { return dma_read_long (addr); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { return uart_read_long (addr); } else if (addr >= DEU_IO_START_ADDR && addr < DEU_IO_END_ADDR) { return deu_read_long (addr); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { return ebiu_read_long (addr); } else if (addr >= SIC_IO_START_ADDR && addr < SIC_IO_END_ADDR) { return sic_read_long (addr); } else if (addr >= L1MEM_IO_START_ADDR && addr < L1MEM_IO_END_ADDR) { return l1mem_read_long (addr); } else if (addr >= L1DMEM_IO_START_ADDR && addr < L1DMEM_IO_END_ADDR) { return l1dmem_read_long (addr); } else if (addr >= CORE_INT_IO_START_ADDR && addr < CORE_INT_IO_END_ADDR) { return core_int_read_long (addr); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { return rtc_read_long (addr); } else if (addr >= CORE_TIMER_IO_START_ADDR && addr < CORE_TIMER_IO_END_ADDR) { return core_timer_read_long (addr); } else if (addr >= TBUF_IO_START_ADDR && addr < TBUF_IO_END_ADDR) { return tbuf_read_long (addr); } else { IO_ERR; } } } static void bf533_io_write_byte (void * state, bu32 addr, bu8 v) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { dma_write_byte (addr, v); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { uart_write_byte (addr, v); } else { IO_ERR; } } return; } static void bf533_io_write_word (void * state, bu32 addr, bu16 v) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { dma_write_word (addr, v); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { uart_write_word (addr, v); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { ebiu_write_word (addr, v); } else if (addr >= WD_IO_START_ADDR && addr < WD_IO_END_ADDR) { wd_write_word (addr, v); } else if (addr >= DPMC_IO_START_ADDR && addr < DPMC_IO_END_ADDR) { dpmc_write_word (addr, v); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { rtc_write_word (addr, v); } else if (addr >= PF_IO_START_ADDR && addr < PF_IO_END_ADDR) { pf_write_word (addr, v); } else { IO_ERR; } } return; } static void bf533_io_write_long (void * state, bu32 addr, bu32 v) { switch (addr) { default: if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) { dma_write_long (addr, v); } else if (addr >= UART_IO_START_ADDR && addr < UART_IO_END_ADDR) { uart_write_long (addr, v); } else if (addr >= EBIU_IO_START_ADDR && addr < EBIU_IO_END_ADDR) { ebiu_write_long (addr, v); } else if (addr >= CORE_INT_IO_START_ADDR && addr < CORE_INT_IO_END_ADDR) { core_int_write_long (addr, v); } else if (addr >= SIC_IO_START_ADDR && addr < SIC_IO_END_ADDR) { sic_write_long (addr, v); } else if (addr >= L1MEM_IO_START_ADDR && addr < L1MEM_IO_END_ADDR) { l1mem_write_long (addr, v); } else if (addr >= L1DMEM_IO_START_ADDR && addr < L1DMEM_IO_END_ADDR) { l1dmem_write_long (addr, v); } else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) { rtc_write_long (addr, v); } else if (addr >= CORE_TIMER_IO_START_ADDR && addr < CORE_TIMER_IO_END_ADDR) { core_timer_write_long (addr, v); } else if (addr >= TBUF_IO_START_ADDR && addr < TBUF_IO_END_ADDR) { return tbuf_write_long (addr, v); } else { IO_ERR; } } return; } bu16 uart_read_word (bu32 addr) { bu16 data; //printf("bf533_uart_read,addr=%x\n",addr); bu32 offset = addr - UART_IO_START_ADDR; /* if(offset != 0 && offset != 0x14 && offset != 0xc && offset!=0x4) printf("###############offset=0x%x\n",offset); */ static int read_num = 0; switch (offset) { case 0x0: // RbR if (io.uart.lcr & 0x80) { data = io.uart.dlh; } if (read_num == 0) { read_num = 1; return 'k'; } if (read_num == 1) { io.uart.lsr &= ~0x1; io.sic.sic_isr &= ~0x4000; data = io.uart.rbr & 0xff; //io.uart.iir = 0x1; read_num = 0; //fprintf (PF, "*****read rbr=%x,pc=%x,isr=%x\n", data, // PCREG, io.sic.sic_isr); } break; case 0x4: // ier if (io.uart.lcr & 0x80) data = io.uart.dlh; else data = io.uart.ier; break; case 0x8: // iir data = io.uart.iir; //printf("read iir=%x,pc=%x\n",data,PCREG); io.uart.iir = 0x1; break; case 0xc: // lcr data = io.uart.lcr; break; case 0x10: // MCR data = 0x0; break; case 0x14: // LSR data = io.uart.lsr; //printf("read lsr=%x,pc=%x\n",data,PCREG); break; case 0x1c: // SCR data = io.uart.lcr; break; case 0x24: // SCR data = io.uart.gctl; break; default: IO_ERR; DBG_PRINT ("uart_read(%s=0x%08x)\n", "uart_reg", addr); break; } return (data); } void uart_write_word (bu32 addr, bu16 data) { bu32 offset = addr - UART_IO_START_ADDR; //if(offset != 0 && offset != 0xc) //printf("************offset=%x,value = %x\n",offset,data); switch (offset) { case 0x0: // THR { unsigned char c = data & 0xff; /*There is no TSR ,so we set TEMT and THRE together */ io.uart.lsr |= 0x60; io.sic.sic_isr &= ~0x8000; io.uart.iir = 0x1; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } break; case 0x4: //FCR /*just walkaround code to open uart */ if (io.uart.lcr & 0x80) { io.uart.dlh = data; /* if(data&0x8){ printf("KSDBG:UART OPEN\n"); UART_OPEN = 1; } */ } else { io.uart.ier = data; /*generate RX interrupt */ if (data & 0x1) { } /*generate TX interrupt */ if (data & 0x2) { } if (data & 0x8) { UART_OPEN = 1; } } break; case 0xc: // SCR io.uart.lcr = data; break; case 0x24: io.uart.gctl = data; break; default: IO_ERR; //printf("%c", data); fflush(stdout); DBG_PRINT ("uart_write(%s=0x%08x)\n", "uart_reg", addr); break; } } bu32 uart_read_long (bu32 addr) { bu16 ret; IO_ERR; return ret; } void uart_write_long (bu32 addr, bu32 value) { uart_write_word(addr, (value & 0xffff)); //IO_ERR; return; } bu8 uart_read_byte (bu32 addr) { bu8 ret; IO_ERR; return ret; } static void uart_write_byte (bu32 addr, bu8 value) { IO_ERR; return; } static bu16 ebiu_read_word (bu32 addr) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: return io.ebiu.amgctl; case 4: return io.ebiu.ambctl0; case 8: return io.ebiu.ambctl1; case 0x10: return io.ebiu.sdgctl; case 0x1c: return io.ebiu.sdstat; default: IO_ERR; } return; } static bu32 ebiu_read_long (bu32 addr) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: return io.ebiu.amgctl; case 4: return io.ebiu.ambctl0; case 8: return io.ebiu.ambctl1; case 0x10: return io.ebiu.sdgctl; default: IO_ERR; } return; } static void ebiu_write_long (bu32 addr, bu32 v) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: io.ebiu.amgctl = v; break; case 4: io.ebiu.ambctl0 = v; break; case 8: io.ebiu.ambctl1 = v; break; case 0x10: io.ebiu.sdgctl = v; break; default: IO_ERR; } return; } static void ebiu_write_word (bu32 addr, bu16 v) { int offset = addr - EBIU_IO_START_ADDR; switch (offset) { case 0: io.ebiu.amgctl = v; break; case 4: io.ebiu.ambctl0 = v; break; case 8: io.ebiu.ambctl1 = v; break; case 0x18: io.ebiu.sdrrc = v; break; default: IO_ERR; } return; } static bu8 dma_read_byte (bu32 addr) { bu8 ret = 0; IO_ERR; return ret; } static void dma_write_byte (bu32 addr, bu8 value) { IO_ERR; /* int channel = addr&0x3c0; int offset = (addr&0x3f)>>2; io.dma.bf533_dma_channel[channel][offset] = value; */ return; } static bu16 dma_read_word (bu32 addr) { bu16 ret; int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; ret = io.dma.bf533_dma_channel[channel][offset]; return ret; } static void dma_write_word (bu32 addr, bu16 value) { int i; int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; DBG_PRINT("\nIn %s,channel=0x%x,offset = %x,value=%x\n",__FUNCTION__, channel,offset,value); switch (offset) { case 0x2: /*CONFIG*/ io.dma.bf533_dma_channel[channel][offset] = value; if (!(value & 0x1)) break; if (channel == BF533_MDMA_D0) { unsigned int src = io.dma.bf533_dma_channel[BF533_MDMA_S0][START_ADDR]; unsigned int dst = io.dma.bf533_dma_channel[BF533_MDMA_D0][START_ADDR]; short x_modify = (short)io.dma.bf533_dma_channel[BF533_MDMA_D0][X_MODIFY]; unsigned int size = io.dma.bf533_dma_channel[BF533_MDMA_D0][X_COUNT] * \ abs(x_modify); /* if two-demision is used */ if(io.dma.bf533_dma_channel[BF533_MDMA_D0][DMA_CONFIG] & 0x10){ size = size * io.dma.bf533_dma_channel[BF533_MDMA_D0][Y_COUNT] * \ io.dma.bf533_dma_channel[BF533_MDMA_D0][Y_MODIFY]; } /* if 16 width is used */ if((((io.dma.bf533_dma_channel[BF533_MDMA_D0][DMA_CONFIG] & 0xc) >> 2)) == 0x1){ size = size / 2; } i = size; //mem_cpy(start_addr,end_addr,size); /*work around code for dma copy to isram */ /* if (dst >= 0xffa00000) { return; }*/ /***************************************/ DBG_PRINT ( "DMA copy begin from 0x%x to 0x%x,size=0x%x\n", src, dst, size); for (; i >= 0; i--) { if(x_modify > 0) put_byte (saved_state.memory, dst++, get_byte (saved_state.memory, src++)); else put_byte (saved_state.memory, dst--, get_byte (saved_state.memory, src--)); } } break; default: io.dma.bf533_dma_channel[channel][offset] = value; break; } return; } static bu32 dma_read_long (bu32 addr) { bu32 ret; int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; ret = io.dma.bf533_dma_channel[channel][offset]; return ret; } static void dma_write_long (bu32 addr, bu32 value) { int channel = (addr & 0x3c0) >> 6; int offset = (addr & 0x3f) >> 2; DBG_PRINT("\nIn %s channel=0x%x,offset = %x,value=%x\n",__FUNCTION__,channel,offset,value); io.dma.bf533_dma_channel[channel][offset] = value; return; } static void core_int_write_long (bu32 addr, bu32 v) { int offset = addr - CORE_INT_IO_START_ADDR; //printf("%x,%x\n",addr,v); switch (offset) { case 0x104: io.core_int.imask = (v | 0x1f) & 0xffff; break; case 0x108: io.core_int.ipend = v; break; case 0x10c: io.core_int.ilat = v; //printf("write ilat %x\n",v); break; case 0x110: io.core_int.iprio = v; break; default: if (offset >= 0 && offset < 0x100) { io.core_int.evt[offset >> 2] = v; return; } IO_ERR; } } static bu32 core_int_read_long (bu32 addr) { int offset = addr - CORE_INT_IO_START_ADDR; bu32 ret; //printf("read %x\n",offset); switch (offset) { case 0x104: ret = (io.core_int.imask | 0x1f) & 0xffff; break; case 0x108: ret = io.core_int.ipend; break; case 0x10c: ret = io.core_int.ilat; //printf("read ilat %x",ret); break; case 0x110: ret = io.core_int.iprio; break; default: if (offset >= 0 && offset < 0x100) { ret = io.core_int.evt[offset >> 2]; return ret; } IO_ERR; } return ret; } static void wd_write_word (bu32 addr, bu16 v) { int offset = addr - WD_IO_START_ADDR; switch (offset) { case 0x0: io.wd.ctl = v; break; case 0x4: io.wd.cnt = v; break; case 0x8: io.wd.stat = v; break; default: IO_ERR; } } static bu32 deu_read_long (bu32 addr) { int offset = addr - DEU_IO_START_ADDR; switch (offset) { case 0x0: return io.deu.dspid; default: IO_ERR; } } static bu16 dpmc_read_word (bu32 addr) { int offset = addr - DPMC_IO_START_ADDR; bu16 ret; switch (offset) { case 0x0: ret = io.dpmc.pll_ctl; break; case 0x4: ret = io.dpmc.pll_div; break; case 0x8: ret = io.dpmc.vr_ctl; break; case 0xc: ret = io.dpmc.pll_stat; /*PLL_LOCKED is set */ break; case 0x10: ret = io.dpmc.pll_lockcnt; break; default: IO_ERR; } return ret; } static void dpmc_write_word (bu32 addr, bu16 v) { int offset = addr - DPMC_IO_START_ADDR; switch (offset) { case 0x0: io.dpmc.pll_ctl = v; break; case 0x4: io.dpmc.pll_div = v; break; case 0x8: io.dpmc.vr_ctl = v; break; case 0xc: io.dpmc.pll_stat = v; break; case 0x10: io.dpmc.pll_lockcnt = v; break; default: IO_ERR; } return; } static bu32 tbuf_read_long (bu32 addr) { int offset = addr - TBUF_IO_START_ADDR; switch (offset) { case 0: return io.tbuf.ctrl; case 4: return io.tbuf.stat; case 0x100: if (io.tbuf.rsel == 1) { io.tbuf.rsel = 0; if (io.tbuf.rix >= 16) io.tbuf.rix = 0; return io.tbuf.sbuf[io.tbuf.rix]; } else { io.tbuf.rsel = 1; return io.tbuf.dbuf[io.tbuf.rix++]; } break; default: IO_ERR; break; } return 0; } static void tbuf_write_long (bu32 addr, bu32 v) { int offset = addr - TBUF_IO_START_ADDR; switch (offset) { case 0: io.tbuf.ctrl = v; break; case 4: io.tbuf.stat = v; break; case 0x100: if (io.tbuf.wsel == 1) { io.tbuf.wsel = 0; if (io.tbuf.wix >= 16) io.tbuf.wix = 0; io.tbuf.sbuf[io.tbuf.wix] = v; } else { io.tbuf.wsel = 1; io.tbuf.dbuf[io.tbuf.wix++] = v; } break; default: IO_ERR; break; } return ; } static bu32 sic_read_long (bu32 addr) { int offset = addr - SIC_IO_START_ADDR; bu32 ret; switch (offset) { case 0x0: ret = io.sic.swrst; break; case 0x4: ret = io.sic.syscr; break; case 0xc: ret = io.sic.sic_imask; //printf("read ret= %x\n",ret); break; case 0x20: ret = io.sic.sic_isr; //printf("read sic_isr 0x%x\n",ret); break; case 0x24: ret = io.sic.sic_iwr; break; default: if (offset >= 0x10 && offset <= 0x18) { ret = io.sic.sic_iar[(offset - 0x10) >> 2]; return ret; } IO_ERR; } return ret; } static void sic_write_long (bu32 addr, bu32 v) { int offset = addr - SIC_IO_START_ADDR; switch (offset) { case 0x24: io.sic.sic_iwr = v; break; case 0xc: //printf("write v=%x\n",v); io.sic.sic_imask = v; break; default: if (offset >= 0x10 && offset <= 0x18) { io.sic.sic_iar[(offset - 0x10) >> 2] = v; return; } IO_ERR; } } static void l1mem_write_long (bu32 addr, bu32 v) { int offset = addr - L1MEM_IO_START_ADDR; int pos = offset >> 2; switch (pos) { default: io.l1mem.reg[pos] = v; break; } } static bu32 l1mem_read_long (bu32 addr) { int offset = addr - L1MEM_IO_START_ADDR; int pos = offset >> 2; bu32 ret; switch (pos) { default: ret = io.l1mem.reg[pos]; } return ret; } static void l1dmem_write_long (bu32 addr, bu32 v) { int offset = addr - L1DMEM_IO_START_ADDR; int pos = offset >> 2; switch (pos) { default: io.l1dmem.reg[pos]; break; } } static void rtc_write_word (bu32 addr, bu16 v) { int offset = addr - RTC_IO_START_ADDR; switch (offset) { case 0x4: io.rtc.ictl = v; return; case 0x14: io.rtc.pren = v; /*set write complete bit to one */ io.rtc.istat |= 0x8000; return; case 0x8: io.rtc.istat = v; return; default: IO_ERR; } } static bu16 rtc_read_word (bu32 addr) { int offset = addr - RTC_IO_START_ADDR; bu16 ret; switch (offset) { case 0x14: ret = io.rtc.pren; break; case 0x8: ret = io.rtc.istat; /*clear write complete bit */ io.rtc.istat &= ~0x8000; break; default: IO_ERR; } return ret; } static void rtc_write_long (bu32 addr, bu32 v) { int offset = addr - RTC_IO_START_ADDR; switch (offset) { case 0x0: io.rtc.stat = v; return; case 0x10: io.rtc.alarm = v; return; default: IO_ERR; } } static bu32 rtc_read_long (bu32 addr) { int offset = addr - RTC_IO_START_ADDR; bu32 ret; switch (offset) { case 0x0: ret = io.rtc.stat; break; default: IO_ERR; } return ret; } static bu32 l1dmem_read_long (bu32 addr) { int offset = addr - L1DMEM_IO_START_ADDR; int pos = offset >> 2; bu32 ret; switch (pos) { default: ret = io.l1dmem.reg[pos]; break; } return ret; } static void core_timer_write_long (bu32 addr, bu32 v) { int offset = addr - CORE_TIMER_IO_START_ADDR; //printf("offset=%x",offset); switch (offset) { case 0x0: io.core_timer.tcntl = v; /*not sure core_int is open at this time */ if (io.core_timer.tcntl & 0x2) { io.core_int.imask |= 1 << CORE_TIMER_IRQ; } /* if autorld is enabled reload tcount */ if (io.core_timer.tcntl & 0x4) { io.core_timer.tcount = io.core_timer.tperiod / 10; } break; case 0x4: io.core_timer.tperiod = v; break; case 0x8: io.core_timer.tscale = v; break; case 0xc: io.core_timer.tcount = v; break; default: IO_ERR; } return; } static bu32 core_timer_read_long (bu32 addr) { int offset = addr - CORE_TIMER_IO_START_ADDR; bu32 ret; switch (offset) { case 0x0: ret = io.core_timer.tcntl; break; case 0x4: ret = io.core_timer.tperiod; break; case 0x8: ret = io.core_timer.tscale; break; case 0xc: ret = io.core_timer.tcount; break; default: IO_ERR; } return ret; } static bu16 pf_read_word (bu32 addr) { int offset = addr - PF_IO_START_ADDR; bu32 ret; switch (offset) { case 0x30: ret = io.pf.fio_dir; break; case 0x40: ret = io.pf.fio_inen; break; default: IO_ERR; } return ret; } static void pf_write_word (bu32 addr, bu16 v) { int offset = addr - PF_IO_START_ADDR; switch (offset) { case 0x4: io.pf.fio_flag_c = v; return; case 0x8: io.pf.fio_flag_s = v; return; case 0x14: io.pf.fio_maska_c = v; return; case 0x24: io.pf.fio_maskb_c = v; return; case 0x30: io.pf.fio_dir = v; return; case 0x10: // Flag Mask Interrupt A Register (set directly) case 0x38: // Flag Source Sensitivity Register case 0x40: // Flag Input Enable Register return; default: IO_ERR; } } static void bf533_io_reset(){} void bf533_mach_init (void * curr_state, machine_config_t * this_mach) { saved_state_type *p_state; /*init io value */ io.dpmc.pll_div = 0x0005; io.dpmc.pll_ctl = 0x1400; io.dpmc.pll_lockcnt = 0x0200; io.dpmc.pll_stat = 0x00a2; io.core_int.ipend = 0x10; /*at the beginning,global int is disabled*/ io.core_int.imask = 0x1f; io.core_int.ilat = 0x0; /**/ io.core_timer.tcntl = 0; io.core_timer.tcount = BF533_HZ; io.core_timer.tperiod = BF533_HZ; io.sic.sic_isr = 0x0; io.uart.lcr = 0x0; io.uart.dll = 0x0001; io.uart.ier = 0x0; io.uart.iir = 0x1; io.uart.lsr = 0x60; io.tbuf.ctrl = 0; io.tbuf.stat = 0; io.tbuf.rix = 0; io.tbuf.rsel = 0; io.tbuf.wix = 0; io.tbuf.wsel = 0; /*init mach */ if (!this_mach) { skyeye_exit (-1); } this_mach->mach_io_read_byte = bf533_io_read_byte; this_mach->mach_io_read_halfword = bf533_io_read_word; this_mach->mach_io_read_word = bf533_io_read_long; this_mach->mach_io_write_byte = bf533_io_write_byte; this_mach->mach_io_write_halfword = bf533_io_write_word; this_mach->mach_io_write_word = bf533_io_write_long; this_mach->mach_io_do_cycle = bf533_io_do_cycle; this_mach->mach_io_reset = bf533_io_reset; this_mach->mach_set_intr = bf533_set_int; //this_mach->mach_update_intr = bf533_update_int; //this_mach->mach_pending_intr = bf533_pending_int; p_state = (saved_state_type *)curr_state; p_state->disable_int = bf533_disable_int; p_state->enable_int = bf533_enable_int; p_state->clear_int = bf533_clear_int; p_state->sti = bf533_sti; p_state->cli = bf533_cli; p_state->set_int = bf533_set_int; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/mach/bf533_io.h����������������������������������������������������������0000644�0001750�0000144�00000006440�10571721153�016471� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* bf533_io.h - necessary bf533 io address range definition for bf533 simulation Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __BF533_IO_H__ #define __BF533_IO_H__ #define IO_START_ADDR 0xFFC00000 #define IO_END_ADDR 0xFFFFFFFF #define DMA_IO_START_ADDR 0xFFC00B00 #define DMA_IO_END_ADDR 0xFFC00FFF #define UART_IO_START_ADDR 0xFFC00400 #define UART_IO_END_ADDR 0xFFC004FF #define CORETIMER_IO_START_ADDR 0xFFE03000 #define CORETIMER_IO_END_ADDR 0xFFE0300C #define EBIU_IO_START_ADDR 0xFFC00A00 #define EBIU_IO_END_ADDR 0xFFC00AFF #define TCNTL 0x0 #define TPERIOD 0x4 #define TSCALE 0x8 #define TCOUNT 0xc #define CORE_INT_IO_START_ADDR 0xFFE02000 #define CORE_INT_IO_END_ADDR 0xFFE02110 #define WD_IO_START_ADDR 0xFFC00200 #define WD_IO_END_ADDR 0xFFC002FF #define DEU_IO_START_ADDR 0xFFE05000 #define DEU_IO_END_ADDR 0xFFE05008 #define DPMC_IO_START_ADDR 0xFFC00000 #define DPMC_IO_END_ADDR 0xFFC000FF #define SIC_IO_START_ADDR 0xFFC00100 #define SIC_IO_END_ADDR 0xFFC001FF #define L1MEM_IO_START_ADDR 0xFFE01004 #define L1MEM_IO_END_ADDR 0xFFE01404 #define L1MEM_IO_SIZE (L1MEM_IO_END_ADDR - L1MEM_IO_START_ADDR) #define L1DMEM_IO_START_ADDR 0xFFE00000 #define L1DMEM_IO_END_ADDR 0xFFE00404 #define L1DMEM_IO_SIZE (L1DMEM_IO_END_ADDR - L1DMEM_IO_START_ADDR) #define RTC_IO_START_ADDR 0xFFC00300 #define RTC_IO_END_ADDR 0xFFC003FF #define RTC_IO_SIZE (RTC_IO_END_ADDR - RTC_IO_START_ADDR) #define CORE_TIMER_IO_START_ADDR 0xFFE03000 #define CORE_TIMER_IO_END_ADDR 0xFFE03010 #define CORE_TIMER_IO_SIZE (CORE_TIMER_IO_END_ADDR-CORE_TIMER_IO_START_ADDR) #define PF_IO_START_ADDR 0xFFC00700 #define PF_IO_END_ADDR 0xFFC007FF #define PF_IO_SIZE (PF_IO_END_ADDR - PF_IO_START_ADDR) #define TBUF_IO_START_ADDR 0xFFE06000 #define TBUF_IO_END_ADDR 0xFFE06103 #define TBUF_IO_SIZE (TBUF_IO_END_ADDR - TBUF_IO_START_ADDR) #define PORT_IO_START_ADDR 0xFFC03200 #define PORT_IO_END_ADDR 0xFFC0320C #define PORT_IO_SIZE (PORT_IO_END_ADDR - PORT_IO_START_ADDR) #define ETH_IO_START_ADDR 0xFFC03000 #define ETH_IO_END_ADDR 0xFFC031D8 #define ETH_IO_SIZE (ETH_IO_END_ADDR - ETH_IO_START_ADDR) #define declare_device(name) \ static void name##_write_byte(bu32 addr, bu8 v); \ static void name##_write_word(bu32 addr, bu16 v); \ static void name##_write_long(bu32 addr, bu32 v); \ static bu8 name##_read_byte(bu32 addr); \ static bu16 name##_read_word(bu32 addr); \ static bu32 name##_read_long(bu32 addr); #endif ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/bfin/mach/bf533.h�������������������������������������������������������������0000644�0001750�0000144�00000015704�10541455476�016016� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * Blackfin BF533/2/1/2.6 support : LG Soft India */ #ifndef _BLKFin_H_ #define _BLKFin_H_ #include <linux/config.h> #define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ /*some misc defines*/ #define IMASK_IVG15 0x8000 #define IMASK_IVG14 0x4000 #define IMASK_IVG13 0x2000 #define IMASK_IVG12 0x1000 #define IMASK_IVG11 0x0800 #define IMASK_IVG10 0x0400 #define IMASK_IVG9 0x0200 #define IMASK_IVG8 0x0100 #define IMASK_IVG7 0x0080 #define IMASK_IVGTMR 0x0040 #define IMASK_IVGHW 0x0020 /***************************/ #define BLKFIN_ICACHESIZE (16*1024) #if defined(CONFIG_BF533) || defined(CONFIG_BF532) #define BLKFIN_DCACHESIZE (32*1024) #define BLKFIN_DSUPBANKS 2 #else #define BLKFIN_DCACHESIZE (16*1024) #define BLKFIN_DSUPBANKS 1 #endif #define BLKFIN_DSUBBANKS 4 #define BLKFIN_DWAYS 2 #define BLKFIN_DLINES 64 #define BLKFIN_ISUBBANKS 4 #define BLKFIN_IWAYS 4 #define BLKFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 #define WAY01_L 0x3 #define WAY2_L 0x4 #define WAY02_L 0x5 #define WAY12_L 0x6 #define WAY012_L 0x7 #define WAY3_L 0x8 #define WAY03_L 0x9 #define WAY13_L 0xA #define WAY013_L 0xB #define WAY32_L 0xC #define WAY320_L 0xD #define WAY321_L 0xE #define WAYALL_L 0xF #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ /* IAR0 BIT FIELDS*/ #define RTC_ERROR_BIT 0x0FFFFFFF #define UART_ERROR_BIT 0xF0FFFFFF #define SPORT1_ERROR_BIT 0xFF0FFFFF #define SPI_ERROR_BIT 0xFFF0FFFF #define SPORT0_ERROR_BIT 0xFFFF0FFF #define PPI_ERROR_BIT 0xFFFFF0FF #define DMA_ERROR_BIT 0xFFFFFF0F #define PLLWAKE_ERROR_BIT 0xFFFFFFFF /* IAR1 BIT FIELDS*/ #define DMA7_UARTTX_BIT 0x0FFFFFFF #define DMA6_UARTRX_BIT 0xF0FFFFFF #define DMA5_SPI_BIT 0xFF0FFFFF #define DMA4_SPORT1TX_BIT 0xFFF0FFFF #define DMA3_SPORT1RX_BIT 0xFFFF0FFF #define DMA2_SPORT0TX_BIT 0xFFFFF0FF #define DMA1_SPORT0RX_BIT 0xFFFFFF0F #define DMA0_PPI_BIT 0xFFFFFFFF /* IAR2 BIT FIELDS*/ #define WDTIMER_BIT 0x0FFFFFFF #define MEMDMA1_BIT 0xF0FFFFFF #define MEMDMA0_BIT 0xFF0FFFFF #define PFB_BIT 0xFFF0FFFF #define PFA_BIT 0xFFFF0FFF #define TIMER2_BIT 0xFFFFF0FF #define TIMER1_BIT 0xFFFFFF0F #define TIMER0_BIT 0xFFFFFFFF #define ZERO 0x0 /********************************* EBIU Settings ************************************/ #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) #if (CONFIG_C_AMBEN_ALL) #define V_AMBEN AMBEN_ALL #endif #if (CONFIG_C_AMBEN) #define V_AMBEN 0x0 #endif #if (CONFIG_C_AMBEN_B0) #define V_AMBEN AMBEN_B0 #endif #if (CONFIG_C_AMBEN_B0_B1) #define V_AMBEN AMBEN_B0_B1 #endif #if (CONFIG_C_AMBEN_B0_B1_B2) #define V_AMBEN AMBEN_B0_B1_B2 #endif #if (CONFIG_C_AMCKEN) #define V_AMCKEN AMCKEN #else #define V_AMCKEN 0x0 #endif #if (CONFIG_C_CDPRIO) #define V_CDPRIO 0x100 #else #define V_CDPRIO 0x0 #endif #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) /********************************PLL Settings **************************************/ #if (CONFIG_VCO_MULT < 0) #error "VCO Multiplier is less than 0. Please select a different value" #endif #if (CONFIG_VCO_MULT == 0) #error "VCO Multiplier should be greater than 0. Please select a different value" #endif #ifdef CONFIG_BLKFIN_STAMP #if(CONFIG_VCO_MULT > 56) && (CONFIG_CLKIN_HALF == 0) #error "VCO Multiplier is more than 56 for STAMP. Please select a different value" #endif #endif #ifdef CONFIG_EZKIT #if(CONFIG_VCO_MULT > 22) && (CONFIG_CLKIN_HALF == 0) #error "VCO Multiplier is more than 22 for EZKIT. Please select a different value" #endif #endif #if(CONFIG_VCO_MULT > 64) #error "VCO Multiplier is more than 64. Please select a different value" #endif #if(CONFIG_CLKIN_HALF == 0) #define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) #else #define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) #endif #if(CONFIG_PLL_BYPASS == 0) #define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) #define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) #else #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif #if (CONFIG_SCLK_DIV < 1) #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" #endif #if (CONFIG_SCLK_DIV > 15) #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" #endif #if (CONFIG_CCLK_DIV != 1) #if (CONFIG_CCLK_DIV != 2) #if (CONFIG_CCLK_DIV != 4) #if (CONFIG_CCLK_DIV != 8) #error "CCLK DIV can be 1,2,4 or 8 only.Please select a proper value" #endif #endif #endif #endif #define MAX_VC 650000000 #if(CONFIG_VCO_HZ > MAX_VC) #error "VCO selected is more than maximum value. Please change the VCO multipler" #endif #if (CONFIG_SCLK_HZ > 133000000) #error "Sclk value selected is more than maximum.Please select a proper value for SCLK multiplier" #endif #if (CONFIG_SCLK_HZ < 27000000) #error "Sclk value selected is less than minimum.Please select a proper value for SCLK multiplier" #endif #if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) #if(CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) #if(CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) #error "Please select sclk less than cclk" #endif #endif #endif #if (CONFIG_CCLK_DIV == 1) #define CONFIG_CCLK_ACT_DIV CCLK_DIV1 #endif #if (CONFIG_CCLK_DIV == 2) #define CONFIG_CCLK_ACT_DIV CCLK_DIV2 #endif #if (CONFIG_CCLK_DIV == 4) #define CONFIG_CCLK_ACT_DIV CCLK_DIV4 #endif #if (CONFIG_CCLK_DIV == 8) #define CONFIG_CCLK_ACT_DIV CCLK_DIV8 #endif #ifndef CONFIG_CCLK_ACT_DIV #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly #endif #ifdef CONFIG_BF533 #define CPU "BF533" #endif #ifdef CONFIG_BF532 #define CPU "BF532" #endif #ifdef CONFIG_BF531 #define CPU "BF531" #endif #ifndef CPU #define CPU "UNKOWN" #endif #if (CONFIG_MEM_SIZE % 4) #error "SDRAM mem size must be multible of 4MB" #endif #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ #define ANOMALY_05000158 0x200 #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #else /*Write Through */ #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #endif #define SDRAM_DKERNEL (SDRAM_DGENERIC | CPLB_LOCK) #define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SIZE_1K 0x00000400 /* 1K */ #define SIZE_4K 0x00001000 /* 4K */ #define SIZE_1M 0x00100000 /* 1M */ #define SIZE_4M 0x00400000 /* 4M */ #endif /* _BLKFin_H_ */ ������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/��������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023523234�013730� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/Makefile.in���������������������������������������������������������������0000644�0001750�0000144�00000110420�11023514464�016000� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������# Makefile.in generated by automake 1.10 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006 Free Software Foundation, Inc. # This Makefile.in is free software; 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0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * 12/06/2007 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __PPC_MEMORY_H__ #define __PPC_MEMORY_H__ //byte boot_rom[8 * 1024 * 1024];/* default 8M boot rom for e500 core */ #define INIT_RAM_SIZE 0x4000 extern byte * init_ram; /* 16k init ram for 8560 */ extern byte * boot_rom; /* default 8M bootrom for 8560 */ extern byte * ddr_ram; /* 64M DDR SDRAM */ extern unsigned long init_ram_start_addr, init_ram_size; extern uint32 boot_romSize; extern uint32 boot_rom_start_addr; #define DEFAULT_BOOTROM_SIZE (8 * 1024 * 1024) #define DDR_RAM_START_ADDR (0x0) #define DDR_RAM_SIZE (64 * 1024 * 1024) #define MPC8650_DPRAM_SIZE 0xC000 #endif ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_boot.c���������������������������������������������������������0000644�0001750�0000144�00000006616�10712073070�017204� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * 30/10/2007 Michael.Kang <blackfin.kang@gmail.com> */ /* * A simple boot function for linux happy */ #include <stdio.h> #include "ppc_cpu.h" #include "ppc_boot.h" #include "ppc_mmu.h" #include "sysendian.h" extern byte * ddr_ram; /* 64M DDR SDRAM */ static void load_initrd(){ FILE *f; const int initrd_start = 32 * 1024 * 1024, initrd_size = 1 * 1024 * 1024; const char * filename = "initrd.img"; /* * r4 - Starting address of the init RAM disk * r5 - Ending address of the init RAM disk */ gCPU.gpr[4] = initrd_start; gCPU.gpr[5] = initrd_start + initrd_size; if(f = fopen(filename, "rb")){ void * t = &ddr_ram[initrd_start]; if (fread(&ddr_ram[initrd_start], 1, initrd_size, f)) printf("Load %s to 0x%x...\n", filename, initrd_start); else printf("Can not load %s to 0x%x\n", filename, initrd_start); fclose(f); } else{ fprintf(stderr, "Can not open initrd file %s.\n", filename); skyeye_exit(-1); } } static void set_bootcmd(){ const int bd_start = 8 * 1024 * 1024; bd_t * t = &ddr_ram[bd_start]; t->bi_immr_base = ppc_word_to_BE(0xe0000000); t->bi_busfreq = ppc_word_to_BE(100 * 1024 * 1024); t->bi_intfreq = ppc_word_to_BE(500 * 1024 * 1024); t->bi_baudrate = ppc_word_to_BE(9600); t->bi_memsize = ppc_word_to_BE(64 * 1024 * 1024); gCPU.gpr[3] = bd_start; char * bootcmd = "root=/dev/ram0 console=ttyCPM0 mem=64M"; const int bootcmd_start= 9 * 1024 * 1024; memcpy(&ddr_ram[bootcmd_start], bootcmd, (strlen(bootcmd) + 1)); gCPU.gpr[6] = bootcmd_start; gCPU.gpr[7] = bootcmd_start + strlen(bootcmd) + 1; } static void setup_boot_map(){ /* setup initial tlb map for linux, that should be done by bootloader */ ppc_tlb_entry_t * entry = &l2_tlb1_vsp[0]; entry->v = 1; /* entry is valid */ entry->ts = 0; /* address space 0 */ entry->tid = 0; /* TID value for shared(global) page */ entry->epn = 0xC0000; /* Virtual address of DDR ram in address space*/ entry->rpn = 0x0; /* Physical address of DDR ram in address space*/ entry->size = 0x7; /* 16M byte page size */ /* usxrw should be initialized to 010101 */ entry->usxrw |= 0x15; /* Full supervisor mode access allowed */ entry->usxrw &= 0x15; /* No user mode access allowed */ entry->wimge = 0x8; /* Caching-inhibited, non-coherent,big-endian*/ entry->x = 0; /* Reserved system attributes */ entry->u = 0; /* User attribute bits */ entry->iprot = 1; /* Page is protected from invalidation */ gCPU.ccsr.ccsr = 0xE0000; /* Just for boot linux */ } void ppc_boot(){ /* Fixme, will move it to skyeye.conf */ load_initrd(); set_bootcmd(); /* just for linux boot, so we need to do some map */ setup_boot_map(); } ������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_boot.h���������������������������������������������������������0000644�0001750�0000144�00000007023�10714066563�017215� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * 30/10/2007 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __PPC_BOOT_H__ #define __PPC_BOOT_H__ #define TARGET_85xx #define TARGET_CPM2 typedef struct bd_info { unsigned int bi_memstart; /* start of DRAM memory */ unsigned int bi_memsize; /* size of DRAM memory in bytes */ unsigned int bi_flashstart; /* start of FLASH memory */ unsigned int bi_flashsize; /* size of FLASH memory */ unsigned int bi_flashoffset; /* reserved area for startup monitor */ unsigned int bi_sramstart; /* start of SRAM memory */ unsigned int bi_sramsize; /* size of SRAM memory */ #if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\ defined(TARGET_83xx) unsigned int bi_immr_base; /* base of IMMR register */ #endif #if defined(TARGET_PPC_MPC52xx) unsigned int bi_mbar_base; /* base of internal registers */ #endif unsigned int bi_bootflags; /* boot / reboot flag (for LynxOS) */ unsigned int bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* Ethernet address */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned int bi_intfreq; /* Internal Freq, in MHz */ unsigned int bi_busfreq; /* Bus Freq, in MHz */ #if defined(TARGET_CPM2) unsigned int bi_cpmfreq; /* CPM_CLK Freq, in MHz */ unsigned int bi_brgfreq; /* BRG_CLK Freq, in MHz */ unsigned int bi_sccfreq; /* SCC_CLK Freq, in MHz */ unsigned int bi_vco; /* VCO Out from PLL, in MHz */ #endif #if defined(TARGET_PPC_MPC52xx) unsigned int bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned int bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif unsigned int bi_baudrate; /* Console Baudrate */ #if defined(TARGET_4xx) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */ unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif #if defined(TARGET_HYMOD) hymod_conf_t bi_hymod_conf; /* hymod configuration information */ #endif #if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \ defined(TARGET_85xx) || defined(TARGET_83xx) /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; #define HAVE_ENET1ADDR #endif #if defined(TARGET_EVB64260) || defined(TARGET_440GX) || defined(TARGET_85xx) /* third onboard ethernet ports */ unsigned char bi_enet2addr[6]; #define HAVE_ENET2ADDR #endif #if defined(TARGET_440GX) /* fourth onboard ethernet ports */ unsigned char bi_enet3addr[6]; #define HAVE_ENET3ADDR #endif #if defined(TARGET_4xx) unsigned int bi_opbfreq; /* OB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif #if defined(TARGET_440GX) int bi_phynum[4]; /* phy mapping */ int bi_phymode[4]; /* phy mode */ #endif } bd_t; #endif /* #ifndef __PPC_BOOT_H__ */ �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_tools.c��������������������������������������������������������0000644�0001750�0000144�00000023720�10635115336�017402� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ppc_tools.c - necessary ppc definition for skyeye debugger Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/21/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "types.h" #include "ppc_fpu.h" #include "ppc_cpu.h" extern PPC_CPU_State gCPU; int ppc_count_leading_zeros(uint64 i) { int ret; uint32 dd = i >> 32; if (dd) { ret = 31; if (dd > 0xffff) { ret -= 16; dd >>= 16; } if (dd > 0xff) { ret -= 8; dd >>= 8; } if (dd & 0xf0) { ret -= 4; dd >>= 4; } if (dd & 0xc) { ret -= 2; dd >>= 2; } if (dd & 0x2) ret--; } else { dd = (uint32)i; ret = 63; if (dd > 0xffff) { ret -= 16; dd >>= 16; } if (dd > 0xff) { ret -= 8; dd >>= 8; } if (dd & 0xf0) { ret -= 4; dd >>= 4; } if (dd & 0xc) { ret -= 2; dd >>= 2; } if (dd & 0x2) ret--; } return ret; } int ppc_fpu_normalize_quadro(ppc_quadro *d) { int ret = d->m0 ? ppc_count_leading_zeros(d->m0) : 64 + ppc_count_leading_zeros(d->m1); return ret; } int ppc_fpu_normalize(ppc_double *d) { return ppc_count_leading_zeros(d->m); } int ppc_fpu_normalize_single(ppc_single *s) { int ret; uint32 dd = s->m; ret = 31; if (dd > 0xffff) { ret -= 16; dd >>= 16; } if (dd > 0xff) { ret -= 8; dd >>= 8; } if (dd & 0xf0) { ret -= 4; dd >>= 4; } if (dd & 0xc) { ret -= 2; dd >>= 2; } if (dd & 0x2) ret--; return ret; } //#include "tools/snprintf.h" void ppc_fpu_unpack_double(ppc_double *res, uint64 d) { FPD_UNPACK_VAR(d, res->s, res->e, res->m); // ht_printf("ud: %qx: s:%d e:%d m:%qx\n", d, res.s, res.e, res.m); // .124 if (res->e == 2047) { if (res->m == 0) { res->type = ppc_fpr_Inf; } else { res->type = ppc_fpr_NaN; } } else if (res->e == 0) { if (res->m == 0) { res->type = ppc_fpr_zero; } else { // normalize denormalized exponent int diff = ppc_fpu_normalize(res) - 8; res->m <<= diff+3; res->e -= 1023 - 1 + diff; res->type = ppc_fpr_norm; } } else { res->e -= 1023; // unbias exponent res->type = ppc_fpr_norm; // add implied bit res->m |= 1ULL<<52; res->m <<= 3; } // ht_printf("ud: %qx: s:%d e:%d m:%qx\n", d, res.s, res.e, res.m); } void ppc_fpu_unpack_single(ppc_single *res, uint32 d) { FPS_UNPACK_VAR(d, res->s, res->e, res->m); // .124 if (res->e == 255) { if (res->m == 0) { res->type = ppc_fpr_Inf; } else { res->type = ppc_fpr_NaN; } } else if (res->e == 0) { if (res->m == 0) { res->type = ppc_fpr_zero; } else { // normalize denormalized exponent int diff = ppc_fpu_normalize_single(res) - 8; res->m <<= diff+3; res->e -= 127 - 1 + diff; res->type = ppc_fpr_norm; } } else { res->e -= 127; // unbias exponent res->type = ppc_fpr_norm; // add implied bit res->m |= 1<<23; res->m <<= 3; } } uint32 ppc_fpu_round(ppc_double *d) { // .132 switch (FPSCR_RN(gCPU.fpscr)) { case FPSCR_RN_NEAR: if (d->m & 0x7) { if ((d->m & 0x7) != 4) { d->m += 4; } else if (d->m & 8) { d->m += 4; } return FPSCR_XX; } return 0; case FPSCR_RN_ZERO: if (d->m & 0x7) { return FPSCR_XX; } return 0; case FPSCR_RN_PINF: if (!d->s && (d->m & 0x7)) { d->m += 8; return FPSCR_XX; } return 0; case FPSCR_RN_MINF: if (d->s && (d->m & 0x7)) { d->m += 8; return FPSCR_XX; } return 0; } return 0; } uint32 ppc_fpu_round_single(ppc_single *s) { switch (FPSCR_RN(gCPU.fpscr)) { case FPSCR_RN_NEAR: if (s->m & 0x7) { if ((s->m & 0x7) != 4) { s->m += 4; } else if (s->m & 8) { s->m += 4; } return FPSCR_XX; } return 0; case FPSCR_RN_ZERO: if (s->m & 0x7) { return FPSCR_XX; } return 0; case FPSCR_RN_PINF: if (!s->s && (s->m & 0x7)) { s->m += 8; return FPSCR_XX; } return 0; case FPSCR_RN_MINF: if (s->s && (s->m & 0x7)) { s->m += 8; return FPSCR_XX; } return 0; } return 0; } uint32 ppc_fpu_round_double(ppc_double *s) { switch (FPSCR_RN(gCPU.fpscr)) { case FPSCR_RN_NEAR: if (s->m & 0x7) { if ((s->m & 0x7) != 4) { s->m += 4; } else if (s->m & 8) { s->m += 4; } return FPSCR_XX; } return 0; case FPSCR_RN_ZERO: if (s->m & 0x7) { return FPSCR_XX; } return 0; case FPSCR_RN_PINF: if (!s->s && (s->m & 0x7)) { s->m += 8; return FPSCR_XX; } return 0; case FPSCR_RN_MINF: if (s->s && (s->m & 0x7)) { s->m += 8; return FPSCR_XX; } return 0; } return 0; } uint32 ppc_fpu_pack_double(ppc_double *d, uint64 *res) { // .124 uint32 ret = 0; // ht_printf("pd_type: %d\n", d.type); switch (d->type) { case ppc_fpr_norm: // ht_printf("pd: %qx: s:%d e:%d m:%qx\n", d, d.s, d.e, d.m); d->e += 1023; // bias exponent // ht_printf("pd: %qx: s:%d e:%d m:%qx\n", d, d.s, d.e, d.m); if (d->e > 0) { ret |= ppc_fpu_round(d); if (d->m & (1ULL<<56)) { d->e++; d->m >>= 4; } else { d->m >>= 3; } if (d->e >= 2047) { d->e = 2047; d->m = 0; ret |= FPSCR_OX; } } else { // number is denormalized d->e = -d->e+1; if (d->e <= 56) { d->m >>= d->e; ret |= ppc_fpu_round(d); d->m <<= 1; if (d->m & (1ULL<<56)) { d->e = 1; d->m = 0; } else { d->e = 0; d->m >>= 4; ret |= FPSCR_UX; } } else { // underflow to zero d->e = 0; d->m = 0; ret |= FPSCR_UX; } } break; case ppc_fpr_zero: d->e = 0; d->m = 0; break; case ppc_fpr_NaN: d->e = 2047; d->m = 1; break; case ppc_fpr_Inf: d->e = 2047; d->m = 0; break; } // ht_printf("pd: %qx: s:%d e:%d m:%qx\n", d, d.s, d.e, d.m); FPD_PACK_VAR(*res, d->s, d->e, d->m); return ret; } uint32 ppc_fpu_pack_single(ppc_double *d, uint32 *res) { // .124 uint32 ret = 0; switch (d->type) { case ppc_fpr_norm: // ht_printf("ps: %qx: s:%d e:%d m:%qx\n", d, d.s, d.e, d.m); d->e += 127; // bias exponent d->m >>= 29; // ht_printf("ps: %qx: s:%d e:%d m:%qx\n", d, d.s, d.e, d.m); if (d->e > 0) { ret |= ppc_fpu_round_double(d); if (d->m & (1ULL<<27)) { d->e++; d->m >>= 4; } else { d->m >>= 3; } if (d->e >= 255) { d->e = 255; d->m = 0; ret |= FPSCR_OX; } } else { // number is denormalized d->e = -d->e+1; if (d->e <= 27) { d->m >>= d->e; ret |= ppc_fpu_round_double(d); d->m <<= 1; if (d->m & (1ULL<<27)) { d->e = 1; d->m = 0; } else { d->e = 0; d->m >>= 4; ret |= FPSCR_UX; } } else { // underflow to zero d->e = 0; d->m = 0; ret |= FPSCR_UX; } } break; case ppc_fpr_zero: d->e = 0; d->m = 0; break; case ppc_fpr_NaN: d->e = 255; d->m = 1; break; case ppc_fpr_Inf: d->e = 255; d->m = 0; break; } // ht_printf("ps: %qx: s:%d e:%d m:%qx\n", d, d.s, d.e, d.m); FPS_PACK_VAR(*res, d->s, d->e, d->m); return ret; } void ppc_fpu_single_to_double(ppc_single *s, ppc_double *d) { d->s = s->s; d->e = s->e; d->m = ((uint64)s->m)<<29; d->type = s->type; } uint32 ppc_fpu_pack_double_as_single(ppc_double *d, uint64 *res) { ppc_single s; s.m = d->m >> 29; s.e = d->e; s.s = d->s; s.type = d->type; uint32 ret = 0; switch (s.type) { case ppc_fpr_norm: s.e = d->e+127; if (s.e > 0) { ret |= ppc_fpu_round_single(&s); if (s.m & (1<<27)) { s.e++; s.m >>= 4; } else { s.m >>= 3; } if (s.e >= 255) { s.type = ppc_fpr_Inf; s.e = 255; s.m = 0; ret |= FPSCR_OX; } d->e = s.e-127; } else { // number is denormalized s.e = -s.e+1; if (s.e <= 27) { s.m >>= s.e; ret |= ppc_fpu_round_single(&s); s.m <<= 1; if (s.m & (1<<27)) { s.e = 1; s.m = 0; } else { s.e = 0; s.m >>= 4; ret |= FPSCR_UX; } } else { // underflow to zero s.type = ppc_fpr_zero; s.e = 0; s.m = 0; ret |= FPSCR_UX; } } break; case ppc_fpr_zero: s.e = 0; s.m = 0; break; case ppc_fpr_NaN: s.e = 2047; s.m = 1; break; case ppc_fpr_Inf: s.e = 2047; s.m = 0; break; } if (s.type == ppc_fpr_norm) { d->m = ((uint64)(s.m))<<32; } else { d->m = s.m; } // ht_printf("dm: %qx\n", d.m); ret |= ppc_fpu_pack_double(d, res); return ret; } uint32 ppc_fpu_double_to_int(ppc_double *d) { switch (d->type) { case ppc_fpr_norm: { if (d->e < 0) { switch (FPSCR_RN(gCPU.fpscr)) { case FPSCR_RN_NEAR: if (d->e < -1) { return 0; } else { return d->s ? (uint32)-1 : 1; } case FPSCR_RN_ZERO: return 0; case FPSCR_RN_PINF: if (d->s) { return 0; } else { return 1; } case FPSCR_RN_MINF: if (d->s) { return (uint32)-1; } else { return 0; } } } if (d->e >= 31) { if (d->s) { return 0x80000000; } else { return 0x7fffffff; } } int i=0; uint64 mask = (1ULL<<(56 - d->e - 1))-1; // we have to round switch (FPSCR_RN(gCPU.fpscr)) { case FPSCR_RN_NEAR: if (d->m & mask) { if (d->m & (1ULL<<(56 - d->e - 2))) { i = 1; } } break; case FPSCR_RN_ZERO: break; case FPSCR_RN_PINF: if (!d->s && (d->m & mask)) { i = 1; } break; case FPSCR_RN_MINF: if (d->s && (d->m & mask)) { i = 1; } break; } d->m >>= 56 - d->e - 1; d->m += i; return d->s ? -d->m : d->m; } case ppc_fpr_zero: return 0; case ppc_fpr_Inf: case ppc_fpr_NaN: if (d->s) { return 0x80000000; } else { return 0x7fffffff; } } return 0; } ������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_io.c�����������������������������������������������������������0000644�0001750�0000144�00000002655�10635115336�016655� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ppc_io.c - necessary arm definition for skyeye debugger Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 04/26/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include <stdint.h> uint32_t ppc_read_byte(void * state, uint32_t addr){ return 0; } uint32_t ppc_read_halfword(void * state,uint32_t addr){ return 0; } uint32_t ppc_read_word(void * state, uint32_t addr){ return 0; } void ppc_write_byte(void * state, uint32_t addr, uint32_t data){} void ppc_write_halfword(void * state, uint32_t addr,uint32_t data){} void ppc_write_word(void * state,uint32_t addr,uint32_t data){} �����������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/sysendian.h��������������������������������������������������������0000644�0001750�0000144�00000005513�10635115336�017402� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * sysendian.h * * Copyright (C) 1999-2004 Stefan Weyergraf * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __SYSTEM_ARCH_SPECIFIC_SYSENDIAN_H__ #define __SYSTEM_ARCH_SPECIFIC_SYSENDIAN_H__ #include "types.h" //#include "config.h" static inline FUNCTION_CONST uint32 ppc_bswap_word(uint32 data) { return (data>>24)|((data>>8)&0xff00)|((data<<8)&0xff0000)|(data<<24); } static inline FUNCTION_CONST uint64 ppc_bswap_dword(uint64 data) { return (((uint64)ppc_bswap_word(data)) << 32) | (uint64)ppc_bswap_word(data >> 32); } static inline FUNCTION_CONST uint16 ppc_bswap_half(uint16 data) { return (data<<8)|(data>>8); } #if HOST_ENDIANESS == HOST_ENDIANESS_LE /* * Little-endian machine */ # define ppc_dword_from_BE(data) (ppc_bswap_dword(data)) # define ppc_word_from_BE(data) (ppc_bswap_word(data)) # define ppc_half_from_BE(data) (ppc_bswap_half(data)) # define ppc_dword_from_LE(data) ((uint64)(data)) # define ppc_word_from_LE(data) ((uint32)(data)) # define ppc_half_from_LE(data) ((uint16)(data)) # define ppc_dword_to_LE(data) ppc_dword_from_LE(data) # define ppc_word_to_LE(data) ppc_word_from_LE(data) # define ppc_half_to_LE(data) ppc_half_from_LE(data) # define ppc_dword_to_BE(data) ppc_dword_from_BE(data) # define ppc_word_to_BE(data) ppc_word_from_BE(data) # define ppc_half_to_BE(data) ppc_half_from_BE(data) #elif HOST_ENDIANESS == HOST_ENDIANESS_BE /* * Big-endian machine */ # define ppc_dword_from_BE(data) ((uint64)(data)) # define ppc_word_from_BE(data) ((uint32)(data)) # define ppc_half_from_BE(data) ((uint16)(data)) # define ppc_dword_from_LE(data) (ppc_bswap_dword(data)) # define ppc_word_from_LE(data) (ppc_bswap_word(data)) # define ppc_half_from_LE(data) (ppc_bswap_half(data)) # define ppc_dword_to_LE(data) ppc_dword_from_LE(data) # define ppc_word_to_LE(data) ppc_word_from_LE(data) # define ppc_half_to_LE(data) ppc_half_from_LE(data) # define ppc_dword_to_BE(data) ppc_dword_from_BE(data) # define ppc_word_to_BE(data) ppc_word_from_BE(data) # define ppc_half_to_BE(data) ppc_half_from_BE(data) #else /* * Weird-endian machine * HOST_ENDIANESS is neither little- nor big-endian? */ # error "What kind of a weird machine do you have? It's neither little- nor big-endian??? This is unsupported." #endif #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_mmu.c����������������������������������������������������������0000644�0001750�0000144�00000264514�10717205606�017051� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_mmu.cc * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * Portions Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nmsu.edu) * Portions Copyright (C) 2004 Apple Computer, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Pages marked: v.??? * From: IBM PowerPC MicroProcessor Family: Altivec(tm) Technology... * Programming Environments Manual */ #include "debug.h" #include "tracers.h" #include "sysendian.h" #include "io.h" #include "ppc_cpu.h" #include "ppc_fpu.h" #include "ppc_vec.h" #include "ppc_mmu.h" #include "ppc_exc.h" #include "ppc_tools.h" #include "ppc_memory.h" #include "ppc_e500_exc.h" #define DEFAULT_CCSR_MEM 0xFF700000 #define CCSR_MEM_SIZE 0x100000 #define GET_CCSR_BASE(reg)(((reg >> 8)&0xFFF) << 20) e500_mmu_t e500_mmu; ppc_tlb_entry_t l1_i_vsp[4]; /* instruction, filled by TLB1 hit */ ppc_tlb_entry_t l1_i_tlb4k[64]; /* instruction, filled by TLB0 hit */ ppc_tlb_entry_t l1_d_vsp[4]; /* data, filled by TLB1 hit */ ppc_tlb_entry_t l1_d_tlb4k[64]; /* data, filled by TLB0 hit */ #define L2_TLB0_SIZE 256 #define L2_TLB1_SIZE 16 ppc_tlb_entry_t l2_tlb0_4k[L2_TLB0_SIZE]; /* unified, filled by tlbwe instruction */ ppc_tlb_entry_t l2_tlb1_vsp[L2_TLB1_SIZE]; /* filled by tlbwe insructions */ /* ea = effective address if translation is an instruction address then as = MSR[IS]; else // data address translation as = MSR[DS] for all TLB entries if !TLB[entry].v then next // compare next TLB entry if as != TLB[entry].ts then next // compare next TLB entry if TLB[entry].tid == 0 then goto pid_match for all PID registers if this PID register == TLB[entry].tid then goto pid_match endfor next // no PIDs matched pid_match://translation match mask = ~(1024 << (2 * TLB[entry].tsize)) - 01 if (ea & mask) != TLB[entry].epn then next // no address match real address = TLB[entry].rpn | (ea & ~mask) // real address computed end translation --success endfor end translation tlb miss */ int ppc_effective_to_physical(uint32 addr, int flags, uint32 *result){ int i,j; uint32 mask; ppc_tlb_entry_t *entry; int tlb1_index; int pid_match = 0; i = 0; /* walk over tlb0 and tlb1 to find the entry */ while(i++ < (L2_TLB0_SIZE + L2_TLB1_SIZE)){ if(i > (L2_TLB0_SIZE - 1)){ tlb1_index = i - L2_TLB0_SIZE; entry = &l2_tlb1_vsp[tlb1_index]; } else entry = &l2_tlb0_4k[i]; if(!entry->v) continue; /* FIXME, not check ts bit now */ if(entry->ts & 0x0) continue; if(entry->tid != 0){ for(j = 0; j < 3; j++){ if(e500_mmu.pid[j] == entry->tid) break; } if(e500_mmu.pid[j] != entry->tid) continue; } if(i > (L2_TLB0_SIZE - 1)){ int k,s = 1; for(k = 0; k < entry->size; k++) s = s * 4; mask = ~((1024 * (s - 1) - 0x1) + 1024); } else mask = ~(1024 * 4 - 0x1); if(entry->size != 0xb){ if((addr & mask) != ((entry->epn << 12) & mask)) continue; *result = (entry->rpn << 12) | (addr & ~mask); // get real address } else {/*if 4G size is mapped, we will not do address check */ //fprintf(stderr,"warning:4G address is used.\n"); if(addr < (entry->epn << 12)) continue; *result = (entry->rpn << 12) | (addr - (entry->epn << 12)); // get real address } return PPC_MMU_OK; } if(ppc_exception(DATA_TLB, 0, addr)) return PPC_MMU_EXC; return PPC_MMU_FATAL; } int e500_mmu_init(){ /* the initial tlb map of real hardware */ ppc_tlb_entry_t * entry = &l2_tlb1_vsp[0]; entry->v = 1; /* entry is valid */ entry->ts = 0; /* address space 0 */ entry->tid = 0; /* TID value for shared(global) page */ entry->epn = 0xFFFFF; /* Address of last 4k byte in address space*/ entry->rpn = 0xFFFFF; /* Address of last 4k byte in address space*/ entry->size = 0x1; /* 4k byte page size */ /* usxrw should be initialized to 010101 */ entry->usxrw |= 0x15; /* Full supervisor mode access allowed */ entry->usxrw &= 0x15; /* No user mode access allowed */ entry->wimge = 0x8; /* Caching-inhibited, non-coherent,big-endian*/ entry->x = 0; /* Reserved system attributes */ entry->u = 0; /* User attribute bits */ entry->iprot = 1; /* Page is protected from invalidation */ gCPU.ccsr.ccsr = 0xFF700; e500_mmu.tlbcfg[0] = 0x4110200; e500_mmu.tlbcfg[1] = 0x101bc010; gCPU.lb_ctrl.lcrr = 0x80000008; gCPU.i2c_reg.i2csr = 0x81; gCPU.i2c_reg.i2cdfsrr = 0x10; gCPU.pic_ram.ctpr0 = 0x0000000F; gCPU.pic_global.svr = 0xFFFF; } int FASTCALL ppc_read_effective_word(uint32 addr, uint32 *result) { uint32 p; int r; if (!(r = ppc_effective_to_physical(addr, PPC_MMU_READ, &p))) { //printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr)); if((p >= GET_CCSR_BASE(gCPU.ccsr.ccsr)) && (p < (GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE))){ int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr); //printf("DBG:in %s,read CCSR,offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, gCPU.pc); if(offset >= 0x919C0 && offset <= 0x919E0){ switch(offset){ case 0x919C0: *result = gCPU.cpm_reg.cpcr; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } if(offset >= 0x2000 && offset <= 0x2E58){ switch(offset){ case 0x2E44: *result = gCPU.ddr_ctrl.err_disable; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } /** * PIC Register Address Map */ if(offset >= 0x50000 && offset <= 0x600B0){ if(offset >= 0x50000 && offset <= 0x50170){ int index = (offset - 0x50000) >> 4; if(index & 0x1) *result = gCPU.pic_ram.eidr[index >> 1]; else *result = gCPU.pic_ram.eivpr[index >> 1]; return r; } if(offset >= 0x50200 && offset <= 0x505F0){ int index = (offset - 0x50200) >> 4; if(index & 0x1) *result = gCPU.pic_ram.iidr[index >> 1]; else *result = gCPU.pic_ram.iivpr[index >> 1]; return r; } switch(offset){ case 0x60080: *result = gCPU.pic_ram.ctpr0; return r; case 0x600a0: *result = gCPU.pic_percpu.iack0; return r; default: fprintf(stderr,"in %s, error when write pic ram,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); break; } } /** * Interrupt Controller */ if(offset >= 0x90C00 && offset <= 0x90C7F){ switch(offset){ case 0x90C08: *result = gCPU.int_ctrl.sipnr_h; return r; case 0x90C0C: *result = gCPU.int_ctrl.sipnr_l; return r; case 0x90C14: *result = gCPU.int_ctrl.scprr_h; return r; case 0x90C18: *result = gCPU.int_ctrl.scprr_l; return r; case 0x90C1C: *result = gCPU.int_ctrl.simr_h; return r; case 0x90C20: *result = gCPU.int_ctrl.simr_l; return r; default: fprintf(stderr,"in %s, error when read interrupt controller,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; } } if(offset >= 0x91A00 && offset <= 0x91A3F){ int i = (0x20 & offset) >> 5; offset = 0x1f & offset; switch(offset){ case 0x0: *result = gCPU.cpm_reg.scc[i].gsmrl; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } /* CPM MUX I/O */ if(offset >= 0x91B00 && offset <= 0x91B1F){ switch(offset){ case 0x91B08: *result = gCPU.cpm_reg.mux.cmxscr; return r; case 0x91B04: *result = gCPU.cpm_reg.mux.cmxfcr; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } /* PIC Global register */ if(offset >= 0x40000 && offset <= 0x4FFF0){ switch(offset){ case 0x41000: *result = gCPU.pic_global.frr= 0x370002; /* according to 8560 manual */ return r; case 0x400a0: *result = gCPU.pic_global.iack; return r; case 0x410f0: *result = gCPU.pic_global.tfrr; return r; case 0x41020: /* source attribute register for DMA0 */ *result = gCPU.pic_global.gcr; return r; case 0x410e0: *result = gCPU.pic_global.svr; return r; case 0x41120: *result = gCPU.pic_global.gtvpr0; return r; case 0x41160: *result = gCPU.pic_global.gtvpr1; return r; case 0x41170: *result = gCPU.pic_global.gtdr1; return r; case 0x411a0: *result = gCPU.pic_global.gtvpr2; return r; case 0x411B0: *result = gCPU.pic_global.gtdr2; return r; case 0x411E0: *result = gCPU.pic_global.gtvpr3; return r; default: fprintf(stderr,"in %s, error when read global.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; //skyeye_exit(-1); } } /* DMA */ if(offset >= 0x21100 && offset <= 0x21300){ switch(offset){ case 0x21110: /* source attribute register for DMA0 */ *result = gCPU.dma.satr0; return r; case 0x21118: *result = gCPU.dma.satr0; return r; default: fprintf(stderr,"in %s, error when read dma.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; //skyeye_exit(-1); } } /* Input/Output port */ if(offset >= 0x90D00 && offset <= 0x90D70){ switch(offset){ case 0x90D00: *result = gCPU.cpm_reg.ioport.pdira; return r; case 0x90D04: *result = gCPU.cpm_reg.ioport.ppara; return r; case 0x90D08: *result = gCPU.cpm_reg.ioport.psora; return r; case 0x90D0C: *result = gCPU.cpm_reg.ioport.podra ; return r; case 0x90D10: *result = gCPU.cpm_reg.ioport.pdata; return r; case 0x90D20: *result = gCPU.cpm_reg.ioport.pdirb; return r; case 0x90D24: *result = gCPU.cpm_reg.ioport.pparb; return r; case 0x90D28: *result = gCPU.cpm_reg.ioport.psorb; return r; case 0x90D40: *result = gCPU.cpm_reg.ioport.pdirc; return r; case 0x90D44: *result = gCPU.cpm_reg.ioport.pparc; return r; case 0x90D48: *result = gCPU.cpm_reg.ioport.psorc; return r; case 0x90D60: *result = gCPU.cpm_reg.ioport.pdird; return r; case 0x90D64: *result = gCPU.cpm_reg.ioport.ppard; return r; case 0x90D68: *result = gCPU.cpm_reg.ioport.psord; return r; default: fprintf(stderr,"in %s, error when read IO port.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; //skyeye_exit(-1); } } if(offset >= 0x80000 && offset < 0x8C000){ *result = ppc_word_from_BE(*((sint32 *)&gCPU.cpm_reg.dpram[offset - 0x80000])); //printf("DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, *result,gCPU.pc); return r; } if(offset >= 0xE0000 && offset <= 0xE0020){ switch(offset){ case 0xE0000: *result = gCPU.por_conf.porpllsr; return r; case 0xE000C: *result = gCPU.por_conf.pordevsr; return r; default: fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__, addr, gCPU.pc); skyeye_exit(-1); } } switch(offset){ case 0x0: *result = gCPU.ccsr.ccsr; break; case 0xC28: *result = gCPU.law.lawbar[1]; break; case 0xC30: *result = gCPU.law.lawar[1]; case 0x90C80: *result = gCPU.sccr; break; case 0xe0e10: *result = gCPU.debug_ctrl.ddrdllcr; return r; case 0x50D4: *result = gCPU.lb_ctrl.lcrr; return r; case 0x20000: *result = gCPU.l2_reg.l2ctl; return r; case 0x8004: *result = gCPU.pci_cfg.cfg_data; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, gCPU.pc); //skyeye_exit(-1); } } else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr - 1 + boot_romSize ))) *result = ppc_word_from_BE(*((int *)&boot_rom[p - boot_rom_start_addr])); else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size))) *result = ppc_word_from_BE(*((int *)&init_ram[p - init_ram_start_addr])); else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){ *result = ppc_word_from_BE(*((int *)&ddr_ram[p])); } else{ fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc); //skyeye_exit(-1); } } return r; } int FASTCALL ppc_read_effective_half(uint32 addr, uint16 *result) { uint32 p; int r; if (!(r = ppc_effective_to_physical(addr, PPC_MMU_READ, &p))) { //printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr)); if((p >= GET_CCSR_BASE(gCPU.ccsr.ccsr)) && (p < (GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE))){ int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr); //printf("DBG:read CCSR,offset=0x%x,pc=0x%x\n", offset, gCPU.pc); if(offset >= 0x919C0 && offset <= 0x919E0){ switch(offset){ case 0x919C0: *result = gCPU.cpm_reg.cpcr; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } if((offset >= 0x80000) && (offset < 0x8C000)){ *result = ppc_half_from_BE(*((sint16 *)&gCPU.cpm_reg.dpram[offset - 0x80000])); return r; } if(offset >= 0x91A00 && offset <= 0x91A3F){ int i = (0x20 & offset) >> 5; offset = 0x1f & offset; switch(offset){ case 0x0: *result = gCPU.cpm_reg.scc[i].gsmrl; return r; case 0x4: *result = gCPU.cpm_reg.scc[i].gsmrh; return r; case 0x8: *result = gCPU.cpm_reg.scc[i].psmr; return r; case 0xE: *result = gCPU.cpm_reg.scc[i].dsr; return r; case 0x14: *result = gCPU.cpm_reg.scc[i].sccm; return r; case 0x10: /* W1C */ *result = gCPU.cpm_reg.scc[i].scce; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } if(offset >= 0xE0000 && offset <= 0xE0020){ switch(offset){ case 0xE0000: *result = gCPU.por_conf.porpllsr; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } switch(offset){ case 0x0: *result = gCPU.ccsr.ccsr; break; case 0x90C80: *result = gCPU.sccr; break; case 0x8004: *result = gCPU.pci_cfg.cfg_data; break; case 0x8006: *result = gCPU.pci_cfg.cfg_data; break; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc); //skyeye_exit(-1); } } else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr - 1 + boot_romSize ))) *result = ppc_half_from_BE(*((sint16 *)&boot_rom[p - boot_rom_start_addr])); else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size))) *result = ppc_half_from_BE(*((sint16 *)&init_ram[p - init_ram_start_addr])); else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))) { *result = ppc_half_from_BE(*((sint16 *)&ddr_ram[p])); } else{ fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc); //skyeye_exit(-1); } } return r; } int FASTCALL ppc_read_effective_byte(uint32 addr, uint8 *result) { uint32 p; int r; if (!(r = ppc_effective_to_physical(addr, PPC_MMU_READ, &p))) { //printf("\nDBG:in %s,addr=0x%x,p=0x%x\n", __FUNCTION__, addr,p); //printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr)); if((p >= GET_CCSR_BASE(gCPU.ccsr.ccsr)) && (p < (GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE))){ int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr); //printf("DBG:read CCSR,offset=0x%x,pc=0x%x\n", offset, gCPU.pc); if(offset >= 0x919C0 && offset <= 0x919E0){ switch(offset){ case 0x919C0: *result = gCPU.cpm_reg.cpcr; return r; default: fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__, addr, gCPU.pc); skyeye_exit(-1); } } if(offset >= 0x80000 && offset < 0x8C000){ *result = *((sint16 *)&gCPU.cpm_reg.dpram[offset - 0x80000]); //printf("DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, *result,gCPU.pc); return r; } if(offset >= 0xE0000 && offset <= 0xE0020){ switch(offset){ case 0xE0000: *result = gCPU.por_conf.porpllsr; return r; default: fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__, addr, gCPU.pc); skyeye_exit(-1); } } switch(offset){ case 0x0: *result = gCPU.ccsr.ccsr; break; case 0x90C80: *result = gCPU.sccr; break; case 0x300C: *result = gCPU.i2c_reg.i2csr; fprintf(prof_file,"KSDBG:read i2csr result=0x%x\n", *result); return r; case 0x8006: *result = gCPU.pci_cfg.cfg_data; return r; default: return r; //fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__,addr,gCPU.pc); //skyeye_exit(-1); } } else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr - 1 + boot_romSize ))) *result = *((byte *)&boot_rom[p - boot_rom_start_addr]); else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size))) *result = *((byte *)&init_ram[p - init_ram_start_addr]); else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){ *result = *((byte *)&ddr_ram[p]); } else{ fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc); skyeye_exit(-1); } } return r; } int FASTCALL ppc_write_effective_word(uint32 addr, uint32 data) { uint32 p; int r; if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) { if(p >= GET_CCSR_BASE(gCPU.ccsr.ccsr) && p <(GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE)){ int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr); //printf("DBG:write to CCSR,value=0x%x,offset=0x%x,pc=0x%x\n", data, offset,gCPU.pc); if(offset >= 0xC08 && offset <= 0xCF0){ if(offset & 0x8){ gCPU.law.lawbar[(offset - 0xC08)/0x20] = data; }else{ gCPU.law.lawar[(offset - 0xC10)/0x20] = data; } return r; } if(offset >= 0x2000 && offset <= 0x2E58){ switch(offset){ case 0x2E44: gCPU.ddr_ctrl.err_disable = data; return r; default: fprintf(stderr,"in %s, error when write ddr_ctrl,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } if(offset >= 0x5000 && offset <= 0x50D4){ if(offset >= 0x5000 && offset <= 0x5038){ gCPU.lb_ctrl.br[(offset - 0x5000)/0x8] = data; return r; } #if 0 switch(offset){ case 0x50D0: gCPU.lb_ctrl.lbcr = data; return r; default: fprintf(stderr,"in %s, error when read CCSR.addr=0x%x, \ pc=0x%x\n",__FUNCTION__, addr, gCPU.pc); skyeye_exit(-1); } #endif fprintf(stderr,"in %s, error when write lb_ctrl.addr=0x%x, \ pc=0x%x\n",__FUNCTION__, addr, gCPU.pc); return r; } /* DMA */ if(offset >= 0x21100 && offset <= 0x21300){ switch(offset){ case 0x21110: /* source attribute register for DMA0 */ gCPU.dma.satr0 = data; return r; case 0x21118: gCPU.dma.satr0 = data; return r; default: fprintf(stderr,"in %s, error when write dma.addr=0x%x, \ pc=0x%x\n",__FUNCTION__, addr, gCPU.pc); return r; //skyeye_exit(-1); } } /** * PIC Register Address Map */ if(offset >= 0x50000 && offset <= 0x600B0){ if(offset >= 0x50000 && offset <= 0x50170){ int index = (offset - 0x50000) >> 4; if(index & 0x1) gCPU.pic_ram.eidr[index >> 1] = data; else gCPU.pic_ram.eivpr[index >> 1] = data; return r; } if(offset >= 0x50200 && offset <= 0x505F0){ int index = (offset - 0x50200) >> 4; return r; } switch(offset){ case 0x60080: gCPU.pic_ram.ctpr0 = data; return r; default: fprintf(stderr,"in %s, error when write pic ram,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; } } /** * Interrupt Controller */ if(offset >= 0x90C00 && offset <= 0x90C7F){ switch(offset){ case 0x90C08: /* W1C */ gCPU.int_ctrl.sipnr_h &= ~data; return r; case 0x90C0C: /* W1C */ gCPU.int_ctrl.sipnr_l &= ~data; return r; case 0x90C14: gCPU.int_ctrl.scprr_h = data; return r; case 0x90C18: gCPU.int_ctrl.scprr_l = data; return r; case 0x90C1C: gCPU.int_ctrl.simr_h = data; return r; case 0x90C20: gCPU.int_ctrl.simr_l = data; return r; default: fprintf(stderr,"in %s, error when write interrupt controller,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; } } if(offset >= 0x919C0 && offset <= 0x919E0){ switch(offset){ case 0x919C0: gCPU.cpm_reg.cpcr = data; /* set FLG bit to zero, that means we are ready for new command*/ /* get sub block code */ if((0x1f & (gCPU.cpm_reg.cpcr >> 21)) == 0x4){ ;/* we */ if((0xf & gCPU.cpm_reg.cpcr) == 0x0){ /* INIT Rx and Tx Param in SCC1 */ } } gCPU.cpm_reg.cpcr &= ~(1 << 16); return r; default: fprintf(stderr,"in %s, error when write cpm,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; } } if(offset >= 0x91A00 && offset <= 0x91A3F){ int i = (0x20 & offset) >> 5; offset = 0x1f & offset; switch(offset){ case 0x0: gCPU.cpm_reg.scc[i].gsmrl = data; if(gCPU.cpm_reg.scc[i].gsmrl & 0x00000020) ; /* Enable Receive */ if(gCPU.cpm_reg.scc[i].gsmrl & 0x00000010) ; /* Enable Transmit */ return r; case 0x4: gCPU.cpm_reg.scc[i].gsmrh = data; return r; case 0x8: gCPU.cpm_reg.scc[i].psmr = data; return r; case 0xE: gCPU.cpm_reg.scc[i].dsr = data; return r; case 0x14: gCPU.cpm_reg.scc[i].sccm = data; return r; case 0x10: /* W1C */ gCPU.cpm_reg.scc[i].scce &= ~data; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } /* CPM MUX I/O */ if(offset >= 0x91B00 && offset <= 0x91B1F){ switch(offset){ case 0x91B04: gCPU.cpm_reg.mux.cmxfcr = data; return r; case 0x91B08: gCPU.cpm_reg.mux.cmxscr = data; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } /* Input/Output port */ if(offset >= 0x90D00 && offset <= 0x90D70){ switch(offset){ case 0x90D00: gCPU.cpm_reg.ioport.pdira = data; return r; case 0x90D04: gCPU.cpm_reg.ioport.ppara = data; return r; case 0x90D08: gCPU.cpm_reg.ioport.psora = data; return r; case 0x90D0C: gCPU.cpm_reg.ioport.podra = data; return r; case 0x90D10: gCPU.cpm_reg.ioport.pdata = data; return r; case 0x90D20: gCPU.cpm_reg.ioport.pdirb = data; return r; case 0x90D24: gCPU.cpm_reg.ioport.pparb = data; return r; case 0x90D28: gCPU.cpm_reg.ioport.psorb = data; return r; case 0x90D40: gCPU.cpm_reg.ioport.pdirc = data; return r; case 0x90D44: gCPU.cpm_reg.ioport.pparc = data; return r; case 0x90D48: gCPU.cpm_reg.ioport.psorc = data; return r; case 0x90D60: gCPU.cpm_reg.ioport.pdird = data; return r; case 0x90D64: gCPU.cpm_reg.ioport.ppard = data; return r; case 0x90D68: gCPU.cpm_reg.ioport.psord = data; return r; default: fprintf(stderr,"in %s, error when write io port.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; //skyeye_exit(-1); } } /* BRG */ if(offset >= 0x919F0 && offset <= 0x919FC){ gCPU.cpm_reg.brgc[(offset - 0x919F0)/4] = data; return r; } if(offset >= 0x80000 && offset < 0x8C000){ //fprintf(prof_file,"DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, data, gCPU.pc); *((sint32 *)&gCPU.cpm_reg.dpram[offset - 0x80000]) = ppc_word_to_BE(data); return r; } if(offset >= 0x8C00 && offset <= 0x8DFC) { switch(offset){ case 0x8C20: gCPU.pci_atmu.potar1 = data; return r; case 0x8C24: gCPU.pci_atmu.potear1 = data; return r; case 0x8C28: gCPU.pci_atmu.powbar1 = data; return r; case 0x8C2C: gCPU.pci_atmu.reserv1 = data; return r; case 0x8C30: gCPU.pci_atmu.powar1 = data; return r; default: fprintf(stderr,"in %s, error when write to PCI_ATMU.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc); //skyeye_exit(-1); return r; } } if(offset >= 0x40000 && offset <= 0x4FFF0){ switch(offset){ case 0x41020: /* source a ttribute register for DMA0 */ gCPU.pic_global.gcr = data; return r; case 0x410e0: gCPU.pic_global.svr = data; return r; case 0x41120: gCPU.pic_global.gtvpr0 = data; return r; case 0x41130: gCPU.pic_global.gtdr0 = data; return r; case 0x41160: gCPU.pic_global.gtvpr1 = data; return r; case 0x41170: gCPU.pic_global.gtdr1 = data; return r; case 0x411a0: gCPU.pic_global.gtvpr2 = data; return r; case 0x411B0: gCPU.pic_global.gtdr2 = data; return r; case 0x411E0: gCPU.pic_global.gtvpr3 = data; return r; case 0x411F0: gCPU.pic_global.gtdr3 = data; return r; default: fprintf(stderr,"in %s, error when write global.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); return r; //skyeye_ex it(-1); } } switch(offset){ case 0x0: gCPU.ccsr.ccsr = data; break; case 0x90C80: gCPU.sccr = data; break; case 0x50D4: gCPU.lb_ctrl.lcrr = data; return r; case 0x3008: gCPU.i2c_reg.i2ccr = data; return r; case 0xe0e10: gCPU.debug_ctrl.ddrdllcr = data; return r; case 0x8000: gCPU.pci_cfg.cfg_addr = data; return r; case 0x8004: gCPU.pci_cfg.cfg_data = data; return r; default: fprintf(stderr,"in %s, error when write to CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); //skyeye_exit(-1); } } else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr + boot_romSize ))) *((int *)&boot_rom[p - boot_rom_start_addr]) = ppc_word_to_BE(data); else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size))) *((int *)&init_ram[p - init_ram_start_addr]) = ppc_word_to_BE(data); else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){ *((int *)&ddr_ram[p]) = ppc_word_to_BE(data); } else{ fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc); //skyeye_exit(-1); } } return r; } int FASTCALL ppc_write_effective_half(uint32 addr, uint16 data) { uint32 p; int r; if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) { //printf("DBG:in %s,addr=0x%x,p=0x%x, data=0x%x\n", __FUNCTION__, addr,p, data); //printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr)); if(p >= GET_CCSR_BASE(gCPU.ccsr.ccsr) && p <(GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE)){ int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr); //printf("DBG:write to CCSR,value=0x%x,offset=0x%x,pc=0x%x\n", data, offset,gCPU.pc); if(offset >= 0xC08 && offset <= 0xCF0){ if(offset & 0x8){ gCPU.law.lawbar[(offset - 0xC08)/0x20] = data; }else{ gCPU.law.lawar[(offset - 0xC10)/0x20] = data; } return r; } if(offset >= 0x5000 && offset <= 0x5038){ gCPU.lb_ctrl.br[(offset - 0x5000)/0x8] = data; return r; } if(offset >= 0x91A00 && offset <= 0x91A3F){ int i = (0x20 & offset) >> 5; offset = 0x1f & offset; switch(offset){ case 0x0: gCPU.cpm_reg.scc[i].gsmrl = data; return r; case 0x4: gCPU.cpm_reg.scc[i].gsmrh = data; return r; case 0x8: gCPU.cpm_reg.scc[i].psmr = data; return r; case 0xE: gCPU.cpm_reg.scc[i].dsr = data; return r; case 0x14: gCPU.cpm_reg.scc[i].sccm = data; return r; case 0x10: /* W1C */ gCPU.cpm_reg.scc[i].scce &= ~data; return r; default: fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \ pc=0x%x\n",__FUNCTION__, offset, gCPU.pc); skyeye_exit(-1); } } if(offset >= 0x919C0 && offset <= 0x919E0){ switch(offset){ case 0x919C0: gCPU.cpm_reg.cpcr = data; return r; default: fprintf(stderr,"in %s, error when write to CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc); //skyeye_exit(-1); } } if(offset >= 0x80000 && offset < 0x8C000){ //fprintf(prof_file,"DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, data, gCPU.pc); *((sint16 *)&gCPU.cpm_reg.dpram[offset - 0x80000]) = ppc_half_to_BE(data); return r; } switch(offset){ case 0x0: gCPU.ccsr.ccsr = data; break; case 0x90C00: gCPU.int_ctrl.sicr = data; break; case 0x90C80: gCPU.sccr = data; break; case 0x8004: gCPU.pci_cfg.cfg_data = data; break; case 0x8006: gCPU.pci_cfg.cfg_data = data; break; default: fprintf(stderr,"in %s, error when write to CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc); //skyeye_exit(-1); } } else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr + boot_romSize ))) *((sint16 *)&boot_rom[p - boot_rom_start_addr]) = ppc_half_to_BE(data); else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size))) *((sint16 *)&init_ram[p - init_ram_start_addr]) = ppc_half_to_BE(data); else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){ *((sint16 *)&ddr_ram[p]) = ppc_half_to_BE(data); } else{ fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc); //skyeye_exit(-1); } } return r; } int FASTCALL ppc_write_effective_byte(uint32 addr, uint8 data) { uint32 p; int r; if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) { //printf("DBG:in %s,addr=0x%x,p=0x%x, data=0x%x, pc=0x%x\n", __FUNCTION__, addr,p, data, gCPU.pc); //printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr)); if(p >= GET_CCSR_BASE(gCPU.ccsr.ccsr) && p <(GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE)){ int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr); //printf("DBG:write to CCSR,value=0x%x,offset=0x%x\n", data, offset); if(offset >= 0xC08 && offset <= 0xCF0){ if(offset & 0x8){ gCPU.law.lawbar[(offset - 0xC08)/0x20] = data; }else{ gCPU.law.lawar[(offset - 0xC10)/0x20] = data; } return r; } if(offset >= 0x80000 && offset < 0x8C000){ //fprintf(prof_file,"DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, data, gCPU.pc); *((byte *)&gCPU.cpm_reg.dpram[offset - 0x80000]) = data; return r; } switch(offset){ case 0x0: gCPU.ccsr.ccsr = data; break; case 0x3000: gCPU.i2c_reg.i2cadr = data; return r; case 0x3004: gCPU.i2c_reg.i2cfdr = data; return r; case 0x3008: gCPU.i2c_reg.i2ccr = data; return r; case 0x300C: gCPU.i2c_reg.i2csr = data; return r; case 0x3010: gCPU.i2c_reg.i2cdr = data; /* set bit of MIF */ gCPU.i2c_reg.i2csr |= 0x02; return r; case 0x3014: gCPU.i2c_reg.i2cdfsrr = data; return r; case 0x8004: gCPU.pci_cfg.cfg_data = data; return r; case 0x8005: gCPU.pci_cfg.cfg_data = data; return r; default: fprintf(stderr,"in %s, error when write to CCSR.addr=0x%x,pc=0x%x\n", __FUNCTION__,addr,gCPU.pc); skyeye_exit(-1); } } else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr + boot_romSize ))) *((byte *)&boot_rom[p - boot_rom_start_addr]) = data; else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size))) *((byte *)&init_ram[p - init_ram_start_addr]) = data; else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){ *((byte *)&ddr_ram[p]) = data; } else{ fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc ); skyeye_exit(-1); } } return r; } void ppc_mmu_tlb_invalidate() { gCPU.effective_code_page = 0xffffffff; } /* pagetable: min. 2^10 (64k) PTEGs PTEG = 64byte The page table can be any size 2^n where 16 <= n <= 25. A PTEG contains eight PTEs of eight bytes each; therefore, each PTEG is 64 bytes long. */ bool FASTCALL ppc_mmu_set_sdr1(uint32 newval, bool quiesce) { /* if (newval == gCPU.sdr1)*/ quiesce = false; PPC_MMU_TRACE("new pagetable: sdr1 = 0x%08x\n", newval); uint32 htabmask = SDR1_HTABMASK(newval); uint32 x = 1; uint32 xx = 0; int n = 0; while ((htabmask & x) && (n < 9)) { n++; xx|=x; x<<=1; } if (htabmask & ~xx) { PPC_MMU_TRACE("new pagetable: broken htabmask (%05x)\n", htabmask); return false; } uint32 htaborg = SDR1_HTABORG(newval); if (htaborg & xx) { PPC_MMU_TRACE("new pagetable: broken htaborg (%05x)\n", htaborg); return false; } gCPU.pagetable_base = htaborg<<16; gCPU.sdr1 = newval; gCPU.pagetable_hashmask = ((xx<<10)|0x3ff); PPC_MMU_TRACE("new pagetable: sdr1 accepted\n"); PPC_MMU_TRACE("number of pages: 2^%d pagetable_start: 0x%08x size: 2^%d\n", n+13, gCPU.pagetable_base, n+16); if (quiesce) { //prom_quiesce(); } return true; } bool FASTCALL ppc_mmu_page_create(uint32 ea, uint32 pa) { uint32 sr = gCPU.sr[EA_SR(ea)]; uint32 page_index = EA_PageIndex(ea); // 16 bit uint32 VSID = SR_VSID(sr); // 24 bit uint32 api = EA_API(ea); // 6 bit (part of page_index) uint32 hash1 = (VSID ^ page_index); uint32 pte, pte2; uint32 h = 0; int j; for (j=0; j<2; j++) { uint32 pteg_addr = ((hash1 & gCPU.pagetable_hashmask)<<6) | gCPU.pagetable_base; int i; for (i=0; i<8; i++) { if (ppc_read_physical_word(pteg_addr, &pte)) { PPC_MMU_ERR("read physical in address translate failed\n"); return false; } if (!(pte & PTE1_V)) { // free pagetable entry found pte = PTE1_V | (VSID << 7) | h | api; pte2 = (PA_RPN(pa) << 12) | 0; if (ppc_write_physical_word(pteg_addr, pte) || ppc_write_physical_word(pteg_addr+4, pte2)) { return false; } else { // ok return true; } } pteg_addr+=8; } hash1 = ~hash1; h = PTE1_H; } return false; } inline bool FASTCALL ppc_mmu_page_free(uint32 ea) { return true; } inline int FASTCALL ppc_direct_physical_memory_handle(uint32 addr, byte *ptr) { if (addr < boot_romSize) { ptr = &boot_rom[addr]; return PPC_MMU_OK; } return PPC_MMU_FATAL; } int FASTCALL ppc_direct_effective_memory_handle(uint32 addr, byte *ptr) { uint32 ea; int r; if (!((r = ppc_effective_to_physical(addr, PPC_MMU_READ, &ea)))) { return ppc_direct_physical_memory_handle(ea, ptr); } return r; } int FASTCALL ppc_direct_effective_memory_handle_code(uint32 addr, byte *ptr) { uint32 ea; int r; if (!((r = ppc_effective_to_physical(addr, PPC_MMU_READ | PPC_MMU_CODE, &ea)))) { return ppc_direct_physical_memory_handle(ea, ptr); } return r; } inline int FASTCALL ppc_read_physical_qword(uint32 addr, Vector_t *result) { if (addr < boot_romSize) { // big endian VECT_D(*result,0) = ppc_dword_from_BE(*((uint64*)(boot_rom+addr))); VECT_D(*result,1) = ppc_dword_from_BE(*((uint64*)(boot_rom+addr+8))); return PPC_MMU_OK; } return io_mem_read128(addr, (uint128 *)result); } inline int FASTCALL ppc_read_physical_dword(uint32 addr, uint64 *result) { if (addr < boot_romSize) { // big endian *result = ppc_dword_from_BE(*((uint64*)(boot_rom+addr))); return PPC_MMU_OK; } int ret = io_mem_read64(addr, result); *result = ppc_bswap_dword(result); return ret; } int FASTCALL ppc_read_physical_word(uint32 addr, uint32 *result) { if (addr < boot_romSize) { // big endian *result = ppc_word_from_BE(*((uint32*)(boot_rom+addr))); return PPC_MMU_OK; } int ret = io_mem_read(addr, result, 4); *result = ppc_bswap_word(result); return ret; } inline int FASTCALL ppc_read_physical_half(uint32 addr, uint16 *result) { if (addr < boot_romSize) { // big endian *result = ppc_half_from_BE(*((uint16*)(boot_rom+addr))); return PPC_MMU_OK; } uint32 r; int ret = io_mem_read(addr, r, 2); *result = ppc_bswap_half(r); return ret; } inline int FASTCALL ppc_read_physical_byte(uint32 addr, uint8 *result) { if (addr < boot_romSize) { // big endian *result = boot_rom[addr]; return PPC_MMU_OK; } uint32 r; int ret = io_mem_read(addr, r, 1); *result = r; return ret; } inline int FASTCALL ppc_read_effective_code(uint32 addr, uint32 *result) { if (addr & 3) { // EXC..bla return PPC_MMU_FATAL; } uint32 p; int r; if (!((r=ppc_effective_to_physical(addr, PPC_MMU_READ | PPC_MMU_CODE, &p)))) { return ppc_read_physical_word(p, result); } return r; } inline int FASTCALL ppc_read_effective_qword(uint32 addr, Vector_t *result) { uint32 p; int r; addr &= ~0x0f; if (!(r = ppc_effective_to_physical(addr, PPC_MMU_READ, &p))) { return ppc_read_physical_qword(p, result); } return r; } inline int FASTCALL ppc_read_effective_dword(uint32 addr, uint64 *result) { uint32 p; int r; if (!(r = ppc_effective_to_physical(addr, PPC_MMU_READ, &p))) { #if 0 if (EA_Offset(addr) > 4088) { // read overlaps two pages.. tricky byte *r1, *r2; byte b[14]; ppc_effective_to_physical((addr & ~0xfff)+4089, PPC_MMU_READ, &p); if ((r = ppc_direct_physical_memory_handle(p, r1))) return r; if ((r = ppc_effective_to_physical((addr & ~0xfff)+4096, PPC_MMU_READ, &p))) return r; if ((r = ppc_direct_physical_memory_handle(p, r2))) return r; memmove(&b[0], r1, 7); memmove(&b[7], r2, 7); memmove(&result, &b[EA_Offset(addr)-4089], 8); result = ppc_dword_from_BE(result); return PPC_MMU_OK; } else { return ppc_read_physical_dword(p, result); } #endif } return r; } inline int FASTCALL ppc_write_physical_qword(uint32 addr, Vector_t *data) { if (addr < boot_romSize) { // big endian *((uint64*)(boot_rom+addr)) = ppc_dword_to_BE(VECT_D(*data,0)); *((uint64*)(boot_rom+addr+8)) = ppc_dword_to_BE(VECT_D(*data,1)); return PPC_MMU_OK; } if (io_mem_write128(addr, (uint128 *)data) == IO_MEM_ACCESS_OK) { return PPC_MMU_OK; } else { return PPC_MMU_FATAL; } } inline int FASTCALL ppc_write_physical_dword(uint32 addr, uint64 data) { if (addr < boot_romSize) { // big endian *((uint64*)(boot_rom+addr)) = ppc_dword_to_BE(data); return PPC_MMU_OK; } if (io_mem_write64(addr, ppc_bswap_dword(data)) == IO_MEM_ACCESS_OK) { return PPC_MMU_OK; } else { return PPC_MMU_FATAL; } } inline int FASTCALL ppc_write_physical_word(uint32 addr, uint32 data) { if (addr < boot_romSize) { // big endian *((uint32*)(boot_rom+addr)) = ppc_word_to_BE(data); return PPC_MMU_OK; } return io_mem_write(addr, ppc_bswap_word(data), 4); } inline int FASTCALL ppc_write_effective_qword(uint32 addr, Vector_t data) { uint32 p; int r; addr &= ~0x0f; if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) { return ppc_write_physical_qword(p, &data); } return r; } inline int FASTCALL ppc_write_effective_dword(uint32 addr, uint64 data) { uint32 p; int r; if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) { if (EA_Offset(addr) > 4088) { // write overlaps two pages.. tricky byte *r1, *r2; byte b[14]; ppc_effective_to_physical((addr & ~0xfff)+4089, PPC_MMU_WRITE, &p); if ((r = ppc_direct_physical_memory_handle(p, r1))) return r; if ((r = ppc_effective_to_physical((addr & ~0xfff)+4096, PPC_MMU_WRITE, &p))) return r; if ((r = ppc_direct_physical_memory_handle(p, r2))) return r; data = ppc_dword_to_BE(data); memmove(&b[0], r1, 7); memmove(&b[7], r2, 7); memmove(&b[EA_Offset(addr)-4089], &data, 8); memmove(r1, &b[0], 7); memmove(r2, &b[7], 7); return PPC_MMU_OK; } else { return ppc_write_physical_dword(p, data); } } return r; } /*************************************************************************** * DMA Interface */ bool ppc_dma_write(uint32 dest, const void *src, uint32 size) { if (dest > boot_romSize || (dest+size) > boot_romSize) return false; byte *ptr; ppc_direct_physical_memory_handle(dest, ptr); memcpy(ptr, src, size); return true; } bool ppc_dma_read(void *dest, uint32 src, uint32 size) { if (src > boot_romSize || (src+size) > boot_romSize) return false; byte *ptr; ppc_direct_physical_memory_handle(src, ptr); memcpy(dest, ptr, size); return true; } bool ppc_dma_set(uint32 dest, int c, uint32 size) { if (dest > boot_romSize || (dest+size) > boot_romSize) return false; byte *ptr; ppc_direct_physical_memory_handle(dest, ptr); memset(ptr, c, size); return true; } /*************************************************************************** * DEPRECATED prom interface */ bool ppc_prom_set_sdr1(uint32 newval, bool quiesce) { return ppc_mmu_set_sdr1(newval, quiesce); } bool ppc_prom_effective_to_physical(uint32 *result, uint32 ea) { return ppc_effective_to_physical(ea, PPC_MMU_READ|PPC_MMU_SV|PPC_MMU_NO_EXC, result) == PPC_MMU_OK; } bool ppc_prom_page_create(uint32 ea, uint32 pa) { uint32 sr = gCPU.sr[EA_SR(ea)]; uint32 page_index = EA_PageIndex(ea); // 16 bit uint32 VSID = SR_VSID(sr); // 24 bit uint32 api = EA_API(ea); // 6 bit (part of page_index) uint32 hash1 = (VSID ^ page_index); uint32 pte, pte2; uint32 h = 0; int j; for (j=0; j<2; j++) { uint32 pteg_addr = ((hash1 & gCPU.pagetable_hashmask)<<6) | gCPU.pagetable_base; int i; for (i=0; i<8; i++) { if (ppc_read_physical_word(pteg_addr, &pte)) { PPC_MMU_ERR("read physical in address translate failed\n"); return false; } if (!(pte & PTE1_V)) { // free pagetable entry found pte = PTE1_V | (VSID << 7) | h | api; pte2 = (PA_RPN(pa) << 12) | 0; if (ppc_write_physical_word(pteg_addr, pte) || ppc_write_physical_word(pteg_addr+4, pte2)) { return false; } else { // ok return true; } } pteg_addr+=8; } hash1 = ~hash1; h = PTE1_H; } return false; } bool ppc_prom_page_free(uint32 ea) { return true; } /*************************************************************************** * MMU Opcodes */ #include "ppc_dec.h" /* * dcbz Data Cache Clear to Zero * .464 */ void ppc_opc_dcbz() { #ifdef E500 //printf("DBG:In %s, for e500,cache is not implemented.\n",__FUNCTION__); //PPC_L1_CACHE_LINE_SIZE int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); // assert rD=0 uint32 a = (rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]; // bytes of per Cache line is 32 bytes int i = 0; for(; i < 32; i += 4) ppc_write_effective_word(a + i, 0); #else //PPC_L1_CACHE_LINE_SIZE int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); // assert rD=0 uint32 a = (rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]; // BAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ppc_write_effective_dword(a, 0) || ppc_write_effective_dword(a+8, 0) || ppc_write_effective_dword(a+16, 0) || ppc_write_effective_dword(a+24, 0); #endif } void ppc_opc_dcbtls(){ #ifdef E500 //printf("DBG:In %s, for e500,cache is not implemented.\n",__FUNCTION__); #else fprintf(stderr,"In %s, cache is not implemented.\n",__FUNCTION__); #endif } /* * lbz Load Byte and Zero * .521 */ void ppc_opc_lbz() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint8 r; int ret = ppc_read_effective_byte((rA?gCPU.gpr[rA]:0)+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; } } /* * lbzu Load Byte and Zero with Update * .522 */ void ppc_opc_lbzu() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); // FIXME: check rA!=0 && rA!=rD uint8 r; int ret = ppc_read_effective_byte(gCPU.gpr[rA]+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; gCPU.gpr[rD] = r; } } /* * lbzux Load Byte and Zero with Update Indexed * .523 */ void ppc_opc_lbzux() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); // FIXME: check rA!=0 && rA!=rD uint8 r; int ret = ppc_read_effective_byte(gCPU.gpr[rA]+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; gCPU.gpr[rD] = r; } } /* * lbzx Load Byte and Zero Indexed * .524 */ void ppc_opc_lbzx() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint8 r; int ret = ppc_read_effective_byte((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; } } /* * lfd Load Floating-Point Double * .530 */ void ppc_opc_lfd() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frD, rA, imm); uint64 r; int ret = ppc_read_effective_dword((rA?gCPU.gpr[rA]:0)+imm, &r); if (ret == PPC_MMU_OK) { gCPU.fpr[frD] = r; } } /* * lfdu Load Floating-Point Double with Update * .531 */ void ppc_opc_lfdu() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frD, rA, imm); // FIXME: check rA!=0 uint64 r; int ret = ppc_read_effective_dword(gCPU.gpr[rA]+imm, &r); if (ret == PPC_MMU_OK) { gCPU.fpr[frD] = r; gCPU.gpr[rA] += imm; } } /* * lfdux Load Floating-Point Double with Update Indexed * .532 */ void ppc_opc_lfdux() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, rA, rB); // FIXME: check rA!=0 uint64 r; int ret = ppc_read_effective_dword(gCPU.gpr[rA]+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; gCPU.fpr[frD] = r; } } /* * lfdx Load Floating-Point Double Indexed * .533 */ void ppc_opc_lfdx() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, rA, rB); uint64 r; int ret = ppc_read_effective_dword((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.fpr[frD] = r; } } /* * lfs Load Floating-Point Single * .534 */ void ppc_opc_lfs() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frD, rA, imm); uint32 r; int ret = ppc_read_effective_word((rA?gCPU.gpr[rA]:0)+imm, &r); if (ret == PPC_MMU_OK) { ppc_single s; ppc_double d; ppc_fpu_unpack_single(&s, r); ppc_fpu_single_to_double(&s, &d); ppc_fpu_pack_double(&d, &(gCPU.fpr[frD])); } } /* * lfsu Load Floating-Point Single with Update * .535 */ void ppc_opc_lfsu() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frD, rA, imm); // FIXME: check rA!=0 uint32 r; int ret = ppc_read_effective_word(gCPU.gpr[rA]+imm, &r); if (ret == PPC_MMU_OK) { ppc_single s; ppc_double d; ppc_fpu_unpack_single(&s, r); ppc_fpu_single_to_double(&s, &d); ppc_fpu_pack_double(&d, &(gCPU.fpr[frD])); gCPU.gpr[rA] += imm; } } /* * lfsux Load Floating-Point Single with Update Indexed * .536 */ void ppc_opc_lfsux() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, rA, rB); // FIXME: check rA!=0 uint32 r; int ret = ppc_read_effective_word(gCPU.gpr[rA]+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; ppc_single s; ppc_double d; ppc_fpu_unpack_single(&s, r); ppc_fpu_single_to_double(&s, &d); ppc_fpu_pack_double(&d, &(gCPU.fpr[frD])); } } /* * lfsx Load Floating-Point Single Indexed * .537 */ void ppc_opc_lfsx() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, rA, rB); uint32 r; int ret = ppc_read_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { ppc_single s; ppc_double d; ppc_fpu_unpack_single(&s, r); ppc_fpu_single_to_double(&s, &d); ppc_fpu_pack_double(&d, &(gCPU.fpr[frD])); } } /* * lha Load Half Word Algebraic * .538 */ void ppc_opc_lha() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint16 r; int ret = ppc_read_effective_half((rA?gCPU.gpr[rA]:0)+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = (r&0x8000)?(r|0xffff0000):r; } } /* * lhau Load Half Word Algebraic with Update * .539 */ void ppc_opc_lhau() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint16 r; // FIXME: rA != 0 int ret = ppc_read_effective_half(gCPU.gpr[rA]+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; gCPU.gpr[rD] = (r&0x8000)?(r|0xffff0000):r; } } /* * lhaux Load Half Word Algebraic with Update Indexed * .540 */ void ppc_opc_lhaux() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint16 r; // FIXME: rA != 0 int ret = ppc_read_effective_half(gCPU.gpr[rA]+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; gCPU.gpr[rD] = (r&0x8000)?(r|0xffff0000):r; } } /* * lhax Load Half Word Algebraic Indexed * .541 */ void ppc_opc_lhax() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint16 r; // FIXME: rA != 0 int ret = ppc_read_effective_half((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = (r&0x8000) ? (r|0xffff0000):r; } } /* * lhbrx Load Half Word Byte-Reverse Indexed * .542 */ void ppc_opc_lhbrx() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint16 r; int ret = ppc_read_effective_half((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = ppc_bswap_half(r); } } /* * lhz Load Half Word and Zero * .543 */ void ppc_opc_lhz() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint16 r; int ret = ppc_read_effective_half((rA?gCPU.gpr[rA]:0)+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; } } /* * lhzu Load Half Word and Zero with Update * .544 */ void ppc_opc_lhzu() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint16 r; // FIXME: rA!=0 int ret = ppc_read_effective_half(gCPU.gpr[rA]+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; gCPU.gpr[rA] += imm; } } /* * lhzux Load Half Word and Zero with Update Indexed * .545 */ void ppc_opc_lhzux() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint16 r; // FIXME: rA != 0 int ret = ppc_read_effective_half(gCPU.gpr[rA]+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; gCPU.gpr[rD] = r; } } /* * lhzx Load Half Word and Zero Indexed * .546 */ void ppc_opc_lhzx() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint16 r; int ret = ppc_read_effective_half((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; } } /* * lmw Load Multiple Word * .547 */ void ppc_opc_lmw() { int rD, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint32 ea = (rA ? gCPU.gpr[rA] : 0) + imm; while (rD <= 31) { if (ppc_read_effective_word(ea, &(gCPU.gpr[rD]))) { return; } rD++; ea += 4; } } /* * lswi Load String Word Immediate * .548 */ void ppc_opc_lswi() { int rA, rD, NB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, NB); if (NB==0) NB=32; uint32 ea = rA ? gCPU.gpr[rA] : 0; uint32 r = 0; int i = 4; uint8 v; while (NB > 0) { if (!i) { i = 4; gCPU.gpr[rD] = r; rD++; rD%=32; r = 0; } if (ppc_read_effective_byte(ea, &v)) { return; } r<<=8; r|=v; ea++; i--; NB--; } while (i) { r<<=8; i--; } gCPU.gpr[rD] = r; } /* * lswx Load String Word Indexed * .550 */ void ppc_opc_lswx() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); int NB = XER_n(gCPU.xer); uint32 ea = gCPU.gpr[rB] + (rA ? gCPU.gpr[rA] : 0); uint32 r = 0; int i = 4; uint8 v; while (NB > 0) { if (!i) { i = 4; gCPU.gpr[rD] = r; rD++; rD%=32; r = 0; } if (ppc_read_effective_byte(ea, &v)) { return; } r<<=8; r|=v; ea++; i--; NB--; } while (i) { r<<=8; i--; } gCPU.gpr[rD] = r; } /* * lwarx Load Word and Reserve Indexed * .553 */ void ppc_opc_lwarx() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint32 r; int ret = ppc_read_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; gCPU.reserve = r; gCPU.have_reservation = 1; } } /* * lwbrx Load Word Byte-Reverse Indexed * .556 */ void ppc_opc_lwbrx() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint32 r; int ret = ppc_read_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = ppc_bswap_word(r); } } /* * lwz Load Word and Zero * .557 */ void ppc_opc_lwz() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint32 r; int ret = ppc_read_effective_word((rA?gCPU.gpr[rA]:0)+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; } } /* * lbzu Load Word and Zero with Update * .558 */ void ppc_opc_lwzu() { int rA, rD; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); // FIXME: check rA!=0 && rA!=rD uint32 r; int ret = ppc_read_effective_word(gCPU.gpr[rA]+imm, &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; gCPU.gpr[rD] = r; } } /* * lwzux Load Word and Zero with Update Indexed * .559 */ void ppc_opc_lwzux() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); // FIXME: check rA!=0 && rA!=rD uint32 r; int ret = ppc_read_effective_word(gCPU.gpr[rA]+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; gCPU.gpr[rD] = r; } } /* * lwzx Load Word and Zero Indexed * .560 */ void ppc_opc_lwzx() { int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); uint32 r; int ret = ppc_read_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &r); if (ret == PPC_MMU_OK) { gCPU.gpr[rD] = r; } } /* lvx Load Vector Indexed * v.127 */ void ppc_opc_lvx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, rA, rB); Vector_t r; int ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]); int ret = ppc_read_effective_qword(ea, &r); if (ret == PPC_MMU_OK) { gCPU.vr[vrD] = r; } } /* lvxl Load Vector Index LRU * v.128 */ void ppc_opc_lvxl() { ppc_opc_lvx(); /* This instruction should hint to the cache that the value won't be * needed again in memory anytime soon. We don't emulate the cache, * so this is effectively exactly the same as lvx. */ } /* lvebx Load Vector Element Byte Indexed * v.119 */ void ppc_opc_lvebx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, rA, rB); uint32 ea; uint8 r; ea = (rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]; int ret = ppc_read_effective_byte(ea, &r); if (ret == PPC_MMU_OK) { VECT_B(gCPU.vr[vrD], ea & 0xf) = r; } } /* lvehx Load Vector Element Half Word Indexed * v.121 */ void ppc_opc_lvehx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, rA, rB); uint32 ea; uint16 r; ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]) & ~1; int ret = ppc_read_effective_half(ea, &r); if (ret == PPC_MMU_OK) { VECT_H(gCPU.vr[vrD], (ea & 0xf) >> 1) = r; } } /* lvewx Load Vector Element Word Indexed * v.122 */ void ppc_opc_lvewx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, rA, rB); uint32 ea; uint32 r; ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]) & ~3; int ret = ppc_read_effective_word(ea, &r); if (ret == PPC_MMU_OK) { VECT_W(gCPU.vr[vrD], (ea & 0xf) >> 2) = r; } } #if HOST_ENDIANESS == HOST_ENDIANESS_LE static byte lvsl_helper[] = { 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 }; #elif HOST_ENDIANESS == HOST_ENDIANESS_BE static byte lvsl_helper[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F }; #else #error Endianess not supported! #endif /* * lvsl Load Vector for Shift Left * v.123 */ void ppc_opc_lvsl() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, rA, rB); uint32 ea; ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]); #if HOST_ENDIANESS == HOST_ENDIANESS_LE memmove(&gCPU.vr[vrD], lvsl_helper+0x10-(ea & 0xf), 16); #elif HOST_ENDIANESS == HOST_ENDIANESS_BE memmove(&gCPU.vr[vrD], lvsl_helper+(ea & 0xf), 16); #else #error Endianess not supported! #endif } /* * lvsr Load Vector for Shift Right * v.125 */ void ppc_opc_lvsr() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, rA, rB); uint32 ea; ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]); #if HOST_ENDIANESS == HOST_ENDIANESS_LE memmove(&gCPU.vr[vrD], lvsl_helper+(ea & 0xf), 16); #elif HOST_ENDIANESS == HOST_ENDIANESS_BE memmove(&gCPU.vr[vrD], lvsl_helper+0x10-(ea & 0xf), 16); #else #error Endianess not supported! #endif } /* * dst Data Stream Touch * v.115 */ void ppc_opc_dst() { VECTOR_DEBUG; /* Since we are not emulating the cache, this is a nop */ } /* * stb Store Byte * .632 */ void ppc_opc_stb() { int rA, rS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rS, rA, imm); ppc_write_effective_byte((rA?gCPU.gpr[rA]:0)+imm, (uint8)gCPU.gpr[rS]) != PPC_MMU_FATAL; } /* * stbu Store Byte with Update * .633 */ void ppc_opc_stbu() { int rA, rS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rS, rA, imm); // FIXME: check rA!=0 int ret = ppc_write_effective_byte(gCPU.gpr[rA]+imm, (uint8)gCPU.gpr[rS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; } } /* * stbux Store Byte with Update Indexed * .634 */ void ppc_opc_stbux() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: check rA!=0 int ret = ppc_write_effective_byte(gCPU.gpr[rA]+gCPU.gpr[rB], (uint8)gCPU.gpr[rS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; } } /* * stbx Store Byte Indexed * .635 */ void ppc_opc_stbx() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); ppc_write_effective_byte((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], (uint8)gCPU.gpr[rS]) != PPC_MMU_FATAL; } /* * stfd Store Floating-Point Double * .642 */ void ppc_opc_stfd() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frS, rA, imm); ppc_write_effective_dword((rA?gCPU.gpr[rA]:0)+imm, gCPU.fpr[frS]) != PPC_MMU_FATAL; } /* * stfdu Store Floating-Point Double with Update * .643 */ void ppc_opc_stfdu() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU ,0 ,0); return; } int rA, frS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frS, rA, imm); // FIXME: check rA!=0 int ret = ppc_write_effective_dword(gCPU.gpr[rA]+imm, gCPU.fpr[frS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; } } /* * stfd Store Floating-Point Double with Update Indexed * .644 */ void ppc_opc_stfdux() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frS, rA, rB); // FIXME: check rA!=0 int ret = ppc_write_effective_dword(gCPU.gpr[rA]+gCPU.gpr[rB], gCPU.fpr[frS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; } } /* * tlbivax TLB invalidated virtual address indexed * .786 */ void ppc_opc_tlbivax() { //fprintf(stderr,"tlbivax is called, but not implemented\n"); int i,j; for(i = 0; i < L2_TLB0_SIZE; i++) if(!l2_tlb0_4k[i].iprot) l2_tlb0_4k[i].v = 0; for(j = 0; j < L2_TLB1_SIZE; j++) if(!l2_tlb1_vsp[i].iprot) l2_tlb1_vsp[i].v = 0; } /* * tlbwe TLB write entry * .978 */ /* * Fixme, now only support e500 */ void ppc_opc_tlbwe() { ppc_tlb_entry_t * entry; int offset; if(TLBSEL(e500_mmu.mas[0]) == 0x0){ //offset = ((ESEL(e500_mmu.mas[0]) & 0x1) << 7) | (EPN(e500_mmu.mas[2]) & 0x7f); /* Fixme: we just implement a simple round-robin replace for TLB0. that is not as described in manual of e500 */ static int tlb0_nv = 0; //offset = ((tlb0_nv & 0x1) << 7) | (EPN(e500_mmu.mas[2]) & 0x7f); offset = tlb0_nv++; if(tlb0_nv == 0xff) tlb0_nv = 0; if(offset >= L2_TLB0_SIZE){ fprintf(stderr, "Out of TLB size..\n"); skyeye_exit(-1); } else{ entry = &l2_tlb0_4k[0 + offset]; /* update TLB0[NV] with MAS0[NV] */ e500_mmu.tlb0_nv = e500_mmu.mas[0] & 0x1; } } else{ offset = ESEL(e500_mmu.mas[0]); if(offset >= L2_TLB1_SIZE){ fprintf(stderr, "Out of TLB size..\n"); skyeye_exit(-1); } else entry = &l2_tlb1_vsp[0 + offset]; } entry->v = e500_mmu.mas[1] >> 31; entry->iprot = (e500_mmu.mas[1] >> 30) & 0x1; entry->ts = (e500_mmu.mas[1] >> 12) & 0x1; entry->tid = (e500_mmu.mas[1] >> 16) & 0xFF; entry->size = (e500_mmu.mas[1] >> 8) & 0xF; entry->wimge = (e500_mmu.mas[2] & 0x1F); entry->x = (e500_mmu.mas[2] >> 5) & 0x3; entry->epn = (e500_mmu.mas[2] >> 12) & 0xFFFFF; entry->usxrw = e500_mmu.mas[3] & 0x3F; entry->u = (e500_mmu.mas[3]) >> 6 & 0xF; entry->rpn = (e500_mmu.mas[3] >> 12) & 0xFFFFF; //printf("In %s, rpn=0x%x, epn=0x%x, offset=0x%x, mas0=0x%x, mas2=0x%x\n", __FUNCTION__, entry->rpn, entry->epn, offset, e500_mmu.mas[0], e500_mmu.mas[2]); } void ppc_opc_tlbsx(){ ppc_tlb_entry_t *entry; int tlb1_index; int va,ea; int mask,addr; int i = 0; int rA, rD, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); ea = gCPU.gpr[rB]; /* walk over tlb0 and tlb1 to find the entry */ while(i++ < (L2_TLB0_SIZE + L2_TLB1_SIZE)){ if(i > (L2_TLB0_SIZE - 1)){ tlb1_index = i - L2_TLB0_SIZE; entry = &l2_tlb1_vsp[tlb1_index]; } else entry = &l2_tlb0_4k[i]; if(!entry->v) continue; /* FIXME, not check ts bit now */ if(entry->ts & 0x0) continue; if(entry->tid != 0 && entry->tid != ((e500_mmu.mas[6] & 0xFF00) >> 8)){ continue; } if(i > (L2_TLB0_SIZE - 1)){ int k,s = 1; for(k = 0; k < entry->size; k++) s = s * 4; mask = ~(1024 * s - 0x1); } else mask = ~(1024 * 4 - 0x1); /* we found the entry */ if((addr & mask) == (entry->epn << 12)){ if(i > (L2_TLB0_SIZE - 1)){ e500_mmu.mas[0] |= (0x1 << 28); e500_mmu.mas[0] |= (e500_mmu.mas[0] & 0xFFF0FFFF) | ((tlb1_index & 0xC) << 16) ; } else{ e500_mmu.mas[0] &= ~(0x1 << 28); e500_mmu.mas[0] = (e500_mmu.mas[0] & 0xFFF0FFFF) | (i << 16); } e500_mmu.mas[1] |= 0x80000000; break; } } } void ppc_opc_tlbrehi(){ ppc_tlb_entry_t * entry; int offset; if(TLBSEL(e500_mmu.mas[0]) == 0x0){ offset = ((ESEL(e500_mmu.mas[0]) & 0x1) << 7) | (EPN(e500_mmu.mas[2]) & 0x7f); if(offset > L2_TLB0_SIZE){ fprintf(stderr, "Out of TLB size..\n"); skyeye_exit(-1); } else entry = &l2_tlb0_4k[0 + offset]; } else{ offset = ESEL(e500_mmu.mas[0]); if(offset > L2_TLB1_SIZE){ fprintf(stderr, "Out of TLB size..\n"); skyeye_exit(-1); } else entry = &l2_tlb1_vsp[0 + offset]; } e500_mmu.mas[1] = (e500_mmu.mas[1] & 0x7FFFFFFF) | (entry->v << 31); e500_mmu.mas[1] = (e500_mmu.mas[1] & 0xbFFFFFFF) | (entry->iprot << 30); e500_mmu.mas[1] = (e500_mmu.mas[1] & 0xFFFFEFFF) | (entry->ts << 12); e500_mmu.mas[1] = (e500_mmu.mas[1] & 0xFF00FFFF) | (entry->tid << 16); e500_mmu.mas[1] = (e500_mmu.mas[1] & 0xFFFFF0FF) | (entry->size << 8); e500_mmu.mas[2] = (e500_mmu.mas[2] & 0xFFFFFFE0) | (entry->wimge); e500_mmu.mas[2] = (e500_mmu.mas[2] & 0xFFFFFF9F) | (entry->x << 5); e500_mmu.mas[2] = (e500_mmu.mas[2] & 0xFFF) | (entry->epn << 12); e500_mmu.mas[3] = (e500_mmu.mas[3] & 0xFFFFFFC0) | (entry->usxrw); e500_mmu.mas[3] = (e500_mmu.mas[3] & 0xFFFFFFC3F) | (entry->u << 6); e500_mmu.mas[3] = (e500_mmu.mas[3] & 0xFFF) | (entry->rpn << 12); } /* * stfdx Store Floating-Point Double Indexed * .645 */ void ppc_opc_stfdx() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frS, rA, rB); ppc_write_effective_dword((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], gCPU.fpr[frS]) != PPC_MMU_FATAL; } /* * stfiwx Store Floating-Point as Integer Word Indexed * .646 */ void ppc_opc_stfiwx() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frS, rA, rB); ppc_write_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], (uint32)gCPU.fpr[frS]) != PPC_MMU_FATAL; } /* * stfs Store Floating-Point Single * .647 */ void ppc_opc_stfs() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frS, rA, imm); uint32 s; ppc_double d; ppc_fpu_unpack_double(&d, gCPU.fpr[frS]); ppc_fpu_pack_single(&d, &s); ppc_write_effective_word((rA?gCPU.gpr[rA]:0)+imm, s) != PPC_MMU_FATAL; } /* * stfsu Store Floating-Point Single with Update * .648 */ void ppc_opc_stfsu() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, frS, rA, imm); // FIXME: check rA!=0 uint32 s; ppc_double d; ppc_fpu_unpack_double(&d, gCPU.fpr[frS]); ppc_fpu_pack_single(&d, &s); int ret = ppc_write_effective_word(gCPU.gpr[rA]+imm, s); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; } } /* * stfsux Store Floating-Point Single with Update Indexed * .649 */ void ppc_opc_stfsux() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frS, rA, rB); // FIXME: check rA!=0 uint32 s; ppc_double d; ppc_fpu_unpack_double(&d, gCPU.fpr[frS]); ppc_fpu_pack_single(&d, &s); int ret = ppc_write_effective_word(gCPU.gpr[rA]+gCPU.gpr[rB], s); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; } } /* * stfsx Store Floating-Point Single Indexed * .650 */ void ppc_opc_stfsx() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0, 0); return; } int rA, frS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frS, rA, rB); uint32 s; ppc_double d; ppc_fpu_unpack_double(&d, gCPU.fpr[frS]); ppc_fpu_pack_single(&d, &s); ppc_write_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], s) != PPC_MMU_FATAL; } /* * sth Store Half Word * .651 */ void ppc_opc_sth() { int rA, rS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rS, rA, imm); ppc_write_effective_half((rA?gCPU.gpr[rA]:0)+imm, (uint16)gCPU.gpr[rS]) != PPC_MMU_FATAL; /*if(gCPU.pc >= 0xfff830e4 && gCPU.pc <= 0xfff83254) fprintf(prof_file, "DBG:in %s,pc=0x%x\n", __FUNCTION__, gCPU.pc); */ } /* * sthbrx Store Half Word Byte-Reverse Indexed * .652 */ void ppc_opc_sthbrx() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); ppc_write_effective_half((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], ppc_bswap_half(gCPU.gpr[rS])) != PPC_MMU_FATAL; } /* * sthu Store Half Word with Update * .653 */ void ppc_opc_sthu() { int rA, rS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rS, rA, imm); // FIXME: check rA!=0 int ret = ppc_write_effective_half(gCPU.gpr[rA]+imm, (uint16)gCPU.gpr[rS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; } } /* * sthux Store Half Word with Update Indexed * .654 */ void ppc_opc_sthux() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: check rA!=0 int ret = ppc_write_effective_half(gCPU.gpr[rA]+gCPU.gpr[rB], (uint16)gCPU.gpr[rS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; } } /* * sthx Store Half Word Indexed * .655 */ void ppc_opc_sthx() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); ppc_write_effective_half((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], (uint16)gCPU.gpr[rS]) != PPC_MMU_FATAL; } /* * stmw Store Multiple Word * .656 */ void ppc_opc_stmw() { int rS, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rS, rA, imm); uint32 ea = (rA ? gCPU.gpr[rA] : 0) + imm; while (rS <= 31) { if (ppc_write_effective_word(ea, gCPU.gpr[rS])) { return; } rS++; ea += 4; } } /* * stswi Store String Word Immediate * .657 */ void ppc_opc_stswi() { int rA, rS, NB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, NB); if (NB==0) NB=32; uint32 ea = rA ? gCPU.gpr[rA] : 0; uint32 r = 0; int i = 0; while (NB > 0) { if (!i) { r = gCPU.gpr[rS]; rS++; rS%=32; i = 4; } if (ppc_write_effective_byte(ea, (r>>24))) { return; } r<<=8; ea++; i--; NB--; } } /* * stswx Store String Word Indexed * .658 */ void ppc_opc_stswx() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); int NB = XER_n(gCPU.xer); uint32 ea = gCPU.gpr[rB] + (rA ? gCPU.gpr[rA] : 0); uint32 r = 0; int i = 0; while (NB > 0) { if (!i) { r = gCPU.gpr[rS]; rS++; rS%=32; i = 4; } if (ppc_write_effective_byte(ea, (r>>24))) { return; } r<<=8; ea++; i--; NB--; } } /* * stw Store Word * .659 */ void ppc_opc_stw() { int rA, rS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rS, rA, imm); ppc_write_effective_word((rA?gCPU.gpr[rA]:0)+imm, gCPU.gpr[rS]) != PPC_MMU_FATAL; } /* * stwbrx Store Word Byte-Reverse Indexed * .660 */ void ppc_opc_stwbrx() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: doppelt gemoppelt ppc_write_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], ppc_bswap_word(gCPU.gpr[rS])) != PPC_MMU_FATAL; } /* * stwcx. Store Word Conditional Indexed * .661 */ void ppc_opc_stwcx_() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.cr &= 0x0fffffff; if (gCPU.have_reservation) { gCPU.have_reservation = false; uint32 v; if (ppc_read_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], &v)) { return; } if (v==gCPU.reserve) { if (ppc_write_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], gCPU.gpr[rS])) { return; } gCPU.cr |= CR_CR0_EQ; } if (gCPU.xer & XER_SO) { gCPU.cr |= CR_CR0_SO; } } } /* * stwu Store Word with Update * .663 */ void ppc_opc_stwu() { int rA, rS; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rS, rA, imm); // FIXME: check rA!=0 int ret = ppc_write_effective_word(gCPU.gpr[rA]+imm, gCPU.gpr[rS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += imm; } } /* * stwux Store Word with Update Indexed * .664 */ void ppc_opc_stwux() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: check rA!=0 int ret = ppc_write_effective_word(gCPU.gpr[rA]+gCPU.gpr[rB], gCPU.gpr[rS]); if (ret == PPC_MMU_OK) { gCPU.gpr[rA] += gCPU.gpr[rB]; } } /* * stwx Store Word Indexed * .665 */ void ppc_opc_stwx() { int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); ppc_write_effective_word((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB], gCPU.gpr[rS]) != PPC_MMU_FATAL; } /* stvx Store Vector Indexed * v.134 */ void ppc_opc_stvx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrS, rA, rB); int ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]); ppc_write_effective_qword(ea, gCPU.vr[vrS]) != PPC_MMU_FATAL; } /* stvxl Store Vector Indexed LRU * v.135 */ void ppc_opc_stvxl() { ppc_opc_stvx(); /* This instruction should hint to the cache that the value won't be * needed again in memory anytime soon. We don't emulate the cache, * so this is effectively exactly the same as lvx. */ } /* stvebx Store Vector Element Byte Indexed * v.131 */ void ppc_opc_stvebx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrS, rA, rB); uint32 ea; ea = (rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]; ppc_write_effective_byte(ea, VECT_B(gCPU.vr[vrS], ea & 0xf)); } /* stvehx Store Vector Element Half Word Indexed * v.132 */ void ppc_opc_stvehx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrS, rA, rB); uint32 ea; ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]) & ~1; ppc_write_effective_half(ea, VECT_H(gCPU.vr[vrS], (ea & 0xf) >> 1)); } /* stvewx Store Vector Element Word Indexed * v.133 */ void ppc_opc_stvewx() { #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC, 0, 0); return; } #endif VECTOR_DEBUG; int rA, vrS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrS, rA, rB); uint32 ea; ea = ((rA?gCPU.gpr[rA]:0)+gCPU.gpr[rB]) & ~3; ppc_write_effective_word(ea, VECT_W(gCPU.vr[vrS], (ea & 0xf) >> 2)); } /* dstst Data Stream Touch for Store * v.117 */ void ppc_opc_dstst() { VECTOR_DEBUG; /* Since we are not emulating the cache, this is a nop */ } /* dss Data Stream Stop * v.114 */ void ppc_opc_dss() { VECTOR_DEBUG; /* Since we are not emulating the cache, this is a nop */ } void ppc_opc_wrteei(){ if ((gCPU.current_opc >> 15) & 0x1) gCPU.msr |= 0x00008000; else gCPU.msr &= ~0x00008000; } void ppc_opc_wrtee(){ int rA, rS, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); if ((gCPU.gpr[rS] >> 15) & 0x1) gCPU.msr |= 0x00008000; else gCPU.msr &= ~0x00008000; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_cpu.h����������������������������������������������������������0000644�0001750�0000144�00000036315�10712073070�017034� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_cpu.h * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_CPU_H__ #define __PPC_CPU_H__ #include <stddef.h> #include <stdio.h> #include "types.h" #define PPC_MHz(v) ((v)*1000*1000) #define TB_TO_PTB_FACTOR 10 #define PPC_MODEL "ppc_model" #define PPC_CPU_MODEL "ppc_cpu" #define PPC_CLOCK_FREQUENCY PPC_MHz(10) #define PPC_BUS_FREQUENCY PPC_MHz(10) #define PPC_TIMEBASE_FREQUENCY (PPC_CLOCK_FREQUENCY / TB_TO_PTB_FACTOR) typedef union Vector_t { uint64 d[2]; sint64 sd[2]; float f[4]; uint32 w[4]; sint32 sw[4]; uint16 h[8]; sint16 sh[8]; uint8 b[16]; sint8 sb[16]; } Vector_t; typedef struct ccsr_reg_s{ uint32_t ccsr; /* Configuration,control and status registers base address register */ uint32_t altcbar; /* allternate configuration base address register */ uint32_t altcar; /* alternate configuration attribute register */ uint32_t bptr; /* Boot page translation register */ }ccsr_reg_t; /* Local bus controll register */ typedef struct lb_ctrl_s{ uint32 br[8]; //uint32 or[8]; uint32 lcrr; /* Clock ratio register */ //uint32 lbcr; /* Configuration register */ }lb_ctrl_t; typedef struct law_reg_s{ uint32_t lawbar[8]; uint32_t lawar[8]; }law_reg_t; typedef struct por_conf_s{ uint32_t porpllsr; uint32_t porbmsr; uint32_t porimpscr; uint32_t pordevsr; uint32_t pordbgmsr; uint32_t gpporcr; }por_conf_t; /* 0x91a00-0x91a9f: SCC1-SCC4 */ typedef struct cpm_scc_s { uint32 gsmrl; uint32 gsmrh; uint16 psmr; char res1[2]; uint16 todr; uint16 dsr; uint16 scce; char res2[2]; uint16 sccm; char res3; uint8 sccs; char res4[8]; } cpm_scc_t; typedef struct cpm_mux_s{ uint32_t cmxfcr; uint32_t cmxscr; } cpm_mux_t; typedef struct cpm_ioport_s{ uint32_t pdira; uint32_t ppara; uint32_t psora; uint32_t podra; uint32_t pdata; uint32_t pdirb; uint32_t pparb; uint32_t psorb; uint32_t podrb; uint32_t pdatb; uint32_t pdirc; uint32_t pparc; uint32_t psorc; uint32_t podrc; uint32_t pdatc; uint32_t pdird; uint32_t ppard; uint32_t psord; uint32_t podrd; uint32_t pdatd; } cpm_ioport_t; typedef struct cpm_reg_s{ uint32_t cpcr; uint32_t rccr; uint32_t rter; uint32_t rtmr; uint32_t rtscr; uint32_t rtsr; byte *dpram; byte *iram; /* instruction RAM */ cpm_scc_t scc[4]; cpm_mux_t mux; uint32_t brgc[4]; cpm_ioport_t ioport; } cpm_reg_t; typedef struct i2c_reg_s{ uint32 i2cadr; uint32 i2ccr; uint32 i2csr; uint32 i2cdr; uint32 i2cfdr; uint32 i2cdfsrr; }i2c_reg_t; typedef struct debug_ctrl_s{ uint32 clkocr; uint32 ddrdllcr; uint32 lbdrrcr; }debug_ctrl_t; typedef struct ppc_dma_s{ uint32 satr0; uint32 datr0; }mpc_dma_t; typedef struct int_ctrl_s{ uint32 sicr; uint32 sipnr_h; uint32 sipnr_l; uint32 scprr_h; uint32 scprr_l; uint32 simr_h; uint32 simr_l; }int_ctrl_t; typedef struct ddr_ctrl_s{ uint32 err_disable; }ddr_ctrl_t; typedef struct l2_reg_s{ uint32 l2ctl; }l2_reg_t; typedef struct pci_cfg_s{ uint32 cfg_addr; uint32 cfg_data; uint32 int_ack; }pci_cfg_t; typedef struct pci_atmu_s{ uint32 potar1; uint32 potear1; uint32 powbar1; uint32 reserv1; uint32 powar1; }pci_atmu_t; typedef struct pic_global_s{ uint32 gcr; uint32 frr; uint32 tfrr; uint32 gtdr0; uint32 gtdr1; uint32 gtdr2; uint32 gtdr3; uint32 gtvpr0; uint32 gtvpr1; uint32 gtvpr2; uint32 gtvpr3; uint32 svr; uint32 iack; }pic_global_t; typedef struct pic_ram_s{ uint32 eivpr[11]; uint32 eidr[11]; uint32 ctpr0; uint32 iivpr[32]; uint32 iidr[32]; }pic_ram_t; typedef struct pic_percpu_s{ uint32 iack0; }pic_percpu_t; typedef struct PPC_CPU_State_s { // * uisa uint32 gpr[32]; uint64 fpr[32]; uint32 cr; uint32 fpscr; uint32 xer; // spr 1 uint32 xer_ca; // carry from xer uint32 lr; // spr 8 uint32 ctr; // spr 9 // * oea uint32 msr; uint32 pvr; // spr 287 // * memory managment uint32 ibatu[4]; // spr 528, 530, 532, 534 uint32 ibatl[4]; // spr 529, 531, 533, 535 uint32 ibat_bl17[4]; // for internal use uint32 dbatu[4]; // spr 536, 538, 540, 542 uint32 dbatl[4]; // spr 537, 539, 541, 543 uint32 dbat_bl17[4]; // for internal use uint32 sdr1; // spr 25 (page table base address) uint32 sr[16]; // * exception handling uint32 dar; // spr 19 uint32 dsisr; // spr 18 uint32 sprg[8]; // spr 272-275 //uint32 sprg[4]; uint32 srr[2]; // spr 26-27 // * misc uint32 dec; // spr 22 uint32 ear; // spr 282 .101 uint32 pir; // spr 1032 uint64 tb; // .75 spr 284(l)/285(u) uint32 hid[16]; // * internal uint32 pc; uint32 npc; uint32 current_opc; bool exception_pending; bool dec_exception; bool ext_exception; bool stop_exception; bool singlestep_ignore; uint32 pagetable_base; int pagetable_hashmask; uint32 reserve; bool have_reservation; // for generic cpu core uint32 effective_code_page; byte *physical_code_page; uint64 pdec; // more precise version of dec uint64 ptb; // more precise version of tb // for altivec uint32 vscr; uint32 vrsave; // spr 256 Vector_t vr[36]; // <--- this MUST be 16-byte alligned uint32 vtemp; /* e500 specific register */ uint32 l1csr[2]; /* L1 cache constrol and status */ uint32 csrr[2]; /* Critical save/restore register */ uint32 mcsrr[2]; /* Machine check save/restore register */ uint32 esr; /* Exception syndrome register */ uint32 mcsr; /* Machine check syndrome register */ uint32 dear; /* Data exception address register */ uint32 dbcr[3]; /* Debug control register */ uint32 dbsr; /* Debug status register */ uint32 pid[3]; /* Process ID */ uint32 tcr; /* Timer control register */ uint32 tsr; /* Timer status register */ uint32 dac[2]; /* Data address compare */ uint32 ivpr; /* Interrupt vector */ uint32 ivor[16]; /* 0 = Critical input */ uint32 iac[2]; /* Instruction address compare */ uint32 tbl; uint32 tbu; uint32 spefscr; ccsr_reg_t ccsr; law_reg_t law; /* Local access window */ lb_ctrl_t lb_ctrl; /* Local bus controll register */ cpm_reg_t cpm_reg; /* Communication processor */ uint32 sccr; /* System clock control register */ por_conf_t por_conf; i2c_reg_t i2c_reg; debug_ctrl_t debug_ctrl; ddr_ctrl_t ddr_ctrl; mpc_dma_t dma; l2_reg_t l2_reg; pci_cfg_t pci_cfg; pci_atmu_t pci_atmu; pic_global_t pic_global; int_ctrl_t int_ctrl; pic_ram_t pic_ram; pic_percpu_t pic_percpu; }PPC_CPU_State; extern PPC_CPU_State gCPU; #define E500 /* cr: .67 0- 3 cr0 4- 7 cr1 8-11 cr2 12-15 cr3 16-19 cr4 20-23 cr5 24-27 cr6 28-31 cr7 */ #define CR_CR0(v) ((v)>>28) #define CR_CR1(v) (((v)>>24)&0xf) #define CR_CRx(v, x) (((v)>>(4*(7-(x))))&0xf) /* cr0 bits: .68 lt gt eq so */ #define CR_CR0_LT (1<<31) #define CR_CR0_GT (1<<30) #define CR_CR0_EQ (1<<29) //#define CR_CR0_EQ (1 << 2) #define CR_CR0_SO (1<<28) /* cr1 bits: .68 4 Floating-point exception (FX) 5 Floating-point enabled exception (FEX) 6 Floating-point invalid exception (VX) 7 Floating-point overflow exception (OX) */ #define CR_CR1_FX (1<<27) #define CR_CR1_FEX (1<<26) #define CR_CR1_VX (1<<25) #define CR_CR1_OX (1<<24) /* FPSCR bits: .70 */ #define FPSCR_FX (1<<31) #define FPSCR_FEX (1<<30) #define FPSCR_VX (1<<29) #define FPSCR_OX (1<<28) #define FPSCR_UX (1<<27) #define FPSCR_ZX (1<<26) #define FPSCR_XX (1<<25) #define FPSCR_VXSNAN (1<<24) #define FPSCR_VXISI (1<<23) #define FPSCR_VXIDI (1<<22) #define FPSCR_VXZDZ (1<<21) #define FPSCR_VXIMZ (1<<20) #define FPSCR_VXVC (1<<19) #define FPSCR_FR (1<<18) #define FPSCR_FI (1<<17) #define FPSCR_FPRF(v) (((v)>>12)&0x1f) #define FPSCR_res0 (1<<11) #define FPSCR_VXSOFT (1<<10) #define FPSCR_VXSQRT (1<<9) #define FPSCR_VXCVI (1<<8) #define FPSCR_VXVE (1<<7) #define FPSCR_VXOE (1<<6) #define FPSCR_VXUE (1<<5) #define FPSCR_VXZE (1<<4) #define FPSCR_VXXE (1<<3) #define FPSCR_VXNI (1<<2) #define FPSCR_RN(v) ((v)&3) #define FPSCR_RN_NEAR 0 #define FPSCR_RN_ZERO 1 #define FPSCR_RN_PINF 2 #define FPSCR_RN_MINF 3 /* VSCR bits: sat = summary saturation nj = non-java floating-point mode */ #define VSCR_SAT 1 #define VSCR_NJ (1<<16) /* xer bits: 0 so 1 ov 2 carry 3-24 res 25-31 number of bytes for lswx/stswx */ #define XER_SO (1<<31) #define XER_OV (1<<30) #define XER_CA (1<<29) #define XER_n(v) ((v)&0x7f) /* msr: .83 0-12 res 13 POW power management enabled 14 res 15 ILE exception little-endian mode 16 EE enable external interrupt 17 PR privilege level (0=sv) 18 FP floating point avail 19 ME maschine check exception enable 20 FE0 floation point exception mode 0 21 SE single step enable 22 BE branch trace enable 23 FE1 floation point exception mode 1 24 res 25 IP exception prefix 26 IR intruction address translation 27 DR data address translation 28-29res 30 RI recoverable exception 31 LE little endian mode */ #define MSR_SF (1<<31) #define MSR_UNKNOWN (1<<30) #define MSR_UNKNOWN2 (1<<27) #define MSR_VEC (1<<25) #define MSR_POW (1<<18) #define MSR_TGPR (1<<15) // 603(e) #define MSR_ILE (1<<16) #define MSR_EE (1<<15) #define MSR_PR (1<<14) #define MSR_FP (1<<13) #define MSR_ME (1<<12) #define MSR_FE0 (1<<11) #define MSR_SE (1<<10) #define MSR_BE (1<<9) #define MSR_FE1 (1<<8) #define MSR_IP (1<<6) #define MSR_IR (1<<5) #define MSR_DR (1<<4) #define MSR_PM (1<<2) #define MSR_RI (1<<1) #define MSR_LE (1) //#define PPC_CPU_UNSUPPORTED_MSR_BITS (/*MSR_POW|*/MSR_ILE|MSR_BE|MSR_IP|MSR_LE) #define PPC_CPU_UNSUPPORTED_MSR_BITS (~(MSR_POW | MSR_UNKNOWN | MSR_UNKNOWN2 | MSR_VEC | MSR_EE | MSR_PR | MSR_FP | MSR_ME | MSR_FE0 | MSR_SE | MSR_FE1 | MSR_IR | MSR_DR | MSR_RI)) #define MSR_RFI_SAVE_MASK (0xff73) /* BAT Register: .88 upper: 0-14 BEPI Block effective page index. 15-18 res 19-29 BL Block length. 30 Vs Supervisor mode valid bit. 31 Vp User mode valid bit. lower: 0-14 BRPN This field is used in conjunction with the BL field to generate highorder bits of the physical address of the block. 15-24 res 25-28 WIMG Memory/cache access mode bits 29 res 30-31 PP Protection bits for block. BAT Area Length BL Encoding 128 Kbytes 000 0000 0000 256 Kbytes 000 0000 0001 512 Kbytes 000 0000 0011 1 Mbyte 000 0000 0111 2 Mbytes 000 0000 1111 4 Mbytes 000 0001 1111 8 Mbytes 000 0011 1111 16 Mbytes 000 0111 1111 32 Mbytes 000 1111 1111 64 Mbytes 001 1111 1111 128 Mbytes 011 1111 1111 256 Mbytes 111 1111 1111 */ #define BATU_BEPI(v) ((v)&0xfffe0000) #define BATU_BL(v) (((v)&0x1ffc)>>2) #define BATU_Vs (1<<1) #define BATU_Vp (1) #define BATL_BRPN(v) ((v)&0xfffe0000) #define BAT_EA_OFFSET(v) ((v)&0x1ffff) #define BAT_EA_11(v) ((v)&0x0ffe0000) #define BAT_EA_4(v) ((v)&0xf0000000) /* sdr1: .91 0-15 The high-order 16 bits of the 32-bit physical address of the page table 16-22 res 23-31 Mask for page table address */ #define SDR1_HTABORG(v) (((v)>>16)&0xffff) #define SDR1_HTABMASK(v) ((v)&0x1ff) #define SDR1_PAGETABLE_BASE(v) ((v)&0xffff) /* sr: .94 0 T=0: 1 Ks sv prot 2 Kp user prot 3 N No execute 4-7 res 8-31 VSID Virtual Segment ID 0 T=1: 1 Ks 2 Kp 3-11 BUID Bus Unit ID 12-31 CNTRL_SPEC */ #define SR_T (1<<31) #define SR_Ks (1<<30) #define SR_Kp (1<<29) #define SR_N (1<<28) #define SR_VSID(v) ((v)&0xffffff) #define SR_BUID(v) (((v)>>20)&0x1ff) #define SR_CNTRL_SPEC(v) ((v)&0xfffff) #define EA_SR(v) (((v)>>28)&0xf) #define EA_PageIndex(v) (((v)>>12)&0xffff) #define EA_Offset(v) ((v)&0xfff) #define EA_API(v) (((v)>>22)&0x3f) #define PA_RPN(v) (((v)>>12)&0xfffff) #define PA_Offset(v) ((v)&0xfff) /* PTE: .364 0 V 1-24 VSID 25 H 26-31 API */ #define PTE1_V (1<<31) #define PTE1_VSID(v) (((v)>>7)&0xffffff) #define PTE1_H (1<<6) #define PTE1_API(v) ((v)&0x3f) #define PTE2_RPN(v) ((v)&0xfffff000) #define PTE2_R (1<<8) #define PTE2_C (1<<7) #define PTE2_WIMG(v) (((v)>>3)&0xf) #define PTE2_PP(v) ((v)&3) #define PPC_L1_CACHE_LINE_SIZE 32 #define PPC_LG_L1_CACHE_LINE_SIZE 5 #define PPC_MAX_L1_COPY_PREFETCH 4 /* * special registers */ #define HID0 1008 /* Checkstop and misc enables */ #define HID1 1009 /* Clock configuration */ #define iabr 1010 /* Instruction address breakpoint register */ #define ictrl 1011 /* Instruction Cache Control */ #define ldstdb 1012 /* Load/Store Debug */ #define dabr 1013 /* Data address breakpoint register */ #define msscr0 1014 /* Memory subsystem control */ #define msscr1 1015 /* Memory subsystem debug */ #define msssr0 1015 /* Memory Subsystem Status */ #define ldstcr 1016 /* Load/Store Status/Control */ #define l2cr2 1016 /* L2 Cache control 2 */ #define l2cr 1017 /* L2 Cache control */ #define l3cr 1018 /* L3 Cache control */ #define ictc 1019 /* I-cache throttling control */ #define thrm1 1020 /* Thermal management 1 */ #define thrm2 1021 /* Thermal management 2 */ #define thrm3 1022 /* Thermal management 3 */ #define pir 1023 /* Processor ID Register */ //; hid0 bits #define HID0_emcp 0 #define HID0_emcpm 0x80000000 #define HID0_dbp 1 #define HID0_dbpm 0x40000000 #define HID0_eba 2 #define HID0_ebam 0x20000000 #define HID0_ebd 3 #define HID0_ebdm 0x10000000 #define HID0_sbclk 4 #define HID0_sbclkm 0x08000000 #define HID0_eclk 6 #define HID0_eclkm 0x02000000 #define HID0_par 7 #define HID0_parm 0x01000000 #define HID0_sten 7 #define HID0_stenm 0x01000000 #define HID0_doze 8 #define HID0_dozem 0x00800000 #define HID0_nap 9 #define HID0_napm 0x00400000 #define HID0_sleep 10 #define HID0_sleepm 0x00200000 #define HID0_dpm 11 #define HID0_dpmm 0x00100000 #define HID0_riseg 12 #define HID0_risegm 0x00080000 #define HID0_eiec 13 #define HID0_eiecm 0x00040000 #define HID0_mum 14 #define HID0_mumm 0x00020000 #define HID0_nhr 15 #define HID0_nhrm 0x00010000 #define HID0_ice 16 #define HID0_icem 0x00008000 #define HID0_dce 17 #define HID0_dcem 0x00004000 #define HID0_ilock 18 #define HID0_ilockm 0x00002000 #define HID0_dlock 19 #define HID0_dlockm 0x00001000 #define HID0_icfi 20 #define HID0_icfim 0x00000800 #define HID0_dcfi 21 #define HID0_dcfim 0x00000400 #define HID0_spd 22 #define HID0_spdm 0x00000200 #define HID0_sge 24 #define HID0_sgem 0x00000080 #define HID0_dcfa 25 #define HID0_dcfam 0x00000040 #define HID0_btic 26 #define HID0_bticm 0x00000020 #define HID0_lrstk 27 #define HID0_lrstkm 0x00000010 #define HID0_abe 28 #define HID0_abem 0x00000008 #define HID0_fold 28 #define HID0_foldm 0x00000008 #define HID0_bht 29 #define HID0_bhtm 0x00000004 #define HID0_nopdst 30 #define HID0_nopdstm 0x00000002 #define HID0_nopti 31 #define HID0_noptim 0x00000001 void ppc_cpu_atomic_raise_ext_exception(); void ppc_cpu_atomic_cancel_ext_exception(); extern uint32 gBreakpoint; extern uint32 gBreakpoint2; FILE * prof_file; void ppc_set_singlestep_v(bool v, const char *file, int line, const char *format, ...); void ppc_set_singlestep_nonverbose(bool v); #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_fpu.c����������������������������������������������������������0000644�0001750�0000144�00000103606�10635115336�017036� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_fpu.cc * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * Copyright (C) 2003 Stefan Weyergraf * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ //#include "debug/tracers.h" #include <stdlib.h> #include "ppc_cpu.h" #include "ppc_dec.h" #include "ppc_fpu.h" #include "tracers.h" // .121 #define PPC_FPR_TYPE2(a,b) (((a)<<8)|(b)) inline void ppc_fpu_add(ppc_double *res, ppc_double *a, ppc_double *b) { switch (PPC_FPR_TYPE2(a->type, b->type)) { case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_norm): { int diff = a->e - b->e; if (diff<0) { diff = -diff; if (diff <= 56) { a->m >>= diff; } else if (a->m != 0) { a->m = 1; } else { a->m = 0; } res->e = b->e; } else { if (diff <= 56) { b->m >>= diff; } else if (b->m != 0) { b->m = 1; } else { b->m = 0; } res->e = a->e; } res->type = ppc_fpr_norm; if (a->s == b->s) { res->s = a->s; res->m = a->m + b->m; if (res->m & (1ULL<<56)) { res->m >>= 1; res->e++; } } else { res->s = a->s; res->m = a->m - b->m; if (!res->m) { if (FPSCR_RN(gCPU.fpscr) == FPSCR_RN_MINF) { res->s |= b->s; } else { res->s &= b->s; } res->type = ppc_fpr_zero; } else { if ((sint64)res->m < 0) { res->m = b->m - a->m; res->s = b->s; } diff = ppc_fpu_normalize(res) - 8; res->e -= diff; res->m <<= diff; } } break; } case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_NaN): res->s = a->s; res->type = ppc_fpr_NaN; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_zero): res->e = a->e; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_zero): res->s = a->s; res->m = a->m; res->type = a->type; break; case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_norm): res->e = b->e; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_NaN): res->s = b->s; res->m = b->m; res->type = b->type; break; case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_Inf): if (a->s != b->s) { // +oo + -oo == NaN res->s = a->s ^ b->s; res->type = ppc_fpr_NaN; break; } // fall-thru case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_zero): res->s = a->s; res->type = a->type; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_Inf): res->s = b->s; res->type = b->type; break; case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_zero): // round bla res->type = ppc_fpr_zero; res->s = a->s && b->s; break; } } inline void ppc_fpu_quadro_mshr(ppc_quadro *q, int exp) { if (exp >= 64) { q->m1 = q->m0; q->m0 = 0; exp -= 64; } uint64 t = q->m0 & ((1ULL<<exp)-1); q->m0 >>= exp; q->m1 >>= exp; q->m1 |= t<<(64-exp); } inline void ppc_fpu_quadro_mshl(ppc_quadro *q, int exp) { if (exp >= 64) { q->m0 = q->m1; q->m1 = 0; exp -= 64; } uint64 t = (q->m1 >> (64-exp)) & ((1ULL<<exp)-1); q->m0 <<= exp; q->m1 <<= exp; q->m0 |= t; } inline void ppc_fpu_add_quadro_m(ppc_quadro *res, const ppc_quadro *a, const ppc_quadro *b) { res->m1 = a->m1+b->m1; if (res->m1 < a->m1) { res->m0 = a->m0+b->m0+1; } else { res->m0 = a->m0+b->m0; } } inline void ppc_fpu_sub_quadro_m(ppc_quadro *res, const ppc_quadro *a, const ppc_quadro *b) { res->m1 = a->m1-b->m1; if (a->m1 < b->m1) { res->m0 = a->m0-b->m0-1; } else { res->m0 = a->m0-b->m0; } } // res has 107 significant bits. a, b have 106 significant bits each. inline void ppc_fpu_add_quadro(ppc_quadro *res, ppc_quadro *a, ppc_quadro *b) { // treat as 107 bit mantissa if (a->type == ppc_fpr_norm) ppc_fpu_quadro_mshl(a, 1); if (b->type == ppc_fpr_norm) ppc_fpu_quadro_mshl(b, 1); switch (PPC_FPR_TYPE2(a->type, b->type)) { case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_norm): { int diff = a->e - b->e; if (diff < 0) { diff = -diff; if (diff <= 107) { // FIXME: may set x_prime ppc_fpu_quadro_mshr(a, diff); } else if (a->m0 || a->m1) { a->m0 = 0; a->m1 = 1; } else { a->m0 = 0; a->m1 = 0; } res->e = b->e; } else { if (diff <= 107) { // FIXME: may set x_prime ppc_fpu_quadro_mshr(b, diff); } else if (b->m0 || b->m1) { b->m0 = 0; b->m1 = 1; } else { b->m0 = 0; b->m1 = 0; } res->e = a->e; } res->type = ppc_fpr_norm; if (a->s == b->s) { res->s = a->s; ppc_fpu_add_quadro_m(res, a, b); int X_prime = res->m1 & 1; if (res->m0 & (1ULL<<(107-64))) { ppc_fpu_quadro_mshr(res, 1); res->e++; } // res = [107] res->m1 = (res->m1 & 0xfffffffffffffffeULL) | X_prime; } else { res->s = a->s; int cmp; if (a->m0 < b->m0) { cmp = -1; } else if (a->m0 > b->m0) { cmp = +1; } else { if (a->m1 < b->m1) { cmp = -1; } else if (a->m1 > b->m1) { cmp = +1; } else { cmp = 0; } } if (!cmp) { if (FPSCR_RN(gCPU.fpscr) == FPSCR_RN_MINF) { res->s |= b->s; } else { res->s &= b->s; } res->type = ppc_fpr_zero; } else { if (cmp < 0) { ppc_fpu_sub_quadro_m(res, b, a); res->s = b->s; } else { ppc_fpu_sub_quadro_m(res, a, b); } diff = ppc_fpu_normalize_quadro(res) - (128-107); int X_prime = res->m1 & 1; res->m1 &= 0xfffffffffffffffeULL; ppc_fpu_quadro_mshl(res, diff); res->e -= diff; res->m1 |= X_prime; } // res = [107] } break; } case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_NaN): res->s = a->s; res->type = ppc_fpr_NaN; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_zero): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_zero): res->e = a->e; res->s = a->s; res->m0 = a->m0; res->m1 = a->m1; res->type = a->type; break; case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_NaN): res->e = b->e; res->s = b->s; res->m0 = b->m0; res->m1 = b->m1; res->type = b->type; break; case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_Inf): if (a->s != b->s) { // +oo + -oo == NaN res->s = a->s ^ b->s; res->type = ppc_fpr_NaN; break; } // fall-thru case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_zero): res->s = a->s; res->type = a->type; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_Inf): res->s = b->s; res->type = b->type; break; case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_zero): // round bla res->type = ppc_fpr_zero; res->s = a->s && b->s; break; } } inline void ppc_fpu_add_uint64_carry(uint64 *a, uint64 b, uint64 *carry) { *carry = (*a+b < *a) ? 1 : 0; *a += b; } // 'res' has 56 significant bits on return, a + b have 56 significant bits each inline void ppc_fpu_mul(ppc_double *res, const ppc_double *a, const ppc_double *b) { res->s = a->s ^ b->s; switch (PPC_FPR_TYPE2(a->type, b->type)) { case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_norm): { res->type = ppc_fpr_norm; res->e = a->e + b->e; // printf("new exp: %d\n", res.e); // ht_printf("MUL:\na.m: %qb\nb.m: %qb\n", a.m, b.m); uint64 fH, fM1, fM2, fL; fL = (a->m & 0xffffffff) * (b->m & 0xffffffff); // [32] * [32] = [63,64] fM1 = (a->m >> 32) * (b->m & 0xffffffff); // [24] * [32] = [55,56] fM2 = (a->m & 0xffffffff) * (b->m >> 32); // [32] * [24] = [55,56] fH = (a->m >> 32) * (b->m >> 32); // [24] * [24] = [47,48] // ht_printf("fH: %qx fM1: %qx fM2: %qx fL: %qx\n", fH, fM1, fM2, fL); // calulate fH * 2^64 + (fM1 + fM2) * 2^32 + fL uint64 rL, rH; rL = fL; // rL = rH = [63,64] rH = fH; // rH = fH = [47,48] uint64 split; split = fM1 + fM2; uint64 carry; ppc_fpu_add_uint64_carry(&rL, (split & 0xffffffff) << 32, &carry); // rL = [63,64] rH += carry; // rH = [0 .. 2^48] rH += split >> 32; // rH = [0:48], where 46, 47 or 48 set // res.m = [0 0 .. 0 | rH_48 rH_47 .. rH_0 | rL_63 rL_62 .. rL_55] // [---------------------------------------------------------] // bit = [63 62 .. 58 | 57 56 .. 9 | 8 7 0 ] // [---------------------------------------------------------] // [15 bits zero | 49 bits rH | 8 most sign.bits rL ] res->m = rH << 9; res->m |= rL >> (64-9); // res.m = [58] // ht_printf("fH: %qx fM1: %qx fM2: %qx fL: %qx\n", fH, fM1, fM2, fL); if (res->m & (1ULL << 57)) { res->m >>= 2; res->e += 2; } else if (res->m & (1ULL << 56)) { res->m >>= 1; res->e++; } // res.m = [56] break; } case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_NaN): res->type = a->type; res->e = a->e; break; case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_zero): res->s = a->s; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_zero): res->type = a->type; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_NaN): res->s = b->s; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_zero): res->type = b->type; break; case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_zero): res->type = ppc_fpr_NaN; break; } } // 'res' has 'prec' significant bits on return, a + b have 56 significant bits each // for 111 >= prec >= 64 inline void ppc_fpu_mul_quadro(ppc_quadro *res, ppc_double *a, ppc_double *b, int prec) { res->s = a->s ^ b->s; switch (PPC_FPR_TYPE2(a->type, b->type)) { case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_norm): { res->type = ppc_fpr_norm; res->e = a->e + b->e; // printf("new exp: %d\n", res.e); // ht_printf("MUL:\na.m: %016qx\nb.m: %016qx\n", a.m, b.m); uint64 fH, fM1, fM2, fL; fL = (a->m & 0xffffffff) * (b->m & 0xffffffff); // [32] * [32] = [63,64] fM1 = (a->m >> 32) * (b->m & 0xffffffff); // [24] * [32] = [55,56] fM2 = (a->m & 0xffffffff) * (b->m >> 32); // [32] * [24] = [55,56] fH = (a->m >> 32) * (b->m >> 32); // [24] * [24] = [47,48] // ht_printf("fH: %016qx fM1: %016qx fM2: %016qx fL: %016qx\n", fH, fM1, fM2, fL); // calulate fH * 2^64 + (fM1 + fM2) * 2^32 + fL uint64 rL, rH; rL = fL; // rL = rH = [63,64] rH = fH; // rH = fH = [47,48] uint64 split; split = fM1 + fM2; uint64 carry; ppc_fpu_add_uint64_carry(&rL, (split & 0xffffffff) << 32, &carry); // rL = [63,64] rH += carry; // rH = [0 .. 2^48] rH += split >> 32; // rH = [0:48], where 46, 47 or 48 set // res.m0 = [0 0 .. 0 | rH_48 rH_47 .. rH_0 | rL_63 rL_62 .. rL_0] // [-----------------------------------------------------------] // log.bit= [127 126 .. 113 | 112 64 | 63 62 0 ] // [-----------------------------------------------------------] // [ 15 bits zero | 49 bits rH | 64 bits rL ] res->m0 = rH; res->m1 = rL; // res.m0|res.m1 = [111,112,113] // ht_printf("res = %016qx%016qx\n", res.m0, res.m1); if (res->m0 & (1ULL << 48)) { ppc_fpu_quadro_mshr(res, 2+(111-prec)); res->e += 2; } else if (res->m0 & (1ULL << 47)) { ppc_fpu_quadro_mshr(res, 1+(111-prec)); res->e += 1; } else { ppc_fpu_quadro_mshr(res, 111-prec); } // res.m0|res.m1 = [prec] break; } case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_NaN): res->type = a->type; res->e = a->e; break; case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_zero): res->s = a->s; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_zero): res->type = a->type; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_NaN): res->s = b->s; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_zero): res->type = b->type; break; case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_zero): res->type = ppc_fpr_NaN; break; } } // calculate one of these: // + m1 * m2 + s // + m1 * m2 - s // - m1 * m2 + s // - m1 * m2 - s // using a 106 bit accumulator // // .752 // // FIXME: There is a bug in this code that shows up in Mac OS X Finder fwd/bwd // button: the top line is not rendered correctly. This works with the jitc_x86 // FPU however... inline void ppc_fpu_mul_add(ppc_double *res, ppc_double *m1, ppc_double *m2, ppc_double *s) { ppc_quadro p; /* ht_printf("m1 = %d * %016qx * 2^%d, %s\n", m1.s, m1.m, m1.e, ppc_fpu_get_fpr_type(m1.type)); ht_printf("m2 = %d * %016qx * 2^%d, %s\n", m2.s, m2.m, m2.e, ppc_fpu_get_fpr_type(m2.type));*/ // create product with 106 significant bits ppc_fpu_mul_quadro(&p, m1, m2, 106); /* ht_printf("p = %d * %016qx%016qx * 2^%d, %s\n", p.s, p.m0, p.m1, p.e, ppc_fpu_get_fpr_type(p.type));*/ // convert s into ppc_quadro /* ht_printf("s = %d * %016qx * 2^%d %s\n", s.s, s.m, s.e, ppc_fpu_get_fpr_type(s.type));*/ ppc_quadro q; q.e = s->e; q.s = s->s; q.type = s->type; q.m0 = 0; q.m1 = s->m; // .. with 106 significant bits ppc_fpu_quadro_mshl(&q, 106-56); /* ht_printf("q = %d * %016qx%016qx * 2^%d %s\n", q.s, q.m0, q.m1, q.e, ppc_fpu_get_fpr_type(q.type));*/ // now we must add p, q. ppc_quadro x; ppc_fpu_add_quadro(&x, &p, &q); // x = [107] /* ht_printf("x = %d * %016qx%016qx * 2^%d %s\n", x.s, x.m0, x.m1, x.e, ppc_fpu_get_fpr_type(x.type));*/ res->type = x.type; res->s = x.s; res->e = x.e; if (x.type == ppc_fpr_norm) { res->m = x.m0 << 13; // 43 bits from m0 res->m |= (x.m1 >> (64-12)) << 1; // 12 bits from m1 res->m |= x.m1 & 1; // X' bit from m1 } /* ht_printf("res = %d * %016qx * 2^%d %s\n", res.s, res.m, res.e, ppc_fpu_get_fpr_type(res.type));*/ } inline void ppc_fpu_div(ppc_double *res, const ppc_double *a, const ppc_double *b) { res->s = a->s ^ b->s; switch (PPC_FPR_TYPE2(a->type, b->type)) { case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_norm): { res->type = ppc_fpr_norm; res->e = a->e - b->e; res->m = 0; uint64 am = a->m, bm = b->m; uint i = 0; while (am && (i<56)) { res->m <<= 1; if (am >= bm) { res->m |= 1; am -= bm; } am <<= 1; // printf("am=%llx, bm=%llx, rm=%llx\n", am, bm, res.m); i++; } res->m <<= 57-i; if (res->m & (1ULL << 56)) { res->m >>= 1; } else { res->e--; } // printf("final: am=%llx, bm=%llx, rm=%llx\n", am, bm, res.m); break; } case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_NaN): res->e = a->e; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_NaN, ppc_fpr_zero): res->s = a->s; // fall-thru case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_norm): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_norm): res->type = a->type; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_NaN): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_NaN): res->s = b->s; res->type = b->type; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_Inf): res->type = ppc_fpr_zero; break; case PPC_FPR_TYPE2(ppc_fpr_norm, ppc_fpr_zero): res->type = ppc_fpr_Inf; break; case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_Inf, ppc_fpr_zero): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_Inf): case PPC_FPR_TYPE2(ppc_fpr_zero, ppc_fpr_zero): res->type = ppc_fpr_NaN; break; } } inline void ppc_fpu_sqrt(ppc_double *D, const ppc_double *B) { switch (B->type) { case ppc_fpr_norm: if (B->s) { D->type = ppc_fpr_NaN; gCPU.fpscr |= FPSCR_VXSQRT; break; } // D := 1/2(D_old + B/D_old) *D = *B; D->e /= 2; int i; for (i=0; i<6; i++) { ppc_double D_old = *D; ppc_double B_div_D_old; ppc_fpu_div(&B_div_D_old, B, &D_old); ppc_fpu_add(D, &D_old, &B_div_D_old); D->e--; /* uint64 e; ppc_double E = D; ppc_fpu_pack_double(E, e); printf("%.20f\n", *(double *)&e);*/ } break; case ppc_fpr_zero: D->type = ppc_fpr_zero; D->s = B->s; break; case ppc_fpr_Inf: if (B->s) { D->type = ppc_fpr_NaN; gCPU.fpscr |= FPSCR_VXSQRT; } else { D->type = ppc_fpr_Inf; D->s = 0; } break; case ppc_fpr_NaN: D->type = ppc_fpr_NaN; break; } } void ppc_fpu_test() { ppc_double A, B, C; double a, b, c; A.type = B.type = ppc_fpr_norm; A.s = 1; A.e = 0; A.m = 0; A.m = ((1ULL<<56)-1)-((1ULL<<10)-1); ht_printf("%qb\n", A.m); B.s = 1; B.e = 0; B.m = 0; B.m = ((1ULL<<56)-1)-((1ULL<<50)-1); a = ppc_fpu_get_double(&A); b = ppc_fpu_get_double(&B); printf("%f + %f = \n", a, b); ppc_fpu_add(&C, &A, &B); uint64 d; uint32 s; ppc_fpu_pack_double_as_single(&C, &d); ht_printf("%064qb\n", d); ppc_fpu_unpack_double(&C, d); ppc_fpu_pack_single(&C, &s); ht_printf("single: %032b\n", s); ppc_single Cs; ppc_fpu_unpack_single(&Cs, s); ppc_fpu_single_to_double(&Cs, &C); // ht_printf("%d\n", ppc_fpu_double_to_int(C)); c = ppc_fpu_get_double(&C); printf("%f\n", c); } /* * a and b must not be NaNs */ inline uint32 ppc_fpu_compare(ppc_double *a, ppc_double *b) { if (a->type == ppc_fpr_zero) { if (b->type == ppc_fpr_zero) return 2; return (b->s) ? 4: 8; } if (b->type == ppc_fpr_zero) return (a->s) ? 8: 4; if (a->s != b->s) return (a->s) ? 8: 4; if (a->e > b->e) return (a->s) ? 8: 4; if (a->e < b->e) return (a->s) ? 4: 8; if (a->m > b->m) return (a->s) ? 8: 4; if (a->m < b->m) return (a->s) ? 4: 8; return 2; } double ppc_fpu_get_double_uint(uint64 d) { ppc_double dd; ppc_fpu_unpack_double(&dd, d); return ppc_fpu_get_double(&dd); } double ppc_fpu_get_double(ppc_double *d) { if (d->type == ppc_fpr_norm) { double r = d->m; int i; for (i=0; i<55; i++) { r = r / 2.0; } if (d->e < 0) { int i; for (i=0; i>d->e; i--) { r = r / 2.0; } } else if (d->e > 0) { int i; for (i=0; i<d->e; i++) { r = r * 2.0; } } if (d->s) r = -r; return r; } else { return 0.0; } } /*********************************************************************************** * */ /* * fabsx Floating Absolute Value * .484 */ void ppc_opc_fabsx() { int frD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, frA, frB); PPC_OPC_ASSERT(frA==0); gCPU.fpr[frD] = gCPU.fpr[frB] & ~FPU_SIGN_BIT; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fabs.\n"); } } /* * faddx Floating Add (Double-Precision) * .485 */ void ppc_opc_faddx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frC==0); ppc_double A, B, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); if (A.s != B.s && A.type == ppc_fpr_Inf && B.type == ppc_fpr_Inf) { gCPU.fpscr |= FPSCR_VXISI; } ppc_fpu_add(&D, &A, &B); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fadd.\n"); } } /* * faddx Floating Add Single * .486 */ void ppc_opc_faddsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frC==0); ppc_double A, B, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); if (A.s != B.s && A.type == ppc_fpr_Inf && B.type == ppc_fpr_Inf) { gCPU.fpscr |= FPSCR_VXISI; } ppc_fpu_add(&D, &A, &B); gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fadds.\n"); } } /* * fcmpo Floating Compare Ordered * .488 */ static uint32 ppc_fpu_cmp_and_mask[8] = { 0xfffffff0, 0xffffff0f, 0xfffff0ff, 0xffff0fff, 0xfff0ffff, 0xff0fffff, 0xf0ffffff, 0x0fffffff, }; void ppc_opc_fcmpo() { int crfD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, crfD, frA, frB); crfD >>= 2; ppc_double A, B; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); uint32 cmp; if (A.type == ppc_fpr_NaN || B.type == ppc_fpr_NaN) { gCPU.fpscr |= FPSCR_VXSNAN; /*if (bla)*/ gCPU.fpscr |= FPSCR_VXVC; cmp = 1; } else { cmp = ppc_fpu_compare(&A, &B); } crfD = 7-crfD; gCPU.fpscr &= ~0x1f000; gCPU.fpscr |= (cmp << 12); gCPU.cr &= ppc_fpu_cmp_and_mask[crfD]; gCPU.cr |= (cmp << (crfD * 4)); } /* * fcmpu Floating Compare Unordered * .489 */ void ppc_opc_fcmpu() { int crfD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, crfD, frA, frB); crfD >>= 2; ppc_double A, B; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); uint32 cmp; if (A.type == ppc_fpr_NaN || B.type == ppc_fpr_NaN) { gCPU.fpscr |= FPSCR_VXSNAN; cmp = 1; } else { cmp = ppc_fpu_compare(&A, &B); } crfD = 7-crfD; gCPU.fpscr &= ~0x1f000; gCPU.fpscr |= (cmp << 12); gCPU.cr &= ppc_fpu_cmp_and_mask[crfD]; gCPU.cr |= (cmp << (crfD * 4)); } /* * fctiwx Floating Convert to Integer Word * .492 */ void ppc_opc_fctiwx() { int frD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, frA, frB); PPC_OPC_ASSERT(frA==0); ppc_double B; ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); gCPU.fpr[frD] = ppc_fpu_double_to_int(&B); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fctiw.\n"); } } /* * fctiwzx Floating Convert to Integer Word with Round toward Zero * .493 */ void ppc_opc_fctiwzx() { int frD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, frA, frB); PPC_OPC_ASSERT(frA==0); uint32 oldfpscr = gCPU.fpscr; gCPU.fpscr &= ~3; gCPU.fpscr |= 1; ppc_double B; ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); gCPU.fpr[frD] = ppc_fpu_double_to_int(&B); gCPU.fpscr = oldfpscr; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fctiwz.\n"); } } /* * fdivx Floating Divide (Double-Precision) * .494 */ void ppc_opc_fdivx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frC==0); ppc_double A, B, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); if (A.type == ppc_fpr_zero && B.type == ppc_fpr_zero) { gCPU.fpscr |= FPSCR_VXZDZ; } if (A.type == ppc_fpr_Inf && B.type == ppc_fpr_Inf) { gCPU.fpscr |= FPSCR_VXIDI; } if (B.type == ppc_fpr_zero && A.type != ppc_fpr_zero) { // FIXME:: gCPU.fpscr |= FPSCR_VXIDI; } ppc_fpu_div(&D, &A, &B); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fdiv.\n"); } } /* * fdivsx Floating Divide Single * .495 */ void ppc_opc_fdivsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frC==0); ppc_double A, B, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); if (A.type == ppc_fpr_zero && B.type == ppc_fpr_zero) { gCPU.fpscr |= FPSCR_VXZDZ; } if (A.type == ppc_fpr_Inf && B.type == ppc_fpr_Inf) { gCPU.fpscr |= FPSCR_VXIDI; } if (B.type == ppc_fpr_zero && A.type != ppc_fpr_zero) { // FIXME:: gCPU.fpscr |= FPSCR_VXIDI; } ppc_fpu_div(&D, &A, &B); gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fdivs.\n"); } } /* * fmaddx Floating Multiply-Add (Double-Precision) * .496 */ void ppc_opc_fmaddx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); ppc_fpu_mul_add(&D, &A, &C, &B); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fmadd.\n"); } } /* * fmaddx Floating Multiply-Add Single * .497 */ void ppc_opc_fmaddsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); ppc_fpu_mul_add(&D, &A, &C, &B); gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fmadds.\n"); } } /* * fmrx Floating Move Register * .498 */ void ppc_opc_fmrx() { int frD, rA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, rA, frB); PPC_OPC_ASSERT(rA==0); gCPU.fpr[frD] = gCPU.fpr[frB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fmr.\n"); } } /* * fmsubx Floating Multiply-Subtract (Double-Precision) * .499 */ void ppc_opc_fmsubx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); B.s ^= 1; ppc_fpu_mul_add(&D, &A, &C, &B); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fmsub.\n"); } } /* * fmsubsx Floating Multiply-Subtract Single * .500 */ void ppc_opc_fmsubsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); ppc_fpu_mul_add(&D, &A, &C, &B); gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fmsubs.\n"); } } /* * fmulx Floating Multipy (Double-Precision) * .501 */ void ppc_opc_fmulx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frB==0); ppc_double A, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); if ((A.type == ppc_fpr_Inf && C.type == ppc_fpr_zero) || (A.type == ppc_fpr_zero && C.type == ppc_fpr_Inf)) { gCPU.fpscr |= FPSCR_VXIMZ; } ppc_fpu_mul(&D, &A, &C); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); // *((double*)&gCPU.fpr[frD]) = *((double*)(&gCPU.fpr[frA]))*(*((double*)(&gCPU.fpr[frC]))); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fmul.\n"); } } /* * fmulsx Floating Multipy Single * .502 */ void ppc_opc_fmulsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frB==0); ppc_double A, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); if ((A.type == ppc_fpr_Inf && C.type == ppc_fpr_zero) || (A.type == ppc_fpr_zero && C.type == ppc_fpr_Inf)) { gCPU.fpscr |= FPSCR_VXIMZ; } ppc_fpu_mul(&D, &A, &C); gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fmuls.\n"); } } /* * fnabsx Floating Negative Absolute Value * .503 */ void ppc_opc_fnabsx() { int frD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, frA, frB); PPC_OPC_ASSERT(frA==0); gCPU.fpr[frD] = gCPU.fpr[frB] | FPU_SIGN_BIT; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fnabs.\n"); } } /* * fnegx Floating Negate * .504 */ void ppc_opc_fnegx() { int frD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, frA, frB); PPC_OPC_ASSERT(frA==0); gCPU.fpr[frD] = gCPU.fpr[frB] ^ FPU_SIGN_BIT; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fneg.\n"); } } /* * fnmaddx Floating Negative Multiply-Add (Double-Precision) * .505 */ void ppc_opc_fnmaddx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D/*, E*/; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); ppc_fpu_mul_add(&D, &A, &C, &B); D.s ^= 1; gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fnmadd.\n"); } } /* * fnmaddsx Floating Negative Multiply-Add Single * .506 */ void ppc_opc_fnmaddsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); ppc_fpu_mul_add(&D, &A, &C, &B); D.s ^= 1; gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fnmadds.\n"); } } /* * fnmsubx Floating Negative Multiply-Subtract (Double-Precision) * .507 */ void ppc_opc_fnmsubx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); B.s ^= 1; ppc_fpu_mul_add(&D, &A, &C, &B); D.s ^= 1; gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fnmsub.\n"); } } /* * fnsubsx Floating Negative Multiply-Subtract Single * .508 */ void ppc_opc_fnmsubsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A, B, C, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_unpack_double(&C, gCPU.fpr[frC]); B.s ^= 1; ppc_fpu_mul_add(&D, &A, &C, &B); D.s ^= 1; gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fnmsubs.\n"); } } /* * fresx Floating Reciprocal Estimate Single * .509 */ void ppc_opc_fresx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frA==0 && frC==0); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fres.\n"); } PPC_FPU_ERR("fres\n"); } /* * frspx Floating Round to Single * .511 */ void ppc_opc_frspx() { int frD, frA, frB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, frA, frB); PPC_OPC_ASSERT(frA==0); ppc_double B; ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); gCPU.fpscr |= ppc_fpu_pack_double_as_single(&B, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("frsp.\n"); } } /* * frsqrtex Floating Reciprocal Square Root Estimate * .512 */ void ppc_opc_frsqrtex() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frA==0 && frC==0); ppc_double B; ppc_double D; ppc_double E; ppc_double Q; ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_sqrt(&Q, &B); E.type = ppc_fpr_norm; E.s = 0; E.e = 0; E.m = 0x80000000000000ULL; ppc_fpu_div(&D, &E, &Q); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("frsqrte.\n"); } } /* * fselx Floating Select * .514 */ void ppc_opc_fselx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); ppc_double A; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); if (A.type == ppc_fpr_NaN || (A.type != ppc_fpr_zero && A.s)) { gCPU.fpr[frD] = gCPU.fpr[frB]; } else { gCPU.fpr[frD] = gCPU.fpr[frC]; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fsel.\n"); } } /* * fsqrtx Floating Square Root (Double-Precision) * .515 */ void ppc_opc_fsqrtx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frA==0 && frC==0); ppc_double B; ppc_double D; ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); ppc_fpu_sqrt(&D, &B); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fsqrt.\n"); } } /* * fsqrtsx Floating Square Root Single * .515 */ void ppc_opc_fsqrtsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frA==0 && frC==0); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fsqrts.\n"); } PPC_FPU_ERR("fsqrts\n"); } /* * fsubx Floating Subtract (Double-Precision) * .517 */ void ppc_opc_fsubx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frC==0); ppc_double A, B, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); if (B.type != ppc_fpr_NaN) { B.s ^= 1; } if (A.s != B.s && A.type == ppc_fpr_Inf && B.type == ppc_fpr_Inf) { gCPU.fpscr |= FPSCR_VXISI; } ppc_fpu_add(&D, &A, &B); gCPU.fpscr |= ppc_fpu_pack_double(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fsub.\n"); } } /* * fsubsx Floating Subtract Single * .518 */ void ppc_opc_fsubsx() { int frD, frA, frB, frC; PPC_OPC_TEMPL_A(gCPU.current_opc, frD, frA, frB, frC); PPC_OPC_ASSERT(frC==0); ppc_double A, B, D; ppc_fpu_unpack_double(&A, gCPU.fpr[frA]); ppc_fpu_unpack_double(&B, gCPU.fpr[frB]); if (B.type != ppc_fpr_NaN) { B.s ^= 1; } if (A.s != B.s && A.type == ppc_fpr_Inf && B.type == ppc_fpr_Inf) { gCPU.fpscr |= FPSCR_VXISI; } ppc_fpu_add(&D, &A, &B); gCPU.fpscr |= ppc_fpu_pack_double_as_single(&D, &(gCPU.fpr[frD])); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_FPU_ERR("fsubs.\n"); } } ��������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/tracers.h����������������������������������������������������������0000644�0001750�0000144�00000015336�10635115336�017054� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * tracers.h * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __TRACERS_H__ #define __TRACERS_H__ #include "types.h" #include "snprintf.h" #define ht_printf(...) #define ht_fprintf(...) #define ht_vfprintf(...) //#define SINGLESTEP //#define PPC_CPU_TRACE(msg...) ht_printf("[CPU/CPU] "msg) #define PPC_CPU_TRACE(msg...) #define PPC_ALU_TRACE(msg...) ht_printf("[CPU/ALU] "msg) #define PPC_FPU_TRACE(msg...) ht_printf("[CPU/FPU] "msg) #define PPC_DEC_TRACE(msg...) ht_printf("[CPU/DEC] "msg) #define PPC_ESC_TRACE(msg...) ht_printf("[CPU/ESC] "msg) //#define PPC_EXC_TRACE(msg...) ht_printf("[CPU/EXC] "msg) #define PPC_EXC_TRACE(msg...) #define PPC_MMU_TRACE(msg...) ht_printf("[CPU/MMU] "msg) #define PPC_OPC_TRACE(msg...) ht_printf("[CPU/OPC] "msg) //#define IO_PROM_TRACE(msg...) ht_printf("[IO/PROM] "msg) //#define IO_PROM_FS_TRACE(msg...) ht_printf("[IO/PROM/FS] "msg) //#define IO_3C90X_TRACE(msg...) ht_printf("[IO/3c90x] "msg) //#define IO_RTL8139_TRACE(msg...) ht_printf("[IO/rtl8139] "msg) //#define IO_GRAPHIC_TRACE(msg...) ht_printf("[IO/GCARD] "msg) //#define IO_CUDA_TRACE(msg...) ht_printf("[IO/CUDA] "msg) //#define IO_PIC_TRACE(msg...) ht_printf("[IO/PIC] "msg) //#define IO_PCI_TRACE(msg...) ht_printf("[IO/PCI] "msg) //#define IO_MACIO_TRACE(msg...) ht_printf("[IO/MACIO] "msg) //#define IO_NVRAM_TRACE(msg...) ht_printf("[IO/NVRAM] "msg) //#define IO_IDE_TRACE(msg...) ht_printf("[IO/IDE] "msg) //#define IO_USB_TRACE(msg...) ht_printf("[IO/USB] "msg) #define IO_CORE_TRACE(msg...) ht_printf("[IO/Generic] "msg) //#define PPC_CPU_WARN(msg...) ht_printf("[CPU/CPU] <Warning> "msg) #define PPC_CPU_WARN(msg...) #define PPC_ALU_WARN(msg...) ht_printf("[CPU/ALU] <Warning> "msg) #define PPC_FPU_WARN(msg...) ht_printf("[CPU/FPU] <Warning> "msg) #define PPC_DEC_WARN(msg...) ht_printf("[CPU/DEC] <Warning> "msg) #define PPC_ESC_WARN(msg...) ht_printf("[CPU/ESC] <Warning> "msg) //#define PPC_EXC_WARN(msg...) ht_printf("[CPU/EXC] <Warning> "msg) #define PPC_EXC_WARN #define PPC_MMU_WARN(msg...) ht_printf("[CPU/MMU] <Warning> "msg) //#define PPC_OPC_WARN(msg...) ht_printf("[CPU/OPC] <Warning> "msg) #define PPC_OPC_WARN(msg...) #define IO_PROM_WARN(msg...) ht_printf("[IO/PROM] <Warning> "msg) #define IO_PROM_FS_WARN(msg...) ht_printf("[IO/PROM/FS] <Warning> "msg) #define IO_3C90X_WARN(msg...) ht_printf("[IO/3c90x] <Warning> "msg) #define IO_RTL8139_WARN(msg...) ht_printf("[IO/rtl8139] <Warning> "msg) #define IO_GRAPHIC_WARN(msg...) ht_printf("[IO/GCARD] <Warning> "msg) #define IO_CUDA_WARN(msg...) ht_printf("[IO/CUDA] <Warning> "msg) #define IO_PIC_WARN(msg...) ht_printf("[IO/PIC] <Warning> "msg) #define IO_PCI_WARN(msg...) ht_printf("[IO/PCI] <Warning> "msg) #define IO_MACIO_WARN(msg...) ht_printf("[IO/MACIO] <Warning> "msg) #define IO_NVRAM_WARN(msg...) ht_printf("[IO/NVRAM] <Warning> "msg) #define IO_IDE_WARN(msg...) ht_printf("[IO/IDE] <Warning> "msg) #define IO_USB_WARN(msg...) ht_printf("[IO/USB] <Warning> "msg) //#define IO_CORE_WARN(msg...) ht_printf("[IO/Generic] <Warning> "msg) #define IO_CORE_WARN(msg...) //#define PPC_CPU_ERR(msg...) {ht_printf("[CPU/CPU] <Error> "msg);exit(1); } #define PPC_CPU_ERR(msg...) //#define PPC_ALU_ERR(msg...) {ht_printf("[CPU/ALU] <Error> "msg);exit(1); } #define PPC_ALU_ERR(msg...) //#define PPC_FPU_ERR(msg...) {ht_printf("[CPU/FPU] <Error> "msg);exit(1); } #define PPC_FPU_ERR #define PPC_DEC_ERR(msg...) {ht_printf("[CPU/DEC] <Error> "msg);exit(1); } #define PPC_ESC_ERR(msg...) {ht_printf("[CPU/ESC] <Error> "msg);exit(1); } //#define PPC_EXC_ERR(msg...) {ht_printf("[CPU/EXC] <Error> "msg);exit(1); } #define PPC_EXC_ERR(msg...) #define PPC_MMU_ERR(msg...) {ht_printf("[CPU/MMU] <Error> "msg);exit(1); } //#define PPC_OPC_ERR(msg...) {ht_printf("[CPU/OPC] <Error> "msg);exit(1); } #define PPC_OPC_ERR(msg...) #define IO_PROM_ERR(msg...) {ht_printf("[IO/PROM] <Error> "msg);exit(1); } #define IO_PROM_FS_ERR(msg...) {ht_printf("[IO/PROM/FS] <Error> "msg);exit(1); } #define IO_3C90X_ERR(msg...) {ht_printf("[IO/3c90x] <Error> "msg);exit(1); } #define IO_RTL8139_ERR(msg...) {ht_printf("[IO/rtl8139] <Error> "msg);exit(1); } #define IO_GRAPHIC_ERR(msg...) {ht_printf("[IO/GCARD] <Error> "msg);exit(1); } #define IO_CUDA_ERR(msg...) {ht_printf("[IO/CUDA] <Error> "msg);exit(1); } #define IO_PIC_ERR(msg...) {ht_printf("[IO/PIC] <Error> "msg);exit(1); } #define IO_PCI_ERR(msg...) {ht_printf("[IO/PCI] <Error> "msg);exit(1); } #define IO_MACIO_ERR(msg...) {ht_printf("[IO/MACIO] <Error> "msg);exit(1); } #define IO_NVRAM_ERR(msg...) {ht_printf("[IO/NVRAM] <Error> "msg);exit(1); } #define IO_IDE_ERR(msg...) {ht_printf("[IO/IDE] <Error> "msg);exit(1); } #define IO_USB_ERR(msg...) {ht_printf("[IO/IDE] <Error> "msg);exit(1); } #define IO_CORE_ERR(msg...) {ht_printf("[IO/Generic] <Error> "msg);exit(1); } /* * */ #ifndef PPC_CPU_TRACE #define PPC_CPU_TRACE(msg...) #endif #ifndef PPC_ALU_TRACE #define PPC_ALU_TRACE(msg...) #endif #ifndef PPC_FPU_TRACE #define PPC_FPU_TRACE(msg...) #endif #ifndef PPC_DEC_TRACE #define PPC_DEC_TRACE(msg...) #endif #ifndef PPC_EXC_TRACE #define PPC_EXC_TRACE(msg...) #endif #ifndef PPC_ESC_TRACE #define PPC_ESC_TRACE(msg...) #endif #ifndef PPC_MMU_TRACE #define PPC_MMU_TRACE(msg...) #endif #ifndef PPC_OPC_TRACE #define PPC_OPC_TRACE(msg...) #endif #ifndef PPC_OPC_WARN #define PPC_OPC_WARN(msg...) #endif #ifndef IO_PROM_TRACE #define IO_PROM_TRACE(msg...) #endif #ifndef IO_PROM_FS_TRACE #define IO_PROM_FS_TRACE(msg...) #endif #ifndef IO_GRAPHIC_TRACE #define IO_GRAPHIC_TRACE(msg...) #endif #ifndef IO_CUDA_TRACE #define IO_CUDA_TRACE(msg...) #endif #ifndef IO_PIC_TRACE #define IO_PIC_TRACE(msg...) #endif #ifndef IO_PCI_TRACE #define IO_PCI_TRACE(msg...) #endif #ifndef IO_MACIO_TRACE #define IO_MACIO_TRACE(msg...) #endif #ifndef IO_ISA_TRACE #define IO_ISA_TRACE(msg...) #endif #ifndef IO_IDE_TRACE #define IO_IDE_TRACE(msg...) #endif #ifndef IO_CORE_TRACE #define IO_CORE_TRACE(msg...) #endif #ifndef IO_NVRAM_TRACE #define IO_NVRAM_TRACE(msg...) #endif #ifndef IO_USB_TRACE #define IO_USB_TRACE(msg...) #endif #ifndef IO_3C90X_TRACE #define IO_3C90X_TRACE(msg...) #endif #ifndef IO_RTL8139_TRACE #define IO_RTL8139_TRACE(msg...) #endif #endif ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_vec.h����������������������������������������������������������0000644�0001750�0000144�00000013723�10635115336�017026� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_vec.h * * Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nmsu.edu) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_VEC_H__ #define __PPC_VEC_H__ #define PPC_OPC_VRc (1<<10) /* Rather than write each function to be endianless, we're writing these * defines to do an endianless access to elements of the vector. * * These are for ADDRESSED vector elements. Usually, most vector operations * can be performed in either direction without care, so most of the * for-loops should not use these, as it will introduce unneeded code * for little-endian systems. */ #if HOST_ENDIANESS == HOST_ENDIANESS_LE #define VECT_B(reg, index) ((reg).b[15 - (index)]) #define VECT_SB(reg, index) ((reg).sb[15 - (index)]) #define VECT_H(reg, index) ((reg).h[7 - (index)]) #define VECT_SH(reg, index) ((reg).sh[7 - (index)]) #define VECT_W(reg, index) ((reg).w[3 - (index)]) #define VECT_SW(reg, index) ((reg).sw[3 - (index)]) #define VECT_D(reg, index) ((reg).d[1 - (index)]) #define VECT_SD(reg, index) ((reg).sd[1 - (index)]) #define VECT_EVEN(index) (((index) << 1) + 1) #define VECT_ODD(index) (((index) << 1) + 0) #elif HOST_ENDIANESS == HOST_ENDIANESS_BE #define VECT_B(reg, index) ((reg).b[(index)]) #define VECT_SB(reg, index) ((reg).sb[(index)]) #define VECT_H(reg, index) ((reg).h[(index)]) #define VECT_SH(reg, index) ((reg).sh[(index)]) #define VECT_W(reg, index) ((reg).w[(index)]) #define VECT_SW(reg, index) ((reg).sw[(index)]) #define VECT_D(reg, index) ((reg).d[(index)]) #define VECT_SD(reg, index) ((reg).sd[(index)]) #define VECT_EVEN(index) (((index) << 1) + 0) #define VECT_ODD(index) (((index) << 1) + 1) #else #error Endianess not supported! #endif //#define VECTOR_DEBUG fprintf(stderr, "[PPC/VEC] %s\n", __FUNCTION__) #define VECTOR_DEBUG //#define VECTOR_DEBUG_COMMON fprintf(stderr, "[PPC/VEC] %s\n", __FUNCTION__) #define VECTOR_DEBUG_COMMON /* Undefine this to turn of the MSR_VEC check for vector instructions. */ //#define __VEC_EXC_OFF__ #include "types.h" //#include "tools/snprintf.h" void ppc_opc_vperm(); void ppc_opc_vsel(); void ppc_opc_vsrb(); void ppc_opc_vsrh(); void ppc_opc_vsrw(); void ppc_opc_vsrab(); void ppc_opc_vsrah(); void ppc_opc_vsraw(); void ppc_opc_vsr(); void ppc_opc_vsro(); void ppc_opc_vslb(); void ppc_opc_vslh(); void ppc_opc_vslw(); void ppc_opc_vsl(); void ppc_opc_vslo(); void ppc_opc_vsldoi(); void ppc_opc_vrlb(); void ppc_opc_vrlh(); void ppc_opc_vrlw(); void ppc_opc_vmrghb(); void ppc_opc_vmrghh(); void ppc_opc_vmrghw(); void ppc_opc_vmrglb(); void ppc_opc_vmrglh(); void ppc_opc_vmrglw(); void ppc_opc_vspltb(); void ppc_opc_vsplth(); void ppc_opc_vspltw(); void ppc_opc_vspltisb(); void ppc_opc_vspltish(); void ppc_opc_vspltisw(); void ppc_opc_mfvscr(); void ppc_opc_mtvscr(); void ppc_opc_vpkuhum(); void ppc_opc_vpkuwum(); void ppc_opc_vpkpx(); void ppc_opc_vpkuhus(); void ppc_opc_vpkshss(); void ppc_opc_vpkuwus(); void ppc_opc_vpkswss(); void ppc_opc_vpkuhus(); void ppc_opc_vpkshus(); void ppc_opc_vpkuwus(); void ppc_opc_vpkswus(); void ppc_opc_vupkhsb(); void ppc_opc_vupkhpx(); void ppc_opc_vupkhsh(); void ppc_opc_vupklsb(); void ppc_opc_vupklpx(); void ppc_opc_vupklsh(); void ppc_opc_vaddubm(); void ppc_opc_vadduhm(); void ppc_opc_vadduwm(); void ppc_opc_vaddfp(); void ppc_opc_vaddcuw(); void ppc_opc_vaddubs(); void ppc_opc_vaddsbs(); void ppc_opc_vadduhs(); void ppc_opc_vaddshs(); void ppc_opc_vadduws(); void ppc_opc_vaddsws(); void ppc_opc_vsububm(); void ppc_opc_vsubuhm(); void ppc_opc_vsubuwm(); void ppc_opc_vsubfp(); void ppc_opc_vsubcuw(); void ppc_opc_vsububs(); void ppc_opc_vsubsbs(); void ppc_opc_vsubuhs(); void ppc_opc_vsubshs(); void ppc_opc_vsubuws(); void ppc_opc_vsubsws(); void ppc_opc_vmuleub(); void ppc_opc_vmulesb(); void ppc_opc_vmuleuh(); void ppc_opc_vmulesh(); void ppc_opc_vmuloub(); void ppc_opc_vmulosb(); void ppc_opc_vmulouh(); void ppc_opc_vmulosh(); void ppc_opc_vmaddfp(); void ppc_opc_vmhaddshs(); void ppc_opc_vmladduhm(); void ppc_opc_vmhraddshs(); void ppc_opc_vmsumubm(); void ppc_opc_vmsumuhm(); void ppc_opc_vmsummbm(); void ppc_opc_vmsumshm(); void ppc_opc_vmsumuhs(); void ppc_opc_vmsumshs(); void ppc_opc_vsum4ubs(); void ppc_opc_vsum4sbs(); void ppc_opc_vsum4shs(); void ppc_opc_vsum2sws(); void ppc_opc_vsumsws(); void ppc_opc_vnmsubfp(); void ppc_opc_vavgub(); void ppc_opc_vavgsb(); void ppc_opc_vavguh(); void ppc_opc_vavgsh(); void ppc_opc_vavguw(); void ppc_opc_vavgsw(); void ppc_opc_vmaxub(); void ppc_opc_vmaxsb(); void ppc_opc_vmaxuh(); void ppc_opc_vmaxsh(); void ppc_opc_vmaxuw(); void ppc_opc_vmaxsw(); void ppc_opc_vmaxfp(); void ppc_opc_vminub(); void ppc_opc_vminsb(); void ppc_opc_vminuh(); void ppc_opc_vminsh(); void ppc_opc_vminuw(); void ppc_opc_vminsw(); void ppc_opc_vminfp(); void ppc_opc_vrfin(); void ppc_opc_vrfip(); void ppc_opc_vrfim(); void ppc_opc_vrfiz(); void ppc_opc_vrefp(); void ppc_opc_vrsqrtefp(); void ppc_opc_vlogefp(); void ppc_opc_vexptefp(); void ppc_opc_vcfux(); void ppc_opc_vcfsx(); void ppc_opc_vctsxs(); void ppc_opc_vctuxs(); void ppc_opc_vand(); void ppc_opc_vandc(); void ppc_opc_vor(); void ppc_opc_vnor(); void ppc_opc_vxor(); void ppc_opc_vcmpequbx(); void ppc_opc_vcmpequhx(); void ppc_opc_vcmpequwx(); void ppc_opc_vcmpeqfpx(); void ppc_opc_vcmpgtubx(); void ppc_opc_vcmpgtsbx(); void ppc_opc_vcmpgtuhx(); void ppc_opc_vcmpgtshx(); void ppc_opc_vcmpgtuwx(); void ppc_opc_vcmpgtswx(); void ppc_opc_vcmpgtfpx(); void ppc_opc_vcmpgefpx(); void ppc_opc_vcmpbfpx(); #endif ���������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_arch_interface.c�����������������������������������������������0000644�0001750�0000144�00000032524�11013043633�021170� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * 12/06/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include "ppc_cpu.h" #include "ppc_mmu.h" #include "ppc_exc.h" #include "ppc_e500_exc.h" #include "ppc_memory.h" #include "ppc_io.h" #include "types.h" #include "tracers.h" #include "skyeye_types.h" #include "skyeye_config.h" #include "sysendian.h" #include "ppc_irq.h" #ifdef __CYGWIN__ #include <time.h> #endif PPC_CPU_State gCPU; /* For load OS image such as linux, we need to fill some entry in TLB to get 16M sdram mapped, then we can load linux to such memory */ static void bootloader(){ } static void ppc_reset_state () { } byte * init_ram; /* 16k init ram for 8560 */ byte * boot_rom; /* default 8M bootrom for 8560 */ byte * ddr_ram; /* 64M DDR SDRAM */ unsigned long init_ram_start_addr, init_ram_size; uint32 boot_romSize; uint32 boot_rom_start_addr; FILE * prof_file; static bool ppc_cpu_init() { memset(&gCPU, 0, sizeof gCPU); //gCPU.pvr = gConfig->getConfigInt(CPU_KEY_PVR); gCPU.cpm_reg.dpram = (void *)malloc(MPC8650_DPRAM_SIZE); if(!gCPU.cpm_reg.dpram){ printf("malloc failed for dpram\n"); skyeye_exit(-1); } else printf("malloc succ for dpram, dpram=0x%x\n", gCPU.cpm_reg.dpram); /* initialize decoder */ ppc_dec_init(); // initialize srs (mostly for prom) int i; for (i=0; i<16; i++) { gCPU.sr[i] = 0x2aa*i; } return true; } static void ppc_init_state () { ppc_cpu_init(); /* initial phsical memory to DEFAULT_GMEMORY_SIZE */ if(!(boot_rom = malloc(DEFAULT_BOOTROM_SIZE))){ fprintf(stderr, "can not initialize physical memory...\n"); skyeye_exit(-1); } /*we set start_addr */ boot_rom_start_addr = 0xFFFFFFFF - DEFAULT_BOOTROM_SIZE + 1; boot_romSize = DEFAULT_BOOTROM_SIZE; /* initialize init_ram parameters */ if(!(init_ram = malloc(INIT_RAM_SIZE))){ fprintf(stderr, "malloc failed!\n"); skyeye_exit(-1); } if(!(ddr_ram = malloc(DDR_RAM_SIZE))){ fprintf(stderr, "malloc failed!\n"); skyeye_exit(-1); } init_ram_size = INIT_RAM_SIZE; init_ram_start_addr = 0xe4010000; gCPU.por_conf.porpllsr = 0x40004; e500_mmu_init(); /* write something to a file for debug or profiling */ if (!prof_file) { prof_file = fopen ("./kernel_prof.txt", "w"); } /* Before boot linux, we need to do some preparation */ ppc_boot(); } typedef struct bd_s{ uint16 flag; uint16 len; uint32 buf_addr; }bd_t; static int scc1_io_do_cycle(){ byte * ram = &gCPU.cpm_reg.dpram[0]; /* Param is stored at 0x8000 for SCC1 */ int rx_base = 0x8000; /* Receive buffer base address */ int tx_base = 0x8002; /* Transmit buffer base address */ /* If SCC0 Receive enalbed */ if(gCPU.cpm_reg.scc[0].gsmrl & 0x00000020){ /* If we already in recv interrupt, we go out */ if(gCPU.cpm_reg.scc[0].scce & 0x1) goto out_of_recv; /* if interrupt is masked */ if(!(gCPU.cpm_reg.scc[0].sccm & 0x1)) goto out_of_recv; struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; /* max idle cound ,when it become zero, rx bd will be closed */ #define MAX_IDLE_COUNT 10 static int max_idle_count = MAX_IDLE_COUNT; uint32 buf_addr; short datlen; static int curr_rx_bd = 0; /* if max idle count not expire , we can still receive data */ /* get a char from current uart */ if (skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { /* build a bd for rx */ int recv_bd_base = ppc_half_from_BE(*(uint16 *)&ram[rx_base]); short bd_flag; gCPU.cpm_reg.scc[0].scce |= 0x1; /* set RX bit*/ /*if int is masked and scc1 interrupt is masked */ if(!(gCPU.int_ctrl.simr_l & 0x10)){ gCPU.int_ctrl.sipnr_l &= 0x10; /* set pending bit in SIPNR_L */ buf_addr = ppc_word_from_BE(*((uint32 *)&ram[recv_bd_base + curr_rx_bd + 4])); ddr_ram[buf_addr] = buf; /* Now we only implement that send a char once */ *((sint16 *)&ram[recv_bd_base + curr_rx_bd + 2]) = ppc_half_to_BE(0x1); bd_flag = ppc_half_from_BE(*(sint16 *)&ram[recv_bd_base + curr_rx_bd]); /* set empty bit to zero ,waiting core to read the date */ bd_flag &= ~0x8000; *((sint16 *)&ram[recv_bd_base + curr_rx_bd]) = ppc_half_to_BE(bd_flag); /* judge empty bit, if current bd not available, we use next bd */ if(bd_flag & 0x2000) /* check wrap bit */ curr_rx_bd = 0; /* Reset pointer to the begin addr of the bd table */ else curr_rx_bd += 8; /* indicate to next BD */ gCPU.pic_percpu.iack0 = SIU_INT_SCC1; /* trigger interrupt */ ppc_exception(EXT_INT, 0, gCPU.pc); } } } out_of_recv: /* If SCC0 transmit enabled */ if(gCPU.cpm_reg.scc[0].gsmrl & 0x00000010){ static int curr_tx_bd = 0; int trans_bd_base = ppc_half_from_BE(*(uint16 *)&ram[tx_base]); short bd_flag = ppc_half_from_BE(*(sint16 *)&ram[trans_bd_base + curr_tx_bd]); short bd_len = ppc_half_from_BE(*(sint16 *)&ram[trans_bd_base + curr_tx_bd + 2]); uint32 buf_addr = ppc_word_from_BE(*((uint32 *)&ram[trans_bd_base + curr_tx_bd + 4])); //fprintf(prof_file, "trans_bd_base=0x%x,curr_tx_bd=0x%x,bd_len=0x%x,buf_addr=0x%x\n",trans_bd_base, curr_tx_bd, bd_len, buf_addr); /* If data ready */ if(bd_flag & 0x8000){ int i = 0; for (;i < bd_len; i++){ char c = ddr_ram[buf_addr + i]; skyeye_uart_write(-1, &c, 1, NULL); } /* set Empty bit */ *((sint16 *)&ram[trans_bd_base + curr_tx_bd]) &= ppc_half_to_BE(~0x8000); if(bd_flag & 0x2000) /* check wrap bit */ curr_tx_bd = 0; /* Reset pointer to the begin addr of the bd table */ else curr_tx_bd += 8; /* indicate to next BD */ } } } #define TCR_DIE (1 << 26) #define TSR_DIS (1 << 27) static void dec_io_do_cycle(){ gCPU.tbl++; /** * test DIE bit of TCR if timer is enabled */ if(!(gCPU.tsr & 0x8000000)){ if((gCPU.tcr & 0x4000000) && (gCPU.msr & 0x8000)) { if(gCPU.dec > 0) gCPU.dec--; /* if decrementer eqauls zero */ if(gCPU.dec == 0){ /* if auto-load mode is set */ #if 0 if (gCPU.tcr & 0x400000) gCPU.dec = gCPU.decar; #endif /* trigger timer interrupt */ ppc_exception(DEC, 0, gCPU.pc); } } } } /* io cycle */ static void ppc_io_do_cycle(){ dec_io_do_cycle(); scc1_io_do_cycle(); } static void ppc_step_once () { uint ops=0; uint32 real_addr; if (true) { static uint32_t dbg_start = 0x1003ccf4; static uint32_t dbg_end = 0xfff83254; static int flag = 0; gCPU.npc = gCPU.pc + 4; switch( ppc_effective_to_physical(gCPU.pc, 0, &real_addr)) { case PPC_MMU_OK: break; /* we had TLB miss and need to jump to its handler */ case PPC_MMU_EXC: goto exec_npc; case PPC_MMU_FATAL: /* TLB miss */ fprintf(stderr, "TLB missed at 0x%x\n", gCPU.pc); skyeye_exit(-1); default: /* TLB miss */ fprintf(stderr, "Somethingwrong during address translation at 0x%x\n", gCPU.pc); skyeye_exit(-1); }; if(real_addr > boot_rom_start_addr) gCPU.current_opc = ppc_word_from_BE(*((int *)&boot_rom[real_addr - boot_rom_start_addr])); else if(real_addr >=0 && real_addr < DDR_RAM_SIZE) gCPU.current_opc = ppc_word_from_BE(*((int *)&ddr_ram[real_addr])); else{ fprintf(stderr,"Can not get instruction from addr 0x%x\n",real_addr); skyeye_exit(-1); } if(gCPU.pc == dbg_start) flag = 0; if(flag){ //fprintf(prof_file,"DBG:before pc=0x%x,r0=0x%x,r3=0x%x,r31=0x%x,ddr_ram[0xc21701e4 + 48]=0x%x\n", gCPU.pc, gCPU.gpr[0], gCPU.gpr[3], gCPU.gpr[31], *(int *)&ddr_ram[0x21701e4 + 48]); fprintf(prof_file,"DBG:before pc=0x%x,r0=0x%x,r1=0x%x,r3=0x%x,r4=0x%x,r5=0x%x,r8=0x%x,r30=0x%x, r31=0x%x, lr=0x%x\n", gCPU.pc, gCPU.gpr[0], gCPU.gpr[1], gCPU.gpr[3], gCPU.gpr[4], gCPU.gpr[5], gCPU.gpr[8], gCPU.gpr[30], gCPU.gpr[31], gCPU.lr); } ppc_exec_opc(); ppc_io_do_cycle(); exec_npc: gCPU.pc = gCPU.npc; } } static void ppc_set_pc (WORD pc) { gCPU.pc = pc; /* Fixme, for e500 core, the first instruction should be executed at 0xFFFFFFFC */ //gCPU.pc = 0xFFFFFFFC; } static WORD ppc_get_pc(){ return gCPU.pc; } /* * Since mmu of ppc always enabled, so we can write virtual address here */ static int ppc_ICE_write_byte (WORD addr, uint8_t v) { ppc_write_effective_byte(addr, v); /* if failed, return -1*/ return 0; } /* * Since mmu of ppc always enabled, so we can read virtual address here */ static int ppc_ICE_read_byte (WORD addr, uint8_t *pv){ // fprintf(stderr, "KSDBG:in %s, addr=0x%x\n", __FUNCTION__, addr); /** * work around for ppc debugger */ if ((addr & 0xFFFFF000) == 0xBFFFF000) return 0; ppc_read_effective_byte(addr, pv); return 0; } static int ppc_parse_cpu (const char *params[]) { return 0; } extern void mpc8560_mach_init(); machine_config_t ppc_machines[] = { /* machine define for MPC8560 */ {"mpc8560", mpc8560_mach_init, NULL, NULL, NULL}, }; static int ppc_parse_mach (machine_config_t * mach, const char *params[]) { int i; for (i = 0; i < (sizeof (ppc_machines) / sizeof (machine_config_t)); i++) { if (!strncmp (params[0], ppc_machines[i].machine_name, MAX_PARAM_NAME)) { skyeye_config.mach = &ppc_machines[i]; SKYEYE_INFO ("mach info: name %s, mach_init addr %p\n", skyeye_config.mach->machine_name, skyeye_config.mach->mach_init); return 0; } } SKYEYE_ERR ("Error: Unkonw mach name \"%s\"\n", params[0]); return -1; } //static mem_config_t ppc_mem; static int ppc_parse_mem (int num_params, const char *params[]) { #if 0 char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, num; mem_config_t *mc = &ppc_mem; mem_bank_t *mb = mc->mem_banks; mc->bank_num = mc->current_num++; num = mc->current_num - 1; /*mem_banks should begin from 0. */ mb[num].filename[0] = '\0'; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: mem_bank %d has wrong parameter \"%s\".\n", num, name); if (!strncmp ("map", name, strlen (name))) { if (!strncmp ("M", value, strlen (value))) { mb[num].read_byte = ppc_read_byte; mb[num].write_byte = ppc_write_byte; mb[num].read_halfword = ppc_read_halfword; mb[num].write_halfword = ppc_write_halfword; mb[num].read_word = ppc_read_word; mb[num].write_word = ppc_write_word; mb[num].type = MEMTYPE_RAM; } else if (!strncmp ("I", value, strlen (value))) { mb[num].read_byte = ppc_read_byte; mb[num].write_byte = ppc_write_byte; mb[num].read_halfword = ppc_read_halfword; mb[num].write_halfword = ppc_write_halfword; mb[num].read_word = ppc_read_word; mb[num].write_word = ppc_write_word; mb[num].type = MEMTYPE_IO; /*ywc 2005-03-30 */ } else if (!strncmp ("F", value, strlen (value))) { mb[num].read_byte = ppc_read_byte; mb[num].write_byte = ppc_write_byte; mb[num].read_halfword = ppc_read_halfword; mb[num].write_halfword = ppc_write_halfword; mb[num].read_word = ppc_read_word; mb[num].write_word = ppc_write_word; mb[num].type = MEMTYPE_FLASH; } else { SKYEYE_ERR ("Error: mem_bank %d \"%s\" parameter has wrong value \"%s\"\n", num, name, value); } } else if (!strncmp ("type", name, strlen (name))) { //chy 2003-09-21: process type if (!strncmp ("R", value, strlen (value))) { if (mb[num].type == MEMTYPE_RAM) mb[num].type = MEMTYPE_ROM; mb[num].write_byte = warn_write_byte; mb[num].write_halfword = warn_write_halfword; mb[num].write_word = warn_write_word; } } else if (!strncmp ("addr", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].addr = strtoul (value, NULL, 16); else mb[num].addr = strtoul (value, NULL, 10); } else if (!strncmp ("size", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].len = strtoul (value, NULL, 16); else mb[num].len = strtoul (value, NULL, 10); } else if (!strncmp ("file", name, strlen (name))) { strncpy (mb[num].filename, value, strlen (value) + 1); } else if (!strncmp ("boot", name, strlen (name))) { /* this must be the last parameter. */ if (!strncmp ("yes", value, strlen (value))) skyeye_config.start_address = mb[num].addr; } else { SKYEYE_ERR ("Error: mem_bank %d has unknow parameter \"%s\".\n", num, name); } } #endif return 0; } void init_ppc_arch () { static arch_config_t ppc_arch; ppc_arch.arch_name = "ppc"; ppc_arch.init = ppc_init_state; ppc_arch.reset = ppc_reset_state; ppc_arch.set_pc = ppc_set_pc; ppc_arch.get_pc = ppc_get_pc; ppc_arch.step_once = ppc_step_once; ppc_arch.ICE_write_byte = ppc_ICE_write_byte; ppc_arch.ICE_read_byte = ppc_ICE_read_byte; ppc_arch.parse_cpu = ppc_parse_cpu; ppc_arch.parse_mach = ppc_parse_mach; ppc_arch.parse_mem = ppc_parse_mem; register_arch (&ppc_arch); } void print_ppc_arg(FILE * log){ if(log) fprintf(log, "r3=0x%x", gCPU.gpr[3]); } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_cpu.c����������������������������������������������������������0000644�0001750�0000144�00000017214�10702130757�017031� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_cpu.cc * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * Portions Copyright (C) 2004 Apple Computer, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "ppc_cpu.h" #include "ppc_dec.h" #include "ppc_fpu.h" #include "ppc_exc.h" #include "ppc_mmu.h" #include "ppc_tools.h" #include "tracers.h" #include "sysendian.h" #include <stdio.h> #include <stdarg.h> //#include "io/graphic/gcard.h" //PPC_CPU_State gCPU; //Debugger *gDebugger; static bool gSinglestep = false; //uint32 gBreakpoint2 = 0x11b3acf4; uint32 gBreakpoint3 = 0xc016ee74&0; uint32 gBreakpoint = 0x11b3acf4&0; uint32 gBreakpoint2 = 0xc017a4f4&0; bool activate = false; static inline void ppc_debug_hook() { if (gCPU.pc == gBreakpoint) { gSinglestep = true; // SINGLESTEP("breakpoint 1"); } if (gCPU.pc == gBreakpoint2) { //SINGLESTEP("breakpoint 2"); } // if (gCPU.pc == gBreakpoint3 && gCPU.gpr[5]==0x100004ec) { /* if (gCPU.pc == gBreakpoint3) { activate = true; SINGLESTEP("breakpoint 3"); }*/ /* if (gSinglestep) { gDebugger->enter(); }*/ } /*sys_mutex exception_mutex;*/ void ppc_cpu_atomic_raise_ext_exception() { /*sys_lock_mutex(exception_mutex);*/ gCPU.ext_exception = true; gCPU.exception_pending = true; /*sys_unlock_mutex(exception_mutex);*/ } void ppc_cpu_atomic_cancel_ext_exception() { /* sys_lock_mutex(exception_mutex); */ gCPU.ext_exception = false; if (!gCPU.dec_exception) gCPU.exception_pending = false; /*sys_unlock_mutex(exception_mutex);*/ } void ppc_cpu_atomic_raise_dec_exception() { /*sys_lock_mutex(exception_mutex);*/ gCPU.dec_exception = true; gCPU.exception_pending = true; /*sys_unlock_mutex(exception_mutex);*/ } void ppc_cpu_wakeup() { } void ppc_cpu_run() { /*gDebugger = new Debugger(); gDebugger->mAlwaysShowRegs = true;*/ PPC_CPU_TRACE("execution started at %08x\n", gCPU.pc); uint ops=0; gCPU.effective_code_page = 0xffffffff; // ppc_fpu_test(); // return; while (true) { gCPU.npc = gCPU.pc+4; if ((gCPU.pc & ~0xfff) == gCPU.effective_code_page) { gCPU.current_opc = ppc_word_from_BE(*((uint32*)(&gCPU.physical_code_page[gCPU.pc & 0xfff]))); ppc_debug_hook(); } else { int ret; if ((ret = ppc_direct_effective_memory_handle_code(gCPU.pc & ~0xfff, gCPU.physical_code_page))) { if (ret == PPC_MMU_EXC) { gCPU.pc = gCPU.npc; continue; } else { PPC_CPU_ERR("?\n"); } } gCPU.effective_code_page = gCPU.pc & ~0xfff; continue; } ppc_exec_opc(); ops++; gCPU.ptb++; if (gCPU.pdec == 0) { gCPU.exception_pending = true; gCPU.dec_exception = true; gCPU.pdec=0xffffffff*TB_TO_PTB_FACTOR; } else { gCPU.pdec--; } if ((ops & 0x3ffff)==0) { /* if (pic_check_interrupt()) { gCPU.exception_pending = true; gCPU.ext_exception = true; }*/ if ((ops & 0x0fffff)==0) { // uint32 j=0; // ppc_read_effective_word(0xc046b2f8, j); ht_printf("@%08x (%u ops) pdec: %08x lr: %08x\r", gCPU.pc, ops, gCPU.pdec, gCPU.lr); #if 0 extern uint32 PIC_enable_low; extern uint32 PIC_enable_high; ht_printf("enable "); int x = 1; for (int i=0; i<31; i++) { if (PIC_enable_low & x) { ht_printf("%d ", i); } x<<=1; } x=1; for (int i=0; i<31; i++) { if (PIC_enable_high & x) { ht_printf("%d ", 32+i); } x<<=1; } ht_printf("\n"); #endif } } gCPU.pc = gCPU.npc; if (gCPU.exception_pending) { if (gCPU.stop_exception) { gCPU.stop_exception = false; if (!gCPU.dec_exception && !gCPU.ext_exception) gCPU.exception_pending = false; break; } if (gCPU.msr & MSR_EE) { /*sys_lock_mutex(exception_mutex);*/ if (gCPU.ext_exception) { ppc_exception(PPC_EXC_EXT_INT,0,0); gCPU.ext_exception = false; gCPU.pc = gCPU.npc; if (!gCPU.dec_exception) gCPU.exception_pending = false; /*sys_unlock_mutex(exception_mutex);*/ continue; } if (gCPU.dec_exception) { ppc_exception(PPC_EXC_DEC,0,0); gCPU.dec_exception = false; gCPU.pc = gCPU.npc; gCPU.exception_pending = false; /*sys_unlock_mutex(exception_mutex);*/ continue; } /*sys_unlock_mutex(exception_mutex);*/ PPC_CPU_ERR("no interrupt, but signaled?!\n"); } } #ifdef PPC_CPU_ENABLE_SINGLESTEP if (gCPU.msr & MSR_SE) { if (gCPU.singlestep_ignore) { gCPU.singlestep_ignore = false; } else { ppc_exception(PPC_EXC_TRACE2); gCPU.pc = gCPU.npc; continue; } } #endif } } void ppc_cpu_stop() { /*sys_lock_mutex(exception_mutex);*/ gCPU.stop_exception = true; gCPU.exception_pending = true; /*sys_unlock_mutex(exception_mutex);*/ } uint64 ppc_get_clock_frequency(int cpu) { return PPC_CLOCK_FREQUENCY; } uint64 ppc_get_bus_frequency(int cpu) { return PPC_BUS_FREQUENCY; } uint64 ppc_get_timebase_frequency(int cpu) { return PPC_TIMEBASE_FREQUENCY; } void ppc_machine_check_exception() { PPC_CPU_ERR("machine check exception\n"); } uint32 ppc_cpu_get_gpr(int cpu, int i) { return gCPU.gpr[i]; } void ppc_cpu_set_gpr(int cpu, int i, uint32 newvalue) { gCPU.gpr[i] = newvalue; } void ppc_cpu_set_msr(int cpu, uint32 newvalue) { gCPU.msr = newvalue; } void ppc_cpu_set_pc(int cpu, uint32 newvalue) { gCPU.pc = newvalue; } uint32 ppc_cpu_get_pc(int cpu) { return gCPU.pc; } uint32 ppc_cpu_get_pvr(int cpu) { return gCPU.pvr; } void ppc_cpu_map_framebuffer(uint32 pa, uint32 ea) { // use BAT for framebuffer gCPU.dbatu[0] = ea|(7<<2)|0x3; gCPU.dbat_bl17[0] = ~(BATU_BL(gCPU.dbatu[0])<<17); gCPU.dbatl[0] = pa; } void ppc_set_singlestep_v(bool v, const char *file, int line, const char *format, ...) { va_list arg; va_start(arg, format); ht_fprintf(stdout, "singlestep %s from %s:%d, info: ", v ? "set" : "cleared", file, line); ht_vfprintf(stdout, format, arg); ht_fprintf(stdout, "\n"); va_end(arg); gSinglestep = v; } void ppc_set_singlestep_nonverbose(bool v) { gSinglestep = v; } #define CPU_KEY_PVR "cpu_pvr" //#include "configparser.h" #define MPC8560_DPRAM_SIZE 0xC000 #define MPC8560_IRAM_SIZE 0x8000 bool ppc_cpu_init() { memset(&gCPU, 0, sizeof gCPU); //gCPU.pvr = gConfig->getConfigInt(CPU_KEY_PVR); gCPU.cpm_reg.dpram = (void *)malloc(MPC8560_DPRAM_SIZE); if(!gCPU.cpm_reg.dpram){ printf("malloc failed for dpram\n"); skyeye_exit(-1); } else printf("malloc succ for dpram, dpram=0x%x\n", gCPU.cpm_reg.dpram); gCPU.cpm_reg.iram = (void *)malloc(MPC8560_IRAM_SIZE); if(!gCPU.cpm_reg.iram){ printf("malloc failed for iram\n"); skyeye_exit(-1); } else printf("malloc succ for dpram, dpram=0x%x\n", gCPU.cpm_reg.iram); ppc_dec_init(); // initialize srs (mostly for prom) int i; for (i=0; i<16; i++) { gCPU.sr[i] = 0x2aa*i; } /*sys_create_mutex(&exception_mutex);*/ PPC_CPU_WARN("You are using the generic CPU!\n"); PPC_CPU_WARN("This is much slower than the just-in-time compiler and\n"); PPC_CPU_WARN("should only be used for debugging purposes or if there's\n"); PPC_CPU_WARN("no just-in-time compiler for your platform.\n"); return true; } void ppc_cpu_init_config() { // gConfig->acceptConfigEntryIntDef("cpu_pvr", 0x000c0201); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_vec.c����������������������������������������������������������0000644�0001750�0000144�00000205112�10635115336�017014� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_vec.cc * * Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nsmu.edu) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Pages marked: v.??? * From: IBM PowerPC MicroProcessor Family: Altivec(tm) Technology... * Programming Environments Manual */ #include <math.h> /* * FIXME: put somewhere appropriate */ #ifndef HAS_LOG2 #define log2(x) log(x)/log(2) #endif /* HAS_LOG2 */ #ifndef HAS_EXP2 #define exp2(x) pow(2, x) #endif /* HAS_EXP2 */ //#include "debug/tracers.h" #include "ppc_cpu.h" #include "ppc_dec.h" #include "ppc_fpu.h" #include "ppc_vec.h" #define SIGN32 0x80000000 /* PACK_PIXEL Packs a uint32 pixel to uint16 pixel * v.219 */ static inline uint16 PACK_PIXEL(uint32 clr) { return (((clr & 0x000000f8) >> 3) | \ ((clr & 0x0000f800) >> 6) | \ ((clr & 0x01f80000) >> 9)); } /* UNPACK_PIXEL Unpacks a uint16 pixel to uint32 pixel * v.276 & v.279 */ static inline uint32 UNPACK_PIXEL(uint16 clr) { return (((uint32)(clr & 0x001f)) | \ ((uint32)(clr & 0x03E0) << 3) | \ ((uint32)(clr & 0x7c00) << 6) | \ (((clr) & 0x8000) ? 0xff000000 : 0)); } static inline uint8 SATURATE_UB(uint16 val) { if (val & 0xff00) { gCPU.vscr |= VSCR_SAT; return 0xff; } return val; } static inline uint8 SATURATE_0B(uint16 val) { if (val & 0xff00) { gCPU.vscr |= VSCR_SAT; return 0; } return val; } static inline uint16 SATURATE_UH(uint32 val) { if (val & 0xffff0000) { gCPU.vscr |= VSCR_SAT; return 0xffff; } return val; } static inline uint16 SATURATE_0H(uint32 val) { if (val & 0xffff0000) { gCPU.vscr |= VSCR_SAT; return 0; } return val; } static inline sint8 SATURATE_SB(sint16 val) { if (val > 127) { // 0x7F gCPU.vscr |= VSCR_SAT; return 127; } else if (val < -128) { // 0x80 gCPU.vscr |= VSCR_SAT; return -128; } return val; } static inline uint8 SATURATE_USB(sint16 val) { if (val > 0xff) { gCPU.vscr |= VSCR_SAT; return 0xff; } else if (val < 0) { gCPU.vscr |= VSCR_SAT; return 0; } return (uint8)val; } static inline sint16 SATURATE_SH(sint32 val) { if (val > 32767) { // 0x7fff gCPU.vscr |= VSCR_SAT; return 32767; } else if (val < -32768) { // 0x8000 gCPU.vscr |= VSCR_SAT; return -32768; } return val; } static inline uint16 SATURATE_USH(sint32 val) { if (val > 0xffff) { gCPU.vscr |= VSCR_SAT; return 0xffff; } else if (val < 0) { gCPU.vscr |= VSCR_SAT; return 0; } return (uint16)val; } static inline sint32 SATURATE_UW(sint64 val) { if (val > 0xffffffffLL) { gCPU.vscr |= VSCR_SAT; return 0xffffffffLL; } return val; } static inline sint32 SATURATE_SW(sint64 val) { if (val > 2147483647LL) { // 0x7fffffff gCPU.vscr |= VSCR_SAT; return 2147483647LL; } else if (val < -2147483648LL) { // 0x80000000 gCPU.vscr |= VSCR_SAT; return -2147483648LL; } return val; } /* vperm Vector Permutation * v.218 */ void ppc_opc_vperm() { VECTOR_DEBUG_COMMON; int vrD, vrA, vrB, vrC; int sel; Vector_t r; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<16; i++) { sel = gCPU.vr[vrC].b[i]; if (sel & 0x10) r.b[i] = VECT_B(gCPU.vr[vrB], sel & 0xf); else r.b[i] = VECT_B(gCPU.vr[vrA], sel & 0xf); } gCPU.vr[vrD] = r; } /* vsel Vector Select * v.238 */ void ppc_opc_vsel() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; uint64 mask, val; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); mask = gCPU.vr[vrC].d[0]; val = gCPU.vr[vrB].d[0] & mask; val |= gCPU.vr[vrA].d[0] & ~mask; gCPU.vr[vrD].d[0] = val; mask = gCPU.vr[vrC].d[1]; val = gCPU.vr[vrB].d[1] & mask; val |= gCPU.vr[vrA].d[1] & ~mask; gCPU.vr[vrD].d[1] = val; } /* vsrb Vector Shift Right Byte * v.256 */ void ppc_opc_vsrb() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for ( i=0; i<16; i++) { gCPU.vr[vrD].b[i] = gCPU.vr[vrA].b[i] >> (gCPU.vr[vrB].b[i] & 0x7); } } /* vsrh Vector Shift Right Half Word * v.257 */ void ppc_opc_vsrh() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { gCPU.vr[vrD].h[i] = gCPU.vr[vrA].h[i] >> (gCPU.vr[vrB].h[i] & 0xf); } } /* vsrw Vector Shift Right Word * v.259 */ void ppc_opc_vsrw() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { gCPU.vr[vrD].w[i] = gCPU.vr[vrA].w[i] >> (gCPU.vr[vrB].w[i] & 0x1f); } } /* vsrab Vector Shift Right Arithmetic Byte * v.253 */ void ppc_opc_vsrab() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { gCPU.vr[vrD].sb[i] = gCPU.vr[vrA].sb[i] >> (gCPU.vr[vrB].b[i] & 0x7); } } /* vsrah Vector Shift Right Arithmetic Half Word * v.254 */ void ppc_opc_vsrah() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { gCPU.vr[vrD].sh[i] = gCPU.vr[vrA].sh[i] >> (gCPU.vr[vrB].h[i] & 0xf); } } /* vsraw Vector Shift Right Arithmetic Word * v.255 */ void ppc_opc_vsraw() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { gCPU.vr[vrD].sw[i] = gCPU.vr[vrA].sw[i] >> (gCPU.vr[vrB].w[i] & 0x1f); } } /* vslb Vector Shift Left Byte * v.240 */ void ppc_opc_vslb() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { gCPU.vr[vrD].b[i] = gCPU.vr[vrA].b[i] << (gCPU.vr[vrB].b[i] & 0x7); } } /* vslh Vector Shift Left Half Word * v.242 */ void ppc_opc_vslh() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { gCPU.vr[vrD].h[i] = gCPU.vr[vrA].h[i] << (gCPU.vr[vrB].h[i] & 0xf); } } /* vslw Vector Shift Left Word * v.244 */ void ppc_opc_vslw() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { gCPU.vr[vrD].w[i] = gCPU.vr[vrA].w[i] << (gCPU.vr[vrB].w[i] & 0x1f); } } /* vsr Vector Shift Right * v.251 */ void ppc_opc_vsr() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; int shift; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); /* Specs say that the low-order 3 bits of all byte elements in vB * must be the same, or the result is undefined. So we can just * use the same low-order 3 bits for all of our shifts. */ shift = gCPU.vr[vrB].w[0] & 0x7; r.d[0] = gCPU.vr[vrA].d[0] >> shift; r.d[1] = gCPU.vr[vrA].d[1] >> shift; VECT_D(r, 1) |= VECT_D(gCPU.vr[vrA], 0) << (64 - shift); gCPU.vr[vrD] = r; } /* vsro Vector Shift Right Octet * v.258 */ void ppc_opc_vsro() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; int shift, i; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); shift = (gCPU.vr[vrB].w[0] >> 3) & 0xf; #if HOST_ENDIANESS == HOST_ENDIANESS_LE for (i=0; i<(16-shift); i++) { r.b[i] = gCPU.vr[vrA].b[i+shift]; } for (; i<16; i++) { r.b[i] = 0; } #elif HOST_ENDIANESS == HOST_ENDIANESS_BE for (i=0; i<shift; i++) { r.b[i] = 0; } for (; i<16; i++) { r.b[i] = gCPU.vr[vrA].b[i-shift]; } #else #error Endianess not supported! #endif gCPU.vr[vrD] = r; } /* vsl Vector Shift Left * v.239 */ void ppc_opc_vsl() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; int shift; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); /* Specs say that the low-order 3 bits of all byte elements in vB * must be the same, or the result is undefined. So we can just * use the same low-order 3 bits for all of our shifts. */ shift = gCPU.vr[vrB].w[0] & 0x7; r.d[0] = gCPU.vr[vrA].d[0] << shift; r.d[1] = gCPU.vr[vrA].d[1] << shift; VECT_D(r, 0) |= VECT_D(gCPU.vr[vrA], 1) >> (64 - shift); gCPU.vr[vrD] = r; } /* vslo Vector Shift Left Octet * v.243 */ void ppc_opc_vslo() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; int shift, i; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); shift = (gCPU.vr[vrB].w[0] >> 3) & 0xf; #if HOST_ENDIANESS == HOST_ENDIANESS_LE for (i=0; i<shift; i++) { r.b[i] = 0; } for (; i<16; i++) { r.b[i] = gCPU.vr[vrA].b[i-shift]; } #elif HOST_ENDIANESS == HOST_ENDIANESS_BE for (i=0; i<(16-shift); i++) { r.b[i] = gCPU.vr[vrA].b[i+shift]; } for (; i<16; i++) { r.b[i] = 0; } #else #error Endianess not supported! #endif gCPU.vr[vrD] = r; } /* vsldoi Vector Shift Left Double by Octet Immediate * v.241 */ void ppc_opc_vsldoi() { VECTOR_DEBUG_COMMON; int vrD, vrA, vrB, shift, ashift; int i; Vector_t r; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, shift); shift &= 0xf; ashift = 16 - shift; #if HOST_ENDIANESS == HOST_ENDIANESS_LE for (i=0; i<shift; i++) { r.b[i] = gCPU.vr[vrB].b[i+ashift]; } for (; i<16; i++) { r.b[i] = gCPU.vr[vrA].b[i-shift]; } #elif HOST_ENDIANESS == HOST_ENDIANESS_BE for (i=0; i<ashift; i++) { r.b[i] = gCPU.vr[vrA].b[i+shift]; } for (; i<16; i++) { r.b[i] = gCPU.vr[vrB].b[i-ashift]; } #else #error Endianess not supported! #endif gCPU.vr[vrD] = r; } /* vrlb Vector Rotate Left Byte * v.234 */ void ppc_opc_vrlb() { VECTOR_DEBUG; int vrD, vrA, vrB, shift; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { shift = (gCPU.vr[vrB].b[i] & 0x7); r.b[i] = gCPU.vr[vrA].b[i] << shift; r.b[i] |= gCPU.vr[vrA].b[i] >> (8 - shift); } gCPU.vr[vrD] = r; } /* vrlh Vector Rotate Left Half Word * v.235 */ void ppc_opc_vrlh() { VECTOR_DEBUG; int vrD, vrA, vrB, shift; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { shift = (gCPU.vr[vrB].h[i] & 0xf); r.h[i] = gCPU.vr[vrA].h[i] << shift; r.h[i] |= gCPU.vr[vrA].h[i] >> (16 - shift); } gCPU.vr[vrD] = r; } /* vrlw Vector Rotate Left Word * v.236 */ void ppc_opc_vrlw() { VECTOR_DEBUG; int vrD, vrA, vrB, shift; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { shift = (gCPU.vr[vrB].w[i] & 0x1F); r.w[i] = gCPU.vr[vrA].w[i] << shift; r.w[i] |= gCPU.vr[vrA].w[i] >> (32 - shift); } gCPU.vr[vrD] = r; } /* With the merges, I just don't see any point in risking that a compiler * might generate actual alu code to calculate anything when it's * compile-time known. Plus, it's easier to validate it like this. */ /* vmrghb Vector Merge High Byte * v.195 */ void ppc_opc_vmrghb() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_B(r, 0) = VECT_B(gCPU.vr[vrA], 0); VECT_B(r, 1) = VECT_B(gCPU.vr[vrB], 0); VECT_B(r, 2) = VECT_B(gCPU.vr[vrA], 1); VECT_B(r, 3) = VECT_B(gCPU.vr[vrB], 1); VECT_B(r, 4) = VECT_B(gCPU.vr[vrA], 2); VECT_B(r, 5) = VECT_B(gCPU.vr[vrB], 2); VECT_B(r, 6) = VECT_B(gCPU.vr[vrA], 3); VECT_B(r, 7) = VECT_B(gCPU.vr[vrB], 3); VECT_B(r, 8) = VECT_B(gCPU.vr[vrA], 4); VECT_B(r, 9) = VECT_B(gCPU.vr[vrB], 4); VECT_B(r,10) = VECT_B(gCPU.vr[vrA], 5); VECT_B(r,11) = VECT_B(gCPU.vr[vrB], 5); VECT_B(r,12) = VECT_B(gCPU.vr[vrA], 6); VECT_B(r,13) = VECT_B(gCPU.vr[vrB], 6); VECT_B(r,14) = VECT_B(gCPU.vr[vrA], 7); VECT_B(r,15) = VECT_B(gCPU.vr[vrB], 7); gCPU.vr[vrD] = r; } /* vmrghh Vector Merge High Half Word * v.196 */ void ppc_opc_vmrghh() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_H(r, 0) = VECT_H(gCPU.vr[vrA], 0); VECT_H(r, 1) = VECT_H(gCPU.vr[vrB], 0); VECT_H(r, 2) = VECT_H(gCPU.vr[vrA], 1); VECT_H(r, 3) = VECT_H(gCPU.vr[vrB], 1); VECT_H(r, 4) = VECT_H(gCPU.vr[vrA], 2); VECT_H(r, 5) = VECT_H(gCPU.vr[vrB], 2); VECT_H(r, 6) = VECT_H(gCPU.vr[vrA], 3); VECT_H(r, 7) = VECT_H(gCPU.vr[vrB], 3); gCPU.vr[vrD] = r; } /* vmrghw Vector Merge High Word * v.197 */ void ppc_opc_vmrghw() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_W(r, 0) = VECT_W(gCPU.vr[vrA], 0); VECT_W(r, 1) = VECT_W(gCPU.vr[vrB], 0); VECT_W(r, 2) = VECT_W(gCPU.vr[vrA], 1); VECT_W(r, 3) = VECT_W(gCPU.vr[vrB], 1); gCPU.vr[vrD] = r; } /* vmrglb Vector Merge Low Byte * v.198 */ void ppc_opc_vmrglb() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_B(r, 0) = VECT_B(gCPU.vr[vrA], 8); VECT_B(r, 1) = VECT_B(gCPU.vr[vrB], 8); VECT_B(r, 2) = VECT_B(gCPU.vr[vrA], 9); VECT_B(r, 3) = VECT_B(gCPU.vr[vrB], 9); VECT_B(r, 4) = VECT_B(gCPU.vr[vrA],10); VECT_B(r, 5) = VECT_B(gCPU.vr[vrB],10); VECT_B(r, 6) = VECT_B(gCPU.vr[vrA],11); VECT_B(r, 7) = VECT_B(gCPU.vr[vrB],11); VECT_B(r, 8) = VECT_B(gCPU.vr[vrA],12); VECT_B(r, 9) = VECT_B(gCPU.vr[vrB],12); VECT_B(r,10) = VECT_B(gCPU.vr[vrA],13); VECT_B(r,11) = VECT_B(gCPU.vr[vrB],13); VECT_B(r,12) = VECT_B(gCPU.vr[vrA],14); VECT_B(r,13) = VECT_B(gCPU.vr[vrB],14); VECT_B(r,14) = VECT_B(gCPU.vr[vrA],15); VECT_B(r,15) = VECT_B(gCPU.vr[vrB],15); gCPU.vr[vrD] = r; } /* vmrglh Vector Merge Low Half Word * v.199 */ void ppc_opc_vmrglh() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_H(r, 0) = VECT_H(gCPU.vr[vrA], 4); VECT_H(r, 1) = VECT_H(gCPU.vr[vrB], 4); VECT_H(r, 2) = VECT_H(gCPU.vr[vrA], 5); VECT_H(r, 3) = VECT_H(gCPU.vr[vrB], 5); VECT_H(r, 4) = VECT_H(gCPU.vr[vrA], 6); VECT_H(r, 5) = VECT_H(gCPU.vr[vrB], 6); VECT_H(r, 6) = VECT_H(gCPU.vr[vrA], 7); VECT_H(r, 7) = VECT_H(gCPU.vr[vrB], 7); gCPU.vr[vrD] = r; } /* vmrglw Vector Merge Low Word * v.200 */ void ppc_opc_vmrglw() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_W(r, 0) = VECT_W(gCPU.vr[vrA], 2); VECT_W(r, 1) = VECT_W(gCPU.vr[vrB], 2); VECT_W(r, 2) = VECT_W(gCPU.vr[vrA], 3); VECT_W(r, 3) = VECT_W(gCPU.vr[vrB], 3); gCPU.vr[vrD] = r; } /* vspltb Vector Splat Byte * v.245 */ void ppc_opc_vspltb() { VECTOR_DEBUG; int vrD, vrB; uint32 uimm; uint64 val; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, uimm, vrB); /* The documentation doesn't stipulate what a value higher than 0xf * will do. Thus, this is by default an undefined value. We * are thus doing this the fastest way that won't crash us. */ val = VECT_B(gCPU.vr[vrB], uimm & 0xf); val |= (val << 8); val |= (val << 16); val |= (val << 32); gCPU.vr[vrD].d[0] = val; gCPU.vr[vrD].d[1] = val; } /* vsplth Vector Splat Half Word * v.246 */ void ppc_opc_vsplth() { VECTOR_DEBUG; int vrD, vrB; uint32 uimm; uint64 val; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, uimm, vrB); /* The documentation doesn't stipulate what a value higher than 0x7 * will do. Thus, this is by default an undefined value. We * are thus doing this the fastest way that won't crash us. */ val = VECT_H(gCPU.vr[vrB], uimm & 0x7); val |= (val << 16); val |= (val << 32); gCPU.vr[vrD].d[0] = val; gCPU.vr[vrD].d[1] = val; } /* vspltw Vector Splat Word * v.250 */ void ppc_opc_vspltw() { VECTOR_DEBUG; int vrD, vrB; uint32 uimm; uint64 val; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, uimm, vrB); /* The documentation doesn't stipulate what a value higher than 0x3 * will do. Thus, this is by default an undefined value. We * are thus doing this the fastest way that won't crash us. */ val = VECT_W(gCPU.vr[vrB], uimm & 0x3); val |= (val << 32); gCPU.vr[vrD].d[0] = val; gCPU.vr[vrD].d[1] = val; } /* vspltisb Vector Splat Immediate Signed Byte * v.247 */ void ppc_opc_vspltisb() { VECTOR_DEBUG_COMMON; int vrD, vrB; uint32 simm; uint64 val; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, simm, vrB); PPC_OPC_ASSERT(vrB==0); val = (simm & 0x10) ? (simm | 0xE0) : simm; val |= (val << 8); val |= (val << 16); val |= (val << 32); gCPU.vr[vrD].d[0] = val; gCPU.vr[vrD].d[1] = val; } /* vspltish Vector Splat Immediate Signed Half Word * v.248 */ void ppc_opc_vspltish() { VECTOR_DEBUG_COMMON; int vrD, vrB; uint32 simm; uint64 val; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, simm, vrB); PPC_OPC_ASSERT(vrB==0); val = (simm & 0x10) ? (simm | 0xFFE0) : simm; val |= (val << 16); val |= (val << 32); gCPU.vr[vrD].d[0] = val; gCPU.vr[vrD].d[1] = val; } /* vspltisw Vector Splat Immediate Signed Word * v.249 */ void ppc_opc_vspltisw() { VECTOR_DEBUG_COMMON; int vrD, vrB; uint32 simm; uint64 val; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, simm, vrB); PPC_OPC_ASSERT(vrB==0); val = (simm & 0x10) ? (simm | 0xFFFFFFE0) : simm; val |= (val << 32); gCPU.vr[vrD].d[0] = val; gCPU.vr[vrD].d[1] = val; } /* mfvscr Move from Vector Status and Control Register * v.129 */ void ppc_opc_mfvscr() { VECTOR_DEBUG_COMMON; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); PPC_OPC_ASSERT(vrB==0); VECT_W(gCPU.vr[vrD], 3) = gCPU.vscr; VECT_W(gCPU.vr[vrD], 2) = 0; VECT_D(gCPU.vr[vrD], 0) = 0; } /* mtvscr Move to Vector Status and Control Register * v.130 */ void ppc_opc_mtvscr() { VECTOR_DEBUG_COMMON; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); PPC_OPC_ASSERT(vrD==0); gCPU.vscr = VECT_W(gCPU.vr[vrB], 3); } /* vpkuhum Vector Pack Unsigned Half Word Unsigned Modulo * v.224 */ void ppc_opc_vpkuhum() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_B(r, 0) = VECT_B(gCPU.vr[vrA], 1); VECT_B(r, 1) = VECT_B(gCPU.vr[vrA], 3); VECT_B(r, 2) = VECT_B(gCPU.vr[vrA], 5); VECT_B(r, 3) = VECT_B(gCPU.vr[vrA], 7); VECT_B(r, 4) = VECT_B(gCPU.vr[vrA], 9); VECT_B(r, 5) = VECT_B(gCPU.vr[vrA],11); VECT_B(r, 6) = VECT_B(gCPU.vr[vrA],13); VECT_B(r, 7) = VECT_B(gCPU.vr[vrA],15); VECT_B(r, 8) = VECT_B(gCPU.vr[vrB], 1); VECT_B(r, 9) = VECT_B(gCPU.vr[vrB], 3); VECT_B(r,10) = VECT_B(gCPU.vr[vrB], 5); VECT_B(r,11) = VECT_B(gCPU.vr[vrB], 7); VECT_B(r,12) = VECT_B(gCPU.vr[vrB], 9); VECT_B(r,13) = VECT_B(gCPU.vr[vrB],11); VECT_B(r,14) = VECT_B(gCPU.vr[vrB],13); VECT_B(r,15) = VECT_B(gCPU.vr[vrB],15); gCPU.vr[vrD] = r; } /* vpkuwum Vector Pack Unsigned Word Unsigned Modulo * v.226 */ void ppc_opc_vpkuwum() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_H(r, 0) = VECT_H(gCPU.vr[vrA], 1); VECT_H(r, 1) = VECT_H(gCPU.vr[vrA], 3); VECT_H(r, 2) = VECT_H(gCPU.vr[vrA], 5); VECT_H(r, 3) = VECT_H(gCPU.vr[vrA], 7); VECT_H(r, 4) = VECT_H(gCPU.vr[vrB], 1); VECT_H(r, 5) = VECT_H(gCPU.vr[vrB], 3); VECT_H(r, 6) = VECT_H(gCPU.vr[vrB], 5); VECT_H(r, 7) = VECT_H(gCPU.vr[vrB], 7); gCPU.vr[vrD] = r; } /* vpkpx Vector Pack Pixel32 * v.219 */ void ppc_opc_vpkpx() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_H(r, 0) = PACK_PIXEL(VECT_W(gCPU.vr[vrA], 0)); VECT_H(r, 1) = PACK_PIXEL(VECT_W(gCPU.vr[vrA], 1)); VECT_H(r, 2) = PACK_PIXEL(VECT_W(gCPU.vr[vrA], 2)); VECT_H(r, 3) = PACK_PIXEL(VECT_W(gCPU.vr[vrA], 3)); VECT_H(r, 4) = PACK_PIXEL(VECT_W(gCPU.vr[vrB], 0)); VECT_H(r, 5) = PACK_PIXEL(VECT_W(gCPU.vr[vrB], 1)); VECT_H(r, 6) = PACK_PIXEL(VECT_W(gCPU.vr[vrB], 2)); VECT_H(r, 7) = PACK_PIXEL(VECT_W(gCPU.vr[vrB], 3)); gCPU.vr[vrD] = r; } /* vpkuhus Vector Pack Unsigned Half Word Unsigned Saturate * v.225 */ void ppc_opc_vpkuhus() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_B(r, 0) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 0)); VECT_B(r, 1) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 1)); VECT_B(r, 2) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 2)); VECT_B(r, 3) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 3)); VECT_B(r, 4) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 4)); VECT_B(r, 5) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 5)); VECT_B(r, 6) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 6)); VECT_B(r, 7) = SATURATE_UB(VECT_H(gCPU.vr[vrA], 7)); VECT_B(r, 8) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 0)); VECT_B(r, 9) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 1)); VECT_B(r,10) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 2)); VECT_B(r,11) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 3)); VECT_B(r,12) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 4)); VECT_B(r,13) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 5)); VECT_B(r,14) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 6)); VECT_B(r,15) = SATURATE_UB(VECT_H(gCPU.vr[vrB], 7)); gCPU.vr[vrD] = r; } /* vpkshss Vector Pack Signed Half Word Signed Saturate * v.220 */ void ppc_opc_vpkshss() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_B(r, 0) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 0)); VECT_B(r, 1) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 1)); VECT_B(r, 2) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 2)); VECT_B(r, 3) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 3)); VECT_B(r, 4) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 4)); VECT_B(r, 5) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 5)); VECT_B(r, 6) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 6)); VECT_B(r, 7) = SATURATE_SB(VECT_H(gCPU.vr[vrA], 7)); VECT_B(r, 8) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 0)); VECT_B(r, 9) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 1)); VECT_B(r,10) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 2)); VECT_B(r,11) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 3)); VECT_B(r,12) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 4)); VECT_B(r,13) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 5)); VECT_B(r,14) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 6)); VECT_B(r,15) = SATURATE_SB(VECT_H(gCPU.vr[vrB], 7)); gCPU.vr[vrD] = r; } /* vpkuwus Vector Pack Unsigned Word Unsigned Saturate * v.227 */ void ppc_opc_vpkuwus() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_H(r, 0) = SATURATE_UH(VECT_W(gCPU.vr[vrA], 0)); VECT_H(r, 1) = SATURATE_UH(VECT_W(gCPU.vr[vrA], 1)); VECT_H(r, 2) = SATURATE_UH(VECT_W(gCPU.vr[vrA], 2)); VECT_H(r, 3) = SATURATE_UH(VECT_W(gCPU.vr[vrA], 3)); VECT_H(r, 4) = SATURATE_UH(VECT_W(gCPU.vr[vrB], 0)); VECT_H(r, 5) = SATURATE_UH(VECT_W(gCPU.vr[vrB], 1)); VECT_H(r, 6) = SATURATE_UH(VECT_W(gCPU.vr[vrB], 2)); VECT_H(r, 7) = SATURATE_UH(VECT_W(gCPU.vr[vrB], 3)); gCPU.vr[vrD] = r; } /* vpkswss Vector Pack Signed Word Signed Saturate * v.222 */ void ppc_opc_vpkswss() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_H(r, 0) = SATURATE_SH(VECT_W(gCPU.vr[vrA], 0)); VECT_H(r, 1) = SATURATE_SH(VECT_W(gCPU.vr[vrA], 1)); VECT_H(r, 2) = SATURATE_SH(VECT_W(gCPU.vr[vrA], 2)); VECT_H(r, 3) = SATURATE_SH(VECT_W(gCPU.vr[vrA], 3)); VECT_H(r, 4) = SATURATE_SH(VECT_W(gCPU.vr[vrB], 0)); VECT_H(r, 5) = SATURATE_SH(VECT_W(gCPU.vr[vrB], 1)); VECT_H(r, 6) = SATURATE_SH(VECT_W(gCPU.vr[vrB], 2)); VECT_H(r, 7) = SATURATE_SH(VECT_W(gCPU.vr[vrB], 3)); gCPU.vr[vrD] = r; } /* vpkshus Vector Pack Signed Half Word Unsigned Saturate * v.221 */ void ppc_opc_vpkshus() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_B(r, 0) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 0)); VECT_B(r, 1) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 1)); VECT_B(r, 2) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 2)); VECT_B(r, 3) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 3)); VECT_B(r, 4) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 4)); VECT_B(r, 5) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 5)); VECT_B(r, 6) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 6)); VECT_B(r, 7) = SATURATE_USB(VECT_H(gCPU.vr[vrA], 7)); VECT_B(r, 8) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 0)); VECT_B(r, 9) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 1)); VECT_B(r,10) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 2)); VECT_B(r,11) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 3)); VECT_B(r,12) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 4)); VECT_B(r,13) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 5)); VECT_B(r,14) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 6)); VECT_B(r,15) = SATURATE_USB(VECT_H(gCPU.vr[vrB], 7)); gCPU.vr[vrD] = r; } /* vpkswus Vector Pack Signed Word Unsigned Saturate * v.223 */ void ppc_opc_vpkswus() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); VECT_H(r, 0) = SATURATE_USH(VECT_W(gCPU.vr[vrA], 0)); VECT_H(r, 1) = SATURATE_USH(VECT_W(gCPU.vr[vrA], 1)); VECT_H(r, 2) = SATURATE_USH(VECT_W(gCPU.vr[vrA], 2)); VECT_H(r, 3) = SATURATE_USH(VECT_W(gCPU.vr[vrA], 3)); VECT_H(r, 4) = SATURATE_USH(VECT_W(gCPU.vr[vrB], 0)); VECT_H(r, 5) = SATURATE_USH(VECT_W(gCPU.vr[vrB], 1)); VECT_H(r, 6) = SATURATE_USH(VECT_W(gCPU.vr[vrB], 2)); VECT_H(r, 7) = SATURATE_USH(VECT_W(gCPU.vr[vrB], 3)); gCPU.vr[vrD] = r; } /* vupkhsb Vector Unpack High Signed Byte * v.277 */ void ppc_opc_vupkhsb() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); VECT_SH(r, 0) = VECT_SB(gCPU.vr[vrB], 0); VECT_SH(r, 1) = VECT_SB(gCPU.vr[vrB], 1); VECT_SH(r, 2) = VECT_SB(gCPU.vr[vrB], 2); VECT_SH(r, 3) = VECT_SB(gCPU.vr[vrB], 3); VECT_SH(r, 4) = VECT_SB(gCPU.vr[vrB], 4); VECT_SH(r, 5) = VECT_SB(gCPU.vr[vrB], 5); VECT_SH(r, 6) = VECT_SB(gCPU.vr[vrB], 6); VECT_SH(r, 7) = VECT_SB(gCPU.vr[vrB], 7); gCPU.vr[vrD] = r; } /* vupkhpx Vector Unpack High Pixel32 * v.279 */ void ppc_opc_vupkhpx() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); VECT_W(r, 0) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 0)); VECT_W(r, 1) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 1)); VECT_W(r, 2) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 2)); VECT_W(r, 3) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 3)); gCPU.vr[vrD] = r; } /* vupkhsh Vector Unpack High Signed Half Word * v.278 */ void ppc_opc_vupkhsh() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); VECT_SW(r, 0) = VECT_SH(gCPU.vr[vrB], 0); VECT_SW(r, 1) = VECT_SH(gCPU.vr[vrB], 1); VECT_SW(r, 2) = VECT_SH(gCPU.vr[vrB], 2); VECT_SW(r, 3) = VECT_SH(gCPU.vr[vrB], 3); gCPU.vr[vrD] = r; } /* vupklsb Vector Unpack Low Signed Byte * v.280 */ void ppc_opc_vupklsb() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); VECT_SH(r, 0) = VECT_SB(gCPU.vr[vrB], 8); VECT_SH(r, 1) = VECT_SB(gCPU.vr[vrB], 9); VECT_SH(r, 2) = VECT_SB(gCPU.vr[vrB],10); VECT_SH(r, 3) = VECT_SB(gCPU.vr[vrB],11); VECT_SH(r, 4) = VECT_SB(gCPU.vr[vrB],12); VECT_SH(r, 5) = VECT_SB(gCPU.vr[vrB],13); VECT_SH(r, 6) = VECT_SB(gCPU.vr[vrB],14); VECT_SH(r, 7) = VECT_SB(gCPU.vr[vrB],15); gCPU.vr[vrD] = r; } /* vupklpx Vector Unpack Low Pixel32 * v.279 */ void ppc_opc_vupklpx() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); VECT_W(r, 0) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 4)); VECT_W(r, 1) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 5)); VECT_W(r, 2) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 6)); VECT_W(r, 3) = UNPACK_PIXEL(VECT_H(gCPU.vr[vrB], 7)); gCPU.vr[vrD] = r; } /* vupklsh Vector Unpack Low Signed Half Word * v.281 */ void ppc_opc_vupklsh() { VECTOR_DEBUG; int vrD, vrA, vrB; Vector_t r; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); VECT_SW(r, 0) = VECT_SH(gCPU.vr[vrB], 4); VECT_SW(r, 1) = VECT_SH(gCPU.vr[vrB], 5); VECT_SW(r, 2) = VECT_SH(gCPU.vr[vrB], 6); VECT_SW(r, 3) = VECT_SH(gCPU.vr[vrB], 7); gCPU.vr[vrD] = r; } /* vaddubm Vector Add Unsigned Byte Modulo * v.141 */ void ppc_opc_vaddubm() { VECTOR_DEBUG; int vrD, vrA, vrB; uint8 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = gCPU.vr[vrA].b[i] + gCPU.vr[vrB].b[i]; gCPU.vr[vrD].b[i] = res; } } /* vadduhm Vector Add Unsigned Half Word Modulo * v.143 */ void ppc_opc_vadduhm() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = gCPU.vr[vrA].h[i] + gCPU.vr[vrB].h[i]; gCPU.vr[vrD].h[i] = res; } } /* vadduwm Vector Add Unsigned Word Modulo * v.145 */ void ppc_opc_vadduwm() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i]; gCPU.vr[vrD].w[i] = res; } } /* vaddfp Vector Add Float Point * v.137 */ void ppc_opc_vaddfp() { VECTOR_DEBUG; int vrD, vrA, vrB; float res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP res = gCPU.vr[vrA].f[i] + gCPU.vr[vrB].f[i]; gCPU.vr[vrD].f[i] = res; } } /* vaddcuw Vector Add Carryout Unsigned Word * v.136 */ void ppc_opc_vaddcuw() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i]; gCPU.vr[vrD].w[i] = (res < gCPU.vr[vrA].w[i]) ? 1 : 0; } } /* vaddubs Vector Add Unsigned Byte Saturate * v.142 */ void ppc_opc_vaddubs() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = (uint16)gCPU.vr[vrA].b[i] + (uint16)gCPU.vr[vrB].b[i]; gCPU.vr[vrD].b[i] = SATURATE_UB(res); } } /* vaddsbs Vector Add Signed Byte Saturate * v.138 */ void ppc_opc_vaddsbs() { VECTOR_DEBUG; int vrD, vrA, vrB; sint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = (sint16)gCPU.vr[vrA].sb[i] + (sint16)gCPU.vr[vrB].sb[i]; gCPU.vr[vrD].b[i] = SATURATE_SB(res); } } /* vadduhs Vector Add Unsigned Half Word Saturate * v.144 */ void ppc_opc_vadduhs() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (uint32)gCPU.vr[vrA].h[i] + (uint32)gCPU.vr[vrB].h[i]; gCPU.vr[vrD].h[i] = SATURATE_UH(res); } } /* vaddshs Vector Add Signed Half Word Saturate * v.139 */ void ppc_opc_vaddshs() { VECTOR_DEBUG; int vrD, vrA, vrB; sint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (sint32)gCPU.vr[vrA].sh[i] + (sint32)gCPU.vr[vrB].sh[i]; gCPU.vr[vrD].h[i] = SATURATE_SH(res); } } /* vadduws Vector Add Unsigned Word Saturate * v.146 */ void ppc_opc_vadduws() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i]; // We do this to prevent us from having to do 64-bit math if (res < gCPU.vr[vrA].w[i]) { res = 0xFFFFFFFF; gCPU.vscr |= VSCR_SAT; } /* 64-bit math | 32-bit hack * ------------------------+------------------------------------- * add, addc (a+b) | add (a+b) * sub, subb (r>ub) | sub (r<a) */ gCPU.vr[vrD].w[i] = res; } } /* vaddsws Vector Add Signed Word Saturate * v.140 */ void ppc_opc_vaddsws() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i]; // We do this to prevent us from having to do 64-bit math if (((gCPU.vr[vrA].w[i] ^ gCPU.vr[vrB].w[i]) & SIGN32) == 0) { // the signs of both operands are the same if (((res ^ gCPU.vr[vrA].w[i]) & SIGN32) != 0) { // sign of result != sign of operands // if res is negative, should have been positive res = (res & SIGN32) ? (SIGN32 - 1) : SIGN32; gCPU.vscr |= VSCR_SAT; } } /* 64-bit math | 32-bit hack * ------------------------+------------------------------------- * add, addc (a+b) | add (a+b) * sub, subb (r>ub) | xor, and (sign == sign) * sub, subb (r<lb) | xor, and (sign != sign) * | and (which) */ gCPU.vr[vrD].w[i] = res; } } /* vsububm Vector Subtract Unsigned Byte Modulo * v.265 */ void ppc_opc_vsububm() { VECTOR_DEBUG; int vrD, vrA, vrB; uint8 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = gCPU.vr[vrA].b[i] - gCPU.vr[vrB].b[i]; gCPU.vr[vrD].b[i] = res; } } /* vsubuhm Vector Subtract Unsigned Half Word Modulo * v.267 */ void ppc_opc_vsubuhm() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = gCPU.vr[vrA].h[i] - gCPU.vr[vrB].h[i]; gCPU.vr[vrD].h[i] = res; } } /* vsubuwm Vector Subtract Unsigned Word Modulo * v.269 */ void ppc_opc_vsubuwm() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i] - gCPU.vr[vrB].w[i]; gCPU.vr[vrD].w[i] = res; } } /* vsubfp Vector Subtract Float Point * v.261 */ void ppc_opc_vsubfp() { VECTOR_DEBUG; int vrD, vrA, vrB; float res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP res = gCPU.vr[vrA].f[i] - gCPU.vr[vrB].f[i]; gCPU.vr[vrD].f[i] = res; } } /* vsubcuw Vector Subtract Carryout Unsigned Word * v.260 */ void ppc_opc_vsubcuw() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i] - gCPU.vr[vrB].w[i]; gCPU.vr[vrD].w[i] = (res <= gCPU.vr[vrA].w[i]) ? 1 : 0; } } /* vsububs Vector Subtract Unsigned Byte Saturate * v.266 */ void ppc_opc_vsububs() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = (uint16)gCPU.vr[vrA].b[i] - (uint16)gCPU.vr[vrB].b[i]; gCPU.vr[vrD].b[i] = SATURATE_0B(res); } } /* vsubsbs Vector Subtract Signed Byte Saturate * v.262 */ void ppc_opc_vsubsbs() { VECTOR_DEBUG; int vrD, vrA, vrB; sint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = (sint16)gCPU.vr[vrA].sb[i] - (sint16)gCPU.vr[vrB].sb[i]; gCPU.vr[vrD].sb[i] = SATURATE_SB(res); } } /* vsubuhs Vector Subtract Unsigned Half Word Saturate * v.268 */ void ppc_opc_vsubuhs() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (uint32)gCPU.vr[vrA].h[i] - (uint32)gCPU.vr[vrB].h[i]; gCPU.vr[vrD].h[i] = SATURATE_0H(res); } } /* vsubshs Vector Subtract Signed Half Word Saturate * v.263 */ void ppc_opc_vsubshs() { VECTOR_DEBUG; int vrD, vrA, vrB; sint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (sint32)gCPU.vr[vrA].sh[i] - (sint32)gCPU.vr[vrB].sh[i]; gCPU.vr[vrD].sh[i] = SATURATE_SH(res); } } /* vsubuws Vector Subtract Unsigned Word Saturate * v.270 */ void ppc_opc_vsubuws() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i] - gCPU.vr[vrB].w[i]; // We do this to prevent us from having to do 64-bit math if (res > gCPU.vr[vrA].w[i]) { res = 0; gCPU.vscr |= VSCR_SAT; } /* 64-bit math | 32-bit hack * ------------------------+------------------------------------- * sub, subb (a+b) | sub (a+b) * sub, subb (r>ub) | sub (r<a) */ gCPU.vr[vrD].w[i] = res; } } /* vsubsws Vector Subtract Signed Word Saturate * v.264 */ void ppc_opc_vsubsws() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res, tmp; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { tmp = -gCPU.vr[vrB].w[i]; res = gCPU.vr[vrA].w[i] + tmp; // We do this to prevent us from having to do 64-bit math if (((gCPU.vr[vrA].w[i] ^ tmp) & SIGN32) == 0) { // the signs of both operands are the same if (((res ^ tmp) & SIGN32) != 0) { // sign of result != sign of operands // if res is negative, should have been positive res = (res & SIGN32) ? (SIGN32 - 1) : SIGN32; gCPU.vscr |= VSCR_SAT; } } /* 64-bit math | 32-bit hack * ------------------------+------------------------------------- * sub, subc (a+b) | neg, add (a-b) * sub, subb (r>ub) | xor, and (sign == sign) * sub, subb (r<lb) | xor, and (sign != sign) * | and (which) */ gCPU.vr[vrD].w[i] = res; } } /* vmuleub Vector Multiply Even Unsigned Byte * v.209 */ void ppc_opc_vmuleub() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (uint16)gCPU.vr[vrA].b[VECT_EVEN(i)] * (uint16)gCPU.vr[vrB].b[VECT_EVEN(i)]; gCPU.vr[vrD].h[i] = res; } } /* vmulesb Vector Multiply Even Signed Byte * v.207 */ void ppc_opc_vmulesb() { VECTOR_DEBUG; int vrD, vrA, vrB; sint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for ( i=0; i<8; i++) { res = (sint16)gCPU.vr[vrA].sb[VECT_EVEN(i)] * (sint16)gCPU.vr[vrB].sb[VECT_EVEN(i)]; gCPU.vr[vrD].sh[i] = res; } } /* vmuleuh Vector Multiply Even Unsigned Half Word * v.210 */ void ppc_opc_vmuleuh() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (uint32)gCPU.vr[vrA].h[VECT_EVEN(i)] * (uint32)gCPU.vr[vrB].h[VECT_EVEN(i)]; gCPU.vr[vrD].w[i] = res; } } /* vmulesh Vector Multiply Even Signed Half Word * v.208 */ void ppc_opc_vmulesh() { VECTOR_DEBUG; int vrD, vrA, vrB; sint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (sint32)gCPU.vr[vrA].sh[VECT_EVEN(i)] * (sint32)gCPU.vr[vrB].sh[VECT_EVEN(i)]; gCPU.vr[vrD].sw[i] = res; } } /* vmuloub Vector Multiply Odd Unsigned Byte * v.213 */ void ppc_opc_vmuloub() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (uint16)gCPU.vr[vrA].b[VECT_ODD(i)] * (uint16)gCPU.vr[vrB].b[VECT_ODD(i)]; gCPU.vr[vrD].h[i] = res; } } /* vmulosb Vector Multiply Odd Signed Byte * v.211 */ void ppc_opc_vmulosb() { VECTOR_DEBUG; int vrD, vrA, vrB; sint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (sint16)gCPU.vr[vrA].sb[VECT_ODD(i)] * (sint16)gCPU.vr[vrB].sb[VECT_ODD(i)]; gCPU.vr[vrD].sh[i] = res; } } /* vmulouh Vector Multiply Odd Unsigned Half Word * v.214 */ void ppc_opc_vmulouh() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (uint32)gCPU.vr[vrA].h[VECT_ODD(i)] * (uint32)gCPU.vr[vrB].h[VECT_ODD(i)]; gCPU.vr[vrD].w[i] = res; } } /* vmulosh Vector Multiply Odd Signed Half Word * v.212 */ void ppc_opc_vmulosh() { VECTOR_DEBUG; int vrD, vrA, vrB; sint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (sint32)gCPU.vr[vrA].sh[VECT_ODD(i)] * (sint32)gCPU.vr[vrB].sh[VECT_ODD(i)]; gCPU.vr[vrD].sw[i] = res; } } /* vmaddfp Vector Multiply Add Floating Point * v.177 */ void ppc_opc_vmaddfp() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; double res; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP res = (double)gCPU.vr[vrA].f[i] * (double)gCPU.vr[vrC].f[i]; res = (double)gCPU.vr[vrB].f[i] + res; gCPU.vr[vrD].f[i] = (float)res; } } /* vmhaddshs Vector Multiply High and Add Signed Half Word Saturate * v.185 */ void ppc_opc_vmhaddshs() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; sint32 prod; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<8; i++) { prod = (sint32)gCPU.vr[vrA].sh[i] * (sint32)gCPU.vr[vrB].sh[i]; prod = (prod >> 15) + (sint32)gCPU.vr[vrC].sh[i]; gCPU.vr[vrD].sh[i] = SATURATE_SH(prod); } } /* vmladduhm Vector Multiply Low and Add Unsigned Half Word Modulo * v.194 */ void ppc_opc_vmladduhm() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; uint32 prod; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for ( i=0; i<8; i++) { prod = (uint32)gCPU.vr[vrA].h[i] * (uint32)gCPU.vr[vrB].h[i]; prod = prod + (uint32)gCPU.vr[vrC].h[i]; gCPU.vr[vrD].h[i] = prod; } } /* vmhraddshs Vector Multiply High Round and Add Signed Half Word Saturate * v.186 */ void ppc_opc_vmhraddshs() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; sint32 prod; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<8; i++) { prod = (sint32)gCPU.vr[vrA].sh[i] * (sint32)gCPU.vr[vrB].sh[i]; prod += 0x4000; prod = (prod >> 15) + (sint32)gCPU.vr[vrC].sh[i]; gCPU.vr[vrD].sh[i] = SATURATE_SH(prod); } } /* vmsumubm Vector Multiply Sum Unsigned Byte Modulo * v.204 */ void ppc_opc_vmsumubm() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; uint32 temp; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<4; i++) { temp = gCPU.vr[vrC].w[i]; temp += (uint16)gCPU.vr[vrA].b[i<<2] * (uint16)gCPU.vr[vrB].b[i<<2]; temp += (uint16)gCPU.vr[vrA].b[(i<<2)+1] * (uint16)gCPU.vr[vrB].b[(i<<2)+1]; temp += (uint16)gCPU.vr[vrA].b[(i<<2)+2] * (uint16)gCPU.vr[vrB].b[(i<<2)+2]; temp += (uint16)gCPU.vr[vrA].b[(i<<2)+3] * (uint16)gCPU.vr[vrB].b[(i<<2)+3]; gCPU.vr[vrD].w[i] = temp; } } /* vmsumuhm Vector Multiply Sum Unsigned Half Word Modulo * v.205 */ void ppc_opc_vmsumuhm() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; uint32 temp; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<4; i++) { temp = gCPU.vr[vrC].w[i]; temp += (uint32)gCPU.vr[vrA].h[i<<1] * (uint32)gCPU.vr[vrB].h[i<<1]; temp += (uint32)gCPU.vr[vrA].h[(i<<1)+1] * (uint32)gCPU.vr[vrB].h[(i<<1)+1]; gCPU.vr[vrD].w[i] = temp; } } /* vmsummbm Vector Multiply Sum Mixed-Sign Byte Modulo * v.201 */ void ppc_opc_vmsummbm() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; sint32 temp; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<4; i++) { temp = gCPU.vr[vrC].sw[i]; temp += (sint16)gCPU.vr[vrA].sb[i<<2] * (uint16)gCPU.vr[vrB].b[i<<2]; temp += (sint16)gCPU.vr[vrA].sb[(i<<2)+1] * (uint16)gCPU.vr[vrB].b[(i<<2)+1]; temp += (sint16)gCPU.vr[vrA].sb[(i<<2)+2] * (uint16)gCPU.vr[vrB].b[(i<<2)+2]; temp += (sint16)gCPU.vr[vrA].sb[(i<<2)+3] * (uint16)gCPU.vr[vrB].b[(i<<2)+3]; gCPU.vr[vrD].sw[i] = temp; } } /* vmsumshm Vector Multiply Sum Signed Half Word Modulo * v.202 */ void ppc_opc_vmsumshm() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; sint32 temp; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<4; i++) { temp = gCPU.vr[vrC].sw[i]; temp += (sint32)gCPU.vr[vrA].sh[i<<1] * (sint32)gCPU.vr[vrB].sh[i<<1]; temp += (sint32)gCPU.vr[vrA].sh[(i<<1)+1] * (sint32)gCPU.vr[vrB].sh[(i<<1)+1]; gCPU.vr[vrD].sw[i] = temp; } } /* vmsumuhs Vector Multiply Sum Unsigned Half Word Saturate * v.206 */ void ppc_opc_vmsumuhs() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; uint64 temp; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); /* For this, there's no way to get around 64-bit math. If we use * the hacks used before, then we have to do it so often, that * we'll outpace the 64-bit math in execution time. */ int i; for (i=0; i<4; i++) { temp = gCPU.vr[vrC].w[i]; temp += (uint32)gCPU.vr[vrA].h[i<<1] * (uint32)gCPU.vr[vrB].h[i<<1]; temp += (uint32)gCPU.vr[vrA].h[(i<<1)+1] * (uint32)gCPU.vr[vrB].h[(i<<1)+1]; gCPU.vr[vrD].w[i] = SATURATE_UW(temp); } } /* vmsumshs Vector Multiply Sum Signed Half Word Saturate * v.203 */ void ppc_opc_vmsumshs() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; sint64 temp; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); /* For this, there's no way to get around 64-bit math. If we use * the hacks used before, then we have to do it so often, that * we'll outpace the 64-bit math in execution time. */ int i; for (i=0; i<4; i++) { temp = gCPU.vr[vrC].sw[i]; temp += (sint32)gCPU.vr[vrA].sh[i<<1] * (sint32)gCPU.vr[vrB].sh[i<<1]; temp += (sint32)gCPU.vr[vrA].sh[(i<<1)+1] * (sint32)gCPU.vr[vrB].sh[(i<<1)+1]; gCPU.vr[vrD].sw[i] = SATURATE_SW(temp); } } /* vsum4ubs Vector Sum Across Partial (1/4) Unsigned Byte Saturate * v.275 */ void ppc_opc_vsum4ubs() { VECTOR_DEBUG; int vrD, vrA, vrB; uint64 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); /* For this, there's no way to get around 64-bit math. If we use * the hacks used before, then we have to do it so often, that * we'll outpace the 64-bit math in execution time. */ int i; for (i=0; i<4; i++) { res = (uint64)gCPU.vr[vrB].w[i]; res += (uint64)gCPU.vr[vrA].b[(i<<2)]; res += (uint64)gCPU.vr[vrA].b[(i<<2)+1]; res += (uint64)gCPU.vr[vrA].b[(i<<2)+2]; res += (uint64)gCPU.vr[vrA].b[(i<<2)+3]; gCPU.vr[vrD].w[i] = SATURATE_UW(res); } } /* vsum4sbs Vector Sum Across Partial (1/4) Signed Byte Saturate * v.273 */ void ppc_opc_vsum4sbs() { VECTOR_DEBUG; int vrD, vrA, vrB; sint64 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (sint64)gCPU.vr[vrB].sw[i]; res += (sint64)gCPU.vr[vrA].sb[(i<<2)]; res += (sint64)gCPU.vr[vrA].sb[(i<<2)+1]; res += (sint64)gCPU.vr[vrA].sb[(i<<2)+2]; res += (sint64)gCPU.vr[vrA].sb[(i<<2)+3]; gCPU.vr[vrD].sw[i] = SATURATE_SW(res); } } /* vsum4shs Vector Sum Across Partial (1/4) Signed Half Word Saturate * v.274 */ void ppc_opc_vsum4shs() { VECTOR_DEBUG; int vrD, vrA, vrB; sint64 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (sint64)gCPU.vr[vrB].sw[i]; res += (sint64)gCPU.vr[vrA].sh[(i<<1)]; res += (sint64)gCPU.vr[vrA].sh[(i<<1)+1]; gCPU.vr[vrD].sw[i] = SATURATE_SW(res); } } /* vsum2sws Vector Sum Across Partial (1/2) Signed Word Saturate * v.272 */ void ppc_opc_vsum2sws() { VECTOR_DEBUG; int vrD, vrA, vrB; sint64 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); res = (sint64)gCPU.vr[vrA].sw[0] + (sint64)gCPU.vr[vrA].sw[1]; res += (sint64)gCPU.vr[vrB].sw[VECT_ODD(0)]; gCPU.vr[vrD].w[VECT_ODD(0)] = SATURATE_SW(res); gCPU.vr[vrD].w[VECT_EVEN(0)] = 0; res = (sint64)gCPU.vr[vrA].sw[2] + (sint64)gCPU.vr[vrA].sw[3]; res += (sint64)gCPU.vr[vrB].sw[VECT_ODD(1)]; gCPU.vr[vrD].w[VECT_ODD(1)] = SATURATE_SW(res); gCPU.vr[vrD].w[VECT_EVEN(1)] = 0; } /* vsumsws Vector Sum Across Signed Word Saturate * v.271 */ void ppc_opc_vsumsws() { VECTOR_DEBUG; int vrD, vrA, vrB; sint64 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); res = (sint64)gCPU.vr[vrA].sw[0] + (sint64)gCPU.vr[vrA].sw[1]; res += (sint64)gCPU.vr[vrA].sw[2] + (sint64)gCPU.vr[vrA].sw[3]; res += (sint64)VECT_W(gCPU.vr[vrB], 3); VECT_W(gCPU.vr[vrD], 3) = SATURATE_SW(res); VECT_W(gCPU.vr[vrD], 2) = 0; VECT_W(gCPU.vr[vrD], 1) = 0; VECT_W(gCPU.vr[vrD], 0) = 0; } /* vnmsubfp Vector Negative Multiply-Subtract Floating Point * v.215 */ void ppc_opc_vnmsubfp() { VECTOR_DEBUG; int vrD, vrA, vrB, vrC; double res; PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP res = (double)gCPU.vr[vrA].f[i] * (double)gCPU.vr[vrC].f[i]; res = (double)gCPU.vr[vrB].f[i] - res; gCPU.vr[vrD].f[i] = (float)res; } } /* vavgub Vector Average Unsigned Byte * v.152 */ void ppc_opc_vavgub() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = (uint16)gCPU.vr[vrA].b[i] + (uint16)gCPU.vr[vrB].b[i] + 1; gCPU.vr[vrD].b[i] = (res >> 1); } } /* vavguh Vector Average Unsigned Half Word * v.153 */ void ppc_opc_vavguh() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (uint32)gCPU.vr[vrA].h[i] + (uint32)gCPU.vr[vrB].h[i] + 1; gCPU.vr[vrD].h[i] = (res >> 1); } } /* vavguw Vector Average Unsigned Word * v.154 */ void ppc_opc_vavguw() { VECTOR_DEBUG; int vrD, vrA, vrB; uint64 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (uint64)gCPU.vr[vrA].w[i] + (uint64)gCPU.vr[vrB].w[i] + 1; gCPU.vr[vrD].w[i] = (res >> 1); } } /* vavgsb Vector Average Signed Byte * v.149 */ void ppc_opc_vavgsb() { VECTOR_DEBUG; int vrD, vrA, vrB; sint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = (sint16)gCPU.vr[vrA].sb[i] + (sint16)gCPU.vr[vrB].sb[i] + 1; gCPU.vr[vrD].sb[i] = (res >> 1); } } /* vavgsh Vector Average Signed Half Word * v.150 */ void ppc_opc_vavgsh() { VECTOR_DEBUG; int vrD, vrA, vrB; sint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = (sint32)gCPU.vr[vrA].sh[i] + (sint32)gCPU.vr[vrB].sh[i] + 1; gCPU.vr[vrD].sh[i] = (res >> 1); } } /* vavgsw Vector Average Signed Word * v.151 */ void ppc_opc_vavgsw() { VECTOR_DEBUG; int vrD, vrA, vrB; sint64 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = (sint64)gCPU.vr[vrA].sw[i] + (sint64)gCPU.vr[vrB].sw[i] + 1; gCPU.vr[vrD].sw[i] = (res >> 1); } } /* vmaxub Vector Maximum Unsigned Byte * v.182 */ void ppc_opc_vmaxub() { VECTOR_DEBUG; int vrD, vrA, vrB; uint8 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = gCPU.vr[vrA].b[i]; if (res < gCPU.vr[vrB].b[i]) res = gCPU.vr[vrB].b[i]; gCPU.vr[vrD].b[i] = res; } } /* vmaxuh Vector Maximum Unsigned Half Word * v.183 */ void ppc_opc_vmaxuh() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = gCPU.vr[vrA].h[i]; if (res < gCPU.vr[vrB].h[i]) res = gCPU.vr[vrB].h[i]; gCPU.vr[vrD].h[i] = res; } } /* vmaxuw Vector Maximum Unsigned Word * v.184 */ void ppc_opc_vmaxuw() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i]; if (res < gCPU.vr[vrB].w[i]) res = gCPU.vr[vrB].w[i]; gCPU.vr[vrD].w[i] = res; } } /* vmaxsb Vector Maximum Signed Byte * v.179 */ void ppc_opc_vmaxsb() { VECTOR_DEBUG; int vrD, vrA, vrB; sint8 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = gCPU.vr[vrA].sb[i]; if (res < gCPU.vr[vrB].sb[i]) res = gCPU.vr[vrB].sb[i]; gCPU.vr[vrD].sb[i] = res; } } /* vmaxsh Vector Maximum Signed Half Word * v.180 */ void ppc_opc_vmaxsh() { VECTOR_DEBUG; int vrD, vrA, vrB; sint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = gCPU.vr[vrA].sh[i]; if (res < gCPU.vr[vrB].sh[i]) res = gCPU.vr[vrB].sh[i]; gCPU.vr[vrD].sh[i] = res; } } /* vmaxsw Vector Maximum Signed Word * v.181 */ void ppc_opc_vmaxsw() { VECTOR_DEBUG; int vrD, vrA, vrB; sint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].sw[i]; if (res < gCPU.vr[vrB].sw[i]) res = gCPU.vr[vrB].sw[i]; gCPU.vr[vrD].sw[i] = res; } } /* vmaxfp Vector Maximum Floating Point * v.178 */ void ppc_opc_vmaxfp() { VECTOR_DEBUG; int vrD, vrA, vrB; float res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP res = gCPU.vr[vrA].f[i]; if (res < gCPU.vr[vrB].f[i]) res = gCPU.vr[vrB].f[i]; gCPU.vr[vrD].f[i] = res; } } /* vminub Vector Minimum Unsigned Byte * v.191 */ void ppc_opc_vminub() { VECTOR_DEBUG; int vrD, vrA, vrB; uint8 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = gCPU.vr[vrA].b[i]; if (res > gCPU.vr[vrB].b[i]) res = gCPU.vr[vrB].b[i]; gCPU.vr[vrD].b[i] = res; } } /* vminuh Vector Minimum Unsigned Half Word * v.192 */ void ppc_opc_vminuh() { VECTOR_DEBUG; int vrD, vrA, vrB; uint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = gCPU.vr[vrA].h[i]; if (res > gCPU.vr[vrB].h[i]) res = gCPU.vr[vrB].h[i]; gCPU.vr[vrD].h[i] = res; } } /* vminuw Vector Minimum Unsigned Word * v.193 */ void ppc_opc_vminuw() { VECTOR_DEBUG; int vrD, vrA, vrB; uint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].w[i]; if (res > gCPU.vr[vrB].w[i]) res = gCPU.vr[vrB].w[i]; gCPU.vr[vrD].w[i] = res; } } /* vminsb Vector Minimum Signed Byte * v.188 */ void ppc_opc_vminsb() { VECTOR_DEBUG; int vrD, vrA, vrB; sint8 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { res = gCPU.vr[vrA].sb[i]; if (res > gCPU.vr[vrB].sb[i]) res = gCPU.vr[vrB].sb[i]; gCPU.vr[vrD].sb[i] = res; } } /* vminsh Vector Minimum Signed Half Word * v.189 */ void ppc_opc_vminsh() { VECTOR_DEBUG; int vrD, vrA, vrB; sint16 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { res = gCPU.vr[vrA].sh[i]; if (res > gCPU.vr[vrB].sh[i]) res = gCPU.vr[vrB].sh[i]; gCPU.vr[vrD].sh[i] = res; } } /* vminsw Vector Minimum Signed Word * v.190 */ void ppc_opc_vminsw() { VECTOR_DEBUG; int vrD, vrA, vrB; sint32 res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { res = gCPU.vr[vrA].sw[i]; if (res > gCPU.vr[vrB].sw[i]) res = gCPU.vr[vrB].sw[i]; gCPU.vr[vrD].sw[i] = res; } } /* vminfp Vector Minimum Floating Point * v.187 */ void ppc_opc_vminfp() { VECTOR_DEBUG; int vrD, vrA, vrB; float res; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP res = gCPU.vr[vrA].f[i]; if (res > gCPU.vr[vrB].f[i]) res = gCPU.vr[vrB].f[i]; gCPU.vr[vrD].f[i] = res; } } /* vrfin Vector Round to Floating-Point Integer Nearest * v.231 */ void ppc_opc_vrfin() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); /* Documentation doesn't dictate how this instruction should * round from a middle point. With a test on a real G4, it was * found to be round to nearest, with bias to even if equidistant. * * This is covered by the function rint() */ int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = rintf(gCPU.vr[vrB].f[i]); } } /* vrfip Vector Round to Floating-Point Integer toward Plus Infinity * v.232 */ void ppc_opc_vrfip() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = ceilf(gCPU.vr[vrB].f[i]); } } /* vrfim Vector Round to Floating-Point Integer toward Minus Infinity * v.230 */ void ppc_opc_vrfim() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = floorf(gCPU.vr[vrB].f[i]); } } /* vrfiz Vector Round to Floating-Point Integer toward Zero * v.233 */ void ppc_opc_vrfiz() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = truncf(gCPU.vr[vrD].f[i]); } } /* vrefp Vector Reciprocal Estimate Floating Point * v.228 */ void ppc_opc_vrefp() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); /* This emulation generates an exact value, instead of an estimate. * This is technically within specs, but some test-suites expect the * exact estimate value returned by G4s. These anomolous failures * should be ignored. */ int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = 1 / gCPU.vr[vrB].f[i]; } } /* vrsqrtefp Vector Reciprocal Square Root Estimate Floating Point * v.237 */ void ppc_opc_vrsqrtefp() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); /* This emulation generates an exact value, instead of an estimate. * This is technically within specs, but some test-suites expect the * exact estimate value returned by G4s. These anomolous failures * should be ignored. */ int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = 1 / sqrt(gCPU.vr[vrB].f[i]); } } /* vlogefp Vector Log2 Estimate Floating Point * v.175 */ void ppc_opc_vlogefp() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); /* This emulation generates an exact value, instead of an estimate. * This is technically within specs, but some test-suites expect the * exact estimate value returned by G4s. These anomolous failures * should be ignored. */ int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = log2(gCPU.vr[vrB].f[i]); } } /* vexptefp Vector 2 Raised to the Exponent Estimate Floating Point * v.173 */ void ppc_opc_vexptefp() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); PPC_OPC_ASSERT(vrA==0); /* This emulation generates an exact value, instead of an estimate. * This is technically within specs, but some test-suites expect the * exact estimate value returned by G4s. These anomolous failures * should be ignored. */ int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = exp2(gCPU.vr[vrB].f[i]); } } /* vcfux Vector Convert from Unsigned Fixed-Point Word * v.156 */ void ppc_opc_vcfux() { VECTOR_DEBUG; int vrD, vrB; uint32 uimm; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, uimm, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = ((float)gCPU.vr[vrB].w[i]) / (1 << uimm); } } /* vcfsx Vector Convert from Signed Fixed-Point Word * v.155 */ void ppc_opc_vcfsx() { VECTOR_DEBUG; int vrD, vrB; uint32 uimm; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, uimm, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP gCPU.vr[vrD].f[i] = ((float)gCPU.vr[vrB].sw[i]) / (1 << uimm); } } /* vctsxs Vector Convert To Signed Fixed-Point Word Saturate * v.171 */ void ppc_opc_vctsxs() { VECTOR_DEBUG; int vrD, vrB; uint32 uimm; float ftmp; sint32 tmp; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, uimm, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP ftmp = gCPU.vr[vrB].f[i] * (float)(1 << uimm); ftmp = truncf(ftmp); tmp = (sint32)ftmp; if (ftmp > 2147483647.0) { tmp = 2147483647; // 0x7fffffff gCPU.vscr |= VSCR_SAT; } else if (ftmp < -2147483648.0) { tmp = -2147483648LL; // 0x80000000 gCPU.vscr |= VSCR_SAT; } gCPU.vr[vrD].sw[i] = tmp; } } /* vctuxs Vector Convert to Unsigned Fixed-Point Word Saturate * v.172 */ void ppc_opc_vctuxs() { VECTOR_DEBUG; int vrD, vrB; uint32 tmp, uimm; float ftmp; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, uimm, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP ftmp = gCPU.vr[vrB].f[i] * (float)(1 << uimm); ftmp = truncf(ftmp); tmp = (uint32)ftmp; if (ftmp > 4294967295.0) { tmp = 0xffffffff; gCPU.vscr |= VSCR_SAT; } else if (ftmp < 0) { tmp = 0; gCPU.vscr |= VSCR_SAT; } gCPU.vr[vrD].w[i] = tmp; } } /* vand Vector Logical AND * v.147 */ void ppc_opc_vand() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); gCPU.vr[vrD].d[0] = gCPU.vr[vrA].d[0] & gCPU.vr[vrB].d[0]; gCPU.vr[vrD].d[1] = gCPU.vr[vrA].d[1] & gCPU.vr[vrB].d[1]; } /* vandc Vector Logical AND with Complement * v.148 */ void ppc_opc_vandc() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); gCPU.vr[vrD].d[0] = gCPU.vr[vrA].d[0] & ~gCPU.vr[vrB].d[0]; gCPU.vr[vrD].d[1] = gCPU.vr[vrA].d[1] & ~gCPU.vr[vrB].d[1]; } /* vor Vector Logical OR * v.217 */ void ppc_opc_vor() { VECTOR_DEBUG_COMMON; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); gCPU.vr[vrD].d[0] = gCPU.vr[vrA].d[0] | gCPU.vr[vrB].d[0]; gCPU.vr[vrD].d[1] = gCPU.vr[vrA].d[1] | gCPU.vr[vrB].d[1]; } /* vnor Vector Logical NOR * v.216 */ void ppc_opc_vnor() { VECTOR_DEBUG; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); gCPU.vr[vrD].d[0] = ~(gCPU.vr[vrA].d[0] | gCPU.vr[vrB].d[0]); gCPU.vr[vrD].d[1] = ~(gCPU.vr[vrA].d[1] | gCPU.vr[vrB].d[1]); } /* vxor Vector Logical XOR * v.282 */ void ppc_opc_vxor() { VECTOR_DEBUG_COMMON; int vrD, vrA, vrB; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); gCPU.vr[vrD].d[0] = gCPU.vr[vrA].d[0] ^ gCPU.vr[vrB].d[0]; gCPU.vr[vrD].d[1] = gCPU.vr[vrA].d[1] ^ gCPU.vr[vrB].d[1]; } #define CR_CR6 (0x00f0) #define CR_CR6_EQ (1<<7) #define CR_CR6_NE (1<<5) /* vcmpequbx Vector Compare Equal-to Unsigned Byte * v.160 */ void ppc_opc_vcmpequbx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { if (gCPU.vr[vrA].b[i] == gCPU.vr[vrB].b[i]) { gCPU.vr[vrD].b[i] = 0xff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].b[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpequhx Vector Compare Equal-to Unsigned Half Word * v.161 */ void ppc_opc_vcmpequhx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { if (gCPU.vr[vrA].h[i] == gCPU.vr[vrB].h[i]) { gCPU.vr[vrD].h[i] = 0xffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].h[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpequwx Vector Compare Equal-to Unsigned Word * v.162 */ void ppc_opc_vcmpequwx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { if (gCPU.vr[vrA].w[i] == gCPU.vr[vrB].w[i]) { gCPU.vr[vrD].w[i] = 0xffffffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].w[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpeqfpx Vector Compare Equal-to-Floating Point * v.159 */ void ppc_opc_vcmpeqfpx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP if (gCPU.vr[vrA].f[i] == gCPU.vr[vrB].f[i]) { gCPU.vr[vrD].w[i] = 0xffffffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].w[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgtubx Vector Compare Greater-Than Unsigned Byte * v.168 */ void ppc_opc_vcmpgtubx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { if (gCPU.vr[vrA].b[i] > gCPU.vr[vrB].b[i]) { gCPU.vr[vrD].b[i] = 0xff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].b[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgtsbx Vector Compare Greater-Than Signed Byte * v.165 */ void ppc_opc_vcmpgtsbx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<16; i++) { if (gCPU.vr[vrA].sb[i] > gCPU.vr[vrB].sb[i]) { gCPU.vr[vrD].b[i] = 0xff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].b[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgtuhx Vector Compare Greater-Than Unsigned Half Word * v.169 */ void ppc_opc_vcmpgtuhx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { if (gCPU.vr[vrA].h[i] > gCPU.vr[vrB].h[i]) { gCPU.vr[vrD].h[i] = 0xffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].h[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgtshx Vector Compare Greater-Than Signed Half Word * v.166 */ void ppc_opc_vcmpgtshx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<8; i++) { if (gCPU.vr[vrA].sh[i] > gCPU.vr[vrB].sh[i]) { gCPU.vr[vrD].h[i] = 0xffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].h[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgtuwx Vector Compare Greater-Than Unsigned Word * v.170 */ void ppc_opc_vcmpgtuwx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { if (gCPU.vr[vrA].w[i] > gCPU.vr[vrB].w[i]) { gCPU.vr[vrD].w[i] = 0xffffffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].w[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgtswx Vector Compare Greater-Than Signed Word * v.167 */ void ppc_opc_vcmpgtswx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { if (gCPU.vr[vrA].sw[i] > gCPU.vr[vrB].sw[i]) { gCPU.vr[vrD].w[i] = 0xffffffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].w[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgtfpx Vector Compare Greater-Than Floating-Point * v.164 */ void ppc_opc_vcmpgtfpx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP if (gCPU.vr[vrA].f[i] > gCPU.vr[vrB].f[i]) { gCPU.vr[vrD].w[i] = 0xffffffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].w[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpgefpx Vector Compare Greater-Than-or-Equal-to Floating Point * v.163 */ void ppc_opc_vcmpgefpx() { VECTOR_DEBUG; int vrD, vrA, vrB; int tf=CR_CR6_EQ | CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP if (gCPU.vr[vrA].f[i] >= gCPU.vr[vrB].f[i]) { gCPU.vr[vrD].w[i] = 0xffffffff; tf &= ~CR_CR6_NE; } else { gCPU.vr[vrD].w[i] = 0; tf &= ~CR_CR6_EQ; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= tf; } } /* vcmpbfpx Vector Compare Bounds Floating Point * v.157 */ void ppc_opc_vcmpbfpx() { VECTOR_DEBUG; int vrD, vrA, vrB; int le, ge; int ib=CR_CR6_NE; PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB); int i; for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP le = (gCPU.vr[vrA].f[i] <= gCPU.vr[vrB].f[i]) ? 0 : 0x80000000; ge = (gCPU.vr[vrA].f[i] >= -gCPU.vr[vrB].f[i]) ? 0 : 0x40000000; gCPU.vr[vrD].w[i] = le | ge; if (le | ge) { ib = 0; } } if (PPC_OPC_VRc & gCPU.current_opc) { gCPU.cr &= ~CR_CR6; gCPU.cr |= ib; } } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_e500_exc.h�����������������������������������������������������0000644�0001750�0000144�00000003060�10643721150�017546� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ppc_e500_exc.h - necessary definition for e500 exception Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 07/04/2007 Michael.Kang <blackfin.kang@gmail.com> */ /* IVOR0 Critical Input IVOR1 Machine Check IVOR2 Data Storage IVOR3 Instruction Storage IVOR4 External Input IVOR5 Alignment IVOR6 Program IVOR7 Floating-Point Unavailable IVOR8 System Call IVOR9 Auxiliary Processor Unavailable IVOR10 Decrementer IVOR11 Fixed-Interval Timer Interrupt IVOR12 Watchdog Timer Interrupt IVOR13 Data TLB Error IVOR14 Instruction TLB Error IVOR15 Debug */ enum { CRI_INPUT = 0, MACH_CHECK, DATA_ST, INSN_ST, EXT_INT, ALIGN, PROG, FP_UN, SYSCALL, AP_UN, DEC, FIT, WD, DATA_TLB, INSN_TLB, DEBUG }; ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/types.h������������������������������������������������������������0000644�0001750�0000144�00000001427�10717060474�016554� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef __TYPES_H__ #define __TYPES_H__ #include <sys/types.h> #include <stdint.h> #ifndef __BEOS__ typedef enum{ false = 0, true = 1 }bool; #define uint64 uint64_t #define uint32 uint32_t #define uint16 uint16_t #define uint8 uint8_t #else /* HEY, bool/uint8/uint16/uint32/uint64 typedef'd by system */ #include <be/support/SupportDefs.h> #endif #define sint64 int64_t #define sint32 int32_t #define sint16 int16_t #define sint8 int8_t #define byte int8_t #define uint uint32_t typedef struct uint128 { uint64 l; uint64 h; } uint128; typedef struct sint128 { sint64 l; sint64 h; } sint128; #define FASTCALL #define IO_MEM_ACCESS_OK 0 #define IO_MEM_ACCESS_EXC 1 #define IO_MEM_ACCESS_FATAL 2 #define FUNCTION_CONST const #endif �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_fpu.h����������������������������������������������������������0000644�0001750�0000144�00000005306�10635115336�017041� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_fpu.h * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_FPU_H__ #define __PPC_FPU_H__ #include "types.h" #define FPU_SIGN_BIT (0x8000000000000000ULL) #define FPD_SIGN(v) (((v)&FPU_SIGN_BIT)?1:0) #define FPD_EXP(v) ((v)>>52) #define FPD_FRAC(v) ((v)&0x000fffffffffffffULL) #define FPS_SIGN(v) ((v)&0x80000000) #define FPS_EXP(v) ((v)>>23) #define FPS_FRAC(v) ((v)&0x007fffff) // m must be uint64 #define FPD_PACK_VAR(f, s, e, m) (f) = ((s)?FPU_SIGN_BIT:0ULL)|((((uint64)(e))&0x7ff)<<52)|((m)&((1ULL<<52)-1)) #define FPD_UNPACK_VAR(f, s, e, m) {(s)=FPD_SIGN(f);(e)=FPD_EXP(f)&0x7ff;(m)=FPD_FRAC(f);} #define FPS_PACK_VAR(f, s, e, m) (f) = ((s)?0x80000000:0)|((e)<<23)|((m)&0x7fffff) #define FPS_UNPACK_VAR(f, s, e, m) {(s)=FPS_SIGN(f);(e)=FPS_EXP(f)&0xff;(m)=FPS_FRAC(f);} #define FPD_UNPACK(freg, fvar) FPD_UNPACK(freg, fvar.s, fvar.e, fvar.m) void ppc_fpu_test(); typedef enum { ppc_fpr_norm, ppc_fpr_zero, ppc_fpr_NaN, ppc_fpr_Inf, }ppc_fpr_type; typedef struct ppc_quadro_s { ppc_fpr_type type; int s; int e; uint64 m0; // most significant uint64 m1; // least significant }ppc_quadro; typedef struct ppc_double_s { ppc_fpr_type type; int s; int e; uint64 m; }ppc_double; typedef struct ppc_single_s { ppc_fpr_type type; int s; int e; uint m; }ppc_single; double ppc_fpu_get_uint64(uint64 d); double ppc_fpu_get_double(ppc_double *d); void ppc_opc_fabsx(); void ppc_opc_faddx(); void ppc_opc_faddsx(); void ppc_opc_fcmpo(); void ppc_opc_fcmpu(); void ppc_opc_fctiwx(); void ppc_opc_fctiwzx(); void ppc_opc_fdivx(); void ppc_opc_fdivsx(); void ppc_opc_fmaddx(); void ppc_opc_fmaddsx(); void ppc_opc_fmrx(); void ppc_opc_fmsubx(); void ppc_opc_fmsubsx(); void ppc_opc_fmulx(); void ppc_opc_fmulsx(); void ppc_opc_fnabsx(); void ppc_opc_fnegx(); void ppc_opc_fnmaddx(); void ppc_opc_fnmaddsx(); void ppc_opc_fnmsubx(); void ppc_opc_fnmsubsx(); void ppc_opc_fresx(); void ppc_opc_frspx(); void ppc_opc_frsqrtex(); void ppc_opc_fselx(); void ppc_opc_fsqrtx(); void ppc_opc_fsqrtsx(); void ppc_opc_fsubx(); void ppc_opc_fsubsx(); #endif ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/debug.h������������������������������������������������������������0000644�0001750�0000144�00000002026�10634524441�016467� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * debug.h * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __DEBUG_H__ #define __DEBUG_H__ #include "types.h" /* * Debugger Interface */ void ppc_set_singlestep_v(bool v, const char *file, int line, const char *infoformat, ...); void ppc_set_singlestep_nonverbose(bool v); #define SINGLESTEP(info...) ppc_set_singlestep_v(true, __FILE__, __LINE__, info) #endif ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_opc.h����������������������������������������������������������0000644�0001750�0000144�00000003652�10635115336�017032� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_opc.h * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_OPC_H__ #define __PPC_OPC_H__ #include "types.h" static inline void ppc_update_cr0(uint32 r) { gCPU.cr &= 0x0fffffff; if (!r) { gCPU.cr |= CR_CR0_EQ; } else if (r & 0x80000000) { gCPU.cr |= CR_CR0_LT; } else { gCPU.cr |= CR_CR0_GT; } if (gCPU.xer & XER_SO) gCPU.cr |= CR_CR0_SO; } void ppc_opc_bx(); void ppc_opc_bcx(); void ppc_opc_bcctrx(); void ppc_opc_bclrx(); void ppc_opc_dcba(); void ppc_opc_dcbf(); void ppc_opc_dcbi(); void ppc_opc_dcbst(); void ppc_opc_dcbt(); void ppc_opc_dcbtst(); void ppc_opc_eciwx(); void ppc_opc_ecowx(); void ppc_opc_eieio(); void ppc_opc_icbi(); void ppc_opc_isync(); void ppc_opc_mcrf(); void ppc_opc_mcrfs(); void ppc_opc_mcrxr(); void ppc_opc_mfcr(); void ppc_opc_mffsx(); void ppc_opc_mfmsr(); void ppc_opc_mfspr(); void ppc_opc_mfsr(); void ppc_opc_mfsrin(); void ppc_opc_mftb(); void ppc_opc_mtcrf(); void ppc_opc_mtfsb0x(); void ppc_opc_mtfsb1x(); void ppc_opc_mtfsfx(); void ppc_opc_mtfsfix(); void ppc_opc_mtmsr(); void ppc_opc_mtspr(); void ppc_opc_mtsr(); void ppc_opc_mtsrin(); void ppc_opc_rfi(); void ppc_opc_sc(); void ppc_opc_sync(); void ppc_opc_tlbia(); void ppc_opc_tlbie(); void ppc_opc_tlbsync(); void ppc_opc_tw(); void ppc_opc_twi(); #endif ��������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_io.h�����������������������������������������������������������0000644�0001750�0000144�00000002643�10635115336�016657� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ppc_io.h - necessary io function definition for powerpc Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 04/26/2006 Michael.Kang <blackfin.kang@gmail.com> */ #ifndef __PPC_IO_H__ #define __PPC_IO_H__ uint32_t ppc_read_byte(void * state, uint32_t addr); uint32_t ppc_read_halfword(void * state,uint32_t addr); uint32_t ppc_read_word(void * state, uint32_t addr); void ppc_write_byte(void * state, uint32_t addr, uint32_t data); void ppc_write_halfword(void * state, uint32_t addr,uint32_t data); void ppc_write_word(void * state,uint32_t addr,uint32_t data); #endif ���������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_e500_exc.c�����������������������������������������������������0000644�0001750�0000144�00000010155�10712640602�017543� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ppc_e500_exc.c - implementation of e500 exception Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 07/04/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include "ppc_cpu.h" #include "ppc_e500_exc.h" #include "ppc_mmu.h" #include "tracers.h" bool FASTCALL ppc_exception(uint32 type, uint32 flags, uint32 a) { switch(type){ case CRI_INPUT: case MACH_CHECK: case DATA_ST: case INSN_ST: fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, gCPU.pc); skyeye_exit(-1); case EXT_INT: gCPU.srr[0] = gCPU.npc; gCPU.srr[1] = gCPU.msr; /* CE,ME,DE is unchanged, other bits should be clear */ gCPU.msr &= 0x21200; break; case ALIGN: case PROG: case FP_UN: fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, gCPU.pc); skyeye_exit(-1); break; case SYSCALL: gCPU.srr[0] = gCPU.npc; gCPU.srr[1] = gCPU.msr; /* WE,EE,PR,IS,DS,FP,FE0,FE1 in msr should be cleared */ gCPU.msr &= ~(0x2e930); break; case AP_UN: fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, gCPU.pc); skyeye_exit(-1); case DEC: gCPU.srr[0] = gCPU.npc; gCPU.srr[1] = gCPU.msr; /* CE,ME and DE bit unchanged, other bit should be clear*/ gCPU.msr &= 0x21200; /* DIS bit is set */ gCPU.tsr |= 0x8000000; break; case FIT: case WD: fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, gCPU.pc); skyeye_exit(-1); break; case DATA_TLB: //printf(" In %s, DATA_TLB exp happened, pc=0x%x,addr=0x%x\n", __FUNCTION__, gCPU.pc, a); gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr; //gCPU.esr |= ST; gCPU.dear = a; /* save the data address accessed by exception instruction */ gCPU.msr &= 0x21200; /* Update TLB */ /** * if TLBSELD = 00, MAS0[ESEL] is updated with the next victim information for TLB0.Finially, * the MAS[0] field is updated with the incremented value of TLB0[NV].Thus, ESEL points to * the current victim * (the entry to be replaced), while MAS0[NV] points to the next victim to be used if a TLB0 * entry is replaced */ /** * update TLBSEL with TLBSELD */ e500_mmu.mas[0] = (e500_mmu.mas[4] & 0x10000000) | (e500_mmu.mas[0] & (~0x10000000)); /* if TLBSELD == 0, update ESEL and NV bit in MAS Register*/ if(!TLBSELD(e500_mmu.mas[4])){ /* if TLBSELD == 0, ESEL = TLB[0].NV */ /* update ESEL of MAS0 */ e500_mmu.mas[0] = (e500_mmu.tlb0_nv << 16) | (e500_mmu.mas[0] & 0xFFF0FFFF) ; /* update NV of MAS0 , NV = ~TLB[0].NV */ e500_mmu.mas[0] = (~e500_mmu.tlb0_nv & 0x1) | (e500_mmu.mas[0] & 0xFFFFFFFE); } /** * Set EPN to EPN of access */ e500_mmu.mas[2] = (a & 0xFFFFF000) | (e500_mmu.mas[3] &0xFFF); /** * Set TSIZE[0 - 3] to TSIZED */ e500_mmu.mas[1] = (e500_mmu.mas[4] & 0xF00)|(e500_mmu.mas[1] & 0xFFFFF0FF); break; case INSN_TLB: case DEBUG: default: fprintf(stderr,"Unknown exception type %d.pc=0x%x\n", type, gCPU.pc); skyeye_exit(-1); } gCPU.npc = (gCPU.ivpr & 0xFFFF0000) | (gCPU.ivor[type] & 0xFFF0); return true; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_alu.h����������������������������������������������������������0000644�0001750�0000144�00000004170�10652137355�017032� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_alu.h * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_ALU_H__ #define __PPC_ALU_H__ void ppc_opc_addx(); void ppc_opc_addcx(); void ppc_opc_addex(); void ppc_opc_addi(); void ppc_opc_addic(); void ppc_opc_addic_(); void ppc_opc_addis(); void ppc_opc_addmex(); void ppc_opc_addzex(); void ppc_opc_andx(); void ppc_opc_andcx(); void ppc_opc_andi_(); void ppc_opc_andis_(); void ppc_opc_cmp(); void ppc_opc_cmpi(); void ppc_opc_cmpl(); void ppc_opc_cmpli(); void ppc_opc_cntlzwx(); void ppc_opc_crand(); void ppc_opc_crandc(); void ppc_opc_creqv(); void ppc_opc_crnand(); void ppc_opc_crnor(); void ppc_opc_cror(); void ppc_opc_crorc(); void ppc_opc_crxor(); void ppc_opc_divwx(); void ppc_opc_divwux(); void ppc_opc_eqvx(); void ppc_opc_extsbx(); void ppc_opc_extshx(); void ppc_opc_mulhwx(); void ppc_opc_mulhwux(); void ppc_opc_mulli(); void ppc_opc_mullwx(); void ppc_opc_nandx(); void ppc_opc_negx(); void ppc_opc_norx(); void ppc_opc_orx(); void ppc_opc_orcx(); void ppc_opc_ori(); void ppc_opc_oris(); void ppc_opc_rlwimix(); void ppc_opc_rlwinmx(); void ppc_opc_rlwnmx(); void ppc_opc_slwx(); void ppc_opc_srawx(); void ppc_opc_srawix(); void ppc_opc_srwx(); void ppc_opc_subfx(); void ppc_opc_subfcx(); void ppc_opc_subfex(); void ppc_opc_subfic(); void ppc_opc_subfmex(); void ppc_opc_subfzex(); void ppc_opc_xorx(); void ppc_opc_xori(); void ppc_opc_xoris(); void ppc_opc_iseleq(); void ppc_opc_iselgt(); void ppc_opc_isel(); void ppc_opc_tlbsx(); #endif ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_tools.h��������������������������������������������������������0000644�0001750�0000144�00000002057�10635115336�017407� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_tools.h * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_TOOLS_H__ #define __PPC_TOOLS_H__ #include "types.h" static inline bool ppc_carry_3(uint32 a, uint32 b, uint32 c) { if ((a+b) < a) { return true; } if ((a+b+c) < c) { return true; } return false; } static inline uint32 ppc_word_rotl(uint32 data, int n) { n &= 0x1f; return (data << n) | (data >> (32-n)); } #endif ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_mmu.h����������������������������������������������������������0000644�0001750�0000144�00000013433�10652141376�017047� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_mmu.h * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nmsu.edu) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_MMU_H__ #define __PPC_MMU_H__ #include "types.h" extern byte *gMemory; extern uint32 gMemorySize; #define PPC_MMU_READ 1 #define PPC_MMU_WRITE 2 #define PPC_MMU_CODE 4 #define PPC_MMU_SV 8 #define PPC_MMU_NO_EXC 16 #define PPC_MMU_OK 0 #define PPC_MMU_EXC 1 #define PPC_MMU_FATAL 2 int FASTCALL ppc_effective_to_physical(uint32 addr, int flags, uint32 *result); bool FASTCALL ppc_mmu_set_sdr1(uint32 newval, bool quiesce); void ppc_mmu_tlb_invalidate(); int FASTCALL ppc_read_physical_dword(uint32 addr, uint64 *result); int FASTCALL ppc_read_physical_word(uint32 addr, uint32 *result); int FASTCALL ppc_read_physical_half(uint32 addr, uint16 *result); int FASTCALL ppc_read_physical_byte(uint32 addr, uint8 *result); int FASTCALL ppc_read_effective_code(uint32 addr, uint32 *result); int FASTCALL ppc_read_effective_dword(uint32 addr, uint64 *result); int FASTCALL ppc_read_effective_word(uint32 addr, uint32 *result); int FASTCALL ppc_read_effective_half(uint32 addr, uint16 *result); int FASTCALL ppc_read_effective_byte(uint32 addr, uint8 *result); int FASTCALL ppc_write_physical_dword(uint32 addr, uint64 data); int FASTCALL ppc_write_physical_word(uint32 addr, uint32 data); int FASTCALL ppc_write_physical_half(uint32 addr, uint16 data); int FASTCALL ppc_write_physical_byte(uint32 addr, uint8 data); int FASTCALL ppc_write_effective_dword(uint32 addr, uint64 data); int FASTCALL ppc_write_effective_word(uint32 addr, uint32 data); int FASTCALL ppc_write_effective_half(uint32 addr, uint16 data); int FASTCALL ppc_write_effective_byte(uint32 addr, uint8 data); int FASTCALL ppc_direct_physical_memory_handle(uint32 addr, byte *ptr); int FASTCALL ppc_direct_effective_memory_handle(uint32 addr, byte *ptr); int FASTCALL ppc_direct_effective_memory_handle_code(uint32 addr, byte *ptr); bool FASTCALL ppc_mmu_page_create(uint32 ea, uint32 pa); bool FASTCALL ppc_mmu_page_free(uint32 ea); bool FASTCALL ppc_init_physical_memory(uint size); /* pte: (page table entry) 1st word: 0 V Valid 1-24 VSID Virtual Segment ID 25 H Hash function 26-31 API Abbreviated page index 2nd word: 0-19 RPN Physical page number 20-22 res 23 R Referenced bit 24 C Changed bit 25-28 WIMG Memory/cache control bits 29 res 30-31 PP Page protection bits */ /* * MMU Opcodes */ void ppc_opc_dcbz(); void ppc_opc_dcbtls(); void ppc_opc_lbz(); void ppc_opc_lbzu(); void ppc_opc_lbzux(); void ppc_opc_lbzx(); void ppc_opc_lfd(); void ppc_opc_lfdu(); void ppc_opc_lfdux(); void ppc_opc_lfdx(); void ppc_opc_lfs(); void ppc_opc_lfsu(); void ppc_opc_lfsux(); void ppc_opc_lfsx(); void ppc_opc_lha(); void ppc_opc_lhau(); void ppc_opc_lhaux(); void ppc_opc_lhax(); void ppc_opc_lhbrx(); void ppc_opc_lhz(); void ppc_opc_lhzu(); void ppc_opc_lhzux(); void ppc_opc_lhzx(); void ppc_opc_lmw(); void ppc_opc_lswi(); void ppc_opc_lswx(); void ppc_opc_lwarx(); void ppc_opc_lwbrx(); void ppc_opc_lwz(); void ppc_opc_lwzu(); void ppc_opc_lwzux(); void ppc_opc_lwzx(); void ppc_opc_lvx(); /* for altivec support */ void ppc_opc_lvxl(); void ppc_opc_lvebx(); void ppc_opc_lvehx(); void ppc_opc_lvewx(); void ppc_opc_lvsl(); void ppc_opc_lvsr(); void ppc_opc_dst(); void ppc_opc_stb(); void ppc_opc_stbu(); void ppc_opc_stbux(); void ppc_opc_stbx(); void ppc_opc_stfd(); void ppc_opc_stfdu(); void ppc_opc_stfdux(); void ppc_opc_stfdx(); void ppc_opc_stfiwx(); void ppc_opc_stfs(); void ppc_opc_stfsu(); void ppc_opc_stfsux(); void ppc_opc_stfsx(); void ppc_opc_sth(); void ppc_opc_sthbrx(); void ppc_opc_sthu(); void ppc_opc_sthux(); void ppc_opc_sthx(); void ppc_opc_stmw(); void ppc_opc_stswi(); void ppc_opc_stswx(); void ppc_opc_stw(); void ppc_opc_stwbrx(); void ppc_opc_stwcx_(); void ppc_opc_stwu(); void ppc_opc_stwux(); void ppc_opc_stwx(); void ppc_opc_stvx(); /* for altivec support */ void ppc_opc_stvxl(); void ppc_opc_stvebx(); void ppc_opc_stvehx(); void ppc_opc_stvewx(); void ppc_opc_dstst(); void ppc_opc_dss(); void ppc_opc_tlbivax(); void ppc_opc_tlbwe(); void ppc_opc_tlbrehi(); void ppc_opc_wrteei(); void ppc_opc_wrtee(); /* tlb entry */ typedef struct ppc_tlb_entry_s{ uint v; uint ts; uint tid; uint epn; uint rpn; uint size; uint usxrw; uint wimge; uint x; uint u; uint iprot; }ppc_tlb_entry_t; typedef struct e500_mmu_s{ uint64 pid[3]; uint64 mmucsr0; uint64 mmucfg; uint64 tlbcfg[2]; uint64 mas[8]; uint32 tlb0_nv; }e500_mmu_t; extern e500_mmu_t e500_mmu; extern ppc_tlb_entry_t l1_i_vsp[4]; /* instruction, filled by TLB1 hit */ extern ppc_tlb_entry_t l1_i_tlb4k[64]; /* instruction, filled by TLB0 hit */ extern ppc_tlb_entry_t l1_d_vsp[4]; /* data, filled by TLB1 hit */ extern ppc_tlb_entry_t l1_d_tlb4k[64]; /* data, filled by TLB0 hit */ #define L2_TLB0_SIZE 256 #define L2_TLB1_SIZE 16 extern ppc_tlb_entry_t l2_tlb0_4k[L2_TLB0_SIZE]; /* unified, filled by tlbwe instruction */ extern ppc_tlb_entry_t l2_tlb1_vsp[L2_TLB1_SIZE]; /* filled by tlbwe insructions */ #define TLBSEL(e) ((e >> 28) & 0x1) #define ESEL(e) ((e >> 16) & 0xf) #define EPN(e) (e >> 12) #define TLBSELD(e) ((e & 0x10000000) >> 28) #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/snprintf.h���������������������������������������������������������0000644�0001750�0000144�00000002425�10635115336�017247� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * HT Editor * snprintf.h * * Copyright (C) 1999-2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __SNPRINTF_H__ #define __SNPRINTF_H__ #include <stdio.h> #include <stdlib.h> #include <stdarg.h> int ht_asprintf(char **ptr, const char *format, ...); int ht_vasprintf(char **ptr, const char *format, va_list ap); int ht_snprintf(char *str, size_t count, const char *fmt, ...); int ht_vsnprintf(char *str, size_t count, const char *fmt, va_list args); int ht_fprintf(FILE *file, const char *fmt, ...); int ht_vfprintf(FILE *file, const char *fmt, va_list args); int ht_printf(const char *fmt, ...); int ht_vprintf(const char *fmt, va_list args); #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_exc.h����������������������������������������������������������0000644�0001750�0000144�00000004034�10635115336�017023� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_exc.h * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_EXC_H__ #define __PPC_EXC_H__ #include "types.h" /* * .250 */ #define PPC_EXC_UNKNOWN 0 #define PPC_EXC_SYS_RESET 0x100 #define PPC_EXC_MACHINE_CHECK 0x00200 #define PPC_EXC_DSI 0x00300 #define PPC_EXC_ISI 0x00400 #define PPC_EXC_EXT_INT 0x00500 #define PPC_EXC_ALIGNMENT 0x00600 #define PPC_EXC_PROGRAM 0x00700 #define PPC_EXC_NO_FPU 0x00800 #define PPC_EXC_DEC 0x00900 //Reserved 0x00A00 //Reserved 0x00B00 #define PPC_EXC_SC 0x00C00 #define PPC_EXC_TRACE2 0x00D00 #define PPC_EXC_FLOAT_ASSIST 0x00E00 #define PPC_EXC_PERF_MON 0xF00 #define PPC_EXC_NO_VEC 0xF20 #define PPC_EXC_ALTIVEC 0xF20 #define PPC_EXC_ALTIVEC_ASSIST 0x1600 #define PPC_EXC_TAU 0x1700 #define PPC_EXC_DSISR_PAGE (1<<30) #define PPC_EXC_DSISR_PROT (1<<27) #define PPC_EXC_DSISR_STORE (1<<25) #define PPC_EXC_SRR1_PAGE PPC_EXC_DSISR_PAGE #define PPC_EXC_SRR1_GUARD (1<<28) #define PPC_EXC_SRR1_PROT PPC_EXC_DSISR_PROT #define PPC_EXC_PROGRAM_FLOAT (1<<20) #define PPC_EXC_PROGRAM_ILL (1<<19) #define PPC_EXC_PROGRAM_PRIV (1<<18) #define PPC_EXC_PROGRAM_TRAP (1<<17) /* * set if srr0 does not not contain the address of the intruction * causing the exception */ #define PPC_EXC_PROGRAM_NEXT (1<<16) bool FASTCALL ppc_exception(uint32 type, uint32 flags, uint32 a); void ppc_cpu_raise_ext_exception(); void ppc_cpu_cancel_ext_exception(); #endif ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_alu.c����������������������������������������������������������0000644�0001750�0000144�00000067274�10702130757�017036� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_alu.cc * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #include "debug/tracers.h" #include "cpu/debug.h" */ #include "debug.h" #include "tracers.h" #include "ppc_alu.h" #include "ppc_dec.h" #include "ppc_exc.h" #include "ppc_cpu.h" #include "ppc_opc.h" #include "ppc_tools.h" #include "ppc_mmu.h" static inline uint32 ppc_mask(int MB, int ME) { uint32 mask; if (MB <= ME) { if (ME-MB == 31) { mask = 0xffffffff; } else { mask = ((1<<(ME-MB+1))-1)<<(31-ME); } } else { mask = ppc_word_rotl((1<<(32-MB+ME+1))-1, 31-ME); } return mask; } /* * addx Add * .422 */ void ppc_opc_addx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); gCPU.gpr[rD] = gCPU.gpr[rA] + gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * addox Add with Overflow * .422 */ void ppc_opc_addox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); gCPU.gpr[rD] = gCPU.gpr[rA] + gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("addox unimplemented\n"); } /* * addcx Add Carrying * .423 */ void ppc_opc_addcx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; gCPU.gpr[rD] = a + gCPU.gpr[rB]; // update xer if (gCPU.gpr[rD] < a) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * addcox Add Carrying with Overflow * .423 */ void ppc_opc_addcox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; gCPU.gpr[rD] = a + gCPU.gpr[rB]; // update xer if (gCPU.gpr[rD] < a) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("addcox unimplemented\n"); } /* * addex Add Extended * .424 */ void ppc_opc_addex() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = a + b + ca; // update xer if (ppc_carry_3(a, b, ca)) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * addeox Add Extended with Overflow * .424 */ void ppc_opc_addeox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = a + b + ca; // update xer if (ppc_carry_3(a, b, ca)) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("addeox unimplemented\n"); } /* * addi Add Immediate * .425 */ void ppc_opc_addi() { int rD, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); gCPU.gpr[rD] = (rA ? gCPU.gpr[rA] : 0) + imm; //fprintf(stderr, "in %s,rD=0x%x,rA=0x%x,imm=0x%x,gCPU.gpr[rD]=0x%x\n",__FUNCTION__, rD,rA,imm,gCPU.gpr[rD]); } /* * addic Add Immediate Carrying * .426 */ void ppc_opc_addic() { int rD, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint32 a = gCPU.gpr[rA]; gCPU.gpr[rD] = a + imm; // update XER if (gCPU.gpr[rD] < a) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } } /* * addic. Add Immediate Carrying and Record * .427 */ void ppc_opc_addic_() { int rD, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint32 a = gCPU.gpr[rA]; gCPU.gpr[rD] = a + imm; // update XER if (gCPU.gpr[rD] < a) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } /* * addis Add Immediate Shifted * .428 */ void ppc_opc_addis() { int rD, rA; uint32 imm; PPC_OPC_TEMPL_D_Shift16(gCPU.current_opc, rD, rA, imm); gCPU.gpr[rD] = (rA ? gCPU.gpr[rA] : 0) + imm; } /* * addmex Add to Minus One Extended * .429 */ void ppc_opc_addmex() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = a + ca + 0xffffffff; if (a || ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * addmeox Add to Minus One Extended with Overflow * .429 */ void ppc_opc_addmeox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = a + ca + 0xffffffff; if (a || ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("addmeox unimplemented\n"); } /* * addzex Add to Zero Extended * .430 */ void ppc_opc_addzex() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = a + ca; if ((a == 0xffffffff) && ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } // update xer if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * addzeox Add to Zero Extended with Overflow * .430 */ void ppc_opc_addzeox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = a + ca; if ((a == 0xffffffff) && ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } // update xer if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("addzeox unimplemented\n"); } /* * andx AND * .431 */ void ppc_opc_andx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = gCPU.gpr[rS] & gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * andcx AND with Complement * .432 */ void ppc_opc_andcx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = gCPU.gpr[rS] & ~gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * andi. AND Immediate * .433 */ void ppc_opc_andi_() { int rS, rA; uint32 imm; PPC_OPC_TEMPL_D_UImm(gCPU.current_opc, rS, rA, imm); gCPU.gpr[rA] = gCPU.gpr[rS] & imm; // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } /* * andis. AND Immediate Shifted * .434 */ void ppc_opc_andis_() { int rS, rA; uint32 imm; PPC_OPC_TEMPL_D_Shift16(gCPU.current_opc, rS, rA, imm); gCPU.gpr[rA] = gCPU.gpr[rS] & imm; // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } /* * cmp Compare * .442 */ static uint32 ppc_cmp_and_mask[8] = { 0xfffffff0, 0xffffff0f, 0xfffff0ff, 0xffff0fff, 0xfff0ffff, 0xff0fffff, 0xf0ffffff, 0x0fffffff, }; void ppc_opc_cmp() { uint32 cr; int rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, cr, rA, rB); cr >>= 2; sint32 a = gCPU.gpr[rA]; sint32 b = gCPU.gpr[rB]; uint32 c; if (a < b) { c = 8; } else if (a > b) { c = 4; } else { c = 2; } if (gCPU.xer & XER_SO) c |= 1; cr = 7-cr; gCPU.cr &= ppc_cmp_and_mask[cr]; gCPU.cr |= c<<(cr*4); } /* * cmpi Compare Immediate * .443 */ void ppc_opc_cmpi() { uint32 cr; int rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, cr, rA, imm); cr >>= 2; sint32 a = gCPU.gpr[rA]; sint32 b = imm; uint32 c; /* if (!VALGRIND_CHECK_READABLE(a, sizeof a)) { ht_printf("%08x <--i\n", gCPU.pc); // SINGLESTEP(""); }*/ if (a < b) { c = 8; } else if (a > b) { c = 4; } else { c = 2; } if (gCPU.xer & XER_SO) c |= 1; cr = 7-cr; gCPU.cr &= ppc_cmp_and_mask[cr]; gCPU.cr |= c<<(cr*4); //fprintf(stderr,"in %s,rA=%d,gpr[rA]=0x%d,im=%d,c=%d\n",__FUNCTION__,rA,gCPU.gpr[rA],imm,c); } /* * cmpl Compare Logical * .444 */ void ppc_opc_cmpl() { uint32 cr; int rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, cr, rA, rB); cr >>= 2; uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; uint32 c; if (a < b) { c = 8; } else if (a > b) { c = 4; } else { c = 2; } if (gCPU.xer & XER_SO) c |= 1; cr = 7-cr; gCPU.cr &= ppc_cmp_and_mask[cr]; gCPU.cr |= c<<(cr*4); } /* * cmpli Compare Logical Immediate * .445 */ void ppc_opc_cmpli() { uint32 cr; int rA; uint32 imm; PPC_OPC_TEMPL_D_UImm(gCPU.current_opc, cr, rA, imm); cr >>= 2; uint32 a = gCPU.gpr[rA]; uint32 b = imm; uint32 c; if (a < b) { c = 8; } else if (a > b) { c = 4; } else { c = 2; } if (gCPU.xer & XER_SO) c |= 1; cr = 7-cr; gCPU.cr &= ppc_cmp_and_mask[cr]; gCPU.cr |= c<<(cr*4); } /* * cntlzwx Count Leading Zeros Word * .447 */ void ppc_opc_cntlzwx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); PPC_OPC_ASSERT(rB==0); uint32 n=0; uint32 x=0x80000000; uint32 v=gCPU.gpr[rS]; while (!(v & x)) { n++; if (n==32) break; x>>=1; } gCPU.gpr[rA] = n; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * crand Condition Register AND * .448 */ void ppc_opc_crand() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); if ((gCPU.cr & (1<<(31-crA))) && (gCPU.cr & (1<<(31-crB)))) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * crandc Condition Register AND with Complement * .449 */ void ppc_opc_crandc() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); if ((gCPU.cr & (1<<(31-crA))) && !(gCPU.cr & (1<<(31-crB)))) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * creqv Condition Register Equivalent * .450 */ void ppc_opc_creqv() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); if (((gCPU.cr & (1<<(31-crA))) && (gCPU.cr & (1<<(31-crB)))) || (!(gCPU.cr & (1<<(31-crA))) && !(gCPU.cr & (1<<(31-crB))))) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * crnand Condition Register NAND * .451 */ void ppc_opc_crnand() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); if (!((gCPU.cr & (1<<(31-crA))) && (gCPU.cr & (1<<(31-crB))))) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * crnor Condition Register NOR * .452 */ void ppc_opc_crnor() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); uint32 t = (1<<(31-crA)) | (1<<(31-crB)); if (!(gCPU.cr & t)) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * cror Condition Register OR * .453 */ void ppc_opc_cror() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); uint32 t = (1<<(31-crA)) | (1<<(31-crB)); if (gCPU.cr & t) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * crorc Condition Register OR with Complement * .454 */ void ppc_opc_crorc() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); if ((gCPU.cr & (1<<(31-crA))) || !(gCPU.cr & (1<<(31-crB)))) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * crxor Condition Register XOR * .448 */ void ppc_opc_crxor() { int crD, crA, crB; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crA, crB); if ((!(gCPU.cr & (1<<(31-crA))) && (gCPU.cr & (1<<(31-crB)))) || ((gCPU.cr & (1<<(31-crA))) && !(gCPU.cr & (1<<(31-crB))))) { gCPU.cr |= (1<<(31-crD)); } else { gCPU.cr &= ~(1<<(31-crD)); } } /* * divwx Divide Word * .470 */ void ppc_opc_divwx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); if (!gCPU.gpr[rB]) { PPC_ALU_WARN("division by zero @%08x\n", gCPU.pc); } sint32 a = gCPU.gpr[rA]; sint32 b = gCPU.gpr[rB]; gCPU.gpr[rD] = a / b; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * divwox Divide Word with Overflow * .470 */ void ppc_opc_divwox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); if (!gCPU.gpr[rB]) { PPC_ALU_ERR("division by zero\n"); } sint32 a = gCPU.gpr[rA]; sint32 b = gCPU.gpr[rB]; gCPU.gpr[rD] = a / b; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("divwox unimplemented\n"); } /* * divwux Divide Word Unsigned * .472 */ void ppc_opc_divwux() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); if (!gCPU.gpr[rB]) { PPC_ALU_WARN("division by zero @%08x\n", gCPU.pc); } gCPU.gpr[rD] = gCPU.gpr[rA] / gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * divwuox Divide Word Unsigned with Overflow * .472 */ void ppc_opc_divwuox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); if (!gCPU.gpr[rB]) { // PPC_ALU_ERR("division by zero\n"); } gCPU.gpr[rD] = gCPU.gpr[rA] / gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("divwuox unimplemented\n"); } /* * eqvx Equivalent * .480 */ void ppc_opc_eqvx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = ~(gCPU.gpr[rS] ^ gCPU.gpr[rB]); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * extsbx Extend Sign Byte * .481 */ void ppc_opc_extsbx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); PPC_OPC_ASSERT(rB==0); gCPU.gpr[rA] = gCPU.gpr[rS]; if (gCPU.gpr[rA] & 0x80) { gCPU.gpr[rA] |= 0xffffff00; } else { gCPU.gpr[rA] &= ~0xffffff00; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * extshx Extend Sign Half Word * .482 */ void ppc_opc_extshx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); PPC_OPC_ASSERT(rB==0); gCPU.gpr[rA] = gCPU.gpr[rS]; if (gCPU.gpr[rA] & 0x8000) { gCPU.gpr[rA] |= 0xffff0000; } else { gCPU.gpr[rA] &= ~0xffff0000; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * mulhwx Multiply High Word * .595 */ void ppc_opc_mulhwx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); sint64 a = (sint32)gCPU.gpr[rA]; sint64 b = (sint32)gCPU.gpr[rB]; sint64 c = a*b; gCPU.gpr[rD] = ((uint64)c)>>32; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); // PPC_ALU_WARN("mulhw. correct?\n"); } } /* * mulhwux Multiply High Word Unsigned * .596 */ void ppc_opc_mulhwux() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint64 a = gCPU.gpr[rA]; uint64 b = gCPU.gpr[rB]; uint64 c = a*b; gCPU.gpr[rD] = c>>32; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * mulli Multiply Low Immediate * .598 */ void ppc_opc_mulli() { int rD, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); // FIXME: signed / unsigned correct? gCPU.gpr[rD] = gCPU.gpr[rA] * imm; } /* * mullwx Multiply Low Word * .599 */ void ppc_opc_mullwx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); gCPU.gpr[rD] = gCPU.gpr[rA] * gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } if (gCPU.current_opc & PPC_OPC_OE) { // update XER flags PPC_ALU_ERR("mullwx unimplemented\n"); } } /* * nandx NAND * .600 */ void ppc_opc_nandx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = ~(gCPU.gpr[rS] & gCPU.gpr[rB]); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * negx Negate * .601 */ void ppc_opc_negx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); gCPU.gpr[rD] = -gCPU.gpr[rA]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * negox Negate with Overflow * .601 */ void ppc_opc_negox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); gCPU.gpr[rD] = -gCPU.gpr[rA]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("negox unimplemented\n"); } /* * norx NOR * .602 */ void ppc_opc_norx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = ~(gCPU.gpr[rS] | gCPU.gpr[rB]); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * orx OR * .603 */ void ppc_opc_orx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = gCPU.gpr[rS] | gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * orcx OR with Complement * .604 */ void ppc_opc_orcx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = gCPU.gpr[rS] | ~gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * ori OR Immediate * .605 */ void ppc_opc_ori() { int rS, rA; uint32 imm; PPC_OPC_TEMPL_D_UImm(gCPU.current_opc, rS, rA, imm); gCPU.gpr[rA] = gCPU.gpr[rS] | imm; } /* * oris OR Immediate Shifted * .606 */ void ppc_opc_oris() { int rS, rA; uint32 imm; PPC_OPC_TEMPL_D_Shift16(gCPU.current_opc, rS, rA, imm); gCPU.gpr[rA] = gCPU.gpr[rS] | imm; } /* * rlwimix Rotate Left Word Immediate then Mask Insert * .617 */ void ppc_opc_rlwimix() { int rS, rA, SH, MB, ME; PPC_OPC_TEMPL_M(gCPU.current_opc, rS, rA, SH, MB, ME); uint32 v = ppc_word_rotl(gCPU.gpr[rS], SH); uint32 mask = ppc_mask(MB, ME); gCPU.gpr[rA] = (v & mask) | (gCPU.gpr[rA] & ~mask); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * rlwinmx Rotate Left Word Immediate then AND with Mask * .618 */ void ppc_opc_rlwinmx() { int rS, rA, SH, MB, ME; PPC_OPC_TEMPL_M(gCPU.current_opc, rS, rA, SH, MB, ME); uint32 v = ppc_word_rotl(gCPU.gpr[rS], SH); uint32 mask = ppc_mask(MB, ME); gCPU.gpr[rA] = v & mask; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * rlwnmx Rotate Left Word then AND with Mask * .620 */ void ppc_opc_rlwnmx() { int rS, rA, rB, MB, ME; PPC_OPC_TEMPL_M(gCPU.current_opc, rS, rA, rB, MB, ME); uint32 v = ppc_word_rotl(gCPU.gpr[rS], gCPU.gpr[rB]); uint32 mask = ppc_mask(MB, ME); gCPU.gpr[rA] = v & mask; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * slwx Shift Left Word * .625 */ void ppc_opc_slwx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); uint32 s = gCPU.gpr[rB] & 0x3f; if (s > 31) { gCPU.gpr[rA] = 0; } else { gCPU.gpr[rA] = gCPU.gpr[rS] << s; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * srawx Shift Right Algebraic Word * .628 */ void ppc_opc_srawx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); uint32 SH = gCPU.gpr[rB] & 0x3f; gCPU.gpr[rA] = gCPU.gpr[rS]; gCPU.xer &= ~XER_CA; if (gCPU.gpr[rA] & 0x80000000) { uint32 ca = 0; uint i; for (i=0; i < SH; i++) { if (gCPU.gpr[rA] & 1) ca = 1; gCPU.gpr[rA] >>= 1; gCPU.gpr[rA] |= 0x80000000; } if (ca) gCPU.xer |= XER_CA; } else { if (SH > 31) { gCPU.gpr[rA] = 0; } else { gCPU.gpr[rA] >>= SH; } } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * srawix Shift Right Algebraic Word Immediate * .629 */ void ppc_opc_srawix() { int rS, rA; uint32 SH; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, SH); gCPU.gpr[rA] = gCPU.gpr[rS]; gCPU.xer &= ~XER_CA; if (gCPU.gpr[rA] & 0x80000000) { uint32 ca = 0; uint i; for (i=0; i < SH; i++) { if (gCPU.gpr[rA] & 1) ca = 1; gCPU.gpr[rA] >>= 1; gCPU.gpr[rA] |= 0x80000000; } if (ca) gCPU.xer |= XER_CA; } else { if (SH > 31) { gCPU.gpr[rA] = 0; } else { gCPU.gpr[rA] >>= SH; } } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * srwx Shift Right Word * .631 */ void ppc_opc_srwx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); uint32 v = gCPU.gpr[rB] & 0x3f; if (v > 31) { gCPU.gpr[rA] = 0; } else { gCPU.gpr[rA] = gCPU.gpr[rS] >> v; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * subfx Subtract From * .666 */ void ppc_opc_subfx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); gCPU.gpr[rD] = ~gCPU.gpr[rA] + gCPU.gpr[rB] + 1; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * subfox Subtract From with Overflow * .666 */ void ppc_opc_subfox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); gCPU.gpr[rD] = ~gCPU.gpr[rA] + gCPU.gpr[rB] + 1; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("subfox unimplemented\n"); } /* * subfcx Subtract From Carrying * .667 */ void ppc_opc_subfcx() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; gCPU.gpr[rD] = ~a + b + 1; // update xer if (ppc_carry_3(~a, b, 1)) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * subfcox Subtract From Carrying with Overflow * .667 */ void ppc_opc_subfcox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; gCPU.gpr[rD] = ~a + b + 1; // update xer if (ppc_carry_3(~a, b, 1)) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("subfcox unimplemented\n"); } /* * subfex Subtract From Extended * .668 */ void ppc_opc_subfex() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = ~a + b + ca; // update xer if (ppc_carry_3(~a, b, ca)) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * subfeox Subtract From Extended with Overflow * .668 */ void ppc_opc_subfeox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = ~a + b + ca; // update xer if (ppc_carry_3(~a, b, ca)) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("subfeox unimplemented\n"); } /* * subfic Subtract From Immediate Carrying * .669 */ void ppc_opc_subfic() { int rD, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, rD, rA, imm); uint32 a = gCPU.gpr[rA]; gCPU.gpr[rD] = ~a + imm + 1; // update XER if (ppc_carry_3(~a, imm, 1)) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } } /* * subfmex Subtract From Minus One Extended * .670 */ void ppc_opc_subfmex() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = ~a + ca + 0xffffffff; // update XER if ((a!=0xffffffff) || ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * subfmeox Subtract From Minus One Extended with Overflow * .670 */ void ppc_opc_subfmeox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = ~a + ca + 0xffffffff; // update XER if ((a!=0xffffffff) || ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("subfmeox unimplemented\n"); } /* * subfzex Subtract From Zero Extended * .671 */ void ppc_opc_subfzex() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = ~a + ca; if (!a && ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } } /* * subfzeox Subtract From Zero Extended with Overflow * .671 */ void ppc_opc_subfzeox() { int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rB == 0); uint32 a = gCPU.gpr[rA]; uint32 ca = ((gCPU.xer&XER_CA)?1:0); gCPU.gpr[rD] = ~a + ca; if (!a && ca) { gCPU.xer |= XER_CA; } else { gCPU.xer &= ~XER_CA; } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rD]); } // update XER flags PPC_ALU_ERR("subfzeox unimplemented\n"); } /* * xorx XOR * .680 */ void ppc_opc_xorx() { int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); gCPU.gpr[rA] = gCPU.gpr[rS] ^ gCPU.gpr[rB]; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr0 flags ppc_update_cr0(gCPU.gpr[rA]); } } /* * xori XOR Immediate * .681 */ void ppc_opc_xori() { int rS, rA; uint32 imm; PPC_OPC_TEMPL_D_UImm(gCPU.current_opc, rS, rA, imm); gCPU.gpr[rA] = gCPU.gpr[rS] ^ imm; } /* * xoris XOR Immediate Shifted * .682 */ void ppc_opc_xoris() { int rS, rA; uint32 imm; PPC_OPC_TEMPL_D_Shift16(gCPU.current_opc, rS, rA, imm); gCPU.gpr[rA] = gCPU.gpr[rS] ^ imm; } void ppc_opc_iseleq(){ int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); //int crb = 2; if(gCPU.cr & CR_CR0_EQ) gCPU.gpr[rD] = gCPU.gpr[rA]; else gCPU.gpr[rD] = gCPU.gpr[rB]; #ifdef E500 //fprintf(stderr,"In %s, not implemented in E500.\n", __FUNCTION__); #else fprintf(stderr,"In %s, not implemented .\n", __FUNCTION); #endif } void ppc_opc_iselgt(){ int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); int crb = ((gCPU.current_opc)>>6)&0x1f; if(gCPU.cr & CR_CR0_GT) gCPU.gpr[rD] = gCPU.gpr[rA]; else gCPU.gpr[rD] = gCPU.gpr[rB]; #ifdef E500 //fprintf(stderr,"In %s, crb=0x%x, not implemented in E500.\n", __FUNCTION__, crb); #else fprintf(stderr,"In %s, not implemented .\n", __FUNCTION); #endif } void ppc_opc_isel(){ #ifdef E500 int rD, rA, rB; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, rA, rB); int crb = ((gCPU.current_opc)>>6)&0x1f; if(gCPU.cr & (1 << (31 - crb))) gCPU.gpr[rD] = gCPU.gpr[rA]; else gCPU.gpr[rD] = gCPU.gpr[rB]; //fprintf(stderr,"In %s, crb=0x%x,not implemented in E500.\n", __FUNCTION__, crb); #else fprintf(stderr,"In %s, not implemented .\n", __FUNCTION__); #endif } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_exc.c����������������������������������������������������������0000644�0001750�0000144�00000007230�10643716537�017030� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_exc.cc * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nmsu.edu) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Pages marked: v.??? * From: IBM PowerPC MicroProcessor Family: Altivec(tm) Technology... * Programming Environments Manual */ /* * Modified by Michael.Kang to implement E500 core */ //#include "tools/snprintf.h" //#include "debug/tracers.h" //#include "cpu/debug.h" //#include "info.h" #include "ppc_cpu.h" #include "ppc_exc.h" #include "ppc_mmu.h" #include "tracers.h" /* IVOR0 Critical Input IVOR1 Machine Check IVOR2 Data Storage IVOR3 Instruction Storage IVOR4 External Input IVOR5 Alignment IVOR6 Program IVOR7 Floating-Point Unavailable IVOR8 System Call IVOR9 Auxiliary Processor Unavailable IVOR10 Decrementer IVOR11 Fixed-Interval Timer Interrupt IVOR12 Watchdog Timer Interrupt IVOR13 Data TLB Error IVOR14 Instruction TLB Error IVOR15 Debug */ /* * .247 */ #define ST (1 << 24) #if 0 bool FASTCALL ppc_exception(uint32 type, uint32 flags, uint32 a) { if (type != PPC_EXC_DEC) PPC_EXC_TRACE("@%08x: type = %08x (%08x, %08x)\n", gCPU.pc, type, flags, a); switch (type) { case PPC_EXC_DSI: { // .271 gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr; gCPU.esr |= ST; gCPU.dear = a /* save the data address accessed by exception instruction */ gCPU.msr &= 0x21200; gCPU.npc = (gCPU.IVPR & 0xFFFF0000) | (IVOR[2] & 0xFFF0); break; } case PPC_EXC_ISI: { // .274 if (gCPU.pc == 0) { PPC_EXC_WARN("pc == 0 in ISI\n"); //SINGLESTEP(""); } gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | flags; break; } case PPC_EXC_DEC: { // .284 gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr & 0x87c0ffff; break; } case PPC_EXC_EXT_INT: { gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr & 0x87c0ffff; break; } case PPC_EXC_SC: { // .285 gCPU.srr[0] = gCPU.npc; gCPU.srr[1] = gCPU.msr & 0x87c0ffff; break; } case PPC_EXC_NO_FPU: { // .284 gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr & 0x87c0ffff; break; } case PPC_EXC_NO_VEC: { // v.41 gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr & 0x87c0ffff; break; } case PPC_EXC_PROGRAM: { // .283 if (flags & PPC_EXC_PROGRAM_NEXT) { gCPU.srr[0] = gCPU.npc; } else { gCPU.srr[0] = gCPU.pc; } gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | flags; break; } case PPC_EXC_FLOAT_ASSIST: { // .288 gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr & 0x87c0ffff; break; } case PPC_EXC_MACHINE_CHECK: { // .270 if (!(gCPU.msr & MSR_ME)) { PPC_EXC_ERR("machine check exception and MSR[ME]=0.\n"); } gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | MSR_RI; break; } case PPC_EXC_TRACE2: { // .286 gCPU.srr[0] = gCPU.pc; gCPU.srr[1] = gCPU.msr & 0x87c0ffff; break; } default: PPC_EXC_ERR("unknown\n"); return false; } ppc_mmu_tlb_invalidate(); gCPU.msr = 0; gCPU.npc = type; return true; } #endif void ppc_cpu_raise_ext_exception() { ppc_cpu_atomic_raise_ext_exception(); } void ppc_cpu_cancel_ext_exception() { ppc_cpu_atomic_cancel_ext_exception(); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/io.h���������������������������������������������������������������0000644�0001750�0000144�00000012223�10702130757�016007� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * io.h * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __IO_IO_H__ #define __IO_IO_H__ /* #include "system/types.h" #include <stdlib.h> #include <string.h> #include "cpu/cpu.h" #include "cpu/debug.h" #include "cpu/mem.h" #include "io.h" #include "io/graphic/gcard.h" #include "io/pic/pic.h" #include "io/pci/pci.h" #include "io/cuda/cuda.h" #include "io/nvram/nvram.h" #include "debug/tracers.h" */ #include "types.h" #define IO_MEM_ACCESS_OK 0 #define IO_MEM_ACCESS_EXC 1 #define IO_MEM_ACCESS_FATAL 2 static inline int io_mem_write(uint32 addr, uint32 data, int size) { IO_CORE_WARN("no one is responsible for address %08x (write: %08x from %08x)\n", addr, data, ppc_cpu_get_pc(0)); SINGLESTEP(""); ppc_machine_check_exception(); return IO_MEM_ACCESS_EXC; } static inline int io_mem_read(uint32 addr, uint32 *data, int size) { #if 0 if (addr >= IO_GCARD_FRAMEBUFFER_PA_START && addr < IO_GCARD_FRAMEBUFFER_PA_END) { gcard_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_PCI_PA_START && addr < IO_PCI_PA_END) { pci_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_PIC_PA_START && addr < IO_PIC_PA_END) { pic_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_CUDA_PA_START && addr < IO_CUDA_PA_END) { cuda_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_NVRAM_PA_START && addr < IO_NVRAM_PA_END) { nvram_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr == 0xff000004) { // wtf? data = 1; return IO_MEM_ACCESS_OK; } // PCI and ISA must be checked at last if (addr >= IO_PCI_DEVICE_PA_START && addr < IO_PCI_DEVICE_PA_END) { pci_read_device(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_ISA_PA_START && addr < IO_ISA_PA_END) { /* * should raise exception here... * but linux dont like this */ isa_read(addr, data, size); return IO_MEM_ACCESS_OK; /*if (isa_read(addr, data, size)) { return IO_MEM_ACCESS_OK; } else { ppc_exception(PPC_EXC_MACHINE_CHECK); return IO_MEM_ACCESS_EXC; }*/ } IO_CORE_WARN("no one is responsible for address %08x (read from %08x)\n", addr, ppc_cpu_get_pc(0)); SINGLESTEP(""); ppc_machine_check_exception(); #endif return IO_MEM_ACCESS_EXC; } static inline int io_mem_write64(uint32 addr, uint64 data) { #if 0 if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_write64(addr, data); return IO_MEM_ACCESS_OK; } IO_CORE_ERR("no one is responsible for address %08x (write64: %016q from %08x)\n", addr, &data, ppc_cpu_get_pc(0)); #endif return IO_MEM_ACCESS_FATAL; } static inline int io_mem_read64(uint32 addr, uint64 *data) { #if 0 if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_read64(addr, data); return IO_MEM_ACCESS_OK; } #endif IO_CORE_ERR("no one is responsible for address %08x (read64 from %08x)\n", addr, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static inline int io_mem_write128(uint32 addr, uint128 *data) { #if 0 if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_write128(addr, data); return IO_MEM_ACCESS_OK; } #endif IO_CORE_ERR("no one is responsible for address %08x (write128: %016q%016q from %08x)\n", addr, data->h, data->l, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static inline int io_mem_write128_native(uint32 addr, uint128 *data) { #if 0 if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_write128_native(addr, data); return IO_MEM_ACCESS_OK; } #endif IO_CORE_ERR("no one is responsible for address %08x (write128: %016q%016q from %08x)\n", addr, data->h, data->l, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static inline int io_mem_read128(uint32 addr, uint128 *data) { #if 0 if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_read128(addr, data); return IO_MEM_ACCESS_OK; } #endif IO_CORE_ERR("no one is responsible for address %08x (read128 from %08x)\n", addr, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static inline int io_mem_read128_native(uint32 addr, uint128 *data) { #if 0 if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_read128_native(addr, data); return IO_MEM_ACCESS_OK; } #endif IO_CORE_ERR("no one is responsible for address %08x (read128 from %08x)\n", addr, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } void io_init(); void io_done(); void io_init_config(); #endif �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_opc.c����������������������������������������������������������0000644�0001750�0000144�00000061662�10711004726�017025� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_opc.cc * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * Copyright (C) 2004 Dainel Foesch (dfoesch@cs.nmsu.edu) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #include "debug/tracers.h" #include "cpu/debug.h" #include "io/pic/pic.h" #include "info.h" */ #include <stdio.h> #include "ppc_cpu.h" #include "ppc_exc.h" #include "ppc_e500_exc.h" #include "ppc_mmu.h" #include "ppc_opc.h" #include "ppc_dec.h" #include "tracers.h" #include "debug.h" void ppc_set_msr(uint32 newmsr) { /* if ((newmsr & MSR_EE) && !(gCPU.msr & MSR_EE)) { if (pic_check_interrupt()) { gCPU.exception_pending = true; gCPU.ext_exception = true; } }*/ ppc_mmu_tlb_invalidate(); #ifndef PPC_CPU_ENABLE_SINGLESTEP if (newmsr & MSR_SE) { PPC_CPU_WARN("MSR[SE] (singlestep enable) set, but compiled w/o SE support.\n"); } #else gCPU.singlestep_ignore = true; #endif if (newmsr & PPC_CPU_UNSUPPORTED_MSR_BITS) { PPC_CPU_ERR("unsupported bits in MSR set: %08x @%08x\n", newmsr & PPC_CPU_UNSUPPORTED_MSR_BITS, gCPU.pc); } if (newmsr & MSR_POW) { // doze(); newmsr &= ~MSR_POW; } gCPU.msr = newmsr; } /* * bx Branch * .435 */ void ppc_opc_bx() { uint32 li; PPC_OPC_TEMPL_I(gCPU.current_opc, li); if (!(gCPU.current_opc & PPC_OPC_AA)) { li += gCPU.pc; } if (gCPU.current_opc & PPC_OPC_LK) { gCPU.lr = gCPU.pc + 4; } gCPU.npc = li; } /* * bcx Branch Conditional * .436 */ void ppc_opc_bcx() { uint32 BO, BI, BD; PPC_OPC_TEMPL_B(gCPU.current_opc, BO, BI, BD); if (!(BO & 4)) { gCPU.ctr--; } bool bo2 = ((BO & 2)?1:0); bool bo8 = ((BO & 8)?1:0); // branch condition true bool cr = ((gCPU.cr & (1<<(31-BI)))?1:0) ; if (((BO & 4) || ((gCPU.ctr!=0) ^ bo2)) && ((BO & 16) || (!(cr ^ bo8)))) { if (!(gCPU.current_opc & PPC_OPC_AA)) { BD += gCPU.pc; } if (gCPU.current_opc & PPC_OPC_LK) { gCPU.lr = gCPU.pc + 4; } gCPU.npc = BD; } //fprintf(stderr,"in %s,BO=0x%x,BI=0x%x,BD=0x%x,cr=0x%x,cr^bo8=0x%x,ctr=0x%x,pc=0x%x\n",__FUNCTION__,BO,BI,BD,gCPU.cr,(cr ^ bo8),gCPU.ctr, gCPU.pc); } /* * bcctrx Branch Conditional to Count Register * .438 */ void ppc_opc_bcctrx() { uint32 BO, BI, BD; PPC_OPC_TEMPL_XL(gCPU.current_opc, BO, BI, BD); PPC_OPC_ASSERT(BD==0); PPC_OPC_ASSERT(!(BO & 2)); bool bo8 = ((BO & 8)?1:0); bool cr = ((gCPU.cr & (1<<(31-BI)))?1:0); if ((BO & 16) || (!(cr ^ bo8))) { if (gCPU.current_opc & PPC_OPC_LK) { gCPU.lr = gCPU.pc + 4; } gCPU.npc = gCPU.ctr & 0xfffffffc; } //fprintf(stderr,"in %s,BO=0x%x,BI=0x%x,BD=0x%x,cr=0x%x,cr^bo8=0x%x,ctr=0x%x,pc=0x%x,npc=0x%x\n",__FUNCTION__,BO,BI,BD,gCPU.cr,(cr ^ bo8),gCPU.ctr, gCPU.pc,gCPU.npc); } /* * bclrx Branch Conditional to Link Register * .440 */ void ppc_opc_bclrx() { uint32 BO, BI, BD; PPC_OPC_TEMPL_XL(gCPU.current_opc, BO, BI, BD); PPC_OPC_ASSERT(BD==0); if (!(BO & 4)) { gCPU.ctr--; } bool bo2 = ((BO & 2)?1:0); bool bo8 = ((BO & 8)?1:0); bool cr = ((gCPU.cr & (1<<(31-BI)))?1:0); if (((BO & 4) || ((gCPU.ctr!=0) ^ bo2)) && ((BO & 16) || (!(cr ^ bo8)))) { BD = gCPU.lr & 0xfffffffc; if (gCPU.current_opc & PPC_OPC_LK) { gCPU.lr = gCPU.pc + 4; } gCPU.npc = BD; } } /* * dcbf Data Cache Block Flush * .458 */ void ppc_opc_dcbf() { // NO-OP } /* * dcbi Data Cache Block Invalidate * .460 */ void ppc_opc_dcbi() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } // FIXME: check addr } /* * dcbst Data Cache Block Store * .461 */ void ppc_opc_dcbst() { // NO-OP } /* * dcbt Data Cache Block Touch * .462 */ void ppc_opc_dcbt() { // NO-OP } /* * dcbtst Data Cache Block Touch for Store * .463 */ void ppc_opc_dcbtst() { // NO-OP } /* * eciwx External Control In Word Indexed * .474 */ void ppc_opc_eciwx() { PPC_OPC_ERR("eciwx unimplemented.\n"); } /* * ecowx External Control Out Word Indexed * .476 */ void ppc_opc_ecowx() { PPC_OPC_ERR("ecowx unimplemented.\n"); } /* * eieio Enforce In-Order Execution of I/O * .478 */ void ppc_opc_eieio() { // NO-OP } /* * icbi Instruction Cache Block Invalidate * .519 */ void ppc_opc_icbi() { // NO-OP } /* * isync Instruction Synchronize * .520 */ void ppc_opc_isync() { // NO-OP } static uint32 ppc_cmp_and_mask[8] = { 0xfffffff0, 0xffffff0f, 0xfffff0ff, 0xffff0fff, 0xfff0ffff, 0xff0fffff, 0xf0ffffff, 0x0fffffff, }; /* * mcrf Move Condition Register Field * .561 */ void ppc_opc_mcrf() { uint32 crD, crS, bla; PPC_OPC_TEMPL_X(gCPU.current_opc, crD, crS, bla); // FIXME: bla == 0 crD>>=2; crS>>=2; crD = 7-crD; crS = 7-crS; uint32 c = (gCPU.cr>>(crS*4)) & 0xf; gCPU.cr &= ppc_cmp_and_mask[crD]; gCPU.cr |= c<<(crD*4); } /* * mcrfs Move to Condition Register from FPSCR * .562 */ void ppc_opc_mcrfs() { PPC_OPC_ERR("mcrfs unimplemented.\n"); } /* * mcrxr Move to Condition Register from XER * .563 */ void ppc_opc_mcrxr() { PPC_OPC_ERR("mcrxr unimplemented.\n"); } /* * mfcr Move from Condition Register * .564 */ void ppc_opc_mfcr() { int rD, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT(rA==0 && rB==0); gCPU.gpr[rD] = gCPU.cr; } /* * mffs Move from FPSCR * .565 */ void ppc_opc_mffsx() { int frD, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, frD, rA, rB); PPC_OPC_ASSERT(rA==0 && rB==0); gCPU.fpr[frD] = gCPU.fpscr; if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_OPC_ERR("mffs. unimplemented.\n"); } } /* * mfmsr Move from Machine State Register * .566 */ void ppc_opc_mfmsr() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rD, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); PPC_OPC_ASSERT((rA == 0) && (rB == 0)); gCPU.gpr[rD] = gCPU.msr; } /* * mfspr Move from Special-Purpose Register * .567 */ void ppc_opc_mfspr() { int rD, spr1, spr2; PPC_OPC_TEMPL_XO(gCPU.current_opc, rD, spr1, spr2); if (gCPU.msr & MSR_PR) { //ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); //printf("Warning, execute mfspe in user mode\n"); //return; } switch (spr2) { case 0: switch (spr1) { case 1: gCPU.gpr[rD] = gCPU.xer; return; case 8: gCPU.gpr[rD] = gCPU.lr; return; case 9: gCPU.gpr[rD] = gCPU.ctr; return; case 18: gCPU.gpr[rD] = gCPU.dsisr; return; case 19: gCPU.gpr[rD] = gCPU.dar; return; case 22: { gCPU.dec = gCPU.pdec / TB_TO_PTB_FACTOR; gCPU.gpr[rD] = gCPU.dec; return; } case 25: gCPU.gpr[rD] = gCPU.sdr1; return; case 26: gCPU.gpr[rD] = gCPU.srr[0]; return; case 27: gCPU.gpr[rD] = gCPU.srr[1]; return; } break; case 1: switch(spr1) { case 16: gCPU.gpr[rD] = e500_mmu.pid[1];return; case 29: gCPU.gpr[rD] = gCPU.dear;return; case 30: gCPU.gpr[rD] = gCPU.esr; return; } break; case 8: switch (spr1) { case 12: { /* gCPU.tb = gCPU.ptb / TB_TO_PTB_FACTOR; gCPU.gpr[rD] = gCPU.tb; */ gCPU.gpr[rD] = gCPU.tbl; return; } case 13: { /* gCPU.tb = gCPU.ptb / TB_TO_PTB_FACTOR; gCPU.gpr[rD] = gCPU.tb >> 32; */ gCPU.gpr[rD] = gCPU.tbu; return; } case 0: gCPU.gpr[rD] = gCPU.vrsave; return; case 16: gCPU.gpr[rD] = gCPU.sprg[0]; return; case 1: case 17: gCPU.gpr[rD] = gCPU.sprg[1]; return; case 2: case 18: gCPU.gpr[rD] = gCPU.sprg[2]; return; case 3: case 19: gCPU.gpr[rD] = gCPU.sprg[3]; return; case 4: case 20: gCPU.gpr[rD] = gCPU.sprg[4]; return; case 5: case 21: gCPU.gpr[rD] = gCPU.sprg[5]; return; case 6: case 22: gCPU.gpr[rD] = gCPU.sprg[6]; return; case 23: case 7: gCPU.gpr[rD] = gCPU.sprg[7]; return; case 26: gCPU.gpr[rD] = gCPU.ear; return; case 31: gCPU.gpr[rD] = gCPU.pvr; return; default: fprintf(stderr, "unknown mfspr: %i:%i\n", spr1, spr2); fprintf(stderr, "pc=0x%x\n", gCPU.pc); skyeye_exit(-1); } break; case 9: switch(spr1) { case 16:gCPU.gpr[rD] = gCPU.dbsr; return; case 20:gCPU.gpr[rD] = gCPU.dbcr[0]; return; case 21:gCPU.gpr[rD] = gCPU.dbcr[1]; return; case 22:gCPU.gpr[rD] = gCPU.dbcr[2]; return; case 28:gCPU.gpr[rD] = gCPU.dac[0]; return; case 29:gCPU.gpr[rD] = gCPU.dac[1]; return; } break; case 16: switch (spr1) { case 0: gCPU.gpr[rD] = gCPU.spefscr; return; case 16: gCPU.gpr[rD] = gCPU.ibatu[0]; return; case 17: gCPU.gpr[rD] = gCPU.ibatl[0]; return; case 18: gCPU.gpr[rD] = gCPU.ibatu[1]; return; case 19: gCPU.gpr[rD] = gCPU.ibatl[1]; return; case 20: gCPU.gpr[rD] = gCPU.ibatu[2]; return; case 21: gCPU.gpr[rD] = gCPU.ibatl[2]; return; case 22: gCPU.gpr[rD] = gCPU.ibatu[3]; return; case 23: gCPU.gpr[rD] = gCPU.ibatl[3]; return; case 24: gCPU.gpr[rD] = gCPU.dbatu[0]; return; case 25: gCPU.gpr[rD] = gCPU.dbatl[0]; return; case 26: gCPU.gpr[rD] = gCPU.dbatu[1]; return; case 27: gCPU.gpr[rD] = gCPU.dbatl[1]; return; case 28: gCPU.gpr[rD] = gCPU.dbatu[2]; return; case 29: gCPU.gpr[rD] = gCPU.dbatl[2]; return; case 30: gCPU.gpr[rD] = gCPU.dbatu[3]; return; case 31: gCPU.gpr[rD] = gCPU.dbatl[3]; return; } break; case 19: switch(spr1) { case 16: gCPU.gpr[rD] = e500_mmu.mas[0]; return; case 17: gCPU.gpr[rD] = e500_mmu.mas[1]; return; case 18: gCPU.gpr[rD] = e500_mmu.mas[2]; return; case 19: gCPU.gpr[rD] = e500_mmu.mas[3]; return; case 20: gCPU.gpr[rD] = e500_mmu.mas[4]; return; case 22: gCPU.gpr[rD] = e500_mmu.mas[6]; return; case 25: gCPU.gpr[rD] = e500_mmu.pid[1]; return; case 26: gCPU.gpr[rD] = e500_mmu.pid[2]; return; } break; case 21: switch(spr1) { case 17:gCPU.gpr[rD] = e500_mmu.tlbcfg[1]; return; } break; case 29: switch (spr1) { case 16: gCPU.gpr[rD] = 0; return; case 17: gCPU.gpr[rD] = 0; return; case 18: gCPU.gpr[rD] = 0; return; case 24: gCPU.gpr[rD] = 0; return; case 25: gCPU.gpr[rD] = 0; return; case 26: gCPU.gpr[rD] = 0; return; case 28: gCPU.gpr[rD] = 0; return; case 29: gCPU.gpr[rD] = 0; return; case 30: gCPU.gpr[rD] = 0; return; } break; case 31: switch (spr1) { case 16: // PPC_OPC_WARN("read from spr %d:%d (HID0) not supported!\n", spr1, spr2); gCPU.gpr[rD] = gCPU.hid[0]; return; case 17: PPC_OPC_WARN("read from spr %d:%d (HID1) not supported!\n", spr1, spr2); gCPU.gpr[rD] = gCPU.hid[1]; return; case 18: gCPU.gpr[rD] = 0; return; case 19: gCPU.gpr[rD] = gCPU.l1csr[1]; return; case 20: gCPU.gpr[rD] = gCPU.iac[0]; return; case 21: gCPU.gpr[rD] = 0; return; case 22: gCPU.gpr[rD] = 0; return; case 23: gCPU.gpr[rD] = 0; return; case 25: PPC_OPC_WARN("read from spr %d:%d (L2CR) not supported! (from %08x)\n", spr1, spr2, gCPU.pc); gCPU.gpr[rD] = 0; return; case 27: PPC_OPC_WARN("read from spr %d:%d (ICTC) not supported!\n", spr1, spr2); gCPU.gpr[rD] = 0; return; case 28: // PPC_OPC_WARN("read from spr %d:%d (THRM1) not supported!\n", spr1, spr2); gCPU.gpr[rD] = 0; return; case 29: // PPC_OPC_WARN("read from spr %d:%d (THRM2) not supported!\n", spr1, spr2); gCPU.gpr[rD] = 0; return; case 30: // PPC_OPC_WARN("read from spr %d:%d (THRM3) not supported!\n", spr1, spr2); gCPU.gpr[rD] = 0; return; case 31: // PPC_OPC_WARN("read from spr %d:%d (???) not supported!\n", spr1, spr2); gCPU.gpr[rD] = 0; return; } break; } fprintf(stderr, "unknown mfspr: %i:%i\n", spr1, spr2); fprintf(stderr, "pc=0x%x\n", gCPU.pc); skyeye_exit(-1); //SINGLESTEP("invalid mfspr\n"); } /* * mfsr Move from Segment Register * .570 */ void ppc_opc_mfsr() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rD, SR, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, SR, rB); // FIXME: check insn gCPU.gpr[rD] = gCPU.sr[SR & 0xf]; } /* * mfsrin Move from Segment Register Indirect * .572 */ void ppc_opc_mfsrin() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rD, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, rA, rB); // FIXME: check insn gCPU.gpr[rD] = gCPU.sr[gCPU.gpr[rB] >> 28]; } /* * mftb Move from Time Base * .574 */ void ppc_opc_mftb() { int rD, spr1, spr2; PPC_OPC_TEMPL_X(gCPU.current_opc, rD, spr1, spr2); switch (spr2) { case 8: switch (spr1) { case 12: { gCPU.tb = gCPU.ptb / TB_TO_PTB_FACTOR; gCPU.gpr[rD] = gCPU.tb; return; } case 13: { gCPU.tb = gCPU.ptb / TB_TO_PTB_FACTOR; gCPU.gpr[rD] = gCPU.tb >> 32; return; } } break; } } /* * mtcrf Move to Condition Register Fields * .576 */ void ppc_opc_mtcrf() { int rS; uint32 crm; uint32 CRM; PPC_OPC_TEMPL_XFX(gCPU.current_opc, rS, crm); CRM = ((crm&0x80)?0xf0000000:0)|((crm&0x40)?0x0f000000:0)|((crm&0x20)?0x00f00000:0)|((crm&0x10)?0x000f0000:0)| ((crm&0x08)?0x0000f000:0)|((crm&0x04)?0x00000f00:0)|((crm&0x02)?0x000000f0:0)|((crm&0x01)?0x0000000f:0); gCPU.cr = (gCPU.gpr[rS] & CRM) | (gCPU.cr & ~CRM); } /* * mtfsb0x Move to FPSCR Bit 0 * .577 */ void ppc_opc_mtfsb0x() { int crbD, n1, n2; PPC_OPC_TEMPL_X(gCPU.current_opc, crbD, n1, n2); if (crbD != 1 && crbD != 2) { gCPU.fpscr &= ~(1<<(31-crbD)); } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_OPC_ERR("mtfsb0. unimplemented.\n"); } } /* * mtfsb1x Move to FPSCR Bit 1 * .578 */ void ppc_opc_mtfsb1x() { int crbD, n1, n2; PPC_OPC_TEMPL_X(gCPU.current_opc, crbD, n1, n2); if (crbD != 1 && crbD != 2) { gCPU.fpscr |= 1<<(31-crbD); } if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_OPC_ERR("mtfsb1. unimplemented.\n"); } } /* * mtfsfx Move to FPSCR Fields * .579 */ void ppc_opc_mtfsfx() { int frB; uint32 fm, FM; PPC_OPC_TEMPL_XFL(gCPU.current_opc, frB, fm); FM = ((fm&0x80)?0xf0000000:0)|((fm&0x40)?0x0f000000:0)|((fm&0x20)?0x00f00000:0)|((fm&0x10)?0x000f0000:0)| ((fm&0x08)?0x0000f000:0)|((fm&0x04)?0x00000f00:0)|((fm&0x02)?0x000000f0:0)|((fm&0x01)?0x0000000f:0); gCPU.fpscr = (gCPU.fpr[frB] & FM) | (gCPU.fpscr & ~FM); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_OPC_ERR("mtfsf. unimplemented.\n"); } } /* * mtfsfix Move to FPSCR Field Immediate * .580 */ void ppc_opc_mtfsfix() { int crfD, n1; uint32 imm; PPC_OPC_TEMPL_X(gCPU.current_opc, crfD, n1, imm); crfD >>= 2; imm >>= 1; crfD = 7-crfD; gCPU.fpscr &= ppc_cmp_and_mask[crfD]; gCPU.fpscr |= imm<<(crfD*4); if (gCPU.current_opc & PPC_OPC_Rc) { // update cr1 flags PPC_OPC_ERR("mtfsfi. unimplemented.\n"); } } /* * mtmsr Move to Machine State Register * .581 */ void ppc_opc_mtmsr() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); PPC_OPC_ASSERT((rA == 0) && (rB == 0)); ppc_set_msr(gCPU.gpr[rS]); } /* * mtspr Move to Special-Purpose Register * .584 */ void ppc_opc_mtspr() { int rS, spr1, spr2; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, spr1, spr2); //fprintf(stderr, "In %s, opc=0x%x,spr1=%d,spr2=%d\n", __FUNCTION__, gCPU.current_opc, spr1, spr2); switch (spr2) { case 0: switch (spr1) { case 1: gCPU.xer = gCPU.gpr[rS]; return; case 8: gCPU.lr = gCPU.gpr[rS]; return; case 9: gCPU.ctr = gCPU.gpr[rS]; return; } break; case 8: //altivec makes this register unpriviledged if (spr1 == 0) { gCPU.vrsave = gCPU.gpr[rS]; return; } switch(spr1){ case 28: gCPU.tbl = gCPU.gpr[rS]; return; case 29: gCPU.tbu = gCPU.gpr[rS]; return; } break; } if (gCPU.msr & MSR_PR) { // ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); //printf("Warning: execute mtspr in user mode\n"); //return; } switch (spr2) { case 0: switch (spr1) { /* case 18: gCPU.gpr[rD] = gCPU.dsisr; return; case 19: gCPU.gpr[rD] = gCPU.dar; return;*/ case 22: { gCPU.dec = gCPU.gpr[rS]; gCPU.pdec = gCPU.dec; gCPU.pdec *= TB_TO_PTB_FACTOR; return; } case 25: if (!ppc_mmu_set_sdr1(gCPU.gpr[rS], true)) { PPC_OPC_ERR("cannot set sdr1\n"); } return; case 26: gCPU.srr[0] = gCPU.gpr[rS]; return; case 27: gCPU.srr[1] = gCPU.gpr[rS]; return; } break; case 1: switch (spr1) { case 26:gCPU.csrr[0] = gCPU.gpr[rS];return; case 27:gCPU.csrr[1] = gCPU.gpr[rS];return; case 29:gCPU.dear = gCPU.gpr[rS];return; case 30:gCPU.esr = gCPU.gpr[rS];return; case 31:gCPU.ivpr = gCPU.gpr[rS];return; } case 8: switch (spr1) { case 16: gCPU.sprg[0] = gCPU.gpr[rS]; return; case 17: gCPU.sprg[1] = gCPU.gpr[rS]; return; case 18: gCPU.sprg[2] = gCPU.gpr[rS]; return; case 19: gCPU.sprg[3] = gCPU.gpr[rS]; return; case 20: gCPU.sprg[4] = gCPU.gpr[rS]; return; case 21: gCPU.sprg[5] = gCPU.gpr[rS]; return; case 22: gCPU.sprg[6] = gCPU.gpr[rS]; return; case 23: gCPU.sprg[7] = gCPU.gpr[rS]; return; /* case 26: gCPU.gpr[rD] = gCPU.ear; return; case 31: gCPU.gpr[rD] = gCPU.pvr; return;*/ } break; case 9: switch (spr1) { case 16:gCPU.dbsr = gCPU.gpr[rS]; return; case 20:gCPU.dbcr[0] = gCPU.gpr[rS]; return; case 21:gCPU.dbcr[1] = gCPU.gpr[rS]; return; case 22:gCPU.dbcr[2] = gCPU.gpr[rS]; return; case 28:gCPU.dac[0] = gCPU.gpr[rS]; return; case 29:gCPU.dac[1] = gCPU.gpr[rS]; return; } break; case 10: switch (spr1){ case 16: /* W1C, write one to clear */ gCPU.tsr &= ~(gCPU.tsr & gCPU.gpr[rS]) ; return; case 20:gCPU.tcr = gCPU.gpr[rS];return; } break; case 12: if(spr1 >= 16 && spr1 < 32){ gCPU.ivor[spr1 - 16] = gCPU.gpr[rS]; return; } switch (spr1){ } break; case 16: switch (spr1) { case 0: gCPU.spefscr = gCPU.gpr[rS]; return; case 16: gCPU.ibatu[0] = gCPU.gpr[rS]; gCPU.ibat_bl17[0] = ~(BATU_BL(gCPU.ibatu[0])<<17); return; case 17: gCPU.ibatl[0] = gCPU.gpr[rS]; return; case 18: gCPU.ibatu[1] = gCPU.gpr[rS]; gCPU.ibat_bl17[1] = ~(BATU_BL(gCPU.ibatu[1])<<17); return; case 19: gCPU.ibatl[1] = gCPU.gpr[rS]; return; case 20: gCPU.ibatu[2] = gCPU.gpr[rS]; gCPU.ibat_bl17[2] = ~(BATU_BL(gCPU.ibatu[2])<<17); return; case 21: gCPU.ibatl[2] = gCPU.gpr[rS]; return; case 22: gCPU.ibatu[3] = gCPU.gpr[rS]; gCPU.ibat_bl17[3] = ~(BATU_BL(gCPU.ibatu[3])<<17); return; case 23: gCPU.ibatl[3] = gCPU.gpr[rS]; return; case 24: gCPU.dbatu[0] = gCPU.gpr[rS]; gCPU.dbat_bl17[0] = ~(BATU_BL(gCPU.dbatu[0])<<17); return; case 25: gCPU.dbatl[0] = gCPU.gpr[rS]; return; case 26: gCPU.dbatu[1] = gCPU.gpr[rS]; gCPU.dbat_bl17[1] = ~(BATU_BL(gCPU.dbatu[1])<<17); return; case 27: gCPU.dbatl[1] = gCPU.gpr[rS]; return; case 28: gCPU.dbatu[2] = gCPU.gpr[rS]; gCPU.dbat_bl17[2] = ~(BATU_BL(gCPU.dbatu[2])<<17); return; case 29: gCPU.dbatl[2] = gCPU.gpr[rS]; return; case 30: gCPU.dbatu[3] = gCPU.gpr[rS]; gCPU.dbat_bl17[3] = ~(BATU_BL(gCPU.dbatu[3])<<17); return; case 31: gCPU.dbatl[3] = gCPU.gpr[rS]; return; } break; case 17: switch(spr1){ case 26: gCPU.mcsrr[0] = gCPU.gpr[rS]; return; case 27: gCPU.mcsrr[1] = gCPU.gpr[rS]; return; case 28: gCPU.mcsr = gCPU.gpr[rS]; return; } break; case 19: switch(spr1){ case 16: e500_mmu.mas[0] = gCPU.gpr[rS]; return; case 17: e500_mmu.mas[1] = gCPU.gpr[rS]; return; case 18: e500_mmu.mas[2] = gCPU.gpr[rS]; return; case 19: e500_mmu.mas[3] = gCPU.gpr[rS]; return; case 20: e500_mmu.mas[4] = gCPU.gpr[rS]; return; case 22: e500_mmu.mas[6] = gCPU.gpr[rS]; return; case 25: e500_mmu.pid[1] = gCPU.gpr[rS]; return; case 26: e500_mmu.pid[2] = gCPU.gpr[rS]; return; } break; case 29: switch(spr1) { case 17: return; case 24: return; case 25: return; case 26: return; } case 31: switch (spr1) { case 16: // PPC_OPC_WARN("write(%08x) to spr %d:%d (HID0) not supported! @%08x\n", gCPU.gpr[rS], spr1, spr2, gCPU.pc); gCPU.hid[0] = gCPU.gpr[rS]; return; case 17: return; case 18: PPC_OPC_ERR("write(%08x) to spr %d:%d (IABR) not supported!\n", gCPU.gpr[rS], spr1, spr2); return; case 19: gCPU.l1csr[1] = gCPU.gpr[rS]; return; case 20: gCPU.iac[0] = gCPU.gpr[rS]; return; case 21: PPC_OPC_ERR("write(%08x) to spr %d:%d (DABR) not supported!\n", gCPU.gpr[rS], spr1, spr2); return; case 27: PPC_OPC_WARN("write(%08x) to spr %d:%d (ICTC) not supported!\n", gCPU.gpr[rS], spr1, spr2); return; case 28: // PPC_OPC_WARN("write(%08x) to spr %d:%d (THRM1) not supported!\n", gCPU.gpr[rS], spr1, spr2); return; case 29: // PPC_OPC_WARN("write(%08x) to spr %d:%d (THRM2) not supported!\n", gCPU.gpr[rS], spr1, spr2); return; case 30: // PPC_OPC_WARN("write(%08x) to spr %d:%d (THRM3) not supported!\n", gCPU.gpr[rS], spr1, spr2); return; case 31: return; } } fprintf(stderr, "unknown mtspr: %i:%i\n", spr1, spr2); fprintf(stderr, "pc=0x%x\n",gCPU.pc); skyeye_exit(-1); } /* * mtsr Move to Segment Register * .587 */ void ppc_opc_mtsr() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rS, SR, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, SR, rB); // FIXME: check insn gCPU.sr[SR & 0xf] = gCPU.gpr[rS]; } /* * mtsrin Move to Segment Register Indirect * .591 */ void ppc_opc_mtsrin() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: check insn gCPU.sr[gCPU.gpr[rB] >> 28] = gCPU.gpr[rS]; } /* * rfi Return from Interrupt * .607 */ void ppc_opc_rfi() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } ppc_set_msr(gCPU.srr[1] & MSR_RFI_SAVE_MASK); gCPU.npc = gCPU.srr[0] & 0xfffffffc; } /* * sc System Call * .621 */ //#include "io/graphic/gcard.h" void ppc_opc_sc() { if (gCPU.gpr[3] == 0x113724fa && gCPU.gpr[4] == 0x77810f9b) { //gcard_osi(0); return; } ppc_exception(SYSCALL ,0 ,0); } /* * sync Synchronize * .672 */ void ppc_opc_sync() { // NO-OP } /* * tlbie Translation Lookaside Buffer Invalidate Entry * .676 */ void ppc_opc_tlbia() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: check rS.. for 0 ppc_mmu_tlb_invalidate(); } /* * tlbie Translation Lookaside Buffer Invalidate All * .676 */ void ppc_opc_tlbie() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: check rS.. for 0 ppc_mmu_tlb_invalidate(); } /* * tlbsync Translation Lookaside Buffer Syncronize * .677 */ void ppc_opc_tlbsync() { if (gCPU.msr & MSR_PR) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_PRIV, 0); return; } int rS, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, rS, rA, rB); // FIXME: check rS.. for 0 ppc_mmu_tlb_invalidate(); } /* * tw Trap Word * .678 */ void ppc_opc_tw() { int TO, rA, rB; PPC_OPC_TEMPL_X(gCPU.current_opc, TO, rA, rB); uint32 a = gCPU.gpr[rA]; uint32 b = gCPU.gpr[rB]; if (((TO & 16) && ((sint32)a < (sint32)b)) || ((TO & 8) && ((sint32)a > (sint32)b)) || ((TO & 4) && (a == b)) || ((TO & 2) && (a < b)) || ((TO & 1) && (a > b))) { ppc_exception(PPC_EXC_PROGRAM, PPC_EXC_PROGRAM_TRAP, 0); } } /* * twi Trap Word Immediate * .679 */ void ppc_opc_twi() { int TO, rA; uint32 imm; PPC_OPC_TEMPL_D_SImm(gCPU.current_opc, TO, rA, imm); uint32 a = gCPU.gpr[rA]; if (((TO & 16) && ((sint32)a < (sint32)imm)) || ((TO & 8) && ((sint32)a > (sint32)imm)) || ((TO & 4) && (a == imm)) || ((TO & 2) && (a < imm)) || ((TO & 1) && (a > imm))) { ppc_exception(PROG, PPC_EXC_PROGRAM_TRAP, 0); } } /* dcba Data Cache Block Allocate * .??? */ void ppc_opc_dcba() { /* NO-OP */ } ������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_irq.h����������������������������������������������������������0000644�0001750�0000144�00000015302�10711400073�017025� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _ASM_POWERPC_IRQ_H #define _ASM_POWERPC_IRQ_H /* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ /* * These constants are used for passing information about interrupt * signal polarity and level/edge sensing to the low-level PIC chip * drivers. */ #define IRQ_SENSE_MASK 0x1 #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */ #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */ #define IRQ_POLARITY_MASK 0x2 #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */ #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */ /* These values must be zero-based and map 1:1 with the SIU configuration. * They are used throughout the 8xx I/O subsystem to generate * interrupt masks, flags, and other control patterns. This is why the * current kernel assumption of the 8259 as the base controller is such * a pain in the butt. */ #define SIU_IRQ0 (0) /* Highest priority */ #define SIU_LEVEL0 (1) #define SIU_IRQ1 (2) #define SIU_LEVEL1 (3) #define SIU_IRQ2 (4) #define SIU_LEVEL2 (5) #define SIU_IRQ3 (6) #define SIU_LEVEL3 (7) #define SIU_IRQ4 (8) #define SIU_LEVEL4 (9) #define SIU_IRQ5 (10) #define SIU_LEVEL5 (11) #define SIU_IRQ6 (12) #define SIU_LEVEL6 (13) #define SIU_IRQ7 (14) #define SIU_LEVEL7 (15) #define MPC8xx_INT_FEC1 SIU_LEVEL1 #define MPC8xx_INT_FEC2 SIU_LEVEL3 #define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1) #define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2) #define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3) #define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4) #define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1) #define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2) /* Internal IRQs on MPC85xx OpenPIC */ #ifndef MPC85xx_OPENPIC_IRQ_OFFSET #ifdef CONFIG_CPM2 #define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) #else #define MPC85xx_OPENPIC_IRQ_OFFSET 0 #endif #endif #define CPM_IRQ_OFFSET 0 /* Not all of these exist on all MPC85xx implementations */ #define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) /* The 12 external interrupt lines */ #define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) #define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) /* CPM related interrupts */ #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) #define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) #endif /* _ASM_IRQ_H */ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_dec.c����������������������������������������������������������0000644�0001750�0000144�00000051663�10711400073�016772� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_dec.cc * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * Portions Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nmsu.edu) * Portions Copyright (C) 2004 Apple Computer, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #include "cstring" #include "system/types.h" #include "cpu/debug.h" #include "cpu/cpu.h" */ #include <stdio.h> #include "types.h" #include "tracers.h" #include "ppc_alu.h" #include "ppc_cpu.h" #include "ppc_dec.h" #include "ppc_exc.h" #include "ppc_fpu.h" #include "ppc_vec.h" #include "ppc_mmu.h" #include "ppc_opc.h" //#include "io/prom/promosi.h" static void ppc_opc_invalid() { /* FIXME by Michael.Kang if (gCPU.pc == gPromOSIEntry && gCPU.current_opc == PROM_MAGIC_OPCODE) { call_prom_osi(); return; }*/ if (gCPU.current_opc == 0x00333301) { // memset(r3, r4, r5) uint32 dest = gCPU.gpr[3]; uint32 c = gCPU.gpr[4]; uint32 size = gCPU.gpr[5]; if (dest & 0xfff) { byte *dst; ppc_direct_effective_memory_handle(dest, dst); uint32 a = 4096 - (dest & 0xfff); memset(dst, c, a); size -= a; dest += a; } while (size >= 4096) { byte *dst; ppc_direct_effective_memory_handle(dest, dst); memset(dst, c, 4096); dest += 4096; size -= 4096; } if (size) { byte *dst; ppc_direct_effective_memory_handle(dest, dst); memset(dst, c, size); } gCPU.pc = gCPU.npc; return; } if (gCPU.current_opc == 0x00333302) { // memcpy uint32 dest = gCPU.gpr[3]; uint32 src = gCPU.gpr[4]; uint32 size = gCPU.gpr[5]; byte *d, *s; ppc_direct_effective_memory_handle(dest, d); ppc_direct_effective_memory_handle(src, s); while (size--) { if (!(dest & 0xfff)) ppc_direct_effective_memory_handle(dest, d); if (!(src & 0xfff)) ppc_direct_effective_memory_handle(src, s); *d = *s; src++; dest++; d++; s++; } gCPU.pc = gCPU.npc; return; } fprintf(stderr, "[PPC/DEC] Bad opcode: %08x (%u:%u)\n", gCPU.current_opc, PPC_OPC_MAIN(gCPU.current_opc), PPC_OPC_EXT(gCPU.current_opc)); fprintf(stderr, "pc=0x%x\n",gCPU.pc); skyeye_exit(-1); //SINGLESTEP("unknown instruction\n"); } // main opcode 19 static void ppc_opc_group_1() { uint32 ext = PPC_OPC_EXT(gCPU.current_opc); //printf("DBG:in %s,before exec pc=0x%x,opc=0x%x,ext=0x%x\n", __FUNCTION__, gCPU.pc, gCPU.current_opc, ext); if (ext & 1) { // crxxx if (ext <= 225) { switch (ext) { case 33: ppc_opc_crnor(); return; case 129: ppc_opc_crandc(); return; case 193: ppc_opc_crxor(); return; case 225: ppc_opc_crnand(); return; } } else { switch (ext) { case 257: ppc_opc_crand(); return; case 289: ppc_opc_creqv(); return; case 417: ppc_opc_crorc(); return; case 449: ppc_opc_cror(); return; } } } else if (ext & (1<<9)) { // bcctrx if (ext == 528) { ppc_opc_bcctrx(); return; } } else { switch (ext) { case 16: ppc_opc_bclrx(); return; case 0: ppc_opc_mcrf(); return; case 50: ppc_opc_rfi(); return; case 150: ppc_opc_isync(); return; } } ppc_opc_invalid(); } ppc_opc_function ppc_opc_table_group2[1015]; //ppc_opc_function * ppc_opc_table_group2; // main opcode 31 static void ppc_opc_init_group2() { uint i; //ppc_opc_table_group2 = (ppc_opc_function *)malloc(sizeof(ppc_opc_function) * 1015); for (i=0; i<(sizeof ppc_opc_table_group2 / sizeof ppc_opc_table_group2[0]); i++) { ppc_opc_table_group2[i] = ppc_opc_invalid; } ppc_opc_table_group2[0] = ppc_opc_cmp; ppc_opc_table_group2[4] = ppc_opc_tw; ppc_opc_table_group2[8] = ppc_opc_subfcx;//+ ppc_opc_table_group2[10] = ppc_opc_addcx;//+ ppc_opc_table_group2[11] = ppc_opc_mulhwux; ppc_opc_table_group2[15] = ppc_opc_isel; ppc_opc_table_group2[19] = ppc_opc_mfcr; ppc_opc_table_group2[20] = ppc_opc_lwarx; ppc_opc_table_group2[23] = ppc_opc_lwzx; ppc_opc_table_group2[24] = ppc_opc_slwx; ppc_opc_table_group2[26] = ppc_opc_cntlzwx; ppc_opc_table_group2[28] = ppc_opc_andx; ppc_opc_table_group2[32] = ppc_opc_cmpl; ppc_opc_table_group2[40] = ppc_opc_subfx; ppc_opc_table_group2[47] = ppc_opc_iselgt; ppc_opc_table_group2[54] = ppc_opc_dcbst; ppc_opc_table_group2[55] = ppc_opc_lwzux; ppc_opc_table_group2[60] = ppc_opc_andcx; ppc_opc_table_group2[75] = ppc_opc_mulhwx; ppc_opc_table_group2[79] = ppc_opc_iseleq; ppc_opc_table_group2[83] = ppc_opc_mfmsr; ppc_opc_table_group2[86] = ppc_opc_dcbf; ppc_opc_table_group2[87] = ppc_opc_lbzx; ppc_opc_table_group2[104] = ppc_opc_negx; ppc_opc_table_group2[119] = ppc_opc_lbzux; ppc_opc_table_group2[124] = ppc_opc_norx; ppc_opc_table_group2[131] = ppc_opc_wrtee; ppc_opc_table_group2[136] = ppc_opc_subfex;//+ ppc_opc_table_group2[138] = ppc_opc_addex;//+ ppc_opc_table_group2[143] = ppc_opc_isel; ppc_opc_table_group2[144] = ppc_opc_mtcrf; ppc_opc_table_group2[146] = ppc_opc_mtmsr; ppc_opc_table_group2[150] = ppc_opc_stwcx_; ppc_opc_table_group2[151] = ppc_opc_stwx; ppc_opc_table_group2[163] = ppc_opc_wrteei; ppc_opc_table_group2[166] = ppc_opc_dcbtls; ppc_opc_table_group2[183] = ppc_opc_stwux; ppc_opc_table_group2[200] = ppc_opc_subfzex;//+ ppc_opc_table_group2[202] = ppc_opc_addzex;//+ ppc_opc_table_group2[207] = ppc_opc_isel; ppc_opc_table_group2[210] = ppc_opc_mtsr; ppc_opc_table_group2[215] = ppc_opc_stbx; ppc_opc_table_group2[232] = ppc_opc_subfmex;//+ ppc_opc_table_group2[234] = ppc_opc_addmex; ppc_opc_table_group2[235] = ppc_opc_mullwx;//+ ppc_opc_table_group2[242] = ppc_opc_mtsrin; ppc_opc_table_group2[246] = ppc_opc_dcbtst; ppc_opc_table_group2[247] = ppc_opc_stbux; ppc_opc_table_group2[266] = ppc_opc_addx;//+ ppc_opc_table_group2[278] = ppc_opc_dcbt; ppc_opc_table_group2[279] = ppc_opc_lhzx; ppc_opc_table_group2[284] = ppc_opc_eqvx; ppc_opc_table_group2[306] = ppc_opc_tlbie; ppc_opc_table_group2[310] = ppc_opc_eciwx; ppc_opc_table_group2[311] = ppc_opc_lhzux; ppc_opc_table_group2[316] = ppc_opc_xorx; ppc_opc_table_group2[339] = ppc_opc_mfspr; ppc_opc_table_group2[343] = ppc_opc_lhax; ppc_opc_table_group2[335] = ppc_opc_isel; ppc_opc_table_group2[370] = ppc_opc_tlbia; ppc_opc_table_group2[371] = ppc_opc_mftb; ppc_opc_table_group2[375] = ppc_opc_lhaux; ppc_opc_table_group2[407] = ppc_opc_sthx; ppc_opc_table_group2[412] = ppc_opc_orcx; ppc_opc_table_group2[438] = ppc_opc_ecowx; ppc_opc_table_group2[439] = ppc_opc_sthux; ppc_opc_table_group2[444] = ppc_opc_orx; ppc_opc_table_group2[459] = ppc_opc_divwux;//+ ppc_opc_table_group2[463] = ppc_opc_isel; ppc_opc_table_group2[467] = ppc_opc_mtspr; ppc_opc_table_group2[470] = ppc_opc_dcbi; ppc_opc_table_group2[476] = ppc_opc_nandx; ppc_opc_table_group2[491] = ppc_opc_divwx;//+ ppc_opc_table_group2[512] = ppc_opc_mcrxr; ppc_opc_table_group2[533] = ppc_opc_lswx; ppc_opc_table_group2[534] = ppc_opc_lwbrx; ppc_opc_table_group2[535] = ppc_opc_lfsx; ppc_opc_table_group2[536] = ppc_opc_srwx; ppc_opc_table_group2[566] = ppc_opc_tlbsync; ppc_opc_table_group2[567] = ppc_opc_lfsux; ppc_opc_table_group2[591] = ppc_opc_isel; ppc_opc_table_group2[595] = ppc_opc_mfsr; ppc_opc_table_group2[597] = ppc_opc_lswi; ppc_opc_table_group2[598] = ppc_opc_sync; ppc_opc_table_group2[599] = ppc_opc_lfdx; ppc_opc_table_group2[631] = ppc_opc_lfdux; ppc_opc_table_group2[659] = ppc_opc_mfsrin; ppc_opc_table_group2[661] = ppc_opc_stswx; ppc_opc_table_group2[662] = ppc_opc_stwbrx; ppc_opc_table_group2[663] = ppc_opc_stfsx; ppc_opc_table_group2[695] = ppc_opc_stfsux; ppc_opc_table_group2[725] = ppc_opc_stswi; ppc_opc_table_group2[727] = ppc_opc_stfdx; ppc_opc_table_group2[758] = ppc_opc_dcba; ppc_opc_table_group2[759] = ppc_opc_stfdux; ppc_opc_table_group2[783] = ppc_opc_isel; ppc_opc_table_group2[786] = ppc_opc_tlbivax; /* TLB invalidated virtual address indexed */ ppc_opc_table_group2[790] = ppc_opc_lhbrx; ppc_opc_table_group2[792] = ppc_opc_srawx; ppc_opc_table_group2[824] = ppc_opc_srawix; ppc_opc_table_group2[847] = ppc_opc_isel; ppc_opc_table_group2[854] = ppc_opc_eieio; ppc_opc_table_group2[911] = ppc_opc_isel; ppc_opc_table_group2[914] = ppc_opc_tlbsx; ppc_opc_table_group2[918] = ppc_opc_sthbrx; ppc_opc_table_group2[922] = ppc_opc_extshx; ppc_opc_table_group2[946] = ppc_opc_tlbrehi; ppc_opc_table_group2[954] = ppc_opc_extsbx; ppc_opc_table_group2[975] = ppc_opc_isel; ppc_opc_table_group2[943] = ppc_opc_isel; ppc_opc_table_group2[978] = ppc_opc_tlbwe; /* TLB write entry */ ppc_opc_table_group2[982] = ppc_opc_icbi; ppc_opc_table_group2[983] = ppc_opc_stfiwx; ppc_opc_table_group2[1014] = ppc_opc_dcbz; if ((ppc_cpu_get_pvr(0) & 0xffff0000) == 0x000c0000) { /* Added for Altivec support */ ppc_opc_table_group2[6] = ppc_opc_lvsl; ppc_opc_table_group2[7] = ppc_opc_lvebx; ppc_opc_table_group2[38] = ppc_opc_lvsr; ppc_opc_table_group2[39] = ppc_opc_lvehx; ppc_opc_table_group2[71] = ppc_opc_lvewx; ppc_opc_table_group2[103] = ppc_opc_lvx; ppc_opc_table_group2[135] = ppc_opc_stvebx; ppc_opc_table_group2[167] = ppc_opc_stvehx; ppc_opc_table_group2[199] = ppc_opc_stvewx; ppc_opc_table_group2[231] = ppc_opc_stvx; ppc_opc_table_group2[342] = ppc_opc_dst; ppc_opc_table_group2[359] = ppc_opc_lvxl; ppc_opc_table_group2[374] = ppc_opc_dstst; ppc_opc_table_group2[487] = ppc_opc_stvxl; ppc_opc_table_group2[822] = ppc_opc_dss; } } // main opcode 31 inline static void ppc_opc_group_2() { uint32 ext = PPC_OPC_EXT(gCPU.current_opc); /* if(gCPU.pc >= 0xfff80100 && gCPU.pc < 0xfffff000) printf("DBG:before exec pc=0x%x,opc=0x%x,ext=0x%x\n", gCPU.pc, gCPU.current_opc, ext); */ if (ext >= (sizeof ppc_opc_table_group2 / sizeof ppc_opc_table_group2[0])) { ppc_opc_invalid(); } ppc_opc_table_group2[ext](); } // main opcode 59 static void ppc_opc_group_f1() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU,0 ,0); return; } uint32 ext = PPC_OPC_EXT(gCPU.current_opc); switch (ext & 0x1f) { case 18: ppc_opc_fdivsx(); return; case 20: ppc_opc_fsubsx(); return; case 21: ppc_opc_faddsx(); return; case 22: ppc_opc_fsqrtsx(); return; case 24: ppc_opc_fresx(); return; case 25: ppc_opc_fmulsx(); return; case 28: ppc_opc_fmsubsx(); return; case 29: ppc_opc_fmaddsx(); return; case 30: ppc_opc_fnmsubsx(); return; case 31: ppc_opc_fnmaddsx(); return; } ppc_opc_invalid(); } // main opcode 63 static void ppc_opc_group_f2() { if ((gCPU.msr & MSR_FP) == 0) { ppc_exception(PPC_EXC_NO_FPU, 0 ,0); return; } uint32 ext = PPC_OPC_EXT(gCPU.current_opc); if (ext & 16) { switch (ext & 0x1f) { case 18: ppc_opc_fdivx(); return; case 20: ppc_opc_fsubx(); return; case 21: ppc_opc_faddx(); return; case 22: ppc_opc_fsqrtx(); return; case 23: ppc_opc_fselx(); return; case 25: ppc_opc_fmulx(); return; case 26: ppc_opc_frsqrtex(); return; case 28: ppc_opc_fmsubx(); return; case 29: ppc_opc_fmaddx(); return; case 30: ppc_opc_fnmsubx(); return; case 31: ppc_opc_fnmaddx(); return; } } else { switch (ext) { case 0: ppc_opc_fcmpu(); return; case 12: ppc_opc_frspx(); return; case 14: ppc_opc_fctiwx(); return; case 15: ppc_opc_fctiwzx(); return; //-- case 32: ppc_opc_fcmpo(); return; case 38: ppc_opc_mtfsb1x(); return; case 40: ppc_opc_fnegx(); return; case 64: ppc_opc_mcrfs(); return; case 70: ppc_opc_mtfsb0x(); return; case 72: ppc_opc_fmrx(); return; case 134: ppc_opc_mtfsfix(); return; case 136: ppc_opc_fnabsx(); return; case 264: ppc_opc_fabsx(); return; case 583: ppc_opc_mffsx(); return; case 711: ppc_opc_mtfsfx(); return; } } ppc_opc_invalid(); } ppc_opc_function ppc_opc_table_groupv[965]; //ppc_opc_function * ppc_opc_table_groupv; static void ppc_opc_init_groupv() { uint i; for (i=0; i<(sizeof ppc_opc_table_groupv / sizeof ppc_opc_table_groupv[0]);i++) { ppc_opc_table_groupv[i] = ppc_opc_invalid; } ppc_opc_table_groupv[0] = ppc_opc_vaddubm; ppc_opc_table_groupv[1] = ppc_opc_vmaxub; ppc_opc_table_groupv[2] = ppc_opc_vrlb; ppc_opc_table_groupv[4] = ppc_opc_vmuloub; ppc_opc_table_groupv[5] = ppc_opc_vaddfp; ppc_opc_table_groupv[6] = ppc_opc_vmrghb; ppc_opc_table_groupv[7] = ppc_opc_vpkuhum; ppc_opc_table_groupv[32] = ppc_opc_vadduhm; ppc_opc_table_groupv[33] = ppc_opc_vmaxuh; ppc_opc_table_groupv[34] = ppc_opc_vrlh; ppc_opc_table_groupv[36] = ppc_opc_vmulouh; ppc_opc_table_groupv[37] = ppc_opc_vsubfp; ppc_opc_table_groupv[38] = ppc_opc_vmrghh; ppc_opc_table_groupv[39] = ppc_opc_vpkuwum; ppc_opc_table_groupv[64] = ppc_opc_vadduwm; ppc_opc_table_groupv[65] = ppc_opc_vmaxuw; ppc_opc_table_groupv[66] = ppc_opc_vrlw; ppc_opc_table_groupv[70] = ppc_opc_vmrghw; ppc_opc_table_groupv[71] = ppc_opc_vpkuhus; ppc_opc_table_groupv[103] = ppc_opc_vpkuwus; ppc_opc_table_groupv[129] = ppc_opc_vmaxsb; ppc_opc_table_groupv[130] = ppc_opc_vslb; ppc_opc_table_groupv[132] = ppc_opc_vmulosb; ppc_opc_table_groupv[133] = ppc_opc_vrefp; ppc_opc_table_groupv[134] = ppc_opc_vmrglb; ppc_opc_table_groupv[135] = ppc_opc_vpkshus; ppc_opc_table_groupv[161] = ppc_opc_vmaxsh; ppc_opc_table_groupv[162] = ppc_opc_vslh; ppc_opc_table_groupv[164] = ppc_opc_vmulosh; ppc_opc_table_groupv[165] = ppc_opc_vrsqrtefp; ppc_opc_table_groupv[166] = ppc_opc_vmrglh; ppc_opc_table_groupv[167] = ppc_opc_vpkswus; ppc_opc_table_groupv[192] = ppc_opc_vaddcuw; ppc_opc_table_groupv[193] = ppc_opc_vmaxsw; ppc_opc_table_groupv[194] = ppc_opc_vslw; ppc_opc_table_groupv[197] = ppc_opc_vexptefp; ppc_opc_table_groupv[198] = ppc_opc_vmrglw; ppc_opc_table_groupv[199] = ppc_opc_vpkshss; ppc_opc_table_groupv[226] = ppc_opc_vsl; ppc_opc_table_groupv[229] = ppc_opc_vlogefp; ppc_opc_table_groupv[231] = ppc_opc_vpkswss; ppc_opc_table_groupv[256] = ppc_opc_vaddubs; ppc_opc_table_groupv[257] = ppc_opc_vminub; ppc_opc_table_groupv[258] = ppc_opc_vsrb; ppc_opc_table_groupv[260] = ppc_opc_vmuleub; ppc_opc_table_groupv[261] = ppc_opc_vrfin; ppc_opc_table_groupv[262] = ppc_opc_vspltb; ppc_opc_table_groupv[263] = ppc_opc_vupkhsb; ppc_opc_table_groupv[288] = ppc_opc_vadduhs; ppc_opc_table_groupv[289] = ppc_opc_vminuh; ppc_opc_table_groupv[290] = ppc_opc_vsrh; ppc_opc_table_groupv[292] = ppc_opc_vmuleuh; ppc_opc_table_groupv[293] = ppc_opc_vrfiz; ppc_opc_table_groupv[294] = ppc_opc_vsplth; ppc_opc_table_groupv[295] = ppc_opc_vupkhsh; ppc_opc_table_groupv[320] = ppc_opc_vadduws; ppc_opc_table_groupv[321] = ppc_opc_vminuw; ppc_opc_table_groupv[322] = ppc_opc_vsrw; ppc_opc_table_groupv[325] = ppc_opc_vrfip; ppc_opc_table_groupv[326] = ppc_opc_vspltw; ppc_opc_table_groupv[327] = ppc_opc_vupklsb; ppc_opc_table_groupv[354] = ppc_opc_vsr; ppc_opc_table_groupv[357] = ppc_opc_vrfim; ppc_opc_table_groupv[359] = ppc_opc_vupklsh; ppc_opc_table_groupv[384] = ppc_opc_vaddsbs; ppc_opc_table_groupv[385] = ppc_opc_vminsb; ppc_opc_table_groupv[386] = ppc_opc_vsrab; ppc_opc_table_groupv[388] = ppc_opc_vmulesb; ppc_opc_table_groupv[389] = ppc_opc_vcfux; ppc_opc_table_groupv[390] = ppc_opc_vspltisb; ppc_opc_table_groupv[391] = ppc_opc_vpkpx; ppc_opc_table_groupv[416] = ppc_opc_vaddshs; ppc_opc_table_groupv[417] = ppc_opc_vminsh; ppc_opc_table_groupv[418] = ppc_opc_vsrah; ppc_opc_table_groupv[420] = ppc_opc_vmulesh; ppc_opc_table_groupv[421] = ppc_opc_vcfsx; ppc_opc_table_groupv[422] = ppc_opc_vspltish; ppc_opc_table_groupv[423] = ppc_opc_vupkhpx; ppc_opc_table_groupv[448] = ppc_opc_vaddsws; ppc_opc_table_groupv[449] = ppc_opc_vminsw; ppc_opc_table_groupv[450] = ppc_opc_vsraw; ppc_opc_table_groupv[453] = ppc_opc_vctuxs; ppc_opc_table_groupv[454] = ppc_opc_vspltisw; ppc_opc_table_groupv[485] = ppc_opc_vctsxs; ppc_opc_table_groupv[487] = ppc_opc_vupklpx; ppc_opc_table_groupv[512] = ppc_opc_vsububm; ppc_opc_table_groupv[513] = ppc_opc_vavgub; ppc_opc_table_groupv[514] = ppc_opc_vand; ppc_opc_table_groupv[517] = ppc_opc_vmaxfp; ppc_opc_table_groupv[518] = ppc_opc_vslo; ppc_opc_table_groupv[544] = ppc_opc_vsubuhm; ppc_opc_table_groupv[545] = ppc_opc_vavguh; ppc_opc_table_groupv[546] = ppc_opc_vandc; ppc_opc_table_groupv[549] = ppc_opc_vminfp; ppc_opc_table_groupv[550] = ppc_opc_vsro; ppc_opc_table_groupv[576] = ppc_opc_vsubuwm; ppc_opc_table_groupv[577] = ppc_opc_vavguw; ppc_opc_table_groupv[578] = ppc_opc_vor; ppc_opc_table_groupv[610] = ppc_opc_vxor; ppc_opc_table_groupv[641] = ppc_opc_vavgsb; ppc_opc_table_groupv[642] = ppc_opc_vnor; ppc_opc_table_groupv[673] = ppc_opc_vavgsh; ppc_opc_table_groupv[704] = ppc_opc_vsubcuw; ppc_opc_table_groupv[705] = ppc_opc_vavgsw; ppc_opc_table_groupv[768] = ppc_opc_vsububs; ppc_opc_table_groupv[770] = ppc_opc_mfvscr; ppc_opc_table_groupv[772] = ppc_opc_vsum4ubs; ppc_opc_table_groupv[800] = ppc_opc_vsubuhs; ppc_opc_table_groupv[802] = ppc_opc_mtvscr; ppc_opc_table_groupv[804] = ppc_opc_vsum4shs; ppc_opc_table_groupv[832] = ppc_opc_vsubuws; ppc_opc_table_groupv[836] = ppc_opc_vsum2sws; ppc_opc_table_groupv[896] = ppc_opc_vsubsbs; ppc_opc_table_groupv[900] = ppc_opc_vsum4sbs; ppc_opc_table_groupv[928] = ppc_opc_vsubshs; ppc_opc_table_groupv[960] = ppc_opc_vsubsws; ppc_opc_table_groupv[964] = ppc_opc_vsumsws; } // main opcode 04 static void ppc_opc_group_v() { uint32 ext = PPC_OPC_EXT(gCPU.current_opc); #ifndef __VEC_EXC_OFF__ if ((gCPU.msr & MSR_VEC) == 0) { ppc_exception(PPC_EXC_NO_VEC,0 ,0); return; } #endif switch(ext & 0x1f) { case 16: if (gCPU.current_opc & PPC_OPC_Rc) return ppc_opc_vmhraddshs(); else return ppc_opc_vmhaddshs(); case 17: return ppc_opc_vmladduhm(); case 18: if (gCPU.current_opc & PPC_OPC_Rc) return ppc_opc_vmsummbm(); else return ppc_opc_vmsumubm(); case 19: if (gCPU.current_opc & PPC_OPC_Rc) return ppc_opc_vmsumuhs(); else return ppc_opc_vmsumuhm(); case 20: if (gCPU.current_opc & PPC_OPC_Rc) return ppc_opc_vmsumshs(); else return ppc_opc_vmsumshm(); case 21: if (gCPU.current_opc & PPC_OPC_Rc) return ppc_opc_vperm(); else return ppc_opc_vsel(); case 22: return ppc_opc_vsldoi(); case 23: if (gCPU.current_opc & PPC_OPC_Rc) return ppc_opc_vnmsubfp(); else return ppc_opc_vmaddfp(); } switch(ext & 0x1ff) { case 3: return ppc_opc_vcmpequbx(); case 35: return ppc_opc_vcmpequhx(); case 67: return ppc_opc_vcmpequwx(); case 99: return ppc_opc_vcmpeqfpx(); case 227: return ppc_opc_vcmpgefpx(); case 259: return ppc_opc_vcmpgtubx(); case 291: return ppc_opc_vcmpgtuhx(); case 323: return ppc_opc_vcmpgtuwx(); case 355: return ppc_opc_vcmpgtfpx(); case 387: return ppc_opc_vcmpgtsbx(); case 419: return ppc_opc_vcmpgtshx(); case 451: return ppc_opc_vcmpgtswx(); case 483: return ppc_opc_vcmpbfpx(); } if (ext >= (sizeof ppc_opc_table_groupv / sizeof ppc_opc_table_groupv[0])) { return ppc_opc_invalid(); } return ppc_opc_table_groupv[ext](); } static ppc_opc_function ppc_opc_table_main[64] = { &ppc_opc_invalid, // 0 &ppc_opc_invalid, // 1 &ppc_opc_invalid, // 2 (tdi on 64 bit platforms) &ppc_opc_twi, // 3 &ppc_opc_invalid, // 4 (altivec group 1) &ppc_opc_invalid, // 5 &ppc_opc_invalid, // 6 &ppc_opc_mulli, // 7 &ppc_opc_subfic, // 8 &ppc_opc_invalid, // 9 &ppc_opc_cmpli, // 10 &ppc_opc_cmpi, // 11 &ppc_opc_addic, // 12 &ppc_opc_addic_, // 13 &ppc_opc_addi, // 14 &ppc_opc_addis, // 15 &ppc_opc_bcx, // 16 &ppc_opc_sc, // 17 &ppc_opc_bx, // 18 &ppc_opc_group_1, // 19 &ppc_opc_rlwimix, // 20 &ppc_opc_rlwinmx, // 21 &ppc_opc_invalid, // 22 &ppc_opc_rlwnmx, // 23 &ppc_opc_ori, // 24 &ppc_opc_oris, // 25 &ppc_opc_xori, // 26 &ppc_opc_xoris, // 27 &ppc_opc_andi_, // 28 &ppc_opc_andis_, // 29 &ppc_opc_invalid, // 30 (group_rld on 64 bit platforms) &ppc_opc_group_2, // 31 &ppc_opc_lwz, // 32 &ppc_opc_lwzu, // 33 &ppc_opc_lbz, // 34 &ppc_opc_lbzu, // 35 &ppc_opc_stw, // 36 &ppc_opc_stwu, // 37 &ppc_opc_stb, // 38 &ppc_opc_stbu, // 39 &ppc_opc_lhz, // 40 &ppc_opc_lhzu, // 41 &ppc_opc_lha, // 42 &ppc_opc_lhau, // 43 &ppc_opc_sth, // 44 &ppc_opc_sthu, // 45 &ppc_opc_lmw, // 46 &ppc_opc_stmw, // 47 &ppc_opc_lfs, // 48 &ppc_opc_lfsu, // 49 &ppc_opc_lfd, // 50 &ppc_opc_lfdu, // 51 &ppc_opc_stfs, // 52 &ppc_opc_stfsu, // 53 &ppc_opc_stfd, // 54 &ppc_opc_stfdu, // 55 &ppc_opc_invalid, // 56 &ppc_opc_invalid, // 57 &ppc_opc_invalid, // 58 (ld on 64 bit platforms) &ppc_opc_group_f1, // 59 &ppc_opc_invalid, // 60 &ppc_opc_invalid, // 61 &ppc_opc_invalid, // 62 &ppc_opc_group_f2, // 63 }; void FASTCALL ppc_exec_opc() { uint32 mainopc = PPC_OPC_MAIN(gCPU.current_opc); // printf("DBG:before exec pc=0x%x,opc=0x%x,mainopc=0x%x\n", gCPU.pc, gCPU.current_opc,mainopc); ppc_opc_table_main[mainopc](); } void ppc_dec_init() { ppc_opc_init_group2(); if ((ppc_cpu_get_pvr(0) & 0xffff0000) == 0x000c0000) { ppc_opc_table_main[4] = ppc_opc_group_v; ppc_opc_init_groupv(); } } �����������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/common/ppc_dec.h����������������������������������������������������������0000644�0001750�0000144�00000004625�10635115336�017005� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * ppc_dec.h * * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_DEC_H__ #define __PPC_DEC_H__ #include "types.h" void FASTCALL ppc_exec_opc(); void ppc_dec_init(); typedef void (*ppc_opc_function)(); #define PPC_OPC_ASSERT(v) #define PPC_OPC_MAIN(opc) (((opc)>>26)&0x3f) #define PPC_OPC_EXT(opc) (((opc)>>1)&0x3ff) #define PPC_OPC_Rc 1 #define PPC_OPC_OE (1<<10) #define PPC_OPC_LK 1 #define PPC_OPC_AA (1<<1) #define PPC_OPC_TEMPL_A(opc, rD, rA, rB, rC) {rD=((opc)>>21)&0x1f;rA=((opc)>>16)&0x1f;rB=((opc)>>11)&0x1f;rC=((opc)>>6)&0x1f;} #define PPC_OPC_TEMPL_B(opc, BO, BI, BD) {BO=((opc)>>21)&0x1f;BI=((opc)>>16)&0x1f;BD=(opc)&0xfffc;if (BD&0x8000) BD |= 0xffff0000;} #define PPC_OPC_TEMPL_D_SImm(opc, rD, rA, imm) {rD=((opc)>>21)&0x1f;rA=((opc)>>16)&0x1f;imm=(opc)&0xffff;if (imm & 0x8000) imm |= 0xffff0000;} #define PPC_OPC_TEMPL_D_UImm(opc, rD, rA, imm) {rD=((opc)>>21)&0x1f;rA=((opc)>>16)&0x1f;imm=(opc)&0xffff;} #define PPC_OPC_TEMPL_D_Shift16(opc, rD, rA, imm) {rD=((opc)>>21)&0x1f;rA=((opc)>>16)&0x1f;imm=(opc)<<16;} #define PPC_OPC_TEMPL_I(opc, LI) {LI=(opc)&0x3fffffc;if (LI&0x02000000) LI |= 0xfc000000;} #define PPC_OPC_TEMPL_M(opc, rS, rA, SH, MB, ME) {rS=((opc)>>21)&0x1f;rA=((opc)>>16)&0x1f;SH=((opc)>>11)&0x1f;MB=((opc)>>6)&0x1f;ME=((opc)>>1)&0x1f;} #define PPC_OPC_TEMPL_X(opc, rS, rA, rB) {rS=((opc)>>21)&0x1f;rA=((opc)>>16)&0x1f;rB=((opc)>>11)&0x1f;} #define PPC_OPC_TEMPL_XFX(opc, rS, CRM) {rS=((opc)>>21)&0x1f;CRM=((opc)>>12)&0xff;} #define PPC_OPC_TEMPL_XO(opc, rS, rA, rB) {rS=((opc)>>21)&0x1f;rA=((opc)>>16)&0x1f;rB=((opc)>>11)&0x1f;} #define PPC_OPC_TEMPL_XL(opc, BO, BI, BD) {BO=((opc)>>21)&0x1f;BI=((opc)>>16)&0x1f;BD=((opc)>>11)&0x1f;} #define PPC_OPC_TEMPL_XFL(opc, rB, FM) {rB=((opc)>>11)&0x1f;FM=((opc)>>17)&0xff;} #endif �����������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/���������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014635� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/mpc8xx_mem.c���������������������������������������������������������0000644�0001750�0000144�00000022243�10541533231�017076� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * ---------------------------------------------------- * * MPC8xx Memory Controller emulation * (C) 2004 Lightmaze Solutions AG * Author: Jochen Karrer * * Status * not yet working * * ---------------------------------------------------- */ #include <stdio.h> #include <stdlib.h> #include <stdint.h> #include <string.h> #include <bus.h> #include <cpu_ppc.h> #include <configfile.h> #include "mpc8xx_immr.h" #include "mpc8xx_mem.h" struct MPC8xx_MemCo { BusDevice *bdev[8]; int is_bootmap; uint32_t immr; /* Internal memory map register */ uint32_t br[8]; uint32_t or[8]; uint32_t mar; uint32_t mcr; uint32_t mamr; uint32_t mbmr; uint16_t mstat; uint16_t mptpr; }; /* * ---------------------------------------- * Boot memory Map * Chapter 15.5.2 of MPC866 Manual * ---------------------------------------- */ static void MPC8xx_BootMap(MPC8xx_MemCo *memco) { uint32_t start,end; uint32_t mapsize; BusDevice *bdev = memco->bdev[0]; start = 0; end = memco->immr & 0xffff0000; // 64k Window if(!bdev) { return; } mapsize=start-end; fprintf(stderr,"IMMR %08x\n",memco->immr); if(mapsize) { fprintf(stderr,"1: Mapping from %08x, size %08x\n",start,mapsize); Mem_AreaAddMapping(bdev,start,mapsize,MEM_FLAG_READABLE | MEM_FLAG_READABLE); } start = (memco->immr & 0xffff0000) + 0x10000; mapsize = ~start+1; if(mapsize) { fprintf(stderr,"2: Mapping from %08x, size %08x\n",start,mapsize); Mem_AreaAddMapping(bdev,start,mapsize,MEM_FLAG_READABLE | MEM_FLAG_READABLE); } } /* * ---------------------------------------------- * Currently ignores readable/writable flags * ---------------------------------------------- */ static void MPC8xx_RebuildMmap(MPC8xx_MemCo *memco) { BusDevice *bdev; int i; for(i=0;i<8;i++) { bdev=memco->bdev[i]; if(bdev) { Mem_AreaDeleteMappings(bdev); } } if(memco->is_bootmap) { MPC8xx_BootMap(memco); } else { for(i=0;i<8;i++) { uint32_t base; uint32_t mapsize; uint32_t mask; uint32_t br; uint32_t or; br = memco->br[i]; or = memco->or[i]; base = br & 0xffff8000; mask = OR_AM(or); mapsize = ~mask+1; bdev=memco->bdev[i]; if(!bdev) continue; if(!BR_V(br)) { continue; } Mem_AreaAddMapping(bdev,base,mapsize,MEM_FLAG_WRITABLE|MEM_FLAG_READABLE); } } } static uint32_t br_read(void *clientData,uint32_t address,int rqlen) { MPC8xx_MemCo *memco = (MPC8xx_MemCo *)clientData; int offs = (address >> 3) & 7; return memco->br[offs]; } static void br_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { MPC8xx_MemCo *memco = (MPC8xx_MemCo *)clientData; int offs = (address >> 3) & 7; memco->br[offs]=value; fprintf(stderr,"PPC-Memco BR %d: %08x, value %08x\n",offs,address,value); MPC8xx_RebuildMmap(memco); return; } static uint32_t or_read(void *clientData,uint32_t address,int rqlen) { MPC8xx_MemCo *memco = (MPC8xx_MemCo *)clientData; int offs = (address >> 3) & 7; fprintf(stderr,"PPC-Memco read OR %d\n",offs); return memco->or[offs]; } static void or_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { MPC8xx_MemCo *memco = (MPC8xx_MemCo *)clientData; int cs = (address >> 3) & 7; int update=0; fprintf(stderr,"OR %d write value %08x\n",cs,value); if(cs==0) { if(memco->is_bootmap) { memco->is_bootmap=0; /* First write enables the memory Map */ update = 1; } } memco->or[cs]=value; MPC8xx_RebuildMmap(memco); } static uint32_t mar_read(void *clientData,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco read MAR register %08x not implemented\n",address); return 0; } static void mar_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco write MAR register %08x not implemented\n",address); } static uint32_t mcr_read(void *clientData,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco read MCR register %08x not implemented\n",address); return 0; } static void mcr_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco write MCR register %08x not implemented\n",address); } static uint32_t mamr_read(void *clientData,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco read MAMR register %08x not implemented\n",address); return 0; } static void mamr_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx MAMR write register %08x not implemented\n",address); } static uint32_t mbmr_read(void *clientData,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx MBMR read register %08x not implemented\n",address); return 0; } static void mbmr_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx MBMR write register %08x not implemented\n",address); } static uint32_t mstat_read(void *clientData,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco read MSTAT register %08x not implemented\n",address); return 0; } static void mstat_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco write MSTAT register %08x not implemented\n",address); } static uint32_t mptpr_read(void *clientData,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx-Memco read MPTPR register %08x not implemented\n",address); return 0; } static void mptpr_write(void *clientData,uint32_t value,uint32_t address,int rqlen) { fprintf(stderr,"MPC8xx write MPTPR register %08x not implemented\n",address); } static void MPC8xx_MemCoMap(MPC8xx_MemCo *memco) { int i; uint32_t addr; uint32_t base = IMMR_ISB(memco->immr); for(i=0;i<8;i++) { addr=MPC8xx_BR(i); IOH_New32(base+addr,br_read,br_write,memco); addr=MPC8xx_OR(i); IOH_New32(base+addr,or_read,or_write,memco); } IOH_New32(base + MPC8xx_MAR,mar_read,mar_write,memco); IOH_New32(base + MPC8xx_MCR,mcr_read,mcr_write,memco); IOH_New32(base + MPC8xx_MAMR,mamr_read,mamr_write,memco); IOH_New32(base + MPC8xx_MBMR,mbmr_read,mbmr_write,memco); IOH_New16(base + MPC8xx_MSTAT,mstat_read,mstat_write,memco); IOH_New16(base + MPC8xx_MPTPR,mptpr_read,mptpr_write,memco); } static void MPC8xx_MemCoUnMap(MPC8xx_MemCo *memco) { int i; uint32_t addr; uint32_t base = IMMR_ISB(memco->immr); for(i=0;i<8;i++) { addr=MPC8xx_BR(i); IOH_Delete32(base + addr); addr=MPC8xx_OR(i); IOH_Delete32(base+addr); } IOH_Delete32(base + MPC8xx_MAR); IOH_Delete32(base + MPC8xx_MCR); IOH_Delete32(base + MPC8xx_MAMR); IOH_Delete32(base + MPC8xx_MBMR); IOH_Delete16(base + MPC8xx_MSTAT); IOH_Delete16(base + MPC8xx_MPTPR); } void MPC8xx_RegisterDevice(MPC8xx_MemCo *memco,BusDevice *bdev,uint32_t cs) { if(cs>7) { fprintf(stderr,"Bug, only 8 Chipselects available but trying to set Nr. %d\n",cs); exit(4324); } if(memco->bdev[cs]) { fprintf(stderr,"NS9750_RegisterDevice warning: There is already a device for CS%d\n",cs); } memco->bdev[cs]=bdev; MPC8xx_RebuildMmap(memco); } static uint32_t MemCo_ImmrRead(int spr,void *cd) { MPC8xx_MemCo *memco=(MPC8xx_MemCo*)cd; return memco->immr; } /* * ----------------------------------------------------------- * SPR638 (IMMR) is a traced Processor processor register * When it changes the Internal registers of * the MPC8xx have to be moved * ----------------------------------------------------------- */ void MemCo_ImmrWrite(uint32_t value,int spr,void *cd) { MPC8xx_MemCo *memco=(MPC8xx_MemCo*)cd; if(value!=memco->immr) { MPC8xx_MemCoUnMap(memco); memco->immr = value; MPC8xx_MemCoMap(memco); if(memco->is_bootmap) { MPC8xx_RebuildMmap(memco); } } } MPC8xx_MemCo * MPC8xx_MemController_New(PpcCpu *cpu) { MPC8xx_MemCo *memco = (MPC8xx_MemCo*)malloc(sizeof(MPC8xx_MemCo)); uint32_t configWord; uint32_t rstconf; uint32_t isb; uint32_t bdis; if(!memco) { fprintf(stderr,"Out of memory\n"); exit(6495); } memset(memco,0,sizeof(MPC8xx_MemCo)); /* from hardreset configuration word */ if(Config_ReadUInt32(&rstconf,"MPC8xx","rstconf")<0) { fprintf(stderr,"Can not read MPC8xx rstconf pin\n"); exit(1468); } if(rstconf) { configWord = 0; fprintf(stderr,"RSTCONFIG is high: configword is 0\n"); } else { if(Config_ReadUInt32(&configWord,"MPC8xx","configWord")<0) { fprintf(stderr,"Can not read MPC8xx configuration word\n"); exit(1468); } } isb = (configWord >> 23)&3; bdis = (configWord >> 28)&1; switch(isb) { case 0: memco->immr=0; break; case 1: memco->immr=0x00f00000; break; case 2: memco->immr=0xff000000; break; case 3: default: memco->immr=0xfff00000; break; } fprintf(stderr,"isb %d immr %08x\n",isb,memco->immr); // fprintf(stderr,"bdis %08x word %08x\n",bdis,configWord); memco->br[0] = 0; memco->or[0] = 0xfff4; memco->mamr = 0x00001000; memco->mbmr = 0x00001000; memco->mstat = 0; memco->mcr = 0; memco->is_bootmap=1; Ppc_RegisterSprHandler(cpu,SPR_IMMR,MemCo_ImmrRead,MemCo_ImmrWrite, memco); MPC8xx_MemCoMap(memco); fprintf(stderr,"MPC8xx Memory Controller created: IMMR 0x%08x\n",memco->immr); return memco; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/skyeye_mach_mpc823.c�������������������������������������������������0000644�0001750�0000144�00000002033�10670135273�020410� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_mpc823.c - peripherl implementation of MPC823 Copyright (C) 2006 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ #include "mpc823.h" �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/mpc8560.h������������������������������������������������������������0000644�0001750�0000144�00000000600�10635115336�016117� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef __MPC8560_H__ #define __MPC8560_H__ #define PCI_TARGET_CODE 0b0000 #define LOCAL_BUS_TARGET_CODE 0b0100 #define RAPID_IO_TARGET_CODE 0b1100 #define DDR_SDRAM_TARGET_CODE 0b1111 #endif #ifndef __MPC8560_H__ #define __MPC8560_H__ #define PCI_TARGET_CODE 0b0000 #define LOCAL_BUS_TARGET_CODE 0b0100 #define RAPID_IO_TARGET_CODE 0b1100 #define DDR_SDRAM_TARGET_CODE 0b1111 #endif ��������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/skyeye_mach_mac.c����������������������������������������������������0000644�0001750�0000144�00000014103�10635115336�020134� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * PearPC * io.h * * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /*#include "system/types.h" #include <stdlib.h> #include <string.h> #include "cpu/cpu.h" #include "cpu/debug.h" #include "cpu/mem.h" #include "io.h" #include "io/graphic/gcard.h" #include "io/pic/pic.h" #include "io/pci/pci.h" #include "io/cuda/cuda.h" #include "io/nvram/nvram.h" #include "debug/tracers.h" */ #include "types.h" #define IO_MEM_ACCESS_OK 0 #define IO_MEM_ACCESS_EXC 1 #define IO_MEM_ACCESS_FATAL 2 static int io_mem_write(uint32 addr, uint32 data, int size) { if (addr >= IO_GCARD_FRAMEBUFFER_PA_START && addr < IO_GCARD_FRAMEBUFFER_PA_END) { gcard_write(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_PCI_PA_START && addr < IO_PCI_PA_END) { pci_write(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_PIC_PA_START && addr < IO_PIC_PA_END) { pic_write(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_CUDA_PA_START && addr < IO_CUDA_PA_END) { cuda_write(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_NVRAM_PA_START && addr < IO_NVRAM_PA_END) { nvram_write(addr, data, size); return IO_MEM_ACCESS_OK; } // PCI and ISA must be checked at last if (addr >= IO_PCI_DEVICE_PA_START && addr < IO_PCI_DEVICE_PA_END) { pci_write_device(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_ISA_PA_START && addr < IO_ISA_PA_END) { /* * should raise exception here... * but linux dont like this */ isa_write(addr, data, size); return IO_MEM_ACCESS_OK; /*if (isa_write(addr, data, size)) { return IO_MEM_ACCESS_OK; } else { ppc_exception(PPC_EXC_MACHINE_CHECK); return IO_MEM_ACCESS_EXC; }*/ } IO_CORE_WARN("no one is responsible for address %08x (write: %08x from %08x)\n", addr, data, ppc_cpu_get_pc(0)); SINGLESTEP(""); ppc_machine_check_exception(); return IO_MEM_ACCESS_EXC; } static int io_mem_read(uint32 addr, uint32 *data, int size) { if (addr >= IO_GCARD_FRAMEBUFFER_PA_START && addr < IO_GCARD_FRAMEBUFFER_PA_END) { gcard_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_PCI_PA_START && addr < IO_PCI_PA_END) { pci_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_PIC_PA_START && addr < IO_PIC_PA_END) { pic_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_CUDA_PA_START && addr < IO_CUDA_PA_END) { cuda_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_NVRAM_PA_START && addr < IO_NVRAM_PA_END) { nvram_read(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr == 0xff000004) { // wtf? data = 1; return IO_MEM_ACCESS_OK; } // PCI and ISA must be checked at last if (addr >= IO_PCI_DEVICE_PA_START && addr < IO_PCI_DEVICE_PA_END) { pci_read_device(addr, data, size); return IO_MEM_ACCESS_OK; } if (addr >= IO_ISA_PA_START && addr < IO_ISA_PA_END) { /* * should raise exception here... * but linux dont like this */ isa_read(addr, data, size); return IO_MEM_ACCESS_OK; /*if (isa_read(addr, data, size)) { return IO_MEM_ACCESS_OK; } else { ppc_exception(PPC_EXC_MACHINE_CHECK); return IO_MEM_ACCESS_EXC; }*/ } IO_CORE_WARN("no one is responsible for address %08x (read from %08x)\n", addr, ppc_cpu_get_pc(0)); SINGLESTEP(""); ppc_machine_check_exception(); return IO_MEM_ACCESS_EXC; } static int io_mem_write64(uint32 addr, uint64 data) { if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_write64(addr, data); return IO_MEM_ACCESS_OK; } IO_CORE_ERR("no one is responsible for address %08x (write64: %016q from %08x)\n", addr, &data, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static int io_mem_read64(uint32 addr, uint64 &data) { if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_read64(addr, data); return IO_MEM_ACCESS_OK; } IO_CORE_ERR("no one is responsible for address %08x (read64 from %08x)\n", addr, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static int io_mem_write128(uint32 addr, uint128 *data) { if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_write128(addr, data); return IO_MEM_ACCESS_OK; } IO_CORE_ERR("no one is responsible for address %08x (write128: %016q%016q from %08x)\n", addr, data->h, data->l, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static int io_mem_write128_native(uint32 addr, uint128 *data) { if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_write128_native(addr, data); return IO_MEM_ACCESS_OK; } IO_CORE_ERR("no one is responsible for address %08x (write128: %016q%016q from %08x)\n", addr, data->h, data->l, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static int io_mem_read128(uint32 addr, uint128 *data) { if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_read128(addr, data); return IO_MEM_ACCESS_OK; } IO_CORE_ERR("no one is responsible for address %08x (read128 from %08x)\n", addr, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } static int io_mem_read128_native(uint32 addr, uint128 *data) { if ((addr >= IO_GCARD_FRAMEBUFFER_PA_START) && (addr < (IO_GCARD_FRAMEBUFFER_PA_END))) { gcard_read128_native(addr, data); return IO_MEM_ACCESS_OK; } IO_CORE_ERR("no one is responsible for address %08x (read128 from %08x)\n", addr, ppc_cpu_get_pc(0)); return IO_MEM_ACCESS_FATAL; } void io_init(); void io_done(); void io_init_config(); �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/skyeye_mach_mpc8560.c������������������������������������������������0000644�0001750�0000144�00000011370�10711400073�020467� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_mpc8560.c - mpc8560 machine simulation implementation Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 01/04/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include <stdint.h> #include "skyeye_config.h" #include <ppc_cpu.h> typedef struct mpc8560_uart_s{ }mpc8560_uart_t; #if 0 typedef struct pic_global_s{ uint32_t brr[2]; uint32_t ipidr[4]; uint32_t ctpr; uint32_t whoami; uint32_t iask; uint32_t eoi; uint32_t frr; uint32_t gcr; uint32_t vir; uint32_t pir; uint32_t ipivpr[4]; uint32_t svr; }pic_global_t; #endif typedef struct global_timer_s{ uint32_t gtccr; uint32_t gtbcr; uint32_t gtvpr; uint32_t gtdr; }global_timer_t; typedef struct pic_timer_s{ uint32_t tfrr; global_timer_t timer[4]; uint32_t tcr; }pic_timer_t; typedef struct pic_int_summary_s{ uint32_t erqsr; uint32_t irqsr[3]; uint32_t cisr[3]; }pic_int_summary_t; /* Performance Monitor Mask Registers */ typedef struct pic_pmm_s{ uint32_t pm0mr[3]; uint32_t pm1mr[3]; uint32_t pm2mr[3]; uint32_t pm3mr[3]; }pic_pmm_t; /* Message Register */ typedef struct pic_message_s{ uint32_t msgr[4]; uint32_t mer; uint32_t msr; uint32_t msir[8]; uint32_t msisr; uint32_t msiir; }pic_message_t; /* Interrupt source configuration register */ typedef struct pic_isc_s{ uint32_t eivpr[12]; uint32_t eidr[12]; uint32_t iivpr[48]; uint32_t iidr[48]; uint32_t mivpr[4]; uint32_t midr[4]; uint32_t msivpr[8]; uint32_t msidr[8]; }pic_isc_t; /* typedef struct pic_percpu_s{ uint32_t ipidr[4]; uint32_t ctpr; uint32_t whoami; uint32_t iask; uint32_t eoi; }pic_percpu_t; */ typedef struct mpc8560_pic_s{ global_timer_t timer_reg; //pic_global_t global_reg; pic_pmm_t pmm_reg; pic_message_t message_reg; pic_isc_t isc_reg; pic_percpu_t percpu_reg; }mpc8560_pic_t; /* local address register window defined by mpc8560 */ typedef struct mpc8560_law_s{ uint32_t lawbar[8]; uint32_t lawar[8]; }mpc8560_law_t; /* local configuration register */ typedef struct mpc8560_conf_s{ uint32_t ccsrbar; /* Configuration,control, and status registers base address register */ uint32_t altcbar; /* alternate configuration base address register */ uint32_t altcar; /* alternate configuration attribute register */ uint32_t bptr; /* boot page translation register */ }mpc8560_conf_t; typedef struct mpc8560_io_s{ mpc8560_pic_t pic; mpc8560_law_t law; mpc8560_conf_t conf; }mpc8560_io_t; static mpc8560_io_t mpc8560_io; static void mpc8560_io_do_cycle (void * state) { } static void mpc8560_io_reset (void * state) { } static uint32_t mpc8560_io_read_byte (void * state, uint32_t addr){} static uint32_t mpc8560_io_read_halfword (void * state, uint32_t addr){} static uint32_t mpc8560_io_read_word (void * state, uint32_t addr) {} static void mpc8560_io_write_byte (void * state, uint32_t addr, uint32_t data) { } static void mpc8560_io_write_halfword (void * state, uint32_t addr, uint32_t data) { } static void mpc8560_io_write_word (void * state, uint32_t addr, uint32_t data) {} static void mpc8560_update_int (void * state) { } void mpc8560_mach_init( void * state, machine_config_t * this_mach){ PPC_CPU_State * p_state = (PPC_CPU_State *)state; this_mach->mach_io_do_cycle = mpc8560_io_do_cycle; this_mach->mach_io_reset = mpc8560_io_reset; this_mach->mach_io_read_byte = mpc8560_io_read_byte; this_mach->mach_io_write_byte = mpc8560_io_write_byte; this_mach->mach_io_read_halfword = mpc8560_io_read_halfword; this_mach->mach_io_write_halfword = mpc8560_io_write_halfword; this_mach->mach_io_read_word = mpc8560_io_read_word; this_mach->mach_io_write_word = mpc8560_io_write_word; this_mach->mach_update_int = mpc8560_update_int; //mpc8560_io.conf.ccsrbar = 0x000FF700; /* Just for convience of boot linux */ mpc8560_io.conf.ccsrbar = 0x000E0000; /* initialize interrupt controller */ int i = 0; for(; i < 32; i++){ p_state->pic_ram.iidr[i] = 0x1; p_state->pic_ram.iivpr[i] = 0x80800000; } } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/mpc8xx_mem.h���������������������������������������������������������0000644�0001750�0000144�00000000736�10541533231�017106� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#define CS0 (0) #define CS1 (1) #define CS2 (2) #define CS3 (3) #define CS4 (4) #define CS5 (5) #define CS6 (6) #define CS7 (7) #define SPR_IMMR (638) /* Internal space base */ #define IMMR_ISB(immr) ((immr) & 0xffff0000); #define IMMR_PARTNUM(immr) (((immr)&0xff00)>>8) #define IMMR_MASKNUM(immr) (((immr)&0xff)) typedef struct MPC8xx_MemCo MPC8xx_MemCo; MPC8xx_MemCo * MPC8xx_MemController_New(); void MPC8xx_RegisterDevice(MPC8xx_MemCo *memco,BusDevice *bdev,uint32_t cs); ����������������������������������skyeye-1.2.5_REL/arch/ppc/mach/skyeye_mach_mpc8548.c������������������������������������������������0000644�0001750�0000144�00000000000�10635115336�020473� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/Makefile�������������������������������������������������������������0000644�0001750�0000144�00000000156�10600011124�016270� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������CROSS_COMPILE ?= EXTRA_CFLAGS ?= CC = $(CROSS_COMPILE)gcc CFLAGS := $(CFLAGS) $(EXTRA_CFLAGS) all: clean: ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/ppc/mach/mpc823.h�������������������������������������������������������������0000644�0001750�0000144�00000004334�10635115336�016041� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* mpc823.h - register definition for MPC823 Copyright (C) 2006 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> */ uint32_t mpc823_mem_map[64 * 1024]; enum{ /* System Interface Unit */ SIUMCR = 0, SYPCR, SWSR = 0xe, SIPED = 0x10, SIMASK, SIEL, SIVEC, TESR, SDCR = 0x30, /* PCMICA */ /* Memory Controller */ /* System Integration Timers */ /* CLOCKS AND RESET */ /* System Integration Timer Keys */ /* Clocks and Reset Keys */ /* Video Controller */ /* LCD Controller */ /* I2C Controller */ /* DMA Controller */ /* Communications Processor Module Interrupt Controller */ /* Parallel Ports */ /* CPM Timers */ /* Communication Processor Module */ /* Baud Rate Generators */ /* Universal Serial Bus */ /* Serial Communication Controller 2 */ /* Serial Communication Controller 3 */ /* Serial Management Controller 1 */ /* Serial Management Controller 2 */ /* Serial Peripheral Interface */ /* Port B */ /* Serial Interface */ /* Specialized RAM */ /* Dual-port RAM */ } enum{ PSMR = 0xa28, SCCE = 0xa30, SCCM = 0xa24, /* SCCX UART mask register */ SCCS = 0xa37, /* SCCX status register */ } enum{ RBASE = 0x00; TBASE = 0x02; RFCR = 0x04; TFCR = 0x05; MRBLR = 0x06; RSTATE= 0x08; RPTR = 0x0c; RBPTR = 0x10; RCNT = 0x12; RTMP = 0x14; TSTATE= 0x18; TPTR = 0x1C; TBPTR = 0x20; TCNT = 0x22; TTMP = 0x24; RCRC = 0x28; TCRC = 0x2c; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/��������������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023523237�013730� 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mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \ uninstall-am armemu32.o:common/armemu.c $(CC) -DMODE32 $(DEFS) $(INCLUDES) common/armemu.c -c -o $@ # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/���������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014636� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_dp.h���������������������������������������������������������0000644�0001750�0000144�00000004726�10541455476�016735� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_DP_H_ #define _ARM2X86_DP_H_ extern op_table_t op_andl_T0_T1; extern op_table_t op_eorl_T0_T1; extern op_table_t op_subl_T0_T1; extern op_table_t op_subl_T0_T1_scv; extern op_table_t op_rsbl_T0_T1; extern op_table_t op_rsbl_T0_T1_scv; extern op_table_t op_addl_T0_T1; extern op_table_t op_addl_T0_T1_scv; extern op_table_t op_adcl_T0_T1; extern op_table_t op_adcl_T0_T1_scv; extern op_table_t op_sbcl_T0_T1; extern op_table_t op_sbcl_T0_T1_scv; extern op_table_t op_rscl_T0_T1; extern op_table_t op_rscl_T0_T1_scv; extern op_table_t op_orrl_T0_T1; extern op_table_t op_movl_T0_T1; extern op_table_t op_bicl_T0_T1; extern op_table_t op_notl_T0_T1; extern op_table_t op_addl_T1_im; extern op_table_t op_subl_T1_T2; extern op_table_t op_addl_T1_T2; //teawater add for xscale(arm v5) 2005.09.01------------------------------------ extern op_table_t op_clzl_T0_T1; extern op_table_t op_qaddl_T0_T1_sq; extern op_table_t op_qsubl_T0_T1_sq; extern op_table_t op_addl_T0_T1_sq; //AJ2D-------------------------------------------------------------------------- typedef void (arm2x86_get_dp_op_t) (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd); extern arm2x86_get_dp_op_t *arm2x86_get_dp_op[16]; extern arm2x86_get_dp_op_t *arm2x86_get_dp_op_setcpsr[16]; extern int arm2x86_dp_init (); static __inline__ void gen_op_addl_T1_im (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword im) { GEN_OP (*tbpp, *plen, op_addl_T1_im); //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, &im, sizeof(im)); *tbpp += sizeof(im); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (im); } #endif //_ARM2X86_DP_H_ ������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_mul.c��������������������������������������������������������0000644�0001750�0000144�00000004242�10541455476�017113� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" uint8_t * get_op_mul_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mul_T0_T1"); T0 = T0 * T1; OP_END ("get_op_mul_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_umull_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_umull_T0_T1"); __asm__ __volatile__ ("movl %" AREG_T0 ", %eax"); __asm__ __volatile__ ("mull %" AREG_T1); __asm__ __volatile__ ("movl %eax, %" AREG_T0); __asm__ __volatile__ ("movl %edx, %" AREG_T1); OP_END ("get_op_umull_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_smull_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_smull_T0_T1"); __asm__ __volatile__ ("movl %" AREG_T0 ", %eax"); __asm__ __volatile__ ("imull %" AREG_T1); __asm__ __volatile__ ("movl %eax, %" AREG_T0); __asm__ __volatile__ ("movl %edx, %" AREG_T1); OP_END ("get_op_smull_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } op_table_t op_mul_T0_T1; op_table_t op_umull_T0_T1; op_table_t op_smull_T0_T1; int arm2x86_mul_init () { op_mul_T0_T1.op = get_op_mul_T0_T1 (&op_mul_T0_T1.len); if (op_mul_T0_T1.len <= 0) return (-1); op_umull_T0_T1.op = get_op_umull_T0_T1 (&op_umull_T0_T1.len); if (op_umull_T0_T1.len <= 0) return (-1); op_smull_T0_T1.op = get_op_smull_T0_T1 (&op_smull_T0_T1.len); if (op_smull_T0_T1.len <= 0) return (-1); return (0); } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/list.h���������������������������������������������������������������0000644�0001750�0000144�00000003554�10541455476�016014� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _LIST_H_ #define _LIST_H_ struct list_head { struct list_head *next, *prev; }; #define LIST_HEAD_INIT(name) { &(name), &(name) } #define LIST_HEAD(name) \ struct list_head name = LIST_HEAD_INIT(name) #define INIT_LIST_HEAD(ptr) do { \ (ptr)->next = (ptr); (ptr)->prev = (ptr); \ } while (0) #define list_for_each_safe(pos, n, head) \ for (pos = (head)->next, n = pos->next; pos != (head); \ pos = n, n = pos->next) #define list_entry(ptr, type, member) \ ((type *)((char *)(ptr)-(unsigned int)(&((type *)0)->member))) static __inline__ void __list_add (struct list_head *new, struct list_head *prev, struct list_head *next) { next->prev = new; new->next = next; new->prev = prev; prev->next = new; } static __inline__ void list_add_tail (struct list_head *new, struct list_head *head) { __list_add (new, head->prev, head); } static __inline__ void __list_del (struct list_head *prev, struct list_head *next) { next->prev = prev; prev->next = next; } static __inline__ void list_del_init (struct list_head *entry) { __list_del (entry->prev, entry->next); INIT_LIST_HEAD (entry); } static __inline__ int list_empty (struct list_head *head) { return head->next == head; } #endif //_LIST_H_ ����������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/tb.h�����������������������������������������������������������������0000644�0001750�0000144�00000006404�10541455476�015443� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _TB_H_ #define _TB_H_ #define ALIGN(val,align) (val - val % align) #define TB_INSN_LEN_MAX tb_insn_len_max //teawater change align to make speed up 2005.07.22----------------------------- //teawater change TB_LEN to 512 2005.10.10-------------------------------------- //#define TB_LEN (1 << 8) //256 #define TB_LEN (1 << 10) //1024 //AJ2D-------------------------------------------------------------------------- #define TB_ALIGN(a) (a & (~(TB_LEN - 1))) //AJ2D-------------------------------------------------------------------------- #define TB_TBP_MAX (TB_LEN / sizeof(ARMword) * TB_INSN_LEN_MAX + op_return.len) //teawater add tb_insn_addr 2005.10.06------------------------------------------ //#define TB_TBT_CACHE_MAX 8 //AJ2D-------------------------------------------------------------------------- #define TB_TBP_DEFAULT (1024 * 1024 * 64) typedef struct tb_cache_s { struct list_head list; ARMword addr; uint8_t *tp; } tb_cache_t; typedef struct tb_s { //teawater add for new tb manage function 2005.07.10---------------------------- struct list_head list; //AJ2D-------------------------------------------------------------------------- int ted; //0 not translated 1 already translated //teawater add tb_insn_addr 2005.10.06------------------------------------------ //struct list_head cache[TB_TBT_CACHE_MAX]; //if set ted = 0 must clear it uint8_t *insn_addr[TB_LEN / sizeof(uint8_t *)]; //AJ2D-------------------------------------------------------------------------- //teawater add for new tb manage function 2005.07.10---------------------------- uint8_t *tbp; ARMword addr; //AJ2D-------------------------------------------------------------------------- //teawater change for if trap translate stop 2005.07.23------------------------- ARMword tran_addr; uint8_t *tbp_now; //AJ2D-------------------------------------------------------------------------- //teawater add last use addr 2005.10.10----------------------------------------- ARMword last_addr; uint8_t *last_tbp; //AJ2D-------------------------------------------------------------------------- //teawater change for local tb branch directly jump 2005.10.17------------------ ARMword ret_addr; //AJ2D-------------------------------------------------------------------------- } tb_t; extern int tb_insn_len_max; extern uint8_t *tb_find (ARMul_State * state, ARMword addr); extern int tb_insn_len_max_init (ARMul_State * state); #ifndef TEA_OUT //#define TEA_DEBUG #ifdef TEA_DEBUG #define TEA_OUT(a) a #else #define TEA_OUT(a) #endif #endif #endif //_TB_H_ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_mem.h��������������������������������������������������������0000644�0001750�0000144�00000005642�10541455476�017106� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_MEM_H_ #define _ARM2X86_MEM_H_ #define LOADWORD_ALIGN(addr, data) ((data >> ((addr & 3) << 3)) | (data << (32 - ((addr & 3) << 3)))) extern op_table_t op_ldr_T0_T1; extern op_table_t op_ldr_T2_T1; extern op_table_t op_ldrh_T0_T1; extern op_table_t op_ldrb_T0_T1; extern op_table_t op_ldrb_T2_T1; extern op_table_t op_str_T0_T1; extern op_table_t op_strh_T0_T1; extern op_table_t op_strb_T0_T1; extern op_table_t op_ldm_T1_T0; extern op_table_t op_stm_T1_T0; extern op_table_t op_ldm_user_T1_T0; extern op_table_t op_stm_user_T1_T0; extern op_table_t op_signextend_halfword_T0; extern op_table_t op_signextend_byte_T0; //teawater add for xscale(arm v5) 2005.09.19------------------------------------ extern op_table_t op_signextend_halfword_T1; extern op_table_t op_signextend_byte_T1; extern op_table_t op_ldrd_T0_T2_T1; extern op_table_t op_strd_T0_T2_T1; //AJ2D-------------------------------------------------------------------------- extern int arm2x86_mem_init (); static __inline__ void gen_op_add_datah_offset (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword insn) { if (insn & (1 << 22)) { //immediate int val = (insn & 0xf) | ((insn >> 4) & 0xf0); if (!(insn & (1 << 23))) val = -val; if (val != 0) gen_op_addl_T1_im (state, tbpp, plen, (ARMword) val); } else { //register ARMword rm = (insn) & 0xf; gen_op_movl_Tx_reg (state, tbpp, plen, 2, rm); if (!(insn & (1 << 23))) GEN_OP (*tbpp, *plen, op_subl_T1_T2); else GEN_OP (*tbpp, *plen, op_addl_T1_T2); } } static __inline__ void gen_op_add_data_offset (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword insn) { if (!(insn & (1 << 25))) { //immediate int val = insn & 0xfff; if (!(insn & (1 << 23))) //U val = -val; if (val != 0) gen_op_addl_T1_im (state, tbpp, plen, (ARMword) val); } else { //register ARMword rm = (insn) & 0xf; ARMword shift = (insn >> 7) & 0x1f; gen_op_movl_Tx_reg (state, tbpp, plen, 2, rm); if (shift != 0) gen_op_shift_T2_im (state, tbpp, plen, ((insn >> 5) & 3), shift); if (!(insn & (1 << 23))) //U GEN_OP (*tbpp, *plen, op_subl_T1_T2); else GEN_OP (*tbpp, *plen, op_addl_T1_T2); } } #endif //_ARM2X86_MEM_H_ ����������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_coproc.c�����������������������������������������������������0000644�0001750�0000144�00000026514�10541455476�017611� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" //-------------------------------------------------------------------------------------------------- void tea_ldc (ARMul_State * state, uint32_t insn, uint32_t address) { ARMword cp_num = (insn >> 8) & 0xf; unsigned cpab; ARMword data; if (!CP_ACCESS_ALLOWED (state, cp_num)) { state->trap = TRAP_INSN_UNDEF; return; } cpab = (state->LDC[cp_num]) (state, ARMul_FIRST, insn, 0); while (cpab == ARMul_BUSY) { //XXX teawater:howto deal with it ? //ARMul_Icycles(state, 1, 0); if (arm2x86_exception (state)) { cpab = (state->LDC[cp_num]) (state, ARMul_INTERRUPT, insn, 0); return; } cpab = (state->LDC[cp_num]) (state, ARMul_BUSY, insn, 0); } if (cpab == ARMul_CANT) { state->trap = TRAP_INSN_UNDEF; return; } cpab = (state->LDC[cp_num]) (state, ARMul_TRANSFER, insn, 0); //XXX teawater:howto deal with BUSUSEDINCPCN ? do { data = ARMul_ReadWord (state, address); if (state->abortSig != LOW) { state->trap = TRAP_DATA_ABORT; return; } cpab = (state->LDC[cp_num]) (state, ARMul_DATA, insn, data); address += 4; } while (cpab == ARMul_INC); } void tea_stc (ARMul_State * state, uint32_t insn, uint32_t address) { ARMword cp_num = (insn >> 8) & 0xf; unsigned cpab; ARMword data; if (!CP_ACCESS_ALLOWED (state, cp_num)) { state->trap = TRAP_INSN_UNDEF; return; } cpab = (state->STC[cp_num]) (state, ARMul_FIRST, insn, &data); while (cpab == ARMul_BUSY) { //XXX teawater:howto deal with it ? //ARMul_Icycles(state, 1, 0); if (arm2x86_exception (state)) { cpab = (state->STC[cp_num]) (state, ARMul_INTERRUPT, insn, 0); return; } cpab = (state->STC[cp_num]) (state, ARMul_BUSY, insn, &data); } if (cpab == ARMul_CANT) { state->trap = TRAP_INSN_UNDEF; return; } //XXX teawater:howto deal with BUSUSEDINCPCN ? do { cpab = (state->STC[cp_num]) (state, ARMul_DATA, insn, &data); ARMul_WriteWord (state, address, data); if (state->abortSig != LOW) { state->trap = TRAP_DATA_ABORT; return; } address += 4; } while (cpab == ARMul_INC); } void tea_mrc (ARMul_State * state, uint32_t insn, uint32_t cp_num) { unsigned cpab; ARMword result = 0; ARMword rd; if (!CP_ACCESS_ALLOWED (state, cp_num)) { state->trap = TRAP_INSN_UNDEF; return; } cpab = (state->MRC[cp_num]) (state, ARMul_FIRST, insn, &result); while (cpab == ARMul_BUSY) { //XXX teawater:howto deal with it ? //ARMul_Icycles(state, 1, 0); if (arm2x86_exception (state)) { cpab = (state->MRC[cp_num]) (state, ARMul_INTERRUPT, insn, 0); return; } cpab = (state->MRC[cp_num]) (state, ARMul_BUSY, insn, &result); } if (cpab == ARMul_CANT) { state->trap = TRAP_INSN_UNDEF; return; } //XXX teawater:howto deal with BUSUSEDINCPCN and so on ? rd = (insn >> 12) & 0xf; if (rd == 15) { st->Reg[15] = (result & (~3)) + 4; state->trap = TRAP_SET_R15; } else { state->Reg[rd] = result; } } void tea_mcr (ARMul_State * state, uint32_t insn, uint32_t cp_num) { unsigned cpab; ARMword source; if (!CP_ACCESS_ALLOWED (state, cp_num)) { state->trap = TRAP_INSN_UNDEF; return; } source = state->Reg[(insn >> 12) & 0xf]; cpab = (state->MCR[cp_num]) (state, ARMul_FIRST, insn, source); while (cpab == ARMul_BUSY) { //XXX teawater:howto deal with it ? //ARMul_Icycles(state, 1, 0); if (arm2x86_exception (state)) { cpab = (state->MCR[cp_num]) (state, ARMul_INTERRUPT, insn, 0); return; } cpab = (state->MCR[cp_num]) (state, ARMul_BUSY, insn, source); } if (cpab == ARMul_CANT) { state->trap = TRAP_INSN_UNDEF; return; } //XXX teawater:howto deal with BUSUSEDINCPCN and so on ? } void tea_cdp (ARMul_State * state, uint32_t insn, uint32_t cp_num) { unsigned cpab; if (!CP_ACCESS_ALLOWED (state, cp_num)) { state->trap = TRAP_INSN_UNDEF; return; } cpab = (state->CDP[cp_num]) (state, ARMul_FIRST, insn); while (cpab == ARMul_BUSY) { //XXX teawater:howto deal with it ? //ARMul_Icycles(state, 1, 0); if (arm2x86_exception (state)) { cpab = (state->CDP[cp_num]) (state, ARMul_INTERRUPT, insn); return; } cpab = (state->CDP[cp_num]) (state, ARMul_BUSY, insn); } if (cpab == ARMul_CANT) { state->trap = TRAP_INSN_UNDEF; return; } //XXX teawater:howto deal with BUSUSEDINCPCN and so on ? } //teawater add for xscale(arm v5) 2005.09.12------------------------------------ uint8_t * get_op_mar_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mar_T0_T1"); if (T1 & 0x80) { T1 |= 0xffffff00; } else { T1 &= 0xff; } st->Accumulator = (ARMdword) T0 + (((ARMdword) T1) << 32); OP_END ("get_op_mar_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_mra_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mra_T0_T1"); T0 = (uint32_t) (st->Accumulator & 0xffffffff); T1 = ((uint32_t) (st->Accumulator >> 32)) & 0xff; if (T1 & 0x80) { T1 |= 0xffffff00; } OP_END ("get_op_mra_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_mia_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mia_T0_T1"); if (T1 & 0x80) { T1 |= 0xffffff00; } else { T1 &= 0xff; } st->Accumulator += (ARMdword) T0 + (((ARMdword) T1) << 32); OP_END ("get_op_mia_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_miaph_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_miaph_T0_T1"); T2 = (uint32_t) ((int32_t) ((int16_t) (T0 >> 16)) * (int32_t) ((int16_t) (T1 >> 16))); if (T2 & 0x80000000) { st->Accumulator += 0xffffffff00000000; } st->Accumulator += (ARMdword) T2; T2 = (uint32_t) ((int32_t) ((int16_t) (T0 & 0xffff)) * (int32_t) ((int16_t) (T1 & 0xffff))); if (T2 & 0x80000000) { st->Accumulator += 0xffffffff00000000; } st->Accumulator += (ARMdword) T2; OP_END ("get_op_miaph_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_miaxy_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_miaxy_T0_T1"); T2 = (uint32_t) ((int32_t) T0 * (int32_t) T1); if (T2 & 0x80000000) { st->Accumulator += 0xffffffff00000000; } st->Accumulator += (ARMdword) T2; OP_END ("get_op_miaxy_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } op_table_t op_mar_T0_T1; op_table_t op_mra_T0_T1; op_table_t op_mia_T0_T1; op_table_t op_miaph_T0_T1; op_table_t op_miaxy_T0_T1; //AJ2D-------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------- uint8_t * get_op_ldc_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldc_T0_T1"); //tea_ldc(st, T0, T1); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_st); T2 = (uint32_t) tea_ldc; __asm__ __volatile__ ("call *%" AREG_T2); __asm__ __volatile__ ("addl $0x10, %esp"); if (st->trap) { __asm__ __volatile__ ("ret"); } OP_END ("get_op_ldc_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_stc_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_stc_T0_T1"); //tea_stc(st, T0, T1); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_st); T2 = (uint32_t) tea_stc; __asm__ __volatile__ ("call *%" AREG_T2); __asm__ __volatile__ ("addl $0x10, %esp"); if (st->trap) { __asm__ __volatile__ ("ret"); } OP_END ("get_op_stc_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_mrc_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mrc_T0_T1"); //tea_mrc(st, T0, T1); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_st); T2 = (uint32_t) tea_mrc; __asm__ __volatile__ ("call *%" AREG_T2); __asm__ __volatile__ ("addl $0x10, %esp"); if (st->trap) { __asm__ __volatile__ ("ret"); } OP_END ("get_op_mrc_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_mcr_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mcr_T0_T1"); //tea_mcr(st, T0, T1); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_st); T2 = (uint32_t) tea_mcr; __asm__ __volatile__ ("call *%" AREG_T2); __asm__ __volatile__ ("addl $0x10, %esp"); if (st->trap) { __asm__ __volatile__ ("ret"); } OP_END ("get_op_mcr_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_cdp_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_cdp_T0_T1"); //tea_cdp(st, T0, T1); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_st); T2 = (uint32_t) tea_cdp; __asm__ __volatile__ ("call *%" AREG_T2); __asm__ __volatile__ ("addl $0x10, %esp"); if (st->trap) { __asm__ __volatile__ ("ret"); } OP_END ("get_op_cdp_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } op_table_t op_ldc_T0_T1; op_table_t op_stc_T0_T1; op_table_t op_mrc_T0_T1; op_table_t op_mcr_T0_T1; op_table_t op_cdp_T0_T1; //-------------------------------------------------------------------------------------------------- int arm2x86_coproc_init () { op_ldc_T0_T1.op = get_op_ldc_T0_T1 (&op_ldc_T0_T1.len); if (op_ldc_T0_T1.len <= 0) return (-1); op_stc_T0_T1.op = get_op_stc_T0_T1 (&op_stc_T0_T1.len); if (op_stc_T0_T1.len <= 0) return (-1); op_mrc_T0_T1.op = get_op_mrc_T0_T1 (&op_mrc_T0_T1.len); if (op_mrc_T0_T1.len <= 0) return (-1); op_mcr_T0_T1.op = get_op_mcr_T0_T1 (&op_mcr_T0_T1.len); if (op_mcr_T0_T1.len <= 0) return (-1); op_cdp_T0_T1.op = get_op_cdp_T0_T1 (&op_cdp_T0_T1.len); if (op_cdp_T0_T1.len <= 0) return (-1); //teawater add for xscale(arm v5) 2005.09.12------------------------------------ op_mar_T0_T1.op = get_op_mar_T0_T1 (&op_mar_T0_T1.len); if (op_mar_T0_T1.len <= 0) return (-1); op_mra_T0_T1.op = get_op_mra_T0_T1 (&op_mra_T0_T1.len); if (op_mra_T0_T1.len <= 0) return (-1); op_mia_T0_T1.op = get_op_mia_T0_T1 (&op_mia_T0_T1.len); if (op_mia_T0_T1.len <= 0) return (-1); op_miaph_T0_T1.op = get_op_miaph_T0_T1 (&op_miaph_T0_T1.len); if (op_miaph_T0_T1.len <= 0) return (-1); op_miaxy_T0_T1.op = get_op_miaxy_T0_T1 (&op_miaxy_T0_T1.len); if (op_miaxy_T0_T1.len <= 0) return (-1); //AJ2D-------------------------------------------------------------------------- return (0); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_self.h�������������������������������������������������������0000644�0001750�0000144�00000003052�10541455476�017252� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_SELF_H_ #define _ARM2X86_SELF_H_ #define AREG_st "ebp" #define AREG_T0 "ebx" #define AREG_T1 "esi" #define AREG_T2 "edi" register ARMul_State *st asm (AREG_st); //register struct ARMul_State *st asm(AREG_st); register uint32_t T0 asm (AREG_T0); register uint32_t T1 asm (AREG_T1); register uint32_t T2 asm (AREG_T2); #define NFLAG_reg st->NFlag #define ZFLAG_reg st->ZFlag #define CFLAG_reg st->CFlag #define VFLAG_reg st->VFlag //teawater change for debug function 2005.07.26--------------------------------- #define QFLAG_reg st->SFlag //AJ2D-------------------------------------------------------------------------- #define CP_ACCESS_ALLOWED(STATE, CP) \ ( ((CP) >= 14) \ || (! (STATE)->is_XScale) \ || (xscale_cp15_cp_access_allowed(STATE,15,CP))) #endif //_ARM2X86_SELF_H_ ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_psr.c��������������������������������������������������������0000644�0001750�0000144�00000024270�10541455476�017125� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" //-------------------------------------------------------------------------------------------------- uint8_t * get_op_set_nf (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_set_nf"); st->Cpsr &= ~((unsigned) 1L << NBIT_SHIFT); st->Cpsr ^= NFLAG_reg << NBIT_SHIFT; OP_END ("get_op_set_nf"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_set_zf (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_set_zf"); st->Cpsr &= ~((unsigned) 1L << ZBIT_SHIFT); st->Cpsr ^= ZFLAG_reg << ZBIT_SHIFT; OP_END ("get_op_set_zf"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_set_cf (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_set_cf"); st->Cpsr &= ~((unsigned) 1L << CBIT_SHIFT); st->Cpsr ^= CFLAG_reg << CBIT_SHIFT; OP_END ("get_op_set_cf"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_set_vf (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_set_vf"); st->Cpsr &= ~((unsigned) 1L << VBIT_SHIFT); st->Cpsr ^= VFLAG_reg << VBIT_SHIFT; OP_END ("get_op_set_vf"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_set_nzcf (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_set_nzcf"); st->Cpsr &= ((~FLAG_MASK) | ((unsigned) 1L << VBIT_SHIFT)); st->Cpsr ^= ((NFLAG_reg << NBIT_SHIFT) | (ZFLAG_reg << ZBIT_SHIFT) | (CFLAG_reg << CBIT_SHIFT)); OP_END ("get_op_set_nzcf"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_set_nzcvf (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_set_nzcvf"); st->Cpsr &= ~FLAG_MASK; st->Cpsr ^= ((NFLAG_reg << NBIT_SHIFT) | (ZFLAG_reg << ZBIT_SHIFT) | (CFLAG_reg << CBIT_SHIFT) | (VFLAG_reg << VBIT_SHIFT)); OP_END ("get_op_set_nzcvf"); *len = end - begin; return ((uint8_t *) begin); } //teawater add for xscale(arm v5) 2005.09.21------------------------------------ uint8_t * get_op_set_q (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_set_q"); st->Cpsr &= ~0x08000000; st->Cpsr ^= ((QFLAG_reg << 27)); OP_END ("get_op_set_q"); *len = end - begin; return ((uint8_t *) begin); } //AJ2D-------------------------------------------------------------------------- op_table_t op_set_nf; op_table_t op_set_zf; op_table_t op_set_cf; op_table_t op_set_vf; op_table_t op_set_nzcf; op_table_t op_set_nzcvf; //teawater add for xscale(arm v5) 2005.09.21------------------------------------ op_table_t op_set_q; //AJ2D-------------------------------------------------------------------------- int op_set_init () { op_set_nf.op = get_op_set_nf (&op_set_nf.len); if (op_set_nf.len <= 0) return (-1); op_set_zf.op = get_op_set_zf (&op_set_zf.len); if (op_set_zf.len <= 0) return (-1); op_set_cf.op = get_op_set_cf (&op_set_cf.len); if (op_set_cf.len <= 0) return (-1); op_set_vf.op = get_op_set_vf (&op_set_vf.len); if (op_set_vf.len <= 0) return (-1); op_set_nzcf.op = get_op_set_nzcf (&op_set_nzcf.len); if (op_set_nzcf.len <= 0) return (-1); op_set_nzcvf.op = get_op_set_nzcvf (&op_set_nzcvf.len); if (op_set_nzcvf.len <= 0) return (-1); //teawater add for xscale(arm v5) 2005.09.21------------------------------------ op_set_q.op = get_op_set_q (&op_set_q.len); if (op_set_q.len <= 0) return (-1); //AJ2D-------------------------------------------------------------------------- return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_logic_T0_sn (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_logic_T0_sn"); NFLAG_reg = T0 >> 31; OP_END ("get_op_logic_T0_sn"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_logic_T0_sz (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_logic_T0_sz"); ZFLAG_reg = T0 ? 0 : 1; OP_END ("get_op_logic_T0_sz"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_logic_T1_sn (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_logic_T1_sn"); NFLAG_reg = T1 >> 31; OP_END ("get_op_logic_T1_sn"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_logic_T1_sz (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_logic_T1_sz"); ZFLAG_reg = T1 ? 0 : 1; OP_END ("get_op_logic_T1_sz"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_logic_0_sc (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_logic_0_sc"); CFLAG_reg = 0; OP_END ("get_op_logic_0_sc"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_logic_1_sc (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_logic_1_sc"); CFLAG_reg = 1; OP_END ("get_op_logic_1_sc"); *len = end - begin; return ((uint8_t *) begin); } op_table_t op_logic_T0_sn; op_table_t op_logic_T0_sz; op_table_t op_logic_T1_sn; op_table_t op_logic_T1_sz; op_table_t op_logic_0_sc; op_table_t op_logic_1_sc; int op_logic_init () { op_logic_T0_sn.op = get_op_logic_T0_sn (&op_logic_T0_sn.len); if (op_logic_T0_sn.len <= 0) return (-1); op_logic_T0_sz.op = get_op_logic_T0_sz (&op_logic_T0_sz.len); if (op_logic_T0_sz.len <= 0) return (-1); op_logic_T1_sn.op = get_op_logic_T1_sn (&op_logic_T1_sn.len); if (op_logic_T1_sn.len <= 0) return (-1); op_logic_T1_sz.op = get_op_logic_T1_sz (&op_logic_T1_sz.len); if (op_logic_T1_sz.len <= 0) return (-1); op_logic_0_sc.op = get_op_logic_0_sc (&op_logic_0_sc.len); if (op_logic_0_sc.len <= 0) return (-1); op_logic_1_sc.op = get_op_logic_1_sc (&op_logic_1_sc.len); if (op_logic_1_sc.len <= 0) return (-1); return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_logicq_T0_T1_sz (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_logicq_T0_T1_sz"); ZFLAG_reg = (T0 | T1) ? 0 : 1; OP_END ("get_op_logicq_T0_T1_sz"); *len = end - begin; return ((uint8_t *) begin); } op_table_t op_logicq_T0_T1_sz; int op_logicq_init () { op_logicq_T0_T1_sz.op = get_op_logicq_T0_T1_sz (&op_logicq_T0_T1_sz.len); if (op_logicq_T0_T1_sz.len <= 0) return (-1); return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_mrs_T0_cpsr (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mrs_T0_cpsr"); T0 = st->Cpsr; OP_END ("get_op_mrs_T0_cpsr"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_mrs_T0_spsr (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_mrs_T0_spsr"); T0 = st->Cpsr & 0x1f; if (T0 == 0x10 && T0 == 0x1f) { //user mode | System mode ("Accessing the SPSR when in User mode is UNPREDICTABLE. Accessing the SPSR when in System mode is UNPREDICTABLE." arm_arm) st->trap = TRAP_UNPREDICTABLE; __asm__ __volatile__ ("ret"); } T0 = st->Spsr[st->Bank]; OP_END ("get_op_mrs_T0_spsr"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_msr_cpsr_T0_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_msr_cpsr_T0_T1"); //chy 2006-02-16 also should not consider SYSTEM32MODE=1f if ((st->Cpsr & 0x1f) == 0x10 ) { //user mode T0 &= 0xff000000; } st->Cpsr &= ~T0; T1 &= T0; st->Cpsr |= T1; if ((T0 | 0xff000000) != 0) { //set the flag field T2 = st->Cpsr; NFLAG_reg = (T2 >> 28) & 1; ZFLAG_reg = (T2 >> 29) & 1; CFLAG_reg = (T2 >> 30) & 1; VFLAG_reg = T2 >> 31; } if ((T0 | 0x00ffffff) != 0) { //set the control field st->trap = TRAP_SET_CPSR; __asm__ __volatile__ ("ret"); } OP_END ("get_op_msr_cpsr_T0_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_msr_spsr_T0_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_msr_spsr_T0_T1"); st->Spsr[st->Bank] &= ~T0; T1 &= T0; st->Spsr[st->Bank] |= T1; OP_END ("get_op_msr_spsr_T0_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } op_table_t op_mrs_T0_cpsr; op_table_t op_mrs_T0_spsr; op_table_t op_msr_cpsr_T0_T1; op_table_t op_msr_spsr_T0_T1; int op_mrsmsr_init () { op_mrs_T0_cpsr.op = get_op_mrs_T0_cpsr (&op_mrs_T0_cpsr.len); if (op_mrs_T0_cpsr.len <= 0) return (-1); op_mrs_T0_spsr.op = get_op_mrs_T0_spsr (&op_mrs_T0_spsr.len); if (op_mrs_T0_spsr.len <= 0) return (-1); op_msr_cpsr_T0_T1.op = get_op_msr_cpsr_T0_T1 (&op_msr_cpsr_T0_T1.len); if (op_msr_cpsr_T0_T1.len <= 0) return (-1); op_msr_spsr_T0_T1.op = get_op_msr_spsr_T0_T1 (&op_msr_spsr_T0_T1.len); if (op_msr_spsr_T0_T1.len <= 0) return (-1); return (0); } //-------------------------------------------------------------------------------------------------- /*uint8_t * get_op_writesr15(int *len) { unsigned int begin=0, end=0; OP_BEGIN("get_op_writesr15"); if (st->Bank > 0) { st->Cpsr = st->Spsr[st->Bank]; __asm__ __volatile__ ("push %"AREG_st); T0 = (uint32_t)ARMul_CPSRAltered; __asm__ __volatile__ ("call *%"AREG1_T0); __asm__ __volatile__ ("addl $0x4, %esp"); st->trapflags |= __asm__ __volatile__ ("ret"); } OP_END("get_op_writesr15"); *len = end - begin; return((uint8_t *)begin); } op_table_t op_writesr15; int op_writesr15_init() { op_writesr15.op = get_op_writesr15(&op_writesr15.len); return(0); }*/ //-------------------------------------------------------------------------------------------------- int arm2x86_psr_init () { op_set_init (); op_logic_init (); op_logicq_init (); op_mrsmsr_init (); //op_writesr15_init(); return (0); } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_test.h�������������������������������������������������������0000644�0001750�0000144�00000002576�10541455476�017312� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_TEST_H_ #define _ARM2X86_TEST_H_ extern op_table_t op_test_dataabort; extern op_table_t op_test_dataabort_ret; extern op_table_t op_test_cpsr_ret_UNP; //extern op_table_t op_test_debug; extern int arm2x86_test_init (); static __inline__ void gen_op_test_dataabort_im (ARMul_State * state, uint8_t ** tbpp, int *plen, uint32_t im) { GEN_OP (*tbpp, *plen, op_test_dataabort); //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp - sizeof(im), &im, sizeof(im)); //} //AJ2D-------------------------------------------------------------------------- } #endif //_ARM2X86_TEST_H_ ����������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_other.h������������������������������������������������������0000644�0001750�0000144�00000014507�10541455476�017451� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_OTHER_H_ #define _ARM2X86_OTHER_H_ extern op_table_t op_addq_T0_T1_eax_T2; extern op_table_t op_b_offset; extern op_table_t op_bl_offset; //teawater add check thumb 2005.07.21------------------------------------------- extern op_table_t op_bx_T1; extern op_table_t op_blx_T1; //AJ2D-------------------------------------------------------------------------- //teawater add for xscale(arm v5) 2005.09.12------------------------------------ extern op_table_t op_hi_T0; extern op_table_t op_hi_T1; extern op_table_t op_lo_T0; extern op_table_t op_lo_T1; extern op_table_t op_smlalxy_T2_T1_T0; extern op_table_t op_smlawy_T2_T1_T0; extern op_table_t op_smulwy_T0_T1; //AJ2D-------------------------------------------------------------------------- //teawater change for local tb branch directly jump 2005.10.17------------------ extern op_table_t op_local_b_offset; //AJ2D-------------------------------------------------------------------------- typedef void (arm2x86_get_other_op_t) (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen); extern arm2x86_get_other_op_t *arm2x86_get_other_op[16]; extern int arm2x86_other_init (); static __inline__ void gen_op_mrs (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword insn) { if ((insn >> 22) & 1) { //spsr GEN_OP (*tbpp, *plen, op_mrs_T0_spsr); } else { //cpsr GEN_OP (*tbpp, *plen, op_mrs_T0_cpsr); } gen_op_movl_reg_Tx (state, tbpp, plen, ((insn >> 12) & 0xf), 0); } static __inline__ void gen_op_msr (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword insn) { uint32_t mask = 0; //get mask & set it to T0 if ((insn >> 16) & 1) { //control field mask mask |= 0xff; } if ((insn >> 17) & 1) { //extension field mask mask |= 0xff00; } if ((insn >> 18) & 1) { //status field mask mask |= 0xff0000; } if ((insn >> 19) & 1) { //flags field mask mask |= 0xff000000; } if (mask == 0) { return; } gen_op_movl_Tx_im (state, tbpp, plen, 0, mask); if ((insn >> 22) & 1) { //spsr GEN_OP (*tbpp, *plen, op_msr_spsr_T0_T1); } else { //cpsr GEN_OP (*tbpp, *plen, op_msr_cpsr_T0_T1); } } static __inline__ void gen_op_ldrhstrh (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword insn, ARMword sh) { ARMword rn, rd; rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; gen_op_movl_Tx_reg (state, tbpp, plen, 1, rn); if (insn & (1 << 24)) { gen_op_add_datah_offset (state, tbpp, plen, insn); } if (insn & (1 << 20)) { if (sh == 1) { //ldrh GEN_OP (*tbpp, *plen, op_ldrh_T0_T1); } else if (sh == 2) { //ldrsb GEN_OP (*tbpp, *plen, op_ldrb_T0_T1); GEN_OP (*tbpp, *plen, op_signextend_byte_T0); } else { //ldrsh GEN_OP (*tbpp, *plen, op_ldrh_T0_T1); GEN_OP (*tbpp, *plen, op_signextend_halfword_T0); } //if (!state->is_XScale) { if (state->abort_model > 1) { gen_op_test_dataabort_im (state, tbpp, plen, op_movl_reg_Tx[0][rd].len); } gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0); } else { //teawater add for xscale(arm v5) 2005.09.15------------------------------------ if (sh == 1) { //strh gen_op_movl_Tx_reg (state, tbpp, plen, 0, rd); GEN_OP (*tbpp, *plen, op_strh_T0_T1); } else if (state->is_v5) { if (sh == 2 || sh == 3) { if (rd >= 14) { gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_UNPREDICTABLE); state->trap = 1; return; } if (sh == 2) { //ldrd GEN_OP (*tbpp, *plen, op_ldrd_T0_T2_T1); if (state->abort_model > 1) { gen_op_test_dataabort_im (state, tbpp, plen, op_movl_reg_Tx[0] [rd].len + op_movl_reg_Tx[2][rd + 1]. len); } gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0); gen_op_movl_reg_Tx (state, tbpp, plen, rd + 1, 2); } else { //strd gen_op_movl_Tx_reg (state, tbpp, plen, 0, rd); gen_op_movl_Tx_reg (state, tbpp, plen, 2, rd + 1); GEN_OP (*tbpp, *plen, op_strd_T0_T2_T1); } } else { //undef gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_INSN_UNDEF); state->trap = 1; return; } } else { //undef gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_INSN_UNDEF); state->trap = 1; return; } //AJ2D-------------------------------------------------------------------------- } if (!(insn & (1 << 24))) { gen_op_add_datah_offset (state, tbpp, plen, insn); gen_op_movl_reg_Tx (state, tbpp, plen, rn, 1); } else if (insn & (1 << 21)) { gen_op_movl_reg_Tx (state, tbpp, plen, rn, 1); } //if (!state->is_XScale) { if (state->abort_model > 1) { GEN_OP (*tbpp, *plen, op_test_dataabort_ret); } } static __inline__ void gen_op_b_offset (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword offset) { GEN_OP (*tbpp, *plen, op_b_offset); offset += 4; //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, &offset, sizeof(offset)); *tbpp += sizeof(offset); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (offset); state->trap = 1; } static __inline__ void gen_op_bl_offset (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword offset) { GEN_OP (*tbpp, *plen, op_bl_offset); offset += 4; //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, &offset, sizeof(offset)); *tbpp += sizeof(offset); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (offset); state->trap = 1; } #endif //_ARM2X86_OTHER_H_ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86.h������������������������������������������������������������0000644�0001750�0000144�00000011062�10714545461�016235� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_H_ #define _ARM2X86_H_ #include <limits.h> /* typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned int uint32_t; #if defined (__x86_64__) typedef unsigned long uint64_t; #else typedef unsigned long long uint64_t; #endif */ /* typedef signed char int8_t; typedef signed short int16_t; typedef signed int int32_t; #if defined (__x86_64__) typedef signed long int64_t; #else typedef signed long long int64_t; #endif */ //chy 2005-05-11 /*#ifndef __CYGWIN__ #define INT8_MIN (-128) #define INT16_MIN (-32767-1) #define INT32_MIN (-2147483647-1) #define INT64_MIN (-(int64_t)(9223372036854775807)-1) #define INT8_MAX (127) #define INT16_MAX (32767) #define INT32_MAX (2147483647) #define INT64_MAX ((int64_t)(9223372036854775807)) #define UINT8_MAX (255) #define UINT16_MAX (65535) #define UINT32_MAX (4294967295U) #define UINT64_MAX ((uint64_t)(18446744073709551615)) #endif*/ #define TRAP_SET_R15 0x01 #define TRAP_RESET 0x10 #define TRAP_INSN_UNDEF 0x11 #define TRAP_SWI 0x12 #define TRAP_INSN_ABORT 0x13 #define TRAP_DATA_ABORT 0x14 #define TRAP_IRQ 0x15 #define TRAP_FIQ 0x16 #define TRAP_SETS_R15 0x20 #define TRAP_SET_CPSR 0x21 #define TRAP_UNPREDICTABLE 0x22 //teawater change for debug function 2005.07.09--------------------------------- #define TRAP_OUT 0x30 #define TRAP_BREAKPOINT 0x40 //AJ2D-------------------------------------------------------------------------- #define wmb() __asm__ __volatile__ ("": : :"memory") #define OP_BEGIN(f) __asm__ __volatile__ ("jmp ."f"_teawater_op_end\n\t""."f"_teawater_op_begin:\n\t") #define OP_END(f) __asm__ __volatile__ ("."f"_teawater_op_end:\n\t""movl $."f"_teawater_op_begin,%0\n\t""movl $."f"_teawater_op_end,%1\n\t":"=g"(begin), "=g"(end)); //teawater remove tb_translate_find 2005.10.21---------------------------------- //#define GEN_OP(a, l, o) do { if(a) { memcpy(a, o.op, o.len);a += o.len; } l += o.len; } while(0) #define GEN_OP(a, l, o) do { memcpy(a, o.op, o.len);a += o.len; l += o.len; } while(0) //AJ2D-------------------------------------------------------------------------- #define Tx_MAX 2 #define tmp_MAX 0 typedef struct op_table_s { uint8_t *op; int len; } op_table_t; extern const uint8_t table_logic_cc[16]; //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) extern volatile uint32_t arm2x86_pfun; #else extern volatile void (*arm2x86_pfun) (void); #endif extern uint32_t arm2x86_tmp_reg[16]; extern volatile uint32_t arm2x86_tmp0; //teawater add for xscale(arm v5) 2005.09.23------------------------------------ extern volatile uint64_t arm2x86_tmp64; //AJ2D-------------------------------------------------------------------------- extern op_table_t op_writesr15; extern op_table_t op_return; extern op_table_t op_addpc; //extern op_table_t op_fiqirq; extern op_table_t op_begin; extern op_table_t op_begin_test_T0; //teawater change for local tb branch directly jump 2005.10.10------------------ #include "tb.h" typedef struct tb_branch_save_s { struct list_head list; // ARMword addr; ARMword dst_addr; uint8_t *tbp; }tb_branch_save_t; extern struct list_head tb_branch_save_list; extern tb_branch_save_t tb_branch_save[TB_LEN / sizeof(ARMword)]; extern tb_t *now_tbt; //AJ2D-------------------------------------------------------------------------- extern int arm2x86_init (); #ifndef IFLAG #define IFLAG (state->IFFlags >> 1) #endif //IFLAG #ifndef FFLAG #define FFLAG (state->IFFlags & 1) #endif //FFLAG static __inline__ int arm2x86_exception (ARMul_State * state) { //reset if (state->NresetSig == LOW) { state->trap = TRAP_RESET; return (1); } //fiq if (!state->NfiqSig && !FFLAG) { state->trap = TRAP_FIQ; return (1); } //irq if (!state->NirqSig && !IFLAG) { state->trap = TRAP_IRQ; return (1); } return (0); } #endif //_ARM2X86_H_ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86.c������������������������������������������������������������0000644�0001750�0000144�00000020011�10714545461�016222� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" const uint8_t table_logic_cc[16] = { 1, /* and */ 1, /* eor */ 0, /* sub */ 0, /* rsb */ 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */ 1, /* tst */ 1, /* teq */ 0, /* cmp */ 0, /* cmn */ 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */ }; //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) volatile uint32_t arm2x86_pfun; #else volatile void (*arm2x86_pfun) (void); #endif uint32_t arm2x86_tmp_reg[16]; volatile uint32_t arm2x86_tmp0; //teawater add for xscale(arm v5) 2005.09.23------------------------------------ volatile uint64_t arm2x86_tmp64; //AJ2D-------------------------------------------------------------------------- //teawater change for local tb branch directly jump 2005.10.10------------------ struct list_head tb_branch_save_list; tb_branch_save_t tb_branch_save[TB_LEN / sizeof(ARMword)]; tb_t *now_tbt; //AJ2D-------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------- //teawater change for debug function 2005.07.09--------------------------------- static int step_out = 0; /* Values for Emulate. */ #define STOP 0 /* stop */ #define CHANGEMODE 1 /* change mode */ #define ONCE 2 /* execute just one interation */ #define RUN 3 /* continuous execution */ #define INSN_SIZE (state->TFlag ? 2 : 4) static inline int tea_check_out (ARMul_State * state) { //teawater add compile switch for DBCT GDB RSP function 2005.10.21-------------- #ifdef DBCT_GDBRSP if (state->tea_break_ok && state->Reg[15] == state->tea_break_addr + 4) { ARMul_Debug (state, 0, 0); state->tea_break_ok = 0; } else { state->tea_break_ok = 1; } //step if (state->Emulate == ONCE) { if (step_out) { step_out = 0; //state->trap = TRAP_OUT; //state->Emulate = STOP; return (1); } else { step_out = 1; } } else if (state->Emulate != RUN) { //state->trap = TRAP_OUT; return (1); } if (state->tea_pc) { int i; if (state->tea_reg_fd) { fprintf (state->tea_reg_fd, "\n"); for (i = 0; i < 15; i++) { fprintf (state->tea_reg_fd, "%x,", state->Reg[i]); } fprintf (state->tea_reg_fd, "%x,", state->Reg[15] - INSN_SIZE); fprintf (state->tea_reg_fd, "%x\n", state->Cpsr); } else { printf ("\n"); for (i = 0; i < 15; i++) { printf ("%x,", state->Reg[i]); } printf ("%x,", state->Reg[15] - INSN_SIZE); printf ("%x\n", state->Cpsr); } } //fprintf(fd, "------------\npc:%x\n", state->Reg[15] - INSN_SIZE); #endif //DBCT_GDBRSP //AJ2D-------------------------------------------------------------------------- //exception if (arm2x86_exception (state)) { return (1); } //teawater change for return if running tb dirty 2005.07.09--------------------- if (((tb_t *) (state->tb_now))->ted == 0) { return (1); } //AJ2D-------------------------------------------------------------------------- //do io io_do_cycle (state); return (0); } uint32_t tea_begin (ARMul_State * state) { if (tea_check_out (state)) { return (ULONG_MAX); } return (0); } extern int stop_simulator; uint32_t tea_begin_test (ARMul_State * state, uint32_t cond) { if (tea_check_out (state)) { return (ULONG_MAX); } //test_op return (gen_op_condition (state, cond)); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_writesr15 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_writesr15"); st->trap = TRAP_SETS_R15; OP_END ("get_op_writesr15"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_return (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_return"); __asm__ __volatile__ ("ret"); OP_END ("get_op_return"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_addpc (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_addpc"); st->Reg[15] += 4; OP_END ("get_op_addpc"); *len = end - begin; return ((uint8_t *) begin); } /* uint8_t * get_op_fiqirq(int *len) { unsigned int begin=0,end=0; OP_BEGIN("get_op_fiqirq"); if (!FFLAG && !st->NfiqSig) { st->trap = TRAP_FIQ; __asm__ __volatile__ ("ret"); } if (!IFLAG && !st->NirqSig) { st->trap = TRAP_IRQ; __asm__ __volatile__ ("ret"); } //io_do_cycle(st); __asm__ __volatile__ ("subl $0xc, %esp"); __asm__ __volatile__ ("push %"AREG_st); arm2x86_pfun = (uint32_t)io_do_cycle; __asm__ __volatile__ ("call *arm2x86_pfun"); __asm__ __volatile__ ("addl $0x10, %esp"); OP_END("get_op_fiqirq"); *len = end - begin; return((uint8_t *)begin); } */ uint8_t * get_op_begin (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_begin"); //T0 = tea_begin(st); __asm__ __volatile__ ("subl $0xc, %esp"); __asm__ __volatile__ ("push %" AREG_st); T2 = (uint32_t) tea_begin; __asm__ __volatile__ ("call *%" AREG_T2); __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T0); if (T0) { __asm__ __volatile__ ("ret"); } OP_END ("get_op_begin"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_begin_test_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_begin_test_T0"); //T0 = tea_begin_test(st, T0); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_st); T2 = (uint32_t) tea_begin_test; __asm__ __volatile__ ("call *%" AREG_T2); __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T0); if (T0 == ULONG_MAX) { __asm__ __volatile__ ("ret"); } if (!T0) { __asm__ __volatile__ ("jmp 0xffffffff"); } OP_END ("get_op_begin_test_T0"); *len = end - begin; return ((uint8_t *) begin); } op_table_t op_writesr15; op_table_t op_return; op_table_t op_addpc; //op_table_t op_fiqirq; op_table_t op_begin; op_table_t op_begin_test_T0; int op_init () { op_writesr15.op = get_op_writesr15 (&op_writesr15.len); if (op_writesr15.len <= 0) return (-1); op_return.op = get_op_return (&op_return.len); if (op_return.len <= 0) return (-1); op_addpc.op = get_op_addpc (&op_addpc.len); if (op_addpc.len <= 0) return (-1); op_begin.op = get_op_begin (&op_begin.len); if (op_begin.len <= 0) return (-1); op_begin_test_T0.op = get_op_begin_test_T0 (&op_begin_test_T0.len); if (op_begin_test_T0.len <= 0) return (-1); return (0); } //-------------------------------------------------------------------------------------------------- int arm2x86_init (ARMul_State * state) { if (op_init ()) { return (-1); } if (arm2x86_test_init ()) { return (-1); } if (arm2x86_shift_init ()) { return (-1); } if (arm2x86_psr_init ()) { return (-1); } if (arm2x86_movl_init ()) { return (-1); } if (arm2x86_mul_init ()) { return (-1); } if (arm2x86_mem_init ()) { return (-1); } if (arm2x86_other_init ()) { return (-1); } if (arm2x86_dp_init ()) { return (-1); } if (arm2x86_coproc_init ()) { return (-1); } if (tb_insn_len_max_init (state)) { return (-1); } //teawater add for new tb manage function 2005.07.10---------------------------- if (tb_memory_init (state)) { return (-1); } //AJ2D-------------------------------------------------------------------------- return (0); } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_dp.c���������������������������������������������������������0000644�0001750�0000144�00000044214�10541455476�016724� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" uint8_t * get_op_andl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_andl_T0_T1"); T0 &= T1; OP_END ("get_op_andl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_eorl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_eorl_T0_T1"); T0 ^= T1; OP_END ("get_op_eorl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_subl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_subl_T0_T1"); T0 -= T1; OP_END ("get_op_subl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_subl_T0_T1_scv (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_subl_T0_T1_scv"); T2 = T0 - T1; //CFLAG_reg = (T0<T1)?1:0; CFLAG_reg = (T0 >= T1) ? 1 : 0; //chy 2006-02-12 chage ! to ~ //VFLAG_reg = !(T2 ^ T1); VFLAG_reg = ~(T2 ^ T1); VFLAG_reg &= (T0 ^ T1); VFLAG_reg >>= 31; T0 = T2; OP_END ("get_op_subl_T0_T1_scv"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_rsbl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_rsbl_T0_T1"); T0 = T1 - T0; OP_END ("get_op_rsbl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_rsbl_T0_T1_scv (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_rsbl_T0_T1_scv"); T2 = T1 - T0; //CFLAG_reg = (T1<T0)?1:0; CFLAG_reg = (T1 >= T0) ? 1 : 0; //chy 2006-02-12 chage ! to ~ //VFLAG_reg = !(T2 ^ T0); VFLAG_reg = ~(T2 ^ T0); VFLAG_reg &= (T0 ^ T1); VFLAG_reg >>= 31; T0 = T2; OP_END ("get_op_rsbl_T0_T1_scv"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_addl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_addl_T0_T1"); T0 += T1; OP_END ("get_op_addl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_addl_T0_T1_scv (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_addl_T0_T1_scv"); T2 = T0 + T1; CFLAG_reg = (T2 < T0); VFLAG_reg = ~(T0 ^ T1); VFLAG_reg &= (T2 ^ T1); VFLAG_reg >>= 31; T0 = T2; OP_END ("get_op_addl_T0_T1_scv"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_adcl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_adcl_T0_T1"); T0 += T1 + CFLAG_reg; OP_END ("get_op_adcl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_adcl_T0_T1_scv (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_adcl_T0_T1_scv"); T2 = T0 + T1 + CFLAG_reg; if (!CFLAG_reg) { CFLAG_reg = (T2 < T0); } else { CFLAG_reg = (T2 <= T0); } VFLAG_reg = ~(T0 ^ T1); VFLAG_reg &= (T2 ^ T1); VFLAG_reg >>= 31; T0 = T2; OP_END ("get_op_adcl_T0_T1_scv"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_sbcl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_sbcl_T0_T1"); //T0 -= (T1 + !CFLAG_reg); T0 = T0 - T1 + CFLAG_reg - 1; OP_END ("get_op_sbcl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_sbcl_T0_T1_scv (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_sbcl_T0_T1_scv"); T2 = T0 - T1 + CFLAG_reg - 1; if (!CFLAG_reg) { CFLAG_reg = (T0 > T1); } else { CFLAG_reg = (T0 >= T1); } //chy 2006-02-12 chage ! to ~ //VFLAG_reg = !(T2 ^ T1); VFLAG_reg = ~(T2 ^ T1); VFLAG_reg &= (T0 ^ T1); VFLAG_reg >>= 31; T0 = T2; OP_END ("get_op_sbcl_T0_T1_scv"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_rscl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_rscl_T0_T1"); //T0 = T1 - T0 - !CFLAG_reg; T0 = T1 - T0 + CFLAG_reg - 1; OP_END ("get_op_rscl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_rscl_T0_T1_scv (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_rscl_T0_T1_scv"); T0 += !CFLAG_reg; T2 = T1 - T0; //CFLAG_reg = (T1<T0)?1:0; //CFLAG_reg = (T1 >= T0)?1:0; if (!CFLAG_reg) { CFLAG_reg = (T1 > T0); } else { CFLAG_reg = (T1 >= T0); } //chy 2006-02-12 chage ! to ~ //VFLAG_reg = !(T2 ^ T0); VFLAG_reg = ~(T2 ^ T0); VFLAG_reg &= (T0 ^ T1); VFLAG_reg >>= 31; T0 = T2; OP_END ("get_op_rscl_T0_T1_scv"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_orrl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_orrl_T0_T1"); T0 |= T1; OP_END ("get_op_orrl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_movl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_T1"); T0 = T1; OP_END ("get_op_movl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_bicl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_bicl_T0_T1"); T0 &= ~T1; OP_END ("get_op_bicl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_notl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_notl_T0_T1"); T0 = ~T1; OP_END ("get_op_notl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_addl_T1_im (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_addl_T1_im"); T1 += INT32_MAX; OP_END ("get_op_addl_T1_im"); *len = end - begin; if (*len <= sizeof (ULONG_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } return ((uint8_t *) begin); } uint8_t * get_op_subl_T1_T2 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_subl_T1_T2"); T1 -= T2; OP_END ("get_op_subl_T1_T2"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_addl_T1_T2 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_addl_T1_T2"); T1 += T2; OP_END ("get_op_addl_T1_T2"); *len = end - begin; return ((uint8_t *) begin); } //teawater add for xscale(arm v5) 2005.09.01------------------------------------ uint8_t * get_op_clzl_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_clzl_T0_T1"); //chy 2006-02-12 fix a bug if(T1){ for (T0 = 0; (T1 & 0x80000000) == 0; T1 <<= 1) { T0++; } } OP_END ("get_op_clzl_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_qaddl_T0_T1_sq (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_qaddl_T0_T1_sq"); T2 = T0 + T1; QFLAG_reg = ~(T0 ^ T1); QFLAG_reg &= (T2 ^ T1); QFLAG_reg >>= 31; T0 = T2; if (QFLAG_reg) { T0 = (T0 >> 31) ? 0x7fffffff : 0x80000000; } OP_END ("get_op_qaddl_T0_T1_sq"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_qsubl_T0_T1_sq (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_qsubl_T0_T1_sq"); T2 = T0 - T1; //chy 2006-02-12 chage ! to ~ //QFLAG_reg = !(T2 ^ T1); QFLAG_reg = ~(T2 ^ T1); QFLAG_reg &= (T0 ^ T1); QFLAG_reg >>= 31; T0 = T2; if (QFLAG_reg) { T0 = (T0 >> 31) ? 0x7fffffff : 0x80000000; } OP_END ("get_op_qsubl_T0_T1_sq"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_addl_T0_T1_sq (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_addl_T0_T1_sq"); T2 = T0 + T1; QFLAG_reg = ~(T0 ^ T1); QFLAG_reg &= (T2 ^ T1); QFLAG_reg >>= 31; T0 = T2; OP_END ("get_op_addl_T0_T1_sq"); *len = end - begin; return ((uint8_t *) begin); } //AJ2D-------------------------------------------------------------------------- op_table_t op_andl_T0_T1; op_table_t op_eorl_T0_T1; op_table_t op_subl_T0_T1; op_table_t op_subl_T0_T1_scv; op_table_t op_rsbl_T0_T1; op_table_t op_rsbl_T0_T1_scv; op_table_t op_addl_T0_T1; op_table_t op_addl_T0_T1_scv; op_table_t op_adcl_T0_T1; op_table_t op_adcl_T0_T1_scv; op_table_t op_sbcl_T0_T1; op_table_t op_sbcl_T0_T1_scv; op_table_t op_rscl_T0_T1; op_table_t op_rscl_T0_T1_scv; op_table_t op_orrl_T0_T1; op_table_t op_movl_T0_T1; op_table_t op_bicl_T0_T1; op_table_t op_notl_T0_T1; op_table_t op_addl_T1_im; op_table_t op_subl_T1_T2; op_table_t op_addl_T1_T2; //teawater add for xscale(arm v5) 2005.09.01------------------------------------ op_table_t op_clzl_T0_T1; op_table_t op_qaddl_T0_T1_sq; op_table_t op_qsubl_T0_T1_sq; op_table_t op_addl_T0_T1_sq; //AJ2D-------------------------------------------------------------------------- int op_dp_T0_T1 () { op_andl_T0_T1.op = get_op_andl_T0_T1 (&op_andl_T0_T1.len); if (op_andl_T0_T1.len <= 0) return (-1); op_eorl_T0_T1.op = get_op_eorl_T0_T1 (&op_eorl_T0_T1.len); if (op_eorl_T0_T1.len <= 0) return (-1); op_subl_T0_T1.op = get_op_subl_T0_T1 (&op_subl_T0_T1.len); if (op_subl_T0_T1.len <= 0) return (-1); op_subl_T0_T1_scv.op = get_op_subl_T0_T1_scv (&op_subl_T0_T1_scv.len); if (op_subl_T0_T1_scv.len <= 0) return (-1); op_rsbl_T0_T1.op = get_op_rsbl_T0_T1 (&op_rsbl_T0_T1.len); if (op_rsbl_T0_T1.len <= 0) return (-1); op_rsbl_T0_T1_scv.op = get_op_rsbl_T0_T1_scv (&op_rsbl_T0_T1_scv.len); if (op_rsbl_T0_T1_scv.len <= 0) return (-1); op_addl_T0_T1.op = get_op_addl_T0_T1 (&op_addl_T0_T1.len); if (op_addl_T0_T1.len <= 0) return (-1); op_addl_T0_T1_scv.op = get_op_addl_T0_T1_scv (&op_addl_T0_T1_scv.len); if (op_addl_T0_T1_scv.len <= 0) return (-1); op_adcl_T0_T1.op = get_op_adcl_T0_T1 (&op_adcl_T0_T1.len); if (op_adcl_T0_T1.len <= 0) return (-1); op_adcl_T0_T1_scv.op = get_op_adcl_T0_T1_scv (&op_adcl_T0_T1_scv.len); if (op_adcl_T0_T1_scv.len <= 0) return (-1); op_sbcl_T0_T1.op = get_op_sbcl_T0_T1 (&op_sbcl_T0_T1.len); if (op_sbcl_T0_T1.len <= 0) return (-1); op_sbcl_T0_T1_scv.op = get_op_sbcl_T0_T1_scv (&op_sbcl_T0_T1_scv.len); if (op_sbcl_T0_T1_scv.len <= 0) return (-1); op_rscl_T0_T1.op = get_op_rscl_T0_T1 (&op_rscl_T0_T1.len); if (op_rscl_T0_T1.len <= 0) return (-1); op_rscl_T0_T1_scv.op = get_op_rscl_T0_T1_scv (&op_rscl_T0_T1_scv.len); if (op_rscl_T0_T1_scv.len <= 0) return (-1); op_orrl_T0_T1.op = get_op_orrl_T0_T1 (&op_orrl_T0_T1.len); if (op_orrl_T0_T1.len <= 0) return (-1); op_movl_T0_T1.op = get_op_movl_T0_T1 (&op_movl_T0_T1.len); if (op_movl_T0_T1.len <= 0) return (-1); op_bicl_T0_T1.op = get_op_bicl_T0_T1 (&op_bicl_T0_T1.len); if (op_bicl_T0_T1.len <= 0) return (-1); op_notl_T0_T1.op = get_op_notl_T0_T1 (&op_notl_T0_T1.len); if (op_notl_T0_T1.len <= 0) return (-1); op_addl_T1_im.op = get_op_addl_T1_im (&op_addl_T1_im.len); if (op_addl_T1_im.len <= 0) return (-1); op_subl_T1_T2.op = get_op_subl_T1_T2 (&op_subl_T1_T2.len); if (op_subl_T1_T2.len <= 0) return (-1); op_addl_T1_T2.op = get_op_addl_T1_T2 (&op_addl_T1_T2.len); if (op_addl_T1_T2.len <= 0) return (-1); //teawater add for xscale(arm v5) 2005.09.01------------------------------------ op_clzl_T0_T1.op = get_op_clzl_T0_T1 (&op_clzl_T0_T1.len); if (op_clzl_T0_T1.len <= 0) return (-1); op_qaddl_T0_T1_sq.op = get_op_qaddl_T0_T1_sq (&op_qaddl_T0_T1_sq.len); if (op_qaddl_T0_T1_sq.len <= 0) return (-1); op_qsubl_T0_T1_sq.op = get_op_qsubl_T0_T1_sq (&op_qsubl_T0_T1_sq.len); if (op_qsubl_T0_T1_sq.len <= 0) return (-1); op_addl_T0_T1_sq.op = get_op_addl_T0_T1_sq (&op_addl_T0_T1_sq.len); if (op_addl_T0_T1_sq.len <= 0) return (-1); //AJ2D-------------------------------------------------------------------------- return (0); } //-------------------------------------------------------------------------------------------------- void arm2x86_get_op_and (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { GEN_OP (*tbpp, *plen, op_andl_T0_T1); } void arm2x86_get_op_eor (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { GEN_OP (*tbpp, *plen, op_eorl_T0_T1); } void arm2x86_get_op_sub (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { GEN_OP (*tbpp, *plen, op_subl_T0_T1_scv); } else { GEN_OP (*tbpp, *plen, op_subl_T0_T1); } } void arm2x86_get_op_rsb (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { GEN_OP (*tbpp, *plen, op_rsbl_T0_T1_scv); } else { GEN_OP (*tbpp, *plen, op_rsbl_T0_T1); } } void arm2x86_get_op_add (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { GEN_OP (*tbpp, *plen, op_addl_T0_T1_scv); } else { GEN_OP (*tbpp, *plen, op_addl_T0_T1); } } void arm2x86_get_op_adc (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { GEN_OP (*tbpp, *plen, op_adcl_T0_T1_scv); } else { GEN_OP (*tbpp, *plen, op_adcl_T0_T1); } } void arm2x86_get_op_sbc (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { GEN_OP (*tbpp, *plen, op_sbcl_T0_T1_scv); } else { GEN_OP (*tbpp, *plen, op_sbcl_T0_T1); } } void arm2x86_get_op_rsc (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { GEN_OP (*tbpp, *plen, op_rscl_T0_T1_scv); } else { GEN_OP (*tbpp, *plen, op_rscl_T0_T1); } } void arm2x86_get_op_tst (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc) { GEN_OP (*tbpp, *plen, op_andl_T0_T1); } } void arm2x86_get_op_teq (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc) { GEN_OP (*tbpp, *plen, op_eorl_T0_T1); } } void arm2x86_get_op_cmp (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc) { GEN_OP (*tbpp, *plen, op_subl_T0_T1_scv); } } void arm2x86_get_op_cmn (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc) { GEN_OP (*tbpp, *plen, op_addl_T0_T1_scv); } } void arm2x86_get_op_orr (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { GEN_OP (*tbpp, *plen, op_orrl_T0_T1); } void arm2x86_get_op_mov (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { GEN_OP (*tbpp, *plen, op_movl_T0_T1); } void arm2x86_get_op_bic (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { GEN_OP (*tbpp, *plen, op_bicl_T0_T1); } void arm2x86_get_op_mvn (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { GEN_OP (*tbpp, *plen, op_notl_T0_T1); } arm2x86_get_dp_op_t *arm2x86_get_dp_op[16] = { arm2x86_get_op_and, arm2x86_get_op_eor, arm2x86_get_op_sub, arm2x86_get_op_rsb, arm2x86_get_op_add, arm2x86_get_op_adc, arm2x86_get_op_sbc, arm2x86_get_op_rsc, arm2x86_get_op_tst, arm2x86_get_op_teq, arm2x86_get_op_cmp, arm2x86_get_op_cmn, arm2x86_get_op_orr, arm2x86_get_op_mov, arm2x86_get_op_bic, arm2x86_get_op_mvn, }; void arm2x86_get_op_setcpsr_nzc (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc) { //set cpsr nf GEN_OP (*tbpp, *plen, op_logic_T0_sn); //GEN_OP(*tbpp, *plen, op_set_nf); //set cpsr zf GEN_OP (*tbpp, *plen, op_logic_T0_sz); //GEN_OP(*tbpp, *plen, op_set_zf); //set cpsr cf //GEN_OP(*tbpp, *plen, op_set_cf); GEN_OP (*tbpp, *plen, op_set_nzcf); } } void arm2x86_get_op_setcpsr_nzc_setreg (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { //set cpsr nf GEN_OP (*tbpp, *plen, op_logic_T0_sn); //GEN_OP(*tbpp, *plen, op_set_nf); //set cpsr zf GEN_OP (*tbpp, *plen, op_logic_T0_sz); //GEN_OP(*tbpp, *plen, op_set_zf); //set cpsr cf //GEN_OP(*tbpp, *plen, op_set_cf); GEN_OP (*tbpp, *plen, op_set_nzcf); } gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0); if (rd == 15 && set_cc) { //change pc & set spsr to cpsr gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_SETS_R15); } } void arm2x86_get_op_setcpsr_nzcv (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc) { //set cpsr nf GEN_OP (*tbpp, *plen, op_logic_T0_sn); //GEN_OP(*tbpp, *plen, op_set_nf); //set cpsr zf GEN_OP (*tbpp, *plen, op_logic_T0_sz); //GEN_OP(*tbpp, *plen, op_set_zf); //set cpsr cf //GEN_OP(*tbpp, *plen, op_set_cf); //set cpsr vf //GEN_OP(*tbpp, *plen, op_set_vf); GEN_OP (*tbpp, *plen, op_set_nzcvf); } } void arm2x86_get_op_setcpsr_nzcv_setreg (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword set_cc, ARMword rd) { if (set_cc && rd != 15) { //set cpsr cf //GEN_OP(*tbpp, *plen, op_set_cf); //set cpsr vf //GEN_OP(*tbpp, *plen, op_set_vf); //set cpsr nf GEN_OP (*tbpp, *plen, op_logic_T0_sn); //GEN_OP(*tbpp, *plen, op_set_nf); //set cpsr zf GEN_OP (*tbpp, *plen, op_logic_T0_sz); //GEN_OP(*tbpp, *plen, op_set_zf); GEN_OP (*tbpp, *plen, op_set_nzcvf); } gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0); if (rd == 15 && set_cc) { //change pc & set spsr to cpsr gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_SETS_R15); } } arm2x86_get_dp_op_t *arm2x86_get_dp_op_setcpsr[16] = { arm2x86_get_op_setcpsr_nzc_setreg, //and arm2x86_get_op_setcpsr_nzc_setreg, //eor arm2x86_get_op_setcpsr_nzcv_setreg, //sub arm2x86_get_op_setcpsr_nzcv_setreg, //rsb arm2x86_get_op_setcpsr_nzcv_setreg, //add arm2x86_get_op_setcpsr_nzcv_setreg, //adc arm2x86_get_op_setcpsr_nzcv_setreg, //sbc arm2x86_get_op_setcpsr_nzcv_setreg, //rsc arm2x86_get_op_setcpsr_nzc, //tst arm2x86_get_op_setcpsr_nzc, //teq arm2x86_get_op_setcpsr_nzcv, //cmp arm2x86_get_op_setcpsr_nzcv, //cmn arm2x86_get_op_setcpsr_nzc_setreg, //orr arm2x86_get_op_setcpsr_nzc_setreg, //mov arm2x86_get_op_setcpsr_nzc_setreg, //bic arm2x86_get_op_setcpsr_nzc_setreg, //mvn }; //-------------------------------------------------------------------------------------------------- int arm2x86_dp_init () { if (op_dp_T0_T1 ()) { return (-1); } return (0); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_shift.h������������������������������������������������������0000644�0001750�0000144�00000006500�10541455476�017437� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_SHIFT_H_ #define _ARM2X86_SHIFT_H_ extern int op_shift_T1_im_maxlen; extern op_table_t op_shift_T1_im[4]; //only shift extern int op_shift_T1_im_sc_maxlen; extern op_table_t op_shift_T1_im_sc[4]; //only set CFlag extern int op_shift_T1_0_maxlen; extern op_table_t op_shift_T1_0[4]; //only shift extern int op_shift_T2_0_sc_maxlen; extern op_table_t op_shift_T2_0_sc[4]; //only set CFlag extern int op_shift_T1_T0_maxlen; extern op_table_t op_shift_T1_T0[4]; //only shift extern int op_shift_T1_T0_sc_maxlen; extern op_table_t op_shift_T1_T0_sc[4]; //shift & set CFlag extern int op_shift_T2_im_maxlen; extern op_table_t op_shift_T2_im[4]; //only shift extern int arm2x86_shift_init (); static __inline__ void gen_op_shift_T1_im (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword op, uint8_t im) { if (im == 0) return; GEN_OP (*tbpp, *plen, op_shift_T1_im[op]); //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy (*tbpp, &im, sizeof (im)); *tbpp += sizeof (im); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (im); } static __inline__ void gen_op_shift_T1_im_sc (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword op, uint8_t im) { if (im == 0) return; //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, op_shift_T1_im_sc[op].op, op_shift_T1_im_sc[op].len); if (!op) { (*tbpp)[4] = 32 - im; } else { (*tbpp)[4] = im - 1; } *tbpp += op_shift_T1_im_sc[op].len; //} //AJ2D-------------------------------------------------------------------------- *plen += op_shift_T1_im_sc[op].len; //set cpsr cf GEN_OP (*tbpp, *plen, op_set_cf); } static __inline__ void gen_op_shift_T1_T0 (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword op) { GEN_OP (*tbpp, *plen, op_shift_T1_T0[op]); } static __inline__ void gen_op_shift_T1_T0_sc (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword op) { GEN_OP (*tbpp, *plen, op_shift_T1_T0_sc[op]); //set cpsr cf GEN_OP (*tbpp, *plen, op_set_cf); } static __inline__ void gen_op_shift_T2_im (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword op, uint8_t im) { if (im == 0) return; GEN_OP (*tbpp, *plen, op_shift_T2_im[op]); //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, &im, sizeof(im)); *tbpp += sizeof(im); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (im); } #endif //_ARM2X86_SHIFT_H_ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_test.c�������������������������������������������������������0000644�0001750�0000144�00000005135�10541455476�017277� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" uint8_t * get_op_test_dataabort (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_test_dataabort"); if (st->abortSig != LOW) { __asm__ __volatile__ ("jmp 0xffffffff"); } OP_END ("get_op_test_dataabort"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_test_dataabort_ret (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_test_dataabort_ret"); if (st->abortSig != LOW) { __asm__ __volatile__ ("ret"); } OP_END ("get_op_test_dataabort_ret"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_test_cpsr_ret_UNP (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_test_cpsr_ret_UNP"); T2 = st->Cpsr & 0x1f; if (T2 == 0x10 || T2 == 0x1f) { st->trap = TRAP_UNPREDICTABLE; __asm__ __volatile__ ("ret"); } OP_END ("get_op_test_cpsr_ret_UNP"); *len = end - begin; return ((uint8_t *) begin); } /*uint8_t * get_op_test_debug(int *len) { unsigned int begin=0,end=0; OP_BEGIN("get_op_test_debug"); T0 = st->Emulate; if (T0 == 0) { st->trap = TRAP_DEBUG; __asm__ __volatile__ ("ret"); } OP_END("get_op_test_debug"); *len = end - begin; return((uint8_t *)begin); }*/ op_table_t op_test_dataabort; op_table_t op_test_dataabort_ret; op_table_t op_test_cpsr_ret_UNP; //op_table_t op_test_debug; int arm2x86_test_init () { op_test_dataabort.op = get_op_test_dataabort (&op_test_dataabort.len); if (op_test_dataabort.len <= 0) return (-1); op_test_dataabort_ret.op = get_op_test_dataabort_ret (&op_test_dataabort_ret.len); if (op_test_dataabort_ret.len <= 0) return (-1); op_test_cpsr_ret_UNP.op = get_op_test_cpsr_ret_UNP (&op_test_cpsr_ret_UNP.len); if (op_test_cpsr_ret_UNP.len <= 0) return (-1); /*op_test_debug.op = get_op_test_debug(&op_test_debug.len); if (op_test_debug.len <= 0) return(-1); */ return (0); } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_mem.c��������������������������������������������������������0000644�0001750�0000144�00000054625�10714545461�017102� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" uint32_t tea_ldm (ARMul_State * state, ARMword address, ARMword reg_map) { int i; ARMword data; for (i = 0; i < 16; i++) { arm2x86_tmp_reg[i] = state->Reg[i]; if (reg_map & (1 << i)) { data = ARMul_ReadWord (state, address); if (state->abortSig != LOW) { state->trap = TRAP_DATA_ABORT; //if (state->is_XScale) { if (!state->abort_model) { return (0); } else { break; } } if (i == 15) { arm2x86_tmp_reg[i] = (data & (~3)) + 4; } else { arm2x86_tmp_reg[i] = data; } address += 4; } } if (state->trap != TRAP_DATA_ABORT) { for (i = 0; i < 16; i++) { state->Reg[i] = arm2x86_tmp_reg[i]; } address -= 4; } return (address); } uint32_t tea_ldm_user (ARMul_State * state, ARMword address, ARMword reg_map) { int i; ARMword data; for (i = 0; i < 15; i++) { if (((state->Mode == FIQ26MODE || state->Mode == FIQ32MODE) && (i >= 8)) || (i >= 13)) { arm2x86_tmp_reg[i] = state->RegBank[USERBANK][i]; } else { arm2x86_tmp_reg[i] = state->Reg[i]; } arm2x86_tmp_reg[i] = state->Reg[i]; if (reg_map & (1 << i)) { data = ARMul_ReadWord (state, address); if (state->abortSig != LOW) { state->trap = TRAP_DATA_ABORT; //if (state->is_XScale) { if (!state->abort_model) { return (0); } else { break; } } /*if (((state->Mode == FIQ26MODE || state->Mode == FIQ32MODE) && (i >= 8)) || (i >= 13)) { state->RegBank[USERBANK][i] = data; } else { state->Reg[i] = data; } */ arm2x86_tmp_reg[i] = data; address += 4; } } if (state->trap != TRAP_DATA_ABORT) { for (i = 0; i < 15; i++) { if (((state->Mode == FIQ26MODE || state->Mode == FIQ32MODE) && (i >= 8)) || (i >= 13)) { state->RegBank[USERBANK][i] = arm2x86_tmp_reg[i]; } else { state->Reg[i] = arm2x86_tmp_reg[i]; } } address -= 4; } return (address); } uint32_t tea_stm (ARMul_State * state, ARMword address, ARMword reg_map) { int i; for (i = 0; i < 16; i++) { if (reg_map & (1 << i)) { if (i == 15) { ARMul_WriteWord (state, address, state->Reg[i] + 4); } else { ARMul_WriteWord (state, address, state->Reg[i]); } if (state->abortSig != LOW) { state->trap = TRAP_DATA_ABORT; //if (state->is_XScale) { if (!state->abort_model) { return (0); } else { break; } } address += 4; } } if (state->trap != TRAP_DATA_ABORT) { address -= 4; } return (address); } uint32_t tea_stm_user (ARMul_State * state, ARMword address, ARMword reg_map) { int i; for (i = 0; i < 16; i++) { if (reg_map & (1 << i)) { if (i == 15) { ARMul_WriteWord (state, address, state->Reg[i] + 4); } else { if (((state->Mode == FIQ26MODE || state->Mode == FIQ32MODE) && (i >= 8)) || (i >= 13)) { ARMul_WriteWord (state, address, state-> RegBank[USERBANK] [i]); } else { ARMul_WriteWord (state, address, state->Reg[i]); } } if (state->abortSig != LOW) { state->trap = TRAP_DATA_ABORT; //if (state->is_XScale) { if (!state->abort_model) { return (0); } else { break; } } address += 4; } } if (state->trap != TRAP_DATA_ABORT) { address -= 4; } return (address); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_ldr_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldr_T0_T1"); //T0 = ARMul_ReadWord(st, T1); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_ReadWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_ReadWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T0); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } if (T1 & 3) { T0 = LOADWORD_ALIGN (T1, T0); } OP_END ("get_op_ldr_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ldr_T2_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldr_T2_T1"); //T2 = ARMul_ReadWord(st, T1); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_ReadWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_ReadWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T2); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } if (T1 & 3) { T2 = LOADWORD_ALIGN (T1, T2); } OP_END ("get_op_ldr_T2_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ldrh_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldrh_T0_T1"); //T0 = ARMul_LoadHalfWord(st, T1); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_LoadHalfWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_LoadHalfWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T0); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_ldrh_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ldrb_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldrb_T0_T1"); //T0 = ARMul_ReadByte(st, T1); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_ReadByte; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_ReadByte; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T0); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_ldrb_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ldrb_T2_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldrb_T2_T1"); //T2 = ARMul_ReadByte(st, T1); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_ReadByte; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_ReadByte; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T2); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_ldrb_T2_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_str_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_str_T0_T1"); //ARMul_WriteWord(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_WriteWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_WriteWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_str_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_strh_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_strh_T0_T1"); //ARMul_StoreHalfWord(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_StoreHalfWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_StoreHalfWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; if (st->abort_model < 2) { //if (st->is_XScale) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_strh_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_strb_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_strb_T0_T1"); //ARMul_WriteByte(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_WriteByte; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_WriteByte; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_strb_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ldm_T1_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldm_T1_T0"); //T1 = tea_ldm(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) tea_ldm; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))tea_ldm; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T1); /*if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; __asm__ __volatile__ ("ret"); } */ if (st->abortSig != LOW) { //if (st->is_XScale) { if (!st->abort_model) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_ldm_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_stm_T1_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_stm_T1_T0"); //T1 = tea_stm(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) tea_stm; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))tea_stm; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T1); /*if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; __asm__ __volatile__ ("ret"); } */ if (st->abortSig != LOW) { //if (st->is_XScale) { if (!st->abort_model) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_stm_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ldm_user_T1_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldm_user_T1_T0"); //T1 = tea_ldm_user(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) tea_ldm_user; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))tea_ldm_user; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T1); /*if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; __asm__ __volatile__ ("ret"); } */ if (st->abortSig != LOW) { //if (st->is_XScale) { if (!st->abort_model) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_ldm_user_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_stm_user_T1_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_stm_user_T1_T0"); //T1 = tea_stm_user(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) tea_stm_user; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))tea_stm_user; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T1); /*if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; __asm__ __volatile__ ("ret"); } */ if (st->abortSig != LOW) { //if (st->is_XScale) { if (!st->abort_model) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_stm_user_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } //teawater add for xscale(arm v5) 2005.09.19------------------------------------ uint8_t * get_op_signextend_halfword_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_signextend_halfword_T0"); //if (T0 & 1 << (16 - 1)) //T0 |= 0xffff0000; T0 = (uint32_t) ((int32_t) ((int16_t) T0)); OP_END ("get_op_signextend_halfword_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_signextend_byte_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_signextend_byte_T0"); //if (T0 & 1 << (8 - 1)) //T0 |= 0xffffff00; T0 = (uint32_t) ((int32_t) ((int8_t) T0)); OP_END ("get_op_signextend_byte_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_signextend_halfword_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_signextend_halfword_T1"); //if (T1 & 1 << (16 - 1)) //T1 |= 0xffff0000; T1 = (uint32_t) ((int32_t) ((int16_t) T1)); OP_END ("get_op_signextend_halfword_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_signextend_byte_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_signextend_byte_T1"); //if (T1 & 1 << (8 - 1)) //T1 |= 0xffffff00; T1 = (uint32_t) ((int32_t) ((int8_t) T1)); OP_END ("get_op_signextend_byte_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ldrd_T0_T2_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ldrd_T0_T2_T1"); //T0 = ARMul_ReadWord(st, T1); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_ReadWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_ReadWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T0); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } if (T1 & 3) { T0 = LOADWORD_ALIGN (T1, T0); } T1 += 4; //T2 = ARMul_ReadWord(st, T1); __asm__ __volatile__ ("subl $0x8, %esp"); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_ReadWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_ReadWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); __asm__ __volatile__ ("movl %eax, %" AREG_T2); T1 -= 4; if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } if (T1 & 3) { T0 = LOADWORD_ALIGN (T1, T2); } OP_END ("get_op_ldrd_T0_T2_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_strd_T0_T2_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_strd_T0_T2_T1"); //ARMul_WriteWord(st, T1, T0); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T0); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_WriteWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_WriteWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } T1 += 4; //ARMul_WriteWord(st, T1, T2); __asm__ __volatile__ ("subl $0x4, %esp"); __asm__ __volatile__ ("push %" AREG_T2); __asm__ __volatile__ ("push %" AREG_T1); __asm__ __volatile__ ("push %" AREG_st); //chy 2005-05-11 #if !(defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)) arm2x86_pfun = (uint32_t) ARMul_WriteWord; __asm__ __volatile__ ("call *arm2x86_pfun"); #else arm2x86_pfun = (volatile void(*))ARMul_WriteWord; wmb (); (*arm2x86_pfun) (); #endif __asm__ __volatile__ ("addl $0x10, %esp"); T1 -= 4; if (st->abortSig != LOW) { st->trap = TRAP_DATA_ABORT; //if (st->is_XScale) { if (st->abort_model < 2) { __asm__ __volatile__ ("ret"); } } OP_END ("get_op_strd_T0_T2_T1"); *len = end - begin; return ((uint8_t *) begin); } //AJ2D-------------------------------------------------------------------------- op_table_t op_ldr_T0_T1; op_table_t op_ldr_T2_T1; op_table_t op_ldrh_T0_T1; op_table_t op_ldrb_T0_T1; op_table_t op_ldrb_T2_T1; op_table_t op_str_T0_T1; op_table_t op_strh_T0_T1; op_table_t op_strb_T0_T1; op_table_t op_ldm_T1_T0; op_table_t op_stm_T1_T0; op_table_t op_ldm_user_T1_T0; op_table_t op_stm_user_T1_T0; op_table_t op_signextend_halfword_T0; op_table_t op_signextend_byte_T0; //teawater add for xscale(arm v5) 2005.09.19------------------------------------ op_table_t op_signextend_halfword_T1; op_table_t op_signextend_byte_T1; op_table_t op_ldrd_T0_T2_T1; op_table_t op_strd_T0_T2_T1; //AJ2D-------------------------------------------------------------------------- int arm2x86_mem_init () { op_ldr_T0_T1.op = get_op_ldr_T0_T1 (&op_ldr_T0_T1.len); if (op_ldr_T0_T1.len <= 0) return (-1); op_ldr_T2_T1.op = get_op_ldr_T2_T1 (&op_ldr_T2_T1.len); if (op_ldr_T2_T1.len <= 0) return (-1); op_ldrh_T0_T1.op = get_op_ldrh_T0_T1 (&op_ldrh_T0_T1.len); if (op_ldrh_T0_T1.len <= 0) return (-1); op_ldrb_T0_T1.op = get_op_ldrb_T0_T1 (&op_ldrb_T0_T1.len); if (op_ldrb_T0_T1.len <= 0) return (-1); op_ldrb_T2_T1.op = get_op_ldrb_T2_T1 (&op_ldrb_T2_T1.len); if (op_ldrb_T2_T1.len <= 0) return (-1); op_str_T0_T1.op = get_op_str_T0_T1 (&op_str_T0_T1.len); if (op_str_T0_T1.len <= 0) return (-1); op_strh_T0_T1.op = get_op_strh_T0_T1 (&op_strh_T0_T1.len); if (op_strh_T0_T1.len <= 0) return (-1); op_strb_T0_T1.op = get_op_strb_T0_T1 (&op_strb_T0_T1.len); if (op_strb_T0_T1.len <= 0) return (-1); op_ldm_T1_T0.op = get_op_ldm_T1_T0 (&op_ldm_T1_T0.len); if (op_ldm_T1_T0.len <= 0) return (-1); op_stm_T1_T0.op = get_op_stm_T1_T0 (&op_stm_T1_T0.len); if (op_stm_T1_T0.len <= 0) return (-1); op_ldm_user_T1_T0.op = get_op_ldm_user_T1_T0 (&op_ldm_user_T1_T0.len); if (op_ldm_user_T1_T0.len <= 0) return (-1); op_stm_user_T1_T0.op = get_op_stm_user_T1_T0 (&op_stm_user_T1_T0.len); if (op_stm_user_T1_T0.len <= 0) return (-1); op_signextend_halfword_T0.op = get_op_signextend_halfword_T0 (&op_signextend_halfword_T0. len); if (op_signextend_halfword_T0.len <= 0) return (-1); op_signextend_byte_T0.op = get_op_signextend_byte_T0 (&op_signextend_byte_T0.len); if (op_signextend_byte_T0.len <= 0) return (-1); //teawater add for xscale(arm v5) 2005.09.20------------------------------------ op_signextend_halfword_T1.op = get_op_signextend_halfword_T1 (&op_signextend_halfword_T1. len); if (op_signextend_halfword_T1.len <= 0) return (-1); op_signextend_byte_T1.op = get_op_signextend_byte_T1 (&op_signextend_byte_T1.len); if (op_signextend_byte_T1.len <= 0) return (-1); op_ldrd_T0_T2_T1.op = get_op_ldrd_T0_T2_T1 (&op_ldrd_T0_T2_T1.len); if (op_ldrd_T0_T2_T1.len <= 0) return (-1); op_strd_T0_T2_T1.op = get_op_strd_T0_T2_T1 (&op_strd_T0_T2_T1.len); if (op_strd_T0_T2_T1.len <= 0) return (-1); //AJ2D-------------------------------------------------------------------------- return (0); } �����������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_movl.c�������������������������������������������������������0000644�0001750�0000144�00000112765�10541455476�017305� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" uint8_t * get_op_movl_T0_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_im"); T0 = ULONG_MAX; OP_END ("get_op_movl_T0_im"); *len = end - begin; if (*len <= sizeof (ULONG_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_im"); T1 = ULONG_MAX; OP_END ("get_op_movl_T1_im"); *len = end - begin; if (*len <= sizeof (ULONG_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_im"); T2 = ULONG_MAX; OP_END ("get_op_movl_T2_im"); *len = end - begin; if (*len <= sizeof (ULONG_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } ret = (uint8_t *) begin; return (ret); } op_table_t op_movl_Tx_im[Tx_MAX + 1]; int op_movl_Tx_im_init () { int i; op_movl_Tx_im[0].op = get_op_movl_T0_im (&op_movl_Tx_im[0].len); op_movl_Tx_im[1].op = get_op_movl_T1_im (&op_movl_Tx_im[1].len); op_movl_Tx_im[2].op = get_op_movl_T2_im (&op_movl_Tx_im[2].len); for (i = 0; i <= Tx_MAX; i++) { if (op_movl_Tx_im[i].op == NULL) { return (-1); } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_movl_tmp0_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_tmp0_im"); arm2x86_tmp0 = ULONG_MAX; OP_END ("get_op_movl_tmp0_im"); *len = end - begin; if (*len <= sizeof (ULONG_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } ret = (uint8_t *) begin; return (ret); } op_table_t op_movl_tmpx_im[tmp_MAX + 1]; int op_movl_tmpx_im_init () { op_movl_tmpx_im[0].op = get_op_movl_tmp0_im (&op_movl_tmpx_im[0].len); if (op_movl_tmpx_im[0].op == NULL) return (-1); return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_movl_T0_r0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r0"); T0 = st->Reg[0]; OP_END ("get_op_movl_T0_r0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r1"); T0 = st->Reg[1]; OP_END ("get_op_movl_T0_r1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r2"); T0 = st->Reg[2]; OP_END ("get_op_movl_T0_r2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r3 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r3"); T0 = st->Reg[3]; OP_END ("get_op_movl_T0_r3"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r4 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r4"); T0 = st->Reg[4]; OP_END ("get_op_movl_T0_r4"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r5 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r5"); T0 = st->Reg[5]; OP_END ("get_op_movl_T0_r5"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r6 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r6"); T0 = st->Reg[6]; OP_END ("get_op_movl_T0_r6"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r7 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r7"); T0 = st->Reg[7]; OP_END ("get_op_movl_T0_r7"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r8 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r8"); T0 = st->Reg[8]; OP_END ("get_op_movl_T0_r8"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r9 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r9"); T0 = st->Reg[9]; OP_END ("get_op_movl_T0_r9"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r10 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r10"); T0 = st->Reg[10]; OP_END ("get_op_movl_T0_r10"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r11 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r11"); T0 = st->Reg[11]; OP_END ("get_op_movl_T0_r11"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r12 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r12"); T0 = st->Reg[12]; OP_END ("get_op_movl_T0_r12"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r13 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r13"); T0 = st->Reg[13]; OP_END ("get_op_movl_T0_r13"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r14 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r14"); T0 = st->Reg[14]; OP_END ("get_op_movl_T0_r14"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T0_r15 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_r15"); T0 = st->Reg[15] + 4; OP_END ("get_op_movl_T0_r15"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r0"); T1 = st->Reg[0]; OP_END ("get_op_movl_T1_r0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r1"); T1 = st->Reg[1]; OP_END ("get_op_movl_T1_r1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r2"); T1 = st->Reg[2]; OP_END ("get_op_movl_T1_r2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r3 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r3"); T1 = st->Reg[3]; OP_END ("get_op_movl_T1_r3"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r4 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r4"); T1 = st->Reg[4]; OP_END ("get_op_movl_T1_r4"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r5 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r5"); T1 = st->Reg[5]; OP_END ("get_op_movl_T1_r5"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r6 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r6"); T1 = st->Reg[6]; OP_END ("get_op_movl_T1_r6"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r7 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r7"); T1 = st->Reg[7]; OP_END ("get_op_movl_T1_r7"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r8 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r8"); T1 = st->Reg[8]; OP_END ("get_op_movl_T1_r8"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r9 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r9"); T1 = st->Reg[9]; OP_END ("get_op_movl_T1_r9"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r10 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r10"); T1 = st->Reg[10]; OP_END ("get_op_movl_T1_r10"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r11 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r11"); T1 = st->Reg[11]; OP_END ("get_op_movl_T1_r11"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r12 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r12"); T1 = st->Reg[12]; OP_END ("get_op_movl_T1_r12"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r13 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r13"); T1 = st->Reg[13]; OP_END ("get_op_movl_T1_r13"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r14 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r14"); T1 = st->Reg[14]; OP_END ("get_op_movl_T1_r14"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T1_r15 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_r15"); T1 = st->Reg[15] + 4; OP_END ("get_op_movl_T1_r15"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r0"); T2 = st->Reg[0]; OP_END ("get_op_movl_T2_r0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r1"); T2 = st->Reg[1]; OP_END ("get_op_movl_T2_r1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r2"); T2 = st->Reg[2]; OP_END ("get_op_movl_T2_r2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r3 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r3"); T2 = st->Reg[3]; OP_END ("get_op_movl_T2_r3"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r4 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r4"); T2 = st->Reg[4]; OP_END ("get_op_movl_T2_r4"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r5 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r5"); T2 = st->Reg[5]; OP_END ("get_op_movl_T2_r5"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r6 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r6"); T2 = st->Reg[6]; OP_END ("get_op_movl_T2_r6"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r7 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r7"); T2 = st->Reg[7]; OP_END ("get_op_movl_T2_r7"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r8 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r8"); T2 = st->Reg[8]; OP_END ("get_op_movl_T2_r8"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r9 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r9"); T2 = st->Reg[9]; OP_END ("get_op_movl_T2_r9"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r10 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r10"); T2 = st->Reg[10]; OP_END ("get_op_movl_T2_r10"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r11 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r11"); T2 = st->Reg[11]; OP_END ("get_op_movl_T2_r11"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r12 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r12"); T2 = st->Reg[12]; OP_END ("get_op_movl_T2_r12"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r13 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r13"); T2 = st->Reg[13]; OP_END ("get_op_movl_T2_r13"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r14 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r14"); T2 = st->Reg[14]; OP_END ("get_op_movl_T2_r14"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_r15 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_r15"); T2 = st->Reg[15] + 4; OP_END ("get_op_movl_T2_r15"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } int op_movl_Tx_reg_maxlen; int op_movl_Tx_reg_array_maxlen[Tx_MAX + 1]; op_table_t op_movl_Tx_reg[Tx_MAX + 1][16]; int op_movl_Tx_reg_init () { int i, j; op_movl_Tx_reg[0][0].op = get_op_movl_T0_r0 (&op_movl_Tx_reg[0][0].len); op_movl_Tx_reg[0][1].op = get_op_movl_T0_r1 (&op_movl_Tx_reg[0][1].len); op_movl_Tx_reg[0][2].op = get_op_movl_T0_r2 (&op_movl_Tx_reg[0][2].len); op_movl_Tx_reg[0][3].op = get_op_movl_T0_r3 (&op_movl_Tx_reg[0][3].len); op_movl_Tx_reg[0][4].op = get_op_movl_T0_r4 (&op_movl_Tx_reg[0][4].len); op_movl_Tx_reg[0][5].op = get_op_movl_T0_r5 (&op_movl_Tx_reg[0][5].len); op_movl_Tx_reg[0][6].op = get_op_movl_T0_r6 (&op_movl_Tx_reg[0][6].len); op_movl_Tx_reg[0][7].op = get_op_movl_T0_r7 (&op_movl_Tx_reg[0][7].len); op_movl_Tx_reg[0][8].op = get_op_movl_T0_r8 (&op_movl_Tx_reg[0][8].len); op_movl_Tx_reg[0][9].op = get_op_movl_T0_r9 (&op_movl_Tx_reg[0][9].len); op_movl_Tx_reg[0][10].op = get_op_movl_T0_r10 (&op_movl_Tx_reg[0][10].len); op_movl_Tx_reg[0][11].op = get_op_movl_T0_r11 (&op_movl_Tx_reg[0][11].len); op_movl_Tx_reg[0][12].op = get_op_movl_T0_r12 (&op_movl_Tx_reg[0][12].len); op_movl_Tx_reg[0][13].op = get_op_movl_T0_r13 (&op_movl_Tx_reg[0][13].len); op_movl_Tx_reg[0][14].op = get_op_movl_T0_r14 (&op_movl_Tx_reg[0][14].len); op_movl_Tx_reg[0][15].op = get_op_movl_T0_r15 (&op_movl_Tx_reg[0][15].len); op_movl_Tx_reg[1][0].op = get_op_movl_T1_r0 (&op_movl_Tx_reg[1][0].len); op_movl_Tx_reg[1][1].op = get_op_movl_T1_r1 (&op_movl_Tx_reg[1][1].len); op_movl_Tx_reg[1][2].op = get_op_movl_T1_r2 (&op_movl_Tx_reg[1][2].len); op_movl_Tx_reg[1][3].op = get_op_movl_T1_r3 (&op_movl_Tx_reg[1][3].len); op_movl_Tx_reg[1][4].op = get_op_movl_T1_r4 (&op_movl_Tx_reg[1][4].len); op_movl_Tx_reg[1][5].op = get_op_movl_T1_r5 (&op_movl_Tx_reg[1][5].len); op_movl_Tx_reg[1][6].op = get_op_movl_T1_r6 (&op_movl_Tx_reg[1][6].len); op_movl_Tx_reg[1][7].op = get_op_movl_T1_r7 (&op_movl_Tx_reg[1][7].len); op_movl_Tx_reg[1][8].op = get_op_movl_T1_r8 (&op_movl_Tx_reg[1][8].len); op_movl_Tx_reg[1][9].op = get_op_movl_T1_r9 (&op_movl_Tx_reg[1][9].len); op_movl_Tx_reg[1][10].op = get_op_movl_T1_r10 (&op_movl_Tx_reg[1][10].len); op_movl_Tx_reg[1][11].op = get_op_movl_T1_r11 (&op_movl_Tx_reg[1][11].len); op_movl_Tx_reg[1][12].op = get_op_movl_T1_r12 (&op_movl_Tx_reg[1][12].len); op_movl_Tx_reg[1][13].op = get_op_movl_T1_r13 (&op_movl_Tx_reg[1][13].len); op_movl_Tx_reg[1][14].op = get_op_movl_T1_r14 (&op_movl_Tx_reg[1][14].len); op_movl_Tx_reg[1][15].op = get_op_movl_T1_r15 (&op_movl_Tx_reg[1][15].len); op_movl_Tx_reg[2][0].op = get_op_movl_T2_r0 (&op_movl_Tx_reg[2][0].len); op_movl_Tx_reg[2][1].op = get_op_movl_T2_r1 (&op_movl_Tx_reg[2][1].len); op_movl_Tx_reg[2][2].op = get_op_movl_T2_r2 (&op_movl_Tx_reg[2][2].len); op_movl_Tx_reg[2][3].op = get_op_movl_T2_r3 (&op_movl_Tx_reg[2][3].len); op_movl_Tx_reg[2][4].op = get_op_movl_T2_r4 (&op_movl_Tx_reg[2][4].len); op_movl_Tx_reg[2][5].op = get_op_movl_T2_r5 (&op_movl_Tx_reg[2][5].len); op_movl_Tx_reg[2][6].op = get_op_movl_T2_r6 (&op_movl_Tx_reg[2][6].len); op_movl_Tx_reg[2][7].op = get_op_movl_T2_r7 (&op_movl_Tx_reg[2][7].len); op_movl_Tx_reg[2][8].op = get_op_movl_T2_r8 (&op_movl_Tx_reg[2][8].len); op_movl_Tx_reg[2][9].op = get_op_movl_T2_r9 (&op_movl_Tx_reg[2][9].len); op_movl_Tx_reg[2][10].op = get_op_movl_T2_r10 (&op_movl_Tx_reg[2][10].len); op_movl_Tx_reg[2][11].op = get_op_movl_T2_r11 (&op_movl_Tx_reg[2][11].len); op_movl_Tx_reg[2][12].op = get_op_movl_T2_r12 (&op_movl_Tx_reg[2][12].len); op_movl_Tx_reg[2][13].op = get_op_movl_T2_r13 (&op_movl_Tx_reg[2][13].len); op_movl_Tx_reg[2][14].op = get_op_movl_T2_r14 (&op_movl_Tx_reg[2][14].len); op_movl_Tx_reg[2][15].op = get_op_movl_T2_r15 (&op_movl_Tx_reg[2][15].len); op_movl_Tx_reg_maxlen = 0; for (i = 0; i <= Tx_MAX; i++) { op_movl_Tx_reg_array_maxlen[i] = 0; for (j = 0; j <= 15; j++) { if (op_movl_Tx_reg[i][j].len <= 0) { return (-1); } if (op_movl_Tx_reg[i][j].len > op_movl_Tx_reg_array_maxlen[i]) { op_movl_Tx_reg_array_maxlen[i] = op_movl_Tx_reg[i][j].len; } } if (op_movl_Tx_reg_array_maxlen[i] > op_movl_Tx_reg_maxlen) { op_movl_Tx_reg_maxlen = op_movl_Tx_reg_array_maxlen[i]; } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_movl_r0_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r0_T0"); st->Reg[0] = T0; OP_END ("get_op_movl_r0_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r1_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r1_T0"); st->Reg[1] = T0; OP_END ("get_op_movl_r1_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r2_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r2_T0"); st->Reg[2] = T0; OP_END ("get_op_movl_r2_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r3_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r3_T0"); st->Reg[3] = T0; OP_END ("get_op_movl_r3_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r4_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r4_T0"); st->Reg[4] = T0; OP_END ("get_op_movl_r4_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r5_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r5_T0"); st->Reg[5] = T0; OP_END ("get_op_movl_r5_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r6_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r6_T0"); st->Reg[6] = T0; OP_END ("get_op_movl_r6_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r7_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r7_T0"); st->Reg[7] = T0; OP_END ("get_op_movl_r7_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r8_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r8_T0"); st->Reg[8] = T0; OP_END ("get_op_movl_r8_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r9_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r9_T0"); st->Reg[9] = T0; OP_END ("get_op_movl_r9_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r10_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r10_T0"); st->Reg[10] = T0; OP_END ("get_op_movl_r10_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r11_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r11_T0"); st->Reg[11] = T0; OP_END ("get_op_movl_r11_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r12_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r12_T0"); st->Reg[12] = T0; OP_END ("get_op_movl_r12_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r13_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r13_T0"); st->Reg[13] = T0; OP_END ("get_op_movl_r13_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r14_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r14_T0"); st->Reg[14] = T0; OP_END ("get_op_movl_r14_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r15_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r15_T0"); st->Reg[15] = (T0 & (~3)) + 4; OP_END ("get_op_movl_r15_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r0_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r0_T1"); st->Reg[0] = T1; OP_END ("get_op_movl_r0_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r1_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r1_T1"); st->Reg[1] = T1; OP_END ("get_op_movl_r1_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r2_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r2_T1"); st->Reg[2] = T1; OP_END ("get_op_movl_r2_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r3_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r3_T1"); st->Reg[3] = T1; OP_END ("get_op_movl_r3_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r4_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r4_T1"); st->Reg[4] = T1; OP_END ("get_op_movl_r4_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r5_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r5_T1"); st->Reg[5] = T1; OP_END ("get_op_movl_r5_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r6_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r6_T1"); st->Reg[6] = T1; OP_END ("get_op_movl_r6_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r7_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r7_T1"); st->Reg[7] = T1; OP_END ("get_op_movl_r7_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r8_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r8_T1"); st->Reg[8] = T1; OP_END ("get_op_movl_r8_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r9_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r9_T1"); st->Reg[9] = T1; OP_END ("get_op_movl_r9_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r10_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r10_T1"); st->Reg[10] = T1; OP_END ("get_op_movl_r10_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r11_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r11_T1"); st->Reg[11] = T1; OP_END ("get_op_movl_r11_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r12_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r12_T1"); st->Reg[12] = T1; OP_END ("get_op_movl_r12_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r13_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r13_T1"); st->Reg[13] = T1; OP_END ("get_op_movl_r13_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r14_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r14_T1"); st->Reg[14] = T1; OP_END ("get_op_movl_r14_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r15_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r15_T1"); st->Reg[15] = (T1 & (~3)) + 4; OP_END ("get_op_movl_r15_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r0_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r0_T2"); st->Reg[0] = T2; OP_END ("get_op_movl_r0_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r1_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r1_T2"); st->Reg[1] = T2; OP_END ("get_op_movl_r1_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r2_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r2_T2"); st->Reg[2] = T2; OP_END ("get_op_movl_r2_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r3_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r3_T2"); st->Reg[3] = T2; OP_END ("get_op_movl_r3_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r4_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r4_T2"); st->Reg[4] = T2; OP_END ("get_op_movl_r4_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r5_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r5_T2"); st->Reg[5] = T2; OP_END ("get_op_movl_r5_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r6_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r6_T2"); st->Reg[6] = T2; OP_END ("get_op_movl_r6_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r7_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r7_T2"); st->Reg[7] = T2; OP_END ("get_op_movl_r7_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r8_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r8_T2"); st->Reg[8] = T2; OP_END ("get_op_movl_r8_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r9_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r9_T2"); st->Reg[9] = T2; OP_END ("get_op_movl_r9_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r10_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r10_T2"); st->Reg[10] = T2; OP_END ("get_op_movl_r10_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r11_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r11_T2"); st->Reg[11] = T2; OP_END ("get_op_movl_r11_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r12_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r12_T2"); st->Reg[12] = T2; OP_END ("get_op_movl_r12_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r13_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r13_T2"); st->Reg[13] = T2; OP_END ("get_op_movl_r13_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r14_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r14_T2"); st->Reg[14] = T2; OP_END ("get_op_movl_r14_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_r15_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_r15_T2"); st->Reg[15] = (T2 & (~3)) + 4; OP_END ("get_op_movl_r15_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } int op_movl_reg_Tx_maxlen; int op_movl_reg_Tx_array_maxlen[Tx_MAX + 1]; op_table_t op_movl_reg_Tx[Tx_MAX + 1][16]; int op_movl_reg_Tx_init () { int i, j; op_movl_reg_Tx[0][0].op = get_op_movl_r0_T0 (&op_movl_reg_Tx[0][0].len); op_movl_reg_Tx[0][1].op = get_op_movl_r1_T0 (&op_movl_reg_Tx[0][1].len); op_movl_reg_Tx[0][2].op = get_op_movl_r2_T0 (&op_movl_reg_Tx[0][2].len); op_movl_reg_Tx[0][3].op = get_op_movl_r3_T0 (&op_movl_reg_Tx[0][3].len); op_movl_reg_Tx[0][4].op = get_op_movl_r4_T0 (&op_movl_reg_Tx[0][4].len); op_movl_reg_Tx[0][5].op = get_op_movl_r5_T0 (&op_movl_reg_Tx[0][5].len); op_movl_reg_Tx[0][6].op = get_op_movl_r6_T0 (&op_movl_reg_Tx[0][6].len); op_movl_reg_Tx[0][7].op = get_op_movl_r7_T0 (&op_movl_reg_Tx[0][7].len); op_movl_reg_Tx[0][8].op = get_op_movl_r8_T0 (&op_movl_reg_Tx[0][8].len); op_movl_reg_Tx[0][9].op = get_op_movl_r9_T0 (&op_movl_reg_Tx[0][9].len); op_movl_reg_Tx[0][10].op = get_op_movl_r10_T0 (&op_movl_reg_Tx[0][10].len); op_movl_reg_Tx[0][11].op = get_op_movl_r11_T0 (&op_movl_reg_Tx[0][11].len); op_movl_reg_Tx[0][12].op = get_op_movl_r12_T0 (&op_movl_reg_Tx[0][12].len); op_movl_reg_Tx[0][13].op = get_op_movl_r13_T0 (&op_movl_reg_Tx[0][13].len); op_movl_reg_Tx[0][14].op = get_op_movl_r14_T0 (&op_movl_reg_Tx[0][14].len); op_movl_reg_Tx[0][15].op = get_op_movl_r15_T0 (&op_movl_reg_Tx[0][15].len); op_movl_reg_Tx[1][0].op = get_op_movl_r0_T1 (&op_movl_reg_Tx[1][0].len); op_movl_reg_Tx[1][1].op = get_op_movl_r1_T1 (&op_movl_reg_Tx[1][1].len); op_movl_reg_Tx[1][2].op = get_op_movl_r2_T1 (&op_movl_reg_Tx[1][2].len); op_movl_reg_Tx[1][3].op = get_op_movl_r3_T1 (&op_movl_reg_Tx[1][3].len); op_movl_reg_Tx[1][4].op = get_op_movl_r4_T1 (&op_movl_reg_Tx[1][4].len); op_movl_reg_Tx[1][5].op = get_op_movl_r5_T1 (&op_movl_reg_Tx[1][5].len); op_movl_reg_Tx[1][6].op = get_op_movl_r6_T1 (&op_movl_reg_Tx[1][6].len); op_movl_reg_Tx[1][7].op = get_op_movl_r7_T1 (&op_movl_reg_Tx[1][7].len); op_movl_reg_Tx[1][8].op = get_op_movl_r8_T1 (&op_movl_reg_Tx[1][8].len); op_movl_reg_Tx[1][9].op = get_op_movl_r9_T1 (&op_movl_reg_Tx[1][9].len); op_movl_reg_Tx[1][10].op = get_op_movl_r10_T1 (&op_movl_reg_Tx[1][10].len); op_movl_reg_Tx[1][11].op = get_op_movl_r11_T1 (&op_movl_reg_Tx[1][11].len); op_movl_reg_Tx[1][12].op = get_op_movl_r12_T1 (&op_movl_reg_Tx[1][12].len); op_movl_reg_Tx[1][13].op = get_op_movl_r13_T1 (&op_movl_reg_Tx[1][13].len); op_movl_reg_Tx[1][14].op = get_op_movl_r14_T1 (&op_movl_reg_Tx[1][14].len); op_movl_reg_Tx[1][15].op = get_op_movl_r15_T1 (&op_movl_reg_Tx[1][15].len); op_movl_reg_Tx[2][0].op = get_op_movl_r0_T2 (&op_movl_reg_Tx[2][0].len); op_movl_reg_Tx[2][1].op = get_op_movl_r1_T2 (&op_movl_reg_Tx[2][1].len); op_movl_reg_Tx[2][2].op = get_op_movl_r2_T2 (&op_movl_reg_Tx[2][2].len); op_movl_reg_Tx[2][3].op = get_op_movl_r3_T2 (&op_movl_reg_Tx[2][3].len); op_movl_reg_Tx[2][4].op = get_op_movl_r4_T2 (&op_movl_reg_Tx[2][4].len); op_movl_reg_Tx[2][5].op = get_op_movl_r5_T2 (&op_movl_reg_Tx[2][5].len); op_movl_reg_Tx[2][6].op = get_op_movl_r6_T2 (&op_movl_reg_Tx[2][6].len); op_movl_reg_Tx[2][7].op = get_op_movl_r7_T2 (&op_movl_reg_Tx[2][7].len); op_movl_reg_Tx[2][8].op = get_op_movl_r8_T2 (&op_movl_reg_Tx[2][8].len); op_movl_reg_Tx[2][9].op = get_op_movl_r9_T2 (&op_movl_reg_Tx[2][9].len); op_movl_reg_Tx[2][10].op = get_op_movl_r10_T2 (&op_movl_reg_Tx[2][10].len); op_movl_reg_Tx[2][11].op = get_op_movl_r11_T2 (&op_movl_reg_Tx[2][11].len); op_movl_reg_Tx[2][12].op = get_op_movl_r12_T2 (&op_movl_reg_Tx[2][12].len); op_movl_reg_Tx[2][13].op = get_op_movl_r13_T2 (&op_movl_reg_Tx[2][13].len); op_movl_reg_Tx[2][14].op = get_op_movl_r14_T2 (&op_movl_reg_Tx[2][14].len); op_movl_reg_Tx[2][15].op = get_op_movl_r15_T2 (&op_movl_reg_Tx[2][15].len); op_movl_reg_Tx_maxlen = 0; for (i = 0; i <= Tx_MAX; i++) { op_movl_reg_Tx_array_maxlen[i] = 0; for (j = 0; j <= 15; j++) { if (op_movl_reg_Tx[i][j].len <= 0) { return (-1); } if (op_movl_reg_Tx[i][j].len > op_movl_reg_Tx_array_maxlen[i]) { op_movl_reg_Tx_array_maxlen[i] = op_movl_reg_Tx[i][j].len; } } if (op_movl_reg_Tx_array_maxlen[i] > op_movl_reg_Tx_maxlen) { op_movl_reg_Tx_maxlen = op_movl_reg_Tx_array_maxlen[i]; } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_movl_eax_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_eax_T2"); __asm__ __volatile__ ("movl %" AREG_T2 ", %eax"); OP_END ("get_op_movl_eax_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } op_table_t op_movl_eax_T2; //-------------------------------------------------------------------------------------------------- uint8_t * get_op_movl_trap_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_trap_im"); st->trap = ULONG_MAX; OP_END ("get_op_movl_trap_im"); *len = end - begin; if (*len <= sizeof (ULONG_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_trap_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_trap_T2"); st->trap = T2; OP_END ("get_op_movl_trap_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } op_table_t op_movl_trap_im; op_table_t op_movl_trap_T2; //-------------------------------------------------------------------------------------------------- uint8_t * get_op_movl_T0_T2 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T0_T2"); T0 = T2; OP_END ("get_op_movl_T0_T2"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } uint8_t * get_op_movl_T2_T1 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T2_T1"); T2 = T1; OP_END ("get_op_movl_T2_T1"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } //teawater add for xscale(arm v5) 2005.09.22------------------------------------ uint8_t * get_op_movl_T1_T0 (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_movl_T1_T0"); T1 = T0; OP_END ("get_op_movl_T1_T0"); *len = end - begin; ret = (uint8_t *) begin; return (ret); } //AJ2D-------------------------------------------------------------------------- op_table_t op_movl_T0_T2; op_table_t op_movl_T2_T1; //teawater add for xscale(arm v5) 2005.09.22------------------------------------ op_table_t op_movl_T1_T0; //AJ2D-------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------- int arm2x86_movl_init () { if (op_movl_Tx_im_init ()) { return (-1); } if (op_movl_tmpx_im_init ()) { return (-1); } if (op_movl_Tx_reg_init ()) { return (-1); } if (op_movl_reg_Tx_init ()) { return (-1); } op_movl_eax_T2.op = get_op_movl_eax_T2 (&op_movl_eax_T2.len); if (op_movl_eax_T2.len <= 0) return (-1); op_movl_trap_im.op = get_op_movl_trap_im (&op_movl_trap_im.len); if (op_movl_trap_im.len <= 0) return (-1); op_movl_trap_T2.op = get_op_movl_trap_T2 (&op_movl_trap_T2.len); if (op_movl_trap_T2.len <= 0) return (-1); op_movl_T0_T2.op = get_op_movl_T0_T2 (&op_movl_T0_T2.len); if (op_movl_T0_T2.len <= 0) return (-1); op_movl_T2_T1.op = get_op_movl_T2_T1 (&op_movl_T2_T1.len); if (op_movl_T2_T1.len <= 0) return (-1); //teawater add for xscale(arm v5) 2005.09.22------------------------------------ op_movl_T1_T0.op = get_op_movl_T1_T0 (&op_movl_T1_T0.len); if (op_movl_T1_T0.len <= 0) return (-1); //AJ2D-------------------------------------------------------------------------- return (0); } �����������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_coproc.h�����������������������������������������������������0000644�0001750�0000144�00000003143�10541455476�017607� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_COPROC_H_ #define _ARM2X86_COPROC_H_ extern op_table_t op_ldc_T0_T1; extern op_table_t op_stc_T0_T1; extern op_table_t op_mrc_T0_T1; extern op_table_t op_mcr_T0_T1; extern op_table_t op_cdp_T0_T1; //teawater add for xscale(arm v5) 2005.09.12------------------------------------ extern op_table_t op_mar_T0_T1; extern op_table_t op_mra_T0_T1; extern op_table_t op_mia_T0_T1; extern op_table_t op_miaph_T0_T1; extern op_table_t op_miaxy_T0_T1; //AJ2D-------------------------------------------------------------------------- extern int arm2x86_coproc_init (); static __inline__ void gen_op_add_imm_offset (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword insn) { int offset = (insn & 0xff) * 4; if (!(insn & (1 << 23))) //U offset = -offset; if (offset != 0) gen_op_addl_T1_im (state, tbpp, plen, (ARMword) offset); } #endif //_ARM2X86_COPROC_H_ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_movl.h�������������������������������������������������������0000644�0001750�0000144�00000006633�10541455476�017306� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_MOVL_H_ #define _ARM2X86_MOVL_H_ extern op_table_t op_movl_Tx_im[Tx_MAX + 1]; extern op_table_t op_movl_tmpx_im[tmp_MAX + 1]; extern int op_movl_Tx_reg_maxlen; extern int op_movl_Tx_reg_array_maxlen[Tx_MAX + 1]; extern op_table_t op_movl_Tx_reg[Tx_MAX + 1][16]; extern int op_movl_reg_Tx_maxlen; extern int op_movl_reg_Tx_array_maxlen[Tx_MAX + 1]; extern op_table_t op_movl_reg_Tx[Tx_MAX + 1][16]; extern op_table_t op_movl_eax_T2; extern op_table_t op_movl_trap_im; extern op_table_t op_movl_trap_T2; extern op_table_t op_movl_T0_T2; extern op_table_t op_movl_T2_T1; //teawater add for xscale(arm v5) 2005.09.22------------------------------------ extern op_table_t op_movl_T1_T0; //AJ2D-------------------------------------------------------------------------- extern int arm2x86_movl_init (); static __inline__ void gen_op_movl_Tx_im (ARMul_State * state, uint8_t ** tbpp, int *plen, int Tx, ARMword im) { GEN_OP (*tbpp, *plen, op_movl_Tx_im[Tx]); //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, &im, sizeof(im)); *tbpp += sizeof(im); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (im); } static __inline__ void gen_op_movl_tmpx_im (ARMul_State * state, uint8_t ** tbpp, int *plen, int tmpx, ARMword im) { GEN_OP (*tbpp, *plen, op_movl_tmpx_im[tmpx]); //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, &im, sizeof(im)); *tbpp += sizeof(im); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (im); } static __inline__ void gen_op_movl_Tx_reg (ARMul_State * state, uint8_t ** tbpp, int *plen, int Tx, ARMword reg) { GEN_OP (*tbpp, *plen, op_movl_Tx_reg[Tx][reg]); } static __inline__ void gen_op_movl_reg_Tx (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword reg, int Tx) { GEN_OP (*tbpp, *plen, op_movl_reg_Tx[Tx][reg]); if (reg == 15) { //change pc state->trap = 1; } } static __inline__ void gen_op_movl_trap_im_use_T2 (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword im) { gen_op_movl_Tx_im (state, tbpp, plen, 2, im); GEN_OP (*tbpp, *plen, op_movl_trap_T2); } static __inline__ void gen_op_movl_trap_im (ARMul_State * state, uint8_t ** tbpp, int *plen, ARMword im) { GEN_OP (*tbpp, *plen, op_movl_trap_im); //teawater remove tb_translate_find 2005.10.21---------------------------------- //if (*tbpp) { memcpy(*tbpp, &im, sizeof(im)); *tbpp += sizeof(im); //} //AJ2D-------------------------------------------------------------------------- *plen += sizeof (im); } #endif //_ARM2X86_MOVL_H_ �����������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_mul.h��������������������������������������������������������0000644�0001750�0000144�00000001670�10541455476�017122� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_MUL_H_ #define _ARM2X86_MUL_H_ extern op_table_t op_mul_T0_T1; extern op_table_t op_umull_T0_T1; extern op_table_t op_smull_T0_T1; extern int arm2x86_mul_init (); #endif //_ARM2X86_MUL_H_ ������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/tb.c�����������������������������������������������������������������0000644�0001750�0000144�00000161262�10714545461�015436� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" //teawater 2005-09-12 for gcc-3.3.x compiling, comment below line //#include "arm2x86_self.h" extern mem_bank_t *bank_ptr (ARMword addr); /*ywc 2005-04-22, in armmem.c*/ extern mem_bank_t *insn_bank_ptr (ARMword addr); extern ARMul_State *state; //teawater add for new tb manage function 2005.07.10---------------------------- //static uint32_t tb_tbt_size = 0; //static uint32_t tb_tbp_size = (1024 * 1024 * 32); #define TB_TBT_SIZE skyeye_config.tb_tbt_size #define TB_TBP_SIZE skyeye_config.tb_tbp_size static tb_t *tbt_table = NULL; static int tbt_table_size = 0; static uint8_t *tbp_begin = NULL; static uint8_t *tbp_now = NULL; static uint32_t tbp_now_size = 0; static int tbp_dynamic = 0; static LIST_HEAD (tbp_dynamic_list); //AJ2D-------------------------------------------------------------------------- #if defined(__FreeBSD__) || defined(__APPLE__) #define MAP_ANONYMOUS MAP_ANON #endif static __inline__ int translate_word (ARMul_State * state, ARMword insn, uint8_t * tbp) { int toplen = 0, len = 0; //teawater add for xscale(arm v5) 2005.09.26------------------------------------ ARMword cond, val, op1, shift, rm, rs, rn, rd, sh, y, x; //AJ2D-------------------------------------------------------------------------- uint8_t *begin = tbp; //init begin = tbp; state->trap = 0; //teawater change for debug function 2005.07.09--------------------------------- //breakpoint if (insn == 0xe7ffdefe) { GEN_OP (tbp, len, op_begin); gen_op_movl_trap_im_use_T2 (state, &tbp, &len, TRAP_BREAKPOINT); GEN_OP (tbp, len, op_return); goto out; } //AJ2D-------------------------------------------------------------------------- //teawater add for xscale(arm v5) 2005.09.01------------------------------------ if ((insn & 0xfff000f0) == 0xe1200070) { //BKPT //GEN_OP(tbp, len, op_begin); gen_op_movl_trap_im_use_T2 (state, &tbp, &len, TRAP_INSN_ABORT); GEN_OP (tbp, len, op_return); goto out; } //AJ2D-------------------------------------------------------------------------- //return if debug || irq || fiq || condition cond = (insn >> 28) & 0xff; if (cond == AL || cond == NV) { GEN_OP (tbp, len, op_begin); //some insn need it //if (cond == NV) // goto translate_word_out; } else { gen_op_movl_Tx_im (state, &tbp, &len, 0, cond); GEN_OP (tbp, len, op_begin_test_T0); toplen = len; } if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { ARMword set_cc, logic_cc, shiftop; if (cond == NV) goto translate_word_out; op1 = (insn >> 21) & 0xf; set_cc = (insn >> 20) & 1; //teawater add for xscale(arm v5) 2005.09.01------------------------------------ if (!set_cc & (op1 >= 0x8 && op1 <= 0xb)) { if (state->is_v5) { sh = ((insn >> 4) & 0xf); if (sh == 0x5) { rm = (insn >> 0) & 0xf; rd = (insn >> 12) & 0xf; rn = (insn >> 16) & 0xf; switch (op1) { case 0x8: //qadd gen_op_movl_Tx_reg (state, &tbp, &len, 0, rm); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rd); GEN_OP (tbp, len, op_qaddl_T0_T1_sq); break; case 0x9: //qsub gen_op_movl_Tx_reg (state, &tbp, &len, 0, rm); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rd); GEN_OP (tbp, len, op_qsubl_T0_T1_sq); break; case 0xa: //qdadd gen_op_movl_Tx_reg (state, &tbp, &len, 0, rn); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rn); GEN_OP (tbp, len, op_qaddl_T0_T1_sq); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rm); GEN_OP (tbp, len, op_qaddl_T0_T1_sq); break; case 0xb: //qdsub gen_op_movl_Tx_reg (state, &tbp, &len, 0, rn); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rn); GEN_OP (tbp, len, op_qaddl_T0_T1_sq); GEN_OP (tbp, len, op_movl_T1_T0); gen_op_movl_Tx_reg (state, &tbp, &len, 0, rm); GEN_OP (tbp, len, op_qsubl_T0_T1_sq); break; } gen_op_movl_reg_Tx (state, &tbp, &len, rd, 0); GEN_OP (tbp, len, op_set_q); goto translate_word_end; } else if ((sh & 0x9) == 0x8) { rm = (insn >> 0) & 0xf; rs = (insn >> 8) & 0xf; rn = (insn >> 12) & 0xf; //rdlo rd = (insn >> 16) & 0xf; //rdhi y = (insn >> 6) & 0x1; x = (insn >> 5) & 0x1; gen_op_movl_Tx_reg (state, &tbp, &len, 0, rm); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rs); if (op1 != 0x9) { if (x) { //t GEN_OP (tbp, len, op_hi_T0); } else { //b GEN_OP (tbp, len, op_lo_T0); } GEN_OP (tbp, len, op_signextend_halfword_T0); } if (y) { //t GEN_OP (tbp, len, op_hi_T1); } else { //b GEN_OP (tbp, len, op_lo_T1); } GEN_OP (tbp, len, op_signextend_halfword_T1); switch (op1) { case 0x8: //smlaxy GEN_OP (tbp, len, op_mul_T0_T1); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rn); GEN_OP (tbp, len, op_addl_T0_T1_sq); gen_op_movl_reg_Tx (state, &tbp, &len, rd, 0); GEN_OP (tbp, len, op_set_q); break; case 0x9: if (x) { //smulwy GEN_OP (tbp, len, op_smulwy_T0_T1); gen_op_movl_reg_Tx (state, &tbp, &len, rd, 0); } else { //smlawy //gen_op_movl_Tx_reg(state, &tbp, &len, 2, rn); //GEN_OP(tbp, len, op_smlawy_T2_T1_T0); GEN_OP (tbp, len, op_smulwy_T0_T1); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rn); GEN_OP (tbp, len, op_addl_T0_T1_sq); gen_op_movl_reg_Tx (state, &tbp, &len, rd, 0); GEN_OP (tbp, len, op_set_q); } break; case 0xa: //smlalxy GEN_OP (tbp, len, op_mul_T0_T1); gen_op_movl_Tx_reg (state, &tbp, &len, 1, rn); //rdlo gen_op_movl_Tx_reg (state, &tbp, &len, 2, rd); //rdhi GEN_OP (tbp, len, op_smlalxy_T2_T1_T0); gen_op_movl_reg_Tx (state, &tbp, &len, 1, rn); gen_op_movl_reg_Tx (state, &tbp, &len, 2, rd); break; case 0xb: //smulxy GEN_OP (tbp, len, op_mul_T0_T1); gen_op_movl_reg_Tx (state, &tbp, &len, rd, 0); break; } goto translate_word_end; } else if (sh == 0x1 && op1 == 0xb) { //clz rm = insn & 0xf; gen_op_movl_Tx_reg (state, &tbp, &len, 1, rm); GEN_OP (tbp, len, op_clzl_T0_T1); rd = (insn >> 12) & 0xf; gen_op_movl_reg_Tx (state, &tbp, &len, rd, 0); goto translate_word_end; } } if (op1 == 0x8 || op1 == 0xa) { //mrs gen_op_mrs (state, &tbp, &len, insn); goto translate_word_end; } } //AJ2D-------------------------------------------------------------------------- logic_cc = table_logic_cc[op1] & set_cc; //in arm_arm A 5.1 if (insn & (1 << 25)) { //immediate operand arm_arm A 5.1.3 val = insn & 0xff; shift = (uint8_t) ((insn >> 8) & 0xf) * 2; //ror if (shift) val = (val >> shift) | (val << (32 - shift)); //op=set val to t1 gen_op_movl_Tx_im (state, &tbp, &len, 1, val); if (logic_cc && shift) { //val = ((insn & 0xff) >> (shift - 1)) & 1; //op=set val[31] to C if (val >> 31) { GEN_OP (tbp, len, op_logic_1_sc); } else { GEN_OP (tbp, len, op_logic_0_sc); } } } else { //register rm = (insn) & 0xf; //op=set rm(0-15) to t1 gen_op_movl_Tx_reg (state, &tbp, &len, 1, rm); //teawater add check thumb 2005.07.21------------------------------------------- if (op1 == 0x9 && !set_cc && ((insn >> 8) & 0xf) == 0xf) { //bx or blx(2) uint32_t tmp = (insn >> 4) & 0xf; if (tmp == 0x1) { //bx GEN_OP (tbp, len, op_bx_T1); } else if (tmp == 0x2) { //blx(2) GEN_OP (tbp, len, op_blx_T1); } if (tmp == 0x1 || tmp == 0x2) { state->trap = 1; goto translate_word_end; } } //AJ2D-------------------------------------------------------------------------- shiftop = (insn >> 5) & 3; if (!(insn & (1 << 4))) { //imm shift = (uint8_t) (insn >> 7) & 0x1f; if (shift != 0) { //op=shift, & set CF if logic_cc if (logic_cc) { gen_op_shift_T1_im_sc (state, &tbp, &len, shiftop, shift); } gen_op_shift_T1_im (state, &tbp, &len, shiftop, shift); } else { GEN_OP (tbp, len, op_movl_T2_T1); GEN_OP (tbp, len, op_shift_T1_0[shiftop]); if (logic_cc) { GEN_OP (tbp, len, op_shift_T2_0_sc [shiftop]); GEN_OP (tbp, len, op_set_cf); } } } else { //reg rs = (insn >> 8) & 0xf; //op=set rs(0-15) to t0 gen_op_movl_Tx_reg (state, &tbp, &len, 0, rs); //op=shift, & set CF if logic_cc if (logic_cc) { //op=shift & set CF gen_op_shift_T1_T0_sc (state, &tbp, &len, shiftop); } else { //op=shift gen_op_shift_T1_T0 (state, &tbp, &len, shiftop); } } } if ((op1 == 0x9 || op1 == 0xb) && !set_cc) { //msr T1, psr gen_op_msr (state, &tbp, &len, insn); goto translate_word_end; } //data processing instruction if (op1 != 0x0f && op1 != 0x0d) { //!mov && !mvn rn = (insn >> 16) & 0xf; //op=set rn(0-15) to t0 gen_op_movl_Tx_reg (state, &tbp, &len, 0, rn); } rd = (insn >> 12) & 0xf; arm2x86_get_dp_op[op1] (state, &tbp, &len, set_cc, rd); arm2x86_get_dp_op_setcpsr[op1] (state, &tbp, &len, set_cc, rd); } else { //other instructions op1 = (insn >> 24) & 0xf; sh = (insn >> 5) & 3; if (cond == NV) { //teawater add for xscale(arm v5) 2005.09.15------------------------------------ if (state->is_v5) { switch (op1) { case 0x5: case 0x7: if (((insn >> 12) & 0xf) == 0xf) { //pld Ignored } goto translate_word_out; break; //teawater add check thumb 2005.07.21------------------------------------------- case 0xa: case 0xb: //blx(1) gen_op_movl_trap_im_use_T2 (state, &tbp, &len, TRAP_UNPREDICTABLE); GEN_OP (tbp, len, op_return); goto out; break; //AJ2D-------------------------------------------------------------------------- case 0xc: case 0xd: //ldc2 stc2 if (state->is_XScale && ((insn >> 8) & 0xf) == 0) { //mar mra goto translate_word_out; } break; case 0xe: //cdp2 mrc2 mcr2 if (state->is_XScale && (insn & (1 << 4)) && (!(insn & (1 << 20))) && ((insn >> 8) & 0xf) == 0) { //mia miaph miabb miabt miatb miatt goto translate_word_out; } break; default: goto translate_word_out; break; } } //AJ2D-------------------------------------------------------------------------- else { goto translate_word_out; } } if (sh != 0 && (op1 == 0 || op1 == 1)) { //ldrh strh ldrsh ldrsb gen_op_ldrhstrh (state, &tbp, &len, insn, sh); } else { arm2x86_get_other_op[op1] (state, insn, &tbp, &len); } } translate_word_end: if (state->trap) { GEN_OP (tbp, len, op_return); } if (toplen && begin) { //set jmp length of condition code //begin[toplen-1] = (uint8_t)(len - toplen); int *p_tmp = (int *) (begin + (toplen - sizeof (int))); *p_tmp = len - toplen; } translate_word_out: //r15 += 4 if (!state->trap || toplen) { GEN_OP (tbp, len, op_addpc); state->trap = 0; } //TEA_OUT(GEN_OP(tbp, len, op_return)); out: if (len > TB_INSN_LEN_MAX) { fprintf (stderr, "SKYEYE: TB_INSN_LEN_MAX: insn %x len %d > TB_INSN_LEN_MAX %d.\n", insn, len, TB_INSN_LEN_MAX); skyeye_exit (-1); } /*#ifdef TEA_DEBUG { static int insn_max = 0; if (len > insn_max) { insn_max = len; fprintf(stderr, "\nSKYEYE: insn_max = %d.\n", insn_max); } } #endif //TEA_DEBUG*/ return (len); } //teawater add tb_insn_addr 2005.10.08------------------------------------------ /* static uint8_t * tb_translate(ARMul_State * state, ARMword *addr, ARMword *tb_begin_addr, uint8_t *tbp, ARMword *tran_addr, uint8_t **tbp_now) */ static uint8_t * tb_translate(ARMul_State * state, ARMword *addr, ARMword *tb_begin_addr, tb_t *tbt) { int len; uint8_t *ret = NULL; // ARMword *tb_end_addr = tb_begin_addr + (TB_LEN - (*tran_addr - TB_ALIGN(*tran_addr))) / sizeof(ARMword); ARMword *tb_end_addr = tb_begin_addr + (TB_LEN - (tbt->tran_addr - TB_ALIGN(tbt->tran_addr))) / sizeof(ARMword); //teawater change for local tb branch directly jump 2005.10.10------------------ tb_branch_save_t *e; struct list_head *list,*n; //AJ2D-------------------------------------------------------------------------- //teawater change for local tb branch directly jump 2005.10.10------------------ INIT_LIST_HEAD(&tb_branch_save_list); now_tbt = tbt; tbt->ret_addr = 0; //AJ2D-------------------------------------------------------------------------- for( ; tb_begin_addr < tb_end_addr; tb_begin_addr++) { //set ret if (addr == tb_begin_addr) { ret = tbt->tbp_now; } //set insn_addr tbt->insn_addr[(tbt->tran_addr - tbt->addr) / sizeof(uint8_t *)] = tbt->tbp_now; //translate len = translate_word(state, *tb_begin_addr, tbt->tbp_now); tbt->tbp_now += len; //teawater change for if trap translate stop 2005.07.23------------------------- //*tran_addr += 4; tbt->tran_addr += 4; if (state->trap && ret && (tbt->tran_addr > tbt->ret_addr)) { break; } //AJ2D-------------------------------------------------------------------------- } //teawater change for if trap translate stop 2005.07.23------------------------- //*tbp_now = tbp; if (!state->trap) { GEN_OP(tbt->tbp_now, len, op_return); } //AJ2D-------------------------------------------------------------------------- //teawater change for local tb branch directly jump 2005.10.10------------------ list_for_each_safe(list, n, &tb_branch_save_list) { e = list_entry(list, tb_branch_save_t, list); //memcpy((e->tbp - sizeof(ARMword)), &((uint32_t)tbt->insn_addr[(e->dst_addr - tbt->addr) / sizeof(uint8_t *)] - (uint32_t)e->tbp), sizeof(ARMword)); *((uint32_t *)(e->tbp - sizeof(ARMword))) = (uint32_t)tbt->insn_addr[(e->dst_addr - tbt->addr) / sizeof(uint8_t *)] - (uint32_t)e->tbp; } //AJ2D-------------------------------------------------------------------------- return(ret); } //AJ2D-------------------------------------------------------------------------- //teawater remove tb_translate_find 2005.10.21---------------------------------- /*static uint8_t * tb_translate_find (ARMul_State * state, ARMword * addr, ARMword * tb_begin_addr, uint8_t * tbp) { int len; uint8_t *ret = NULL; ARMword *tb_end_addr = tb_begin_addr + TB_LEN / sizeof (ARMword); for (; tb_begin_addr < tb_end_addr; tb_begin_addr++) { if (addr == tb_begin_addr) { ret = tbp; break; } len = translate_word (state, *tb_begin_addr, NULL); tbp += len; } return (ret); }*/ //AJ2D-------------------------------------------------------------------------- //teawater add tb_insn_addr 2005.10.06------------------------------------------ /* static inline void tb_insert_cache (tb_t * tbt, ARMword addr, uint8_t * ret) { tb_cache_t *e = malloc (sizeof (tb_cache_t)); if (e) { uint32_t cache_num = addr & (TB_TBT_CACHE_MAX - 1); if (!tbt->cache[cache_num].next) INIT_LIST_HEAD (&tbt->cache[cache_num]); e->addr = addr; e->tp = ret; list_add_tail (&e->list, &tbt->cache[cache_num]); } else { TEA_OUT (fprintf (stderr, "SKYEYE: tb_find: Error allocating mem for cache.\n")); } } static inline uint8_t * tb_find_cache (tb_t * tbt, ARMword addr) { tb_cache_t *e; struct list_head *list, *n; uint32_t cache_num = addr & (TB_TBT_CACHE_MAX - 1); if (tbt->cache[cache_num].next) { list_for_each_safe (list, n, &tbt->cache[cache_num]) { e = list_entry (list, tb_cache_t, list); if (e->addr == addr) { return (e->tp); } } } return (NULL); } static inline void tb_clear_cache (tb_t * tbt) { tb_cache_t *e; struct list_head *list, *n; uint32_t cache_num; for (cache_num = 0; cache_num < TB_TBT_CACHE_MAX; cache_num++) { if (tbt->cache[cache_num].next) { list_for_each_safe (list, n, &tbt->cache[cache_num]) { e = list_entry (list, tb_cache_t, list); list_del_init (&e->list); free (e); } } } } */ //AJ2D-------------------------------------------------------------------------- static inline void tb_get_tbp (tb_t * tbt) { tb_t *e; struct list_head *list; if (tbp_now_size) { tbt->tbp = tbp_now; tbp_now += TB_TBP_MAX; tbp_now_size -= TB_TBP_MAX; } else { //get the oldest tbt from tbp_dynamic_list's head if (list_empty (&tbp_dynamic_list)) { fprintf (stderr, "SKYEYE: mem_reset: some bug.\n"); skyeye_exit (-1); } e = list_entry (tbp_dynamic_list.next, tb_t, list); tbt->tbp = e->tbp; e->tbp = NULL; //teawater add tb_insn_addr 2005.10.06------------------------------------------ /*if (e->ted) { tb_clear_cache(e); e->ted = 0; }*/ e->ted = 0; //AJ2D-------------------------------------------------------------------------- list_del_init (&e->list); } } static inline mem_bank_t * tb_get_mbp (ARMword addr, int *bank_num) { mem_bank_t *ret; ret = insn_bank_ptr (addr); if (ret) { *bank_num = ret - state->mem_bank->mem_banks; } return (ret); } uint8_t * tb_find (ARMul_State * state, ARMword ADDR) { uint8_t *ret = NULL; ARMword addr, align_addr; ARMword *real_begin_addr, *real_addr; static ARMword save_align_addr = 0x1; static tb_t *tbt; static uint8_t *tbp; static mem_bank_t *mbp; static int bank_num = -1; //get addr & align_addr if (mmu_v2p_dbct (state, ADDR, &addr)) { goto out; } align_addr = TB_ALIGN (addr); if (align_addr == save_align_addr) { goto get_ret; } //init bank_num = -1; save_align_addr = 0x1; //get tbt if (tbt_table_size) { //dynamic tbt tbt = &(tbt_table [align_addr & (uint32_t) (tbt_table_size - 1)]); if (tbt->addr != align_addr) { if (tbt->ted) { //teawater add tb_insn_addr 2005.10.06------------------------------------------ //tb_clear_cache(tbt); //AJ2D-------------------------------------------------------------------------- tbt->ted = 0; } tbt->addr = align_addr; } //get tbt->tbp if (!tbt->tbp) { tb_get_tbp (tbt); } else { if (tbp_dynamic) { list_del_init (&tbt->list); } } } else { //static tbt mbp = tb_get_mbp (align_addr, &bank_num); if (!mbp) { goto out; } if (!state->mem.tbt[bank_num]) { if (!tbp_dynamic) { state->mem.tbp[bank_num] = mmap (NULL, state->mem.rom_size[bank_num] / sizeof (ARMword) * TB_INSN_LEN_MAX + state->mem.rom_size[bank_num] / TB_LEN * op_return.len, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); if (state->mem.tbp[bank_num] == MAP_FAILED) { fprintf (stderr, "SKYEYE: mem_reset: Error allocating mem for bank number %d.\n", bank_num); skyeye_exit (-1); } } state->mem.tbt[bank_num] = malloc (state->mem.rom_size[bank_num] / TB_LEN * sizeof (tb_t)); if (!state->mem.tbt[bank_num]) { fprintf (stderr, "SKYEYE: mem_reset: Error allocating mem for bank number %d.\n", bank_num); skyeye_exit (-1); } memset (state->mem.tbt[bank_num], 0, state->mem.rom_size[bank_num] / TB_LEN * sizeof (tb_t)); } tbt = &(state->mem. tbt[bank_num][(align_addr - mbp->addr) / TB_LEN]); //teawater add tb_insn_addr 2005.10.08------------------------------------------ tbt->addr = align_addr; //AJ2D-------------------------------------------------------------------------- //get tbt->tbp if (!tbt->tbp) { if (tbp_dynamic) { //dynamic tbp tb_get_tbp (tbt); } else { tbt->tbp = &(state->mem. tbp[bank_num][(align_addr - mbp->addr) / sizeof (ARMword) * TB_INSN_LEN_MAX + (align_addr - mbp->addr) / TB_LEN * op_return.len]); } } else { if (tbp_dynamic) { list_del_init (&tbt->list); } } } //get tbp tbp = tbt->tbp; //set tb_now to check the current running block is written. state->tb_now = (void *) tbt; //set save_align_addr save_align_addr = align_addr; //add tbt to tbp_dynamic_list's tail to be the newest one if (tbp_dynamic) { list_add_tail (&tbt->list, &tbp_dynamic_list); } //find ret from tb get_ret: if (tbt->ted) { //tbt has been translated //teawater add last use addr 2005.10.10----------------------------------------- if (tbt->last_addr == addr) { return(tbt->last_tbp); } //addr is align /*if (addr == align_addr) { ret = tbp; goto out; }*/ //AJ2D-------------------------------------------------------------------------- if (addr >= tbt->tran_addr) { //block need continue translate if (bank_num == -1) { mbp = tb_get_mbp (align_addr, &bank_num); if (!mbp) { goto out; } } real_begin_addr = &(state->mem. rom[bank_num][(align_addr - mbp->addr) / sizeof (ARMword)]) + (tbt->tran_addr - align_addr) / sizeof (ARMword); real_addr = real_begin_addr + (addr - tbt->tran_addr) / sizeof (ARMword); //teawater add tb_insn_addr 2005.10.08------------------------------------------ //ret = tb_translate(state, real_addr, real_begin_addr, tbt->tbp_now, &tbt->tran_addr, &tbt->tbp_now); ret = tb_translate(state, real_addr, real_begin_addr, tbt); //AJ2D-------------------------------------------------------------------------- } else { //teawater add tb_insn_addr 2005.10.08------------------------------------------ /*//find in cache ret = tb_find_cache(tbt, addr); if (ret) { goto out; } if (bank_num == -1) { mbp = tb_get_mbp(align_addr, &bank_num); if(!mbp) { goto out; } } real_begin_addr = &(state->mem.rom[bank_num][(align_addr - mbp->addr) / sizeof(ARMword)]); real_addr = real_begin_addr + (addr - align_addr) / sizeof(ARMword); ret = tb_translate_find(state, real_addr, real_begin_addr, tbp);*/ //find in insn_addr ret = tbt->insn_addr[(addr - align_addr) / sizeof(uint8_t *)]; //AJ2D-------------------------------------------------------------------------- } } else { //tbt has not been translated if (bank_num == -1) { mbp = tb_get_mbp (align_addr, &bank_num); if (!mbp) { goto out; } } real_begin_addr = &(state->mem. rom[bank_num][(align_addr - mbp->addr) / sizeof (ARMword)]); real_addr = real_begin_addr + (addr - align_addr) / sizeof (ARMword); tbt->tran_addr = align_addr; //teawater add tb_insn_addr 2005.10.08------------------------------------------ //ret = tb_translate(state, real_addr, real_begin_addr, tbp, &tbt->tran_addr, &tbt->tbp_now); tbt->tbp_now = tbp; ret = tb_translate(state, real_addr, real_begin_addr, tbt); /*if (ret) { tbt->ted = 1; }*/ tbt->ted = 1; //AJ2D-------------------------------------------------------------------------- } //teawater add tb_insn_addr 2005.10.08------------------------------------------ /*if (ret) { tb_insert_cache(tbt, addr, ret); }*/ //AJ2D-------------------------------------------------------------------------- out: //teawater add last use addr 2005.10.10----------------------------------------- if (ret) { tbt->last_addr = addr; tbt->last_tbp = ret; } //AJ2D-------------------------------------------------------------------------- return (ret); } int tb_setdirty (ARMul_State * state, ARMword addr, mem_bank_t * mbp) { ARMword align_addr = TB_ALIGN (addr); static ARMword save_align_addr = 0x1; static tb_t *tbt = NULL; if (save_align_addr == align_addr) { goto setdirty; } save_align_addr = 0x1; //get tbt if (tbt_table_size) { tbt = &(tbt_table [align_addr & (uint32_t) (tbt_table_size - 1)]); if (tbt->addr != align_addr) { return (0); } } else { int bank_num; if (!mbp) { mbp = tb_get_mbp (align_addr, &bank_num); if (!mbp) { return (0); } } else { bank_num = mbp - state->mem_bank->mem_banks; } if (!state->mem.tbt[bank_num]) { return (0); } tbt = &(state->mem. tbt[bank_num][(align_addr - mbp->addr) / TB_LEN]); } save_align_addr = align_addr; setdirty: if (tbt->ted) { //teawater add tb_insn_addr 2005.10.09------------------------------------------ //tb_clear_cache(tbt); //AJ2D-------------------------------------------------------------------------- tbt->ted = 0; switch (state->cpu->cpu_val & state->cpu->cpu_mask) { case SA1100: case SA1110: mmu_wb_drain_all (state, (&state->mmu.u.sa_mmu.wb_t)); break; case 0x41009200: mmu_wb_drain_all (state, (&state->mmu.u.arm920t_mmu.wb_t)); break; }; } return (0); } int tb_insn_len_max = 0; int tb_insn_len_max_init (ARMul_State * state) { int dp_len = 0, other_len = 0; //return if debug || irq || fiq || condition if (op_begin.len > op_movl_Tx_im[0].len + sizeof (ARMword) + op_begin_test_T0.len) { tb_insn_len_max += op_begin.len; } else { tb_insn_len_max += op_movl_Tx_im[0].len + sizeof (ARMword) + op_begin_test_T0.len; } //end tb_insn_len_max += op_return.len; tb_insn_len_max += op_addpc.len; //TEA_OUT(tb_insn_len_max += op_return.len); //dp_len { int dp_head_len = 0; int sm_head; int op_setcpsr_nzc_len = 0, op_setcpsr_nzc_setr15_len = 0, op_setcpsr_nzc_notsetr15_len = 0, op_setcpsr_nzc_setreg_len = 0; int op_setcpsr_nzcv_len = 0, op_setcpsr_nzcv_setr15_len = 0, op_setcpsr_nzcv_notsetr15_len = 0, op_setcpsr_nzcv_setreg_len = 0; int dp_tmp1; //dp_head_len { int dp_head_imm_len = 0, dp_head_reg_len = 0; //dp_head_imm_len dp_head_imm_len += op_movl_Tx_im[1].len; dp_head_imm_len += sizeof (ARMword); if (op_logic_1_sc.len > op_logic_0_sc.len) { dp_head_imm_len += op_logic_1_sc.len; } else { dp_head_imm_len += op_logic_0_sc.len; } //dp_head_reg_len { int dp_head_reg_imm_len = 0, dp_head_reg_reg_len = 0; dp_head_reg_len += op_movl_Tx_reg_array_maxlen[1]; //dp_head_reg_imm_len //shift != 0 dp_head_reg_imm_len += op_shift_T1_im_sc_maxlen; dp_head_reg_imm_len += op_set_cf.len; dp_head_reg_imm_len += op_shift_T1_im_maxlen; dp_head_reg_imm_len += sizeof (uint8_t); //shift == 0 dp_tmp1 = op_movl_T2_T1.len; dp_tmp1 += op_shift_T1_0_maxlen; dp_tmp1 += op_shift_T2_0_sc_maxlen; dp_tmp1 += op_set_cf.len; //compare if (dp_tmp1 > dp_head_reg_imm_len) dp_head_reg_imm_len = dp_tmp1; //dp_head_reg_reg_len if (op_shift_T1_T0_sc_maxlen + op_set_cf.len > op_shift_T1_T0_maxlen) { dp_head_reg_reg_len += op_shift_T1_T0_sc_maxlen + op_set_cf.len; } else { dp_head_reg_reg_len += op_shift_T1_T0_maxlen; } dp_head_reg_reg_len += op_movl_Tx_reg_array_maxlen[0]; if (dp_head_reg_imm_len > dp_head_reg_reg_len) { dp_head_reg_len += dp_head_reg_imm_len; } else { dp_head_reg_len += dp_head_reg_reg_len; } } if (dp_head_imm_len > dp_head_reg_len) { dp_head_len = dp_head_imm_len; } else { dp_head_len = dp_head_reg_len; } } //op_setcpsr_nzc_len op_setcpsr_nzc_len += op_logic_T0_sn.len; //op_setcpsr_nzc_len += op_set_nf.len; op_setcpsr_nzc_len += op_logic_T0_sz.len; //op_setcpsr_nzc_len += op_set_zf.len; //op_setcpsr_nzc_len += op_set_cf.len; op_setcpsr_nzc_len += op_set_nzcf.len; //op_setcpsr_nzcv_len op_setcpsr_nzcv_len += op_logic_T0_sn.len; //op_setcpsr_nzcv_len += op_set_nf.len; op_setcpsr_nzcv_len += op_logic_T0_sz.len; //op_setcpsr_nzcv_len += op_set_zf.len; //op_setcpsr_nzcv_len += op_set_cf.len; //op_setcpsr_nzcv_len += op_set_vf.len; op_setcpsr_nzcv_len += op_set_nzcvf.len; //op_setcpsr_nzc_setreg op_setcpsr_nzc_notsetr15_len += op_setcpsr_nzc_len; op_setcpsr_nzc_notsetr15_len += op_movl_reg_Tx_array_maxlen[0]; op_setcpsr_nzc_setr15_len += op_movl_reg_Tx_array_maxlen[0]; op_setcpsr_nzc_setr15_len += op_movl_Tx_im[2].len + sizeof (ARMword) + op_movl_trap_T2.len; if (op_setcpsr_nzc_notsetr15_len > op_setcpsr_nzc_setr15_len) { op_setcpsr_nzc_setreg_len += op_setcpsr_nzc_notsetr15_len; } else { op_setcpsr_nzc_setreg_len += op_setcpsr_nzc_setr15_len; } //op_setcpsr_nzcv_setreg op_setcpsr_nzcv_notsetr15_len += op_setcpsr_nzcv_len; op_setcpsr_nzcv_notsetr15_len += op_movl_reg_Tx_array_maxlen[0]; op_setcpsr_nzcv_setr15_len += op_movl_reg_Tx_array_maxlen[0]; op_setcpsr_nzcv_setr15_len += op_movl_Tx_im[2].len + sizeof (ARMword) + op_movl_trap_T2.len; if (op_setcpsr_nzcv_notsetr15_len > op_setcpsr_nzcv_setr15_len) { op_setcpsr_nzcv_setreg_len += op_setcpsr_nzcv_notsetr15_len; } else { op_setcpsr_nzcv_setreg_len += op_setcpsr_nzcv_setr15_len; } //mrs if (op_mrs_T0_spsr.len > op_mrs_T0_cpsr.len) { dp_len += op_mrs_T0_spsr.len; } else { dp_len += op_mrs_T0_cpsr.len; } dp_len += op_movl_reg_Tx_array_maxlen[0]; TEA_OUT (printf ("mrs insn's max len is %d\n", dp_len + tb_insn_len_max)); //teawater add for xscale(arm v5) 2005.09.14------------------------------------] //clz dp_tmp1 = 0; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_clzl_T0_T1.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("clz insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //AJ2D-------------------------------------------------------------------------- //teawater add for xscale(arm v5) 2005.09.26------------------------------------ //qadd dp_tmp1 = 0; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_qaddl_T0_T1_sq.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; dp_tmp1 += op_set_q.len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("qadd insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //qsub dp_tmp1 = 0; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_qsubl_T0_T1_sq.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; dp_tmp1 += op_set_q.len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("qsub insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //qdadd dp_tmp1 = 0; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_qaddl_T0_T1_sq.len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_qaddl_T0_T1_sq.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; dp_tmp1 += op_set_q.len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("qdadd insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //qdsub dp_tmp1 = 0; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_qaddl_T0_T1_sq.len; dp_tmp1 += op_movl_T1_T0.len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_qsubl_T0_T1_sq.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; dp_tmp1 += op_set_q.len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("qdsub insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //sm_head sm_head = 0; sm_head += op_movl_Tx_reg_array_maxlen[0]; sm_head += op_movl_Tx_reg_array_maxlen[1]; if (op_hi_T0.len > op_lo_T0.len) { sm_head += op_hi_T0.len; } else { sm_head += op_lo_T0.len; } sm_head += op_signextend_halfword_T0.len; if (op_hi_T1.len > op_lo_T1.len) { sm_head += op_hi_T1.len; } else { sm_head += op_lo_T1.len; } sm_head += op_signextend_halfword_T1.len; //smlaxy dp_tmp1 = sm_head; dp_tmp1 += op_mul_T0_T1.len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_addl_T0_T1_sq.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; dp_tmp1 += op_set_q.len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("smlaxy insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //smulwy dp_tmp1 = sm_head; dp_tmp1 += op_smulwy_T0_T1.len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("smulwy insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //smlawy dp_tmp1 = sm_head; dp_tmp1 += op_smulwy_T0_T1.len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_addl_T0_T1_sq.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; dp_tmp1 += op_set_q.len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("smlawy insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //smlalxy dp_tmp1 = sm_head; dp_tmp1 += op_mul_T0_T1.len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; dp_tmp1 += op_movl_Tx_reg_array_maxlen[2]; dp_tmp1 += op_smlalxy_T2_T1_T0.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[1]; dp_tmp1 += op_movl_reg_Tx_array_maxlen[2]; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("smlalxy insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //smulxy dp_tmp1 = sm_head; dp_tmp1 += op_mul_T0_T1.len; dp_tmp1 += op_movl_reg_Tx_array_maxlen[0]; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("smulxy insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //AJ2D-------------------------------------------------------------------------- //teawater add check thumb 2005.07.21------------------------------------------- //bx or blx(2) dp_tmp1 += op_movl_Tx_reg_array_maxlen[1]; if (op_bx_T1.len > op_blx_T1.len) { dp_tmp1 += op_bx_T1.len; } else { dp_tmp1 += op_blx_T1.len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("bx or blx(2) insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //AJ2D-------------------------------------------------------------------------- //msr dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_im[0].len + sizeof (ARMword); if (op_msr_spsr_T0_T1.len > op_msr_cpsr_T0_T1.len) { dp_tmp1 += op_msr_spsr_T0_T1.len; } else { dp_tmp1 += op_msr_spsr_T0_T1.len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("msr insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //and dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_andl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_setreg_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("and insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //eor dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_eorl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_setreg_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("eor insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //sub dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; if (op_subl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len > op_subl_T0_T1.len + op_setcpsr_nzcv_setr15_len) { dp_tmp1 += op_subl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len; } else { dp_tmp1 += op_subl_T0_T1.len + op_setcpsr_nzcv_setr15_len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("sub insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //rsb dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; if (op_rsbl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len > op_rsbl_T0_T1.len + op_setcpsr_nzcv_setr15_len) { dp_tmp1 += op_rsbl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len; } else { dp_tmp1 += op_rsbl_T0_T1.len + op_setcpsr_nzcv_setr15_len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("rsb insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //add dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; if (op_addl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len > op_addl_T0_T1.len + op_setcpsr_nzcv_setr15_len) { dp_tmp1 += op_addl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len; } else { dp_tmp1 += op_addl_T0_T1.len + op_setcpsr_nzcv_setr15_len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("add insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //adc dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; if (op_adcl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len > op_adcl_T0_T1.len + op_setcpsr_nzcv_setr15_len) { dp_tmp1 += op_adcl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len; } else { dp_tmp1 += op_adcl_T0_T1.len + op_setcpsr_nzcv_setr15_len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("adc insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //sbc dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; if (op_sbcl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len > op_sbcl_T0_T1.len + op_setcpsr_nzcv_setr15_len) { dp_tmp1 += op_sbcl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len; } else { dp_tmp1 += op_sbcl_T0_T1.len + op_setcpsr_nzcv_setr15_len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("sbc insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //rsc dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; if (op_rscl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len > op_rscl_T0_T1.len + op_setcpsr_nzcv_setr15_len) { dp_tmp1 += op_rscl_T0_T1_scv.len + op_setcpsr_nzcv_notsetr15_len; } else { dp_tmp1 += op_rscl_T0_T1.len + op_setcpsr_nzcv_setr15_len; } if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("rsc insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //tst dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_andl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("tst insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //teq dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_eorl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("teq insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //cmp dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_subl_T0_T1_scv.len; dp_tmp1 += op_setcpsr_nzcv_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("cmp insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //cmn dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_addl_T0_T1_scv.len; dp_tmp1 += op_setcpsr_nzcv_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("cmn insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //orr dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_orrl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_setreg_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("orr insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //mov dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_setreg_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("mov insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //bic dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_movl_Tx_reg_array_maxlen[0]; dp_tmp1 += op_bicl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_setreg_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("bic insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); //mvn dp_tmp1 = 0; dp_tmp1 += dp_head_len; dp_tmp1 += op_notl_T0_T1.len; dp_tmp1 += op_setcpsr_nzc_setreg_len; if (dp_tmp1 > dp_len) { dp_len = dp_tmp1; } TEA_OUT (printf ("mvn insn's max len is %d\n", dp_tmp1 + tb_insn_len_max)); } //other_len { int op_add_data_offset_len = 0, ldr_head_len = 0, str_head_len = 0; int other_tmp1, other_tmp2; //op_add_data_offset_len op_add_data_offset_len += op_movl_Tx_reg_array_maxlen[2]; op_add_data_offset_len += op_shift_T2_im_maxlen; op_add_data_offset_len += sizeof (uint8_t); if (op_subl_T1_T2.len > op_addl_T1_T2.len) { op_add_data_offset_len += op_subl_T1_T2.len; } else { op_add_data_offset_len += op_addl_T1_T2.len; } if (op_addl_T1_im.len + sizeof (ARMword) > op_add_data_offset_len) { op_add_data_offset_len = op_addl_T1_im.len + sizeof (ARMword); } //ldr_head_len str_head_len ldr_head_len += op_movl_Tx_reg_array_maxlen[1]; ldr_head_len += op_add_data_offset_len; ldr_head_len += op_movl_reg_Tx_array_maxlen[1]; //if (!state->is_XScale) { if (state->abort_model > 1) { ldr_head_len += op_test_dataabort_ret.len; } str_head_len = ldr_head_len; ldr_head_len += op_movl_reg_Tx_array_maxlen[0]; //if (!state->is_XScale) { if (state->abort_model > 1) { ldr_head_len += op_test_dataabort.len; } str_head_len += op_movl_Tx_reg_array_maxlen[0]; //ldrh other_tmp1 = ldr_head_len; other_tmp1 += op_ldrh_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldrh insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //ldrsb other_tmp1 = ldr_head_len; other_tmp1 += op_ldrb_T0_T1.len; other_tmp1 += op_signextend_byte_T0.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldrsb insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //ldrsh other_tmp1 = ldr_head_len; other_tmp1 += op_ldrh_T0_T1.len; other_tmp1 += op_signextend_halfword_T0.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldrsh insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //ldrb other_tmp1 = ldr_head_len; other_tmp1 += op_ldrb_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldrb insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //ldr other_tmp1 = ldr_head_len; other_tmp1 += op_ldr_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldr insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //strh other_tmp1 = str_head_len; other_tmp1 += op_strh_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("strh insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //teawater add for xscale(arm v5) 2005.09.26------------------------------------ //ldrd other_tmp1 = ldr_head_len; other_tmp1 += op_ldrd_T0_T2_T1.len; if (state->abort_model > 1) { other_tmp1 += op_test_dataabort_ret.len; } other_tmp1 += op_movl_reg_Tx_array_maxlen[0]; other_tmp1 += op_movl_reg_Tx_array_maxlen[2]; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldrd insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //strd other_tmp1 = ldr_head_len; other_tmp1 += op_movl_reg_Tx_array_maxlen[0]; other_tmp1 += op_movl_reg_Tx_array_maxlen[2]; other_tmp1 += op_strd_T0_T2_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("strd insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //AJ2D-------------------------------------------------------------------------- //strb other_tmp1 = str_head_len; other_tmp1 += op_strb_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("strb insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //str other_tmp1 = str_head_len; other_tmp1 += op_str_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("str insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //mul other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_mul_T0_T1.len; other_tmp1 += op_logic_T0_sn.len; other_tmp1 += op_set_nf.len; other_tmp1 += op_logic_T0_sz.len; other_tmp1 += op_set_zf.len; other_tmp1 += op_movl_reg_Tx_array_maxlen[0]; TEA_OUT (printf ("mul insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //mla other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_addl_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("mla insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //mull other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; if (op_smull_T0_T1.len > op_umull_T0_T1.len) { other_tmp1 += op_smull_T0_T1.len; } else { other_tmp1 += op_umull_T0_T1.len; } other_tmp1 += op_movl_Tx_reg_array_maxlen[2]; other_tmp1 += op_movl_eax_T2.len; other_tmp1 += op_movl_Tx_reg_array_maxlen[2]; other_tmp1 += op_addq_T0_T1_eax_T2.len; other_tmp1 += op_logic_T0_sn.len; other_tmp1 += op_set_nf.len; other_tmp1 += op_logic_T0_sz.len; other_tmp1 += op_set_zf.len; other_tmp1 += op_movl_reg_Tx_array_maxlen[0]; other_tmp1 += op_movl_reg_Tx_array_maxlen[1]; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("mull insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //swp other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; if (op_ldrb_T2_T1.len + op_strb_T0_T1.len > op_ldr_T2_T1.len + op_str_T0_T1.len) { other_tmp1 += op_ldrb_T2_T1.len + op_strb_T0_T1.len; } else { other_tmp1 += op_ldr_T2_T1.len + op_str_T0_T1.len; } other_tmp1 += op_movl_reg_Tx_array_maxlen[2]; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("swp insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //insn_undef other_tmp1 = 0; other_tmp1 += op_movl_Tx_im[2].len + sizeof (ARMword) + op_movl_trap_T2.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("insn_undef insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //ldm stm other_tmp1 = 0; other_tmp1 += op_test_cpsr_ret_UNP.len; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_movl_Tx_im[2].len + sizeof (ARMword) + op_movl_trap_T2.len; other_tmp1 += op_addl_T1_im.len + sizeof (ARMword); other_tmp1 += op_movl_Tx_im[0].len + sizeof (ARMword); other_tmp2 = op_ldm_user_T1_T0.len; if (op_ldm_T1_T0.len > other_tmp2) { other_tmp2 = op_ldm_T1_T0.len; } if (op_stm_user_T1_T0.len > other_tmp2) { other_tmp2 = op_stm_user_T1_T0.len; } if (op_stm_T1_T0.len > other_tmp2) { other_tmp2 = op_stm_T1_T0.len; } other_tmp1 += other_tmp2; //if (!state->is_XScale) { if (state->abort_model > 1) { ldr_head_len += op_test_dataabort.len; } other_tmp1 += op_addl_T1_im.len + sizeof (ARMword); other_tmp1 += op_movl_reg_Tx_array_maxlen[1]; //if (!state->is_XScale) { if (state->abort_model > 1) { ldr_head_len += op_test_dataabort_ret.len; } if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldm stm insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //b other_tmp1 = 0; other_tmp1 += op_b_offset.len + sizeof (ARMword); //teawater change for local tb branch directly jump 2005.10.21------------------ other_tmp1 += op_local_b_offset.len; //AJ2D-------------------------------------------------------------------------- if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("b insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //bl other_tmp1 = 0; other_tmp1 += op_bl_offset.len + sizeof (ARMword); //teawater change for local tb branch directly jump 2005.10.21------------------ other_tmp1 += op_local_b_offset.len; //AJ2D-------------------------------------------------------------------------- if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("bl insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //teawater add for xscale(arm v5) 2005.09.14------------------------------------ //mar other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_mar_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("mar insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //mra other_tmp1 += op_mra_T0_T1.len; other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("mra insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //AJ2D-------------------------------------------------------------------------- //ldc stc other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_addl_T1_im.len + sizeof (ARMword); other_tmp1 += op_movl_Tx_im[0].len + sizeof (ARMword); if (op_ldc_T0_T1.len > op_stc_T0_T1.len) { other_tmp1 += op_ldc_T0_T1.len; } else { other_tmp1 += op_stc_T0_T1.len; } other_tmp1 += op_movl_reg_Tx_array_maxlen[1]; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("ldc stc insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //teawater add for xscale(arm v5) 2005.09.14------------------------------------ //mia other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_smull_T0_T1.len; other_tmp1 += op_mia_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("mia insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //miaph other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_miaph_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("miaph insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //miabb other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_lo_T0.len; other_tmp1 += op_lo_T1.len; other_tmp1 += op_miaxy_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("miabb insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //miabt other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_lo_T0.len; other_tmp1 += op_hi_T1.len; other_tmp1 += op_miaxy_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("miabt insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //miatb other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_hi_T0.len; other_tmp1 += op_lo_T1.len; other_tmp1 += op_miaxy_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("miatb insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //miatt other_tmp1 = 0; other_tmp1 += op_movl_Tx_reg_array_maxlen[0]; other_tmp1 += op_movl_Tx_reg_array_maxlen[1]; other_tmp1 += op_hi_T0.len; other_tmp1 += op_hi_T1.len; other_tmp1 += op_miaxy_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("miatt insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //AJ2D-------------------------------------------------------------------------- //mrc other_tmp1 = 0; other_tmp1 += op_movl_Tx_im[0].len + sizeof (ARMword); other_tmp1 += op_movl_Tx_im[1].len + sizeof (ARMword); other_tmp1 += op_mrc_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("mrc insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //mcr other_tmp1 = 0; other_tmp1 += op_movl_Tx_im[0].len + sizeof (ARMword); other_tmp1 += op_movl_Tx_im[1].len + sizeof (ARMword); other_tmp1 += op_mcr_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("mcr insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //cdp other_tmp1 = 0; other_tmp1 += op_movl_Tx_im[0].len + sizeof (ARMword); other_tmp1 += op_movl_Tx_im[1].len + sizeof (ARMword); other_tmp1 += op_cdp_T0_T1.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("cdp insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); //swi other_tmp1 = 0; other_tmp1 += op_movl_Tx_im[2].len + sizeof (ARMword) + op_movl_trap_T2.len; if (other_tmp1 > other_len) { other_len = other_tmp1; } TEA_OUT (printf ("swi insn's max len is %d\n", other_tmp1 + tb_insn_len_max)); } if (dp_len > other_len) { tb_insn_len_max += dp_len; } else { tb_insn_len_max += other_len; } TEA_OUT (printf ("tb_insn_len_max is %d\n", tb_insn_len_max)); return (0); } //teawater add for new tb manage function 2005.07.10---------------------------- int tb_memory_init (ARMul_State * state) { int i; uint64_t tmp_u64; mem_bank_t *mbp; //tbt if (TB_TBT_SIZE) { //get align tbt size TB_TBT_SIZE = ALIGN (TB_TBT_SIZE, sizeof (tb_cache_t)); if (TB_TBT_SIZE < sizeof (tb_cache_t)) { fprintf (stderr, "SKYEYE: tb_memory_init: TB_TBT_SIZE %u is too little.\n", (unsigned int) TB_TBT_SIZE); return (-1); } //get tbt max size tmp_u64 = 0; for (i = 0; i < state->mem_bank->current_num; i++) { tmp_u64 += state->mem_bank->mem_banks[i].len; } tmp_u64 = tmp_u64 / TB_LEN * sizeof (tb_cache_t); if (TB_TBT_SIZE >= tmp_u64) { //if set size >= max size, use the simple function TB_TBT_SIZE = 0; } else { //get mem by TB_TBT_SIZE tbt_table = (tb_t *) malloc (TB_TBT_SIZE); if (!tbt_table) { fprintf (stderr, "SKYEYE: tb_memory_init: Error allocating mem.\n"); return (-1); } memset (tbt_table, 0, TB_TBT_SIZE); tbt_table_size = TB_TBT_SIZE / sizeof (tb_cache_t); } } //tbp if (TB_TBP_SIZE) { //get align tbp size TB_TBP_SIZE = ALIGN (TB_TBP_SIZE, TB_TBP_MAX); if (TB_TBP_SIZE < TB_TBP_MAX) { fprintf (stderr, "SKYEYE: tb_memory_init: TB_TBP_SIZE %u is too little.\n", (unsigned int) TB_TBP_SIZE); return (-1); } } if (TB_TBT_SIZE) { //get tbp max size tmp_u64 = tbt_table_size * TB_LEN / sizeof (ARMword) * TB_INSN_LEN_MAX + tbt_table_size * op_return.len; if (TB_TBP_SIZE == 0 || TB_TBP_SIZE > tmp_u64) { TB_TBP_SIZE = tmp_u64; } else { tbp_dynamic = 1; } } else { if (TB_TBP_SIZE) { //get tbp max size tmp_u64 = 0; for (i = 0; i < state->mem_bank->current_num; i++) { tmp_u64 += state->mem_bank->mem_banks[i].len; } tmp_u64 = tmp_u64 / sizeof (ARMword) * TB_INSN_LEN_MAX + tmp_u64 / TB_LEN * op_return.len; if (TB_TBP_SIZE >= tmp_u64) { //if set size >= max size, use the simple function TB_TBP_SIZE = 0; } else { tbp_dynamic = 1; } } } if (TB_TBP_SIZE) { //get mem by TB_TBP_SIZE tbp_begin = mmap (NULL, TB_TBP_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); if (tbp_begin == MAP_FAILED) { fprintf (stderr, "SKYEYE: tb_memory_init: Error allocating mem.\n"); return (-1); } tbp_now_size = TB_TBP_SIZE; tbp_now = tbp_begin; } if (TB_TBT_SIZE) { printf ("dbct translate block entry use memory 0x%08x bytes.\n", TB_TBT_SIZE); } if (TB_TBP_SIZE) { printf ("dbct translate block use memory 0x%08x bytes.\n", TB_TBP_SIZE); } return (0); } //AJ2D-------------------------------------------------------------------------- ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_psr.h��������������������������������������������������������0000644�0001750�0000144�00000004701�10541455476�017127� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #ifndef _ARM2X86_PSR_H_ #define _ARM2X86_PSR_H_ extern op_table_t op_set_nf; extern op_table_t op_set_zf; extern op_table_t op_set_cf; extern op_table_t op_set_vf; extern op_table_t op_set_nzcf; extern op_table_t op_set_nzcvf; extern op_table_t op_logic_T0_sn; extern op_table_t op_logic_T0_sz; extern op_table_t op_logic_T1_sn; extern op_table_t op_logic_T1_sz; extern op_table_t op_logic_0_sc; extern op_table_t op_logic_1_sc; extern op_table_t op_logicq_T0_T1_sz; extern op_table_t op_mrs_T0_cpsr; extern op_table_t op_mrs_T0_spsr; extern op_table_t op_msr_spsr_T0_T1; extern op_table_t op_msr_cpsr_T0_T1; //teawater add for xscale(arm v5) 2005.09.21------------------------------------ extern op_table_t op_set_q; //AJ2D-------------------------------------------------------------------------- //extern op_table_t op_writesr15; extern int arm2x86_psr_init (); static __inline__ uint32_t gen_op_condition (ARMul_State * state, uint32_t cond) { uint32_t ret; switch (cond) { case EQ: ret = ZFLAG; break; case NE: ret = !ZFLAG; break; case VS: ret = VFLAG; break; case VC: ret = !VFLAG; break; case MI: ret = NFLAG; break; case PL: ret = !NFLAG; break; case CS: ret = CFLAG; break; case CC: ret = !CFLAG; break; case HI: ret = (CFLAG && !ZFLAG); break; case LS: ret = (!CFLAG || ZFLAG); break; case GE: ret = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); break; case LT: ret = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); break; case GT: ret = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG)); break; case LE: ret = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG; break; default: ret = 0; break; } return (ret); } #endif //_ARM2X86_PSR_H_ ���������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_shift.c������������������������������������������������������0000644�0001750�0000144�00000034270�10541455476�017437� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" uint8_t * get_op_lsl_T1_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsl_T1_im"); T1 = T1 << 31; OP_END ("get_op_lsl_T1_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } uint8_t * get_op_lsr_T1_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsr_T1_im"); T1 = T1 >> 31; OP_END ("get_op_lsr_T1_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } uint8_t * get_op_asr_T1_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_asr_T1_im"); T1 = (int32_t) T1 >> 31; OP_END ("get_op_asr_T1_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } uint8_t * get_op_ror_T1_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ror_T1_im"); __asm__ __volatile__ ("rorl $31,%%" AREG_T1 "\n\t"::); OP_END ("get_op_ror_T1_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } int op_shift_T1_im_maxlen; op_table_t op_shift_T1_im[4]; int op_shift_T1_im_init () { int i; op_shift_T1_im[0].op = get_op_lsl_T1_im (&op_shift_T1_im[0].len); op_shift_T1_im[1].op = get_op_lsr_T1_im (&op_shift_T1_im[1].len); op_shift_T1_im[2].op = get_op_asr_T1_im (&op_shift_T1_im[2].len); op_shift_T1_im[3].op = get_op_ror_T1_im (&op_shift_T1_im[3].len); op_shift_T1_im_maxlen = 0; for (i = 0; i < 4; i++) { if (op_shift_T1_im[i].op == NULL) { return (-1); } if (op_shift_T1_im[i].len > op_shift_T1_im_maxlen) { op_shift_T1_im_maxlen = op_shift_T1_im[i].len; } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_lsl_T1_im_sc (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsl_T1_im_sc"); st->CFlag = (T1 >> (32 - 2)) & 1; OP_END ("get_op_lsl_T1_im_sc"); *len = end - begin; ret = (uint8_t *) begin; if (*len < 5) return (NULL); if (ret[4] != (32 - 2)) return (NULL); return (ret); } uint8_t * get_op_lsr_T1_im_sc (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; //teawater correct a little bug 2005.10.06-------------------------------------- OP_BEGIN("get_op_lsr_T1_im_sc"); st->CFlag = (T1 >> (31 - 1)) & 1; OP_END("get_op_lsr_T1_im_sc"); //AJ2D-------------------------------------------------------------------------- *len = end - begin; ret = (uint8_t *) begin; if (*len < 5) return (NULL); if (ret[4] != 30) return (NULL); return (ret); } int op_shift_T1_im_sc_maxlen; op_table_t op_shift_T1_im_sc[4]; int op_shift_T1_im_sc_init () { op_shift_T1_im_sc[0].op = get_op_lsl_T1_im_sc (&op_shift_T1_im_sc[0].len); if (op_shift_T1_im_sc[0].op == NULL) return (-1); op_shift_T1_im_sc[1].op = get_op_lsr_T1_im_sc (&op_shift_T1_im_sc[1].len); if (op_shift_T1_im_sc[1].op == NULL) return (-1); op_shift_T1_im_sc[2].op = op_shift_T1_im_sc[1].op; op_shift_T1_im_sc[2].len = op_shift_T1_im_sc[1].len; op_shift_T1_im_sc[3].op = op_shift_T1_im_sc[1].op; op_shift_T1_im_sc[3].len = op_shift_T1_im_sc[1].len; if (op_shift_T1_im_sc[0].len > op_shift_T1_im_sc[1].len) { op_shift_T1_im_sc_maxlen = op_shift_T1_im_sc[0].len; } else { op_shift_T1_im_sc_maxlen = op_shift_T1_im_sc[1].len; } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_lsr_T1_0 (int *len) { //arm_arm A 5.1.7 uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsr_T1_0"); T1 = 0; OP_END ("get_op_lsr_T1_0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_asr_T1_0 (int *len) { //arm_arm A 5.1.9 uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_asr_T1_0"); T1 = (int32_t) T1 >> 31; OP_END ("get_op_asr_T1_0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_rrx_T1_0 (int *len) { //arm_arm A 5.1.11 uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_rrx_T1_0"); T1 = (T1 >> 1) | (st->CFlag << 31); OP_END ("get_op_rrx_T1_0"); *len = end - begin; return ((uint8_t *) begin); } int op_shift_T1_0_maxlen; op_table_t op_shift_T1_0[4]; int op_shift_T1_0_init () { int i; op_shift_T1_0[0].op = NULL; op_shift_T1_0[0].len = 0; op_shift_T1_0[1].op = get_op_lsr_T1_0 (&op_shift_T1_0[1].len); op_shift_T1_0[2].op = get_op_asr_T1_0 (&op_shift_T1_0[2].len); op_shift_T1_0[3].op = get_op_rrx_T1_0 (&op_shift_T1_0[3].len); op_shift_T1_0_maxlen = 0; for (i = 1; i < 4; i++) { if (op_shift_T1_0[i].op == NULL) { return (-1); } if (op_shift_T1_0[i].len > op_shift_T1_0_maxlen) { op_shift_T1_0_maxlen = op_shift_T1_0[i].len; } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_lsr_T2_0_sc (int *len) { //arm_arm A 5.1.7 uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsr_T2_0_sc"); st->CFlag = T2 >> 31; OP_END ("get_op_lsr_T2_0_sc"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_asr_T2_0_sc (int *len) { //arm_arm A 5.1.9 uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_asr_T2_0_sc"); st->CFlag = T2 >> 31; OP_END ("get_op_asr_T2_0_sc"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_rrx_T2_0_sc (int *len) { //arm_arm A 5.1.11 uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_rrx_T2_0_sc"); st->CFlag = T2 & 1; OP_END ("get_op_rrx_T2_0_sc"); *len = end - begin; return ((uint8_t *) begin); } int op_shift_T2_0_sc_maxlen; op_table_t op_shift_T2_0_sc[4]; int op_shift_T2_0_sc_init () { int i; op_shift_T2_0_sc[0].op = NULL; op_shift_T2_0_sc[0].len = 0; op_shift_T2_0_sc[1].op = get_op_lsr_T2_0_sc (&op_shift_T2_0_sc[1].len); op_shift_T2_0_sc[2].op = get_op_asr_T2_0_sc (&op_shift_T2_0_sc[2].len); op_shift_T2_0_sc[3].op = get_op_rrx_T2_0_sc (&op_shift_T2_0_sc[3].len); op_shift_T2_0_sc_maxlen = 0; for (i = 1; i < 4; i++) { if (op_shift_T2_0_sc[i].op == NULL) { return (-1); } if (op_shift_T2_0_sc[i].len > op_shift_T2_0_sc_maxlen) { op_shift_T2_0_sc_maxlen = op_shift_T2_0_sc[i].len; } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_lsl_T1_T0 (int *len) { //arm_arm A 5.1.6 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsl_T1_T0"); T0 &= 0xff; if (T0) T1 = (T0 < 32) ? (T1 << T0) : 0; OP_END ("get_op_lsl_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_lsr_T1_T0 (int *len) { //arm_arm A 5.1.8 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsr_T1_T0"); T0 &= 0xff; if (T0) T1 = (T0 < 32) ? (T1 >> T0) : 0; OP_END ("get_op_lsr_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_asr_T1_T0 (int *len) { //arm_arm A 5.1.10 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_asr_T1_T0"); T0 &= 0xff; if (T0 >= 32) { T0 = 31; } if (T0) T1 = (int32_t) T1 >> T0; OP_END ("get_op_asr_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ror_T1_T0 (int *len) { //arm_arm A 5.1.12 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ror_T1_T0"); T0 &= 0xff; if (T0) { T0 &= 0x1f; if (T0) T1 = (T1 >> T0) | (T1 << (32 - T0)); } OP_END ("get_op_ror_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } int op_shift_T1_T0_maxlen; op_table_t op_shift_T1_T0[4]; int op_shift_T1_T0_init () { int i; op_shift_T1_T0[0].op = get_op_lsl_T1_T0 (&op_shift_T1_T0[0].len); op_shift_T1_T0[1].op = get_op_lsr_T1_T0 (&op_shift_T1_T0[1].len); op_shift_T1_T0[2].op = get_op_asr_T1_T0 (&op_shift_T1_T0[2].len); op_shift_T1_T0[3].op = get_op_ror_T1_T0 (&op_shift_T1_T0[3].len); op_shift_T1_T0_maxlen = 0; for (i = 0; i < 4; i++) { if (op_shift_T1_T0[i].op == NULL) { return (-1); } if (op_shift_T1_T0[i].len > op_shift_T1_T0_maxlen) { op_shift_T1_T0_maxlen = op_shift_T1_T0[i].len; } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_lsl_T1_T0_sc (int *len) { //arm_arm A 5.1.6 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsl_T1_T0_sc"); T0 &= 0xff; if (T0) { if (T0 < 32) { st->CFlag = (T1 >> (32 - T0)) & 1; T1 = T1 << T0; } else if (T0 == 32) { st->CFlag = T1 & 1; T1 = 0; } else { //T0 > 32 st->CFlag = 0; T1 = 0; } } OP_END ("get_op_lsl_T1_T0_sc"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_lsr_T1_T0_sc (int *len) { //arm_arm A 5.1.8 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsr_T1_T0_sc"); T0 &= 0xff; if (T0) { if (T0 < 32) { st->CFlag = (T1 >> (T0 - 1)) & 1; T1 = T1 >> T0; } else if (T0 == 32) { st->CFlag = T1 >> 31; T1 = 0; } else { //T0 > 32 st->CFlag = 0; T1 = 0; } } OP_END ("get_op_lsr_T1_T0_sc"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_asr_T1_T0_sc (int *len) { //arm_arm A 5.1.10 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_asr_T1_T0_sc"); T0 &= 0xff; if (T0) { if (T0 < 32) { st->CFlag = (T1 >> (T0 - 1)) & 1; } if (T0 >= 32) { st->CFlag = T1 >> 31; T0 = 31; } T1 = (int32_t) T1 >> T0; } OP_END ("get_op_asr_T1_T0_sc"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_ror_T1_T0_sc (int *len) { //arm_arm A 5.1.12 unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ror_T1_T0_sc"); T0 &= 0xff; if (T0) { T0 &= 0x1f; if (T0 == 0) { st->CFlag = T1 >> 31; } if (T0) { st->CFlag = (T1 >> (T0 - 1)) & 1; T1 = (T1 >> T0) | (T1 << (32 - T0)); } } OP_END ("get_op_ror_T1_T0_sc"); *len = end - begin; return ((uint8_t *) begin); } int op_shift_T1_T0_sc_maxlen; op_table_t op_shift_T1_T0_sc[4]; int op_shift_T1_T0_sc_init () { int i; op_shift_T1_T0_sc[0].op = get_op_lsl_T1_T0_sc (&op_shift_T1_T0_sc[0].len); op_shift_T1_T0_sc[1].op = get_op_lsr_T1_T0_sc (&op_shift_T1_T0_sc[1].len); op_shift_T1_T0_sc[2].op = get_op_asr_T1_T0_sc (&op_shift_T1_T0_sc[2].len); op_shift_T1_T0_sc[3].op = get_op_ror_T1_T0_sc (&op_shift_T1_T0_sc[3].len); op_shift_T1_T0_sc_maxlen = 0; for (i = 0; i < 4; i++) { if (op_shift_T1_T0[i].op == NULL) { return (-1); } if (op_shift_T1_T0_sc[i].len > op_shift_T1_T0_sc_maxlen) { op_shift_T1_T0_sc_maxlen = op_shift_T1_T0_sc[i].len; } } return (0); } //-------------------------------------------------------------------------------------------------- uint8_t * get_op_lsl_T2_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsl_T2_im"); T2 = T2 << 31; OP_END ("get_op_lsl_T2_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } uint8_t * get_op_lsr_T2_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lsr_T2_im"); T2 = T2 >> 31; OP_END ("get_op_lsr_T2_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } uint8_t * get_op_asr_T2_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_asr_T2_im"); T2 = (int32_t) T2 >> 31; OP_END ("get_op_asr_T2_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } uint8_t * get_op_ror_T2_im (int *len) { uint8_t *ret; unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_ror_T2_im"); __asm__ __volatile__ ("rorl $31,%%" AREG_T2 "\n\t"::); OP_END ("get_op_ror_T2_im"); *len = end - begin; if (*len <= sizeof (uint8_t)) { return (NULL); } else { *len -= sizeof (uint8_t); } ret = (uint8_t *) begin; if (ret[*len] != 31) return (NULL); return (ret); } int op_shift_T2_im_maxlen; op_table_t op_shift_T2_im[4]; int op_shift_T2_im_init () { int i; op_shift_T2_im[0].op = get_op_lsl_T2_im (&op_shift_T2_im[0].len); op_shift_T2_im[1].op = get_op_lsr_T2_im (&op_shift_T2_im[1].len); op_shift_T2_im[2].op = get_op_asr_T2_im (&op_shift_T2_im[2].len); op_shift_T2_im[3].op = get_op_ror_T2_im (&op_shift_T2_im[3].len); op_shift_T2_im_maxlen = 0; for (i = 0; i < 4; i++) { if (op_shift_T2_im[i].op == NULL) { return (-1); } if (op_shift_T2_im[i].len > op_shift_T2_im_maxlen) { op_shift_T2_im_maxlen = op_shift_T2_im[i].len; } } return (0); } //-------------------------------------------------------------------------------------------------- int arm2x86_shift_init () { if (op_shift_T1_im_init ()) { return (-1); } if (op_shift_T1_im_sc_init ()) { return (-1); } if (op_shift_T1_0_init ()) { return (-1); } if (op_shift_T2_0_sc_init ()) { return (-1); } if (op_shift_T1_T0_init ()) { return (-1); } if (op_shift_T1_T0_sc_init ()) { return (-1); } if (op_shift_T2_im_init ()) { return (-1); } return (0); } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/dbct/arm2x86_other.c������������������������������������������������������0000644�0001750�0000144�00000050601�10541455476�017437� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* * author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com> */ #include "armdefs.h" #include "arm2x86_self.h" uint8_t * get_op_addq_T0_T1_eax_T2 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_addq_T0_T1_eax_T2"); __asm__ __volatile__ ("addl %eax, %" AREG_T0); __asm__ __volatile__ ("adcl %" AREG_T2 ", %" AREG_T1); OP_END ("get_op_addq_T0_T1_eax_T2"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_b_offset (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_b_offset"); st->Reg[15] += INT32_MAX; OP_END ("get_op_b_offset"); *len = end - begin; if (*len <= sizeof (INT32_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } return ((uint8_t *) begin); } uint8_t * get_op_bl_offset (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_bl_offset"); //st->Reg[14] = st->Reg[15] + 4; st->Reg[14] = st->Reg[15]; wmb (); st->Reg[15] += INT32_MAX; OP_END ("get_op_bl_offset"); *len = end - begin; if (*len <= sizeof (INT32_MAX)) { return (NULL); } else { *len -= sizeof (ULONG_MAX); } return ((uint8_t *) begin); } //teawater add check thumb 2005.07.21------------------------------------------- uint8_t * get_op_bx_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_bx_T1"); if (T1 & 1) { //thumb XXX st->TFlag = 1; st->Reg[15] = (T1 & 0xfffffffe) + 2; st->trap = TRAP_UNPREDICTABLE; } else { //arm st->TFlag = 0; st->Reg[15] = (T1 & 0xfffffffc) + 4; } OP_END ("get_op_bx_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_blx_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_blx_T1"); if (T1 & 1) { //thumb XXX st->TFlag = 1; st->Reg[14] = st->Reg[15]; st->Reg[15] = (T1 & 0xfffffffe) + 2; st->trap = TRAP_UNPREDICTABLE; } else { //arm st->TFlag = 0; st->Reg[14] = st->Reg[15]; st->Reg[15] = (T1 & 0xfffffffc) + 4; } OP_END ("get_op_blx_T1"); *len = end - begin; return ((uint8_t *) begin); } //AJ2D-------------------------------------------------------------------------- //teawater add for xscale(arm v5) 2005.09.12------------------------------------ uint8_t * get_op_hi_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_hi_T0"); //T0 = (uint32_t)((int32_t)((int16_t)(T0 >> 16))); T0 = T0 >> 16; OP_END ("get_op_hi_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_hi_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_hi_T1"); //T1 = (uint32_t)((int32_t)((int16_t)(T1 >> 16))); T1 = T1 >> 16; OP_END ("get_op_hi_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_lo_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lo_T0"); //T0 = (uint32_t)((int32_t)((int16_t)(T0 & 0xffff))); T0 = T0 & 0xffff; OP_END ("get_op_lo_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_lo_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_lo_T1"); //T1 = (uint32_t)((int32_t)((int16_t)(T1 & 0xffff))); T1 = T1 & 0xffff; OP_END ("get_op_lo_T1"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_smlalxy_T2_T1_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_smlalxy_T2_T1_T0"); arm2x86_tmp64 = (uint64_t) T1; arm2x86_tmp64 = ((uint64_t) T2) << 32; arm2x86_tmp64 += (uint64_t) T0; T1 = (uint32_t) (arm2x86_tmp64 & 0xffffffff); T2 = (uint32_t) (arm2x86_tmp64 >> 32); OP_END ("get_op_smlalxy_T2_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_smlawy_T2_T1_T0 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_smlawy_T2_T1_T0"); arm2x86_tmp64 = (uint64_t) T0 *(uint64_t) T1; T0 = (uint32_t) ((arm2x86_tmp64 >> 16) & 0xffffffff); T1 = T0 + T2; QFLAG_reg = ~(T0 ^ T2); QFLAG_reg &= (T1 ^ T2); QFLAG_reg >>= 31; T0 = T1; OP_END ("get_op_smlawy_T2_T1_T0"); *len = end - begin; return ((uint8_t *) begin); } uint8_t * get_op_smulwy_T0_T1 (int *len) { unsigned int begin = 0, end = 0; OP_BEGIN ("get_op_smulwy_T0_T1"); arm2x86_tmp64 = (uint64_t) T0 *(uint64_t) T1; T0 = (uint32_t) ((arm2x86_tmp64 >> 16) & 0xffffffff); OP_END ("get_op_smulwy_T0_T1"); *len = end - begin; return ((uint8_t *) begin); } //AJ2D-------------------------------------------------------------------------- //teawater change for local tb branch directly jump 2005.10.17------------------ uint8_t * get_op_local_b_offset(int *len) { unsigned int begin=0,end=0; OP_BEGIN("get_op_local_b_offset"); __asm__ __volatile__ ("jmp 0xffffffff"); OP_END("get_op_local_b_offset"); *len = end - begin; if (*len <= sizeof(INT32_MAX)) { return(NULL); } return((uint8_t *)begin); } op_table_t op_local_b_offset; //AJ2D-------------------------------------------------------------------------- op_table_t op_addq_T0_T1_eax_T2; op_table_t op_b_offset; op_table_t op_bl_offset; //teawater add check thumb 2005.07.21------------------------------------------- op_table_t op_bx_T1; op_table_t op_blx_T1; //AJ2D-------------------------------------------------------------------------- //teawater add for xscale(arm v5) 2005.09.12------------------------------------ op_table_t op_hi_T0; op_table_t op_hi_T1; op_table_t op_lo_T0; op_table_t op_lo_T1; op_table_t op_smlalxy_T2_T1_T0; op_table_t op_smlawy_T2_T1_T0; op_table_t op_smulwy_T0_T1; //AJ2D-------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------------- void arm2x86_get_op_mul (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { ARMword rd, rn, rs, rm; rd = (insn >> 16) & 0xf; rn = (insn >> 12) & 0xf; rs = (insn >> 8) & 0xf; rm = (insn) & 0xf; if (!(insn & (1 << 23))) { //32 bit //mul gen_op_movl_Tx_reg (state, tbpp, plen, 0, rs); gen_op_movl_Tx_reg (state, tbpp, plen, 1, rm); GEN_OP (*tbpp, *plen, op_mul_T0_T1); if (insn & (1 << 21)) { //mla gen_op_movl_Tx_reg (state, tbpp, plen, 1, rn); GEN_OP (*tbpp, *plen, op_addl_T0_T1); } if (insn & (1 << 20)) { //set cpsr nf GEN_OP (*tbpp, *plen, op_logic_T0_sn); GEN_OP (*tbpp, *plen, op_set_nf); //set cpsr zf GEN_OP (*tbpp, *plen, op_logic_T0_sz); GEN_OP (*tbpp, *plen, op_set_zf); } gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0); if (rd == 15) { state->trap = 1; } } else { //64 bit gen_op_movl_Tx_reg (state, tbpp, plen, 0, rs); gen_op_movl_Tx_reg (state, tbpp, plen, 1, rm); if (insn & (1 << 22)) { //smull GEN_OP (*tbpp, *plen, op_smull_T0_T1); } else { //umull GEN_OP (*tbpp, *plen, op_umull_T0_T1); } if (insn & (1 << 21)) { //smlal if smull //umlal if umull gen_op_movl_Tx_reg (state, tbpp, plen, 2, rn); GEN_OP (*tbpp, *plen, op_movl_eax_T2); gen_op_movl_Tx_reg (state, tbpp, plen, 2, rd); GEN_OP (*tbpp, *plen, op_addq_T0_T1_eax_T2); } if (insn & (1 << 20)) { //set cpsr nf GEN_OP (*tbpp, *plen, op_logic_T0_sn); GEN_OP (*tbpp, *plen, op_set_nf); //set cpsr zf GEN_OP (*tbpp, *plen, op_logic_T0_sz); GEN_OP (*tbpp, *plen, op_set_zf); } gen_op_movl_reg_Tx (state, tbpp, plen, rn, 0); gen_op_movl_reg_Tx (state, tbpp, plen, rd, 1); if (rn == 15 || rd == 15) { state->trap = 1; } } } void arm2x86_get_op_swp (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { ARMword rd, rn, rm; rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; rm = (insn) & 0xf; gen_op_movl_Tx_reg (state, tbpp, plen, 0, rm); gen_op_movl_Tx_reg (state, tbpp, plen, 1, rn); if (insn & (1 << 22)) { //swpb //ldrb T2 from T1 GEN_OP (*tbpp, *plen, op_ldrb_T2_T1); //strb T0 to T1 GEN_OP (*tbpp, *plen, op_strb_T0_T1); } else { //swp //ldr T2 from T1 GEN_OP (*tbpp, *plen, op_ldr_T2_T1); //str T0 to T1 GEN_OP (*tbpp, *plen, op_str_T0_T1); } gen_op_movl_reg_Tx (state, tbpp, plen, rd, 2); } void arm2x86_get_op_insn_undef (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_INSN_UNDEF); state->trap = 1; } void arm2x86_get_op_ldrstr (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { ARMword rn = (insn >> 16) & 0xf; ARMword rd = (insn >> 12) & 0xf; gen_op_movl_Tx_reg (state, tbpp, plen, 1, rn); if (insn & (1 << 24)) { //P gen_op_add_data_offset (state, tbpp, plen, insn); } if (insn & (1 << 20)) { //L if (insn & (1 << 22)) { //B //ldrb GEN_OP (*tbpp, *plen, op_ldrb_T0_T1); } else { //ldr GEN_OP (*tbpp, *plen, op_ldr_T0_T1); } //if (!state->is_XScale) { if (state->abort_model > 1) { gen_op_test_dataabort_im (state, tbpp, plen, op_movl_reg_Tx[0][rd].len); } gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0); } else { gen_op_movl_Tx_reg (state, tbpp, plen, 0, rd); if (insn & (1 << 22)) { //B //strb GEN_OP (*tbpp, *plen, op_strb_T0_T1); } else { //str GEN_OP (*tbpp, *plen, op_str_T0_T1); } } if (!(insn & (1 << 24))) { //!P gen_op_add_data_offset (state, tbpp, plen, insn); gen_op_movl_reg_Tx (state, tbpp, plen, rn, 1); } else if (insn & (1 << 21)) { //P & W gen_op_movl_reg_Tx (state, tbpp, plen, rn, 1); } //if (!state->is_XScale) { if (state->abort_model > 1) { GEN_OP (*tbpp, *plen, op_test_dataabort_ret); } } void arm2x86_get_op_ldmstm (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { int i, n; ARMword rn = (insn >> 16) & 0xf; if (rn == 15) { gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_UNPREDICTABLE); state->trap = 1; return; } if (insn & (1 << 22)) { //S ("^") if (!(insn & (1 << 15)) && (insn & (1 << 21))) { gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_UNPREDICTABLE); state->trap = 1; return; } GEN_OP (*tbpp, *plen, op_test_cpsr_ret_UNP); } gen_op_movl_Tx_reg (state, tbpp, plen, 1, rn); n = 0; for (i = 0; i < 16; i++) { if (insn & (1 << i)) { if (i == 15 && (insn & (1 << 20))) { //have pc & L state->trap = 1; if (insn & (1 << 22)) { //S gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_SETS_R15); } } n++; } } if (n == 0) { //compute total size ("If bits[15:0] are all zero, the result is UNPREDICTABLE" arm_arm) gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_UNPREDICTABLE); state->trap = 1; return; } if (insn & (1 << 23)) { //U //i increment if (insn & (1 << 24)) { //P //b before gen_op_addl_T1_im (state, tbpp, plen, 4); } else { //a after } } else { //d decrement if (insn & (1 << 24)) { //P //b before gen_op_addl_T1_im (state, tbpp, plen, (-(n * 4))); } else { //a after if (n != 1) { gen_op_addl_T1_im (state, tbpp, plen, (-((n - 1) * 4))); } } } gen_op_movl_Tx_im (state, tbpp, plen, 0, insn & 0xffff); if (insn & (1 << 20)) { //L //ldm if (insn & (1 << 22) && !state->trap) { //S ("^") & don't have pc GEN_OP (*tbpp, *plen, op_ldm_user_T1_T0); } else { GEN_OP (*tbpp, *plen, op_ldm_T1_T0); } } else { //stm if (insn & (1 << 22)) { //S ("^") GEN_OP (*tbpp, *plen, op_stm_user_T1_T0); } else { GEN_OP (*tbpp, *plen, op_stm_T1_T0); } } if (insn & (1 << 21)) { //W //write back //if (!state->is_XScale) { if (state->abort_model > 1) { gen_op_test_dataabort_im (state, tbpp, plen, op_addl_T1_im.len + sizeof (ARMword) + op_movl_reg_Tx[0][rn].len); } if (insn & (1 << 23)) { //U //i increment if (insn & (1 << 24)) { //P //b before } else { //a after gen_op_addl_T1_im (state, tbpp, plen, 4); } } else { //d decrement if (insn & (1 << 24)) { //P //b before if (n != 1) { gen_op_addl_T1_im (state, tbpp, plen, (-((n - 1) * 4))); } } else { //a after gen_op_addl_T1_im (state, tbpp, plen, (-(n * 4))); } } gen_op_movl_reg_Tx (state, tbpp, plen, rn, 1); } //if (!state->is_XScale) { if (state->abort_model > 1) { GEN_OP (*tbpp, *plen, op_test_dataabort_ret); } } void arm2x86_get_op_bbl (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { int offset = ((((int) insn << 8) >> 8) << 2) + 4; if (insn & (1 << 24)) { //bl gen_op_bl_offset (state, tbpp, plen, (ARMword) offset); } else { //b gen_op_b_offset (state, tbpp, plen, (ARMword) offset); } //teawater change for local tb branch directly jump 2005.10.18------------------ if (now_tbt->addr == TB_ALIGN(now_tbt->tran_addr + offset + sizeof(ARMword))) { int tmp_i = (now_tbt->tran_addr - now_tbt->addr) / sizeof(ARMword); GEN_OP(*tbpp, *plen, op_local_b_offset); tb_branch_save[tmp_i].dst_addr = now_tbt->tran_addr + offset + sizeof(ARMword); tb_branch_save[tmp_i].tbp = *tbpp; list_add_tail(&tb_branch_save[tmp_i].list, &tb_branch_save_list); if (now_tbt->ret_addr < tb_branch_save[tmp_i].dst_addr) { now_tbt->ret_addr = tb_branch_save[tmp_i].dst_addr; } } //AJ2D-------------------------------------------------------------------------- } void arm2x86_get_op_ldcstc (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { ARMword rn = (insn >> 16) & 0xf; //ARMword crd = (insn >> 12) & 0xf; //ARMword cp = (insn >> 8) & 0xf; //teawater add for xscale(arm v5) 2005.09.06------------------------------------ if (state->is_XScale && ((insn >> 8) & 0xf) == 0) { uint32_t tmp_32 = (insn >> 20) & 0xff; if (tmp_32 == 0xc4) { //mar gen_op_movl_Tx_reg (state, tbpp, plen, 0, ((insn >> 12) & 0xf)); //rdlo gen_op_movl_Tx_reg (state, tbpp, plen, 1, ((insn >> 16) & 0xf)); //rdhi GEN_OP (*tbpp, *plen, op_mar_T0_T1); return; } else if (tmp_32 == 0xc5) { //mra GEN_OP (*tbpp, *plen, op_mra_T0_T1); gen_op_movl_reg_Tx (state, tbpp, plen, ((insn >> 12) & 0xf), 0); //rdlo gen_op_movl_reg_Tx (state, tbpp, plen, ((insn >> 16) & 0xf), 1); //rdhi return; } } //AJ2D-------------------------------------------------------------------------- //XXX teawater:howto deal with N gen_op_movl_Tx_reg (state, tbpp, plen, 1, rn); if (insn & (1 << 24)) //P gen_op_add_imm_offset (state, tbpp, plen, insn); gen_op_movl_Tx_im (state, tbpp, plen, 0, insn); if (insn & (1 << 20)) { //L //ldc GEN_OP (*tbpp, *plen, op_ldc_T0_T1); } else { //stc GEN_OP (*tbpp, *plen, op_stc_T0_T1); } if (!(insn & (1 << 24))) { //!P gen_op_add_imm_offset (state, tbpp, plen, insn); gen_op_movl_reg_Tx (state, tbpp, plen, rn, 1); } else if (insn & (1 << 21)) { //P & W gen_op_movl_reg_Tx (state, tbpp, plen, rn, 1); } } void arm2x86_get_op_cdp_mrcmcr (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { gen_op_movl_Tx_im (state, tbpp, plen, 0, insn); //put cp_num to T1 gen_op_movl_Tx_im (state, tbpp, plen, 1, (insn >> 8) & 0xf); if (insn & (1 << 4)) { if (insn & (1 << 20)) { //L //mrc GEN_OP (*tbpp, *plen, op_mrc_T0_T1); } else { //teawater add for xscale(arm v5) 2005.09.06------------------------------------ if (state->is_XScale && ((insn >> 8) & 0xf) == 0) { switch ((insn >> 16) & 0xf) { case 0x0: //mia gen_op_movl_Tx_reg (state, tbpp, plen, 0, (insn & 0xf)); //rm gen_op_movl_Tx_reg (state, tbpp, plen, 1, ((insn >> 12) & 0xf)); //rs GEN_OP (*tbpp, *plen, op_smull_T0_T1); GEN_OP (*tbpp, *plen, op_mia_T0_T1); return; break; case 0x8: //miaph gen_op_movl_Tx_reg (state, tbpp, plen, 0, (insn & 0xf)); //rm gen_op_movl_Tx_reg (state, tbpp, plen, 1, ((insn >> 12) & 0xf)); //rs GEN_OP (*tbpp, *plen, op_miaph_T0_T1); return; break; case 0xc: //miabb 1100 gen_op_movl_Tx_reg (state, tbpp, plen, 0, (insn & 0xf)); //rm gen_op_movl_Tx_reg (state, tbpp, plen, 1, ((insn >> 12) & 0xf)); //rs GEN_OP (*tbpp, *plen, op_lo_T0); GEN_OP (*tbpp, *plen, op_lo_T1); GEN_OP (*tbpp, *plen, op_signextend_halfword_T0); GEN_OP (*tbpp, *plen, op_signextend_halfword_T1); GEN_OP (*tbpp, *plen, op_miaxy_T0_T1); return; break; case 0xd: //miabt 1101 gen_op_movl_Tx_reg (state, tbpp, plen, 0, (insn & 0xf)); //rm gen_op_movl_Tx_reg (state, tbpp, plen, 1, ((insn >> 12) & 0xf)); //rs GEN_OP (*tbpp, *plen, op_lo_T0); GEN_OP (*tbpp, *plen, op_hi_T1); GEN_OP (*tbpp, *plen, op_signextend_halfword_T0); GEN_OP (*tbpp, *plen, op_signextend_halfword_T1); GEN_OP (*tbpp, *plen, op_miaxy_T0_T1); return; break; case 0xe: //miatb 1110 gen_op_movl_Tx_reg (state, tbpp, plen, 0, (insn & 0xf)); //rm gen_op_movl_Tx_reg (state, tbpp, plen, 1, ((insn >> 12) & 0xf)); //rs GEN_OP (*tbpp, *plen, op_hi_T0); GEN_OP (*tbpp, *plen, op_lo_T1); GEN_OP (*tbpp, *plen, op_signextend_halfword_T0); GEN_OP (*tbpp, *plen, op_signextend_halfword_T1); GEN_OP (*tbpp, *plen, op_miaxy_T0_T1); return; break; case 0xf: //miatt 1111 gen_op_movl_Tx_reg (state, tbpp, plen, 0, (insn & 0xf)); //rm gen_op_movl_Tx_reg (state, tbpp, plen, 1, ((insn >> 12) & 0xf)); //rs GEN_OP (*tbpp, *plen, op_hi_T0); GEN_OP (*tbpp, *plen, op_hi_T1); GEN_OP (*tbpp, *plen, op_signextend_halfword_T0); GEN_OP (*tbpp, *plen, op_signextend_halfword_T1); GEN_OP (*tbpp, *plen, op_miaxy_T0_T1); return; break; } } //AJ2D-------------------------------------------------------------------------- //mcr GEN_OP (*tbpp, *plen, op_mcr_T0_T1); } } else { //cdp GEN_OP (*tbpp, *plen, op_cdp_T0_T1); } } void arm2x86_get_op_swi (ARMul_State * state, ARMword insn, uint8_t ** tbpp, int *plen) { gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_SWI); state->trap = 1; } arm2x86_get_other_op_t *arm2x86_get_other_op[16] = { arm2x86_get_op_mul, arm2x86_get_op_swp, arm2x86_get_op_insn_undef, arm2x86_get_op_insn_undef, arm2x86_get_op_ldrstr, arm2x86_get_op_ldrstr, arm2x86_get_op_ldrstr, arm2x86_get_op_ldrstr, arm2x86_get_op_ldmstm, arm2x86_get_op_ldmstm, arm2x86_get_op_bbl, arm2x86_get_op_bbl, arm2x86_get_op_ldcstc, arm2x86_get_op_ldcstc, arm2x86_get_op_cdp_mrcmcr, arm2x86_get_op_swi, }; //-------------------------------------------------------------------------------------------------- int arm2x86_other_init () { op_addq_T0_T1_eax_T2.op = get_op_addq_T0_T1_eax_T2 (&op_addq_T0_T1_eax_T2.len); if (op_addq_T0_T1_eax_T2.len <= 0) return (-1); op_b_offset.op = get_op_b_offset (&op_b_offset.len); if (op_b_offset.len <= 0) return (-1); op_bl_offset.op = get_op_bl_offset (&op_bl_offset.len); if (op_bl_offset.len <= 0) return (-1); //teawater add check thumb 2005.07.21------------------------------------------- op_bx_T1.op = get_op_bx_T1 (&op_bx_T1.len); if (op_bx_T1.len <= 0) return (-1); op_blx_T1.op = get_op_blx_T1 (&op_blx_T1.len); if (op_blx_T1.len <= 0) return (-1); //AJ2D-------------------------------------------------------------------------- //teawater add for xscale(arm v5) 2005.09.12------------------------------------ op_hi_T0.op = get_op_hi_T0 (&op_hi_T0.len); if (op_hi_T0.len <= 0) return (-1); op_hi_T1.op = get_op_hi_T1 (&op_hi_T1.len); if (op_hi_T1.len <= 0) return (-1); op_lo_T0.op = get_op_lo_T0 (&op_lo_T0.len); if (op_lo_T0.len <= 0) return (-1); op_smlalxy_T2_T1_T0.op = get_op_smlalxy_T2_T1_T0 (&op_smlalxy_T2_T1_T0.len); if (op_smlalxy_T2_T1_T0.len <= 0) return (-1); op_smlawy_T2_T1_T0.op = get_op_smlawy_T2_T1_T0 (&op_smlawy_T2_T1_T0.len); if (op_smlawy_T2_T1_T0.len <= 0) return (-1); op_smulwy_T0_T1.op = get_op_smulwy_T0_T1 (&op_smulwy_T0_T1.len); if (op_smulwy_T0_T1.len <= 0) return (-1); //AJ2D-------------------------------------------------------------------------- //teawater change for local tb branch directly jump 2005.10.17------------------ op_local_b_offset.op = get_op_local_b_offset(&op_local_b_offset.len); if (op_local_b_offset.len <= 0) return(-1); //AJ2D-------------------------------------------------------------------------- return (0); } �������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/Makefile.am���������������������������������������������������������������0000644�0001750�0000144�00000003340�11006631442�015763� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������arm_comm = common/arm_arch_interface.c common/armcopro.c common/armemu.c common/arminit.c common/armio.c common/armmem.c common/armmmu.c common/armos.c common/armsupp.c common/armvirt.c common/thumbemu.c arm_mmu = common/mmu/arm7100_mmu.c common/mmu/arm920t_mmu.c common/mmu/arm926ejs_mmu.c common/mmu/cache.c common/mmu/maverick.c common/mmu/rb.c common/mmu/sa_mmu.c common/mmu/tlb.c common/mmu/wb.c common/mmu/xscale_copro.c arm_dbct = dbct/arm2x86.c dbct/arm2x86_coproc.c dbct/arm2x86_dp.c dbct/arm2x86_mem.c dbct/arm2x86_movl.c dbct/arm2x86_mul.c dbct/arm2x86_other.c dbct/arm2x86_psr.c dbct/arm2x86_shift.c dbct/arm2x86_test.c dbct/tb.c arm_mach = mach/skyeye_mach_ep9312.c mach/skyeye_mach_s3c2440.c\ mach/skyeye_mach_at91.c mach/skyeye_mach_ns9750.c mach/skyeye_mach_s3c3410x.c \ mach/skyeye_mach_ps7500.c mach/skyeye_mach_s3c44b0x.c \ mach/skyeye_mach_at91rm92.c mach/skyeye_mach_lh79520.c mach/skyeye_mach_pxa250.c mach/skyeye_mach_s3c4510b.c \ mach/skyeye_mach_cs89712.c mach/skyeye_mach_lpc2210.c mach/skyeye_mach_pxa270.c mach/skyeye_mach_sa.c \ mach/skyeye_mach_ep7312.c mach/skyeye_mach_lpc.c mach/skyeye_mach_s3c2410x.c mach/skyeye_mach_sharp.c libarm_a_SOURCES = $(arm_comm) $(arm_mmu) $(arm_mach) if DBCT libarm_a_SOURCES += $(arm_dbct) endif noinst_LIBRARIES = libarm.a DEFS = -DMODET -g -O2 -D_FILE_OFFSET_BITS=64 -DSTANDALONE -DDEFAULT_INLINE=0 libarm_a_LIBADD = armemu32.o INCLUDES = -I$(top_srcdir)/utils/share -I$(top_srcdir)/utils/debugger -I$(top_srcdir)/utils/profile/ -Icommon/ -Imach -I$(top_srcdir)/utils/debugger -I$(top_srcdir)/device/uart -I$(top_srcdir)/device/flash @COMMON_INCLUDES@ armemu32.o:common/armemu.c $(CC) -DMODE32 $(DEFS) $(INCLUDES) common/armemu.c -c -o $@ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/�������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�015212� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armmmu.c�����������������������������������������������������������0000644�0001750�0000144�00000010340�10541455476�016675� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armmmu.c - Memory Management Unit emulation. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <assert.h> #include <string.h> #include "armdefs.h" extern mmu_ops_t xscale_mmu_ops; #define MMU_OPS (state->mmu.ops) static mmu_inited = 0; ARMword skyeye_cachetype = -1; int mmu_init (ARMul_State * state) { int ret; state->mmu.control = 0x70; state->mmu.translation_table_base = 0xDEADC0DE; state->mmu.domain_access_control = 0xDEADC0DE; state->mmu.fault_status = 0; state->mmu.fault_address = 0; state->mmu.process_id = 0; switch (state->cpu->cpu_val & state->cpu->cpu_mask) { case SA1100: case SA1110: fprintf (stderr, "SKYEYE: use sa11xx mmu ops\n"); state->mmu.ops = sa_mmu_ops; break; case PXA250: case PXA270: //xscale fprintf (stderr, "SKYEYE: use xscale mmu ops\n"); state->mmu.ops = xscale_mmu_ops; break; case 0x41807200: //arm720t case 0x41007700: //arm7tdmi case 0x41007100: //arm7100 fprintf (stderr, "SKYEYE: use arm7100 mmu ops\n"); state->mmu.ops = arm7100_mmu_ops; break; case 0x41009200: fprintf (stderr, "SKYEYE: use arm920t mmu ops\n"); state->mmu.ops = arm920t_mmu_ops; break; case 0x41069260: fprintf (stderr, "SKYEYE: use arm926ejs mmu ops\n"); state->mmu.ops = arm926ejs_mmu_ops; break; default: fprintf (stderr, "SKYEYE: armmmu.c : mmu_init: unknown cpu_val&cpu_mask 0x%x\n", state->cpu->cpu_val & state->cpu->cpu_mask); skyeye_exit (-1); break; }; ret = state->mmu.ops.init (state); mmu_inited = (ret == 0); return ret; } int mmu_reset (ARMul_State * state) { if (mmu_inited) mmu_exit (state); return mmu_init (state); } void mmu_exit (ARMul_State * state) { MMU_OPS.exit (state); mmu_inited = 0; } fault_t mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data) { return MMU_OPS.read_byte (state, virt_addr, data); }; fault_t mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data) { return MMU_OPS.read_halfword (state, virt_addr, data); }; fault_t mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data) { return MMU_OPS.read_word (state, virt_addr, data); }; fault_t mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data) { fault_t fault; //static int count = 0; //count ++; fault = MMU_OPS.write_byte (state, virt_addr, data); return fault; } fault_t mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data) { fault_t fault; //static int count = 0; //count ++; fault = MMU_OPS.write_halfword (state, virt_addr, data); return fault; } fault_t mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data) { fault_t fault; static int count = 0; count++; fault = MMU_OPS.write_word (state, virt_addr, data); /*used for debug for MMU* if (!fault){ ARMword tmp; if (mmu_read_word(state, virt_addr, &tmp)){ err_msg("load back\n"); exit(-1); }else{ if (tmp != data){ err_msg("load back not equal %d %x\n", count, virt_addr); } } } */ return fault; }; fault_t mmu_load_instr (ARMul_State * state, ARMword virt_addr, ARMword * instr) { return MMU_OPS.load_instr (state, virt_addr, instr); } ARMword mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value) { return MMU_OPS.mrc (state, instr, value); } void mmu_mcr (ARMul_State * state, ARMword instr, ARMword value) { MMU_OPS.mcr (state, instr, value); } /*ywc 20050416*/ int mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr) { return (MMU_OPS.v2p_dbct (state, virt_addr, phys_addr)); } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/thumbemu.c���������������������������������������������������������0000644�0001750�0000144�00000034205�10541455476�017233� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* thumbemu.c -- Thumb instruction emulation. Copyright (C) 1996, Cygnus Software Technologies Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* We can provide simple Thumb simulation by decoding the Thumb instruction into its corresponding ARM instruction, and using the existing ARM simulator. */ #ifndef MODET /* required for the Thumb instruction support */ #if 1 #error "MODET needs to be defined for the Thumb world to work" #else #define MODET (1) #endif #endif #include "armdefs.h" #include "armemu.h" #include "armos.h" /* Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field, with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions allows easier simulation of the special dual BL instruction. */ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr) ARMul_State *state; ARMword pc; ARMword tinstr; ARMword *ainstr; { tdstate valid = t_decoded; /* default assumes a valid instruction */ ARMword next_instr; if (state->bigendSig) { next_instr = tinstr & 0xFFFF; tinstr >>= 16; } else { next_instr = tinstr >> 16; tinstr &= 0xFFFF; } #if 1 /* debugging to catch non updates */ *ainstr = 0xDEADC0DE; #endif switch ((tinstr & 0xF800) >> 11) { case 0: /* LSL */ case 1: /* LSR */ case 2: /* ASR */ /* Format 1 */ *ainstr = 0xE1B00000 /* base opcode */ | ((tinstr & 0x1800) >> (11 - 5)) /* shift type */ |((tinstr & 0x07C0) << (7 - 6)) /* imm5 */ |((tinstr & 0x0038) >> 3) /* Rs */ |((tinstr & 0x0007) << 12); /* Rd */ break; case 3: /* ADD/SUB */ /* Format 2 */ { ARMword subset[4] = { 0xE0900000, /* ADDS Rd,Rs,Rn */ 0xE0500000, /* SUBS Rd,Rs,Rn */ 0xE2900000, /* ADDS Rd,Rs,#imm3 */ 0xE2500000 /* SUBS Rd,Rs,#imm3 */ }; /* It is quicker indexing into a table, than performing switch or conditionals: */ *ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */ |((tinstr & 0x01C0) >> 6) /* Rn or imm3 */ |((tinstr & 0x0038) << (16 - 3)) /* Rs */ |((tinstr & 0x0007) << (12 - 0)); /* Rd */ } break; case 4: /* MOV */ case 5: /* CMP */ case 6: /* ADD */ case 7: /* SUB */ /* Format 3 */ { ARMword subset[4] = { 0xE3B00000, /* MOVS Rd,#imm8 */ 0xE3500000, /* CMP Rd,#imm8 */ 0xE2900000, /* ADDS Rd,Rd,#imm8 */ 0xE2500000, /* SUBS Rd,Rd,#imm8 */ }; *ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */ |((tinstr & 0x00FF) >> 0) /* imm8 */ |((tinstr & 0x0700) << (16 - 8)) /* Rn */ |((tinstr & 0x0700) << (12 - 8)); /* Rd */ } break; case 8: /* Arithmetic and high register transfers */ /* TODO: Since the subsets for both Format 4 and Format 5 instructions are made up of different ARM encodings, we could save the following conditional, and just have one large subset. */ if ((tinstr & (1 << 10)) == 0) { /* Format 4 */ struct { ARMword opcode; enum { t_norm, t_shift, t_neg, t_mul } otype; } subset[16] = { { 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */ { 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */ { 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */ { 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */ { 0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */ { 0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */ { 0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */ { 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */ { 0xE1100000, t_norm}, /* TST Rd,Rs */ { 0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */ { 0xE1500000, t_norm}, /* CMP Rd,Rs */ { 0xE1700000, t_norm}, /* CMN Rd,Rs */ { 0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */ { 0xE0100090, t_mul}, /* MULS Rd,Rd,Rs */ { 0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */ { 0xE1F00000, t_norm} /* MVNS Rd,Rs */ }; *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */ switch (subset[(tinstr & 0x03C0) >> 6].otype) { case t_norm: *ainstr |= ((tinstr & 0x0007) << 16) /* Rn */ |((tinstr & 0x0007) << 12) /* Rd */ |((tinstr & 0x0038) >> 3); /* Rs */ break; case t_shift: *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ |((tinstr & 0x0007) >> 0) /* Rm */ |((tinstr & 0x0038) << (8 - 3)); /* Rs */ break; case t_neg: *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ |((tinstr & 0x0038) << (16 - 3)); /* Rn */ break; case t_mul: *ainstr |= ((tinstr & 0x0007) << 16) /* Rd */ |((tinstr & 0x0007) << 8) /* Rs */ |((tinstr & 0x0038) >> 3); /* Rm */ break; } } else { /* Format 5 */ ARMword Rd = ((tinstr & 0x0007) >> 0); ARMword Rs = ((tinstr & 0x0038) >> 3); if (tinstr & (1 << 7)) Rd += 8; if (tinstr & (1 << 6)) Rs += 8; switch ((tinstr & 0x03C0) >> 6) { case 0x1: /* ADD Rd,Rd,Hs */ case 0x2: /* ADD Hd,Hd,Rs */ case 0x3: /* ADD Hd,Hd,Hs */ *ainstr = 0xE0800000 /* base */ | (Rd << 16) /* Rn */ |(Rd << 12) /* Rd */ |(Rs << 0); /* Rm */ break; case 0x5: /* CMP Rd,Hs */ case 0x6: /* CMP Hd,Rs */ case 0x7: /* CMP Hd,Hs */ *ainstr = 0xE1500000 /* base */ | (Rd << 16) /* Rn */ |(Rd << 12) /* Rd */ |(Rs << 0); /* Rm */ break; case 0x9: /* MOV Rd,Hs */ case 0xA: /* MOV Hd,Rs */ case 0xB: /* MOV Hd,Hs */ *ainstr = 0xE1A00000 /* base */ | (Rd << 16) /* Rn */ |(Rd << 12) /* Rd */ |(Rs << 0); /* Rm */ break; case 0xC: /* BX Rs */ case 0xD: /* BX Hs */ *ainstr = 0xE12FFF10 /* base */ | ((tinstr & 0x0078) >> 3); /* Rd */ break; case 0x0: /* UNDEFINED */ case 0x4: /* UNDEFINED */ case 0x8: /* UNDEFINED */ valid = t_undefined; break; case 0xE: /* BLX */ case 0xF: /* BLX */ if (state->is_v5) { *ainstr = 0xE1200030 /* base */ |(Rs << 0); /* Rm */ } else { valid = t_undefined; } break; } } break; case 9: /* LDR Rd,[PC,#imm8] */ /* Format 6 */ *ainstr = 0xE59F0000 /* base */ | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ |((tinstr & 0x00FF) << (2 - 0)); /* off8 */ break; case 10: case 11: /* TODO: Format 7 and Format 8 perform the same ARM encoding, so the following could be merged into a single subset, saving on the following boolean: */ if ((tinstr & (1 << 9)) == 0) { /* Format 7 */ ARMword subset[4] = { 0xE7800000, /* STR Rd,[Rb,Ro] */ 0xE7C00000, /* STRB Rd,[Rb,Ro] */ 0xE7900000, /* LDR Rd,[Rb,Ro] */ 0xE7D00000 /* LDRB Rd,[Rb,Ro] */ }; *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ |((tinstr & 0x0007) << (12 - 0)) /* Rd */ |((tinstr & 0x0038) << (16 - 3)) /* Rb */ |((tinstr & 0x01C0) >> 6); /* Ro */ } else { /* Format 8 */ ARMword subset[4] = { 0xE18000B0, /* STRH Rd,[Rb,Ro] */ 0xE19000D0, /* LDRSB Rd,[Rb,Ro] */ 0xE19000B0, /* LDRH Rd,[Rb,Ro] */ 0xE19000F0 /* LDRSH Rd,[Rb,Ro] */ }; *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ |((tinstr & 0x0007) << (12 - 0)) /* Rd */ |((tinstr & 0x0038) << (16 - 3)) /* Rb */ |((tinstr & 0x01C0) >> 6); /* Ro */ } break; case 12: /* STR Rd,[Rb,#imm5] */ case 13: /* LDR Rd,[Rb,#imm5] */ case 14: /* STRB Rd,[Rb,#imm5] */ case 15: /* LDRB Rd,[Rb,#imm5] */ /* Format 9 */ { ARMword subset[4] = { 0xE5800000, /* STR Rd,[Rb,#imm5] */ 0xE5900000, /* LDR Rd,[Rb,#imm5] */ 0xE5C00000, /* STRB Rd,[Rb,#imm5] */ 0xE5D00000 /* LDRB Rd,[Rb,#imm5] */ }; /* The offset range defends on whether we are transferring a byte or word value: */ *ainstr = subset[(tinstr & 0x1800) >> 11] /* base */ |((tinstr & 0x0007) << (12 - 0)) /* Rd */ |((tinstr & 0x0038) << (16 - 3)) /* Rb */ |((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */ } break; case 16: /* STRH Rd,[Rb,#imm5] */ case 17: /* LDRH Rd,[Rb,#imm5] */ /* Format 10 */ *ainstr = ((tinstr & (1 << 11)) /* base */ ? 0xE1D000B0 /* LDRH */ : 0xE1C000B0) /* STRH */ |((tinstr & 0x0007) << (12 - 0)) /* Rd */ |((tinstr & 0x0038) << (16 - 3)) /* Rb */ |((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */ |((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */ break; case 18: /* STR Rd,[SP,#imm8] */ case 19: /* LDR Rd,[SP,#imm8] */ /* Format 11 */ *ainstr = ((tinstr & (1 << 11)) /* base */ ? 0xE59D0000 /* LDR */ : 0xE58D0000) /* STR */ |((tinstr & 0x0700) << (12 - 8)) /* Rd */ |((tinstr & 0x00FF) << 2); /* off8 */ break; case 20: /* ADD Rd,PC,#imm8 */ case 21: /* ADD Rd,SP,#imm8 */ /* Format 12 */ if ((tinstr & (1 << 11)) == 0) { /* NOTE: The PC value used here should by word aligned */ /* We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is needed. */ *ainstr = 0xE28F0F00 /* base */ | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ |(tinstr & 0x00FF); /* off8 */ } else { /* We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is needed. */ *ainstr = 0xE28D0F00 /* base */ | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ |(tinstr & 0x00FF); /* off8 */ } break; case 22: case 23: if ((tinstr & 0x0F00) == 0x0000) { /* Format 13 */ /* NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30): */ *ainstr = ((tinstr & (1 << 7)) /* base */ ? 0xE24DDF00 /* SUB */ : 0xE28DDF00) /* ADD */ |(tinstr & 0x007F); /* off7 */ } else if ((tinstr & 0x0F00) == 0x0e00) *ainstr = 0xEF000000 | SWI_Breakpoint; else { /* Format 14 */ ARMword subset[4] = { 0xE92D0000, /* STMDB sp!,{rlist} */ 0xE92D4000, /* STMDB sp!,{rlist,lr} */ 0xE8BD0000, /* LDMIA sp!,{rlist} */ 0xE8BD8000 /* LDMIA sp!,{rlist,pc} */ }; *ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */ |(tinstr & 0x00FF); /* mask8 */ } break; case 24: /* STMIA */ case 25: /* LDMIA */ /* Format 15 */ *ainstr = ((tinstr & (1 << 11)) /* base */ ? 0xE8B00000 /* LDMIA */ : 0xE8A00000) /* STMIA */ |((tinstr & 0x0700) << (16 - 8)) /* Rb */ |(tinstr & 0x00FF); /* mask8 */ break; case 26: /* Bcc */ case 27: /* Bcc/SWI */ if ((tinstr & 0x0F00) == 0x0F00) { if (tinstr == (ARMul_ABORTWORD & 0xffff) && state->AbortAddr == pc) { *ainstr = ARMul_ABORTWORD; break; } /* Format 17 : SWI */ *ainstr = 0xEF000000; /* Breakpoint must be handled specially. */ if ((tinstr & 0x00FF) == 0x18) *ainstr |= ((tinstr & 0x00FF) << 16); /* New breakpoint value. See gdb/arm-tdep.c */ else if ((tinstr & 0x00FF) == 0xFE) *ainstr |= SWI_Breakpoint; else *ainstr |= (tinstr & 0x00FF); } else if ((tinstr & 0x0F00) != 0x0E00) { /* Format 16 */ int doit = FALSE; /* TODO: Since we are doing a switch here, we could just add the SWI and undefined instruction checks into this switch to same on a couple of conditionals: */ switch ((tinstr & 0x0F00) >> 8) { case EQ: doit = ZFLAG; break; case NE: doit = !ZFLAG; break; case VS: doit = VFLAG; break; case VC: doit = !VFLAG; break; case MI: doit = NFLAG; break; case PL: doit = !NFLAG; break; case CS: doit = CFLAG; break; case CC: doit = !CFLAG; break; case HI: doit = (CFLAG && !ZFLAG); break; case LS: doit = (!CFLAG || ZFLAG); break; case GE: doit = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); break; case LT: doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); break; case GT: doit = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG)); break; case LE: doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG; break; } if (doit) { state->Reg[15] = (pc + 4 + (((tinstr & 0x7F) << 1) | ((tinstr & (1 << 7)) ? 0xFFFFFF00 : 0))); FLUSHPIPE; } valid = t_branch; } else /* UNDEFINED : cc=1110(AL) uses different format */ valid = t_undefined; break; case 28: /* B */ /* Format 18 */ state->Reg[15] = (pc + 4 + (((tinstr & 0x3FF) << 1) | ((tinstr & (1 << 10)) ? 0xFFFFF800 : 0))); FLUSHPIPE; valid = t_branch; break; case 29: /* UNDEFINED */ valid = t_undefined; break; case 30: /* BL instruction 1 */ /* Format 19 */ /* There is no single ARM instruction equivalent for this Thumb instruction. To keep the simulation simple (from the user perspective) we check if the following instruction is the second half of this BL, and if it is we simulate it immediately. */ state->Reg[14] = state->Reg[15] + (((tinstr & 0x07FF) << 12) | ((tinstr & (1 << 10)) ? 0xFF800000 : 0)); valid = t_branch; /* in-case we don't have the 2nd half */ tinstr = next_instr; /* move the instruction down */ if (((tinstr & 0xF800) >> 11) != 31) break; /* exit, since not correct instruction */ /* else we fall through to process the second half of the BL */ pc += 2; /* point the pc at the 2nd half */ case 31: /* BL instruction 2 */ /* Format 19 */ /* There is no single ARM instruction equivalent for this instruction. Also, it should only ever be matched with the fmt19 "BL instruction 1" instruction. However, we do allow the simulation of it on its own, with undefined results if r14 is not suitably initialised. */ { ARMword tmp = (pc + 2); state->Reg[15] = (state->Reg[14] + ((tinstr & 0x07FF) << 1)); state->Reg[14] = (tmp | 1); valid = t_branch; FLUSHPIPE; } break; } return valid; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armengr.h����������������������������������������������������������0000644�0001750�0000144�00000002071�10541455476�017041� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armengr.h -- ARMulator emulation macros: SA11x Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _ARMENGR_H_ #define _ARMENGR_H_ extern void ARMul_EnergyInit (ARMul_State * state); extern void ARMul_do_energy (ARMul_State * state, ARMword instr, ARMword pc); extern void ARMul_do_cycle (ARMul_State * state); #endif �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armsym.h�����������������������������������������������������������0000644�0001750�0000144�00000004566�10541455476�016731� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armsym.h -- ARMulator emulation macros: SA11x Instruction Emulator. Copyright (C) 2001 Princeton University. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef ARMSYM_H #define ARMSYM_H #include "armdefs.h" struct sym_func { char *name; long long total_energy; // for all instances long long total_cycle; // for all instances int instances; // number of instances }; typedef struct sym_func SYM_FUNC; struct sym_funcinst { /* Function Info */ SYM_FUNC *func_symbol; ARMword func_start_addr; // the address at which this function starts ARMword ret_addr; // the PC at which we make sub-routine call /* Profiling Data */ float tenergy; long long tcycle; }; #define MAX_LEVEL 1024 struct sym_taskinst { ARMword task_id; // Actually is the pointer to Linux struct task_struct /* Task call stack */ struct sym_funcinst func_stack[MAX_LEVEL]; int level; /* Profiling Data */ float total_energy; long long total_cycle; /* link data */ struct sym_taskinst *next; }; typedef struct sym_funcinst FUNC_NODE; typedef struct sym_taskinst TASK_STACK; /***************************************************** Function declaration ******************************************************/ //void ARMul_InitSymTable(bfd *abfd); SYM_FUNC *ARMul_GetSym (ARMword address); void ARMul_ProfInit (ARMul_State * state); FUNC_NODE *ARMul_CreateChild (ARMul_State * state); void ARMul_DestroyChild (ARMul_State * state); void ARMul_CallCheck (ARMul_State * state, ARMword cur_pc, ARMword to_pc, ARMword instr); void ARMul_TaskSwitch (ARMul_State * state); ARMword ARMul_TaskCreate (ARMul_State * state); void ARMul_ReportEnergy (ARMul_State * state, FILE * pf); void ARMul_Consolidate (ARMul_State * state); #endif ������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armcopro.c���������������������������������������������������������0000644�0001750�0000144�00000114016�10541455476�017226� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator. Copyright (C) 1994, 2000 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "armdefs.h" #include "armos.h" #include "armemu.h" //chy 2005-07-08 #include "ansidecl.h" //chy ------- //#include "iwmmxt.h" //chy 2005-09-19 add CP6 MRC support (for get irq number and base) extern unsigned xscale_cp6_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data); //chy 2005-09-19--------------- extern unsigned xscale_cp13_init (ARMul_State * state); extern unsigned xscale_cp13_exit (ARMul_State * state); extern unsigned xscale_cp13_ldc (ARMul_State * state, unsigned type, ARMword instr, ARMword data); extern unsigned xscale_cp13_stc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data); extern unsigned xscale_cp13_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data); extern unsigned xscale_cp13_mcr (ARMul_State * state, unsigned type, ARMword instr, ARMword data); extern unsigned xscale_cp13_cdp (ARMul_State * state, unsigned type, ARMword instr); extern unsigned xscale_cp13_read_reg (ARMul_State * state, unsigned reg, ARMword * data); extern unsigned xscale_cp13_write_reg (ARMul_State * state, unsigned reg, ARMword data); extern unsigned xscale_cp14_init (ARMul_State * state); extern unsigned xscale_cp14_exit (ARMul_State * state); extern unsigned xscale_cp14_ldc (ARMul_State * state, unsigned type, ARMword instr, ARMword data); extern unsigned xscale_cp14_stc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data); extern unsigned xscale_cp14_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data); extern unsigned xscale_cp14_mcr (ARMul_State * state, unsigned type, ARMword instr, ARMword data); extern unsigned xscale_cp14_cdp (ARMul_State * state, unsigned type, ARMword instr); extern unsigned xscale_cp14_read_reg (ARMul_State * state, unsigned reg, ARMword * data); extern unsigned xscale_cp14_write_reg (ARMul_State * state, unsigned reg, ARMword data); extern unsigned xscale_cp15_init (ARMul_State * state); extern unsigned xscale_cp15_exit (ARMul_State * state); extern unsigned xscale_cp15_ldc (ARMul_State * state, unsigned type, ARMword instr, ARMword data); extern unsigned xscale_cp15_stc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data); extern unsigned xscale_cp15_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data); extern unsigned xscale_cp15_mcr (ARMul_State * state, unsigned type, ARMword instr, ARMword data); extern unsigned xscale_cp15_cdp (ARMul_State * state, unsigned type, ARMword instr); extern unsigned xscale_cp15_read_reg (ARMul_State * state, unsigned reg, ARMword * data); extern unsigned xscale_cp15_write_reg (ARMul_State * state, unsigned reg, ARMword data); /* Dummy Co-processors. */ static unsigned NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED, unsigned a ATTRIBUTE_UNUSED, ARMword b ATTRIBUTE_UNUSED) { return ARMul_CANT; } static unsigned NoCoPro4R (ARMul_State * state ATTRIBUTE_UNUSED, unsigned a ATTRIBUTE_UNUSED, ARMword b ATTRIBUTE_UNUSED, ARMword c ATTRIBUTE_UNUSED) { return ARMul_CANT; } static unsigned NoCoPro4W (ARMul_State * state ATTRIBUTE_UNUSED, unsigned a ATTRIBUTE_UNUSED, ARMword b ATTRIBUTE_UNUSED, ARMword * c ATTRIBUTE_UNUSED) { return ARMul_CANT; } /* The XScale Co-processors. */ /* Coprocessor 15: System Control. */ static void write_cp14_reg (unsigned, ARMword); static ARMword read_cp14_reg (unsigned); /* There are two sets of registers for copro 15. One set is available when opcode_2 is 0 and the other set when opcode_2 >= 1. */ static ARMword XScale_cp15_opcode_2_is_0_Regs[16]; static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16]; /* There are also a set of breakpoint registers which are accessed via CRm instead of opcode_2. */ static ARMword XScale_cp15_DBR1; static ARMword XScale_cp15_DBCON; static ARMword XScale_cp15_IBCR0; static ARMword XScale_cp15_IBCR1; static unsigned XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED) { int i; for (i = 16; i--;) { XScale_cp15_opcode_2_is_0_Regs[i] = 0; XScale_cp15_opcode_2_is_not_0_Regs[i] = 0; } /* Initialise the processor ID. */ //chy 2003-03-24, is same as cpu id in skyeye_options.c //XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000; XScale_cp15_opcode_2_is_0_Regs[0] = 0x69050000; /* Initialise the cache type. */ XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA; /* Initialise the ARM Control Register. */ XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078; } /* Check an access to a register. */ static unsigned check_cp15_access (ARMul_State * state, unsigned reg, unsigned CRm, unsigned opcode_1, unsigned opcode_2) { /* Do not allow access to these register in USER mode. */ //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode == USER26MODE || state->Mode == USER32MODE ) return ARMul_CANT; /* Opcode_1should be zero. */ if (opcode_1 != 0) return ARMul_CANT; /* Different register have different access requirements. */ switch (reg) { case 0: case 1: /* CRm must be 0. Opcode_2 can be anything. */ if (CRm != 0) return ARMul_CANT; break; case 2: case 3: /* CRm must be 0. Opcode_2 must be zero. */ if ((CRm != 0) || (opcode_2 != 0)) return ARMul_CANT; break; case 4: /* Access not allowed. */ return ARMul_CANT; case 5: case 6: /* Opcode_2 must be zero. CRm must be 0. */ if ((CRm != 0) || (opcode_2 != 0)) return ARMul_CANT; break; case 7: /* Permissable combinations: Opcode_2 CRm 0 5 0 6 0 7 1 5 1 6 1 10 4 10 5 2 6 5 */ switch (opcode_2) { default: return ARMul_CANT; case 6: if (CRm != 5) return ARMul_CANT; break; case 5: if (CRm != 2) return ARMul_CANT; break; case 4: if (CRm != 10) return ARMul_CANT; break; case 1: if ((CRm != 5) && (CRm != 6) && (CRm != 10)) return ARMul_CANT; break; case 0: if ((CRm < 5) || (CRm > 7)) return ARMul_CANT; break; } break; case 8: /* Permissable combinations: Opcode_2 CRm 0 5 0 6 0 7 1 5 1 6 */ if (opcode_2 > 1) return ARMul_CANT; if ((CRm < 5) || (CRm > 7)) return ARMul_CANT; if (opcode_2 == 1 && CRm == 7) return ARMul_CANT; break; case 9: /* Opcode_2 must be zero or one. CRm must be 1 or 2. */ if (((CRm != 0) && (CRm != 1)) || ((opcode_2 != 1) && (opcode_2 != 2))) return ARMul_CANT; break; case 10: /* Opcode_2 must be zero or one. CRm must be 4 or 8. */ if (((CRm != 0) && (CRm != 1)) || ((opcode_2 != 4) && (opcode_2 != 8))) return ARMul_CANT; break; case 11: /* Access not allowed. */ return ARMul_CANT; case 12: /* Access not allowed. */ return ARMul_CANT; case 13: /* Opcode_2 must be zero. CRm must be 0. */ if ((CRm != 0) || (opcode_2 != 0)) return ARMul_CANT; break; case 14: /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */ if (opcode_2 != 0) return ARMul_CANT; if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) && (CRm != 9)) return ARMul_CANT; break; case 15: /* Opcode_2 must be zero. CRm must be 1. */ if ((CRm != 1) || (opcode_2 != 0)) return ARMul_CANT; break; default: /* Should never happen. */ return ARMul_CANT; } return ARMul_DONE; } //chy 2003-09-03 commit below funs #if 0 /* Store a value into one of coprocessor 15's registers. */ static void write_cp15_reg (ARMul_State * state, unsigned reg, unsigned opcode_2, unsigned CRm, ARMword value) { if (opcode_2) { switch (reg) { case 0: /* Cache Type. */ /* Writes are not allowed. */ return; case 1: /* Auxillary Control. */ /* Only BITS (5, 4) and BITS (1, 0) can be written. */ value &= 0x33; break; default: return; } XScale_cp15_opcode_2_is_not_0_Regs[reg] = value; } else { switch (reg) { case 0: /* ID. */ /* Writes are not allowed. */ return; case 1: /* ARM Control. */ /* Only BITS (13, 11), BITS (9, 7) and BITS (2, 0) can be written. BITS (31, 14) and BIT (10) write as zero, BITS (6, 3) write as one. */ value &= 0x00003b87; value |= 0x00000078; /* Change the endianness if necessary. */ if ((value & ARMul_CP15_R1_ENDIAN) != (XScale_cp15_opcode_2_is_0_Regs[reg] & ARMul_CP15_R1_ENDIAN)) { state->bigendSig = value & ARMul_CP15_R1_ENDIAN; /* Force ARMulator to notice these now. */ state->Emulate = CHANGEMODE; } break; case 2: /* Translation Table Base. */ /* Only BITS (31, 14) can be written. */ value &= 0xffffc000; break; case 3: /* Domain Access Control. */ /* All bits writable. */ break; case 5: /* Fault Status Register. */ /* BITS (10, 9) and BITS (7, 0) can be written. */ value &= 0x000006ff; break; case 6: /* Fault Address Register. */ /* All bits writable. */ break; case 7: /* Cache Functions. */ case 8: /* TLB Operations. */ case 10: /* TLB Lock Down. */ /* Ignore writes. */ return; case 9: /* Data Cache Lock. */ /* Only BIT (0) can be written. */ value &= 0x1; break; case 13: /* Process ID. */ /* Only BITS (31, 25) are writable. */ value &= 0xfe000000; break; case 14: /* DBR0, DBR1, DBCON, IBCR0, IBCR1 */ /* All bits can be written. Which register is accessed is dependent upon CRm. */ switch (CRm) { case 0: /* DBR0 */ break; case 3: /* DBR1 */ XScale_cp15_DBR1 = value; break; case 4: /* DBCON */ XScale_cp15_DBCON = value; break; case 8: /* IBCR0 */ XScale_cp15_IBCR0 = value; break; case 9: /* IBCR1 */ XScale_cp15_IBCR1 = value; break; default: return; } break; case 15: /* Coprpcessor Access Register. */ /* Access is only valid if CRm == 1. */ if (CRm != 1) return; /* Only BITS (13, 0) may be written. */ value &= 0x00003fff; break; default: return; } XScale_cp15_opcode_2_is_0_Regs[reg] = value; } return; } /* Return the value in a cp15 register. */ ARMword read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm) { if (opcode_2 == 0) { if (reg == 15 && CRm != 1) return 0; if (reg == 14) { switch (CRm) { case 3: return XScale_cp15_DBR1; case 4: return XScale_cp15_DBCON; case 8: return XScale_cp15_IBCR0; case 9: return XScale_cp15_IBCR1; default: break; } } return XScale_cp15_opcode_2_is_0_Regs[reg]; } else return XScale_cp15_opcode_2_is_not_0_Regs[reg]; return 0; } static unsigned XScale_cp15_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { unsigned reg = BITS (12, 15); unsigned result; result = check_cp15_access (state, reg, 0, 0, 0); if (result == ARMul_DONE && type == ARMul_DATA) write_cp15_reg (state, reg, 0, 0, data); return result; } static unsigned XScale_cp15_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { unsigned reg = BITS (12, 15); unsigned result; result = check_cp15_access (state, reg, 0, 0, 0); if (result == ARMul_DONE && type == ARMul_DATA) *data = read_cp15_reg (reg, 0, 0); return result; } static unsigned XScale_cp15_MRC (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { unsigned opcode_2 = BITS (5, 7); unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2); if (result == ARMul_DONE) *value = read_cp15_reg (reg, opcode_2, CRm); return result; } static unsigned XScale_cp15_MCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { unsigned opcode_2 = BITS (5, 7); unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2); if (result == ARMul_DONE) write_cp15_reg (state, reg, opcode_2, CRm, value); return result; } static unsigned XScale_cp15_read_reg (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value) { /* FIXME: Not sure what to do about the alternative register set here. For now default to just accessing CRm == 0 registers. */ *value = read_cp15_reg (reg, 0, 0); return TRUE; } static unsigned XScale_cp15_write_reg (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword value) { /* FIXME: Not sure what to do about the alternative register set here. For now default to just accessing CRm == 0 registers. */ write_cp15_reg (state, reg, 0, 0, value); return TRUE; } /* Check for special XScale memory access features. */ void XScale_check_memacc (ARMul_State * state, ARMword * address, int store) { ARMword dbcon, r0, r1; int e1, e0; if (!state->is_XScale) return; /* Check for PID-ification. XXX BTB access support will require this test failing. */ r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000); if (r0 && (*address & 0xfe000000) == 0) *address |= r0; /* Check alignment fault enable/disable. */ if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (*address & 3)) { /* Set the FSR and FAR. Do not use XScale_set_fsr_far as this checks the DCSR register. */ write_cp15_reg (state, 5, 0, 0, ARMul_CP15_R5_MMU_EXCPT); write_cp15_reg (state, 6, 0, 0, *address); ARMul_Abort (state, ARMul_DataAbortV); } if (XScale_debug_moe (state, -1)) return; /* Check the data breakpoint registers. */ dbcon = read_cp15_reg (14, 0, 4); r0 = read_cp15_reg (14, 0, 0); r1 = read_cp15_reg (14, 0, 3); e0 = dbcon & ARMul_CP15_DBCON_E0; if (dbcon & ARMul_CP15_DBCON_M) { /* r1 is a inverse mask. */ if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1)) && ((*address & ~r1) == (r0 & ~r1))) { XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); ARMul_OSHandleSWI (state, SWI_Breakpoint); } } else { if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1)) && ((*address & ~3) == (r0 & ~3))) { XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); ARMul_OSHandleSWI (state, SWI_Breakpoint); } e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2; if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1)) && ((*address & ~3) == (r1 & ~3))) { XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); ARMul_OSHandleSWI (state, SWI_Breakpoint); } } } // Anthony Lee removed 2006-08-27: below has one to replace this #if 0 /* Set the XScale FSR and FAR registers. */ void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword _far) { if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0) return; write_cp15_reg (state, 5, 0, 0, fsr); write_cp15_reg (state, 6, 0, 0, _far); } #endif /* Set the XScale debug `method of entry' if it is enabled. */ int XScale_debug_moe (ARMul_State * state, int moe) { ARMword value; if (!state->is_XScale) return 1; value = read_cp14_reg (10); if (value & (1UL << 31)) { if (moe != -1) { value &= ~0x1c; value |= moe; write_cp14_reg (10, value); } return 1; } return 0; } #endif /* Coprocessor 13: Interrupt Controller and Bus Controller. */ /* There are two sets of registers for copro 13. One set (of three registers) is available when CRm is 0 and the other set (of six registers) when CRm is 1. */ static ARMword XScale_cp13_CR0_Regs[16]; static ARMword XScale_cp13_CR1_Regs[16]; static unsigned XScale_cp13_init (ARMul_State * state ATTRIBUTE_UNUSED) { int i; for (i = 16; i--;) { XScale_cp13_CR0_Regs[i] = 0; XScale_cp13_CR1_Regs[i] = 0; } } /* Check an access to a register. */ static unsigned check_cp13_access (ARMul_State * state, unsigned reg, unsigned CRm, unsigned opcode_1, unsigned opcode_2) { /* Do not allow access to these registers in USER mode. */ //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode == USER26MODE || state->Mode == USER32MODE ) return ARMul_CANT; /* The opcodes should be zero. */ if ((opcode_1 != 0) || (opcode_2 != 0)) return ARMul_CANT; /* Do not allow access to these register if bit 13 of coprocessor 15's register 15 is zero. */ if (!CP_ACCESS_ALLOWED (state, 13)) return ARMul_CANT; /* Registers 0, 4 and 8 are defined when CRm == 0. Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1. For all other CRm values undefined behaviour results. */ if (CRm == 0) { if (reg == 0 || reg == 4 || reg == 8) return ARMul_DONE; } else if (CRm == 1) { if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8)) return ARMul_DONE; } return ARMul_CANT; } #if 0 /* Store a value into one of coprocessor 13's registers. */ static void write_cp13_reg (unsigned reg, unsigned CRm, ARMword value) { switch (CRm) { case 0: switch (reg) { case 0: /* INTCTL */ /* Only BITS (3:0) can be written. */ value &= 0xf; break; case 4: /* INTSRC */ /* No bits may be written. */ return; case 8: /* INTSTR */ /* Only BITS (1:0) can be written. */ value &= 0x3; break; default: /* Should not happen. Ignore any writes to unimplemented registers. */ return; } XScale_cp13_CR0_Regs[reg] = value; break; case 1: switch (reg) { case 0: /* BCUCTL */ /* Only BITS (30:28) and BITS (3:0) can be written. BIT(31) is write ignored. */ value &= 0x7000000f; value |= XScale_cp13_CR1_Regs[0] & (1UL << 31); break; case 1: /* BCUMOD */ /* Only bit 0 is accecssible. */ value &= 1; value |= XScale_cp13_CR1_Regs[1] & ~1; break; case 4: /* ELOG0 */ case 5: /* ELOG1 */ case 6: /* ECAR0 */ case 7: /* ECAR1 */ /* No bits can be written. */ return; case 8: /* ECTST */ /* Only BITS (7:0) can be written. */ value &= 0xff; break; default: /* Should not happen. Ignore any writes to unimplemented registers. */ return; } XScale_cp13_CR1_Regs[reg] = value; break; default: /* Should not happen. */ break; } return; } /* Return the value in a cp13 register. */ static ARMword read_cp13_reg (unsigned reg, unsigned CRm) { if (CRm == 0) return XScale_cp13_CR0_Regs[reg]; else if (CRm == 1) return XScale_cp13_CR1_Regs[reg]; return 0; } static unsigned XScale_cp13_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { unsigned reg = BITS (12, 15); unsigned result; result = check_cp13_access (state, reg, 0, 0, 0); if (result == ARMul_DONE && type == ARMul_DATA) write_cp13_reg (reg, 0, data); return result; } static unsigned XScale_cp13_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { unsigned reg = BITS (12, 15); unsigned result; result = check_cp13_access (state, reg, 0, 0, 0); if (result == ARMul_DONE && type == ARMul_DATA) *data = read_cp13_reg (reg, 0); return result; } static unsigned XScale_cp13_MRC (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7)); if (result == ARMul_DONE) *value = read_cp13_reg (reg, CRm); return result; } static unsigned XScale_cp13_MCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7)); if (result == ARMul_DONE) write_cp13_reg (reg, CRm, value); return result; } static unsigned XScale_cp13_read_reg (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value) { /* FIXME: Not sure what to do about the alternative register set here. For now default to just accessing CRm == 0 registers. */ *value = read_cp13_reg (reg, 0); return TRUE; } static unsigned XScale_cp13_write_reg (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword value) { /* FIXME: Not sure what to do about the alternative register set here. For now default to just accessing CRm == 0 registers. */ write_cp13_reg (reg, 0, value); return TRUE; } #endif /* Coprocessor 14: Performance Monitoring, Clock and Power management, Software Debug. */ static ARMword XScale_cp14_Regs[16]; static unsigned XScale_cp14_init (ARMul_State * state ATTRIBUTE_UNUSED) { int i; for (i = 16; i--;) XScale_cp14_Regs[i] = 0; } /* Check an access to a register. */ static unsigned check_cp14_access (ARMul_State * state, unsigned reg, unsigned CRm, unsigned opcode1, unsigned opcode2) { /* Not allowed to access these register in USER mode. */ //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode == USER26MODE || state->Mode == USER32MODE ) return ARMul_CANT; /* CRm should be zero. */ if (CRm != 0) return ARMul_CANT; /* OPcodes should be zero. */ if (opcode1 != 0 || opcode2 != 0) return ARMul_CANT; /* Accessing registers 4 or 5 has unpredicatable results. */ if (reg >= 4 && reg <= 5) return ARMul_CANT; return ARMul_DONE; } #if 0 /* Store a value into one of coprocessor 14's registers. */ static void write_cp14_reg (unsigned reg, ARMword value) { switch (reg) { case 0: /* PMNC */ /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */ value &= 0x0ffff77f; /* Reset the clock counter if necessary. */ if (value & ARMul_CP14_R0_CLKRST) XScale_cp14_Regs[1] = 0; break; case 4: case 5: /* We should not normally reach this code. The debugger interface can bypass the normal checks though, so it could happen. */ value = 0; break; case 6: /* CCLKCFG */ /* Only BITS (3:0) can be written. */ value &= 0xf; break; case 7: /* PWRMODE */ /* Although BITS (1:0) can be written with non-zero values, this would have the side effect of putting the processor to sleep. Thus in order for the register to be read again, it would have to go into ACTIVE mode, which means that any read will see these bits as zero. Rather than trying to implement complex reset-to-zero-upon-read logic we just override the write value with zero. */ value = 0; break; case 10: /* DCSR */ /* Only BITS (31:30), BITS (23:22), BITS (20:16) and BITS (5:0) can be written. */ value &= 0xc0df003f; break; case 11: /* TBREG */ /* No writes are permitted. */ value = 0; break; case 14: /* TXRXCTRL */ /* Only BITS (31:30) can be written. */ value &= 0xc0000000; break; default: /* All bits can be written. */ break; } XScale_cp14_Regs[reg] = value; } /* Return the value in a cp14 register. Not a static function since it is used by the code to emulate the BKPT instruction in armemu.c. */ ARMword read_cp14_reg (unsigned reg) { return XScale_cp14_Regs[reg]; } static unsigned XScale_cp14_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { unsigned reg = BITS (12, 15); unsigned result; result = check_cp14_access (state, reg, 0, 0, 0); if (result == ARMul_DONE && type == ARMul_DATA) write_cp14_reg (reg, data); return result; } static unsigned XScale_cp14_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { unsigned reg = BITS (12, 15); unsigned result; result = check_cp14_access (state, reg, 0, 0, 0); if (result == ARMul_DONE && type == ARMul_DATA) *data = read_cp14_reg (reg); return result; } static unsigned XScale_cp14_MRC (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { unsigned reg = BITS (16, 19); unsigned result; result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7)); if (result == ARMul_DONE) *value = read_cp14_reg (reg); return result; } static unsigned XScale_cp14_MCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { unsigned reg = BITS (16, 19); unsigned result; result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7)); if (result == ARMul_DONE) write_cp14_reg (reg, value); return result; } static unsigned XScale_cp14_read_reg (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value) { *value = read_cp14_reg (reg); return TRUE; } static unsigned XScale_cp14_write_reg (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword value) { write_cp14_reg (reg, value); return TRUE; } #endif /* Here's ARMulator's MMU definition. A few things to note: 1) It has eight registers, but only two are defined. 2) You can only access its registers with MCR and MRC. 3) MMU Register 0 (ID) returns 0x41440110 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4 controls 32/26 bit program space, bit 5 controls 32/26 bit data space, bit 6 controls late abort timimg and bit 7 controls big/little endian. */ static ARMword MMUReg[8]; static unsigned MMUInit (ARMul_State * state) { /* 2004-05-09 chy ------------------------------------------------------------- read ARM Architecture Reference Manual 2.6.5 Data Abort There are three Abort Model in ARM arch. Early Abort Model: used in some ARMv3 and earlier implementations. In this model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and the base register was unchanged for all other instructions. (oldest) Base Restored Abort Model: If a Data Abort occurs in an instruction which specifies base register writeback, the value in the base register is unchanged. (strongarm, xscale) Base Updated Abort Model: If a Data Abort occurs in an instruction which specifies base register writeback, the base register writeback still occurs. (arm720T) read PART B chap2 The System Control Coprocessor CP15 2.4 Register1:control register L(bit 6): in some ARMv3 and earlier implementations, the abort model of the processor could be configured: 0=early Abort Model Selected(now obsolete) 1=Late Abort Model selceted(same as Base Updated Abort Model) on later processors, this bit reads as 1 and ignores writes. ------------------------------------------------------------- So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) if lateabtSig=0, then it means Base Restored Abort Model because the ARMs which skyeye simulates are all belonged to ARMv4, so I think MMUReg[1]'s bit 6 should always be 1 */ MMUReg[1] = state->prog32Sig << 4 | state->data32Sig << 5 | 1 << 6 | state->bigendSig << 7; //state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7; ARMul_ConsolePrint (state, ", MMU present"); return TRUE; } static unsigned MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { mmu_mrc (state, instr, value); return (ARMul_DONE); } static unsigned MMUMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value) { mmu_mcr (state, instr, value); return (ARMul_DONE); } #if 0 static unsigned MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { int reg = BITS (16, 19) & 7; if (reg == 0) *value = 0x41440110; else *value = MMUReg[reg]; return ARMul_DONE; } static unsigned MMUMCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { int reg = BITS (16, 19) & 7; MMUReg[reg] = value; if (reg == 1) { ARMword p, d, l, b; p = state->prog32Sig; d = state->data32Sig; l = state->lateabtSig; b = state->bigendSig; state->prog32Sig = value >> 4 & 1; state->data32Sig = value >> 5 & 1; state->lateabtSig = value >> 6 & 1; state->bigendSig = value >> 7 & 1; if (p != state->prog32Sig || d != state->data32Sig || l != state->lateabtSig || b != state->bigendSig) /* Force ARMulator to notice these now. */ state->Emulate = CHANGEMODE; } return ARMul_DONE; } static unsigned MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value) { if (reg == 0) *value = 0x41440110; else if (reg < 8) *value = MMUReg[reg]; return TRUE; } static unsigned MMUWrite (ARMul_State * state, unsigned reg, ARMword value) { if (reg < 8) MMUReg[reg] = value; if (reg == 1) { ARMword p, d, l, b; p = state->prog32Sig; d = state->data32Sig; l = state->lateabtSig; b = state->bigendSig; state->prog32Sig = value >> 4 & 1; state->data32Sig = value >> 5 & 1; state->lateabtSig = value >> 6 & 1; state->bigendSig = value >> 7 & 1; if (p != state->prog32Sig || d != state->data32Sig || l != state->lateabtSig || b != state->bigendSig) /* Force ARMulator to notice these now. */ state->Emulate = CHANGEMODE; } return TRUE; } #endif /* What follows is the Validation Suite Coprocessor. It uses two co-processor numbers (4 and 5) and has the follwing functionality. Sixteen registers. Both co-processor nuimbers can be used in an MCR and MRC to access these registers. CP 4 can LDC and STC to and from the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of cycles (specified in a CP register), CDP 2 issues an IRQW in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32 bit time value in a CP register (actually it's the total number of N, S, I, C and F cyles). */ static ARMword ValReg[16]; static unsigned ValLDC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword data) { static unsigned words; if (type != ARMul_DATA) words = 0; else { ValReg[BITS (12, 15)] = data; if (BIT (22)) /* It's a long access, get two words. */ if (words++ != 4) return ARMul_INC; } return ARMul_DONE; } static unsigned ValSTC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword * data) { static unsigned words; if (type != ARMul_DATA) words = 0; else { *data = ValReg[BITS (12, 15)]; if (BIT (22)) /* It's a long access, get two words. */ if (words++ != 4) return ARMul_INC; } return ARMul_DONE; } static unsigned ValMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { *value = ValReg[BITS (16, 19)]; return ARMul_DONE; } static unsigned ValMCR (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { ValReg[BITS (16, 19)] = value; return ARMul_DONE; } static unsigned ValCDP (ARMul_State * state, unsigned type, ARMword instr) { static unsigned int finish = 0; if (BITS (20, 23) != 0) return ARMul_CANT; if (type == ARMul_FIRST) { ARMword howlong; howlong = ValReg[BITS (0, 3)]; /* First cycle of a busy wait. */ finish = ARMul_Time (state) + howlong; return howlong == 0 ? ARMul_DONE : ARMul_BUSY; } else if (type == ARMul_BUSY) { if (ARMul_Time (state) >= finish) return ARMul_DONE; else return ARMul_BUSY; } return ARMul_CANT; } static unsigned DoAFIQ (ARMul_State * state) { state->NfiqSig = LOW; return 0; } static unsigned DoAIRQ (ARMul_State * state) { state->NirqSig = LOW; return 0; } static unsigned IntCDP (ARMul_State * state, unsigned type, ARMword instr) { static unsigned int finish; ARMword howlong; howlong = ValReg[BITS (0, 3)]; switch ((int) BITS (20, 23)) { case 0: if (type == ARMul_FIRST) { /* First cycle of a busy wait. */ finish = ARMul_Time (state) + howlong; return howlong == 0 ? ARMul_DONE : ARMul_BUSY; } else if (type == ARMul_BUSY) { if (ARMul_Time (state) >= finish) return ARMul_DONE; else return ARMul_BUSY; } return ARMul_DONE; case 1: if (howlong == 0) ARMul_Abort (state, ARMul_FIQV); else ARMul_ScheduleEvent (state, howlong, DoAFIQ); return ARMul_DONE; case 2: if (howlong == 0) ARMul_Abort (state, ARMul_IRQV); else ARMul_ScheduleEvent (state, howlong, DoAIRQ); return ARMul_DONE; case 3: state->NfiqSig = HIGH; return ARMul_DONE; case 4: state->NirqSig = HIGH; return ARMul_DONE; case 5: ValReg[BITS (0, 3)] = ARMul_Time (state); return ARMul_DONE; } return ARMul_CANT; } /* Install co-processor instruction handlers in this routine. */ unsigned ARMul_CoProInit (ARMul_State * state) { unsigned int i; /* Initialise tham all first. */ for (i = 0; i < 16; i++) ARMul_CoProDetach (state, i); /* Install CoPro Instruction handlers here. The format is: ARMul_CoProAttach (state, CP Number, Init routine, Exit routine LDC routine, STC routine, MRC routine, MCR routine, CDP routine, Read Reg routine, Write Reg routine). */ if (state->is_ep9312) { ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4, DSPMRC4, DSPMCR4, DSPCDP4, NULL, NULL); ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5, DSPMRC5, DSPMCR5, DSPCDP5, NULL, NULL); ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL, DSPMRC6, DSPMCR6, DSPCDP6, NULL, NULL); } else { ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL); ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL); } if (state->is_XScale) { //chy 2005-09-19, for PXA27x's CP6 if (state->is_pxa27x) { ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL, xscale_cp6_mrc, NULL, NULL, NULL, NULL); } //chy 2005-09-19 end------------- ARMul_CoProAttach (state, 13, xscale_cp13_init, xscale_cp13_exit, xscale_cp13_ldc, xscale_cp13_stc, xscale_cp13_mrc, xscale_cp13_mcr, xscale_cp13_cdp, xscale_cp13_read_reg, xscale_cp13_write_reg); ARMul_CoProAttach (state, 14, xscale_cp14_init, xscale_cp14_exit, xscale_cp14_ldc, xscale_cp14_stc, xscale_cp14_mrc, xscale_cp14_mcr, xscale_cp14_cdp, xscale_cp14_read_reg, xscale_cp14_write_reg); //chy: 2003-08-24. ARMul_CoProAttach (state, 15, xscale_cp15_init, xscale_cp15_exit, xscale_cp15_ldc, xscale_cp15_stc, xscale_cp15_mrc, xscale_cp15_mcr, xscale_cp15_cdp, xscale_cp15_read_reg, xscale_cp15_write_reg); } else { //all except xscale ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL, // MMUMRC, MMUMCR, NULL, MMURead, MMUWrite); MMUMRC, MMUMCR, NULL, NULL, NULL); } //chy 2003-09-03 do it in future!!!!???? #if 0 if (state->is_iWMMXt) { ARMul_CoProAttach (state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC, NULL, NULL, IwmmxtCDP, NULL, NULL); ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL, IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL, NULL); } #endif //----------------------------------------------------------------------------- //chy 2004-05-25, found the user/system code visit CP 1,2, so I add below code. ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL, ValMRC, ValMCR, NULL, NULL, NULL); ARMul_CoProAttach (state, 2, NULL, NULL, ValLDC, ValSTC, NULL, NULL, NULL, NULL, NULL); //------------------------------------------------------------------------------ /* No handlers below here. */ /* Call all the initialisation routines. */ for (i = 0; i < 16; i++) if (state->CPInit[i]) (state->CPInit[i]) (state); return TRUE; } /* Install co-processor finalisation routines in this routine. */ void ARMul_CoProExit (ARMul_State * state) { register unsigned i; for (i = 0; i < 16; i++) if (state->CPExit[i]) (state->CPExit[i]) (state); for (i = 0; i < 16; i++) /* Detach all handlers. */ ARMul_CoProDetach (state, i); } /* Routines to hook Co-processors into ARMulator. */ void ARMul_CoProAttach (ARMul_State * state, unsigned number, ARMul_CPInits * init, ARMul_CPExits * exit, ARMul_LDCs * ldc, ARMul_STCs * stc, ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp, ARMul_CPReads * read, ARMul_CPWrites * write) { if (init != NULL) state->CPInit[number] = init; if (exit != NULL) state->CPExit[number] = exit; if (ldc != NULL) state->LDC[number] = ldc; if (stc != NULL) state->STC[number] = stc; if (mrc != NULL) state->MRC[number] = mrc; if (mcr != NULL) state->MCR[number] = mcr; if (cdp != NULL) state->CDP[number] = cdp; if (read != NULL) state->CPRead[number] = read; if (write != NULL) state->CPWrite[number] = write; } void ARMul_CoProDetach (ARMul_State * state, unsigned number) { ARMul_CoProAttach (state, number, NULL, NULL, NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, NoCoPro3R, NULL, NULL); state->CPInit[number] = NULL; state->CPExit[number] = NULL; state->CPRead[number] = NULL; state->CPWrite[number] = NULL; } //chy 2003-09-03:below funs just replace the old ones /* Set the XScale FSR and FAR registers. */ void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword _far) { //if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0) if (!state->is_XScale) return; //assume opcode2=0 crm =0 xscale_cp15_write_reg (state, 5, fsr); xscale_cp15_write_reg (state, 6, _far); } //chy 2003-09-03 seems 0 is CANT, 1 is DONE ???? int XScale_debug_moe (ARMul_State * state, int moe) { //chy 2003-09-03 , W/R CP14 reg, now it's no use ???? printf ("SKYEYE: XScale_debug_moe called !!!!\n"); return 1; } #if 0 //chy 2003-09-03 : only called by iwmmxt.c!!!! //chy assume opcode_2=0 /* Return the value in a cp15 register. */ ARMword read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm) { unsigned value; if (reg != 15) { printf ("SKYEYE: read_cp15_reg read other reg 0x%x \n", reg); exit (-1); } xscale_cp15_read_reg (reg, &value); printf ("SKYEYE: read_cp15_reg read reg 0x%x, val 0x%x \n", reg, value); return value; } #endif ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armemu.c�����������������������������������������������������������0000644�0001750�0000144�00000425756�11006552446�016702� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. Modifications to add arch. v4 support by <jsmith@cygnus.com>. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "armdefs.h" #include "armemu.h" #include "armos.h" #include "skyeye2gdb.h" #include "code_cov.h" //#include "iwmmxt.h" //chy 2003-07-11: for debug instrs //extern int skyeye_instr_debug; extern FILE *skyeye_logfd; static ARMword GetDPRegRHS (ARMul_State *, ARMword); static ARMword GetDPSRegRHS (ARMul_State *, ARMword); static void WriteR15 (ARMul_State *, ARMword); static void WriteSR15 (ARMul_State *, ARMword); static void WriteR15Branch (ARMul_State *, ARMword); static ARMword GetLSRegRHS (ARMul_State *, ARMword); static ARMword GetLS7RHS (ARMul_State *, ARMword); static unsigned LoadWord (ARMul_State *, ARMword, ARMword); static unsigned LoadHalfWord (ARMul_State *, ARMword, ARMword, int); static unsigned LoadByte (ARMul_State *, ARMword, ARMword, int); static unsigned StoreWord (ARMul_State *, ARMword, ARMword); static unsigned StoreHalfWord (ARMul_State *, ARMword, ARMword); static unsigned StoreByte (ARMul_State *, ARMword, ARMword); static void LoadMult (ARMul_State *, ARMword, ARMword, ARMword); static void StoreMult (ARMul_State *, ARMword, ARMword, ARMword); static void LoadSMult (ARMul_State *, ARMword, ARMword, ARMword); static void StoreSMult (ARMul_State *, ARMword, ARMword, ARMword); static unsigned Multiply64 (ARMul_State *, ARMword, int, int); static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int); static void Handle_Load_Double (ARMul_State *, ARMword); static void Handle_Store_Double (ARMul_State *, ARMword); static int handle_v6_insn (ARMul_State * state, ARMword instr); #define LUNSIGNED (0) /* unsigned operation */ #define LSIGNED (1) /* signed operation */ #define LDEFAULT (0) /* default : do nothing */ #define LSCC (1) /* set condition codes on result */ #ifdef NEED_UI_LOOP_HOOK /* How often to run the ui_loop update, when in use. */ #define UI_LOOP_POLL_INTERVAL 0x32000 /* Counter for the ui_loop_hook update. */ static int ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; /* Actual hook to call to run through gdb's gui event loop. */ extern int (*ui_loop_hook) (int); #endif /* NEED_UI_LOOP_HOOK */ extern int stop_simulator; /* Short-hand macros for LDR/STR. */ /* Store post decrement writeback. */ #define SHDOWNWB() \ lhs = LHS ; \ if (StoreHalfWord (state, instr, lhs)) \ LSBase = lhs - GetLS7RHS (state, instr); /* Store post increment writeback. */ #define SHUPWB() \ lhs = LHS ; \ if (StoreHalfWord (state, instr, lhs)) \ LSBase = lhs + GetLS7RHS (state, instr); /* Store pre decrement. */ #define SHPREDOWN() \ (void)StoreHalfWord (state, instr, LHS - GetLS7RHS (state, instr)); /* Store pre decrement writeback. */ #define SHPREDOWNWB() \ temp = LHS - GetLS7RHS (state, instr); \ if (StoreHalfWord (state, instr, temp)) \ LSBase = temp; /* Store pre increment. */ #define SHPREUP() \ (void)StoreHalfWord (state, instr, LHS + GetLS7RHS (state, instr)); /* Store pre increment writeback. */ #define SHPREUPWB() \ temp = LHS + GetLS7RHS (state, instr); \ if (StoreHalfWord (state, instr, temp)) \ LSBase = temp; /* Load post decrement writeback. */ #define LHPOSTDOWN() \ { \ int done = 1; \ lhs = LHS; \ temp = lhs - GetLS7RHS (state, instr); \ \ switch (BITS (5, 6)) \ { \ case 1: /* H */ \ if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ LSBase = temp; \ break; \ case 2: /* SB */ \ if (LoadByte (state, instr, lhs, LSIGNED)) \ LSBase = temp; \ break; \ case 3: /* SH */ \ if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ LSBase = temp; \ break; \ case 0: /* SWP handled elsewhere. */ \ default: \ done = 0; \ break; \ } \ if (done) \ break; \ } /* Load post increment writeback. */ #define LHPOSTUP() \ { \ int done = 1; \ lhs = LHS; \ temp = lhs + GetLS7RHS (state, instr); \ \ switch (BITS (5, 6)) \ { \ case 1: /* H */ \ if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ LSBase = temp; \ break; \ case 2: /* SB */ \ if (LoadByte (state, instr, lhs, LSIGNED)) \ LSBase = temp; \ break; \ case 3: /* SH */ \ if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ LSBase = temp; \ break; \ case 0: /* SWP handled elsewhere. */ \ default: \ done = 0; \ break; \ } \ if (done) \ break; \ } /* Load pre decrement. */ #define LHPREDOWN() \ { \ int done = 1; \ \ temp = LHS - GetLS7RHS (state, instr); \ switch (BITS (5, 6)) \ { \ case 1: /* H */ \ (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ break; \ case 2: /* SB */ \ (void) LoadByte (state, instr, temp, LSIGNED); \ break; \ case 3: /* SH */ \ (void) LoadHalfWord (state, instr, temp, LSIGNED); \ break; \ case 0: \ /* SWP handled elsewhere. */ \ default: \ done = 0; \ break; \ } \ if (done) \ break; \ } /* Load pre decrement writeback. */ #define LHPREDOWNWB() \ { \ int done = 1; \ \ temp = LHS - GetLS7RHS (state, instr); \ switch (BITS (5, 6)) \ { \ case 1: /* H */ \ if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ LSBase = temp; \ break; \ case 2: /* SB */ \ if (LoadByte (state, instr, temp, LSIGNED)) \ LSBase = temp; \ break; \ case 3: /* SH */ \ if (LoadHalfWord (state, instr, temp, LSIGNED)) \ LSBase = temp; \ break; \ case 0: \ /* SWP handled elsewhere. */ \ default: \ done = 0; \ break; \ } \ if (done) \ break; \ } /* Load pre increment. */ #define LHPREUP() \ { \ int done = 1; \ \ temp = LHS + GetLS7RHS (state, instr); \ switch (BITS (5, 6)) \ { \ case 1: /* H */ \ (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ break; \ case 2: /* SB */ \ (void) LoadByte (state, instr, temp, LSIGNED); \ break; \ case 3: /* SH */ \ (void) LoadHalfWord (state, instr, temp, LSIGNED); \ break; \ case 0: \ /* SWP handled elsewhere. */ \ default: \ done = 0; \ break; \ } \ if (done) \ break; \ } /* Load pre increment writeback. */ #define LHPREUPWB() \ { \ int done = 1; \ \ temp = LHS + GetLS7RHS (state, instr); \ switch (BITS (5, 6)) \ { \ case 1: /* H */ \ if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ LSBase = temp; \ break; \ case 2: /* SB */ \ if (LoadByte (state, instr, temp, LSIGNED)) \ LSBase = temp; \ break; \ case 3: /* SH */ \ if (LoadHalfWord (state, instr, temp, LSIGNED)) \ LSBase = temp; \ break; \ case 0: \ /* SWP handled elsewhere. */ \ default: \ done = 0; \ break; \ } \ if (done) \ break; \ } /*ywc 2005-03-31*/ //teawater add for arm2x86 2005.02.17------------------------------------------- #ifdef DBCT #include "dbct/tb.h" #include "dbct/arm2x86_self.h" #endif //AJ2D-------------------------------------------------------------------------- /* EMULATION of ARM6. */ /* The PC pipeline value depends on whether ARM or Thumb instructions are being executed. */ ARMword isize; extern int debugmode; #ifdef MODE32 //chy 2006-04-12, for ICE debug int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr) { int i; if(debugmode){ if (instr == ARMul_ABORTWORD) return 0; for (i=0;i<skyeye_ice.num_bps;i++){ if(skyeye_ice.bps[i] == addr){ //for test //printf("SKYEYE: ICE_debug bps [%d]== 0x%x\n", i,addr); state->EndCondition = 0; state->Emulate = STOP; return 1; } } if (skyeye_ice.tps_status==TRACE_STARTED) { for (i=0;i<skyeye_ice.num_tps;i++) { if (((skyeye_ice.tps[i].tp_address==addr)&&(skyeye_ice.tps[i].status==TRACEPOINT_ENABLED))||(skyeye_ice.tps[i].status==TRACEPOINT_STEPPING)) { handle_tracepoint(i); } } } } return 0; } /* void chy_debug() { printf("SkyEye chy_deubeg begin\n"); } */ ARMword ARMul_Emulate32 (ARMul_State * state) #else ARMword ARMul_Emulate26 (ARMul_State * state) #endif { ARMword instr; /* The current instruction. */ ARMword dest = 0; /* Almost the DestBus. */ ARMword temp; /* Ubiquitous third hand. */ ARMword pc = 0; /* The address of the current instruction. */ ARMword lhs; /* Almost the ABus and BBus. */ ARMword rhs; ARMword decoded = 0; /* Instruction pipeline. */ ARMword loaded = 0; ARMword decoded_addr=0; ARMword loaded_addr=0; ARMword have_bp=0; static unsigned remote_interrupt_test_time=0; /* Execute the next instruction. */ if (state->NextInstr < PRIMEPIPE) { decoded = state->decoded; loaded = state->loaded; pc = state->pc; //chy 2006-04-12, for ICE debug decoded_addr=state->decoded_addr; loaded_addr=state->loaded_addr; } do { /* Just keep going. */ isize = INSN_SIZE; switch (state->NextInstr) { case SEQ: /* Advance the pipeline, and an S cycle. */ state->Reg[15] += isize; pc += isize; instr = decoded; //chy 2006-04-12, for ICE debug have_bp=ARMul_ICE_debug(state,instr,decoded_addr); decoded = loaded; decoded_addr=loaded_addr; loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize); loaded_addr=pc + (isize * 2); if(have_bp) goto TEST_EMULATE; break; case NONSEQ: /* Advance the pipeline, and an N cycle. */ state->Reg[15] += isize; pc += isize; instr = decoded; //chy 2006-04-12, for ICE debug have_bp=ARMul_ICE_debug(state,instr,decoded_addr); decoded = loaded; decoded_addr=loaded_addr; loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize); loaded_addr=pc + (isize * 2); NORMALCYCLE; if(have_bp) goto TEST_EMULATE; break; case PCINCEDSEQ: /* Program counter advanced, and an S cycle. */ pc += isize; instr = decoded; //chy 2006-04-12, for ICE debug have_bp=ARMul_ICE_debug(state,instr,decoded_addr); decoded = loaded; decoded_addr=loaded_addr; loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize); loaded_addr=pc + (isize * 2); NORMALCYCLE; if(have_bp) goto TEST_EMULATE; break; case PCINCEDNONSEQ: /* Program counter advanced, and an N cycle. */ pc += isize; instr = decoded; //chy 2006-04-12, for ICE debug have_bp=ARMul_ICE_debug(state,instr,decoded_addr); decoded = loaded; decoded_addr=loaded_addr; loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize); loaded_addr=pc + (isize * 2); NORMALCYCLE; if(have_bp) goto TEST_EMULATE; break; case RESUME: /* The program counter has been changed. */ pc = state->Reg[15]; #ifndef MODE32 pc = pc & R15PCBITS; #endif state->Reg[15] = pc + (isize * 2); state->Aborted = 0; //chy 2004-05-25, fix bug provided by Carl van Schaik<cvansch@cse.unsw.EDU.AU> state->AbortAddr = 1; instr = ARMul_ReLoadInstr (state, pc, isize); //chy 2006-04-12, for ICE debug have_bp=ARMul_ICE_debug(state,instr,pc); decoded = ARMul_ReLoadInstr (state, pc + isize, isize); decoded_addr=pc+isize; loaded = ARMul_ReLoadInstr (state, pc + isize * 2, isize); loaded_addr=pc + isize * 2; NORMALCYCLE; if(have_bp) goto TEST_EMULATE; break; default: /* The program counter has been changed. */ pc = state->Reg[15]; #ifndef MODE32 pc = pc & R15PCBITS; #endif state->Reg[15] = pc + (isize * 2); state->Aborted = 0; //chy 2004-05-25, fix bug provided by Carl van Schaik<cvansch@cse.unsw.EDU.AU> state->AbortAddr = 1; instr = ARMul_LoadInstrN (state, pc, isize); //chy 2006-04-12, for ICE debug have_bp=ARMul_ICE_debug(state,instr,pc); decoded = ARMul_LoadInstrS (state, pc + (isize), isize); decoded_addr=pc+isize; loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize); loaded_addr=pc + isize * 2; NORMALCYCLE; if(have_bp) goto TEST_EMULATE; break; } if (state->EventSet) ARMul_EnvokeEvent (state); /* do profiling for code coverage */ if (skyeye_config.code_cov.prof_on) cov_prof(EXEC_FLAG, pc); //2003-07-11 chy: for test if (skyeye_config.log.logon >= 1) { if (state->NumInstrs >= skyeye_config.log.start && state->NumInstrs <= skyeye_config.log.end) { static int mybegin = 0; static int myinstrnum = 0; if (mybegin == 0) mybegin = 1; #if 0 if (state->NumInstrs == 3695) { printf ("***********SKYEYE: numinstr = 3695\n"); } static int mybeg2 = 0; static int mybeg3 = 0; static int mybeg4 = 0; static int mybeg5 = 0; if (pc == 0xa0008000) { //mybegin=1; printf ("************SKYEYE: real vmlinux begin now numinstr is %llu ****************\n", state->NumInstrs); } //chy 2003-09-02 test fiq if (state->NumInstrs == 67347000) { printf ("***********SKYEYE: numinstr = 67347000, begin log\n"); mybegin = 1; } if (pc == 0xc00087b4) { //numinstr=67348714 mybegin = 1; printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs); } if (pc == 0xc00087b8) { //in start_kernel::sti() mybeg4 = 1; printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs); } //if(pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr if (pc == 0xc001e500) { //MRA instr mybeg5 = 1; printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs); } if (pc >= 0xc0000000 && mybeg2 == 0) { mybeg2 = 1; printf ("************SKYEYE: enable mmu&cache, now numinstr is %llu **************\n", state->NumInstrs); SKYEYE_OUTREGS (stderr); printf ("************************************************************************\n"); } //chy 2003-09-01 test after tlb-flush if (pc == 0xc00261ac) { //sleep(2); mybeg3 = 1; printf ("************SKYEYE: after tlb-flush numinstr is %llu ****************\n", state->NumInstrs); } if (mybeg3 == 1) { SKYEYE_OUTREGS (skyeye_logfd); SKYEYE_OUTMOREREGS (skyeye_logfd); fprintf (skyeye_logfd, "\n"); } #endif if (mybegin == 1) { //fprintf(skyeye_logfd,"p %x,i %x,d %x,l %x,",pc,instr,decoded,loaded); //chy for test 20050729 /*if(state->NumInstrs>=3302294) { if(pc==0x100c9d4 && instr==0xe1b0f00e){ chy_debug(); printf("*********************************************\n"); printf("******SKYEYE N %llx :p %x,i %x\n SKYEYE******\n",state->NumInstrs,pc,instr); printf("*********************************************\n"); } */ if (skyeye_config.log.logon >= 1) fprintf (skyeye_logfd, "N %llx :p %x,i %x,", state->NumInstrs, pc, #ifdef MODET TFLAG ? instr & 0xffff : instr #else instr #endif ); if (skyeye_config.log.logon >= 2) SKYEYE_OUTREGS (skyeye_logfd); if (skyeye_config.log.logon >= 3) SKYEYE_OUTMOREREGS (skyeye_logfd); fprintf (skyeye_logfd, "\n"); if (skyeye_config.log.length > 0) { myinstrnum++; if (myinstrnum >= skyeye_config.log. length) { myinstrnum = 0; fflush (skyeye_logfd); fseek (skyeye_logfd, 0L, SEEK_SET); } } } //SKYEYE_OUTREGS(skyeye_logfd); //SKYEYE_OUTMOREREGS(skyeye_logfd); } } #if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); if (instr == 0) abort (); #endif #if 0 /* Enable this code to help track down stack alignment bugs. */ { static ARMword old_sp = -1; if (old_sp != state->Reg[13]) { old_sp = state->Reg[13]; fprintf (stderr, "pc: %08x: SP set to %08x%s\n", pc & ~1, old_sp, (old_sp % 8) ? " [UNALIGNED!]" : ""); } } #endif /* Any exceptions ? */ if (state->NresetSig == LOW) { ARMul_Abort (state, ARMul_ResetV); /*added energy_prof statement by ksh in 2004-11-26 */ //chy 2005-07-28 for standalone //ARMul_do_energy(state,instr,pc); break; } else if (!state->NfiqSig && !FFLAG) { ARMul_Abort (state, ARMul_FIQV); /*added energy_prof statement by ksh in 2004-11-26 */ //chy 2005-07-28 for standalone //ARMul_do_energy(state,instr,pc); break; } else if (!state->NirqSig && !IFLAG) { ARMul_Abort (state, ARMul_IRQV); /*added energy_prof statement by ksh in 2004-11-26 */ //chy 2005-07-28 for standalone //ARMul_do_energy(state,instr,pc); break; } //teawater add for arm2x86 2005.04.26------------------------------------------- if (state->tea_pc) { int i; if (state->tea_reg_fd) { fprintf (state->tea_reg_fd, "\n"); for (i = 0; i < 15; i++) { fprintf (state->tea_reg_fd, "%x,", state->Reg[i]); } fprintf (state->tea_reg_fd, "%x,", pc); state->Cpsr = ARMul_GetCPSR (state); fprintf (state->tea_reg_fd, "%x\n", state->Cpsr); } else { printf ("\n"); for (i = 0; i < 15; i++) { printf ("%x,", state->Reg[i]); } printf ("%x,", pc); state->Cpsr = ARMul_GetCPSR (state); printf ("%x\n", state->Cpsr); } } //AJ2D-------------------------------------------------------------------------- if (state->CallDebug > 0) { instr = ARMul_Debug (state, pc, instr); if (state->Emulate < ONCE) { state->NextInstr = RESUME; break; } if (state->Debug) { fprintf (stderr, "sim: At %08lx Instr %08lx Mode %02lx\n", pc, instr, state->Mode); (void) fgetc (stdin); } } else if (state->Emulate < ONCE) { state->NextInstr = RESUME; break; } io_do_cycle (state); state->NumInstrs++; #ifdef MODET /* Provide Thumb instruction decoding. If the processor is in Thumb mode, then we can simply decode the Thumb instruction, and map it to the corresponding ARM instruction (by directly loading the instr variable, and letting the normal ARM simulator execute). There are some caveats to ensure that the correct pipelined PC value is used when executing Thumb code, and also for dealing with the BL instruction. */ if (TFLAG) { ARMword new; /* Check if in Thumb mode. */ switch (ARMul_ThumbDecode (state, pc, instr, &new)) { case t_undefined: /* This is a Thumb instruction. */ ARMul_UndefInstr (state, instr); goto donext; case t_branch: /* Already processed. */ goto donext; case t_decoded: /* ARM instruction available. */ //printf("t decode %04lx -> %08lx\n", instr & 0xffff, new); instr = new; /* So continue instruction decoding. */ break; default: break; } } #endif /* Check the condition codes. */ if ((temp = TOPBITS (28)) == AL) /* Vile deed in the need for speed. */ goto mainswitch; /* Check the condition code. */ switch ((int) TOPBITS (28)) { case AL: temp = TRUE; break; case NV: if (state->is_v5) { if (BITS (25, 27) == 5) { /* BLX(1) */ ARMword dest; state->Reg[14] = pc + 4; /* Force entry into Thumb mode. */ dest = pc + 8 + 1; if (BIT (23)) dest += (NEGBRANCH + (BIT (24) << 1)); else dest += POSBRANCH + (BIT (24) << 1); WriteR15Branch (state, dest); goto donext; } else if ((instr & 0xFC70F000) == 0xF450F000) /* The PLD instruction. Ignored. */ goto donext; else if (((instr & 0xfe500f00) == 0xfc100100) || ((instr & 0xfe500f00) == 0xfc000100)) /* wldrw and wstrw are unconditional. */ goto mainswitch; else /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */ ARMul_UndefInstr (state, instr); } temp = FALSE; break; case EQ: temp = ZFLAG; break; case NE: temp = !ZFLAG; break; case VS: temp = VFLAG; break; case VC: temp = !VFLAG; break; case MI: temp = NFLAG; break; case PL: temp = !NFLAG; break; case CS: temp = CFLAG; break; case CC: temp = !CFLAG; break; case HI: temp = (CFLAG && !ZFLAG); break; case LS: temp = (!CFLAG || ZFLAG); break; case GE: temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); break; case LT: temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); break; case GT: temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG)); break; case LE: temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG; break; } /* cc check */ //chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it... #if 0 /* Handle the Clock counter here. */ if (state->is_XScale) { ARMword cp14r0; int ok; ok = state->CPRead[14] (state, 0, &cp14r0); if (ok && (cp14r0 & ARMul_CP14_R0_ENABLE)) { unsigned int newcycles, nowtime = ARMul_Time (state); newcycles = nowtime - state->LastTime; state->LastTime = nowtime; if (cp14r0 & ARMul_CP14_R0_CCD) { if (state->CP14R0_CCD == -1) state->CP14R0_CCD = newcycles; else state->CP14R0_CCD += newcycles; if (state->CP14R0_CCD >= 64) { newcycles = 0; while (state->CP14R0_CCD >= 64) state->CP14R0_CCD -= 64, newcycles++; goto check_PMUintr; } } else { ARMword cp14r1; int do_int = 0; state->CP14R0_CCD = -1; check_PMUintr: cp14r0 |= ARMul_CP14_R0_FLAG2; (void) state->CPWrite[14] (state, 0, cp14r0); ok = state->CPRead[14] (state, 1, &cp14r1); /* Coded like this for portability. */ while (ok && newcycles) { if (cp14r1 == 0xffffffff) { cp14r1 = 0; do_int = 1; } else cp14r1++; newcycles--; } (void) state->CPWrite[14] (state, 1, cp14r1); if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2)) { ARMword temp; if (state-> CPRead[13] (state, 8, &temp) && (temp & ARMul_CP13_R8_PMUS)) ARMul_Abort (state, ARMul_FIQV); else ARMul_Abort (state, ARMul_IRQV); } } } } /* Handle hardware instructions breakpoints here. */ if (state->is_XScale) { if ((pc | 3) == (read_cp15_reg (14, 0, 8) | 2) || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2)) { if (XScale_debug_moe (state, ARMul_CP14_R10_MOE_IB)) ARMul_OSHandleSWI (state, SWI_Breakpoint); } } #endif /* Actual execution of instructions begins here. */ /* If the condition codes don't match, stop here. */ if (temp) { mainswitch: if (state->is_XScale) { if (BIT (20) == 0 && BITS (25, 27) == 0) { if (BITS (4, 7) == 0xD) { /* XScale Load Consecutive insn. */ ARMword temp = GetLS7RHS (state, instr); ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; ARMword addr = BIT (24) ? temp2 : LHS; if (BIT (12)) ARMul_UndefInstr (state, instr); else if (addr & 7) /* Alignment violation. */ ARMul_Abort (state, ARMul_DataAbortV); else { int wb = BIT (21) || (!BIT (24)); state->Reg[BITS (12, 15)] = ARMul_LoadWordN (state, addr); state->Reg[BITS (12, 15) + 1] = ARMul_LoadWordN (state, addr + 4); if (wb) LSBase = temp2; } goto donext; } else if (BITS (4, 7) == 0xF) { /* XScale Store Consecutive insn. */ ARMword temp = GetLS7RHS (state, instr); ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; ARMword addr = BIT (24) ? temp2 : LHS; if (BIT (12)) ARMul_UndefInstr (state, instr); else if (addr & 7) /* Alignment violation. */ ARMul_Abort (state, ARMul_DataAbortV); else { ARMul_StoreWordN (state, addr, state-> Reg[BITS (12, 15)]); ARMul_StoreWordN (state, addr + 4, state-> Reg[BITS (12, 15) + 1]); if (BIT (21) || !BIT (24)) LSBase = temp2; } goto donext; } } //chy 2003-09-03 TMRRC(iwmmxt.c) and MRA has the same decoded instr???? //Now, I commit iwmmxt process, may be future, I will change it!!!! //if (ARMul_HandleIwmmxt (state, instr)) // goto donext; } switch ((int) BITS (20, 27)) { /* Data Processing Register RHS Instructions. */ case 0x00: /* AND reg and MUL */ #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, no write-back, down, post indexed. */ SHDOWNWB (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif if (BITS (4, 7) == 9) { /* MUL */ rhs = state->Reg[MULRHSReg]; if (MULLHSReg == MULDESTReg) { UNDEF_MULDestEQOp1; state->Reg[MULDESTReg] = 0; } else if (MULDESTReg != 15) state->Reg[MULDESTReg] = state-> Reg[MULLHSReg] * rhs; else UNDEF_MULPCDest; for (dest = 0, temp = 0; dest < 32; dest++) if (rhs & (1L << dest)) temp = dest; /* Mult takes this many/2 I cycles. */ ARMul_Icycles (state, ARMul_MultTable[temp], 0L); } else { /* AND reg. */ rhs = DPRegRHS; dest = LHS & rhs; WRITEDEST (dest); } break; case 0x01: /* ANDS reg and MULS */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, no write-back, down, post indexed. */ LHPOSTDOWN (); /* Fall through to rest of decoding. */ #endif if (BITS (4, 7) == 9) { /* MULS */ rhs = state->Reg[MULRHSReg]; if (MULLHSReg == MULDESTReg) { UNDEF_MULDestEQOp1; state->Reg[MULDESTReg] = 0; CLEARN; SETZ; } else if (MULDESTReg != 15) { dest = state->Reg[MULLHSReg] * rhs; ARMul_NegZero (state, dest); state->Reg[MULDESTReg] = dest; } else UNDEF_MULPCDest; for (dest = 0, temp = 0; dest < 32; dest++) if (rhs & (1L << dest)) temp = dest; /* Mult takes this many/2 I cycles. */ ARMul_Icycles (state, ARMul_MultTable[temp], 0L); } else { /* ANDS reg. */ rhs = DPSRegRHS; dest = LHS & rhs; WRITESDEST (dest); } break; case 0x02: /* EOR reg and MLA */ #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, write-back, down, post indexed. */ SHDOWNWB (); break; } #endif if (BITS (4, 7) == 9) { /* MLA */ rhs = state->Reg[MULRHSReg]; if (MULLHSReg == MULDESTReg) { UNDEF_MULDestEQOp1; state->Reg[MULDESTReg] = state->Reg[MULACCReg]; } else if (MULDESTReg != 15) state->Reg[MULDESTReg] = state-> Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; else UNDEF_MULPCDest; for (dest = 0, temp = 0; dest < 32; dest++) if (rhs & (1L << dest)) temp = dest; /* Mult takes this many/2 I cycles. */ ARMul_Icycles (state, ARMul_MultTable[temp], 0L); } else { rhs = DPRegRHS; dest = LHS ^ rhs; WRITEDEST (dest); } break; case 0x03: /* EORS reg and MLAS */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, write-back, down, post-indexed. */ LHPOSTDOWN (); /* Fall through to rest of the decoding. */ #endif if (BITS (4, 7) == 9) { /* MLAS */ rhs = state->Reg[MULRHSReg]; if (MULLHSReg == MULDESTReg) { UNDEF_MULDestEQOp1; dest = state->Reg[MULACCReg]; ARMul_NegZero (state, dest); state->Reg[MULDESTReg] = dest; } else if (MULDESTReg != 15) { dest = state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; ARMul_NegZero (state, dest); state->Reg[MULDESTReg] = dest; } else UNDEF_MULPCDest; for (dest = 0, temp = 0; dest < 32; dest++) if (rhs & (1L << dest)) temp = dest; /* Mult takes this many/2 I cycles. */ ARMul_Icycles (state, ARMul_MultTable[temp], 0L); } else { /* EORS Reg. */ rhs = DPSRegRHS; dest = LHS ^ rhs; WRITESDEST (dest); } break; case 0x04: /* SUB reg */ #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, no write-back, down, post indexed. */ SHDOWNWB (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif rhs = DPRegRHS; dest = LHS - rhs; WRITEDEST (dest); break; case 0x05: /* SUBS reg */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, no write-back, down, post indexed. */ LHPOSTDOWN (); /* Fall through to the rest of the instruction decoding. */ #endif lhs = LHS; rhs = DPRegRHS; dest = lhs - rhs; if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, lhs, rhs, dest); ARMul_SubOverflow (state, lhs, rhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x06: /* RSB reg */ #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, write-back, down, post indexed. */ SHDOWNWB (); break; } #endif rhs = DPRegRHS; dest = rhs - LHS; WRITEDEST (dest); break; case 0x07: /* RSBS reg */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, write-back, down, post indexed. */ LHPOSTDOWN (); /* Fall through to remainder of instruction decoding. */ #endif lhs = LHS; rhs = DPRegRHS; dest = rhs - lhs; if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, rhs, lhs, dest); ARMul_SubOverflow (state, rhs, lhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x08: /* ADD reg */ #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, no write-back, up, post indexed. */ SHUPWB (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif #ifdef MODET if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32 = 64 */ ARMul_Icycles (state, Multiply64 (state, instr, LUNSIGNED, LDEFAULT), 0L); break; } #endif rhs = DPRegRHS; dest = LHS + rhs; WRITEDEST (dest); break; case 0x09: /* ADDS reg */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, no write-back, up, post indexed. */ LHPOSTUP (); /* Fall through to remaining instruction decoding. */ #endif #ifdef MODET if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32=64 */ ARMul_Icycles (state, Multiply64 (state, instr, LUNSIGNED, LSCC), 0L); break; } #endif lhs = LHS; rhs = DPRegRHS; dest = lhs + rhs; ASSIGNZ (dest == 0); if ((lhs | rhs) >> 30) { /* Possible C,V,N to set. */ ASSIGNN (NEG (dest)); ARMul_AddCarry (state, lhs, rhs, dest); ARMul_AddOverflow (state, lhs, rhs, dest); } else { CLEARN; CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x0a: /* ADC reg */ #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, write-back, up, post-indexed. */ SHUPWB (); break; } if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32=64 */ ARMul_Icycles (state, MultiplyAdd64 (state, instr, LUNSIGNED, LDEFAULT), 0L); break; } #endif rhs = DPRegRHS; dest = LHS + rhs + CFLAG; WRITEDEST (dest); break; case 0x0b: /* ADCS reg */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, write-back, up, post indexed. */ LHPOSTUP (); /* Fall through to remaining instruction decoding. */ if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32=64 */ ARMul_Icycles (state, MultiplyAdd64 (state, instr, LUNSIGNED, LSCC), 0L); break; } #endif lhs = LHS; rhs = DPRegRHS; dest = lhs + rhs + CFLAG; ASSIGNZ (dest == 0); if ((lhs | rhs) >> 30) { /* Possible C,V,N to set. */ ASSIGNN (NEG (dest)); ARMul_AddCarry (state, lhs, rhs, dest); ARMul_AddOverflow (state, lhs, rhs, dest); } else { CLEARN; CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x0c: /* SBC reg */ #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, no write-back, up post indexed. */ SHUPWB (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32=64 */ ARMul_Icycles (state, Multiply64 (state, instr, LSIGNED, LDEFAULT), 0L); break; } #endif rhs = DPRegRHS; dest = LHS - rhs - !CFLAG; WRITEDEST (dest); break; case 0x0d: /* SBCS reg */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, no write-back, up, post indexed. */ LHPOSTUP (); if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32=64 */ ARMul_Icycles (state, Multiply64 (state, instr, LSIGNED, LSCC), 0L); break; } #endif lhs = LHS; rhs = DPRegRHS; dest = lhs - rhs - !CFLAG; if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, lhs, rhs, dest); ARMul_SubOverflow (state, lhs, rhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x0e: /* RSC reg */ #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, write-back, up, post indexed. */ SHUPWB (); break; } if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32=64 */ ARMul_Icycles (state, MultiplyAdd64 (state, instr, LSIGNED, LDEFAULT), 0L); break; } #endif rhs = DPRegRHS; dest = rhs - LHS - !CFLAG; WRITEDEST (dest); break; case 0x0f: /* RSCS reg */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, write-back, up, post indexed. */ LHPOSTUP (); /* Fall through to remaining instruction decoding. */ if (BITS (4, 7) == 0x9) { /* MULL */ /* 32x32=64 */ ARMul_Icycles (state, MultiplyAdd64 (state, instr, LSIGNED, LSCC), 0L); break; } #endif lhs = LHS; rhs = DPRegRHS; dest = rhs - lhs - !CFLAG; if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, rhs, lhs, dest); ARMul_SubOverflow (state, rhs, lhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x10: /* TST reg and MRS CPSR and SWP word. */ if (state->is_v5e) { if (BIT (4) == 0 && BIT (7) == 1) { /* ElSegundo SMLAxy insn. */ ARMword op1 = state-> Reg[BITS (0, 3)]; ARMword op2 = state-> Reg[BITS (8, 11)]; ARMword Rn = state-> Reg[BITS (12, 15)]; if (BIT (5)) op1 >>= 16; if (BIT (6)) op2 >>= 16; op1 &= 0xFFFF; op2 &= 0xFFFF; if (op1 & 0x8000) op1 -= 65536; if (op2 & 0x8000) op2 -= 65536; op1 *= op2; if (AddOverflow (op1, Rn, op1 + Rn)) SETS; state->Reg[BITS (16, 19)] = op1 + Rn; break; } if (BITS (4, 11) == 5) { /* ElSegundo QADD insn. */ ARMword op1 = state-> Reg[BITS (0, 3)]; ARMword op2 = state-> Reg[BITS (16, 19)]; ARMword result = op1 + op2; if (AddOverflow (op1, op2, result)) { result = POS (result) ? 0x80000000 : 0x7fffffff; SETS; } state->Reg[BITS (12, 15)] = result; break; } } #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, no write-back, down, pre indexed. */ SHPREDOWN (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif if (BITS (4, 11) == 9) { /* SWP */ UNDEF_SWPPC; temp = LHS; BUSUSEDINCPCS; #ifndef MODE32 if (VECTORACCESS (temp) || ADDREXCEPT (temp)) { INTERNALABORT (temp); (void) ARMul_LoadWordN (state, temp); (void) ARMul_LoadWordN (state, temp); } else #endif dest = ARMul_SwapWord (state, temp, state-> Reg [RHSReg]); if (temp & 3) DEST = ARMul_Align (state, temp, dest); else DEST = dest; if (state->abortSig || state->Aborted) TAKEABORT; } else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */ UNDEF_MRSPC; DEST = ECC | EINT | EMODE; } else { UNDEF_Test; } break; case 0x11: /* TSTP reg */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, no write-back, down, pre indexed. */ LHPREDOWN (); /* Continue with remaining instruction decode. */ #endif if (DESTReg == 15) { /* TSTP reg */ #ifdef MODE32 //chy 2006-02-15 if in user mode, can not set cpsr 0:23 //from p165 of ARMARM book state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else rhs = DPRegRHS; temp = LHS & rhs; SETR15PSR (temp); #endif } else { /* TST reg */ rhs = DPSRegRHS; dest = LHS & rhs; ARMul_NegZero (state, dest); } break; case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */ if (state->is_v5) { if (BITS (4, 7) == 3) { /* BLX(2) */ ARMword temp; if (TFLAG) temp = (pc + 2) | 1; else temp = pc + 4; WriteR15Branch (state, state-> Reg[RHSReg]); state->Reg[14] = temp; break; } } if (state->is_v5e) { if (BIT (4) == 0 && BIT (7) == 1 && (BIT (5) == 0 || BITS (12, 15) == 0)) { /* ElSegundo SMLAWy/SMULWy insn. */ unsigned long long op1 = state-> Reg[BITS (0, 3)]; unsigned long long op2 = state-> Reg[BITS (8, 11)]; unsigned long long result; if (BIT (6)) op2 >>= 16; if (op1 & 0x80000000) op1 -= 1ULL << 32; op2 &= 0xFFFF; if (op2 & 0x8000) op2 -= 65536; result = (op1 * op2) >> 16; if (BIT (5) == 0) { ARMword Rn = state-> Reg[BITS (12, 15)]; if (AddOverflow (result, Rn, result + Rn)) SETS; result += Rn; } state->Reg[BITS (16, 19)] = result; break; } if (BITS (4, 11) == 5) { /* ElSegundo QSUB insn. */ ARMword op1 = state-> Reg[BITS (0, 3)]; ARMword op2 = state-> Reg[BITS (16, 19)]; ARMword result = op1 - op2; if (SubOverflow (op1, op2, result)) { result = POS (result) ? 0x80000000 : 0x7fffffff; SETS; } state->Reg[BITS (12, 15)] = result; break; } } #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, write-back, down, pre indexed. */ SHPREDOWNWB (); break; } if (BITS (4, 27) == 0x12FFF1) { /* BX */ WriteR15Branch (state, state->Reg[RHSReg]); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif if (state->is_v5) { if (BITS (4, 7) == 0x7) { ARMword value; extern int SWI_vector_installed; /* Hardware is allowed to optionally override this instruction and treat it as a breakpoint. Since this is a simulator not hardware, we take the position that if a SWI vector was not installed, then an Abort vector was probably not installed either, and so normally this instruction would be ignored, even if an Abort is generated. This is a bad thing, since GDB uses this instruction for its breakpoints (at least in Thumb mode it does). So intercept the instruction here and generate a breakpoint SWI instead. */ if (!SWI_vector_installed) ARMul_OSHandleSWI (state, SWI_Breakpoint); else { /* BKPT - normally this will cause an abort, but on the XScale we must check the DCSR. */ XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc); if (!XScale_debug_moe (state, ARMul_CP14_R10_MOE_BT)) break; } /* Force the next instruction to be refetched. */ state->NextInstr = RESUME; break; } } if (DESTReg == 15) { /* MSR reg to CPSR. */ UNDEF_MSRPC; temp = DPRegRHS; #ifdef MODET /* Don't allow TBIT to be set by MSR. */ temp &= ~TBIT; #endif ARMul_FixCPSR (state, instr, temp); } else UNDEF_Test; break; case 0x13: /* TEQP reg */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, write-back, down, pre indexed. */ LHPREDOWNWB (); /* Continue with remaining instruction decode. */ #endif if (DESTReg == 15) { /* TEQP reg */ #ifdef MODE32 state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else rhs = DPRegRHS; temp = LHS ^ rhs; SETR15PSR (temp); #endif } else { /* TEQ Reg. */ rhs = DPSRegRHS; dest = LHS ^ rhs; ARMul_NegZero (state, dest); } break; case 0x14: /* CMP reg and MRS SPSR and SWP byte. */ if (state->is_v5e) { if (BIT (4) == 0 && BIT (7) == 1) { /* ElSegundo SMLALxy insn. */ unsigned long long op1 = state-> Reg[BITS (0, 3)]; unsigned long long op2 = state-> Reg[BITS (8, 11)]; unsigned long long dest; unsigned long long result; if (BIT (5)) op1 >>= 16; if (BIT (6)) op2 >>= 16; op1 &= 0xFFFF; if (op1 & 0x8000) op1 -= 65536; op2 &= 0xFFFF; if (op2 & 0x8000) op2 -= 65536; dest = (unsigned long long) state-> Reg[BITS (16, 19)] << 32; dest |= state-> Reg[BITS (12, 15)]; dest += op1 * op2; state->Reg[BITS (12, 15)] = dest; state->Reg[BITS (16, 19)] = dest >> 32; break; } if (BITS (4, 11) == 5) { /* ElSegundo QDADD insn. */ ARMword op1 = state-> Reg[BITS (0, 3)]; ARMword op2 = state-> Reg[BITS (16, 19)]; ARMword op2d = op2 + op2; ARMword result; if (AddOverflow (op2, op2, op2d)) { SETS; op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; } result = op1 + op2d; if (AddOverflow (op1, op2d, result)) { SETS; result = POS (result) ? 0x80000000 : 0x7fffffff; } state->Reg[BITS (12, 15)] = result; break; } } #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, no write-back, down, pre indexed. */ SHPREDOWN (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif if (BITS (4, 11) == 9) { /* SWP */ UNDEF_SWPPC; temp = LHS; BUSUSEDINCPCS; #ifndef MODE32 if (VECTORACCESS (temp) || ADDREXCEPT (temp)) { INTERNALABORT (temp); (void) ARMul_LoadByte (state, temp); (void) ARMul_LoadByte (state, temp); } else #endif DEST = ARMul_SwapByte (state, temp, state-> Reg [RHSReg]); if (state->abortSig || state->Aborted) TAKEABORT; } else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS SPSR */ UNDEF_MRSPC; DEST = GETSPSR (state->Bank); } else UNDEF_Test; break; case 0x15: /* CMPP reg. */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, no write-back, down, pre indexed. */ LHPREDOWN (); /* Continue with remaining instruction decode. */ #endif if (DESTReg == 15) { /* CMPP reg. */ #ifdef MODE32 state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else rhs = DPRegRHS; temp = LHS - rhs; SETR15PSR (temp); #endif } else { /* CMP reg. */ lhs = LHS; rhs = DPRegRHS; dest = lhs - rhs; ARMul_NegZero (state, dest); if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, lhs, rhs, dest); ARMul_SubOverflow (state, lhs, rhs, dest); } else { CLEARC; CLEARV; } } break; case 0x16: /* CMN reg and MSR reg to SPSR */ if (state->is_v5e) { if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0) { /* ElSegundo SMULxy insn. */ ARMword op1 = state-> Reg[BITS (0, 3)]; ARMword op2 = state-> Reg[BITS (8, 11)]; ARMword Rn = state-> Reg[BITS (12, 15)]; if (BIT (5)) op1 >>= 16; if (BIT (6)) op2 >>= 16; op1 &= 0xFFFF; op2 &= 0xFFFF; if (op1 & 0x8000) op1 -= 65536; if (op2 & 0x8000) op2 -= 65536; state->Reg[BITS (16, 19)] = op1 * op2; break; } if (BITS (4, 11) == 5) { /* ElSegundo QDSUB insn. */ ARMword op1 = state-> Reg[BITS (0, 3)]; ARMword op2 = state-> Reg[BITS (16, 19)]; ARMword op2d = op2 + op2; ARMword result; if (AddOverflow (op2, op2, op2d)) { SETS; op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; } result = op1 - op2d; if (SubOverflow (op1, op2d, result)) { SETS; result = POS (result) ? 0x80000000 : 0x7fffffff; } state->Reg[BITS (12, 15)] = result; break; } } if (state->is_v5) { if (BITS (4, 11) == 0xF1 && BITS (16, 19) == 0xF) { /* ARM5 CLZ insn. */ ARMword op1 = state-> Reg[BITS (0, 3)]; int result = 32; if (op1) for (result = 0; (op1 & 0x80000000) == 0; op1 <<= 1) result++; state->Reg[BITS (12, 15)] = result; break; } } #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, write-back, down, pre indexed. */ SHPREDOWNWB (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif if (DESTReg == 15) { /* MSR */ UNDEF_MSRPC; ARMul_FixSPSR (state, instr, DPRegRHS); } else { UNDEF_Test; } break; case 0x17: /* CMNP reg */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, write-back, down, pre indexed. */ LHPREDOWNWB (); /* Continue with remaining instruction decoding. */ #endif if (DESTReg == 15) { #ifdef MODE32 state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else rhs = DPRegRHS; temp = LHS + rhs; SETR15PSR (temp); #endif break; } else { /* CMN reg. */ lhs = LHS; rhs = DPRegRHS; dest = lhs + rhs; ASSIGNZ (dest == 0); if ((lhs | rhs) >> 30) { /* Possible C,V,N to set. */ ASSIGNN (NEG (dest)); ARMul_AddCarry (state, lhs, rhs, dest); ARMul_AddOverflow (state, lhs, rhs, dest); } else { CLEARN; CLEARC; CLEARV; } } break; case 0x18: /* ORR reg */ #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, no write-back, up, pre indexed. */ SHPREUP (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif rhs = DPRegRHS; dest = LHS | rhs; WRITEDEST (dest); break; case 0x19: /* ORRS reg */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, no write-back, up, pre indexed. */ LHPREUP (); /* Continue with remaining instruction decoding. */ #endif rhs = DPSRegRHS; dest = LHS | rhs; WRITESDEST (dest); break; case 0x1a: /* MOV reg */ #ifdef MODET if (BITS (4, 11) == 0xB) { /* STRH register offset, write-back, up, pre indexed. */ SHPREUPWB (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif dest = DPRegRHS; WRITEDEST (dest); break; case 0x1b: /* MOVS reg */ #ifdef MODET if ((BITS (4, 11) & 0xF9) == 0x9) /* LDR register offset, write-back, up, pre indexed. */ LHPREUPWB (); /* Continue with remaining instruction decoding. */ #endif dest = DPSRegRHS; WRITESDEST (dest); break; case 0x1c: /* BIC reg */ #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, no write-back, up, pre indexed. */ SHPREUP (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } else if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif rhs = DPRegRHS; dest = LHS & ~rhs; WRITEDEST (dest); break; case 0x1d: /* BICS reg */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, no write-back, up, pre indexed. */ LHPREUP (); /* Continue with instruction decoding. */ #endif rhs = DPSRegRHS; dest = LHS & ~rhs; WRITESDEST (dest); break; case 0x1e: /* MVN reg */ #ifdef MODET if (BITS (4, 7) == 0xB) { /* STRH immediate offset, write-back, up, pre indexed. */ SHPREUPWB (); break; } if (BITS (4, 7) == 0xD) { Handle_Load_Double (state, instr); break; } if (BITS (4, 7) == 0xF) { Handle_Store_Double (state, instr); break; } #endif dest = ~DPRegRHS; WRITEDEST (dest); break; case 0x1f: /* MVNS reg */ #ifdef MODET if ((BITS (4, 7) & 0x9) == 0x9) /* LDR immediate offset, write-back, up, pre indexed. */ LHPREUPWB (); /* Continue instruction decoding. */ #endif dest = ~DPSRegRHS; WRITESDEST (dest); break; /* Data Processing Immediate RHS Instructions. */ case 0x20: /* AND immed */ dest = LHS & DPImmRHS; WRITEDEST (dest); break; case 0x21: /* ANDS immed */ DPSImmRHS; dest = LHS & rhs; WRITESDEST (dest); break; case 0x22: /* EOR immed */ dest = LHS ^ DPImmRHS; WRITEDEST (dest); break; case 0x23: /* EORS immed */ DPSImmRHS; dest = LHS ^ rhs; WRITESDEST (dest); break; case 0x24: /* SUB immed */ dest = LHS - DPImmRHS; WRITEDEST (dest); break; case 0x25: /* SUBS immed */ lhs = LHS; rhs = DPImmRHS; dest = lhs - rhs; if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, lhs, rhs, dest); ARMul_SubOverflow (state, lhs, rhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x26: /* RSB immed */ dest = DPImmRHS - LHS; WRITEDEST (dest); break; case 0x27: /* RSBS immed */ lhs = LHS; rhs = DPImmRHS; dest = rhs - lhs; if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, rhs, lhs, dest); ARMul_SubOverflow (state, rhs, lhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x28: /* ADD immed */ dest = LHS + DPImmRHS; WRITEDEST (dest); break; case 0x29: /* ADDS immed */ lhs = LHS; rhs = DPImmRHS; dest = lhs + rhs; ASSIGNZ (dest == 0); if ((lhs | rhs) >> 30) { /* Possible C,V,N to set. */ ASSIGNN (NEG (dest)); ARMul_AddCarry (state, lhs, rhs, dest); ARMul_AddOverflow (state, lhs, rhs, dest); } else { CLEARN; CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x2a: /* ADC immed */ dest = LHS + DPImmRHS + CFLAG; WRITEDEST (dest); break; case 0x2b: /* ADCS immed */ lhs = LHS; rhs = DPImmRHS; dest = lhs + rhs + CFLAG; ASSIGNZ (dest == 0); if ((lhs | rhs) >> 30) { /* Possible C,V,N to set. */ ASSIGNN (NEG (dest)); ARMul_AddCarry (state, lhs, rhs, dest); ARMul_AddOverflow (state, lhs, rhs, dest); } else { CLEARN; CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x2c: /* SBC immed */ dest = LHS - DPImmRHS - !CFLAG; WRITEDEST (dest); break; case 0x2d: /* SBCS immed */ lhs = LHS; rhs = DPImmRHS; dest = lhs - rhs - !CFLAG; if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, lhs, rhs, dest); ARMul_SubOverflow (state, lhs, rhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x2e: /* RSC immed */ dest = DPImmRHS - LHS - !CFLAG; WRITEDEST (dest); break; case 0x2f: /* RSCS immed */ lhs = LHS; rhs = DPImmRHS; dest = rhs - lhs - !CFLAG; if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, rhs, lhs, dest); ARMul_SubOverflow (state, rhs, lhs, dest); } else { CLEARC; CLEARV; } WRITESDEST (dest); break; case 0x30: /* TST immed */ UNDEF_Test; break; case 0x31: /* TSTP immed */ if (DESTReg == 15) { /* TSTP immed. */ #ifdef MODE32 state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else temp = LHS & DPImmRHS; SETR15PSR (temp); #endif } else { /* TST immed. */ DPSImmRHS; dest = LHS & rhs; ARMul_NegZero (state, dest); } break; case 0x32: /* TEQ immed and MSR immed to CPSR */ if (DESTReg == 15) /* MSR immed to CPSR. */ ARMul_FixCPSR (state, instr, DPImmRHS); else UNDEF_Test; break; case 0x33: /* TEQP immed */ if (DESTReg == 15) { /* TEQP immed. */ #ifdef MODE32 state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else temp = LHS ^ DPImmRHS; SETR15PSR (temp); #endif } else { DPSImmRHS; /* TEQ immed */ dest = LHS ^ rhs; ARMul_NegZero (state, dest); } break; case 0x34: /* CMP immed */ UNDEF_Test; break; case 0x35: /* CMPP immed */ if (DESTReg == 15) { /* CMPP immed. */ #ifdef MODE32 state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else temp = LHS - DPImmRHS; SETR15PSR (temp); #endif break; } else { /* CMP immed. */ lhs = LHS; rhs = DPImmRHS; dest = lhs - rhs; ARMul_NegZero (state, dest); if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { ARMul_SubCarry (state, lhs, rhs, dest); ARMul_SubOverflow (state, lhs, rhs, dest); } else { CLEARC; CLEARV; } } break; case 0x36: /* CMN immed and MSR immed to SPSR */ if (DESTReg == 15) ARMul_FixSPSR (state, instr, DPImmRHS); else UNDEF_Test; break; case 0x37: /* CMNP immed. */ if (DESTReg == 15) { /* CMNP immed. */ #ifdef MODE32 state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); #else temp = LHS + DPImmRHS; SETR15PSR (temp); #endif break; } else { /* CMN immed. */ lhs = LHS; rhs = DPImmRHS; dest = lhs + rhs; ASSIGNZ (dest == 0); if ((lhs | rhs) >> 30) { /* Possible C,V,N to set. */ ASSIGNN (NEG (dest)); ARMul_AddCarry (state, lhs, rhs, dest); ARMul_AddOverflow (state, lhs, rhs, dest); } else { CLEARN; CLEARC; CLEARV; } } break; case 0x38: /* ORR immed. */ dest = LHS | DPImmRHS; WRITEDEST (dest); break; case 0x39: /* ORRS immed. */ DPSImmRHS; dest = LHS | rhs; WRITESDEST (dest); break; case 0x3a: /* MOV immed. */ dest = DPImmRHS; WRITEDEST (dest); break; case 0x3b: /* MOVS immed. */ DPSImmRHS; WRITESDEST (rhs); break; case 0x3c: /* BIC immed. */ dest = LHS & ~DPImmRHS; WRITEDEST (dest); break; case 0x3d: /* BICS immed. */ DPSImmRHS; dest = LHS & ~rhs; WRITESDEST (dest); break; case 0x3e: /* MVN immed. */ dest = ~DPImmRHS; WRITEDEST (dest); break; case 0x3f: /* MVNS immed. */ DPSImmRHS; WRITESDEST (~rhs); break; /* Single Data Transfer Immediate RHS Instructions. */ case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */ lhs = LHS; if (StoreWord (state, instr, lhs)) LSBase = lhs - LSImmRHS; break; case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */ lhs = LHS; if (LoadWord (state, instr, lhs)) LSBase = lhs - LSImmRHS; break; case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; temp = lhs - LSImmRHS; state->NtransSig = LOW; if (StoreWord (state, instr, lhs)) LSBase = temp; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; state->NtransSig = LOW; if (LoadWord (state, instr, lhs)) LSBase = lhs - LSImmRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */ lhs = LHS; if (StoreByte (state, instr, lhs)) LSBase = lhs - LSImmRHS; break; case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */ lhs = LHS; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = lhs - LSImmRHS; break; case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; state->NtransSig = LOW; if (StoreByte (state, instr, lhs)) LSBase = lhs - LSImmRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; state->NtransSig = LOW; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = lhs - LSImmRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */ lhs = LHS; if (StoreWord (state, instr, lhs)) LSBase = lhs + LSImmRHS; break; case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */ lhs = LHS; if (LoadWord (state, instr, lhs)) LSBase = lhs + LSImmRHS; break; case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; state->NtransSig = LOW; if (StoreWord (state, instr, lhs)) LSBase = lhs + LSImmRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; state->NtransSig = LOW; if (LoadWord (state, instr, lhs)) LSBase = lhs + LSImmRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */ lhs = LHS; if (StoreByte (state, instr, lhs)) LSBase = lhs + LSImmRHS; break; case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */ lhs = LHS; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = lhs + LSImmRHS; break; case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; state->NtransSig = LOW; if (StoreByte (state, instr, lhs)) LSBase = lhs + LSImmRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; lhs = LHS; state->NtransSig = LOW; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = lhs + LSImmRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */ (void) StoreWord (state, instr, LHS - LSImmRHS); break; case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */ (void) LoadWord (state, instr, LHS - LSImmRHS); break; case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS - LSImmRHS; if (StoreWord (state, instr, temp)) LSBase = temp; break; case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS - LSImmRHS; if (LoadWord (state, instr, temp)) LSBase = temp; break; case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */ (void) StoreByte (state, instr, LHS - LSImmRHS); break; case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */ (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED); break; case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS - LSImmRHS; if (StoreByte (state, instr, temp)) LSBase = temp; break; case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS - LSImmRHS; if (LoadByte (state, instr, temp, LUNSIGNED)) LSBase = temp; break; case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */ (void) StoreWord (state, instr, LHS + LSImmRHS); break; case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */ (void) LoadWord (state, instr, LHS + LSImmRHS); break; case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS + LSImmRHS; if (StoreWord (state, instr, temp)) LSBase = temp; break; case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS + LSImmRHS; if (LoadWord (state, instr, temp)) LSBase = temp; break; case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */ (void) StoreByte (state, instr, LHS + LSImmRHS); break; case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */ (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED); break; case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS + LSImmRHS; if (StoreByte (state, instr, temp)) LSBase = temp; break; case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */ UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; temp = LHS + LSImmRHS; if (LoadByte (state, instr, temp, LUNSIGNED)) LSBase = temp; break; /* Single Data Transfer Register RHS Instructions. */ case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; if (StoreWord (state, instr, lhs)) LSBase = lhs - LSRegRHS; break; case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs - LSRegRHS; if (LoadWord (state, instr, lhs)) LSBase = temp; break; case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; state->NtransSig = LOW; if (StoreWord (state, instr, lhs)) LSBase = lhs - LSRegRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs - LSRegRHS; state->NtransSig = LOW; if (LoadWord (state, instr, lhs)) LSBase = temp; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; if (StoreByte (state, instr, lhs)) LSBase = lhs - LSRegRHS; break; case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs - LSRegRHS; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = temp; break; case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; state->NtransSig = LOW; if (StoreByte (state, instr, lhs)) LSBase = lhs - LSRegRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs - LSRegRHS; state->NtransSig = LOW; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = temp; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; if (StoreWord (state, instr, lhs)) LSBase = lhs + LSRegRHS; break; case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs + LSRegRHS; if (LoadWord (state, instr, lhs)) LSBase = temp; break; case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; state->NtransSig = LOW; if (StoreWord (state, instr, lhs)) LSBase = lhs + LSRegRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs + LSRegRHS; state->NtransSig = LOW; if (LoadWord (state, instr, lhs)) LSBase = temp; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; if (StoreByte (state, instr, lhs)) LSBase = lhs + LSRegRHS; break; case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs + LSRegRHS; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = temp; break; case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; state->NtransSig = LOW; if (StoreByte (state, instr, lhs)) LSBase = lhs + LSRegRHS; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; lhs = LHS; temp = lhs + LSRegRHS; state->NtransSig = LOW; if (LoadByte (state, instr, lhs, LUNSIGNED)) LSBase = temp; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; break; case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } (void) StoreWord (state, instr, LHS - LSRegRHS); break; case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } (void) LoadWord (state, instr, LHS - LSRegRHS); break; case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS - LSRegRHS; if (StoreWord (state, instr, temp)) LSBase = temp; break; case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS - LSRegRHS; if (LoadWord (state, instr, temp)) LSBase = temp; break; case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } (void) StoreByte (state, instr, LHS - LSRegRHS); break; case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED); break; case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS - LSRegRHS; if (StoreByte (state, instr, temp)) LSBase = temp; break; case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS - LSRegRHS; if (LoadByte (state, instr, temp, LUNSIGNED)) LSBase = temp; break; case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } (void) StoreWord (state, instr, LHS + LSRegRHS); break; case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } (void) LoadWord (state, instr, LHS + LSRegRHS); break; case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS + LSRegRHS; if (StoreWord (state, instr, temp)) LSBase = temp; break; case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS + LSRegRHS; if (LoadWord (state, instr, temp)) LSBase = temp; break; case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */ if (BIT (4)) { #ifdef MODE32 if (state->is_v6 && handle_v6_insn (state, instr)) break; #endif ARMul_UndefInstr (state, instr); break; } (void) StoreByte (state, instr, LHS + LSRegRHS); break; case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED); break; case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */ if (BIT (4)) { ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS + LSRegRHS; if (StoreByte (state, instr, temp)) LSBase = temp; break; case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */ if (BIT (4)) { /* Check for the special breakpoint opcode. This value should correspond to the value defined as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */ if (BITS (0, 19) == 0xfdefe) { if (!ARMul_OSHandleSWI (state, SWI_Breakpoint)) ARMul_Abort (state, ARMul_SWIV); } else ARMul_UndefInstr (state, instr); break; } UNDEF_LSRBaseEQOffWb; UNDEF_LSRBaseEQDestWb; UNDEF_LSRPCBaseWb; UNDEF_LSRPCOffWb; temp = LHS + LSRegRHS; if (LoadByte (state, instr, temp, LUNSIGNED)) LSBase = temp; break; /* Multiple Data Transfer Instructions. */ case 0x80: /* Store, No WriteBack, Post Dec. */ STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L); break; case 0x81: /* Load, No WriteBack, Post Dec. */ LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L); break; case 0x82: /* Store, WriteBack, Post Dec. */ temp = LSBase - LSMNumRegs; STOREMULT (instr, temp + 4L, temp); break; case 0x83: /* Load, WriteBack, Post Dec. */ temp = LSBase - LSMNumRegs; LOADMULT (instr, temp + 4L, temp); break; case 0x84: /* Store, Flags, No WriteBack, Post Dec. */ STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L); break; case 0x85: /* Load, Flags, No WriteBack, Post Dec. */ LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L); break; case 0x86: /* Store, Flags, WriteBack, Post Dec. */ temp = LSBase - LSMNumRegs; STORESMULT (instr, temp + 4L, temp); break; case 0x87: /* Load, Flags, WriteBack, Post Dec. */ temp = LSBase - LSMNumRegs; LOADSMULT (instr, temp + 4L, temp); break; case 0x88: /* Store, No WriteBack, Post Inc. */ STOREMULT (instr, LSBase, 0L); break; case 0x89: /* Load, No WriteBack, Post Inc. */ LOADMULT (instr, LSBase, 0L); break; case 0x8a: /* Store, WriteBack, Post Inc. */ temp = LSBase; STOREMULT (instr, temp, temp + LSMNumRegs); break; case 0x8b: /* Load, WriteBack, Post Inc. */ temp = LSBase; LOADMULT (instr, temp, temp + LSMNumRegs); break; case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */ STORESMULT (instr, LSBase, 0L); break; case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */ LOADSMULT (instr, LSBase, 0L); break; case 0x8e: /* Store, Flags, WriteBack, Post Inc. */ temp = LSBase; STORESMULT (instr, temp, temp + LSMNumRegs); break; case 0x8f: /* Load, Flags, WriteBack, Post Inc. */ temp = LSBase; LOADSMULT (instr, temp, temp + LSMNumRegs); break; case 0x90: /* Store, No WriteBack, Pre Dec. */ STOREMULT (instr, LSBase - LSMNumRegs, 0L); break; case 0x91: /* Load, No WriteBack, Pre Dec. */ LOADMULT (instr, LSBase - LSMNumRegs, 0L); break; case 0x92: /* Store, WriteBack, Pre Dec. */ temp = LSBase - LSMNumRegs; STOREMULT (instr, temp, temp); break; case 0x93: /* Load, WriteBack, Pre Dec. */ temp = LSBase - LSMNumRegs; LOADMULT (instr, temp, temp); break; case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */ STORESMULT (instr, LSBase - LSMNumRegs, 0L); break; case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */ LOADSMULT (instr, LSBase - LSMNumRegs, 0L); break; case 0x96: /* Store, Flags, WriteBack, Pre Dec. */ temp = LSBase - LSMNumRegs; STORESMULT (instr, temp, temp); break; case 0x97: /* Load, Flags, WriteBack, Pre Dec. */ temp = LSBase - LSMNumRegs; LOADSMULT (instr, temp, temp); break; case 0x98: /* Store, No WriteBack, Pre Inc. */ STOREMULT (instr, LSBase + 4L, 0L); break; case 0x99: /* Load, No WriteBack, Pre Inc. */ LOADMULT (instr, LSBase + 4L, 0L); break; case 0x9a: /* Store, WriteBack, Pre Inc. */ temp = LSBase; STOREMULT (instr, temp + 4L, temp + LSMNumRegs); break; case 0x9b: /* Load, WriteBack, Pre Inc. */ temp = LSBase; LOADMULT (instr, temp + 4L, temp + LSMNumRegs); break; case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */ STORESMULT (instr, LSBase + 4L, 0L); break; case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */ LOADSMULT (instr, LSBase + 4L, 0L); break; case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */ temp = LSBase; STORESMULT (instr, temp + 4L, temp + LSMNumRegs); break; case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */ temp = LSBase; LOADSMULT (instr, temp + 4L, temp + LSMNumRegs); break; /* Branch forward. */ case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7: state->Reg[15] = pc + 8 + POSBRANCH; FLUSHPIPE; break; /* Branch backward. */ case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: state->Reg[15] = pc + 8 + NEGBRANCH; FLUSHPIPE; break; /* Branch and Link forward. */ case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7: /* Put PC into Link. */ #ifdef MODE32 state->Reg[14] = pc + 4; #else state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; #endif state->Reg[15] = pc + 8 + POSBRANCH; FLUSHPIPE; break; /* Branch and Link backward. */ case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: /* Put PC into Link. */ #ifdef MODE32 state->Reg[14] = pc + 4; #else state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; #endif state->Reg[15] = pc + 8 + NEGBRANCH; FLUSHPIPE; break; /* Co-Processor Data Transfers. */ case 0xc4: if (state->is_v5) { /* Reading from R15 is UNPREDICTABLE. */ if (BITS (12, 15) == 15 || BITS (16, 19) == 15) ARMul_UndefInstr (state, instr); /* Is access to coprocessor 0 allowed ? */ else if (!CP_ACCESS_ALLOWED (state, CPNum)) ARMul_UndefInstr (state, instr); /* Special treatment for XScale coprocessors. */ else if (state->is_XScale) { /* Only opcode 0 is supported. */ if (BITS (4, 7) != 0x00) ARMul_UndefInstr (state, instr); /* Only coporcessor 0 is supported. */ else if (CPNum != 0x00) ARMul_UndefInstr (state, instr); /* Only accumulator 0 is supported. */ else if (BITS (0, 3) != 0x00) ARMul_UndefInstr (state, instr); else { /* XScale MAR insn. Move two registers into accumulator. */ state->Accumulator = state-> Reg[BITS (12, 15)]; state->Accumulator += (ARMdword) state-> Reg[BITS (16, 19)] << 32; } } else /* FIXME: Not sure what to do for other v5 processors. */ ARMul_UndefInstr (state, instr); break; } /* Drop through. */ case 0xc0: /* Store , No WriteBack , Post Dec. */ ARMul_STC (state, instr, LHS); break; case 0xc5: if (state->is_v5) { /* Writes to R15 are UNPREDICATABLE. */ if (DESTReg == 15 || LHSReg == 15) ARMul_UndefInstr (state, instr); /* Is access to the coprocessor allowed ? */ else if (!CP_ACCESS_ALLOWED (state, CPNum)) ARMul_UndefInstr (state, instr); /* Special handling for XScale coprcoessors. */ else if (state->is_XScale) { /* Only opcode 0 is supported. */ if (BITS (4, 7) != 0x00) ARMul_UndefInstr (state, instr); /* Only coprocessor 0 is supported. */ else if (CPNum != 0x00) ARMul_UndefInstr (state, instr); /* Only accumulator 0 is supported. */ else if (BITS (0, 3) != 0x00) ARMul_UndefInstr (state, instr); else { /* XScale MRA insn. Move accumulator into two registers. */ ARMword t1 = (state-> Accumulator >> 32) & 255; if (t1 & 128) t1 -= 256; state->Reg[BITS (12, 15)] = state-> Accumulator; state->Reg[BITS (16, 19)] = t1; break; } } else /* FIXME: Not sure what to do for other v5 processors. */ ARMul_UndefInstr (state, instr); break; } /* Drop through. */ case 0xc1: /* Load , No WriteBack , Post Dec. */ ARMul_LDC (state, instr, LHS); break; case 0xc2: case 0xc6: /* Store , WriteBack , Post Dec. */ lhs = LHS; state->Base = lhs - LSCOff; ARMul_STC (state, instr, lhs); break; case 0xc3: case 0xc7: /* Load , WriteBack , Post Dec. */ lhs = LHS; state->Base = lhs - LSCOff; ARMul_LDC (state, instr, lhs); break; case 0xc8: case 0xcc: /* Store , No WriteBack , Post Inc. */ ARMul_STC (state, instr, LHS); break; case 0xc9: case 0xcd: /* Load , No WriteBack , Post Inc. */ ARMul_LDC (state, instr, LHS); break; case 0xca: case 0xce: /* Store , WriteBack , Post Inc. */ lhs = LHS; state->Base = lhs + LSCOff; ARMul_STC (state, instr, LHS); break; case 0xcb: case 0xcf: /* Load , WriteBack , Post Inc. */ lhs = LHS; state->Base = lhs + LSCOff; ARMul_LDC (state, instr, LHS); break; case 0xd0: case 0xd4: /* Store , No WriteBack , Pre Dec. */ ARMul_STC (state, instr, LHS - LSCOff); break; case 0xd1: case 0xd5: /* Load , No WriteBack , Pre Dec. */ ARMul_LDC (state, instr, LHS - LSCOff); break; case 0xd2: case 0xd6: /* Store , WriteBack , Pre Dec. */ lhs = LHS - LSCOff; state->Base = lhs; ARMul_STC (state, instr, lhs); break; case 0xd3: case 0xd7: /* Load , WriteBack , Pre Dec. */ lhs = LHS - LSCOff; state->Base = lhs; ARMul_LDC (state, instr, lhs); break; case 0xd8: case 0xdc: /* Store , No WriteBack , Pre Inc. */ ARMul_STC (state, instr, LHS + LSCOff); break; case 0xd9: case 0xdd: /* Load , No WriteBack , Pre Inc. */ ARMul_LDC (state, instr, LHS + LSCOff); break; case 0xda: case 0xde: /* Store , WriteBack , Pre Inc. */ lhs = LHS + LSCOff; state->Base = lhs; ARMul_STC (state, instr, lhs); break; case 0xdb: case 0xdf: /* Load , WriteBack , Pre Inc. */ lhs = LHS + LSCOff; state->Base = lhs; ARMul_LDC (state, instr, lhs); break; /* Co-Processor Register Transfers (MCR) and Data Ops. */ case 0xe2: if (!CP_ACCESS_ALLOWED (state, CPNum)) { ARMul_UndefInstr (state, instr); break; } if (state->is_XScale) switch (BITS (18, 19)) { case 0x0: if (BITS (4, 11) == 1 && BITS (16, 17) == 0) { /* XScale MIA instruction. Signed multiplication of two 32 bit values and addition to 40 bit accumulator. */ long long Rm = state-> Reg [MULLHSReg]; long long Rs = state-> Reg [MULACCReg]; if (Rm & (1 << 31)) Rm -= 1ULL << 32; if (Rs & (1 << 31)) Rs -= 1ULL << 32; state->Accumulator += Rm * Rs; goto donext; } break; case 0x2: if (BITS (4, 11) == 1 && BITS (16, 17) == 0) { /* XScale MIAPH instruction. */ ARMword t1 = state-> Reg[MULLHSReg] >> 16; ARMword t2 = state-> Reg[MULACCReg] >> 16; ARMword t3 = state-> Reg[MULLHSReg] & 0xffff; ARMword t4 = state-> Reg[MULACCReg] & 0xffff; long long t5; if (t1 & (1 << 15)) t1 -= 1 << 16; if (t2 & (1 << 15)) t2 -= 1 << 16; if (t3 & (1 << 15)) t3 -= 1 << 16; if (t4 & (1 << 15)) t4 -= 1 << 16; t1 *= t2; t5 = t1; if (t5 & (1 << 31)) t5 -= 1ULL << 32; state->Accumulator += t5; t3 *= t4; t5 = t3; if (t5 & (1 << 31)) t5 -= 1ULL << 32; state->Accumulator += t5; goto donext; } break; case 0x3: if (BITS (4, 11) == 1) { /* XScale MIAxy instruction. */ ARMword t1; ARMword t2; long long t5; if (BIT (17)) t1 = state-> Reg [MULLHSReg] >> 16; else t1 = state-> Reg [MULLHSReg] & 0xffff; if (BIT (16)) t2 = state-> Reg [MULACCReg] >> 16; else t2 = state-> Reg [MULACCReg] & 0xffff; if (t1 & (1 << 15)) t1 -= 1 << 16; if (t2 & (1 << 15)) t2 -= 1 << 16; t1 *= t2; t5 = t1; if (t5 & (1 << 31)) t5 -= 1ULL << 32; state->Accumulator += t5; goto donext; } break; default: break; } /* Drop through. */ case 0xe0: case 0xe4: case 0xe6: case 0xe8: case 0xea: case 0xec: case 0xee: if (BIT (4)) { /* MCR. */ if (DESTReg == 15) { UNDEF_MCRPC; #ifdef MODE32 ARMul_MCR (state, instr, state->Reg[15] + isize); #else ARMul_MCR (state, instr, ECC | ER15INT | EMODE | ((state->Reg[15] + isize) & R15PCBITS)); #endif } else ARMul_MCR (state, instr, DEST); } else /* CDP Part 1. */ ARMul_CDP (state, instr); break; /* Co-Processor Register Transfers (MRC) and Data Ops. */ case 0xe1: case 0xe3: case 0xe5: case 0xe7: case 0xe9: case 0xeb: case 0xed: case 0xef: if (BIT (4)) { /* MRC */ temp = ARMul_MRC (state, instr); if (DESTReg == 15) { ASSIGNN ((temp & NBIT) != 0); ASSIGNZ ((temp & ZBIT) != 0); ASSIGNC ((temp & CBIT) != 0); ASSIGNV ((temp & VBIT) != 0); } else DEST = temp; } else /* CDP Part 2. */ ARMul_CDP (state, instr); break; /* SWI instruction. */ case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: if (instr == ARMul_ABORTWORD && state->AbortAddr == pc) { /* A prefetch abort. */ XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc); ARMul_Abort (state, ARMul_PrefetchAbortV); break; } #if 0 if (!ARMul_OSHandleSWI (state, BITS (0, 23))) #else ARMul_Abort (state, ARMul_SWIV); #endif break; } } #ifdef MODET donext: #endif #ifdef NEED_UI_LOOP_HOOK if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) { ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; ui_loop_hook (0); } #endif /* NEED_UI_LOOP_HOOK */ /*added energy_prof statement by ksh in 2004-11-26 */ //chy 2005-07-28 for standalone //ARMul_do_energy(state,instr,pc); //teawater add for record reg value to ./reg.txt 2005.07.10--------------------- if (state->tea_break_ok && pc == state->tea_break_addr) { ARMul_Debug (state, 0, 0); state->tea_break_ok = 0; } else { state->tea_break_ok = 1; } //AJ2D-------------------------------------------------------------------------- //chy 2006-04-14 for ctrl-c debug if(debugmode){ if (instr != ARMul_ABORTWORD) { remote_interrupt_test_time++; //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!! if(remote_interrupt_test_time>=2000){ remote_interrupt_test_time=0; if(remote_interrupt()){ //for test //printf("SKYEYE: ICE_debug recv Ctrl_C\n"); state->EndCondition = 0; state->Emulate = STOP; } } } } //chy 2006-04-12 for ICE debug TEST_EMULATE: if (state->Emulate == ONCE) state->Emulate = STOP; //chy: 2003-08-23: should not use CHANGEMODE !!!! /* If we have changed mode, allow the PC to advance before stopping. */ // else if (state->Emulate == CHANGEMODE) // continue; else if (state->Emulate != RUN) break; } while (!stop_simulator); state->decoded = decoded; state->loaded = loaded; state->pc = pc; //chy 2006-04-12, for ICE debug state->decoded_addr=decoded_addr; state->loaded_addr=loaded_addr; return pc; } //teawater add for arm2x86 2005.02.17------------------------------------------- /*ywc 2005-04-01*/ //#include "tb.h" //#include "arm2x86_self.h" static volatile void (*gen_func) (void); //static volatile ARMul_State *tmp_st; //static volatile ARMul_State *save_st; static volatile uint32_t tmp_st; static volatile uint32_t save_st; static volatile uint32_t save_T0; static volatile uint32_t save_T1; static volatile uint32_t save_T2; #ifdef MODE32 #ifdef DBCT //teawater change for debug function 2005.07.09--------------------------------- ARMword ARMul_Emulate32_dbct (ARMul_State * state) { static int init = 0; static FILE *fd; /*if (!init) { fd = fopen("./pc.txt", "w"); if (!fd) { exit(-1); } init = 1; } */ state->Reg[15] += INSN_SIZE; do { /*if(skyeye_config.log.logon>=1){ if(state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) { static int mybegin=0; static int myinstrnum=0; if(mybegin==0) mybegin=1; if(mybegin==1) { state->Reg[15] -= INSN_SIZE; if(skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr); if(skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd); if(skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd); fprintf(skyeye_logfd,"\n"); if(skyeye_config.log.length>0){ myinstrnum++; if(myinstrnum>=skyeye_config.log.length) { myinstrnum=0; fflush(skyeye_logfd); fseek(skyeye_logfd,0L,SEEK_SET); } } state->Reg[15] += INSN_SIZE; } } } */ state->trap = 0; gen_func = (void *) tb_find (state, state->Reg[15] - INSN_SIZE); if (!gen_func) { //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n"); //exit(-1); //TRAP_INSN_ABORT //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); //TEA_OUT(printf("TRAP_INSN_ABORT\n")); //teawater add for xscale(arm v5) 2005.09.01------------------------------------ /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE); state->Reg[15] += INSN_SIZE; ARMul_Abort(state, ARMul_PrefetchAbortV); state->Reg[15] += INSN_SIZE; goto next; */ state->trap = TRAP_INSN_ABORT; goto check; //AJ2D-------------------------------------------------------------------------- } save_st = (uint32_t) st; save_T0 = T0; save_T1 = T1; save_T2 = T2; tmp_st = (uint32_t) state; wmb (); st = (ARMul_State *) tmp_st; gen_func (); st = (ARMul_State *) save_st; T0 = save_T0; T1 = save_T1; T2 = save_T2; /*if (state->trap != TRAP_OUT) { state->tea_break_ok = 1; } if (state->trap <= TRAP_SET_R15) { goto next; } */ //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); //teawater add check thumb 2005.07.21------------------------------------------- /*if (TFLAG) { state->Reg[15] -= 2; return(state->Reg[15]); } */ //AJ2D-------------------------------------------------------------------------- //teawater add for xscale(arm v5) 2005.09.01------------------------------------ check: //AJ2D-------------------------------------------------------------------------- switch (state->trap) { case TRAP_RESET: { //TEA_OUT(printf("TRAP_RESET\n")); ARMul_Abort (state, ARMul_ResetV); state->Reg[15] += INSN_SIZE; } break; case TRAP_UNPREDICTABLE: { ARMul_Debug (state, 0, 0); } break; case TRAP_INSN_UNDEF: { //TEA_OUT(printf("TRAP_INSN_UNDEF\n")); state->Reg[15] += INSN_SIZE; ARMul_UndefInstr (state, 0); state->Reg[15] += INSN_SIZE; } break; case TRAP_SWI: { //TEA_OUT(printf("TRAP_SWI\n")); state->Reg[15] += INSN_SIZE; ARMul_Abort (state, ARMul_SWIV); state->Reg[15] += INSN_SIZE; } break; //teawater add for xscale(arm v5) 2005.09.01------------------------------------ case TRAP_INSN_ABORT: { XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE); state->Reg[15] += INSN_SIZE; ARMul_Abort (state, ARMul_PrefetchAbortV); state->Reg[15] += INSN_SIZE; } break; //AJ2D-------------------------------------------------------------------------- case TRAP_DATA_ABORT: { //TEA_OUT(printf("TRAP_DATA_ABORT\n")); state->Reg[15] += INSN_SIZE; ARMul_Abort (state, ARMul_DataAbortV); state->Reg[15] += INSN_SIZE; } break; case TRAP_IRQ: { //TEA_OUT(printf("TRAP_IRQ\n")); state->Reg[15] += INSN_SIZE; ARMul_Abort (state, ARMul_IRQV); state->Reg[15] += INSN_SIZE; } break; case TRAP_FIQ: { //TEA_OUT(printf("TRAP_FIQ\n")); state->Reg[15] += INSN_SIZE; ARMul_Abort (state, ARMul_FIQV); state->Reg[15] += INSN_SIZE; } break; case TRAP_SETS_R15: { //TEA_OUT(printf("TRAP_SETS_R15\n")); /*if (state->Bank > 0) { state->Cpsr = state->Spsr[state->Bank]; ARMul_CPSRAltered (state); } */ WriteSR15 (state, state->Reg[15]); } break; case TRAP_SET_CPSR: { //TEA_OUT(printf("TRAP_SET_CPSR\n")); //chy 2006-02-15 USERBANK=SYSTEMBANK=0 //chy 2006-02-16 should use Mode to test //if (state->Bank > 0) { if (state->Mode != USER26MODE && state->Mode != USER32MODE){ ARMul_CPSRAltered (state); } state->Reg[15] += INSN_SIZE; } break; case TRAP_OUT: { //TEA_OUT(printf("TRAP_OUT\n")); goto out; } break; case TRAP_BREAKPOINT: { //TEA_OUT(printf("TRAP_BREAKPOINT\n")); state->Reg[15] -= INSN_SIZE; if (!ARMul_OSHandleSWI (state, SWI_Breakpoint)) { ARMul_Abort (state, ARMul_SWIV); } state->Reg[15] += INSN_SIZE; } break; } next: if (state->Emulate == ONCE) { state->Emulate = STOP; break; } else if (state->Emulate != RUN) { break; } } while (!stop_simulator); out: state->Reg[15] -= INSN_SIZE; return (state->Reg[15]); } #endif //AJ2D-------------------------------------------------------------------------- #endif //AJ2D-------------------------------------------------------------------------- /* This routine evaluates most Data Processing register RHS's with the S bit clear. It is intended to be called from the macro DPRegRHS, which filters the common case of an unshifted register with in line code. */ static ARMword GetDPRegRHS (ARMul_State * state, ARMword instr) { ARMword shamt, base; base = RHSReg; if (BIT (4)) { /* Shift amount in a register. */ UNDEF_Shift; INCPC; #ifndef MODE32 if (base == 15) base = ECC | ER15INT | R15PC | EMODE; else #endif base = state->Reg[base]; ARMul_Icycles (state, 1, 0L); shamt = state->Reg[BITS (8, 11)] & 0xff; switch ((int) BITS (5, 6)) { case LSL: if (shamt == 0) return (base); else if (shamt >= 32) return (0); else return (base << shamt); case LSR: if (shamt == 0) return (base); else if (shamt >= 32) return (0); else return (base >> shamt); case ASR: if (shamt == 0) return (base); else if (shamt >= 32) return ((ARMword) ((int) base >> 31L)); else return ((ARMword) (( int) base >> (int) shamt)); case ROR: shamt &= 0x1f; if (shamt == 0) return (base); else return ((base << (32 - shamt)) | (base >> shamt)); } } else { /* Shift amount is a constant. */ #ifndef MODE32 if (base == 15) base = ECC | ER15INT | R15PC | EMODE; else #endif base = state->Reg[base]; shamt = BITS (7, 11); switch ((int) BITS (5, 6)) { case LSL: return (base << shamt); case LSR: if (shamt == 0) return (0); else return (base >> shamt); case ASR: if (shamt == 0) return ((ARMword) (( int) base >> 31L)); else return ((ARMword) (( int) base >> (int) shamt)); case ROR: if (shamt == 0) /* It's an RRX. */ return ((base >> 1) | (CFLAG << 31)); else return ((base << (32 - shamt)) | (base >> shamt)); } } return 0; } /* This routine evaluates most Logical Data Processing register RHS's with the S bit set. It is intended to be called from the macro DPSRegRHS, which filters the common case of an unshifted register with in line code. */ static ARMword GetDPSRegRHS (ARMul_State * state, ARMword instr) { ARMword shamt, base; base = RHSReg; if (BIT (4)) { /* Shift amount in a register. */ UNDEF_Shift; INCPC; #ifndef MODE32 if (base == 15) base = ECC | ER15INT | R15PC | EMODE; else #endif base = state->Reg[base]; ARMul_Icycles (state, 1, 0L); shamt = state->Reg[BITS (8, 11)] & 0xff; switch ((int) BITS (5, 6)) { case LSL: if (shamt == 0) return (base); else if (shamt == 32) { ASSIGNC (base & 1); return (0); } else if (shamt > 32) { CLEARC; return (0); } else { ASSIGNC ((base >> (32 - shamt)) & 1); return (base << shamt); } case LSR: if (shamt == 0) return (base); else if (shamt == 32) { ASSIGNC (base >> 31); return (0); } else if (shamt > 32) { CLEARC; return (0); } else { ASSIGNC ((base >> (shamt - 1)) & 1); return (base >> shamt); } case ASR: if (shamt == 0) return (base); else if (shamt >= 32) { ASSIGNC (base >> 31L); return ((ARMword) (( int) base >> 31L)); } else { ASSIGNC ((ARMword) (( int) base >> (int) (shamt - 1)) & 1); return ((ARMword) ((int) base >> (int) shamt)); } case ROR: if (shamt == 0) return (base); shamt &= 0x1f; if (shamt == 0) { ASSIGNC (base >> 31); return (base); } else { ASSIGNC ((base >> (shamt - 1)) & 1); return ((base << (32 - shamt)) | (base >> shamt)); } } } else { /* Shift amount is a constant. */ #ifndef MODE32 if (base == 15) base = ECC | ER15INT | R15PC | EMODE; else #endif base = state->Reg[base]; shamt = BITS (7, 11); switch ((int) BITS (5, 6)) { case LSL: ASSIGNC ((base >> (32 - shamt)) & 1); return (base << shamt); case LSR: if (shamt == 0) { ASSIGNC (base >> 31); return (0); } else { ASSIGNC ((base >> (shamt - 1)) & 1); return (base >> shamt); } case ASR: if (shamt == 0) { ASSIGNC (base >> 31L); return ((ARMword) ((int) base >> 31L)); } else { ASSIGNC ((ARMword) ((int) base >> (int) (shamt - 1)) & 1); return ((ARMword) (( int) base >> (int) shamt)); } case ROR: if (shamt == 0) { /* It's an RRX. */ shamt = CFLAG; ASSIGNC (base & 1); return ((base >> 1) | (shamt << 31)); } else { ASSIGNC ((base >> (shamt - 1)) & 1); return ((base << (32 - shamt)) | (base >> shamt)); } } } return 0; } /* This routine handles writes to register 15 when the S bit is not set. */ static void WriteR15 (ARMul_State * state, ARMword src) { /* The ARM documentation states that the two least significant bits are discarded when setting PC, except in the cases handled by WriteR15Branch() below. It's probably an oversight: in THUMB mode, the second least significant bit should probably not be discarded. */ #ifdef MODET if (TFLAG) src &= 0xfffffffe; else #endif src &= 0xfffffffc; #ifdef MODE32 state->Reg[15] = src & PCBITS; #else state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE; ARMul_R15Altered (state); #endif FLUSHPIPE; } /* This routine handles writes to register 15 when the S bit is set. */ static void WriteSR15 (ARMul_State * state, ARMword src) { #ifdef MODE32 if (state->Bank > 0) { state->Cpsr = state->Spsr[state->Bank]; ARMul_CPSRAltered (state); } #ifdef MODET if (TFLAG) src &= 0xfffffffe; else #endif src &= 0xfffffffc; state->Reg[15] = src & PCBITS; #else #ifdef MODET if (TFLAG) /* ARMul_R15Altered would have to support it. */ abort (); else #endif src &= 0xfffffffc; if (state->Bank == USERBANK) state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE; else state->Reg[15] = src; ARMul_R15Altered (state); #endif FLUSHPIPE; } /* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM will switch to Thumb mode if the least significant bit is set. */ static void WriteR15Branch (ARMul_State * state, ARMword src) { #ifdef MODET if (src & 1) { /* Thumb bit. */ SETT; state->Reg[15] = src & 0xfffffffe; } else { CLEART; state->Reg[15] = src & 0xfffffffc; } state->Cpsr = ARMul_GetCPSR (state); FLUSHPIPE; #else WriteR15 (state, src); #endif } /* This routine evaluates most Load and Store register RHS's. It is intended to be called from the macro LSRegRHS, which filters the common case of an unshifted register with in line code. */ static ARMword GetLSRegRHS (ARMul_State * state, ARMword instr) { ARMword shamt, base; base = RHSReg; #ifndef MODE32 if (base == 15) /* Now forbidden, but ... */ base = ECC | ER15INT | R15PC | EMODE; else #endif base = state->Reg[base]; shamt = BITS (7, 11); switch ((int) BITS (5, 6)) { case LSL: return (base << shamt); case LSR: if (shamt == 0) return (0); else return (base >> shamt); case ASR: if (shamt == 0) return ((ARMword) (( int) base >> 31L)); else return ((ARMword) (( int) base >> (int) shamt)); case ROR: if (shamt == 0) /* It's an RRX. */ return ((base >> 1) | (CFLAG << 31)); else return ((base << (32 - shamt)) | (base >> shamt)); default: break; } return 0; } /* This routine evaluates the ARM7T halfword and signed transfer RHS's. */ static ARMword GetLS7RHS (ARMul_State * state, ARMword instr) { if (BIT (22) == 0) { /* Register. */ #ifndef MODE32 if (RHSReg == 15) /* Now forbidden, but ... */ return ECC | ER15INT | R15PC | EMODE; #endif return state->Reg[RHSReg]; } /* Immediate. */ return BITS (0, 3) | (BITS (8, 11) << 4); } /* This function does the work of loading a word for a LDR instruction. */ #define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ fprintf(skyeye_logfd, \ "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \ description, state->NumInstrs, state->pc, instr, \ address, dest); \ } #define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ fprintf(skyeye_logfd, \ "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \ description, state->NumInstrs, state->pc, instr, \ address, DEST); \ } static unsigned LoadWord (ARMul_State * state, ARMword instr, ARMword address) { ARMword dest; BUSUSEDINCPCS; #ifndef MODE32 if (ADDREXCEPT (address)) INTERNALABORT (address); #endif dest = ARMul_LoadWordN (state, address); if (state->Aborted) { TAKEABORT; return state->lateabtSig; } if (address & 3) dest = ARMul_Align (state, address, dest); WRITEDESTB (dest); ARMul_Icycles (state, 1, 0L); MEM_LOAD_LOG("WORD"); return (DESTReg != LHSReg); } #ifdef MODET /* This function does the work of loading a halfword. */ static unsigned LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address, int signextend) { ARMword dest; BUSUSEDINCPCS; #ifndef MODE32 if (ADDREXCEPT (address)) INTERNALABORT (address); #endif dest = ARMul_LoadHalfWord (state, address); if (state->Aborted) { TAKEABORT; return state->lateabtSig; } UNDEF_LSRBPC; if (signextend) if (dest & 1 << (16 - 1)) dest = (dest & ((1 << 16) - 1)) - (1 << 16); WRITEDEST (dest); ARMul_Icycles (state, 1, 0L); MEM_LOAD_LOG("HALFWORD"); return (DESTReg != LHSReg); } #endif /* MODET */ /* This function does the work of loading a byte for a LDRB instruction. */ static unsigned LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend) { ARMword dest; BUSUSEDINCPCS; #ifndef MODE32 if (ADDREXCEPT (address)) INTERNALABORT (address); #endif dest = ARMul_LoadByte (state, address); if (state->Aborted) { TAKEABORT; return state->lateabtSig; } UNDEF_LSRBPC; if (signextend) if (dest & 1 << (8 - 1)) dest = (dest & ((1 << 8) - 1)) - (1 << 8); WRITEDEST (dest); ARMul_Icycles (state, 1, 0L); MEM_LOAD_LOG("BYTE"); return (DESTReg != LHSReg); } /* This function does the work of loading two words for a LDRD instruction. */ static void Handle_Load_Double (ARMul_State * state, ARMword instr) { ARMword dest_reg; ARMword addr_reg; ARMword write_back = BIT (21); ARMword immediate = BIT (22); ARMword add_to_base = BIT (23); ARMword pre_indexed = BIT (24); ARMword offset; ARMword addr; ARMword sum; ARMword base; ARMword value1; ARMword value2; BUSUSEDINCPCS; /* If the writeback bit is set, the pre-index bit must be clear. */ if (write_back && !pre_indexed) { ARMul_UndefInstr (state, instr); return; } /* Extract the base address register. */ addr_reg = LHSReg; /* Extract the destination register and check it. */ dest_reg = DESTReg; /* Destination register must be even. */ if ((dest_reg & 1) /* Destination register cannot be LR. */ || (dest_reg == 14)) { ARMul_UndefInstr (state, instr); return; } /* Compute the base address. */ base = state->Reg[addr_reg]; /* Compute the offset. */ offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state-> Reg[RHSReg]; /* Compute the sum of the two. */ if (add_to_base) sum = base + offset; else sum = base - offset; /* If this is a pre-indexed mode use the sum. */ if (pre_indexed) addr = sum; else addr = base; /* The address must be aligned on a 8 byte boundary. */ if (addr & 0x7) { #ifdef ABORTS ARMul_DATAABORT (addr); #else ARMul_UndefInstr (state, instr); #endif return; } /* For pre indexed or post indexed addressing modes, check that the destination registers do not overlap the address registers. */ if ((!pre_indexed || write_back) && (addr_reg == dest_reg || addr_reg == dest_reg + 1)) { ARMul_UndefInstr (state, instr); return; } /* Load the words. */ value1 = ARMul_LoadWordN (state, addr); value2 = ARMul_LoadWordN (state, addr + 4); /* Check for data aborts. */ if (state->Aborted) { TAKEABORT; return; } ARMul_Icycles (state, 2, 0L); /* Store the values. */ state->Reg[dest_reg] = value1; state->Reg[dest_reg + 1] = value2; /* Do the post addressing and writeback. */ if (!pre_indexed) addr = sum; if (!pre_indexed || write_back) state->Reg[addr_reg] = addr; } /* This function does the work of storing two words for a STRD instruction. */ static void Handle_Store_Double (ARMul_State * state, ARMword instr) { ARMword src_reg; ARMword addr_reg; ARMword write_back = BIT (21); ARMword immediate = BIT (22); ARMword add_to_base = BIT (23); ARMword pre_indexed = BIT (24); ARMword offset; ARMword addr; ARMword sum; ARMword base; BUSUSEDINCPCS; /* If the writeback bit is set, the pre-index bit must be clear. */ if (write_back && !pre_indexed) { ARMul_UndefInstr (state, instr); return; } /* Extract the base address register. */ addr_reg = LHSReg; /* Base register cannot be PC. */ if (addr_reg == 15) { ARMul_UndefInstr (state, instr); return; } /* Extract the source register. */ src_reg = DESTReg; /* Source register must be even. */ if (src_reg & 1) { ARMul_UndefInstr (state, instr); return; } /* Compute the base address. */ base = state->Reg[addr_reg]; /* Compute the offset. */ offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state-> Reg[RHSReg]; /* Compute the sum of the two. */ if (add_to_base) sum = base + offset; else sum = base - offset; /* If this is a pre-indexed mode use the sum. */ if (pre_indexed) addr = sum; else addr = base; /* The address must be aligned on a 8 byte boundary. */ if (addr & 0x7) { #ifdef ABORTS ARMul_DATAABORT (addr); #else ARMul_UndefInstr (state, instr); #endif return; } /* For pre indexed or post indexed addressing modes, check that the destination registers do not overlap the address registers. */ if ((!pre_indexed || write_back) && (addr_reg == src_reg || addr_reg == src_reg + 1)) { ARMul_UndefInstr (state, instr); return; } /* Load the words. */ ARMul_StoreWordN (state, addr, state->Reg[src_reg]); ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]); if (state->Aborted) { TAKEABORT; return; } /* Do the post addressing and writeback. */ if (!pre_indexed) addr = sum; if (!pre_indexed || write_back) state->Reg[addr_reg] = addr; } /* This function does the work of storing a word from a STR instruction. */ static unsigned StoreWord (ARMul_State * state, ARMword instr, ARMword address) { MEM_STORE_LOG("WORD"); BUSUSEDINCPCN; #ifndef MODE32 if (DESTReg == 15) state->Reg[15] = ECC | ER15INT | R15PC | EMODE; #endif #ifdef MODE32 ARMul_StoreWordN (state, address, DEST); #else if (VECTORACCESS (address) || ADDREXCEPT (address)) { INTERNALABORT (address); (void) ARMul_LoadWordN (state, address); } else ARMul_StoreWordN (state, address, DEST); #endif if (state->Aborted) { TAKEABORT; return state->lateabtSig; } return TRUE; } #ifdef MODET /* This function does the work of storing a byte for a STRH instruction. */ static unsigned StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) { MEM_STORE_LOG("HALFWORD"); BUSUSEDINCPCN; #ifndef MODE32 if (DESTReg == 15) state->Reg[15] = ECC | ER15INT | R15PC | EMODE; #endif #ifdef MODE32 ARMul_StoreHalfWord (state, address, DEST); #else if (VECTORACCESS (address) || ADDREXCEPT (address)) { INTERNALABORT (address); (void) ARMul_LoadHalfWord (state, address); } else ARMul_StoreHalfWord (state, address, DEST); #endif if (state->Aborted) { TAKEABORT; return state->lateabtSig; } return TRUE; } #endif /* MODET */ /* This function does the work of storing a byte for a STRB instruction. */ static unsigned StoreByte (ARMul_State * state, ARMword instr, ARMword address) { MEM_STORE_LOG("BYTE"); BUSUSEDINCPCN; #ifndef MODE32 if (DESTReg == 15) state->Reg[15] = ECC | ER15INT | R15PC | EMODE; #endif #ifdef MODE32 ARMul_StoreByte (state, address, DEST); #else if (VECTORACCESS (address) || ADDREXCEPT (address)) { INTERNALABORT (address); (void) ARMul_LoadByte (state, address); } else ARMul_StoreByte (state, address, DEST); #endif if (state->Aborted) { TAKEABORT; return state->lateabtSig; } UNDEF_LSRBPC; return TRUE; } /* This function does the work of loading the registers listed in an LDM instruction, when the S bit is clear. The code here is always increment after, it's up to the caller to get the input address correct and to handle base register modification. */ static void LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) { ARMword dest, temp; UNDEF_LSMNoRegs; UNDEF_LSMPCBase; UNDEF_LSMBaseInListWb; BUSUSEDINCPCS; #ifndef MODE32 if (ADDREXCEPT (address)) INTERNALABORT (address); #endif /*chy 2004-05-23 may write twice if (BIT (21) && LHSReg != 15) LSBase = WBBase; */ /* N cycle first. */ for (temp = 0; !BIT (temp); temp++); dest = ARMul_LoadWordN (state, address); if (!state->abortSig && !state->Aborted) state->Reg[temp++] = dest; else if (!state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } /*chy 2004-05-23 chy goto end*/ if (state->Aborted) goto L_ldm_makeabort; /* S cycles from here on. */ for (; temp < 16; temp++) if (BIT (temp)) { /* Load this register. */ address += 4; dest = ARMul_LoadWordS (state, address); if (!state->abortSig && !state->Aborted) state->Reg[temp] = dest; else if (!state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } /*chy 2004-05-23 chy goto end */ if (state->Aborted) goto L_ldm_makeabort; } if (BIT (15) && !state->Aborted) /* PC is in the reg list. */ WriteR15Branch (state, PC); /* To write back the final register. */ /* ARMul_Icycles (state, 1, 0L);*/ /*chy 2004-05-23, see below if (state->Aborted) { if (BIT (21) && LHSReg != 15) LSBase = WBBase; TAKEABORT; } */ /*chy 2004-05-23 should compare the Abort Models*/ L_ldm_makeabort: /* To write back the final register. */ ARMul_Icycles (state, 1, 0L); /* chy 2005-11-24, bug found by benjl@cse.unsw.edu.au, etc */ /* if (state->Aborted) { if (BIT (21) && LHSReg != 15) if(!(state->abortSig && state->Aborted && state->lateabtSig==LOW)) LSBase = WBBase; TAKEABORT; }else if (BIT (21) && LHSReg != 15) LSBase = WBBase; */ if (state->Aborted) { if (BIT (21) && LHSReg != 15) { if (!(state->abortSig)) { } } TAKEABORT; } else if (BIT (21) && LHSReg != 15) { LSBase = WBBase; } /* chy 2005-11-24, over */ } /* This function does the work of loading the registers listed in an LDM instruction, when the S bit is set. The code here is always increment after, it's up to the caller to get the input address correct and to handle base register modification. */ static void LoadSMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) { ARMword dest, temp; UNDEF_LSMNoRegs; UNDEF_LSMPCBase; UNDEF_LSMBaseInListWb; BUSUSEDINCPCS; #ifndef MODE32 if (ADDREXCEPT (address)) INTERNALABORT (address); #endif /* chy 2004-05-23, may write twice if (BIT (21) && LHSReg != 15) LSBase = WBBase; */ if (!BIT (15) && state->Bank != USERBANK) { /* Temporary reg bank switch. */ (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); UNDEF_LSMUserBankWb; } /* N cycle first. */ for (temp = 0; !BIT (temp); temp++); dest = ARMul_LoadWordN (state, address); if (!state->abortSig) state->Reg[temp++] = dest; else if (!state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } /*chy 2004-05-23 chy goto end*/ if (state->Aborted) goto L_ldm_s_makeabort; /* S cycles from here on. */ for (; temp < 16; temp++) if (BIT (temp)) { /* Load this register. */ address += 4; dest = ARMul_LoadWordS (state, address); if (!state->abortSig && !state->Aborted) state->Reg[temp] = dest; else if (!state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } /*chy 2004-05-23 chy goto end */ if (state->Aborted) goto L_ldm_s_makeabort; } /*chy 2004-05-23 label of ldm_s_makeabort*/ L_ldm_s_makeabort: /*chy 2004-06-06 LSBase process should be here, not in the end of this function. Because ARMul_CPSRAltered maybe change R13(SP) R14(lr). If not, simulate INSTR ldmia sp!,[....pc]^ error.*/ /*chy 2004-05-23 should compare the Abort Models*/ if (state->Aborted) { if (BIT (21) && LHSReg != 15) if (! (state->abortSig && state->Aborted && state->lateabtSig == LOW)) LSBase = WBBase; TAKEABORT; } else if (BIT (21) && LHSReg != 15) LSBase = WBBase; if (BIT (15) && !state->Aborted) { /* PC is in the reg list. */ #ifdef MODE32 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode != USER26MODE && state->Mode != USER32MODE ){ state->Cpsr = GETSPSR (state->Bank); ARMul_CPSRAltered (state); } WriteR15 (state, PC); #else //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode == USER26MODE || state->Mode == USER32MODE ) { /* Protect bits in user mode. */ ASSIGNN ((state->Reg[15] & NBIT) != 0); ASSIGNZ ((state->Reg[15] & ZBIT) != 0); ASSIGNC ((state->Reg[15] & CBIT) != 0); ASSIGNV ((state->Reg[15] & VBIT) != 0); } else ARMul_R15Altered (state); FLUSHPIPE; #endif } //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (!BIT (15) && state->Mode != USER26MODE && state->Mode != USER32MODE ) /* Restore the correct bank. */ (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); /* To write back the final register. */ ARMul_Icycles (state, 1, 0L); /* chy 2004-05-23, see below if (state->Aborted) { if (BIT (21) && LHSReg != 15) LSBase = WBBase; TAKEABORT; } */ } /* This function does the work of storing the registers listed in an STM instruction, when the S bit is clear. The code here is always increment after, it's up to the caller to get the input address correct and to handle base register modification. */ static void StoreMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) { ARMword temp; UNDEF_LSMNoRegs; UNDEF_LSMPCBase; UNDEF_LSMBaseInListWb; if (!TFLAG) /* N-cycle, increment the PC and update the NextInstr state. */ BUSUSEDINCPCN; #ifndef MODE32 if (VECTORACCESS (address) || ADDREXCEPT (address)) INTERNALABORT (address); if (BIT (15)) PATCHR15; #endif /* N cycle first. */ for (temp = 0; !BIT (temp); temp++); #ifdef MODE32 ARMul_StoreWordN (state, address, state->Reg[temp++]); #else if (state->Aborted) { (void) ARMul_LoadWordN (state, address); /* Fake the Stores as Loads. */ for (; temp < 16; temp++) if (BIT (temp)) { /* Save this register. */ address += 4; (void) ARMul_LoadWordS (state, address); } if (BIT (21) && LHSReg != 15) LSBase = WBBase; TAKEABORT; return; } else ARMul_StoreWordN (state, address, state->Reg[temp++]); #endif if (state->abortSig && !state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } //chy 2004-05-23, needn't store other when aborted if (state->Aborted) goto L_stm_takeabort; /* S cycles from here on. */ for (; temp < 16; temp++) if (BIT (temp)) { /* Save this register. */ address += 4; ARMul_StoreWordS (state, address, state->Reg[temp]); if (state->abortSig && !state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } //chy 2004-05-23, needn't store other when aborted if (state->Aborted) goto L_stm_takeabort; } //chy 2004-05-23,should compare the Abort Models L_stm_takeabort: if (BIT (21) && LHSReg != 15) { if (! (state->abortSig && state->Aborted && state->lateabtSig == LOW)) LSBase = WBBase; } if (state->Aborted) TAKEABORT; } /* This function does the work of storing the registers listed in an STM instruction when the S bit is set. The code here is always increment after, it's up to the caller to get the input address correct and to handle base register modification. */ static void StoreSMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) { ARMword temp; UNDEF_LSMNoRegs; UNDEF_LSMPCBase; UNDEF_LSMBaseInListWb; BUSUSEDINCPCN; #ifndef MODE32 if (VECTORACCESS (address) || ADDREXCEPT (address)) INTERNALABORT (address); if (BIT (15)) PATCHR15; #endif if (state->Bank != USERBANK) { /* Force User Bank. */ (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); UNDEF_LSMUserBankWb; } for (temp = 0; !BIT (temp); temp++); /* N cycle first. */ #ifdef MODE32 ARMul_StoreWordN (state, address, state->Reg[temp++]); #else if (state->Aborted) { (void) ARMul_LoadWordN (state, address); for (; temp < 16; temp++) /* Fake the Stores as Loads. */ if (BIT (temp)) { /* Save this register. */ address += 4; (void) ARMul_LoadWordS (state, address); } if (BIT (21) && LHSReg != 15) LSBase = WBBase; TAKEABORT; return; } else ARMul_StoreWordN (state, address, state->Reg[temp++]); #endif if (state->abortSig && !state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } //chy 2004-05-23, needn't store other when aborted if (state->Aborted) goto L_stm_s_takeabort; /* S cycles from here on. */ for (; temp < 16; temp++) if (BIT (temp)) { /* Save this register. */ address += 4; ARMul_StoreWordS (state, address, state->Reg[temp]); if (state->abortSig && !state->Aborted) { XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); state->Aborted = ARMul_DataAbortV; } //chy 2004-05-23, needn't store other when aborted if (state->Aborted) goto L_stm_s_takeabort; } //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode != USER26MODE && state->Mode != USER32MODE ) /* Restore the correct bank. */ (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); //chy 2004-05-23,should compare the Abort Models L_stm_s_takeabort: if (BIT (21) && LHSReg != 15) { if (! (state->abortSig && state->Aborted && state->lateabtSig == LOW)) LSBase = WBBase; } if (state->Aborted) TAKEABORT; } /* This function does the work of adding two 32bit values together, and calculating if a carry has occurred. */ static ARMword Add32 (ARMword a1, ARMword a2, int *carry) { ARMword result = (a1 + a2); unsigned int uresult = (unsigned int) result; unsigned int ua1 = (unsigned int) a1; /* If (result == RdLo) and (state->Reg[nRdLo] == 0), or (result > RdLo) then we have no carry. */ if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1)) *carry = 1; else *carry = 0; return result; } /* This function does the work of multiplying two 32bit values to give a 64bit result. */ static unsigned Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc) { /* Operand register numbers. */ int nRdHi, nRdLo, nRs, nRm; ARMword RdHi = 0, RdLo = 0, Rm; /* Cycle count. */ int scount; nRdHi = BITS (16, 19); nRdLo = BITS (12, 15); nRs = BITS (8, 11); nRm = BITS (0, 3); /* Needed to calculate the cycle count. */ Rm = state->Reg[nRm]; /* Check for illegal operand combinations first. */ if (nRdHi != 15 && nRdLo != 15 && nRs != 15 && nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm) { /* Intermediate results. */ ARMword lo, mid1, mid2, hi; int carry; ARMword Rs = state->Reg[nRs]; int sign = 0; if (msigned) { /* Compute sign of result and adjust operands if necessary. */ sign = (Rm ^ Rs) & 0x80000000; if (((signed int) Rm) < 0) Rm = -Rm; if (((signed int) Rs) < 0) Rs = -Rs; } /* We can split the 32x32 into four 16x16 operations. This ensures that we do not lose precision on 32bit only hosts. */ lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF)); mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF)); hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care to propogate the carries from the additions. */ RdLo = Add32 (lo, (mid1 << 16), &carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), &carry); RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); if (sign) { /* Negate result if necessary. */ RdLo = ~RdLo; RdHi = ~RdHi; if (RdLo == 0xFFFFFFFF) { RdLo = 0; RdHi += 1; } else RdLo += 1; } state->Reg[nRdLo] = RdLo; state->Reg[nRdHi] = RdHi; } else fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS\n"); if (scc) /* Ensure that both RdHi and RdLo are used to compute Z, but don't let RdLo's sign bit make it to N. */ ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); /* The cycle count depends on whether the instruction is a signed or unsigned multiply, and what bits are clear in the multiplier. */ if (msigned && (Rm & ((unsigned) 1 << 31))) /* Invert the bits to make the check against zero. */ Rm = ~Rm; if ((Rm & 0xFFFFFF00) == 0) scount = 1; else if ((Rm & 0xFFFF0000) == 0) scount = 2; else if ((Rm & 0xFF000000) == 0) scount = 3; else scount = 4; return 2 + scount; } /* This function does the work of multiplying two 32bit values and adding a 64bit value to give a 64bit result. */ static unsigned MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc) { unsigned scount; ARMword RdLo, RdHi; int nRdHi, nRdLo; int carry = 0; nRdHi = BITS (16, 19); nRdLo = BITS (12, 15); RdHi = state->Reg[nRdHi]; RdLo = state->Reg[nRdLo]; scount = Multiply64 (state, instr, msigned, LDEFAULT); RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry); RdHi = (RdHi + state->Reg[nRdHi]) + carry; state->Reg[nRdLo] = RdLo; state->Reg[nRdHi] = RdHi; if (scc) /* Ensure that both RdHi and RdLo are used to compute Z, but don't let RdLo's sign bit make it to N. */ ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); /* Extra cycle for addition. */ return scount + 1; } /* Attempt to emulate an ARMv6 instruction. Returns non-zero upon success. */ static int handle_v6_insn (ARMul_State * state, ARMword instr) { switch (BITS (20, 27)) { #if 0 case 0x03: printf ("Unhandled v6 insn: ldr\n"); break; case 0x04: printf ("Unhandled v6 insn: umaal\n"); break; case 0x06: printf ("Unhandled v6 insn: mls/str\n"); break; case 0x16: printf ("Unhandled v6 insn: smi\n"); break; case 0x18: printf ("Unhandled v6 insn: strex\n"); break; case 0x19: printf ("Unhandled v6 insn: ldrex\n"); break; case 0x1a: printf ("Unhandled v6 insn: strexd\n"); break; case 0x1b: printf ("Unhandled v6 insn: ldrexd\n"); break; case 0x1c: printf ("Unhandled v6 insn: strexb\n"); break; case 0x1d: printf ("Unhandled v6 insn: ldrexb\n"); break; case 0x1e: printf ("Unhandled v6 insn: strexh\n"); break; case 0x1f: printf ("Unhandled v6 insn: ldrexh\n"); break; case 0x30: printf ("Unhandled v6 insn: movw\n"); break; case 0x32: printf ("Unhandled v6 insn: nop/sev/wfe/wfi/yield\n"); break; case 0x34: printf ("Unhandled v6 insn: movt\n"); break; case 0x3f: printf ("Unhandled v6 insn: rbit\n"); break; #endif case 0x61: printf ("Unhandled v6 insn: sadd/ssub\n"); break; case 0x62: printf ("Unhandled v6 insn: qadd/qsub\n"); break; case 0x63: printf ("Unhandled v6 insn: shadd/shsub\n"); break; case 0x65: printf ("Unhandled v6 insn: uadd/usub\n"); break; case 0x66: printf ("Unhandled v6 insn: uqadd/uqsub\n"); break; case 0x67: printf ("Unhandled v6 insn: uhadd/uhsub\n"); break; case 0x68: printf ("Unhandled v6 insn: pkh/sxtab/selsxtb\n"); break; case 0x6c: printf ("Unhandled v6 insn: uxtb16/uxtab16\n"); break; case 0x70: printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n"); break; case 0x74: printf ("Unhandled v6 insn: smlald/smlsld\n"); break; case 0x75: printf ("Unhandled v6 insn: smmla/smmls/smmul\n"); break; case 0x78: printf ("Unhandled v6 insn: usad/usada8\n"); break; case 0x7a: printf ("Unhandled v6 insn: usbfx\n"); break; case 0x7c: printf ("Unhandled v6 insn: bfc/bfi\n"); break; case 0x6a: { ARMword Rm; int ror = -1; switch (BITS (4, 11)) { case 0x07: ror = 0; break; case 0x47: ror = 8; break; case 0x87: ror = 16; break; case 0xc7: ror = 24; break; case 0x01: case 0xf3: printf ("Unhandled v6 insn: ssat\n"); return 0; default: break; } if (ror == -1) { if (BITS (4, 6) == 0x7) { printf ("Unhandled v6 insn: ssat\n"); return 0; } break; } Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF); if (Rm & 0x80) Rm |= 0xffffff00; if (BITS (16, 19) == 0xf) /* SXTB */ state->Reg[BITS (12, 15)] = Rm; else /* SXTAB */ state->Reg[BITS (12, 15)] += Rm; } return 1; case 0x6b: { ARMword Rm; int ror = -1; switch (BITS (4, 11)) { case 0x07: ror = 0; break; case 0x47: ror = 8; break; case 0x87: ror = 16; break; case 0xc7: ror = 24; break; case 0xfb: printf ("Unhandled v6 insn: rev\n"); return 0; default: break; } if (ror == -1) break; Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF); if (Rm & 8000) Rm |= 0xffff0000; if (BITS (16, 19) == 0xf) /* SXTH */ state->Reg[BITS (12, 15)] = Rm; else /* SXTAH */ state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; } return 1; case 0x6e: { ARMword Rm; int ror = -1; switch (BITS (4, 11)) { case 0x07: ror = 0; break; case 0x47: ror = 8; break; case 0x87: ror = 16; break; case 0xc7: ror = 24; break; case 0x01: case 0xf3: printf ("Unhandled v6 insn: usat\n"); return 0; default: break; } if (ror == -1) { if (BITS (4, 6) == 0x7) { printf ("Unhandled v6 insn: usat\n"); return 0; } break; } Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF); if (BITS (16, 19) == 0xf) /* UXTB */ state->Reg[BITS (12, 15)] = Rm; else /* UXTAB */ state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; } return 1; case 0x6f: { ARMword Rm; int ror = -1; switch (BITS (4, 11)) { case 0x07: ror = 0; break; case 0x47: ror = 8; break; case 0x87: ror = 16; break; case 0xc7: ror = 24; break; case 0xfb: printf ("Unhandled v6 insn: revsh\n"); return 0; default: break; } if (ror == -1) break; Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF); if (BITS (16, 19) == 0xf) /* UXT */ state->Reg[BITS (12, 15)] = Rm; else { /* UXTAH */ state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; } } return 1; #if 0 case 0x84: printf ("Unhandled v6 insn: srs\n"); break; #endif default: break; } printf ("Unhandled v6 insn: UNKNOWN: %08x\n", instr); return 0; } ������������������skyeye-1.2.5_REL/arch/arm/common/armsym.c�����������������������������������������������������������0000644�0001750�0000144�00000050240�10541455476�016712� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armsym.c -- Main instruction emulation: SA11x Instruction Emulator. Copyright (C) 2001 Princeton University This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <assert.h> #include "bfd.h" #include <search.h> #include "armsym.h" #include "armdefs.h" static char itoa_tab[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f' }; static int storage_needed; static asymbol **symbol_table; static unsigned int number_of_symbols, kernel_number; static SYM_FUNC trap_sym = { "Trap", 0, 0, 0 }; static SYM_FUNC init_sym = { "Init", 0, 0, 0 }; /* <tktan> BUG200103311736 */ static FUNC_NODE init_node = { &init_sym, 0, 0, 0 }; static ARMword debug; #if 0 void ARMul_InitSymTable () { int i, j, digit; ENTRY newentry, *oldentry; SYM_FUNC *symp; asymbol *symptr; int key; bfd *appl_bfd; bfd *abfd; int appl_storage_needed; abfd = bfd_openr ("./vmlinux", 0); /* <tktan> BUG200105221946 : get symbol from usrappl */ appl_bfd = bfd_openr ("init/usrappl", 0); if (appl_bfd == NULL) { printf ("Can't open init/usrappl\n"); exit (0); } if (!bfd_check_format (appl_bfd, bfd_object)) { printf ("Wrong format\n"); exit (0); } appl_storage_needed = bfd_get_symtab_upper_bound (appl_bfd); if (appl_storage_needed < 0) { printf ("FAIL\n"); exit (0); } /* <tktan> BUG200105221946 */ if (!bfd_check_format (abfd, bfd_object)) { printf ("Wrong format\n"); exit (0); } storage_needed = bfd_get_symtab_upper_bound (abfd); if (storage_needed < 0) { printf ("FAIL\n"); exit (0); } // <tktan> BUG200105221946 :symbol_table = (asymbol **) malloc (storage_needed); symbol_table = (asymbol **) malloc (appl_storage_needed + storage_needed); number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); kernel_number = number_of_symbols; /* <tktan> BUG200106022219 */ if (number_of_symbols < 0) { printf ("FAIL\n"); exit (0); } /* <tktan> BUG200105221946 */ number_of_symbols += bfd_canonicalize_symtab (appl_bfd, &(symbol_table[number_of_symbols])); // printf("Number of symbols = %d\n", number_of_symbols) ; if (!hcreate (number_of_symbols << 1)) { printf ("Not enough memory for hash table\n"); exit (0); } for (i = 0; i < number_of_symbols; i++) { symptr = symbol_table[i]; key = symptr->value + symptr->section->vma; // adjust for section address if (((i < kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 ((i < kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654 (symbol_table[i]->flags & 0x10)) { // Is a function symbol // printf("%x %8x %s\n", symbol_table[i]->flags, key, symbol_table[i]->name); // *********************************************************** // This is converting the function symbol value to char string // and use it as a key in the GNU hash table // ******************************************************** newentry.key = (char *) malloc (9); for (j = 0; j < 8; j++) { newentry.key[j] = itoa_tab[((key) >> (j << 2)) & 0xf]; } newentry.key[8] = 0; // ************************************************* // This is allocating memory for a struct funcsym // ************************************************* symp = (SYM_FUNC *) malloc (sizeof (SYM_FUNC)); newentry.data = (char *) symp; symp->name = (char *) symbol_table[i]->name; symp->total_cycle = 0; symp->total_energy = 0; symp->instances = 0; // *********************************************** // Insert into hash table // ******************************************* /* <tktan> BUG200106022219 */ oldentry = hsearch (newentry, FIND); if (oldentry) { // was entered // printf("Duplicate Symbol: %x %s\n", key, symp->name); oldentry->data = (char *) symp; } else if (!hsearch (newentry, ENTER)) { printf ("Insufficient memory\n"); exit (0); } } } return; } #else /************************************************************************** This function read the symbol list and store into a table It then generates a hash table based on the value of function symbol and the data is the pointer to struct funcsym defined in armsym.h The GNU hash table is used. **************************************************************************/ /*************** * added by ksh ***************/ void ARMul_InitSymTable (char *filename) { int i, j, digit; ENTRY newentry, *oldentry; SYM_FUNC *symp; asymbol *symptr; int key; bfd *abfd; printf ("call ARMul_InitSymTable,kernle filename is %s. \n", filename); if (!filename) { printf ("Can not get correct kernel filename!Maybe your skyeye.conf have something wrong!\n"); skyeye_exit (-1); } /* <tktan> BUG200105221946 : get symbol from usrappl */ abfd = bfd_openr (filename, 0); /* <tktan> BUG200105221946 : get symbol from usrappl */ /* <tktan> BUG200105221946 */ if (!bfd_check_format (abfd, bfd_object)) { printf ("Wrong format\n"); skyeye_exit (0); } storage_needed = bfd_get_symtab_upper_bound (abfd); if (storage_needed < 0) { printf ("FAIL\n"); skyeye_exit (0); } // <tktan> BUG200105221946 :symbol_table = (asymbol **) malloc (storage_needed); symbol_table = (asymbol **) malloc (storage_needed); number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); kernel_number = number_of_symbols; /* <tktan> BUG200106022219 */ if (number_of_symbols < 0) { printf ("FAIL\n"); skyeye_exit (0); } if (!hcreate (number_of_symbols << 1)) { printf ("Not enough memory for hash table\n"); skyeye_exit (0); } for (i = 0; i < number_of_symbols; i++) { symptr = symbol_table[i]; key = symptr->value + symptr->section->vma; // adjust for section address if (((i < kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 ((i < kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654 (symbol_table[i]->flags & 0x10)) { // Is a function symbol // printf("%x %8x %s\n", symbol_table[i]->flags, key, symbol_table[i]->name); // *********************************************************** // This is converting the function symbol value to char string // and use it as a key in the GNU hash table // ******************************************************** newentry.key = (char *) malloc (9); for (j = 0; j < 8; j++) { newentry.key[j] = itoa_tab[((key) >> (j << 2)) & 0xf]; } newentry.key[8] = 0; // ************************************************* // This is allocating memory for a struct funcsym // ************************************************* symp = (SYM_FUNC *) malloc (sizeof (SYM_FUNC)); newentry.data = (char *) symp; symp->name = (char *) symbol_table[i]->name; symp->total_cycle = 0; symp->total_energy = 0; symp->instances = 0; // *********************************************** // Insert into hash table // ******************************************* /* <tktan> BUG200106022219 */ oldentry = hsearch (newentry, FIND); if (oldentry) { // was entered // printf("Duplicate Symbol: %x %s\n", key, symp->name); oldentry->data = (char *) symp; } else if (!hsearch (newentry, ENTER)) { printf ("Insufficient memory\n"); skyeye_exit (0); } } } return; } #endif /*************************************************************** This function get check the hash table for an entry If it exists, the corresponding pointer to the SYM_FUNC will be returned *************************************************************/ SYM_FUNC * ARMul_GetSym (ARMword address) { int j; ENTRY entry, *ep; char text[9]; SYM_FUNC *symp; //printf("GetSym %x\n", address); entry.key = text; for (j = 0; j < 8; j++) { entry.key[j] = itoa_tab[(address >> (j << 2)) & 0xf]; } entry.key[8] = 0; /*a bug need to fixed */ ep = hsearch (entry, FIND); if (ep != 0) { symp = (SYM_FUNC *) ep->data; return (symp); } else return (0); } /*************************************** * Function to initialize the energy profiling tree root ***************************************************/ void ARMul_ProfInit (ARMul_State * state) { /* <tktan> BUG200103311736 */ TASK_STACK *tsp; printf ("call ARMul_ProfInit \n"); tsp = malloc (sizeof (TASK_STACK)); if (tsp <= 0) { printf ("Memory allocation error in ARMul_ProfInit \n"); skyeye_exit (-1); } state->energy.cur_task = (void *) tsp; tsp->task_id = 0xc00f0000; // where the INIT_TASK reside memcpy (&(tsp->func_stack[0]), &init_node, sizeof (FUNC_NODE)); tsp->level = 0; tsp->total_energy = 0; tsp->total_cycle = 0; tsp->next = tsp; return; } /**************************************** * Function to create child function node ****************************************/ FUNC_NODE * ARMul_CreateChild (ARMul_State * state) { TASK_STACK *tsp; int level; FUNC_NODE *fnp; tsp = (TASK_STACK *) state->energy.cur_task; (tsp->level)++; level = tsp->level; /* <tktan> BUG200105311233 */ if (level >= MAX_LEVEL) { printf ("ARMul_CreateChild failed\n"); assert (0); } fnp = &(tsp->func_stack[level]); // printf("Create Child!\n "); fnp->tenergy = tsp->total_energy; fnp->tcycle = tsp->total_cycle; return (fnp); } /****************************************** * Function to destroy child nodes *****************************************/ void ARMul_DestroyChild (ARMul_State * state) { TASK_STACK *tsp; int level; long long fenergy; long long fcycle; FUNC_NODE *fnp; tsp = (TASK_STACK *) state->energy.cur_task; level = tsp->level; fnp = &(tsp->func_stack[level]); // <tktan> BUG200105222137 fenergy = state->t_energy - fnp->tenergy; fenergy = tsp->total_energy - fnp->tenergy; fcycle = tsp->total_cycle - fnp->tcycle; /* <tktan> BUG200105181702 */ if ((state->energy.enable_func_energy) && !(strcmp (state->energy.func_energy, fnp->func_symbol->name))) { printf ("energy_report %s %f\n", fnp->func_symbol->name, fenergy); } /* <tktan> BUG200104101936 */ if (state->energy.energy_prof) { fnp->func_symbol->total_energy += fenergy; fnp->func_symbol->total_cycle += fcycle; (fnp->func_symbol->instances)++; } //printf("Destroy child,name %s \n",fnp->func_symbol->name); tsp->level = level - 1; return; } /************************************************ Function to check the different kind of branch ************************************************/ void ARMul_CallCheck (ARMul_State * state, ARMword cur_pc, ARMword to_pc, ARMword instr) { FUNC_NODE *child_node; TASK_STACK *tsp; SYM_FUNC *symp; int i, bt, level; ARMword new_task_id, fp_value; tsp = (TASK_STACK *) state->energy.cur_task; level = tsp->level; fp_value = state->Reg[11]; // BUG200311301153 #if 0 if (debug != tsp->task_id || !debug) { printf ("cur_task is changed! %x \n", tsp->task_id); debug = tsp->task_id; } #endif /* <tktan> BUG200105311233 */ if (level >= MAX_LEVEL) { printf ("ARMul_CallCheck failed\n"); printf ("level %d \n", level); //exit(-1); } // First check if it is normal return if (to_pc == (tsp->func_stack[level].ret_addr + 4)) { if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ //if(1){ printf ("[%x:%d:%x] Function return %s (%x)--> %s (%x)\n", tsp->task_id, level, fp_value, tsp->func_stack[level].func_symbol->name, cur_pc, tsp->func_stack[level - 1].func_symbol->name, to_pc); } /* <tktan> BUG200104101736 */ ARMul_DestroyChild (state); return; } // Check if it is a trap return // a trap return is one that jump to a saved interrupted address, saved // in .ret_addr bt = 0; while ((level - bt >= 0) && (bt <= 3)) { if (to_pc == tsp->func_stack[level - bt].ret_addr) { if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ printf ("[%x:%d:%x] Trap Return -> %s\n", tsp->task_id, level, fp_value, tsp->func_stack[level - bt - 1].func_symbol->name); } /* <tktan> BUG200104101736 */ for (i = 0; i <= bt; i++) { ARMul_DestroyChild (state); } return; } bt++; } // BUG200311212039 // check if it is a recursive call, or I was missing some returns through // abnormal jumps bt = 0; while ((level - bt >= 0) && (bt <= 2)) { if (to_pc == tsp->func_stack[level - bt].func_start_addr) { if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ printf ("[%x:%d:%x] Function %s ended\n", tsp->task_id, level, fp_value, tsp->func_stack[level - bt].func_symbol-> name); } /* <tktan> BUG200104101736 */ for (i = 0; i <= bt; i++) { ARMul_DestroyChild (state); } } bt++; } tsp = (TASK_STACK *) state->energy.cur_task; level = tsp->level; // check if it is a trap //if (!(to_pc & 0xffffffe0) && (state->Reg[14] == (cur_pc+4))) { // check for pc from 0x0 - 0x1f // BUG200311302126: Reg[14]_abt is cur_pc+8 for DataAbort, // but cur_pc+4 for other exception. So, better not check it if (!(to_pc & 0xffffffe0)) { // check for pc from 0x0 - 0x1f child_node = ARMul_CreateChild (state); /* <tktan> BUG200104101736 */ child_node->ret_addr = cur_pc; child_node->func_start_addr = to_pc; child_node->func_symbol = &trap_sym; if (state->energy.func_display & state->energy.func_disp_start) { /* <tktan> BUG200104191428 */ printf ("[%x:%d:%x] Function %s(%x) --> Trap %x\n", tsp->task_id, level, fp_value, tsp->func_stack[level].func_symbol->name, cur_pc, to_pc); } return; } // Check if it is a function call if ((state->Reg[14] == (cur_pc + 4)) || /* <tktan> BUG200105172030 */ (BITS (20, 27) & 0xf0) == 0xb0) { /* <tktan> BUG200104012116 */ symp = ARMul_GetSym (to_pc); if (symp) { // it is an entry into a function child_node = ARMul_CreateChild (state); /* <tktan> BUG2001040101736 */ child_node->ret_addr = cur_pc; child_node->func_start_addr = to_pc; child_node->func_symbol = symp; /* <tktan> BUG200105211055 : perform task switch */ if (!strcmp (symp->name, "__switch_to")) { // BUG200204021340 ARMul_TaskSwitch (state); } if (!strcmp (symp->name, "copy_thread")) { new_task_id = ARMul_TaskCreate (state); } } } /* <tktan> BUG200104012116 */ // Just a normal branch, maybe return; } /* <tktan> BUG200105211055 : perform task switch */ void ARMul_TaskSwitch (ARMul_State * state) { TASK_STACK *ctsp, *oldtsp, *newtsp; //ARMword to_thread_id; ARMword to_task_id; int done = 0; //to_thread_id = state->Reg[2] ; // r1, the to_task task structure to_task_id = state->Reg[7]; oldtsp = (TASK_STACK *) state->energy.cur_task; //printf("cur_task id %x \n",state->Reg[0]); oldtsp->task_id = state->Reg[0]; /* <tktan> BUG200106051701 */ //printf("Task ThreadInfo Switch from %x to %x\n", oldtsp->thread_id, to_thread_id); //printf("task switch from %x to %x \n",oldtsp->task_id,to_task_id); ctsp = oldtsp->next; while (!done && (ctsp != oldtsp)) { if (ctsp->task_id == to_task_id) { done = 1; newtsp = ctsp; } // printf("ctsp taskid=%x,next task_id=%x \n",ctsp->task_id,ctsp->next->task_id); ctsp = ctsp->next; } if (done) state->energy.cur_task = (void *) newtsp; else { printf ("Error : Can not find task stack\n"); //print_allTask(state); skyeye_exit (-1); } } void print_allTask (ARMul_State * state) { TASK_STACK *ctsp, *oldtsp, *newtsp; ARMword to_task_id; oldtsp = (TASK_STACK *) state->energy.cur_task; ctsp = oldtsp; #if 0 printf ("Begin to print all task...\n"); do { printf ("ctsp taskid=%x,next task_id=%x \n", ctsp->task_id, ctsp->next->task_id); ctsp = ctsp->next; } while (ctsp != oldtsp); printf ("End to print....\n"); #endif } /* <tktan> BUG200105211055 : create new task stack */ ARMword ARMul_TaskCreate (ARMul_State * state) { TASK_STACK *oldtsp, *newtsp, *oldnext; ARMword to_task_id; int i; to_task_id = state->Reg[3]; // r3, the to_task task structure if (to_task_id == 0x00000000) { // BUG200204081717 to_task_id = state->Reg[5]; // r5 store the to_task task structure } oldtsp = (TASK_STACK *) state->energy.cur_task; newtsp = malloc (sizeof (TASK_STACK)); memcpy (newtsp, oldtsp, sizeof (TASK_STACK)); newtsp->task_id = to_task_id; newtsp->level -= 2; // point to the SWI level /* <tktan> BUG200105222137 */ newtsp->total_cycle = 0; // newtsp->total_energy = 0.0; BUG200106142205, possible problem newtsp->total_energy = 0; for (i = 0; i <= newtsp->level; i++) { newtsp->func_stack[i].tcycle = 0; newtsp->func_stack[i].tenergy = 0; } /* put newtsp after oldtsp */ oldnext = oldtsp->next; oldtsp->next = newtsp; newtsp->next = oldnext; //printf("Create a new task,task_id=%x \n",to_task_id); //print_allTask(state); return (to_task_id); } /******************************************** * Function to report energy tree *******************************************/ void ARMul_ReportEnergy (ARMul_State * state, FILE * pf) { int i, j; ENTRY entry, *ep; char text[9]; SYM_FUNC *symp; asymbol *symptr; ARMword address; TASK_STACK *ctsp, *oldtsp; float energy; ARMul_Consolidate (state); // <tktan> BUG200105222137 for (i = 0; i < number_of_symbols; i++) { symptr = symbol_table[i]; address = symptr->value + symptr->section->vma; // adjust for section address if (((i < kernel_number) && (symbol_table[i]->flags == 0x01)) || // <tktan> BUG200105172154, BUG200106022219 ((i < kernel_number) && (symbol_table[i]->flags == 0x02)) || // <tktan> BUG200204051654, BUG200311211406 (symbol_table[i]->flags & 0x10)) { // Is a function symbol // *********************************************************** // This is converting the function symbol value to char string // and use it as a key in the GNU hash table // ******************************************************** entry.key = text; for (j = 0; j < 8; j++) { entry.key[j] = itoa_tab[(address >> (j << 2)) & 0xf]; } entry.key[8] = 0; ep = hsearch (entry, FIND); if (ep != 0) { symp = (SYM_FUNC *) ep->data; /*modified by ksh for evaluate the usrappl program only */ /* if(strncmp(symp->name,"usrappl",7) != 0){ continue; } */ if (symp->instances > 0) { // only show if executed energy = symp->total_energy; fprintf (pf, "%s %d %lld %f\n", symp->name, symp->instances, symp->total_cycle, energy); } } } } /* <tktan> BUG200105222137 : print out task energy */ oldtsp = (TASK_STACK *) state->energy.cur_task; ctsp = oldtsp; do { energy = ctsp->total_energy; fprintf (pf, "Task[%x] %lld %f\n", ctsp->task_id, ctsp->total_cycle, energy); ctsp = ctsp->next; } while (ctsp != oldtsp); } /* <tktan> BUG200105222137 : consolidate unfinished function energy */ void ARMul_Consolidate (ARMul_State * state) { long long fenergy; // <tktan> BUG200106142205 long long fcycle; // <tktan> BUG200106142205 FUNC_NODE *fnp; TASK_STACK *ctsp, *oldtsp; int i; double energy; /* <tktan> BUG200105222137 : report energy for tasks */ /* <tktan> BUG200106041235 : use do instead of while */ oldtsp = (TASK_STACK *) state->energy.cur_task; ctsp = oldtsp; do { for (i = ctsp->level; i >= 0; i--) { fnp = &(ctsp->func_stack[i]); fenergy = ctsp->total_energy - fnp->tenergy; fcycle = ctsp->total_cycle - fnp->tcycle; /* copied from <tktan> BUG200105181702 */ if ((state->energy.enable_func_energy) && !(strcmp (state->energy.func_energy, fnp->func_symbol->name))) { //energy = I2ENERGY(fenergy); //fprintf(pf,"energy_report %s %f\n", fnp->func_symbol->name, energy); } /* copied from <tktan> BUG200104101936 */ fnp->func_symbol->total_energy += fenergy; fnp->func_symbol->total_cycle += fcycle; (fnp->func_symbol->instances)++; } ctsp = ctsp->next; } while (ctsp != oldtsp); } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armdefs.h����������������������������������������������������������0000644�0001750�0000144�00000074550�11006120657�017025� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _ARMDEFS_H_ #define _ARMDEFS_H_ #include <stdio.h> #include <stdlib.h> #include <errno.h> //teawater add for arm2x86 2005.02.14------------------------------------------- // koodailar remove it for mingw 2005.12.18---------------- //anthonylee modify it for portable 2007.01.30 #include "portable/mman.h" //AJ2D-------------------------------------------------------------------------- //teawater add for arm2x86 2005.07.03------------------------------------------- #include <sys/types.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include <unistd.h> #include <errno.h> #include <sys/stat.h> #include <fcntl.h> //AJ2D-------------------------------------------------------------------------- //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #include <signal.h> #include <sys/time.h> //#define DBCT_TEST_SPEED #define DBCT_TEST_SPEED_SEC 10 //AJ2D-------------------------------------------------------------------------- //teawater add compile switch for DBCT GDB RSP function 2005.10.21-------------- //#define DBCT_GDBRSP //AJ2D-------------------------------------------------------------------------- #include <skyeye_defs.h> #define ARM_BYTE_TYPE 0 #define ARM_HALFWORD_TYPE 1 #define ARM_WORD_TYPE 2 //the define of cachetype #define NONCACHE 0 #define DATACACHE 1 #define INSTCACHE 2 #ifndef __STDC__ typedef char *VoidStar; #endif typedef unsigned long long ARMdword; /* must be 64 bits wide */ typedef unsigned int ARMword; /* must be 32 bits wide */ typedef unsigned char ARMbyte; /* must be 8 bits wide */ typedef unsigned short ARMhword; /* must be 16 bits wide */ typedef struct ARMul_State ARMul_State; typedef struct ARMul_io ARMul_io; typedef struct ARMul_Energy ARMul_Energy; //teawater add for arm2x86 2005.06.24------------------------------------------- #include <stdint.h> //AJ2D-------------------------------------------------------------------------- /* //chy 2005-05-11 #ifndef __CYGWIN__ //teawater add for arm2x86 2005.02.14------------------------------------------- typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned int uint32_t; #if defined (__x86_64__) typedef unsigned long uint64_t; #else typedef unsigned long long uint64_t; #endif ////AJ2D-------------------------------------------------------------------------- #endif */ #include "armmmu.h" #include "armmem.h" #include "armio.h" #include "lcd/skyeye_lcd.h" #include "skyeye.h" #include "skyeye_device.h" #include "net/skyeye_net.h" #include "skyeye_config.h" typedef unsigned ARMul_CPInits (ARMul_State * state); typedef unsigned ARMul_CPExits (ARMul_State * state); typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type, ARMword instr, ARMword value); typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type, ARMword instr, ARMword * value); typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type, ARMword instr, ARMword * value); typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type, ARMword instr, ARMword value); typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type, ARMword instr); typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg, ARMword * value); typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg, ARMword value); //added by ksh,2004-3-5 struct ARMul_io { ARMword *instr; //to display the current interrupt state ARMword *net_flag; //to judge if network is enabled ARMword *net_int; //netcard interrupt //ywc,2004-04-01 ARMword *ts_int; ARMword *ts_is_enable; ARMword *ts_addr_begin; ARMword *ts_addr_end; ARMword *ts_buffer; }; /* added by ksh,2004-11-26,some energy profiling */ struct ARMul_Energy { int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */ int enable_func_energy; /* <tktan> BUG200105181702 */ char *func_energy; int func_display; /* <tktan> BUG200103311509 : for function call display */ int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */ char *start_func; /* <tktan> BUG200104191428 */ FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */ long long tcycle, pcycle; float t_energy; void *cur_task; /* <tktan> BUG200103291737 */ long long t_mem_cycle, t_idle_cycle, t_uart_cycle; long long p_mem_cycle, p_idle_cycle, p_uart_cycle; long long p_io_update_tcycle; /*record CCCR,to get current core frequency */ ARMword cccr; }; #define MAX_BANK 8 #define MAX_STR 1024 typedef struct mem_bank { ARMword (*read_byte) (ARMul_State * state, ARMword addr); void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data); ARMword (*read_halfword) (ARMul_State * state, ARMword addr); void (*write_halfword) (ARMul_State * state, ARMword addr, ARMword data); ARMword (*read_word) (ARMul_State * state, ARMword addr); void (*write_word) (ARMul_State * state, ARMword addr, ARMword data); unsigned int addr, len; char filename[MAX_STR]; unsigned type; //chy 2003-09-21: maybe io,ram,rom } mem_bank_t; typedef struct { int bank_num; int current_num; /*current num of bank */ mem_bank_t mem_banks[MAX_BANK]; } mem_config_t; struct ARMul_State { ARMword Emulate; /* to start and stop emulation */ unsigned EndCondition; /* reason for stopping */ unsigned ErrorCode; /* type of illegal instruction */ ARMword Reg[16]; /* the current register file */ ARMword RegBank[7][16]; /* all the registers */ ARMword Cpsr; /* the current psr */ ARMword Spsr[7]; /* the exception psr's */ //chy:2003-08-19, used in arm xscale /* 40 bit accumulator. We always keep this 64 bits wide, and move only 40 bits out of it in an MRA insn. */ ARMdword Accumulator; ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */ //chy:2003-08-19, used in arm v5e|xscale ARMword SFlag; #ifdef MODET ARMword TFlag; /* Thumb state */ #endif ARMword Bank; /* the current register bank */ ARMword Mode; /* the current mode */ ARMword instr, pc, temp; /* saved register state */ ARMword loaded, decoded; /* saved pipeline state */ //chy 2006-04-12 for ICE breakpoint ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/ unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */ unsigned long long NumInstrs; /* the number of instructions executed */ unsigned NextInstr; unsigned VectorCatch; /* caught exception mask */ unsigned CallDebug; /* set to call the debugger */ unsigned CanWatch; /* set by memory interface if its willing to suffer the overhead of checking for watchpoints on each memory access */ unsigned MemReadDebug, MemWriteDebug; unsigned int StopHandle; unsigned char *MemInPtr; /* the Data In bus */ unsigned char *MemOutPtr; /* the Data Out bus (which you may not need */ unsigned char *MemSparePtr; /* extra space */ ARMword MemSize; unsigned char *OSptr; /* OS Handle */ char *CommandLine; /* Command Line from ARMsd */ ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */ ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */ ARMul_LDCs *LDC[16]; /* LDC instruction */ ARMul_STCs *STC[16]; /* STC instruction */ ARMul_MRCs *MRC[16]; /* MRC instruction */ ARMul_MCRs *MCR[16]; /* MCR instruction */ ARMul_CDPs *CDP[16]; /* CDP instruction */ ARMul_CPReads *CPRead[16]; /* Read CP register */ ARMul_CPWrites *CPWrite[16]; /* Write CP register */ unsigned char *CPData[16]; /* Coprocessor data */ unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */ unsigned EventSet; /* the number of events in the queue */ unsigned int Now; /* time to the nearest cycle */ struct EventNode **EventPtr; /* the event list */ unsigned Debug; /* show instructions as they are executed */ unsigned NresetSig; /* reset the processor */ unsigned NfiqSig; unsigned NirqSig; unsigned abortSig; unsigned NtransSig; unsigned bigendSig; unsigned prog32Sig; unsigned data32Sig; /* 2004-05-09 chy ---------------------------------------------------------- read ARM Architecture Reference Manual 2.6.5 Data Abort There are three Abort Model in ARM arch. Early Abort Model: used in some ARMv3 and earlier implementations. In this model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and the base register was unchanged for all other instructions. (oldest) Base Restored Abort Model: If a Data Abort occurs in an instruction which specifies base register writeback, the value in the base register is unchanged. (strongarm, xscale) Base Updated Abort Model: If a Data Abort occurs in an instruction which specifies base register writeback, the base register writeback still occurs. (arm720T) read PART B chap2 The System Control Coprocessor CP15 2.4 Register1:control register L(bit 6): in some ARMv3 and earlier implementations, the abort model of the processor could be configured: 0=early Abort Model Selected(now obsolete) 1=Late Abort Model selceted(same as Base Updated Abort Model) on later processors, this bit reads as 1 and ignores writes. ------------------------------------------------------------- So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) if lateabtSig=0, then it means Base Restored Abort Model */ unsigned lateabtSig; ARMword Vector; /* synthesize aborts in cycle modes */ ARMword Aborted; /* sticky flag for aborts */ ARMword Reseted; /* sticky flag for Reset */ ARMword Inted, LastInted; /* sticky flags for interrupts */ ARMword Base; /* extra hand for base writeback */ ARMword AbortAddr; /* to keep track of Prefetch aborts */ const struct Dbg_HostosInterface *hostif; int verbose; /* non-zero means print various messages like the banner */ mmu_state_t mmu; mem_state_t mem; /*remove io_state to skyeye_mach_*.c files */ //io_state_t io; /* point to a interrupt pending register. now for skyeye-ne2k.c * later should move somewhere. e.g machine_config_t*/ //chy: 2003-08-11, for different arm core type unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ unsigned is_v5; /* Are we emulating a v5 architecture ? */ unsigned is_v5e; /* Are we emulating a v5e architecture ? */ unsigned is_v6; /* Are we emulating a v6 architecture ? */ unsigned is_XScale; /* Are we emulating an XScale architecture ? */ unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */ unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */ //chy 2005-09-19 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */ //chy: seems only used in xscale's CP14 unsigned int LastTime; /* Value of last call to ARMul_Time() */ ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */ //added by ksh:for handle different machs io 2004-3-5 ARMul_io mach_io; /*added by ksh,2004-11-26,some energy profiling*/ ARMul_Energy energy; //teawater add for next_dis 2004.10.27----------------------- int disassemble; //AJ2D------------------------------------------ //teawater add for arm2x86 2005.02.15------------------------------------------- uint32_t trap; uint32_t tea_break_addr; uint32_t tea_break_ok; int tea_pc; //AJ2D-------------------------------------------------------------------------- //teawater add for arm2x86 2005.07.03------------------------------------------- /* * 2007-01-24 removed the term-io functions by Anthony Lee, * moved to "device/uart/skyeye_uart_stdio.c". */ //AJ2D-------------------------------------------------------------------------- //teawater add for arm2x86 2005.07.05------------------------------------------- //arm_arm A2-18 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model //AJ2D-------------------------------------------------------------------------- //teawater change for return if running tb dirty 2005.07.09--------------------- void *tb_now; //AJ2D-------------------------------------------------------------------------- //teawater add for record reg value to ./reg.txt 2005.07.10--------------------- FILE *tea_reg_fd; //AJ2D-------------------------------------------------------------------------- /*added by ksh in 2005-10-1*/ cpu_config_t *cpu; mem_config_t *mem_bank; /* added LPC remap function */ int vector_remap_flag; uint32_t vector_remap_addr; uint32_t vector_remap_size; //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED uint64_t instr_count; #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- }; #define ResetPin NresetSig #define FIQPin NfiqSig #define IRQPin NirqSig #define AbortPin abortSig #define TransPin NtransSig #define BigEndPin bigendSig #define Prog32Pin prog32Sig #define Data32Pin data32Sig #define LateAbortPin lateabtSig /***************************************************************************\ * Types of ARM we know about * \***************************************************************************/ /* The bitflags */ #define ARM_Fix26_Prop 0x01 #define ARM_Nexec_Prop 0x02 #define ARM_Debug_Prop 0x10 #define ARM_Isync_Prop ARM_Debug_Prop #define ARM_Lock_Prop 0x20 //chy 2003-08-11 #define ARM_v4_Prop 0x40 #define ARM_v5_Prop 0x80 #define ARM_v5e_Prop 0x100 #define ARM_XScale_Prop 0x200 #define ARM_ep9312_Prop 0x400 #define ARM_iWMMXt_Prop 0x800 //chy 2005-09-19 #define ARM_PXA27X_Prop 0x1000 /* ARM2 family */ #define ARM2 (ARM_Fix26_Prop) #define ARM2as ARM2 #define ARM61 ARM2 #define ARM3 ARM2 #ifdef ARM60 /* previous definition in armopts.h */ #undef ARM60 #endif /* ARM6 family */ #define ARM6 (ARM_Lock_Prop) #define ARM60 ARM6 #define ARM600 ARM6 #define ARM610 ARM6 #define ARM620 ARM6 /***************************************************************************\ * Macros to extract instruction fields * \***************************************************************************/ #define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */ #define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ #define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */ /***************************************************************************\ * The hardware vector addresses * \***************************************************************************/ #define ARMResetV 0L #define ARMUndefinedInstrV 4L #define ARMSWIV 8L #define ARMPrefetchAbortV 12L #define ARMDataAbortV 16L #define ARMAddrExceptnV 20L #define ARMIRQV 24L #define ARMFIQV 28L #define ARMErrorV 32L /* This is an offset, not an address ! */ #define ARMul_ResetV ARMResetV #define ARMul_UndefinedInstrV ARMUndefinedInstrV #define ARMul_SWIV ARMSWIV #define ARMul_PrefetchAbortV ARMPrefetchAbortV #define ARMul_DataAbortV ARMDataAbortV #define ARMul_AddrExceptnV ARMAddrExceptnV #define ARMul_IRQV ARMIRQV #define ARMul_FIQV ARMFIQV /***************************************************************************\ * Mode and Bank Constants * \***************************************************************************/ #define USER26MODE 0L #define FIQ26MODE 1L #define IRQ26MODE 2L #define SVC26MODE 3L #define USER32MODE 16L #define FIQ32MODE 17L #define IRQ32MODE 18L #define SVC32MODE 19L #define ABORT32MODE 23L #define UNDEF32MODE 27L //chy 2006-02-15 add system32 mode #define SYSTEM32MODE 31L #define ARM32BITMODE (state->Mode > 3) #define ARM26BITMODE (state->Mode <= 3) #define ARMMODE (state->Mode) #define ARMul_MODEBITS 0x1fL #define ARMul_MODE32BIT ARM32BITMODE #define ARMul_MODE26BIT ARM26BITMODE #define USERBANK 0 #define FIQBANK 1 #define IRQBANK 2 #define SVCBANK 3 #define ABORTBANK 4 #define UNDEFBANK 5 #define DUMMYBANK 6 #define SYSTEMBANK USERBANK #define BANK_CAN_ACCESS_SPSR(bank) \ ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK) /***************************************************************************\ * Definitons of things in the emulator * \***************************************************************************/ extern void ARMul_EmulateInit (void); extern ARMul_State *ARMul_NewState (void); extern void ARMul_Reset (ARMul_State * state); extern ARMword ARMul_DoProg (ARMul_State * state); extern ARMword ARMul_DoInstr (ARMul_State * state); /***************************************************************************\ * Definitons of things for event handling * \***************************************************************************/ extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay, unsigned (*func) ()); extern void ARMul_EnvokeEvent (ARMul_State * state); extern unsigned int ARMul_Time (ARMul_State * state); /***************************************************************************\ * Useful support routines * \***************************************************************************/ extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg); extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value); extern ARMword ARMul_GetPC (ARMul_State * state); extern ARMword ARMul_GetNextPC (ARMul_State * state); extern void ARMul_SetPC (ARMul_State * state, ARMword value); extern ARMword ARMul_GetR15 (ARMul_State * state); extern void ARMul_SetR15 (ARMul_State * state, ARMword value); extern ARMword ARMul_GetCPSR (ARMul_State * state); extern void ARMul_SetCPSR (ARMul_State * state, ARMword value); extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode); extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value); /***************************************************************************\ * Definitons of things to handle aborts * \***************************************************************************/ extern void ARMul_Abort (ARMul_State * state, ARMword address); #ifdef MODET #define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */ #define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ state->AbortAddr = (address & (state->TFlag ? ~1L : ~3L)) #else #define ARMul_ABORTWORD 0xefffffff /* SWI -1 */ #define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ state->AbortAddr = (address & ~3L) #endif #define ARMul_DATAABORT(address) state->abortSig = HIGH ; \ state->Aborted = ARMul_DataAbortV ; #define ARMul_CLEARABORT state->abortSig = LOW /***************************************************************************\ * Definitons of things in the memory interface * \***************************************************************************/ extern unsigned ARMul_MemoryInit (ARMul_State * state, unsigned int initmemsize); extern void ARMul_MemoryExit (ARMul_State * state); extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize); extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize); extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize); extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address); extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address); extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address); extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address); extern void ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data); extern void ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data); extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data); extern void ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data); extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data); extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data); extern void ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address); extern void ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address); extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address); extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address); extern void ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data); extern void ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data); extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword, ARMword, ARMword, ARMword, ARMword, ARMword, ARMword, ARMword, ARMword); /***************************************************************************\ * Definitons of things in the co-processor interface * \***************************************************************************/ #define ARMul_FIRST 0 #define ARMul_TRANSFER 1 #define ARMul_BUSY 2 #define ARMul_DATA 3 #define ARMul_INTERRUPT 4 #define ARMul_DONE 0 #define ARMul_CANT 1 #define ARMul_INC 3 #define ARMul_CP13_R0_FIQ 0x1 #define ARMul_CP13_R0_IRQ 0x2 #define ARMul_CP13_R8_PMUS 0x1 #define ARMul_CP14_R0_ENABLE 0x0001 #define ARMul_CP14_R0_CLKRST 0x0004 #define ARMul_CP14_R0_CCD 0x0008 #define ARMul_CP14_R0_INTEN0 0x0010 #define ARMul_CP14_R0_INTEN1 0x0020 #define ARMul_CP14_R0_INTEN2 0x0040 #define ARMul_CP14_R0_FLAG0 0x0100 #define ARMul_CP14_R0_FLAG1 0x0200 #define ARMul_CP14_R0_FLAG2 0x0400 #define ARMul_CP14_R10_MOE_IB 0x0004 #define ARMul_CP14_R10_MOE_DB 0x0008 #define ARMul_CP14_R10_MOE_BT 0x000c #define ARMul_CP15_R1_ENDIAN 0x0080 #define ARMul_CP15_R1_ALIGN 0x0002 #define ARMul_CP15_R5_X 0x0400 #define ARMul_CP15_R5_ST_ALIGN 0x0001 #define ARMul_CP15_R5_IMPRE 0x0406 #define ARMul_CP15_R5_MMU_EXCPT 0x0400 #define ARMul_CP15_DBCON_M 0x0100 #define ARMul_CP15_DBCON_E1 0x000c #define ARMul_CP15_DBCON_E0 0x0003 extern unsigned ARMul_CoProInit (ARMul_State * state); extern void ARMul_CoProExit (ARMul_State * state); extern void ARMul_CoProAttach (ARMul_State * state, unsigned number, ARMul_CPInits * init, ARMul_CPExits * exit, ARMul_LDCs * ldc, ARMul_STCs * stc, ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp, ARMul_CPReads * read, ARMul_CPWrites * write); extern void ARMul_CoProDetach (ARMul_State * state, unsigned number); /***************************************************************************\ * Definitons of things in the host environment * \***************************************************************************/ extern unsigned ARMul_OSInit (ARMul_State * state); extern void ARMul_OSExit (ARMul_State * state); extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number); extern ARMword ARMul_OSLastErrorP (ARMul_State * state); extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr); extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector, ARMword pc); extern int rdi_log; /***************************************************************************\ * Host-dependent stuff * \***************************************************************************/ #ifdef macintosh pascal void SpinCursor (short increment); /* copied from CursorCtl.h */ # define HOURGLASS SpinCursor( 1 ) # define HOURGLASS_RATE 1023 /* 2^n - 1 */ #endif //teawater add for arm2x86 2005.02.14------------------------------------------- /*ywc 2005-03-31*/ /* #include "arm2x86.h" #include "arm2x86_dp.h" #include "arm2x86_movl.h" #include "arm2x86_psr.h" #include "arm2x86_shift.h" #include "arm2x86_mem.h" #include "arm2x86_mul.h" #include "arm2x86_test.h" #include "arm2x86_other.h" #include "list.h" #include "tb.h" */ #define EQ 0 #define NE 1 #define CS 2 #define CC 3 #define MI 4 #define PL 5 #define VS 6 #define VC 7 #define HI 8 #define LS 9 #define GE 10 #define LT 11 #define GT 12 #define LE 13 #define AL 14 #define NV 15 #ifndef NFLAG #define NFLAG state->NFlag #endif //NFLAG #ifndef ZFLAG #define ZFLAG state->ZFlag #endif //ZFLAG #ifndef CFLAG #define CFLAG state->CFlag #endif //CFLAG #ifndef VFLAG #define VFLAG state->VFlag #endif //VFLAG #ifndef IFLAG #define IFLAG (state->IFFlags >> 1) #endif //IFLAG #ifndef FFLAG #define FFLAG (state->IFFlags & 1) #endif //FFLAG #ifndef IFFLAGS #define IFFLAGS state->IFFlags #endif //VFLAG #define FLAG_MASK 0xf0000000 #define NBIT_SHIFT 31 #define ZBIT_SHIFT 30 #define CBIT_SHIFT 29 #define VBIT_SHIFT 28 #ifdef DBCT //teawater change for local tb branch directly jump 2005.10.18------------------ #include "dbct/list.h" #include "dbct/arm2x86.h" #include "dbct/arm2x86_dp.h" #include "dbct/arm2x86_movl.h" #include "dbct/arm2x86_psr.h" #include "dbct/arm2x86_shift.h" #include "dbct/arm2x86_mem.h" #include "dbct/arm2x86_mul.h" #include "dbct/arm2x86_test.h" #include "dbct/arm2x86_other.h" #include "dbct/arm2x86_coproc.h" #include "dbct/tb.h" #endif //AJ2D-------------------------------------------------------------------------- //AJ2D-------------------------------------------------------------------------- #define SKYEYE_OUTREGS(fd) { fprintf ((fd), "R %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,C %x,S %x,%x,%x,%x,%x,%x,%x,M %x,B %x,E %x,I %x,P %x,T %x,L %x,D %x,",\ state->Reg[0],state->Reg[1],state->Reg[2],state->Reg[3], \ state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \ state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \ state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \ state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\ state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\ state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\ state->temp,state->loaded,state->decoded);} #define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\ RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ RF %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ RI %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ RS %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ RA %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\ state->RegBank[0][0],state->RegBank[0][1],state->RegBank[0][2],state->RegBank[0][3], \ state->RegBank[0][4],state->RegBank[0][5],state->RegBank[0][6],state->RegBank[0][7], \ state->RegBank[0][8],state->RegBank[0][9],state->RegBank[0][10],state->RegBank[0][11], \ state->RegBank[0][12],state->RegBank[0][13],state->RegBank[0][14],state->RegBank[0][15], \ state->RegBank[1][0],state->RegBank[1][1],state->RegBank[1][2],state->RegBank[1][3], \ state->RegBank[1][4],state->RegBank[1][5],state->RegBank[1][6],state->RegBank[1][7], \ state->RegBank[1][8],state->RegBank[1][9],state->RegBank[1][10],state->RegBank[1][11], \ state->RegBank[1][12],state->RegBank[1][13],state->RegBank[1][14],state->RegBank[1][15], \ state->RegBank[2][0],state->RegBank[2][1],state->RegBank[2][2],state->RegBank[2][3], \ state->RegBank[2][4],state->RegBank[2][5],state->RegBank[2][6],state->RegBank[2][7], \ state->RegBank[2][8],state->RegBank[2][9],state->RegBank[2][10],state->RegBank[2][11], \ state->RegBank[2][12],state->RegBank[2][13],state->RegBank[2][14],state->RegBank[2][15], \ state->RegBank[3][0],state->RegBank[3][1],state->RegBank[3][2],state->RegBank[3][3], \ state->RegBank[3][4],state->RegBank[3][5],state->RegBank[3][6],state->RegBank[3][7], \ state->RegBank[3][8],state->RegBank[3][9],state->RegBank[3][10],state->RegBank[3][11], \ state->RegBank[3][12],state->RegBank[3][13],state->RegBank[3][14],state->RegBank[3][15], \ state->RegBank[4][0],state->RegBank[4][1],state->RegBank[4][2],state->RegBank[4][3], \ state->RegBank[4][4],state->RegBank[4][5],state->RegBank[4][6],state->RegBank[4][7], \ state->RegBank[4][8],state->RegBank[4][9],state->RegBank[4][10],state->RegBank[4][11], \ state->RegBank[4][12],state->RegBank[4][13],state->RegBank[4][14],state->RegBank[4][15], \ state->RegBank[5][0],state->RegBank[5][1],state->RegBank[5][2],state->RegBank[5][3], \ state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \ state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \ state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \ );} #define SA1110 0x6901b110 #define SA1100 0x4401a100 #define PXA250 0x69052100 #define PXA270 0x69054110 //#define PXA250 0x69052903 // 0x69052903; //PXA250 B1 from intel 278522-001.pdf extern void ARMul_UndefInstr (ARMul_State *, ARMword); extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword); extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword); extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...); extern void ARMul_SelectProcessor (ARMul_State *, unsigned); #endif /* _ARMDEFS_H_ */ ��������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armio.c������������������������������������������������������������0000644�0001750�0000144�00000016416�10634527135�016513� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armio.c - I/O registers and interrupt controller. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson Changes to support running uClinux/Atmel AT91 targets Copyright (C) 2002 David McCullough <davidm@snapgear.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <sys/time.h> #include <sys/types.h> #include <unistd.h> #include "armdefs.h" /* * 7/17/2003 clean some routine. * clean io_reset only to do special mach_io_reset function. * wlm <wlm@student.dlut.edu.cn> */ /* Reset IO. * Now only reset some Internal IO Register. * Every machine has a reset routine to init it's special registers. * wlm 2003/7/17 * */ /* some machine need less number. e.g. s3c2440 only need DIVISOR = 1 to boot*/ #define DIVISOR (50) static int prescale = DIVISOR; void io_reset (ARMul_State * state) { struct device_desc *dev; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (dev->reset) dev->reset (dev); } if(skyeye_config.mach->mach_io_reset) skyeye_config.mach->mach_io_reset (state); else fprintf(stderr,"SKYEYE_ERR:mach_io_reset is NULL\n"); } void io_do_cycle (ARMul_State * state) { struct device_desc *dev; int i; //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED state->instr_count++; #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- prescale--; if (prescale < 0) { prescale = DIVISOR; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (dev->update) dev->update (dev); } skyeye_config.mach->mach_io_do_cycle (state); } } unsigned char mem_read_char (ARMul_State * state, ARMword addr) { union { unsigned char buf[4]; ARMword w; } tmp; tmp.w = mem_read_word (state, addr & ~0x3); if (state->bigendSig == HIGH) //if (big_endian) return (tmp.buf[3 - (addr & 0x3)]); return (tmp.buf[addr & 0x3]); } void mem_write_char (ARMul_State * state, ARMword addr, unsigned char c) { union { unsigned char buf[4]; ARMword w; } tmp; tmp.w = mem_read_word (state, addr & ~0x3); if (state->bigendSig == HIGH) /*big enddian? */ //if (big_endian) tmp.buf[3 - (addr & 0x3)] = c; else tmp.buf[addr & 0x3] = c; mem_write_word (state, addr & ~0x3, tmp.w); } /* Internal registers from 0x80000000 to 0x80002000. We also define a "debug I/O" register thereafter. */ ARMword io_read_byte (ARMul_State * state, ARMword addr) { struct device_desc *dev; ARMword data; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->read_byte) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->read_byte (dev, addr, (u8 *) & data) != ADDR_NOHIT) return data & 0xff; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->read_byte (dev, addr, (u8 *) & data) != ADDR_NOHIT) return data & 0xff; } } return skyeye_config.mach->mach_io_read_byte (state, addr); } ARMword io_read_halfword (ARMul_State * state, ARMword addr) { struct device_desc *dev; ARMword data; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->read_halfword) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->read_halfword (dev, addr, (u16 *) & data) != ADDR_NOHIT) return data & 0xffff; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->read_halfword (dev, addr, (u16 *) & data) != ADDR_NOHIT) return data & 0xffff; } } return skyeye_config.mach->mach_io_read_halfword (state, addr); } ARMword io_read_word (ARMul_State * state, ARMword addr) { struct device_desc *dev; ARMword data; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->read_word) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->read_word (dev, addr, (u32 *) & data) != ADDR_NOHIT) return data; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->read_word (dev, addr, (u32 *) & data) != ADDR_NOHIT) return data; } } return skyeye_config.mach->mach_io_read_word (state, addr); } void io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { struct device_desc *dev; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->write_byte) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->write_byte (dev, addr, (u8) data) != ADDR_NOHIT) return; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->write_byte (dev, addr, (u8) data) != ADDR_NOHIT) return; } } skyeye_config.mach->mach_io_write_byte (state, addr, data); } void io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { struct device_desc *dev; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->write_halfword) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->write_halfword (dev, addr, (u16) data) != ADDR_NOHIT) return; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->write_halfword (dev, addr, (u16) data) != ADDR_NOHIT) return; } } skyeye_config.mach->mach_io_write_halfword (state, addr, data); } void io_write_word (ARMul_State * state, ARMword addr, ARMword data) { struct device_desc *dev; int i; for (i = 0; i < skyeye_config.mach->dev_count; i++) { dev = skyeye_config.mach->devices[i]; if (!dev->write_word) continue; /* if we specify size=0, we don't check * whether "addr" is in the range of address space of device. * */ if (dev->size == 0) { if (dev->write_word (dev, addr, data) != ADDR_NOHIT) return; } else if ((addr >= dev->base) && (addr < (dev->base + dev->size))) { if (dev->write_word (dev, addr, data) != ADDR_NOHIT) return; } } skyeye_config.mach->mach_io_write_word (state, addr, data); } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/���������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�016010� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/wb.h�����������������������������������������������������������0000644�0001750�0000144�00000002137�10541455476�016617� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _MMU_WB_H_ #define _MMU_WB_H_ typedef struct wb_entry_s { ARMword pa; //phy_addr ARMbyte *data; //data int nb; //number byte to write } wb_entry_t; typedef struct wb_s { int num; //number of wb_entry int nb; //number of byte of each entry int first; // int last; // int used; // wb_entry_t *entrys; } wb_t; typedef struct wb_desc_s { int num; int nb; } wb_desc_t; /* wb_init * @wb_t :wb_t to init * @num :num of entrys * @nw :num of word of each entry * * $ -1:error * 0:ok * */ int mmu_wb_init (wb_t * wb_t, int num, int nb); /* wb_exit * @wb_t :wb_t to exit * */ void mmu_wb_exit (wb_t * wb); /* wb_write_bytes :put bytess in Write Buffer * @state: ARMul_State * @wb_t: write buffer * @pa: physical address * @data: data ptr * @n number of byte to write * * Note: write buffer merge is not implemented, can be done late * */ void mmu_wb_write_bytess (ARMul_State * state, wb_t * wb_t, ARMword pa, ARMbyte * data, int n); /* wb_drain_all * @wb_t wb_t to drain * */ void mmu_wb_drain_all (ARMul_State * state, wb_t * wb_t); #endif /*_MMU_WB_H_*/ ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/sa_mmu.c�������������������������������������������������������0000644�0001750�0000144�00000045760�10555732132�017464� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armmmu.c - Memory Management Unit emulation. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <assert.h> #include <string.h> #include "armdefs.h" typedef struct sa_mmu_desc_s { int i_tlb; cache_desc_t i_cache; int d_tlb; cache_desc_t main_d_cache; cache_desc_t mini_d_cache; int rb; wb_desc_t wb; } sa_mmu_desc_t; static sa_mmu_desc_t sa11xx_mmu_desc = { 32, {32, 32, 16, CACHE_WRITE_BACK}, 32, {32, 32, 8, CACHE_WRITE_BACK}, {32, 2, 8, CACHE_WRITE_BACK}, 4, //{8, 4}, for word size {8, 16}, //for byte size, chy 2003-07-11 }; static fault_t sa_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype); static fault_t sa_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype); static fault_t update_cache (ARMul_State * state, ARMword va, ARMword data, ARMword datatype, cache_line_t * cache, cache_t * cache_t, ARMword real_va); int sa_mmu_init (ARMul_State * state) { sa_mmu_desc_t *desc; cache_desc_t *c_desc; state->mmu.control = 0x70; state->mmu.translation_table_base = 0xDEADC0DE; state->mmu.domain_access_control = 0xDEADC0DE; state->mmu.fault_status = 0; state->mmu.fault_address = 0; state->mmu.process_id = 0; desc = &sa11xx_mmu_desc; if (mmu_tlb_init (I_TLB (), desc->i_tlb)) { err_msg ("i_tlb init %d\n", -1); goto i_tlb_init_error; } c_desc = &desc->i_cache; if (mmu_cache_init (I_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("i_cache init %d\n", -1); goto i_cache_init_error; } if (mmu_tlb_init (D_TLB (), desc->d_tlb)) { err_msg ("d_tlb init %d\n", -1); goto d_tlb_init_error; } c_desc = &desc->main_d_cache; if (mmu_cache_init (MAIN_D_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("main_d_cache init %d\n", -1); goto main_d_cache_init_error; } c_desc = &desc->mini_d_cache; if (mmu_cache_init (MINI_D_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("mini_d_cache init %d\n", -1); goto mini_d_cache_init_error; } if (mmu_wb_init (WB (), desc->wb.num, desc->wb.nb)) { err_msg ("wb init %d\n", -1); goto wb_init_error; } if (mmu_rb_init (RB (), desc->rb)) { err_msg ("rb init %d\n", -1); goto rb_init_error; } return 0; rb_init_error: mmu_wb_exit (WB ()); wb_init_error: mmu_cache_exit (MINI_D_CACHE ()); mini_d_cache_init_error: mmu_cache_exit (MAIN_D_CACHE ()); main_d_cache_init_error: mmu_tlb_exit (D_TLB ()); d_tlb_init_error: mmu_cache_exit (I_CACHE ()); i_cache_init_error: mmu_tlb_exit (I_TLB ()); i_tlb_init_error: return -1; } void sa_mmu_exit (ARMul_State * state) { mmu_rb_exit (RB ()); mmu_wb_exit (WB ()); mmu_cache_exit (MINI_D_CACHE ()); mmu_cache_exit (MAIN_D_CACHE ()); mmu_tlb_exit (D_TLB ()); mmu_cache_exit (I_CACHE ()); mmu_tlb_exit (I_TLB ()); }; static fault_t sa_mmu_load_instr (ARMul_State * state, ARMword va, ARMword * instr) { fault_t fault; tlb_entry_t *tlb; cache_line_t *cache; int c; //cache bit ARMword pa; //physical addr static int debug_count = 0; //used for debug d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); if (MMU_Enabled) { /*align check */ if ((va & (WORD_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else va &= ~(WORD_SIZE - 1); /*translate tlb */ fault = translate (state, va, I_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, va, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } /*search cache no matter MMU enabled/disabled */ cache = mmu_cache_search (state, I_CACHE (), va); if (cache) { *instr = cache->data[va_cache_index (va, I_CACHE ())]; return 0; } /*if MMU disabled or C flag is set alloc cache */ if (MMU_Disabled) { c = 1; pa = va; } else { c = tlb_c_flag (tlb); pa = tlb_va_to_pa (tlb, va); } if (c) { int index; debug_count++; cache = mmu_cache_alloc (state, I_CACHE (), va, pa); index = va_cache_index (va, I_CACHE ()); *instr = cache->data[va_cache_index (va, I_CACHE ())]; } else *instr = mem_read_word (state, pa); return 0; }; static fault_t sa_mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = sa_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE); return fault; } static fault_t sa_mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = sa_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE); return fault; } static fault_t sa_mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data) { return sa_mmu_read (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t sa_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype) { fault_t fault; rb_entry_t *rb; tlb_entry_t *tlb; cache_line_t *cache; ARMword pa, real_va, temp, offset; d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); real_va = va; /*if MMU disabled, memory_read */ if (MMU_Disabled) { //*data = mem_read_word(state, va); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, va); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, va); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, va); else { printf ("SKYEYE:1 sa_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } // else va &= ~(WORD_SIZE - 1); /*translate va to tlb */ fault = translate (state, va, D_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access permission */ fault = check_access (state, va, tlb, 1); if (fault) return fault; /*search in read buffer */ rb = mmu_rb_search (RB (), va); if (rb) { if (rb->fault) return rb->fault; *data = rb->data[(va & (rb_masks[rb->type] - 1)) >> WORD_SHT]; goto datatrans; //return 0; }; /*search main cache */ cache = mmu_cache_search (state, MAIN_D_CACHE (), va); if (cache) { *data = cache->data[va_cache_index (va, MAIN_D_CACHE ())]; goto datatrans; //return 0; } /*search mini cache */ cache = mmu_cache_search (state, MINI_D_CACHE (), va); if (cache) { *data = cache->data[va_cache_index (va, MINI_D_CACHE ())]; goto datatrans; //return 0; } /*get phy_addr */ pa = tlb_va_to_pa (tlb, va); if ((pa >= 0xe0000000) && (pa < 0xe8000000)) { if (tlb_c_flag (tlb)) { if (tlb_b_flag (tlb)) { mmu_cache_soft_flush (state, MAIN_D_CACHE (), pa); } else { mmu_cache_soft_flush (state, MINI_D_CACHE (), pa); } } return 0; } /*if Buffer, drain Write Buffer first */ if (tlb_b_flag (tlb)) mmu_wb_drain_all (state, WB ()); /*alloc cache or mem_read */ if (tlb_c_flag (tlb) && MMU_DCacheEnabled) { cache_t *cache_t; if (tlb_b_flag (tlb)) cache_t = MAIN_D_CACHE (); else cache_t = MINI_D_CACHE (); cache = mmu_cache_alloc (state, cache_t, va, pa); *data = cache->data[va_cache_index (va, cache_t)]; } else { //*data = mem_read_word(state, pa); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, pa | (real_va & 3)); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, pa | (real_va & 2)); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, pa); else { printf ("SKYEYE:2 sa_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } datatrans: if (datatype == ARM_HALFWORD_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ *data = (temp >> offset) & 0xffff; } else if (datatype == ARM_BYTE_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ *data = (temp >> offset & 0xffL); } end: return 0; } static fault_t sa_mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data) { return sa_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE); } static fault_t sa_mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data) { return sa_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE); } static fault_t sa_mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data) { return sa_mmu_write (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t sa_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype) { tlb_entry_t *tlb; cache_line_t *cache; int b; ARMword pa, real_va; fault_t fault; d_msg ("va = %x, val = %x\n", va, data); va = mmu_pid_va_map (va); real_va = va; /*search instruction cache */ cache = mmu_cache_search (state, I_CACHE (), va); if (cache) { update_cache (state, va, data, datatype, cache, I_CACHE (), real_va); } if (MMU_Disabled) { //mem_write_word(state, va, data); if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, va, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, va, data); else if (datatype == ARM_WORD_TYPE) mem_write_word (state, va, data); else { printf ("SKYEYE:1 sa_mmu_write error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ //if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } //else va &= ~(WORD_SIZE - 1); /*tlb translate */ fault = translate (state, va, D_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*tlb check access */ fault = check_access (state, va, tlb, 0); if (fault) { d_msg ("check_access\n"); return fault; } /*search main cache */ cache = mmu_cache_search (state, MAIN_D_CACHE (), va); if (cache) { update_cache (state, va, data, datatype, cache, MAIN_D_CACHE (), real_va); } else { /*search mini cache */ cache = mmu_cache_search (state, MINI_D_CACHE (), va); if (cache) { update_cache (state, va, data, datatype, cache, MINI_D_CACHE (), real_va); } } if (!cache) { b = tlb_b_flag (tlb); pa = tlb_va_to_pa (tlb, va); if (b) { if (MMU_WBEnabled) { if (datatype == ARM_WORD_TYPE) mmu_wb_write_bytes (state, WB (), pa, &data, 4); else if (datatype == ARM_HALFWORD_TYPE) mmu_wb_write_bytes (state, WB (), (pa | (real_va & 2)), &data, 2); else if (datatype == ARM_BYTE_TYPE) mmu_wb_write_bytes (state, WB (), (pa | (real_va & 3)), &data, 1); } else { if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } } else { mmu_wb_drain_all (state, WB ()); if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } } return 0; } static fault_t update_cache (ARMul_State * state, ARMword va, ARMword data, ARMword datatype, cache_line_t * cache, cache_t * cache_t, ARMword real_va) { ARMword temp, offset; ARMword index = va_cache_index (va, cache_t); //cache->data[index] = data; if (datatype == ARM_WORD_TYPE) cache->data[index] = data; else if (datatype == ARM_HALFWORD_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset); } else if (datatype == ARM_BYTE_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset); } if (index < (cache_t->width >> (WORD_SHT + 1))) cache->tag |= TAG_FIRST_HALF_DIRTY; else cache->tag |= TAG_LAST_HALF_DIRTY; return 0; } ARMword sa_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value) { mmu_regnum_t creg = BITS (16, 19) & 15; ARMword data; switch (creg) { case MMU_ID: // printf("mmu_mrc read ID "); data = 0x41007100; /* v3 */ data = state->cpu->cpu_val; break; case MMU_CONTROL: // printf("mmu_mrc read CONTROL"); data = state->mmu.control; break; case MMU_TRANSLATION_TABLE_BASE: // printf("mmu_mrc read TTB "); data = state->mmu.translation_table_base; break; case MMU_DOMAIN_ACCESS_CONTROL: // printf("mmu_mrc read DACR "); data = state->mmu.domain_access_control; break; case MMU_FAULT_STATUS: // printf("mmu_mrc read FSR "); data = state->mmu.fault_status; break; case MMU_FAULT_ADDRESS: // printf("mmu_mrc read FAR "); data = state->mmu.fault_address; break; case MMU_PID: data = state->mmu.process_id; default: printf ("mmu_mrc read UNKNOWN - reg %d\n", creg); data = 0; break; } // printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]); *value = data; return data; } void sa_mmu_cache_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); if (OPC_2 == 0 && CRm == 7) { mmu_cache_invalidate_all (state, I_CACHE ()); mmu_cache_invalidate_all (state, MAIN_D_CACHE ()); mmu_cache_invalidate_all (state, MINI_D_CACHE ()); return; } if (OPC_2 == 0 && CRm == 5) { mmu_cache_invalidate_all (state, I_CACHE ()); return; } if (OPC_2 == 0 && CRm == 6) { mmu_cache_invalidate_all (state, MAIN_D_CACHE ()); mmu_cache_invalidate_all (state, MINI_D_CACHE ()); return; } if (OPC_2 == 1 && CRm == 6) { mmu_cache_invalidate (state, MAIN_D_CACHE (), value); mmu_cache_invalidate (state, MINI_D_CACHE (), value); return; } if (OPC_2 == 1 && CRm == 0xa) { mmu_cache_clean (state, MAIN_D_CACHE (), value); mmu_cache_clean (state, MINI_D_CACHE (), value); return; } if (OPC_2 == 4 && CRm == 0xa) { mmu_wb_drain_all (state, WB ()); return; } err_msg ("Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm); } static void sa_mmu_tlb_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); if (OPC_2 == 0 && CRm == 0x7) { mmu_tlb_invalidate_all (state, I_TLB ()); mmu_tlb_invalidate_all (state, D_TLB ()); return; } if (OPC_2 == 0 && CRm == 0x5) { mmu_tlb_invalidate_all (state, I_TLB ()); return; } if (OPC_2 == 0 && CRm == 0x6) { mmu_tlb_invalidate_all (state, D_TLB ()); return; } if (OPC_2 == 1 && CRm == 0x6) { mmu_tlb_invalidate_entry (state, D_TLB (), value); return; } err_msg ("Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm); } static void sa_mmu_rb_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); if (OPC_2 == 0x0 && CRm == 0x0) { mmu_rb_invalidate_all (RB ()); return; } if (OPC_2 == 0x2) { int idx = CRm & 0x3; int type = ((CRm >> 2) & 0x3) + 1; if ((idx < 4) && (type < 4)) mmu_rb_load (state, RB (), idx, type, value); return; } if ((OPC_2 == 1) && (CRm < 4)) { mmu_rb_invalidate_entry (RB (), CRm); return; } err_msg ("Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm); } static void sa_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value) { mmu_regnum_t creg = BITS (16, 19) & 15; if (!strncmp (state->cpu->cpu_arch_name, "armv4", 5)) { switch (creg) { case MMU_CONTROL: // printf("mmu_mcr wrote CONTROL "); state->mmu.control = (value | 0x70) & 0xFFFD; break; case MMU_TRANSLATION_TABLE_BASE: // printf("mmu_mcr wrote TTB "); state->mmu.translation_table_base = value & 0xFFFFC000; break; case MMU_DOMAIN_ACCESS_CONTROL: // printf("mmu_mcr wrote DACR "); state->mmu.domain_access_control = value; break; case MMU_FAULT_STATUS: state->mmu.fault_status = value & 0xFF; break; case MMU_FAULT_ADDRESS: state->mmu.fault_address = value; break; case MMU_CACHE_OPS: sa_mmu_cache_ops (state, instr, value); break; case MMU_TLB_OPS: sa_mmu_tlb_ops (state, instr, value); break; case MMU_SA_RB_OPS: sa_mmu_rb_ops (state, instr, value); break; case MMU_SA_DEBUG: break; case MMU_SA_CP15_R15: break; case MMU_PID: //2004-06-06 lyh, bug provided by wen ye wenye@cs.ucsb.edu state->mmu.process_id = value & 0x7e000000; break; default: printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); break; } } } //teawater add for arm2x86 2005.06.24------------------------------------------- static int sa_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr) { fault_t fault; tlb_entry_t *tlb; virt_addr = mmu_pid_va_map (virt_addr); if (MMU_Enabled) { /*align check */ if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else virt_addr &= ~(WORD_SIZE - 1); /*translate tlb */ fault = translate (state, virt_addr, I_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, virt_addr, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } if (MMU_Disabled) { *phys_addr = virt_addr; } else { *phys_addr = tlb_va_to_pa (tlb, virt_addr); } return (0); } //AJ2D-------------------------------------------------------------------------- /*sa mmu_ops_t*/ mmu_ops_t sa_mmu_ops = { sa_mmu_init, sa_mmu_exit, sa_mmu_read_byte, sa_mmu_write_byte, sa_mmu_read_halfword, sa_mmu_write_halfword, sa_mmu_read_word, sa_mmu_write_word, sa_mmu_load_instr, sa_mmu_mcr, sa_mmu_mrc, //teawater add for arm2x86 2005.06.24------------------------------------------- sa_mmu_v2p_dbct, //AJ2D-------------------------------------------------------------------------- }; ����������������skyeye-1.2.5_REL/arch/arm/common/mmu/sa_mmu.h�������������������������������������������������������0000644�0001750�0000144�00000002625�10541455476�017472� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* sa_mmu.h - StrongARM Memory Management Unit emulation. ARMulator extensions for SkyEye. <lyhost@263.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _SA_MMU_H_ #define _SA_MMU_H_ typedef struct sa_mmu_s { tlb_t i_tlb; cache_t i_cache; tlb_t d_tlb; cache_t main_d_cache; cache_t mini_d_cache; rb_t rb_t; wb_t wb_t; } sa_mmu_t; #define I_TLB() (&state->mmu.u.sa_mmu.i_tlb) #define I_CACHE() (&state->mmu.u.sa_mmu.i_cache) #define D_TLB() (&state->mmu.u.sa_mmu.d_tlb) #define MAIN_D_CACHE() (&state->mmu.u.sa_mmu.main_d_cache) #define MINI_D_CACHE() (&state->mmu.u.sa_mmu.mini_d_cache) #define WB() (&state->mmu.u.sa_mmu.wb_t) #define RB() (&state->mmu.u.sa_mmu.rb_t) extern mmu_ops_t sa_mmu_ops; #endif /*_SA_MMU_H_*/ �����������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/arm926ejs_mmu.h������������������������������������������������0000644�0001750�0000144�00000002034�10541455476�020603� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* arm926ejs_mmu.h - ARM926EJS Memory Management Unit emulation. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ARM926EJS_MMU_H_ #define _ARM926EJS_MMU_H_ typedef struct arm926ejs_mmu_s { tlb_t main_tlb; tlb_t lockdown_tlb; cache_t i_cache; cache_t d_cache; wb_t wb_t; } arm926ejs_mmu_t; extern mmu_ops_t arm926ejs_mmu_ops; #endif /*_ARM926EJS_MMU_H_*/ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/wb.c�����������������������������������������������������������0000644�0001750�0000144�00000005454�11006120657�016602� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "armdefs.h" /* wb_init * @wb_t :wb_t to init * @num :num of entrys * @nb :num of byte of each entry * * $ -1:error * 0:ok * */ int mmu_wb_init (wb_t * wb_t, int num, int nb) { int i; wb_entry_t *entrys, *wb; entrys = (wb_entry_t *) malloc (sizeof (*entrys) * num); if (entrys == NULL) { err_msg ("malloc size %d\n", sizeof (*entrys) * num); goto entrys_malloc_error; } for (wb = entrys, i = 0; i < num; i++, wb++) { /*chy 2004-06-06, fix bug found by wenye@cs.ucsb.edu */ //wb->data = (ARMword *)malloc(sizeof(ARMword) * nb); wb->data = (ARMword *) malloc (nb); if (wb->data == NULL) { err_msg ("malloc size of %d\n", nb); goto data_malloc_error; } }; wb_t->first = wb_t->last = wb_t->used = 0; wb_t->num = num; wb_t->nb = nb; wb_t->entrys = entrys; return 0; data_malloc_error: while (--i >= 0) free (entrys[i].data); free (entrys); entrys_malloc_error: return -1; }; /* wb_exit * @wb_t :wb_t to exit * */ void mmu_wb_exit (wb_t * wb_t) { int i; wb_entry_t *wb; wb = wb_t->entrys; for (i = 0; i < wb_t->num; i++, wb++) { free (wb->data); } free (wb_t->entrys); }; /* wb_write_words :put words in Write Buffer * @state: ARMul_State * @wb_t: write buffer * @pa: physical address * @data: data ptr * @n number of word to write * * Note: write buffer merge is not implemented, can be done late * */ void mmu_wb_write_bytes (ARMul_State * state, wb_t * wb_t, ARMword pa, ARMbyte * data, int n) { int i; wb_entry_t *wb; while (n) { if (wb_t->num == wb_t->used) { /*clean the last wb entry */ ARMword t; wb = &wb_t->entrys[wb_t->last]; t = wb->pa; for (i = 0; i < wb->nb; i++) { mem_write_byte (state, t, wb->data[i]); //t += WORD_SIZE; t++; } wb_t->last++; if (wb_t->last == wb_t->num) wb_t->last = 0; wb_t->used--; } wb = &wb_t->entrys[wb_t->first]; i = (n < wb_t->nb) ? n : wb_t->nb; wb->pa = pa; //pa += i << WORD_SHT; pa += i; wb->nb = i; //memcpy(wb->data, data, i << WORD_SHT); memcpy (wb->data, data, i); data += i; n -= i; wb_t->first++; if (wb_t->first == wb_t->num) wb_t->first = 0; wb_t->used++; }; //teawater add for set_dirty fflash cache function 2005.07.18------------------- #ifdef DBCT if (!skyeye_config.no_dbct) { tb_setdirty (state, pa, NULL); } #endif //AJ2D-------------------------------------------------------------------------- } /* wb_drain_all * @wb_t wb_t to drain * */ void mmu_wb_drain_all (ARMul_State * state, wb_t * wb_t) { ARMword pa; wb_entry_t *wb; int i; while (wb_t->used) { wb = &wb_t->entrys[wb_t->last]; pa = wb->pa; for (i = 0; i < wb->nb; i++) { mem_write_byte (state, pa, wb->data[i]); //pa += WORD_SIZE; pa++; } wb_t->last++; if (wb_t->last == wb_t->num) wb_t->last = 0; wb_t->used--; }; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/arm7100_mmu.h��������������������������������������������������0000644�0001750�0000144�00000001756�10541455476�020162� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ARM7100_MMU_H_ #define _ARM7100_MMU_H_ typedef struct arm7100_mmu_s { cache_t cache_t; tlb_t tlb_t; } arm7100_mmu_t; extern mmu_ops_t arm7100_mmu_ops; #endif /*_ARM7100_MMU_H_*/ ������������������skyeye-1.2.5_REL/arch/arm/common/mmu/arm920t_mmu.c��������������������������������������������������0000644�0001750�0000144�00000047100�10555732132�020245� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* arm920t_mmu.c - ARM920T Memory Management Unit emulation. Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <assert.h> #include <string.h> #include "armdefs.h" #define ARM920T_I_TLB() (&state->mmu.u.arm920t_mmu.i_tlb) #define ARM920T_I_CACHE() (&state->mmu.u.arm920t_mmu.i_cache) #define ARM920T_D_TLB() (&state->mmu.u.arm920t_mmu.d_tlb) #define ARM920T_D_CACHE() (&state->mmu.u.arm920t_mmu.d_cache) #define ARM920T_WB() (&state->mmu.u.arm920t_mmu.wb_t) typedef struct arm920t_mmu_desc_s { int i_tlb; cache_desc_t i_cache; int d_tlb; cache_desc_t d_cache; wb_desc_t wb; } arm920t_mmu_desc_t; static arm920t_mmu_desc_t arm920t_mmu_desc = { 64, /* 32 bytes per line * 64 way * 8 set * */ {32, 64, 8, CACHE_WRITE_BACK}, 64, {32, 64, 8, CACHE_WRITE_BACK}, {8, 8} //for byte size }; static fault_t arm920t_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype); static fault_t arm920t_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype); static fault_t update_cache (ARMul_State * state, ARMword va, ARMword data, ARMword datatype, cache_line_t * cache, cache_t * cache_t, ARMword real_va); int arm920t_mmu_init (ARMul_State * state) { arm920t_mmu_desc_t *desc; cache_desc_t *c_desc; state->mmu.control = 0x70; state->mmu.translation_table_base = 0xDEADC0DE; state->mmu.domain_access_control = 0xDEADC0DE; state->mmu.fault_status = 0; state->mmu.fault_address = 0; state->mmu.process_id = 0; desc = &arm920t_mmu_desc; if (mmu_tlb_init (ARM920T_I_TLB (), desc->i_tlb)) { err_msg ("i_tlb init %d\n", -1); goto i_tlb_init_error; } c_desc = &desc->i_cache; if (mmu_cache_init (ARM920T_I_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("i_cache init %d\n", -1); goto i_cache_init_error; } if (mmu_tlb_init (ARM920T_D_TLB (), desc->d_tlb)) { err_msg ("d_tlb init %d\n", -1); goto d_tlb_init_error; } c_desc = &desc->d_cache; if (mmu_cache_init (ARM920T_D_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("d_cache init %d\n", -1); goto d_cache_init_error; } if (mmu_wb_init (ARM920T_WB (), desc->wb.num, desc->wb.nb)) { err_msg ("wb init %d\n", -1); goto wb_init_error; } return 0; wb_init_error: mmu_cache_exit (ARM920T_D_CACHE ()); d_cache_init_error: mmu_tlb_exit (ARM920T_D_TLB ()); d_tlb_init_error: mmu_cache_exit (ARM920T_I_CACHE ()); i_cache_init_error: mmu_tlb_exit (ARM920T_I_TLB ()); i_tlb_init_error: return -1; } void arm920t_mmu_exit (ARMul_State * state) { mmu_wb_exit (ARM920T_WB ()); mmu_cache_exit (ARM920T_D_CACHE ()); mmu_tlb_exit (ARM920T_D_TLB ()); mmu_cache_exit (ARM920T_I_CACHE ()); mmu_tlb_exit (ARM920T_I_TLB ()); }; static fault_t arm920t_mmu_load_instr (ARMul_State * state, ARMword va, ARMword * instr) { fault_t fault; tlb_entry_t *tlb; cache_line_t *cache; int c; //cache bit ARMword pa; //physical addr static int debug_count = 0; //used for debug d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); if (MMU_Enabled) { /*align check */ if ((va & (WORD_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else va &= ~(WORD_SIZE - 1); /*translate tlb */ fault = translate (state, va, ARM920T_I_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, va, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } /*search cache no matter MMU enabled/disabled */ cache = mmu_cache_search (state, ARM920T_I_CACHE (), va); if (cache) { *instr = cache->data[va_cache_index (va, ARM920T_I_CACHE ())]; return 0; } /*if MMU disabled or C flag is set alloc cache */ if (MMU_Disabled) { c = 1; pa = va; } else { c = tlb_c_flag (tlb); pa = tlb_va_to_pa (tlb, va); } if (c) { int index; debug_count++; cache = mmu_cache_alloc (state, ARM920T_I_CACHE (), va, pa); index = va_cache_index (va, ARM920T_I_CACHE ()); *instr = cache->data[va_cache_index (va, ARM920T_I_CACHE ())]; } else *instr = mem_read_word (state, pa); return 0; }; static fault_t arm920t_mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = arm920t_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE); return fault; } static fault_t arm920t_mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = arm920t_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE); return fault; } static fault_t arm920t_mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data) { return arm920t_mmu_read (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t arm920t_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype) { fault_t fault; tlb_entry_t *tlb; cache_line_t *cache; ARMword pa, real_va, temp, offset; d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); real_va = va; /*if MMU disabled, memory_read */ if (MMU_Disabled) { //*data = mem_read_word(state, va); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, va); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, va); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, va); else { printf ("SKYEYE:1 arm920t_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } // else va &= ~(WORD_SIZE - 1); /*translate va to tlb */ fault = translate (state, va, ARM920T_D_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access permission */ fault = check_access (state, va, tlb, 1); if (fault) return fault; /*search main cache */ cache = mmu_cache_search (state, ARM920T_D_CACHE (), va); if (cache) { *data = cache->data[va_cache_index (va, ARM920T_D_CACHE ())]; goto datatrans; //return 0; } /*get phy_addr */ pa = tlb_va_to_pa (tlb, va); if ((pa >= 0xe0000000) && (pa < 0xe8000000)) { if (tlb_c_flag (tlb)) { //if (tlb_b_flag(tlb)){ // mmu_cache_soft_flush(state, ARM920T_D_CACHE(), pa); //} mmu_cache_soft_flush (state, ARM920T_D_CACHE (), pa); } return 0; } /*if Buffer, drain Write Buffer first */ if (tlb_b_flag (tlb)) mmu_wb_drain_all (state, ARM920T_WB ()); /*alloc cache or mem_read */ if (tlb_c_flag (tlb) && MMU_DCacheEnabled) { cache_t *cache_t; //if (tlb_b_flag(tlb)) cache_t = ARM920T_D_CACHE (); cache = mmu_cache_alloc (state, cache_t, va, pa); *data = cache->data[va_cache_index (va, cache_t)]; } else { //*data = mem_read_word(state, pa); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, pa | (real_va & 3)); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, pa | (real_va & 2)); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, pa); else { printf ("SKYEYE:2 arm920t_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } datatrans: if (datatype == ARM_HALFWORD_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ *data = (temp >> offset) & 0xffff; } else if (datatype == ARM_BYTE_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ *data = (temp >> offset & 0xffL); } end: // printf("va: %x, pa:%x data: %x\n", va, pa, *data); return 0; } static fault_t arm920t_mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data) { return arm920t_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE); } static fault_t arm920t_mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data) { return arm920t_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE); } static fault_t arm920t_mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data) { return arm920t_mmu_write (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t arm920t_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype) { tlb_entry_t *tlb; cache_line_t *cache; int b; ARMword pa, real_va; fault_t fault; d_msg ("va = %x, val = %x\n", va, data); va = mmu_pid_va_map (va); real_va = va; /*search instruction cache */ cache = mmu_cache_search (state, ARM920T_I_CACHE (), va); if (cache) { update_cache (state, va, data, datatype, cache, ARM920T_I_CACHE (), real_va); } if (MMU_Disabled) { //mem_write_word(state, va, data); if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, va, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, va, data); else if (datatype == ARM_WORD_TYPE) mem_write_word (state, va, data); else { printf ("SKYEYE:1 arm920t_mmu_write error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ //if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } //else va &= ~(WORD_SIZE - 1); /*tlb translate */ fault = translate (state, va, ARM920T_D_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*tlb check access */ fault = check_access (state, va, tlb, 0); if (fault) { d_msg ("check_access\n"); return fault; } /*search main cache */ cache = mmu_cache_search (state, ARM920T_D_CACHE (), va); if (cache) { update_cache (state, va, data, datatype, cache, ARM920T_D_CACHE (), real_va); } if (!cache) { b = tlb_b_flag (tlb); pa = tlb_va_to_pa (tlb, va); if (b) { if (MMU_WBEnabled) { if (datatype == ARM_WORD_TYPE) mmu_wb_write_bytes (state, ARM920T_WB (), pa, &data, 4); else if (datatype == ARM_HALFWORD_TYPE) mmu_wb_write_bytes (state, ARM920T_WB (), (pa | (real_va & 2)), &data, 2); else if (datatype == ARM_BYTE_TYPE) mmu_wb_write_bytes (state, ARM920T_WB (), (pa | (real_va & 3)), &data, 1); } else { if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } } else { mmu_wb_drain_all (state, ARM920T_WB ()); if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } } return 0; } static fault_t update_cache (ARMul_State * state, ARMword va, ARMword data, ARMword datatype, cache_line_t * cache, cache_t * cache_t, ARMword real_va) { ARMword temp, offset; ARMword index = va_cache_index (va, cache_t); //cache->data[index] = data; if (datatype == ARM_WORD_TYPE) cache->data[index] = data; else if (datatype == ARM_HALFWORD_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset); } else if (datatype == ARM_BYTE_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset); } if (index < (cache_t->width >> (WORD_SHT + 1))) cache->tag |= TAG_FIRST_HALF_DIRTY; else cache->tag |= TAG_LAST_HALF_DIRTY; return 0; } ARMword arm920t_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value) { mmu_regnum_t creg = BITS (16, 19) & 0xf; int OPC_2 = BITS (5, 7) & 0x7; ARMword data; switch (creg) { case MMU_ID: if (OPC_2 == 0) data = state->cpu->cpu_val; else if (OPC_2 == 1) /* Cache type: * 000 0110 1 000 101 110 0 10 000 101 110 0 10 * */ data = 0x0D172172; break; case MMU_CONTROL: /* * 6:3 should be 1. * 11:10 should be 0 * */ data = (state->mmu.control | 0x78) & 0xFFFFF3FF;; break; case MMU_TRANSLATION_TABLE_BASE: data = state->mmu.translation_table_base; break; case MMU_DOMAIN_ACCESS_CONTROL: data = state->mmu.domain_access_control; break; case MMU_FAULT_STATUS: /* OPC_2 = 0: data FSR value * */ if (OPC_2 == 0) data = state->mmu.fault_status; break; case MMU_FAULT_ADDRESS: data = state->mmu.fault_address; break; case MMU_PID: data = state->mmu.process_id; default: printf ("mmu_mrc read UNKNOWN - reg %d\n", creg); data = 0; break; } // printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]); *value = data; return data; } /* ARM920T Cache Operation, P44 * */ void arm920t_mmu_cache_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); if (OPC_2 == 0 && CRm == 7) { mmu_cache_invalidate_all (state, ARM920T_I_CACHE ()); mmu_cache_invalidate_all (state, ARM920T_D_CACHE ()); return; } if (OPC_2 == 0 && CRm == 5) { mmu_cache_invalidate_all (state, ARM920T_I_CACHE ()); return; } /*Invalidate ICache single entry **/ if (OPC_2 == 1 && CRm == 5) { mmu_cache_invalidate (state, ARM920T_I_CACHE (), value); return; } /* FIXME: should complete * Prefetch ICache line (using MVA) * */ if (OPC_2 == 1 && CRm == 13) { //mmu_cache_invalidate(state, ARM920T_I_CACHE(), value); return; } if (OPC_2 == 0 && CRm == 6) { mmu_cache_invalidate_all (state, ARM920T_D_CACHE ()); return; } /* Invalidate DCache single entry (using MVA) * */ if (OPC_2 == 1 && CRm == 6) { mmu_cache_invalidate (state, ARM920T_D_CACHE (), value); return; } /* Clean DCache single entry (using MVA) * */ if (OPC_2 == 1 && CRm == 0xa) { mmu_cache_clean (state, ARM920T_D_CACHE (), value); return; } /* Clean and Invalidate DCache entry (using MVA) * */ if (OPC_2 == 1 && CRm == 14) { mmu_cache_clean (state, ARM920T_D_CACHE (), value); mmu_cache_invalidate (state, ARM920T_D_CACHE (), value); return; } /* Clean DCache single entry (using index) * */ if (OPC_2 == 2 && CRm == 0xa) { mmu_cache_clean_by_index (state, ARM920T_D_CACHE (), value); return; } /* Clean and Invalidate DCache entry (using index) * */ if (OPC_2 == 2 && CRm == 14) { mmu_cache_clean_by_index (state, ARM920T_D_CACHE (), value); mmu_cache_invalidate_by_index (state, ARM920T_D_CACHE (), value); return; } /* Drain write buffer * */ if (OPC_2 == 4 && CRm == 0xa) { mmu_wb_drain_all (state, ARM920T_WB ()); return; } /* FIXME: how to do a waiting operation? * Wait for a interrupt * */ if (OPC_2 == 4 && CRm == 0) { return; } err_msg ("Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm); } static void arm920t_mmu_tlb_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); if (OPC_2 == 0 && CRm == 0x7) { mmu_tlb_invalidate_all (state, ARM920T_I_TLB ()); mmu_tlb_invalidate_all (state, ARM920T_D_TLB ()); return; } if (OPC_2 == 0 && CRm == 0x5) { mmu_tlb_invalidate_all (state, ARM920T_I_TLB ()); return; } if (OPC_2 == 1 && CRm == 0x5) { mmu_tlb_invalidate_entry (state, ARM920T_I_TLB (), value); return; } if (OPC_2 == 0 && CRm == 0x6) { mmu_tlb_invalidate_all (state, ARM920T_D_TLB ()); return; } if (OPC_2 == 1 && CRm == 0x6) { mmu_tlb_invalidate_entry (state, ARM920T_D_TLB (), value); return; } err_msg ("Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm); } static void arm920t_mmu_cache_lockdown (ARMul_State * state, ARMword instr, ARMword value) { int OPC_2 = BITS (5, 7) & 0x7; } static void arm920t_mmu_tlb_lockdown (ARMul_State * state, ARMword instr, ARMword value) { } static ARMword arm920t_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value) { mmu_regnum_t creg = BITS (16, 19) & 15; int OPC_2 = BITS (5, 7) & 0x7; if (!strncmp (state->cpu->cpu_arch_name, "armv4", 5)) { switch (creg) { case MMU_CONTROL: // printf("mmu_mcr wrote CONTROL "); state->mmu.control = (value | 0x78) & 0xFFFFF3FF; break; case MMU_TRANSLATION_TABLE_BASE: // printf("mmu_mcr wrote TTB "); state->mmu.translation_table_base = value & 0xFFFFC000; break; case MMU_DOMAIN_ACCESS_CONTROL: // printf("mmu_mcr wrote DACR "); state->mmu.domain_access_control = value; break; case MMU_FAULT_STATUS: if (OPC_2 == 0) state->mmu.fault_status = value & 0xFF; break; case MMU_FAULT_ADDRESS: state->mmu.fault_address = value; break; case MMU_CACHE_OPS: arm920t_mmu_cache_ops (state, instr, value); break; case MMU_TLB_OPS: arm920t_mmu_tlb_ops (state, instr, value); break; case MMU_CACHE_LOCKDOWN: /* * FIXME: cache lock down*/ break; case MMU_TLB_LOCKDOWN: /* FIXME:tlb lock down */ break; case MMU_PID: /*0:24 should be zero. */ state->mmu.process_id = value & 0xfe000000; break; default: printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); break; } } } //teawater add for arm2x86 2005.06.19------------------------------------------- static int arm920t_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr) { fault_t fault; tlb_entry_t *tlb; virt_addr = mmu_pid_va_map (virt_addr); if (MMU_Enabled) { /*align check */ if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else virt_addr &= ~(WORD_SIZE - 1); /*translate tlb */ fault = translate (state, virt_addr, ARM920T_I_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, virt_addr, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } if (MMU_Disabled) { *phys_addr = virt_addr; } else { *phys_addr = tlb_va_to_pa (tlb, virt_addr); } return (0); } //AJ2D-------------------------------------------------------------------------- /*arm920t mmu_ops_t*/ mmu_ops_t arm920t_mmu_ops = { arm920t_mmu_init, arm920t_mmu_exit, arm920t_mmu_read_byte, arm920t_mmu_write_byte, arm920t_mmu_read_halfword, arm920t_mmu_write_halfword, arm920t_mmu_read_word, arm920t_mmu_write_word, arm920t_mmu_load_instr, arm920t_mmu_mcr, arm920t_mmu_mrc, //teawater add for arm2x86 2005.06.19------------------------------------------- arm920t_mmu_v2p_dbct, //AJ2D-------------------------------------------------------------------------- }; ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/rb.c�����������������������������������������������������������0000644�0001750�0000144�00000004444�10555732132�016600� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "armdefs.h" /*chy 2004-06-06, fix bug found by wenye@cs.ucsb.edu*/ ARMword rb_masks[] = { 0x0, //RB_INVALID 4, //RB_1 16, //RB_4 32, //RB_8 }; /*mmu_rb_init * @rb_t :rb_t to init * @num :number of entry * */ int mmu_rb_init (rb_t * rb_t, int num) { int i; rb_entry_t *entrys; entrys = (rb_entry_t *) malloc (sizeof (*entrys) * num); if (entrys == NULL) { printf ("SKYEYE:mmu_rb_init malloc error\n"); return -1; } for (i = 0; i < num; i++) { entrys[i].type = RB_INVALID; entrys[i].fault = 0; } rb_t->entrys = entrys; rb_t->num = num; return 0; } /*mmu_rb_exit*/ void mmu_rb_exit (rb_t * rb_t) { free (rb_t->entrys); }; /*mmu_rb_search * @rb_t :rb_t to serach * @va :va address to math * * $ NULL :not match * NO-NULL: * */ rb_entry_t * mmu_rb_search (rb_t * rb_t, ARMword va) { int i; rb_entry_t *rb = rb_t->entrys; d_msg ("va = %x\n", va); for (i = 0; i < rb_t->num; i++, rb++) { //2004-06-06 lyh bug from wenye@cs.ucsb.edu if (rb->type) { if ((va >= rb->va) && (va < (rb->va + rb_masks[rb->type]))) return rb; } } return NULL; }; void mmu_rb_invalidate_entry (rb_t * rb_t, int i) { rb_t->entrys[i].type = RB_INVALID; } void mmu_rb_invalidate_all (rb_t * rb_t) { int i; for (i = 0; i < rb_t->num; i++) mmu_rb_invalidate_entry (rb_t, i); }; void mmu_rb_load (ARMul_State * state, rb_t * rb_t, int i_rb, int type, ARMword va) { rb_entry_t *rb; int i; ARMword max_start, min_end; fault_t fault; tlb_entry_t *tlb; /*align va according to type */ va &= ~(rb_masks[type] - 1); /*invalidate all RB match [va, va + rb_masks[type]] */ for (rb = rb_t->entrys, i = 0; i < rb_t->num; i++, rb++) { if (rb->type) { max_start = max (va, rb->va); min_end = min (va + rb_masks[type], rb->va + rb_masks[rb->type]); if (max_start < min_end) rb->type = RB_INVALID; } } /*load word */ rb = &rb_t->entrys[i_rb]; rb->type = type; fault = translate (state, va, D_TLB (), &tlb); if (fault) { rb->fault = fault; return; } fault = check_access (state, va, tlb, 1); if (fault) { rb->fault = fault; return; } rb->fault = 0; va = tlb_va_to_pa (tlb, va); //2004-06-06 lyh bug from wenye@cs.ucsb.edu for (i = 0; i < (rb_masks[type] / 4); i++, va += WORD_SIZE) { rb->data[i] = mem_read_word (state, va); }; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/arm920t_mmu.h��������������������������������������������������0000644�0001750�0000144�00000002002�10541455476�020252� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* arm920t_mmu.h - ARM920T Memory Management Unit emulation. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ARM920T_MMU_H_ #define _ARM920T_MMU_H_ typedef struct arm920t_mmu_s { tlb_t i_tlb; cache_t i_cache; tlb_t d_tlb; cache_t d_cache; wb_t wb_t; } arm920t_mmu_t; extern mmu_ops_t arm920t_mmu_ops; #endif /*_ARM920T_MMU_H_*/ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/rb.h�����������������������������������������������������������0000644�0001750�0000144�00000001751�10541455476�016613� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _MMU_RB_H #define _MMU_RB_H enum rb_type_t { RB_INVALID = 0, //invalid RB_1, //1 word RB_4, //4 word RB_8, //8 word }; /*bytes of each rb_type*/ extern ARMword rb_masks[]; #define RB_WORD_NUM 8 typedef struct rb_entry_s { ARMword data[RB_WORD_NUM]; //array to store data ARMword va; //first word va int type; //rb type fault_t fault; //fault set by rb alloc } rb_entry_t; typedef struct rb_s { int num; rb_entry_t *entrys; } rb_t; /*mmu_rb_init * @rb_t :rb_t to init * @num :number of entry * */ int mmu_rb_init (rb_t * rb_t, int num); /*mmu_rb_exit*/ void mmu_rb_exit (rb_t * rb_t); /*mmu_rb_search * @rb_t :rb_t to serach * @va :va address to math * * $ NULL :not match * NO-NULL: * */ rb_entry_t *mmu_rb_search (rb_t * rb_t, ARMword va); void mmu_rb_invalidate_entry (rb_t * rb_t, int i); void mmu_rb_invalidate_all (rb_t * rb_t); void mmu_rb_load (ARMul_State * state, rb_t * rb_t, int i_rb, int type, ARMword va); #endif /*_MMU_RB_H_*/ �����������������������skyeye-1.2.5_REL/arch/arm/common/mmu/maverick.c�����������������������������������������������������0000644�0001750�0000144�00000066257�10555732132�020010� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* maverick.c -- Cirrus/DSP co-processor interface. Copyright (C) 2003 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <assert.h> #include "armdefs.h" #include "ansidecl.h" #include "armemu.h" /*#define CIRRUS_DEBUG 1 */ #if CIRRUS_DEBUG # define printfdbg printf #else # define printfdbg printf_nothing #endif #define POS64(i) ( (~(i)) >> 63 ) #define NEG64(i) ( (i) >> 63 ) /* Define Co-Processor instruction handlers here. */ /* Here's ARMulator's DSP definition. A few things to note: 1) it has 16 64-bit registers and 4 72-bit accumulators 2) you can only access its registers with MCR and MRC. */ /* We can't define these in here because this file might not be linked unless the target is arm9e-*. They are defined in wrapper.c. Eventually the simulator should be made to handle any coprocessor at run time. */ struct maverick_regs { union { int i; float f; } upper; union { int i; float f; } lower; }; union maverick_acc_regs { long double ld; /* Acc registers are 72-bits. */ }; struct maverick_regs DSPregs[16]; union maverick_acc_regs DSPacc[4]; ARMword DSPsc; #define DEST_REG (BITS (12, 15)) #define SRC1_REG (BITS (16, 19)) #define SRC2_REG (BITS (0, 3)) static int lsw_int_index, msw_int_index; static int lsw_float_index, msw_float_index; static double mv_getRegDouble (int); static long long mv_getReg64int (int); static void mv_setRegDouble (int, double val); static void mv_setReg64int (int, long long val); static union { double d; long long ll; int ints[2]; } reg_conv; static void printf_nothing (void *foo, ...) { } static void cirrus_not_implemented (char *insn) { fprintf (stderr, "Cirrus instruction '%s' not implemented.\n", insn); fprintf (stderr, "aborting!\n"); skyeye_exit (1); } static unsigned DSPInit (ARMul_State * state) { ARMul_ConsolePrint (state, ", DSP present"); return TRUE; } unsigned DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { switch (BITS (5, 7)) { case 0: /* cfmvrdl */ /* Move lower half of a DF stored in a DSP reg into an Arm reg. */ printfdbg ("cfmvrdl\n"); printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i); printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); *value = (ARMword) DSPregs[SRC1_REG].lower.i; break; case 1: /* cfmvrdh */ /* Move upper half of a DF stored in a DSP reg into an Arm reg. */ printfdbg ("cfmvrdh\n"); printfdbg ("\tupper half=0x%x\n", DSPregs[SRC1_REG].upper.i); printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); *value = (ARMword) DSPregs[SRC1_REG].upper.i; break; case 2: /* cfmvrs */ /* Move SF from upper half of a DSP register to an Arm register. */ *value = (ARMword) DSPregs[SRC1_REG].upper.i; printfdbg ("cfmvrs = mvf%d <-- %f\n", SRC1_REG, DSPregs[SRC1_REG].upper.f); break; #ifdef doesnt_work case 4: /* cfcmps */ { float a, b; int n, z, c, v; a = DSPregs[SRC1_REG].upper.f; b = DSPregs[SRC2_REG].upper.f; printfdbg ("cfcmps\n"); printfdbg ("\tcomparing %f and %f\n", a, b); z = a == b; /* zero */ n = a != b; /* negative */ v = a > b; /* overflow */ c = 0; /* carry */ *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } case 5: /* cfcmpd */ { double a, b; int n, z, c, v; a = mv_getRegDouble (SRC1_REG); b = mv_getRegDouble (SRC2_REG); printfdbg ("cfcmpd\n"); printfdbg ("\tcomparing %g and %g\n", a, b); z = a == b; /* zero */ n = a != b; /* negative */ v = a > b; /* overflow */ c = 0; /* carry */ *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } #else case 4: /* cfcmps */ { float a, b; int n, z, c, v; a = DSPregs[SRC1_REG].upper.f; b = DSPregs[SRC2_REG].upper.f; printfdbg ("cfcmps\n"); printfdbg ("\tcomparing %f and %f\n", a, b); z = a == b; /* zero */ n = a < b; /* negative */ c = a > b; /* carry */ v = 0; /* fixme */ printfdbg ("\tz = %d, n = %d\n", z, n); *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } case 5: /* cfcmpd */ { double a, b; int n, z, c, v; a = mv_getRegDouble (SRC1_REG); b = mv_getRegDouble (SRC2_REG); printfdbg ("cfcmpd\n"); printfdbg ("\tcomparing %g and %g\n", a, b); z = a == b; /* zero */ n = a < b; /* negative */ c = a > b; /* carry */ v = 0; /* fixme */ *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } #endif default: fprintf (stderr, "unknown opcode in DSPMRC4 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { switch (BITS (5, 7)) { case 0: /* cfmvr64l */ /* Move lower half of 64bit int from Cirrus to Arm. */ *value = (ARMword) DSPregs[SRC1_REG].lower.i; printfdbg ("cfmvr64l ARM_REG = mvfx%d <-- %d\n", DEST_REG, (int) *value); break; case 1: /* cfmvr64h */ /* Move upper half of 64bit int from Cirrus to Arm. */ *value = (ARMword) DSPregs[SRC1_REG].upper.i; printfdbg ("cfmvr64h <-- %d\n", (int) *value); break; case 4: /* cfcmp32 */ { int res; int n, z, c, v; unsigned int a, b; printfdbg ("cfcmp32 mvfx%d - mvfx%d\n", SRC1_REG, SRC2_REG); /* FIXME: see comment for cfcmps. */ a = DSPregs[SRC1_REG].lower.i; b = DSPregs[SRC2_REG].lower.i; res = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i; /* zero */ z = res == 0; /* negative */ n = res < 0; /* overflow */ v = SubOverflow (DSPregs[SRC1_REG].lower.i, DSPregs[SRC2_REG].lower.i, res); /* carry */ c = (NEG (a) && POS (b) || (NEG (a) && POS (res)) || (POS (b) && POS (res))); *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } case 5: /* cfcmp64 */ { long long res; int n, z, c, v; unsigned long long a, b; printfdbg ("cfcmp64 mvdx%d - mvdx%d\n", SRC1_REG, SRC2_REG); /* fixme: see comment for cfcmps. */ a = mv_getReg64int (SRC1_REG); b = mv_getReg64int (SRC2_REG); res = mv_getReg64int (SRC1_REG) - mv_getReg64int (SRC2_REG); /* zero */ z = res == 0; /* negative */ n = res < 0; /* overflow */ v = ((NEG64 (a) && POS64 (b) && POS64 (res)) || (POS64 (a) && NEG64 (b) && NEG64 (res))); /* carry */ c = (NEG64 (a) && POS64 (b) || (NEG64 (a) && POS64 (res)) || (POS64 (b) && POS64 (res))); *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } default: fprintf (stderr, "unknown opcode in DSPMRC5 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPMRC6 (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value) { switch (BITS (5, 7)) { case 0: /* cfmval32 */ cirrus_not_implemented ("cfmval32"); break; case 1: /* cfmvam32 */ cirrus_not_implemented ("cfmvam32"); break; case 2: /* cfmvah32 */ cirrus_not_implemented ("cfmvah32"); break; case 3: /* cfmva32 */ cirrus_not_implemented ("cfmva32"); break; case 4: /* cfmva64 */ cirrus_not_implemented ("cfmva64"); break; case 5: /* cfmvsc32 */ cirrus_not_implemented ("cfmvsc32"); break; default: fprintf (stderr, "unknown opcode in DSPMRC6 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPMCR4 (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { switch (BITS (5, 7)) { case 0: /* cfmvdlr */ /* Move the lower half of a DF value from an Arm register into the lower half of a Cirrus register. */ printfdbg ("cfmvdlr <-- 0x%x\n", (int) value); DSPregs[SRC1_REG].lower.i = (int) value; break; case 1: /* cfmvdhr */ /* Move the upper half of a DF value from an Arm register into the upper half of a Cirrus register. */ printfdbg ("cfmvdhr <-- 0x%x\n", (int) value); DSPregs[SRC1_REG].upper.i = (int) value; break; case 2: /* cfmvsr */ /* Move SF from Arm register into upper half of Cirrus register. */ printfdbg ("cfmvsr <-- 0x%x\n", (int) value); DSPregs[SRC1_REG].upper.i = (int) value; break; default: fprintf (stderr, "unknown opcode in DSPMCR4 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPMCR5 (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { union { int s; unsigned int us; } val; switch (BITS (5, 7)) { case 0: /* cfmv64lr */ /* Move lower half of a 64bit int from an ARM register into the lower half of a DSP register and sign extend it. */ printfdbg ("cfmv64lr mvdx%d <-- 0x%x\n", SRC1_REG, (int) value); DSPregs[SRC1_REG].lower.i = (int) value; break; case 1: /* cfmv64hr */ /* Move upper half of a 64bit int from an ARM register into the upper half of a DSP register. */ printfdbg ("cfmv64hr ARM_REG = mvfx%d <-- 0x%x\n", SRC1_REG, (int) value); DSPregs[SRC1_REG].upper.i = (int) value; break; case 2: /* cfrshl32 */ printfdbg ("cfrshl32\n"); val.us = value; if (val.s > 0) DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i << value; else DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -value; break; case 3: /* cfrshl64 */ printfdbg ("cfrshl64\n"); val.us = value; if (val.s > 0) mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) << value); else mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) >> -value); break; default: fprintf (stderr, "unknown opcode in DSPMCR5 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPMCR6 (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value) { switch (BITS (5, 7)) { case 0: /* cfmv32al */ cirrus_not_implemented ("cfmv32al"); break; case 1: /* cfmv32am */ cirrus_not_implemented ("cfmv32am"); break; case 2: /* cfmv32ah */ cirrus_not_implemented ("cfmv32ah"); break; case 3: /* cfmv32a */ cirrus_not_implemented ("cfmv32a"); break; case 4: /* cfmv64a */ cirrus_not_implemented ("cfmv64a"); break; case 5: /* cfmv32sc */ cirrus_not_implemented ("cfmv32sc"); break; default: fprintf (stderr, "unknown opcode in DSPMCR6 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword data) { static unsigned words; if (type != ARMul_DATA) { words = 0; return ARMul_DONE; } if (BIT (22)) { /* it's a long access, get two words */ /* cfldrd */ printfdbg ("cfldrd: %x (words = %d) (bigend = %d) DESTREG = %d\n", data, words, state->bigendSig, DEST_REG); if (words == 0) { if (state->bigendSig) DSPregs[DEST_REG].upper.i = (int) data; else DSPregs[DEST_REG].lower.i = (int) data; } else { if (state->bigendSig) DSPregs[DEST_REG].lower.i = (int) data; else DSPregs[DEST_REG].upper.i = (int) data; } ++words; if (words == 2) { printfdbg ("\tmvd%d <-- mem = %g\n", DEST_REG, mv_getRegDouble (DEST_REG)); return ARMul_DONE; } else return ARMul_INC; } else { /* Get just one word. */ /* cfldrs */ printfdbg ("cfldrs\n"); DSPregs[DEST_REG].upper.i = (int) data; printfdbg ("\tmvf%d <-- mem = %f\n", DEST_REG, DSPregs[DEST_REG].upper.f); return ARMul_DONE; } } unsigned DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword data) { static unsigned words; if (type != ARMul_DATA) { words = 0; return ARMul_DONE; } if (BIT (22)) { /* It's a long access, get two words. */ /* cfldr64 */ printfdbg ("cfldr64: %d\n", data); if (words == 0) { if (state->bigendSig) DSPregs[DEST_REG].upper.i = (int) data; else DSPregs[DEST_REG].lower.i = (int) data; } else { if (state->bigendSig) DSPregs[DEST_REG].lower.i = (int) data; else DSPregs[DEST_REG].upper.i = (int) data; } ++words; if (words == 2) { printfdbg ("\tmvdx%d <-- mem = %lld\n", DEST_REG, mv_getReg64int (DEST_REG)); return ARMul_DONE; } else return ARMul_INC; } else { /* Get just one word. */ /* cfldr32 */ printfdbg ("cfldr32 mvfx%d <-- %d\n", DEST_REG, (int) data); /* 32bit ints should be sign extended to 64bits when loaded. */ mv_setReg64int (DEST_REG, (long long) data); return ARMul_DONE; } } unsigned DSPSTC4 (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword * data) { static unsigned words; if (type != ARMul_DATA) { words = 0; return ARMul_DONE; } if (BIT (22)) { /* It's a long access, get two words. */ /* cfstrd */ printfdbg ("cfstrd\n"); if (words == 0) { if (state->bigendSig) *data = (ARMword) DSPregs[DEST_REG].upper.i; else *data = (ARMword) DSPregs[DEST_REG].lower.i; } else { if (state->bigendSig) *data = (ARMword) DSPregs[DEST_REG].lower.i; else *data = (ARMword) DSPregs[DEST_REG].upper.i; } ++words; if (words == 2) { printfdbg ("\tmem = mvd%d = %g\n", DEST_REG, mv_getRegDouble (DEST_REG)); return ARMul_DONE; } else return ARMul_INC; } else { /* Get just one word. */ /* cfstrs */ printfdbg ("cfstrs mvf%d <-- %f\n", DEST_REG, DSPregs[DEST_REG].upper.f); *data = (ARMword) DSPregs[DEST_REG].upper.i; return ARMul_DONE; } } unsigned DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword * data) { static unsigned words; if (type != ARMul_DATA) { words = 0; return ARMul_DONE; } if (BIT (22)) { /* It's a long access, store two words. */ /* cfstr64 */ printfdbg ("cfstr64\n"); if (words == 0) { if (state->bigendSig) *data = (ARMword) DSPregs[DEST_REG].upper.i; else *data = (ARMword) DSPregs[DEST_REG].lower.i; } else { if (state->bigendSig) *data = (ARMword) DSPregs[DEST_REG].lower.i; else *data = (ARMword) DSPregs[DEST_REG].upper.i; } ++words; if (words == 2) { printfdbg ("\tmem = mvd%d = %lld\n", DEST_REG, mv_getReg64int (DEST_REG)); return ARMul_DONE; } else return ARMul_INC; } else { /* Store just one word. */ /* cfstr32 */ *data = (ARMword) DSPregs[DEST_REG].lower.i; printfdbg ("cfstr32 MEM = %d\n", (int) *data); return ARMul_DONE; } } unsigned DSPCDP4 (ARMul_State * state, unsigned type, ARMword instr) { int opcode2; opcode2 = BITS (5, 7); switch (BITS (20, 21)) { case 0: switch (opcode2) { case 0: /* cfcpys */ printfdbg ("cfcpys mvf%d = mvf%d = %f\n", DEST_REG, SRC1_REG, DSPregs[SRC1_REG].upper.f); DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f; break; case 1: /* cfcpyd */ printfdbg ("cfcpyd mvd%d = mvd%d = %g\n", DEST_REG, SRC1_REG, mv_getRegDouble (SRC1_REG)); mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG)); break; case 2: /* cfcvtds */ printfdbg ("cfcvtds mvf%d = (float) mvd%d = %f\n", DEST_REG, SRC1_REG, (float) mv_getRegDouble (SRC1_REG)); DSPregs[DEST_REG].upper.f = (float) mv_getRegDouble (SRC1_REG); break; case 3: /* cfcvtsd */ printfdbg ("cfcvtsd mvd%d = mvf%d = %g\n", DEST_REG, SRC1_REG, (double) DSPregs[SRC1_REG].upper.f); mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].upper.f); break; case 4: /* cfcvt32s */ printfdbg ("cfcvt32s mvf%d = mvfx%d = %f\n", DEST_REG, SRC1_REG, (float) DSPregs[SRC1_REG].lower.i); DSPregs[DEST_REG].upper.f = (float) DSPregs[SRC1_REG].lower.i; break; case 5: /* cfcvt32d */ printfdbg ("cfcvt32d mvd%d = mvfx%d = %g\n", DEST_REG, SRC1_REG, (double) DSPregs[SRC1_REG].lower.i); mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].lower.i); break; case 6: /* cfcvt64s */ printfdbg ("cfcvt64s mvf%d = mvdx%d = %f\n", DEST_REG, SRC1_REG, (float) mv_getReg64int (SRC1_REG)); DSPregs[DEST_REG].upper.f = (float) mv_getReg64int (SRC1_REG); break; case 7: /* cfcvt64d */ printfdbg ("cfcvt64d mvd%d = mvdx%d = %g\n", DEST_REG, SRC1_REG, (double) mv_getReg64int (SRC1_REG)); mv_setRegDouble (DEST_REG, (double) mv_getReg64int (SRC1_REG)); break; } break; case 1: switch (opcode2) { case 0: /* cfmuls */ printfdbg ("cfmuls mvf%d = mvf%d = %f\n", DEST_REG, SRC1_REG, DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f); DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f; break; case 1: /* cfmuld */ printfdbg ("cfmuld mvd%d = mvd%d = %g\n", DEST_REG, SRC1_REG, mv_getRegDouble (SRC1_REG) * mv_getRegDouble (SRC2_REG)); mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG) * mv_getRegDouble (SRC2_REG)); break; default: fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } break; case 3: switch (opcode2) { case 0: /* cfabss */ DSPregs[DEST_REG].upper.f = (DSPregs[SRC1_REG].upper.f < 0.0F ? -DSPregs[SRC1_REG].upper. f : DSPregs[SRC1_REG].upper.f); printfdbg ("cfabss mvf%d = |mvf%d| = %f\n", DEST_REG, SRC1_REG, DSPregs[DEST_REG].upper.f); break; case 1: /* cfabsd */ mv_setRegDouble (DEST_REG, (mv_getRegDouble (SRC1_REG) < 0.0 ? -mv_getRegDouble (SRC1_REG) : mv_getRegDouble (SRC1_REG))); printfdbg ("cfabsd mvd%d = |mvd%d| = %g\n", DEST_REG, SRC1_REG, mv_getRegDouble (DEST_REG)); break; case 2: /* cfnegs */ DSPregs[DEST_REG].upper.f = -DSPregs[SRC1_REG].upper.f; printfdbg ("cfnegs mvf%d = -mvf%d = %f\n", DEST_REG, SRC1_REG, DSPregs[DEST_REG].upper.f); break; case 3: /* cfnegd */ mv_setRegDouble (DEST_REG, -mv_getRegDouble (SRC1_REG)); printfdbg ("cfnegd mvd%d = -mvd%d = %g\n", DEST_REG, mv_getRegDouble (DEST_REG)); break; case 4: /* cfadds */ DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + DSPregs[SRC2_REG].upper.f; printfdbg ("cfadds mvf%d = mvf%d + mvf%d = %f\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].upper.f); break; case 5: /* cfaddd */ mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG) + mv_getRegDouble (SRC2_REG)); printfdbg ("cfaddd: mvd%d = mvd%d + mvd%d = %g\n", DEST_REG, SRC1_REG, SRC2_REG, mv_getRegDouble (DEST_REG)); break; case 6: /* cfsubs */ DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f - DSPregs[SRC2_REG].upper.f; printfdbg ("cfsubs: mvf%d = mvf%d - mvf%d = %f\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].upper.f); break; case 7: /* cfsubd */ mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG) - mv_getRegDouble (SRC2_REG)); printfdbg ("cfsubd: mvd%d = mvd%d - mvd%d = %g\n", DEST_REG, SRC1_REG, SRC2_REG, mv_getRegDouble (DEST_REG)); break; } break; default: fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPCDP5 (ARMul_State * state, unsigned type, ARMword instr) { int opcode2; char shift; opcode2 = BITS (5, 7); /* Shift constants are 7bit signed numbers in bits 0..3|5..7. */ shift = BITS (0, 3) | (BITS (5, 7)) << 4; if (shift & 0x40) shift |= 0xc0; switch (BITS (20, 21)) { case 0: /* cfsh32 */ printfdbg ("cfsh32 %s amount=%d\n", shift < 0 ? "right" : "left", shift); if (shift < 0) /* Negative shift is a right shift. */ DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -shift; else /* Positive shift is a left shift. */ DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i << shift; break; case 1: switch (opcode2) { case 0: /* cfmul32 */ DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; printfdbg ("cfmul32 mvfx%d = mvfx%d * mvfx%d = %d\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].lower.i); break; case 1: /* cfmul64 */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) * mv_getReg64int (SRC2_REG)); printfdbg ("cfmul64 mvdx%d = mvdx%d * mvdx%d = %lld\n", DEST_REG, SRC1_REG, SRC2_REG, mv_getReg64int (DEST_REG)); break; case 2: /* cfmac32 */ DSPregs[DEST_REG].lower.i += DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; printfdbg ("cfmac32 mvfx%d += mvfx%d * mvfx%d = %d\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].lower.i); break; case 3: /* cfmsc32 */ DSPregs[DEST_REG].lower.i -= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; printfdbg ("cfmsc32 mvfx%d -= mvfx%d * mvfx%d = %d\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].lower.i); break; case 4: /* cfcvts32 */ /* fixme: this should round */ DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; printfdbg ("cfcvts32 mvfx%d = mvf%d = %d\n", DEST_REG, SRC1_REG, DSPregs[DEST_REG].lower.i); break; case 5: /* cfcvtd32 */ /* fixme: this should round */ DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); printfdbg ("cfcvtd32 mvdx%d = mvd%d = %d\n", DEST_REG, SRC1_REG, DSPregs[DEST_REG].lower.i); break; case 6: /* cftruncs32 */ DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; printfdbg ("cftruncs32 mvfx%d = mvf%d = %d\n", DEST_REG, SRC1_REG, DSPregs[DEST_REG].lower.i); break; case 7: /* cftruncd32 */ DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); printfdbg ("cftruncd32 mvfx%d = mvd%d = %d\n", DEST_REG, SRC1_REG, DSPregs[DEST_REG].lower.i); break; } break; case 2: /* cfsh64 */ printfdbg ("cfsh64\n"); if (shift < 0) /* Negative shift is a right shift. */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) >> -shift); else /* Positive shift is a left shift. */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) << shift); printfdbg ("\t%llx\n", mv_getReg64int (DEST_REG)); break; case 3: switch (opcode2) { case 0: /* cfabs32 */ DSPregs[DEST_REG].lower.i = (DSPregs[SRC1_REG].lower.i < 0 ? -DSPregs[SRC1_REG].lower. i : DSPregs[SRC1_REG].lower.i); printfdbg ("cfabs32 mvfx%d = |mvfx%d| = %d\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].lower.i); break; case 1: /* cfabs64 */ mv_setReg64int (DEST_REG, (mv_getReg64int (SRC1_REG) < 0 ? -mv_getReg64int (SRC1_REG) : mv_getReg64int (SRC1_REG))); printfdbg ("cfabs64 mvdx%d = |mvdx%d| = %lld\n", DEST_REG, SRC1_REG, SRC2_REG, mv_getReg64int (DEST_REG)); break; case 2: /* cfneg32 */ DSPregs[DEST_REG].lower.i = -DSPregs[SRC1_REG].lower.i; printfdbg ("cfneg32 mvfx%d = -mvfx%d = %d\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].lower.i); break; case 3: /* cfneg64 */ mv_setReg64int (DEST_REG, -mv_getReg64int (SRC1_REG)); printfdbg ("cfneg64 mvdx%d = -mvdx%d = %lld\n", DEST_REG, SRC1_REG, SRC2_REG, mv_getReg64int (DEST_REG)); break; case 4: /* cfadd32 */ DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + DSPregs[SRC2_REG].lower.i; printfdbg ("cfadd32 mvfx%d = mvfx%d + mvfx%d = %d\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].lower.i); break; case 5: /* cfadd64 */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) + mv_getReg64int (SRC2_REG)); printfdbg ("cfadd64 mvdx%d = mvdx%d + mvdx%d = %lld\n", DEST_REG, SRC1_REG, SRC2_REG, mv_getReg64int (DEST_REG)); break; case 6: /* cfsub32 */ DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i; printfdbg ("cfsub32 mvfx%d = mvfx%d - mvfx%d = %d\n", DEST_REG, SRC1_REG, SRC2_REG, DSPregs[DEST_REG].lower.i); break; case 7: /* cfsub64 */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) - mv_getReg64int (SRC2_REG)); printfdbg ("cfsub64 mvdx%d = mvdx%d - mvdx%d = %d\n", DEST_REG, SRC1_REG, SRC2_REG, mv_getReg64int (DEST_REG)); break; } break; default: fprintf (stderr, "unknown opcode in DSPCDP5 0x%x\n", instr); cirrus_not_implemented ("unknown"); break; } return ARMul_DONE; } unsigned DSPCDP6 (ARMul_State * state, unsigned type, ARMword instr) { int opcode2; opcode2 = BITS (5, 7); switch (BITS (20, 21)) { case 0: /* cfmadd32 */ cirrus_not_implemented ("cfmadd32"); break; case 1: /* cfmsub32 */ cirrus_not_implemented ("cfmsub32"); break; case 2: /* cfmadda32 */ cirrus_not_implemented ("cfmadda32"); break; case 3: /* cfmsuba32 */ cirrus_not_implemented ("cfmsuba32"); break; default: fprintf (stderr, "unknown opcode in DSPCDP6 0x%x\n", instr); } return ARMul_DONE; } /* Conversion functions. 32-bit integers are stored in the LOWER half of a 64-bit physical register. Single precision floats are stored in the UPPER half of a 64-bit physical register. */ static double mv_getRegDouble (int regnum) { reg_conv.ints[lsw_float_index] = DSPregs[regnum].upper.i; reg_conv.ints[msw_float_index] = DSPregs[regnum].lower.i; return reg_conv.d; } static void mv_setRegDouble (int regnum, double val) { reg_conv.d = val; DSPregs[regnum].upper.i = reg_conv.ints[lsw_float_index]; DSPregs[regnum].lower.i = reg_conv.ints[msw_float_index]; } static long long mv_getReg64int (int regnum) { reg_conv.ints[lsw_int_index] = DSPregs[regnum].lower.i; reg_conv.ints[msw_int_index] = DSPregs[regnum].upper.i; return reg_conv.ll; } static void mv_setReg64int (int regnum, long long val) { reg_conv.ll = val; DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index]; DSPregs[regnum].upper.i = reg_conv.ints[msw_int_index]; } /* Compute LSW in a double and a long long. */ void mv_compute_host_endianness (ARMul_State * state) { static union { long long ll; int ints[2]; int i; double d; float floats[2]; float f; } conv; /* Calculate where's the LSW in a 64bit int. */ conv.ll = 45; if (conv.ints[0] == 0) { msw_int_index = 0; lsw_int_index = 1; } else { assert (conv.ints[1] == 0); msw_int_index = 1; lsw_int_index = 0; } /* Calculate where's the LSW in a double. */ conv.d = 3.0; if (conv.ints[0] == 0) { msw_float_index = 0; lsw_float_index = 1; } else { assert (conv.ints[1] == 0); msw_float_index = 1; lsw_float_index = 0; } printfdbg ("lsw_int_index %d\n", lsw_int_index); printfdbg ("lsw_float_index %d\n", lsw_float_index); } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/tlb.c����������������������������������������������������������0000644�0001750�0000144�00000015701�10555732132�016754� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <assert.h> #include "armdefs.h" ARMword tlb_masks[] = { 0x00000000, /* TLB_INVALID */ 0xFFFFF000, /* TLB_SMALLPAGE */ 0xFFFF0000, /* TLB_LARGEPAGE */ 0xFFF00000, /* TLB_SECTION */ 0xFFFFF000, /*TLB_ESMALLPAGE, have TEX attirbute, only for XScale */ 0xFFFFFC00 /* TLB_TINYPAGE */ }; /* This function encodes table 8-2 Interpreting AP bits, returning non-zero if access is allowed. */ static int check_perms (ARMul_State * state, int ap, int read) { int s, r, user; s = state->mmu.control & CONTROL_SYSTEM; r = state->mmu.control & CONTROL_ROM; //chy 2006-02-15 , should consider system mode, don't conside 26bit mode user = (state->Mode == USER32MODE) || (state->Mode == USER26MODE) || (state->Mode == SYSTEM32MODE); switch (ap) { case 0: return read && ((s && !user) || r); case 1: return !user; case 2: return read || !user; case 3: return 1; } return 0; } fault_t check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb, int read) { int access; state->mmu.last_domain = tlb->domain; access = (state->mmu.domain_access_control >> (tlb->domain * 2)) & 3; if ((access == 0) || (access == 2)) { /* It's unclear from the documentation whether this should always raise a section domain fault, or if it should be a page domain fault in the case of an L1 that describes a page table. In the ARM710T datasheets, "Figure 8-9: Sequence for checking faults" seems to indicate the former, while "Table 8-4: Priority encoding of fault status" gives a value for FS[3210] in the event of a domain fault for a page. Hmm. */ return SECTION_DOMAIN_FAULT; } if (access == 1) { /* client access - check perms */ int subpage, ap; switch (tlb->mapping) { /*ks 2004-05-09 * only for XScale * Extend Small Page(ESP) Format * 31-12 bits the base addr of ESP * 11-10 bits SBZ * 9-6 bits TEX * 5-4 bits AP * 3 bit C * 2 bit B * 1-0 bits 11 * */ case TLB_ESMALLPAGE: //xj subpage = 0; //printf("TLB_ESMALLPAGE virt_addr=0x%x \n",virt_addr ); break; case TLB_TINYPAGE: subpage = 0; //printf("TLB_TINYPAGE virt_addr=0x%x \n",virt_addr ); break; case TLB_SMALLPAGE: subpage = (virt_addr >> 10) & 3; break; case TLB_LARGEPAGE: subpage = (virt_addr >> 14) & 3; break; case TLB_SECTION: subpage = 3; break; default: assert (0); subpage = 0; /* cleans a warning */ } ap = (tlb->perms >> (subpage * 2 + 4)) & 3; if (!check_perms (state, ap, read)) { if (tlb->mapping == TLB_SECTION) { return SECTION_PERMISSION_FAULT; } else { return SUBPAGE_PERMISSION_FAULT; } } } else { /* access == 3 */ /* manager access - don't check perms */ } return NO_FAULT; } fault_t translate (ARMul_State * state, ARMword virt_addr, tlb_t * tlb_t, tlb_entry_t ** tlb) { *tlb = mmu_tlb_search (state, tlb_t, virt_addr); if (!*tlb) { /* walk the translation tables */ ARMword l1addr, l1desc; tlb_entry_t entry; l1addr = state->mmu.translation_table_base & 0xFFFFC000; l1addr = (l1addr | (virt_addr >> 18)) & ~3; l1desc = mem_read_word (state, l1addr); switch (l1desc & 3) { case 0: //SBZ { return PAGE_TRANSLATION_FAULT; } case 3: /* fine page table */ // dcl 2006-01-08 { ARMword l2addr, l2desc; l2addr = l1desc & 0xFFFFF000; l2addr = (l2addr | ((virt_addr & 0x000FFC00) >> 8)) & ~3; l2desc = mem_read_word (state, l2addr); entry.virt_addr = virt_addr; entry.phys_addr = l2desc; entry.perms = l2desc & 0x00000FFC; entry.domain = (l1desc >> 5) & 0x0000000F; switch (l2desc & 3) { case 0: state->mmu.last_domain = entry.domain; return PAGE_TRANSLATION_FAULT; case 3: entry.mapping = TLB_TINYPAGE; break; case 1: // this is untested entry.mapping = TLB_LARGEPAGE; break; case 2: // this is untested entry.mapping = TLB_SMALLPAGE; break; } } break; case 1: /* coarse page table */ { ARMword l2addr, l2desc; l2addr = l1desc & 0xFFFFFC00; l2addr = (l2addr | ((virt_addr & 0x000FF000) >> 10)) & ~3; l2desc = mem_read_word (state, l2addr); entry.virt_addr = virt_addr; entry.phys_addr = l2desc; entry.perms = l2desc & 0x00000FFC; entry.domain = (l1desc >> 5) & 0x0000000F; //printf("SKYEYE:PAGE virt_addr = %x,l1desc=%x,phys_addr=%x\n",virt_addr,l1desc,entry.phys_addr); //chy 2003-09-02 for xscale switch (l2desc & 3) { case 0: state->mmu.last_domain = entry.domain; return PAGE_TRANSLATION_FAULT; case 3: if (!state->is_XScale) { state->mmu.last_domain = entry.domain; return PAGE_TRANSLATION_FAULT; }; //ks 2004-05-09 xscale shold use Extend Small Page //entry.mapping = TLB_SMALLPAGE; entry.mapping = TLB_ESMALLPAGE; //xj break; case 1: entry.mapping = TLB_LARGEPAGE; break; case 2: entry.mapping = TLB_SMALLPAGE; break; } } break; case 2: /* section */ //printf("SKYEYE:WARNING: not implement section mapping incompletely\n"); //printf("SKYEYE:SECTION virt_addr = %x,l1desc=%x\n",virt_addr,l1desc); //return SECTION_DOMAIN_FAULT; //#if 0 entry.virt_addr = virt_addr; entry.phys_addr = l1desc; entry.perms = l1desc & 0x00000C0C; entry.domain = (l1desc >> 5) & 0x0000000F; entry.mapping = TLB_SECTION; break; //#endif } entry.virt_addr &= tlb_masks[entry.mapping]; entry.phys_addr &= tlb_masks[entry.mapping]; /* place entry in the tlb */ *tlb = &tlb_t->entrys[tlb_t->cycle]; tlb_t->cycle = (tlb_t->cycle + 1) % tlb_t->num; **tlb = entry; } state->mmu.last_domain = (*tlb)->domain; return NO_FAULT; } int mmu_tlb_init (tlb_t * tlb_t, int num) { tlb_entry_t *e; int i; e = (tlb_entry_t *) malloc (sizeof (*e) * num); if (e == NULL) { err_msg ("malloc size %d\n", sizeof (*e) * num); goto tlb_malloc_error; } tlb_t->entrys = e; for (i = 0; i < num; i++, e++) e->mapping = TLB_INVALID; tlb_t->cycle = 0; tlb_t->num = num; return 0; tlb_malloc_error: return -1; } void mmu_tlb_exit (tlb_t * tlb_t) { free (tlb_t->entrys); }; void mmu_tlb_invalidate_all (ARMul_State * state, tlb_t * tlb_t) { int entry; for (entry = 0; entry < tlb_t->num; entry++) { tlb_t->entrys[entry].mapping = TLB_INVALID; } tlb_t->cycle = 0; } void mmu_tlb_invalidate_entry (ARMul_State * state, tlb_t * tlb_t, ARMword addr) { tlb_entry_t *tlb; tlb = mmu_tlb_search (state, tlb_t, addr); if (tlb) { tlb->mapping = TLB_INVALID; } } tlb_entry_t * mmu_tlb_search (ARMul_State * state, tlb_t * tlb_t, ARMword virt_addr) { int entry; for (entry = 0; entry < tlb_t->num; entry++) { tlb_entry_t *tlb; ARMword mask; tlb = &(tlb_t->entrys[entry]); if (tlb->mapping == TLB_INVALID) { continue; } mask = tlb_masks[tlb->mapping]; if ((virt_addr & mask) == (tlb->virt_addr & mask)) { return tlb; } } return NULL; } ���������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/arm7100_mmu.c��������������������������������������������������0000644�0001750�0000144�00000032505�10555732132�020141� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armmmu.c - Memory Management Unit emulation. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <assert.h> #include <string.h> #include "armdefs.h" #ifdef CACHE #undef CACHE #endif /* */ #ifdef TLB #undef TLB #endif /* */ #define CACHE() (&state->mmu.u.arm7100_mmu.cache_t) #define TLB() (&state->mmu.u.arm7100_mmu.tlb_t) static fault_t a71_mmu_read (ARMul_State * state, ARMword virt_addr, ARMword * data, ARMword datatype); static fault_t a71_mmu_write (ARMul_State * state, ARMword virt_addr, ARMword data, ARMword datatype); static int a71_mmu_init (ARMul_State * state) { state->mmu.control = 0x70; state->mmu.translation_table_base = 0xDEADC0DE; state->mmu.domain_access_control = 0xDEADC0DE; state->mmu.fault_status = 0; state->mmu.fault_address = 0; if (mmu_cache_init (CACHE (), 16, 4, 128, CACHE_WRITE_THROUGH)) { err_msg ("cache init %d\n", -1); goto cache_error; } if (mmu_tlb_init (TLB (), 64)) { err_msg ("tlb init %d\n", -1); goto tlb_error; }; return 0; tlb_error:mmu_cache_exit (CACHE ()); cache_error:return -1; } static void a71_mmu_exit (ARMul_State * state) { mmu_cache_exit (CACHE ()); mmu_tlb_exit (TLB ()); } static fault_t a71_mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = a71_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE); return fault; } static fault_t a71_mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = a71_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE); return fault; } static fault_t a71_mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data) { return a71_mmu_read (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t a71_mmu_read (ARMul_State * state, ARMword virt_addr, ARMword * data, ARMword datatype) { tlb_entry_t *tlb; ARMword phys_addr; ARMword temp, offset; fault_t fault; if (!(state->mmu.control & CONTROL_MMU)) { // *data = mem_read_word(state, virt_addr); //#if 0 if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, virt_addr); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, virt_addr); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, virt_addr); else { printf ("SKYEYE:1 a71_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } //#endif return NO_FAULT; } #if 0 /* XXX */ if (hack && (virt_addr >= 0xc0000000) && (virt_addr < 0xc0200000)) { printf ("0x%08x\n", virt_addr); } #endif /* */ if ((virt_addr & 3) && (datatype == ARM_WORD_TYPE) && (state->mmu.control & CONTROL_ALIGN_FAULT) || (virt_addr & 1) && (datatype == ARM_HALFWORD_TYPE) && (state->mmu.control & CONTROL_ALIGN_FAULT)) { fprintf (stderr, "SKYEYE, a71_mmu_read ALIGNMENT_FAULT\n"); return ALIGNMENT_FAULT; } if (state->mmu.control & CONTROL_CACHE) { cache_line_t *cache; cache = mmu_cache_search (state, CACHE (), virt_addr); if (cache) { if (datatype == ARM_WORD_TYPE) *data = cache->data[(virt_addr >> 2) & 3]; else if (datatype == ARM_HALFWORD_TYPE) { temp = cache->data[(virt_addr >> 2) & 3]; offset = (((ARMword) state->bigendSig * 2) ^ (virt_addr & 2)) << 3; /* bit offset into the word */ *data = (temp >> offset) & 0xffff; } else if (datatype == ARM_BYTE_TYPE) { temp = cache->data[(virt_addr >> 2) & 3]; offset = (((ARMword) state->bigendSig * 3) ^ (virt_addr & 3)) << 3; /* bit offset into the word */ *data = (temp >> offset & 0xffL); } return NO_FAULT; } } fault = translate (state, virt_addr, TLB (), &tlb); if (fault) { return fault; } fault = check_access (state, virt_addr, tlb, 1); if (fault) { return fault; } phys_addr = (tlb->phys_addr & tlb_masks[tlb->mapping]) | (virt_addr & ~tlb_masks[tlb->mapping]); /* allocate to the cache if cacheable */ if ((tlb->perms & 0x08) && (state->mmu.control & CONTROL_CACHE)) { cache_line_t *cache; ARMword fetch; int i; cache = mmu_cache_alloc (state, CACHE (), virt_addr, 0); fetch = phys_addr & 0xFFFFFFF0; for (i = 0; i < 4; i++) { cache->data[i] = mem_read_word (state, fetch); fetch += 4; } cache->tag = va_cache_align (virt_addr, CACHE ()) | TAG_VALID_FLAG; //*data = cache->data[(virt_addr >> 2) & 3]; if (datatype == ARM_WORD_TYPE) *data = cache->data[(virt_addr >> 2) & 3]; else if (datatype == ARM_HALFWORD_TYPE) { temp = cache->data[(virt_addr >> 2) & 3]; offset = (((ARMword) state->bigendSig * 2) ^ (virt_addr & 2)) << 3; /* bit offset into the word */ *data = (temp >> offset) & 0xffff; } else if (datatype == ARM_BYTE_TYPE) { temp = cache->data[(virt_addr >> 2) & 3]; offset = (((ARMword) state->bigendSig * 3) ^ (virt_addr & 3)) << 3; /* bit offset into the word */ *data = (temp >> offset & 0xffL); } return NO_FAULT; } else { if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, phys_addr); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, phys_addr); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, phys_addr); else { printf ("SKYEYE:2 a71_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return NO_FAULT; } } static fault_t a71_mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data) { return a71_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE); } static fault_t a71_mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data) { return a71_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE); } static fault_t a71_mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data) { return a71_mmu_write (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t a71_mmu_write (ARMul_State * state, ARMword virt_addr, ARMword data, ARMword datatype) { tlb_entry_t *tlb; ARMword phys_addr; fault_t fault; ARMword temp, offset; if (!(state->mmu.control & CONTROL_MMU)) { if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, virt_addr, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, virt_addr, data); else if (datatype == ARM_WORD_TYPE) mem_write_word (state, virt_addr, data); else { printf ("SKYEYE:1 a71_mmu_write error: unknown data type %d\n", datatype); skyeye_exit (-1); } return NO_FAULT; } // if ((virt_addr & 3) && (state->mmu.control & CONTROL_ALIGN_FAULT)) { if ((virt_addr & 3) && (datatype == ARM_WORD_TYPE) && (state->mmu.control & CONTROL_ALIGN_FAULT) || (virt_addr & 1) && (datatype == ARM_HALFWORD_TYPE) && (state->mmu.control & CONTROL_ALIGN_FAULT)) { fprintf (stderr, "SKYEYE, a71_mmu_write ALIGNMENT_FAULT\n"); return ALIGNMENT_FAULT; } if (state->mmu.control & CONTROL_CACHE) { cache_line_t *cache; cache = mmu_cache_search (state, CACHE (), virt_addr); if (cache) { if (datatype == ARM_WORD_TYPE) cache->data[(virt_addr >> 2) & 3] = data; else if (datatype == ARM_HALFWORD_TYPE) { temp = cache->data[(virt_addr >> 2) & 3]; offset = (((ARMword) state->bigendSig * 2) ^ (virt_addr & 2)) << 3; /* bit offset into the word */ cache->data[(virt_addr >> 2) & 3] = (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset); } else if (datatype == ARM_BYTE_TYPE) { temp = cache->data[(virt_addr >> 2) & 3]; offset = (((ARMword) state->bigendSig * 3) ^ (virt_addr & 3)) << 3; /* bit offset into the word */ cache->data[(virt_addr >> 2) & 3] = (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset); } } } fault = translate (state, virt_addr, TLB (), &tlb); if (fault) { return fault; } fault = check_access (state, virt_addr, tlb, 0); if (fault) { return fault; } phys_addr = (tlb->phys_addr & tlb_masks[tlb->mapping]) | (virt_addr & ~tlb_masks[tlb->mapping]); if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, phys_addr, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, phys_addr, data); else if (datatype == ARM_WORD_TYPE) mem_write_word (state, phys_addr, data); else { printf ("SKYEYE:2 a71_mmu_write error: unknown data type %d \n", datatype); skyeye_exit (-1); } return NO_FAULT; } static ARMword a71_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value) { mmu_regnum_t creg = BITS (16, 19) & 15; ARMword data; switch (creg) { case MMU_ID: // printf("mmu_mrc read ID "); #if 0 #ifdef MMU_V4 data = 0x41018100; /* v4 */ #else /* */ data = 0x41007100; /* v3 */ #endif /* */ #endif /* */ //data = 0x41007100; data = state->cpu->cpu_val; break; case MMU_CONTROL: // printf("mmu_mrc read CONTROL"); data = state->mmu.control; break; case MMU_TRANSLATION_TABLE_BASE: // printf("mmu_mrc read TTB "); data = state->mmu.translation_table_base; break; case MMU_DOMAIN_ACCESS_CONTROL: // printf("mmu_mrc read DACR "); data = state->mmu.domain_access_control; break; case MMU_FAULT_STATUS: // printf("mmu_mrc read FSR "); data = state->mmu.fault_status; break; case MMU_FAULT_ADDRESS: // printf("mmu_mrc read FAR "); data = state->mmu.fault_address; break; default: printf ("mmu_mrc read UNKNOWN - reg %d\n", creg); data = 0; break; } // printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]); *value = data; return data; } static void a71_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value) { mmu_regnum_t creg = BITS (16, 19) & 15; if (!strncmp (state->cpu->cpu_arch_name, "armv4", 5)) { switch (creg) { case MMU_CONTROL: // printf("mmu_mcr wrote CONTROL "); state->mmu.control = (value | 0x70) & 0xFFFF; break; case MMU_TRANSLATION_TABLE_BASE: // printf("mmu_mcr wrote TTB "); state->mmu.translation_table_base = value & 0xFFFFC000; break; case MMU_DOMAIN_ACCESS_CONTROL: // printf("mmu_mcr wrote DACR "); state->mmu.domain_access_control = value; break; //#ifdef MMU_V4 case MMU_FAULT_STATUS: state->mmu.fault_status = value & 0xFF; break; case MMU_FAULT_ADDRESS: state->mmu.fault_address = value; break; case MMU_V4_CACHE_OPS: /* incomplete */ if ((BITS (5, 7) & 7) == 0) { mmu_cache_invalidate_all (state, CACHE ()); } break; case MMU_V4_TLB_OPS: /* incomplete */ switch (BITS (5, 7) & 7) { case 0: mmu_tlb_invalidate_all (state, TLB ()); break; case 1: mmu_tlb_invalidate_entry (state, TLB (), value); break; } break; default: printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); break; } //#else } else { switch (creg) { case MMU_CONTROL: state->mmu.control = (value | 0x70) & 0xFFFF; break; case MMU_TRANSLATION_TABLE_BASE: state->mmu.translation_table_base = value & 0xFFFFC000; break; case MMU_DOMAIN_ACCESS_CONTROL: state->mmu.domain_access_control = value; break; case MMU_V3_FLUSH_TLB: // printf("mmu_mcr wrote FLUSH_TLB "); mmu_tlb_invalidate_all (state, TLB ()); break; case MMU_V3_FLUSH_TLB_ENTRY: // printf("mmu_mcr wrote FLUSH_TLB_ENTRY"); mmu_tlb_invalidate_entry (state, TLB (), value); break; case MMU_V3_FLUSH_CACHE: // printf("mmu_mcr wrote FLUSH_CACHE "); mmu_cache_invalidate_all (state, CACHE ()); break; default: printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); break; //#endif } } // printf("\t\t\t\tpc = 0x%08x\n", state->Reg[15]); } static int a71_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr) { tlb_entry_t *tlb; ARMword temp, offset; fault_t fault; ARMword datatype = ARM_WORD_TYPE; int ret = -1; if ((virt_addr & 3) && (datatype == ARM_WORD_TYPE) && (state->mmu.control & CONTROL_ALIGN_FAULT) || (virt_addr & 1) && (datatype == ARM_HALFWORD_TYPE) && (state->mmu.control & CONTROL_ALIGN_FAULT)) { fprintf (stderr, "SKYEYE, a71_mmu_read ALIGNMENT_FAULT\n"); goto out; } if (!(state->mmu.control & CONTROL_MMU)) { *phys_addr = virt_addr; } else { fault = translate (state, virt_addr, TLB (), &tlb); if (fault) { goto out; } fault = check_access (state, virt_addr, tlb, 1); if (fault) { goto out; } *phys_addr = (tlb->phys_addr & tlb_masks[tlb->mapping]) | (virt_addr & ~tlb_masks[tlb->mapping]); } ret = 0; out:return (ret); } #undef CACHE #undef TLB mmu_ops_t arm7100_mmu_ops = { a71_mmu_init, a71_mmu_exit, a71_mmu_read_byte, a71_mmu_write_byte, a71_mmu_read_halfword, a71_mmu_write_halfword, a71_mmu_read_word, a71_mmu_write_word, a71_mmu_read_word, // load instr a71_mmu_mcr, a71_mmu_mrc, a71_mmu_v2p_dbct // ywc 2005-04-16 test }; �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/cache.c��������������������������������������������������������0000644�0001750�0000144�00000016727�10555732132�017247� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "armdefs.h" /* mmu cache init * * @cache_t :cache_t to init * @width :cache line width in byte * @way :way of each cache set * @set :cache set num * * $ -1: error * 0: sucess */ int mmu_cache_init (cache_t * cache_t, int width, int way, int set, int w_mode) { int i, j; cache_set_t *sets; cache_line_t *lines; /*alloc cache set */ sets = NULL; lines = NULL; //fprintf(stderr, "mmu_cache_init: mallloc beg size %d,sets 0x%x\n", sizeof(cache_set_t) * set,sets); //exit(-1); sets = (cache_set_t *) malloc (sizeof (cache_set_t) * set); if (sets == NULL) { err_msg ("set malloc size %d\n", sizeof (cache_set_t) * set); goto sets_error; } //fprintf(stderr, "mmu_cache_init: mallloc end sets 0x%x\n", sets); cache_t->sets = sets; /*init cache set */ for (i = 0; i < set; i++) { /*alloc cache line */ lines = (cache_line_t *) malloc (sizeof (cache_line_t) * way); if (lines == NULL) { err_msg ("line malloc size %d\n", sizeof (cache_line_t) * way); goto lines_error; } /*init cache line */ for (j = 0; j < way; j++) { lines[j].tag = 0; //invalid lines[j].data = (ARMword *) malloc (width); if (lines[j].data == NULL) { err_msg ("data alloc size %d\n", width); goto data_error; } } sets[i].lines = lines; sets[i].cycle = 0; } cache_t->width = width; cache_t->set = set; cache_t->way = way; cache_t->w_mode = w_mode; return 0; data_error: /*free data */ while (j-- > 0) free (lines[j].data); /*free data error line */ free (lines); lines_error: /*free lines already alloced */ while (i-- > 0) { for (j = 0; j < way; j++) free (sets[i].lines[j].data); free (sets[i].lines); } /*free sets */ free (sets); sets_error: return -1; }; /* free a cache_t's inner data, the ptr self is not freed, * when needed do like below: * mmu_cache_exit(cache); * free(cache_t); * * @cache_t : the cache_t to free */ void mmu_cache_exit (cache_t * cache_t) { int i, j; cache_set_t *sets, *set; cache_line_t *lines, *line; /*free all set */ sets = cache_t->sets; for (set = sets, i = 0; i < cache_t->set; i++, set++) { /*free all line */ lines = set->lines; for (line = lines, j = 0; j < cache_t->way; j++, line++) free (line->data); free (lines); } free (sets); } /* mmu cache search * * @state :ARMul_State * @cache_t :cache_t to search * @va :virtual address * * $ NULL: no cache match * cache :cache matched */ cache_line_t * mmu_cache_search (ARMul_State * state, cache_t * cache_t, ARMword va) { int i; int set = va_cache_set (va, cache_t); ARMword tag = va_cache_align (va, cache_t); cache_line_t *cache; cache_set_t *cache_set = cache_t->sets + set; for (i = 0, cache = cache_set->lines; i < cache_t->way; i++, cache++) { if ((cache->tag & TAG_VALID_FLAG) && (tag == va_cache_align (cache->tag, cache_t))) return cache; } return NULL; } /* mmu cache search by set/index * * @state :ARMul_State * @cache_t :cache_t to search * @index :set/index value. * * $ NULL: no cache match * cache :cache matched */ cache_line_t * mmu_cache_search_by_index (ARMul_State * state, cache_t * cache_t, ARMword index) { int way = cache_t->way; int set_v = index_cache_set (index, cache_t); int i = 0, index_v = 0; cache_set_t *set; while ((way >>= 1) >= 1) i++; index_v = index >> (32 - i); set = cache_t->sets + set_v; return set->lines + index_v; } /* mmu cache alloc * * @state :ARMul_State * @cache_t :cache_t to alloc from * @va :virtual address that require cache alloc, need not cache aligned * @pa :physical address of va * * $ cache_alloced, always alloc OK */ cache_line_t * mmu_cache_alloc (ARMul_State * state, cache_t * cache_t, ARMword va, ARMword pa) { cache_line_t *cache; cache_set_t *set; int i; va = va_cache_align (va, cache_t); pa = va_cache_align (pa, cache_t); set = &cache_t->sets[va_cache_set (va, cache_t)]; /*robin-round */ cache = &set->lines[set->cycle++]; if (set->cycle == cache_t->way) set->cycle = 0; if (cache_t->w_mode == CACHE_WRITE_BACK) { ARMword t; /*if cache valid, try to write back */ if (cache->tag & TAG_VALID_FLAG) { mmu_cache_write_back (state, cache_t, cache); } /*read in cache_line */ t = pa; for (i = 0; i < (cache_t->width >> WORD_SHT); i++, t += WORD_SIZE) { cache->data[i] = mem_read_word (state, t); } } /*store tag and pa */ cache->tag = va | TAG_VALID_FLAG; cache->pa = pa; return cache; }; /* mmu_cache_write_back write cache data to memory * @state * @cache_t :cache_t of the cache line * @cache : cache line */ void mmu_cache_write_back (ARMul_State * state, cache_t * cache_t, cache_line_t * cache) { ARMword pa = cache->pa; int nw = cache_t->width >> WORD_SHT; ARMword *data = cache->data; int i; int t0, t1, t2; if ((cache->tag & 1) == 0) return; switch (cache-> tag & ~1 & (TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY)) { case 0: return; case TAG_FIRST_HALF_DIRTY: nw /= 2; break; case TAG_LAST_HALF_DIRTY: nw /= 2; pa += nw << WORD_SHT; data += nw; break; case TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY: break; } for (i = 0; i < nw; i++, data++, pa += WORD_SIZE) mem_write_word (state, pa, *data); cache->tag &= ~(TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY); }; /* mmu_cache_clean: clean a cache of va in cache_t * * @state :ARMul_State * @cache_t :cache_t to clean * @va :virtaul address */ void mmu_cache_clean (ARMul_State * state, cache_t * cache_t, ARMword va) { cache_line_t *cache; cache = mmu_cache_search (state, cache_t, va); if (cache) mmu_cache_write_back (state, cache_t, cache); } /* mmu_cache_clean_by_index: clean a cache by set/index format value * * @state :ARMul_State * @cache_t :cache_t to clean * @va :set/index format value */ void mmu_cache_clean_by_index (ARMul_State * state, cache_t * cache_t, ARMword index) { cache_line_t *cache; cache = mmu_cache_search_by_index (state, cache_t, index); if (cache) mmu_cache_write_back (state, cache_t, cache); } /* mmu_cache_invalidate : invalidate a cache of va * * @state :ARMul_State * @cache_t :cache_t to invalid * @va :virt_addr to invalid */ void mmu_cache_invalidate (ARMul_State * state, cache_t * cache_t, ARMword va) { cache_line_t *cache; cache = mmu_cache_search (state, cache_t, va); if (cache) { mmu_cache_write_back (state, cache_t, cache); cache->tag = 0; } } /* mmu_cache_invalidate_by_index : invalidate a cache by index format * * @state :ARMul_State * @cache_t :cache_t to invalid * @index :set/index data */ void mmu_cache_invalidate_by_index (ARMul_State * state, cache_t * cache_t, ARMword index) { cache_line_t *cache; cache = mmu_cache_search_by_index (state, cache_t, index); if (cache) { mmu_cache_write_back (state, cache_t, cache); cache->tag = 0; } } /* mmu_cache_invalidate_all * * @state: * @cache_t * */ void mmu_cache_invalidate_all (ARMul_State * state, cache_t * cache_t) { int i, j; cache_set_t *set; cache_line_t *cache; set = cache_t->sets; for (i = 0; i < cache_t->set; i++, set++) { cache = set->lines; for (j = 0; j < cache_t->way; j++, cache++) { mmu_cache_write_back (state, cache_t, cache); cache->tag = 0; } } }; void mmu_cache_soft_flush (ARMul_State * state, cache_t * cache_t, ARMword pa) { ARMword set, way; cache_line_t *cache; pa = (pa / cache_t->width); way = pa & (cache_t->way - 1); set = (pa / cache_t->way) & (cache_t->set - 1); cache = &cache_t->sets[set].lines[way]; mmu_cache_write_back (state, cache_t, cache); cache->tag = 0; } �����������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/tlb.h����������������������������������������������������������0000644�0001750�0000144�00000003702�10541455476�016767� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _MMU_TLB_H_ #define _MMU_TLB_H_ typedef enum tlb_mapping_t { TLB_INVALID = 0, TLB_SMALLPAGE = 1, TLB_LARGEPAGE = 2, TLB_SECTION = 3, TLB_ESMALLPAGE = 4, TLB_TINYPAGE = 5 } tlb_mapping_t; extern ARMword tlb_masks[]; /* Permissions bits in a TLB entry: * * 31 12 11 10 9 8 7 6 5 4 3 2 1 0 * +-------------+-----+-----+-----+-----+---+---+-------+ * Page:| | ap3 | ap2 | ap1 | ap0 | C | B | | * +-------------+-----+-----+-----+-----+---+---+-------+ * * 31 12 11 10 9 4 3 2 1 0 * +-------------+-----+-----------------+---+---+-------+ * Section: | | AP | | C | B | | * +-------------+-----+-----------------+---+---+-------+ */ /* section: section base address [31:20] AP - table 8-2, page 8-8 domain C,B page: page base address [31:16] or [31:12] ap[3:0] domain (from L1) C,B */ typedef struct tlb_entry_t { ARMword virt_addr; ARMword phys_addr; ARMword perms; ARMword domain; tlb_mapping_t mapping; } tlb_entry_t; typedef struct tlb_s { int num; /*num of tlb entry */ int cycle; /*current tlb cycle */ tlb_entry_t *entrys; } tlb_t; #define tlb_c_flag(tlb) \ ((tlb)->perms & 0x8) #define tlb_b_flag(tlb) \ ((tlb)->perms & 0x4) #define tlb_va_to_pa(tlb, va) \ (\ {\ ARMword mask = tlb_masks[tlb->mapping]; \ (tlb->phys_addr & mask) | (va & ~mask);\ }\ ) fault_t check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb, int read); fault_t translate (ARMul_State * state, ARMword virt_addr, tlb_t * tlb_t, tlb_entry_t ** tlb); int mmu_tlb_init (tlb_t * tlb_t, int num); void mmu_tlb_exit (tlb_t * tlb_t); void mmu_tlb_invalidate_all (ARMul_State * state, tlb_t * tlb_t); void mmu_tlb_invalidate_entry (ARMul_State * state, tlb_t * tlb_t, ARMword addr); tlb_entry_t *mmu_tlb_search (ARMul_State * state, tlb_t * tlb_t, ARMword virt_addr); #endif /*_MMU_TLB_H_*/ ��������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/arm926ejs_mmu.c������������������������������������������������0000644�0001750�0000144�00000052016�10555732132�020573� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* arm926ejs_mmu.c - ARM926EJS Memory Management Unit emulation. Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <assert.h> #include <string.h> #include "armdefs.h" #define ARM926EJS_MAIN_TLB() (&state->mmu.u.arm926ejs_mmu.main_tlb) #define ARM926EJS_I_CACHE() (&state->mmu.u.arm926ejs_mmu.i_cache) #define ARM926EJS_LOCKDOWN_TLB() (&state->mmu.u.arm926ejs_mmu.lockdown_tlb) #define ARM926EJS_D_CACHE() (&state->mmu.u.arm926ejs_mmu.d_cache) #define ARM926EJS_WB() (&state->mmu.u.arm926ejs_mmu.wb_t) typedef struct arm926ejs_mmu_desc_s { int main_tlb; int lockdown_tlb; cache_desc_t i_cache; cache_desc_t d_cache; wb_desc_t wb; } arm926ejs_mmu_desc_t; static arm926ejs_mmu_desc_t arm926ejs_mmu_desc = { /* (2 way *32) entry main TLB */ 64, /* 8 entry locked down TLB */ 8, /* 32 bytes per line * 4 way * 64 set * * 8K i cache * 4K d cache * */ {32, 4, 64, CACHE_WRITE_BACK}, {32, 4, 32, CACHE_WRITE_BACK}, {8, 8} //for byte size }; static fault_t arm926ejs_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype); static fault_t arm926ejs_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype); static fault_t update_cache (ARMul_State * state, ARMword va, ARMword data, ARMword datatype, cache_line_t * cache, cache_t * cache_t, ARMword real_va); int arm926ejs_mmu_init (ARMul_State * state) { arm926ejs_mmu_desc_t *desc; cache_desc_t *c_desc; state->mmu.control = 0x50078; state->mmu.translation_table_base = 0x0; state->mmu.domain_access_control = 0xDEADC0DE; state->mmu.fault_status = 0; state->mmu.fault_address = 0; state->mmu.process_id = 0; desc = &arm926ejs_mmu_desc; if (mmu_tlb_init (ARM926EJS_MAIN_TLB (), desc->main_tlb)) { err_msg ("main_tlb init %d\n", -1); goto main_tlb_init_error; } c_desc = &desc->i_cache; if (mmu_cache_init (ARM926EJS_I_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("i_cache init %d\n", -1); goto i_cache_init_error; } if (mmu_tlb_init (ARM926EJS_LOCKDOWN_TLB (), desc->lockdown_tlb)) { err_msg ("lockdown_tlb init %d\n", -1); goto lockdown_tlb_init_error; } c_desc = &desc->d_cache; if (mmu_cache_init (ARM926EJS_D_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("d_cache init %d\n", -1); goto d_cache_init_error; } if (mmu_wb_init (ARM926EJS_WB (), desc->wb.num, desc->wb.nb)) { err_msg ("wb init %d\n", -1); goto wb_init_error; } return 0; wb_init_error: mmu_cache_exit (ARM926EJS_D_CACHE ()); d_cache_init_error: mmu_tlb_exit (ARM926EJS_LOCKDOWN_TLB ()); lockdown_tlb_init_error: mmu_cache_exit (ARM926EJS_I_CACHE ()); i_cache_init_error: mmu_tlb_exit (ARM926EJS_MAIN_TLB ()); main_tlb_init_error: return -1; } void arm926ejs_mmu_exit (ARMul_State * state) { mmu_wb_exit (ARM926EJS_WB ()); mmu_cache_exit (ARM926EJS_D_CACHE ()); mmu_tlb_exit (ARM926EJS_LOCKDOWN_TLB ()); mmu_cache_exit (ARM926EJS_I_CACHE ()); mmu_tlb_exit (ARM926EJS_MAIN_TLB ()); }; static fault_t arm926ejs_mmu_load_instr (ARMul_State * state, ARMword va, ARMword * instr) { fault_t fault; tlb_entry_t *tlb; cache_line_t *cache; int c; //cache bit ARMword pa; //physical addr static int debug_count = 0; //used for debug d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); if (MMU_Enabled) { /*align check */ if ((va & (WORD_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else va &= ~(WORD_SIZE - 1); /*translate tlb */ fault = translate (state, va, ARM926EJS_MAIN_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, va, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } /*search cache no matter MMU enabled/disabled */ cache = mmu_cache_search (state, ARM926EJS_I_CACHE (), va); if (cache) { *instr = cache-> data[va_cache_index (va, ARM926EJS_I_CACHE ())]; return 0; } /*if MMU disabled or C flag is set alloc cache */ if (MMU_Disabled) { c = 1; pa = va; } else { c = tlb_c_flag (tlb); pa = tlb_va_to_pa (tlb, va); } if (c) { int index; debug_count++; cache = mmu_cache_alloc (state, ARM926EJS_I_CACHE (), va, pa); index = va_cache_index (va, ARM926EJS_I_CACHE ()); *instr = cache-> data[va_cache_index (va, ARM926EJS_I_CACHE ())]; } else *instr = mem_read_word (state, pa); return 0; }; static fault_t arm926ejs_mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = arm926ejs_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE); return fault; } static fault_t arm926ejs_mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = arm926ejs_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE); return fault; } static fault_t arm926ejs_mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data) { return arm926ejs_mmu_read (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t arm926ejs_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype) { fault_t fault; tlb_entry_t *tlb; cache_line_t *cache; ARMword pa, real_va, temp, offset; //printf("%s va = %x, val = %x\n", __FUNCTION__, va, *data); d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); real_va = va; /*if MMU disabled, memory_read */ if (MMU_Disabled) { //*data = mem_read_word(state, va); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, va); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, va); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, va); else { printf ("SKYEYE:1 arm926ejs_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } // else va &= ~(WORD_SIZE - 1); /*translate va to tlb */ fault = translate (state, va, ARM926EJS_MAIN_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access permission */ fault = check_access (state, va, tlb, 1); if (fault) return fault; /*search main cache */ cache = mmu_cache_search (state, ARM926EJS_D_CACHE (), va); if (cache) { *data = cache-> data[va_cache_index (va, ARM926EJS_D_CACHE ())]; goto datatrans; //return 0; } /*get phy_addr */ pa = tlb_va_to_pa (tlb, va); if ((pa >= 0xe0000000) && (pa < 0xe8000000)) { if (tlb_c_flag (tlb)) { //if (tlb_b_flag(tlb)){ // mmu_cache_soft_flush(state, ARM926EJS_D_CACHE(), pa); //} mmu_cache_soft_flush (state, ARM926EJS_D_CACHE (), pa); } return 0; } /*if Buffer, drain Write Buffer first */ if (tlb_b_flag (tlb)) mmu_wb_drain_all (state, ARM926EJS_WB ()); /*alloc cache or mem_read */ if (tlb_c_flag (tlb) && MMU_DCacheEnabled) { cache_t *cache_t; //if (tlb_b_flag(tlb)) cache_t = ARM926EJS_D_CACHE (); cache = mmu_cache_alloc (state, cache_t, va, pa); *data = cache->data[va_cache_index (va, cache_t)]; } else { //*data = mem_read_word(state, pa); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, pa | (real_va & 3)); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, pa | (real_va & 2)); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, pa); else { printf ("SKYEYE:2 arm926ejs_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } datatrans: if (datatype == ARM_HALFWORD_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ *data = (temp >> offset) & 0xffff; } else if (datatype == ARM_BYTE_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ *data = (temp >> offset & 0xffL); } end: // printf("va: %x, pa:%x data: %x\n", va, pa, *data); return 0; } static fault_t arm926ejs_mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data) { return arm926ejs_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE); } static fault_t arm926ejs_mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data) { return arm926ejs_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE); } static fault_t arm926ejs_mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data) { return arm926ejs_mmu_write (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t arm926ejs_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype) { tlb_entry_t *tlb; cache_line_t *cache; int b; ARMword pa, real_va; fault_t fault; //printf("%s va = %x, val = %x\n", __FUNCTION__, va, data); d_msg ("va = %x, val = %x\n", va, data); va = mmu_pid_va_map (va); real_va = va; /*search instruction cache */ cache = mmu_cache_search (state, ARM926EJS_I_CACHE (), va); if (cache) { update_cache (state, va, data, datatype, cache, ARM926EJS_I_CACHE (), real_va); } if (MMU_Disabled) { //mem_write_word(state, va, data); if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, va, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, va, data); else if (datatype == ARM_WORD_TYPE) mem_write_word (state, va, data); else { printf ("SKYEYE:1 arm926ejs_mmu_write error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ //if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } //else va &= ~(WORD_SIZE - 1); /*tlb translate */ fault = translate (state, va, ARM926EJS_MAIN_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*tlb check access */ fault = check_access (state, va, tlb, 0); if (fault) { d_msg ("check_access\n"); return fault; } /*search main cache */ cache = mmu_cache_search (state, ARM926EJS_D_CACHE (), va); if (cache) { update_cache (state, va, data, datatype, cache, ARM926EJS_D_CACHE (), real_va); } if (!cache) { b = tlb_b_flag (tlb); pa = tlb_va_to_pa (tlb, va); if (b) { if (MMU_WBEnabled) { if (datatype == ARM_WORD_TYPE) mmu_wb_write_bytes (state, ARM926EJS_WB (), pa, &data, 4); else if (datatype == ARM_HALFWORD_TYPE) mmu_wb_write_bytes (state, ARM926EJS_WB (), (pa | (real_va & 2)), &data, 2); else if (datatype == ARM_BYTE_TYPE) mmu_wb_write_bytes (state, ARM926EJS_WB (), (pa | (real_va & 3)), &data, 1); } else { if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } } else { mmu_wb_drain_all (state, ARM926EJS_WB ()); if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } } return 0; } static fault_t update_cache (ARMul_State * state, ARMword va, ARMword data, ARMword datatype, cache_line_t * cache, cache_t * cache_t, ARMword real_va) { ARMword temp, offset; ARMword index = va_cache_index (va, cache_t); //cache->data[index] = data; if (datatype == ARM_WORD_TYPE) cache->data[index] = data; else if (datatype == ARM_HALFWORD_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset); } else if (datatype == ARM_BYTE_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset); } if (index < (cache_t->width >> (WORD_SHT + 1))) cache->tag |= TAG_FIRST_HALF_DIRTY; else cache->tag |= TAG_LAST_HALF_DIRTY; return 0; } ARMword arm926ejs_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value) { mmu_regnum_t creg = BITS (16, 19) & 0xf; int OPC_2 = BITS (5, 7) & 0x7; ARMword data; //printf("mmu_mrc read - reg %d\n", creg); switch (creg) { case MMU_ID: if (OPC_2 == 0) { data = state->cpu->cpu_val; } else if (OPC_2 == 1) /* ARM926EJS Cache type: * Ctype S Dsize Isize * Size assoc M Len Size assoc M Len *NS9750: 000 1110 1 00 0011 010 0 10 00 0100 010 0 10 *see ARM926ejs TRM P2-8 * */ data = 0x1D0D2112; else if (OPC_2 == 2) { /* TCM status */ data = 0x0; } break; case MMU_CONTROL: /* * 6:3 should be 1. * 11:10 should be 0 * 18,16 should be 1 * 17 should be 0 * 31:19 should be 0 * */ data = (state->mmu.control | 0x50078) & 0x0005F3FF;; break; case MMU_TRANSLATION_TABLE_BASE: data = state->mmu.translation_table_base & 0xFFFFC000; break; case MMU_DOMAIN_ACCESS_CONTROL: data = state->mmu.domain_access_control; break; case MMU_FAULT_STATUS: /* OPC_2 = 0: data FSR value * */ if (OPC_2 == 0) data = state->mmu.fault_status & 0x0FF; break; case MMU_FAULT_ADDRESS: data = state->mmu.fault_address; break; case MMU_CACHE_OPS: /* TODO */ //arm926ejs_mmu_cache_ops(state, instr, value); break; case MMU_TLB_LOCKDOWN: /* FIXME:tlb lock down */ data = state->mmu.tlb_locked_down; break; case MMU_PID: data = state->mmu.process_id; default: printf ("mmu_mrc read UNKNOWN - reg %d\n", creg); data = 0; break; } // printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]); *value = data; return data; } /* ARM926EJS Cache Operation, P44 * */ void arm926ejs_mmu_cache_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); //printf("%s - CRm: %d, OPC_2: %d\n", __FUNCTION__, CRm, OPC_2); if (OPC_2 == 0 && CRm == 7) { mmu_cache_invalidate_all (state, ARM926EJS_I_CACHE ()); mmu_cache_invalidate_all (state, ARM926EJS_D_CACHE ()); return; } if (OPC_2 == 0 && CRm == 5) { mmu_cache_invalidate_all (state, ARM926EJS_I_CACHE ()); return; } /*Invalidate ICache single entry **/ if (OPC_2 == 1 && CRm == 5) { mmu_cache_invalidate (state, ARM926EJS_I_CACHE (), value); return; } /* Invalidate ICache single entry Set/way */ if (OPC_2 == 2 && CRm == 5) { mmu_cache_invalidate_by_index (state, ARM926EJS_I_CACHE (), value); return; } /* TODO: * Prefetch ICache line (using MVA) * */ if (OPC_2 == 1 && CRm == 13) { //mmu_cache_invalidate(state, ARM926EJS_I_CACHE(), value); return; } if (OPC_2 == 0 && CRm == 6) { mmu_cache_invalidate_all (state, ARM926EJS_D_CACHE ()); return; } /* Invalidate DCache single entry (using MVA) * */ if (OPC_2 == 1 && CRm == 6) { mmu_cache_invalidate (state, ARM926EJS_D_CACHE (), value); return; } /* Invalidate DCache single entry Set/way */ if (OPC_2 == 2 && CRm == 6) { mmu_cache_invalidate_by_index (state, ARM926EJS_D_CACHE (), value); return; } /* Clean DCache single entry (using MVA) * */ if (OPC_2 == 1 && CRm == 0xa) { mmu_cache_clean (state, ARM926EJS_D_CACHE (), value); return; } /* Clean and Invalidate DCache entry (using MVA) * */ if (OPC_2 == 1 && CRm == 14) { mmu_cache_clean (state, ARM926EJS_D_CACHE (), value); mmu_cache_invalidate (state, ARM926EJS_D_CACHE (), value); return; } /* Clean DCache single entry (Set Way) * */ if (OPC_2 == 2 && CRm == 0xa) { mmu_cache_clean_by_index (state, ARM926EJS_D_CACHE (), value); return; } /* Clean and Invalidate DCache entry (Set/Way) * */ if (OPC_2 == 2 && CRm == 14) { mmu_cache_clean_by_index (state, ARM926EJS_D_CACHE (), value); mmu_cache_invalidate_by_index (state, ARM926EJS_D_CACHE (), value); return; } /* Drain write buffer * */ if (OPC_2 == 4 && CRm == 0xa) { mmu_wb_drain_all (state, ARM926EJS_WB ()); return; } /* FIXME: how to do a waiting operation? * Wait for a interrupt * */ if (OPC_2 == 4 && CRm == 0) { return; } err_msg ("Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm); } static void arm926ejs_mmu_tlb_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); //printf("%s - CRm: %d, OPC_2: %d\n", __FUNCTION__, CRm, OPC_2); if (OPC_2 == 0 && (CRm == 0x7) || (CRm == 0x6) || (CRm == 0x5)) { mmu_tlb_invalidate_all (state, ARM926EJS_MAIN_TLB ()); //mmu_tlb_invalidate_all(state, ARM926EJS_LOCKDOWN_TLB()); return; } if (OPC_2 == 1 && (CRm == 0x5 || (CRm == 0x7) || (CRm == 0x6))) { mmu_tlb_invalidate_entry (state, ARM926EJS_MAIN_TLB (), value); return; } err_msg ("Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm); } static void arm926ejs_mmu_cache_lockdown (ARMul_State * state, ARMword instr, ARMword value) { int OPC_2 = BITS (5, 7) & 0x7; } static void arm926ejs_mmu_tlb_lockdown (ARMul_State * state, ARMword instr, ARMword value) { } static ARMword arm926ejs_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value) { mmu_regnum_t creg = BITS (16, 19) & 15; int OPC_2 = BITS (5, 7) & 0x7; //printf("mmu_mcr - reg %d\n", creg); switch (creg) { case MMU_CONTROL: // printf("mmu_mcr wrote CONTROL "); state->mmu.control = (value | 0x50078) & 0x0005F3FF; break; case MMU_TRANSLATION_TABLE_BASE: // printf("mmu_mcr wrote TTB "); state->mmu.translation_table_base = value & 0xFFFFC000; break; case MMU_DOMAIN_ACCESS_CONTROL: // printf("mmu_mcr wrote DACR "); state->mmu.domain_access_control = value; break; case MMU_FAULT_STATUS: if (OPC_2 == 0) state->mmu.fault_status = value & 0xFF; break; case MMU_FAULT_ADDRESS: state->mmu.fault_address = value; break; case MMU_CACHE_OPS: arm926ejs_mmu_cache_ops (state, instr, value); break; case MMU_TLB_OPS: arm926ejs_mmu_tlb_ops (state, instr, value); break; case MMU_CACHE_LOCKDOWN: /* * FIXME: cache lock down*/ break; case MMU_TLB_LOCKDOWN: /* FIXME:tlb lock down */ state->mmu.tlb_locked_down = value; break; case MMU_PID: /*0:24 should be zero. */ state->mmu.process_id = value & 0xfe000000; break; default: printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); break; } } //teawater add for arm2x86 2005.06.19------------------------------------------- static int arm926ejs_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr) { fault_t fault; tlb_entry_t *tlb; virt_addr = mmu_pid_va_map (virt_addr); if (MMU_Enabled) { /*align check */ if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else virt_addr &= ~(WORD_SIZE - 1); /*translate tlb */ fault = translate (state, virt_addr, ARM926EJS_MAIN_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, virt_addr, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } if (MMU_Disabled) { *phys_addr = virt_addr; } else { *phys_addr = tlb_va_to_pa (tlb, virt_addr); } return (0); } //AJ2D-------------------------------------------------------------------------- /*arm926ejs mmu_ops_t*/ mmu_ops_t arm926ejs_mmu_ops = { arm926ejs_mmu_init, arm926ejs_mmu_exit, arm926ejs_mmu_read_byte, arm926ejs_mmu_write_byte, arm926ejs_mmu_read_halfword, arm926ejs_mmu_write_halfword, arm926ejs_mmu_read_word, arm926ejs_mmu_write_word, arm926ejs_mmu_load_instr, arm926ejs_mmu_mcr, arm926ejs_mmu_mrc, //teawater add for arm2x86 2005.06.19------------------------------------------- arm926ejs_mmu_v2p_dbct, //AJ2D-------------------------------------------------------------------------- }; ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/xscale_copro.c�������������������������������������������������0000644�0001750�0000144�00000104233�10555732132�020653� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armmmu.c - Memory Management Unit emulation. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <assert.h> #include <string.h> #include "armdefs.h" #include "armemu.h" #include "pxa.h" //chy 2005-09-19 extern pxa270_io_t pxa270_io; //chy 2005-09-19 -----end typedef struct xscale_mmu_desc_s { int i_tlb; cache_desc_t i_cache; int d_tlb; cache_desc_t main_d_cache; cache_desc_t mini_d_cache; //int rb; xscale has no read buffer wb_desc_t wb; } xscale_mmu_desc_t; static xscale_mmu_desc_t pxa_mmu_desc = { 32, {32, 32, 32, CACHE_WRITE_BACK}, 32, {32, 32, 32, CACHE_WRITE_BACK}, {32, 2, 8, CACHE_WRITE_BACK}, {8, 16}, //for byte size, }; //chy 2005-09-19 for cp6 #define CR0_ICIP 0 #define CR1_ICMR 1 //chy 2005-09-19 ---end //----------- for cp14----------------- #define CCLKCFG 6 #define PWRMODE 7 typedef struct xscale_cp14_reg_s { unsigned cclkcfg; //reg6 unsigned pwrmode; //reg7 } xscale_cp14_reg_s; xscale_cp14_reg_s pxa_cp14_regs; //-------------------------------------- static fault_t xscale_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype); static fault_t xscale_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype); ARMword xscale_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value); ARMword xscale_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value); //chy 2005-09-19 for xscale pxa27x cp6 unsigned xscale_cp6_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { unsigned opcode_2 = BITS (5, 7); unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; //printf("SKYEYE: xscale_cp6_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,state->Reg[15], instr); switch (reg) { case CR0_ICIP: // cp 6 reg 0 //printf("cp6_mrc cr0 ICIP \n"); *data = (pxa270_io.icmr & pxa270_io.icpr) & ~pxa270_io.iclr; break; case CR1_ICMR: // cp 6 reg 1 //printf("cp6_mrc cr1 ICMR\n"); *data = pxa270_io.icmr; break; default: *data = 0; printf ("SKYEYE:cp6_mrc unknown cp6 regs!!!!!!\n"); printf ("SKYEYE: xscale_cp6_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n", opcode_2, CRm, reg, state->Reg[15], instr); break; } return 0; } //chy 2005-09-19 end //xscale cp13 ---------------------------------------------------- unsigned xscale_cp13_init (ARMul_State * state) { //printf("SKYEYE: xscale_cp13_init: begin\n"); return 0; } unsigned xscale_cp13_exit (ARMul_State * state) { //printf("SKYEYE: xscale_cp13_exit: begin\n"); return 0; } unsigned xscale_cp13_ldc (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { printf ("SKYEYE: xscale_cp13_ldc: ERROR isn't existed,"); SKYEYE_OUTREGS (stderr); fprintf (stderr, "\n"); skyeye_exit (-1); } unsigned xscale_cp13_stc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { printf ("SKYEYE: xscale_cp13_stc: ERROR isn't existed,"); SKYEYE_OUTREGS (stderr); fprintf (stderr, "\n"); skyeye_exit (-1); } unsigned xscale_cp13_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { printf ("SKYEYE: xscale_cp13_mrc: ERROR isn't existed,"); SKYEYE_OUTREGS (stderr); fprintf (stderr, "\n"); skyeye_exit (-1); } unsigned xscale_cp13_mcr (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { printf ("SKYEYE: xscale_cp13_mcr: ERROR isn't existed,"); SKYEYE_OUTREGS (stderr); fprintf (stderr, "\n"); skyeye_exit (-1); } unsigned xscale_cp13_cdp (ARMul_State * state, unsigned type, ARMword instr) { printf ("SKYEYE: xscale_cp13_cdp: ERROR isn't existed,"); SKYEYE_OUTREGS (stderr); fprintf (stderr, "\n"); skyeye_exit (-1); } unsigned xscale_cp13_read_reg (ARMul_State * state, unsigned reg, ARMword * data) { printf ("SKYEYE: xscale_cp13_read_reg: ERROR isn't existed,"); SKYEYE_OUTREGS (stderr); fprintf (stderr, "\n"); return 0; //exit(-1); } unsigned xscale_cp13_write_reg (ARMul_State * state, unsigned reg, ARMword data) { printf ("SKYEYE: xscale_cp13_write_reg: ERROR isn't existed,"); SKYEYE_OUTREGS (stderr); fprintf (stderr, "\n"); skyeye_exit (-1); } //------------------------------------------------------------------ //xscale cp14 ---------------------------------------------------- unsigned xscale_cp14_init (ARMul_State * state) { //printf("SKYEYE: xscale_cp14_init: begin\n"); pxa_cp14_regs.cclkcfg = 0; pxa_cp14_regs.pwrmode = 0; return 0; } unsigned xscale_cp14_exit (ARMul_State * state) { //printf("SKYEYE: xscale_cp14_exit: begin\n"); return 0; } unsigned xscale_cp14_ldc (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { printf ("SKYEYE: xscale_cp14_ldc: ERROR isn't existed, reg15 0x%x\n", state->Reg[15]); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } unsigned xscale_cp14_stc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { printf ("SKYEYE: xscale_cp14_stc: ERROR isn't existed, reg15 0x%x\n", state->Reg[15]); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } unsigned xscale_cp14_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { unsigned opcode_2 = BITS (5, 7); unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; //printf("SKYEYE: xscale_cp14_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,\ state->Reg[15], instr); switch (reg) { case CCLKCFG: // cp 14 reg 6 //printf("cp14_mrc cclkcfg \n"); *data = pxa_cp14_regs.cclkcfg; break; case PWRMODE: // cp 14 reg 7 //printf("cp14_mrc pwrmode \n"); *data = pxa_cp14_regs.pwrmode; break; default: *data = 0; printf ("SKYEYE:cp14_mrc unknown cp14 regs!!!!!!\n"); break; } return 0; } unsigned xscale_cp14_mcr (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { unsigned opcode_2 = BITS (5, 7); unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; //printf("SKYEYE: xscale_cp14_mcr:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,\ state->Reg[15], instr); switch (reg) { case CCLKCFG: // cp 14 reg 6 //printf("cp14_mcr cclkcfg \n"); pxa_cp14_regs.cclkcfg = data & 0xf; break; case PWRMODE: // cp 14 reg 7 //printf("cp14_mcr pwrmode \n"); pxa_cp14_regs.pwrmode = data & 0x3; break; default:printf ("SKYEYE: cp14_mcr unknown cp14 regs!!!!!!\n"); break; } return 0; } unsigned xscale_cp14_cdp (ARMul_State * state, unsigned type, ARMword instr) { printf ("SKYEYE: xscale_cp14_cdp: ERROR isn't existed, reg15 0x%x\n", state->Reg[15]); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } unsigned xscale_cp14_read_reg (ARMul_State * state, unsigned reg, ARMword * data) { printf ("SKYEYE: xscale_cp14_read_reg: ERROR isn't existed, reg15 0x%x\n", state->Reg[15]); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } unsigned xscale_cp14_write_reg (ARMul_State * state, unsigned reg, ARMword data) { printf ("SKYEYE: xscale_cp14_write_reg: ERROR isn't existed, reg15 0x%x\n", state->Reg[15]); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } //------------------------------------------------------------------ //cp15 ------------------------------------- unsigned xscale_cp15_ldc (ARMul_State * state, unsigned type, ARMword instr, ARMword data) { printf ("SKYEYE: xscale_cp15_ldc: ERROR isn't existed\n"); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } unsigned xscale_cp15_stc (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) { printf ("SKYEYE: xscale_cp15_stc: ERROR isn't existed\n"); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } unsigned xscale_cp15_cdp (ARMul_State * state, unsigned type, ARMword instr) { printf ("SKYEYE: xscale_cp15_cdp: ERROR isn't existed\n"); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } unsigned xscale_cp15_read_reg (ARMul_State * state, unsigned reg, ARMword * data) { //chy 2003-09-03: for xsacle_cp15_cp_access_allowed if (reg == 15) { *data = state->mmu.copro_access; //printf("SKYEYE: xscale_cp15_read_reg: reg 0x%x,data %x\n",reg,*data); return 0; } printf ("SKYEYE: xscale_cp15_read_reg: reg 0x%x, ERROR isn't existed\n", reg); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } //chy 2003-09-03 used by macro CP_ACCESS_ALLOWED in armemu.h unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg, unsigned cpnum) { unsigned data; xscale_cp15_read_reg (state, reg, &data); //printf("SKYEYE: cp15_cp_access_allowed data %x, cpnum %x, result %x\n", data, cpnum, (data & 1<<cpnum)); if (data & 1 << cpnum) return 1; else return 0; } unsigned xscale_cp15_write_reg (ARMul_State * state, unsigned reg, ARMword value) { switch (reg) { case MMU_FAULT_STATUS: //printf("SKYEYE:cp15_write_reg wrote FS val 0x%x \n",value); state->mmu.fault_status = value & 0x6FF; break; case MMU_FAULT_ADDRESS: //printf("SKYEYE:cp15_write_reg wrote FA val 0x%x \n",value); state->mmu.fault_address = value; break; default: printf ("SKYEYE: xscale_cp15_write_reg: reg 0x%x R15 %x ERROR isn't existed\n", reg, state->Reg[15]); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); } return 0; } int xscale_cp15_init (ARMul_State * state) { xscale_mmu_desc_t *desc; cache_desc_t *c_desc; state->mmu.control = 0; state->mmu.translation_table_base = 0xDEADC0DE; state->mmu.domain_access_control = 0xDEADC0DE; state->mmu.fault_status = 0; state->mmu.fault_address = 0; state->mmu.process_id = 0; state->mmu.cache_type = 0xB1AA1AA; //0000 1011 0001 1010 1010 0001 1010 1010 state->mmu.aux_control = 0; desc = &pxa_mmu_desc; if (mmu_tlb_init (I_TLB (), desc->i_tlb)) { err_msg ("i_tlb init %d\n", -1); goto i_tlb_init_error; } c_desc = &desc->i_cache; if (mmu_cache_init (I_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("i_cache init %d\n", -1); goto i_cache_init_error; } if (mmu_tlb_init (D_TLB (), desc->d_tlb)) { err_msg ("d_tlb init %d\n", -1); goto d_tlb_init_error; } c_desc = &desc->main_d_cache; if (mmu_cache_init (MAIN_D_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("main_d_cache init %d\n", -1); goto main_d_cache_init_error; } c_desc = &desc->mini_d_cache; if (mmu_cache_init (MINI_D_CACHE (), c_desc->width, c_desc->way, c_desc->set, c_desc->w_mode)) { err_msg ("mini_d_cache init %d\n", -1); goto mini_d_cache_init_error; } if (mmu_wb_init (WB (), desc->wb.num, desc->wb.nb)) { err_msg ("wb init %d\n", -1); goto wb_init_error; } #if 0 if (mmu_rb_init (RB (), desc->rb)) { err_msg ("rb init %d\n", -1); goto rb_init_error; } #endif return 0; #if 0 rb_init_error: mmu_wb_exit (WB ()); #endif wb_init_error: mmu_cache_exit (MINI_D_CACHE ()); mini_d_cache_init_error: mmu_cache_exit (MAIN_D_CACHE ()); main_d_cache_init_error: mmu_tlb_exit (D_TLB ()); d_tlb_init_error: mmu_cache_exit (I_CACHE ()); i_cache_init_error: mmu_tlb_exit (I_TLB ()); i_tlb_init_error: return -1; } void xscale_cp15_exit (ARMul_State * state) { //mmu_rb_exit(RB()); mmu_wb_exit (WB ()); mmu_cache_exit (MINI_D_CACHE ()); mmu_cache_exit (MAIN_D_CACHE ()); mmu_tlb_exit (D_TLB ()); mmu_cache_exit (I_CACHE ()); mmu_tlb_exit (I_TLB ()); }; static fault_t xscale_mmu_load_instr (ARMul_State * state, ARMword va, ARMword * instr) { fault_t fault; tlb_entry_t *tlb; cache_line_t *cache; int c; //cache bit ARMword pa; //physical addr static int debug_count = 0; //used for debug d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); if (MMU_Enabled) { /*align check */ if ((va & (INSN_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else va &= ~(INSN_SIZE - 1); /*translate tlb */ fault = translate (state, va, I_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, va, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } //chy 2003-09-02 for test, don't use cache ????? #if 0 /*search cache no matter MMU enabled/disabled */ cache = mmu_cache_search (state, I_CACHE (), va); if (cache) { *instr = cache->data[va_cache_index (va, I_CACHE ())]; return 0; } #endif /*if MMU disabled or C flag is set alloc cache */ if (MMU_Disabled) { c = 1; pa = va; } else { c = tlb_c_flag (tlb); pa = tlb_va_to_pa (tlb, va); } //chy 2003-09-03 only read mem, don't use cache now,will change later ???? *instr = mem_read_word (state, pa); #if 0 //----------------------------------------------------------- //chy 2003-09-02 for test???? if (pa >= 0xa01c8000 && pa <= 0xa01c8020) { printf ("SKYEYE:load_instr: pa %x, va %x,instr %x, R15 %x\n", pa, va, *instr, state->Reg[15]); } //---------------------------------------------------------------------- #endif return 0; if (c) { int index; debug_count++; cache = mmu_cache_alloc (state, I_CACHE (), va, pa); index = va_cache_index (va, I_CACHE ()); *instr = cache->data[va_cache_index (va, I_CACHE ())]; } else *instr = mem_read_word (state, pa); return 0; }; static fault_t xscale_mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = xscale_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE); return fault; } static fault_t xscale_mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data) { //ARMword temp,offset; fault_t fault; fault = xscale_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE); return fault; } static fault_t xscale_mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data) { return xscale_mmu_read (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t xscale_mmu_read (ARMul_State * state, ARMword va, ARMword * data, ARMword datatype) { fault_t fault; // rb_entry_t *rb; tlb_entry_t *tlb; cache_line_t *cache; ARMword pa, real_va, temp, offset; //chy 2003-09-02 for test ???? static unsigned chyst1 = 0, chyst2 = 0; d_msg ("va = %x\n", va); va = mmu_pid_va_map (va); real_va = va; /*if MMU disabled, memory_read */ if (MMU_Disabled) { //*data = mem_read_word(state, va); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, va); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, va); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, va); else { printf ("SKYEYE:1 xscale_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } // else va &= ~(WORD_SIZE - 1); /*translate va to tlb */ fault = translate (state, va, D_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access permission */ fault = check_access (state, va, tlb, 1); if (fault) return fault; #if 0 //------------------------------------------------ //chy 2003-09-02 for test only ,should commit ???? if (datatype == ARM_WORD_TYPE) { if (real_va >= 0xffff0000 && real_va <= 0xffff0020) { pa = tlb_va_to_pa (tlb, va); *data = mem_read_word (state, pa); chyst1++; printf ("**SKYEYE:mmu_read word %d: pa %x, va %x, data %x, R15 %x\n", chyst1, pa, real_va, *data, state->Reg[15]); /* cache==mmu_cache_search(state,MAIN_D_CACHE(),va); if(cache){ *data = cache->data[va_cache_index(va, MAIN_D_CACHE())]; printf("cached data %x\n",*data); }else printf("no cached data\n"); */ } } //------------------------------------------------- #endif #if 0 /*search in read buffer */ rb = mmu_rb_search (RB (), va); if (rb) { if (rb->fault) return rb->fault; *data = rb->data[(va & (rb_masks[rb->type] - 1)) >> WORD_SHT]; goto datatrans; //return 0; }; #endif /*2004-07-19 chy: add support of xscale MMU CacheDisabled option */ if (MMU_CacheDisabled) { //if(1){ can be used to test cache error /*get phy_addr */ pa = tlb_va_to_pa (tlb, real_va); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, pa); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, pa); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, pa); else { printf ("SKYEYE:MMU_CacheDisabled xscale_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*search main cache */ cache = mmu_cache_search (state, MAIN_D_CACHE (), va); if (cache) { *data = cache->data[va_cache_index (va, MAIN_D_CACHE ())]; #if 0 //------------------------------------------------------------------------ //chy 2003-09-02 for test only ,should commit ???? if (real_va >= 0xffff0000 && real_va <= 0xffff0020) { pa = tlb_va_to_pa (tlb, va); chyst2++; printf ("**SKYEYE:mmu_read wordk:cache %d: pa %x, va %x, data %x, R15 %x\n", chyst2, pa, real_va, *data, state->Reg[15]); } //------------------------------------------------------------------- #endif goto datatrans; //return 0; } //chy 2003-08-24, now maybe we don't need minidcache ???? #if 0 /*search mini cache */ cache = mmu_cache_search (state, MINI_D_CACHE (), va); if (cache) { *data = cache->data[va_cache_index (va, MINI_D_CACHE ())]; goto datatrans; //return 0; } #endif /*get phy_addr */ pa = tlb_va_to_pa (tlb, va); //chy 2003-08-24 , in xscale it means what ????? #if 0 if ((pa >= 0xe0000000) && (pa < 0xe8000000)) { if (tlb_c_flag (tlb)) { if (tlb_b_flag (tlb)) { mmu_cache_soft_flush (state, MAIN_D_CACHE (), pa); } else { mmu_cache_soft_flush (state, MINI_D_CACHE (), pa); } } return 0; } #endif //chy 2003-08-24, check phy addr //ywc 2004-11-30, inactive this check because of using 0xc0000000 as the framebuffer start address /* if(pa >= 0xb0000000){ printf("SKYEYE:xscale_mmu_read: phy address 0x%x error,reg[15] 0x%x\n",pa,state->Reg[15]); return 0; } */ //chy 2003-08-24, now maybe we don't need wb ???? #if 0 /*if Buffer, drain Write Buffer first */ if (tlb_b_flag (tlb)) mmu_wb_drain_all (state, WB ()); #endif /*alloc cache or mem_read */ if (tlb_c_flag (tlb) && MMU_DCacheEnabled) { cache_t *cache_t; if (tlb_b_flag (tlb)) cache_t = MAIN_D_CACHE (); else cache_t = MINI_D_CACHE (); cache = mmu_cache_alloc (state, cache_t, va, pa); *data = cache->data[va_cache_index (va, cache_t)]; } else { //*data = mem_read_word(state, pa); if (datatype == ARM_BYTE_TYPE) *data = mem_read_byte (state, pa | (real_va & 3)); else if (datatype == ARM_HALFWORD_TYPE) *data = mem_read_halfword (state, pa | (real_va & 2)); else if (datatype == ARM_WORD_TYPE) *data = mem_read_word (state, pa); else { printf ("SKYEYE:2 xscale_mmu_read error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } datatrans: if (datatype == ARM_HALFWORD_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ *data = (temp >> offset) & 0xffff; } else if (datatype == ARM_BYTE_TYPE) { temp = *data; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ *data = (temp >> offset & 0xffL); } end: return 0; } static fault_t xscale_mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data) { return xscale_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE); } static fault_t xscale_mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data) { return xscale_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE); } static fault_t xscale_mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data) { return xscale_mmu_write (state, virt_addr, data, ARM_WORD_TYPE); } static fault_t xscale_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype) { tlb_entry_t *tlb; cache_line_t *cache; cache_t *cache_t; int b; ARMword pa, real_va, temp, offset; fault_t fault; ARMword index; //chy 2003-09-02 for test ???? // static unsigned chyst1=0,chyst2=0; d_msg ("va = %x, val = %x\n", va, data); va = mmu_pid_va_map (va); real_va = va; if (MMU_Disabled) { //mem_write_word(state, va, data); if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, va, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, va, data); else if (datatype == ARM_WORD_TYPE) mem_write_word (state, va, data); else { printf ("SKYEYE:1 xscale_mmu_write error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*align check */ if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { d_msg ("align\n"); return ALIGNMENT_FAULT; } //else va &= ~(WORD_SIZE - 1); /*tlb translate */ fault = translate (state, va, D_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*tlb check access */ fault = check_access (state, va, tlb, 0); if (fault) { d_msg ("check_access\n"); return fault; } /*2004-07-19 chy: add support for xscale MMU_CacheDisabled */ if (MMU_CacheDisabled) { //if(1){ can be used to test the cache error /*get phy_addr */ pa = tlb_va_to_pa (tlb, real_va); if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, pa, data); else if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else { printf ("SKYEYE:MMU_CacheDisabled xscale_mmu_write error: unknown data type %d\n", datatype); skyeye_exit (-1); } return 0; } /*search main cache */ b = tlb_b_flag (tlb); pa = tlb_va_to_pa (tlb, va); cache = mmu_cache_search (state, MAIN_D_CACHE (), va); if (cache) { cache_t = MAIN_D_CACHE (); goto has_cache; } //chy 2003-08-24, now maybe we don't need minidcache ???? #if 0 /*search mini cache */ cache = mmu_cache_search (state, MINI_D_CACHE (), va); if (cache) { cache_t = MINI_D_CACHE (); goto has_cache; } #endif b = tlb_b_flag (tlb); pa = tlb_va_to_pa (tlb, va); //chy 2003-08-24, check phy addr 0xa0000000, size 0x04000000 //ywc 2004-11-30, inactive this check because of using 0xc0000000 as the framebuffer start address /* if(pa >= 0xb0000000){ printf("SKYEYE:xscale_mmu_write phy address 0x%x error,reg[15] 0x%x\n",pa,state->Reg[15]); return 0; } */ //chy 2003-08-24, now maybe we don't need WB ???? #if 0 if (b) { if (MMU_WBEnabled) { if (datatype == ARM_WORD_TYPE) mmu_wb_write_bytes (state, WB (), pa, &data, 4); else if (datatype == ARM_HALFWORD_TYPE) mmu_wb_write_bytes (state, WB (), (pa | (real_va & 2)), &data, 2); else if (datatype == ARM_BYTE_TYPE) mmu_wb_write_bytes (state, WB (), (pa | (real_va & 3)), &data, 1); } else { if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } } else { mmu_wb_drain_all (state, WB ()); if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } #endif //chy 2003-08-24, just write phy addr if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); #if 0 //------------------------------------------------------------- //chy 2003-09-02 for test ???? if (datatype == ARM_WORD_TYPE) { if (real_va >= 0xffff0000 && real_va <= 0xffff0020) { printf ("**SKYEYE:mmu_write word: pa %x, va %x, data %x, R15 %x \n", pa, real_va, data, state->Reg[15]); } } //-------------------------------------------------------------- #endif return 0; has_cache: index = va_cache_index (va, cache_t); //cache->data[index] = data; if (datatype == ARM_WORD_TYPE) cache->data[index] = data; else if (datatype == ARM_HALFWORD_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset); } else if (datatype == ARM_BYTE_TYPE) { temp = cache->data[index]; offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */ cache->data[index] = (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset); } if (index < (cache_t->width >> (WORD_SHT + 1))) cache->tag |= TAG_FIRST_HALF_DIRTY; else cache->tag |= TAG_LAST_HALF_DIRTY; //------------------------------------------------------------- //chy 2003-09-03 be sure the changed value will be in memory as soon as possible, so I cache can get the newest value #if 0 { if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); } #endif #if 0 //chy 2003-09-02 for test ???? if (datatype == ARM_WORD_TYPE) { if (real_va >= 0xffff0000 && real_va <= 0xffff0020) { printf ("**SKYEYE:mmu_write word:cache: pa %x, va %x, data %x, R15 %x\n", pa, real_va, data, state->Reg[15]); } } //------------------------------------------------------------- #endif if (datatype == ARM_WORD_TYPE) mem_write_word (state, pa, data); else if (datatype == ARM_HALFWORD_TYPE) mem_write_halfword (state, (pa | (real_va & 2)), data); else if (datatype == ARM_BYTE_TYPE) mem_write_byte (state, (pa | (real_va & 3)), data); return 0; } ARMword xscale_cp15_mrc (ARMul_State * state, unsigned type, ARMword instr, ARMword * value) { return xscale_mmu_mrc (state, instr, value); } ARMword xscale_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value) { ARMword data; unsigned opcode_2 = BITS (5, 7); unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; mmu_regnum_t creg = reg; /* printf("SKYEYE: xscale_cp15_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,\ state->Reg[15], instr); */ switch (creg) { case MMU_ID: //XSCALE_CP15 //printf("mmu_mrc read ID \n"); data = (opcode_2 ? state->mmu.cache_type : state->cpu-> cpu_val); break; case MMU_CONTROL: //XSCALE_CP15_AUX_CONTROL //printf("mmu_mrc read CONTROL \n"); data = (opcode_2 ? state->mmu.aux_control : state->mmu. control); break; case MMU_TRANSLATION_TABLE_BASE: //printf("mmu_mrc read TTB \n"); data = state->mmu.translation_table_base; break; case MMU_DOMAIN_ACCESS_CONTROL: //printf("mmu_mrc read DACR \n"); data = state->mmu.domain_access_control; break; case MMU_FAULT_STATUS: //printf("mmu_mrc read FSR \n"); data = state->mmu.fault_status; break; case MMU_FAULT_ADDRESS: //printf("mmu_mrc read FAR \n"); data = state->mmu.fault_address; break; case MMU_PID: //printf("mmu_mrc read PID \n"); data = state->mmu.process_id; case XSCALE_CP15_COPRO_ACCESS: //printf("xscale cp15 read coprocessor access\n"); data = state->mmu.copro_access; break; default: data = 0; printf ("SKYEYE: xscale_cp15_mrc read UNKNOWN - reg %d, pc 0x%x\n", creg, state->Reg[15]); skyeye_exit (-1); break; } *value = data; //printf("SKYEYE: xscale_cp15_mrc:end value 0x%x\n",data); return ARMul_DONE; } void xscale_cp15_cache_ops (ARMul_State * state, ARMword instr, ARMword value) { //chy: 2003-08-24 now, the BTB isn't simualted ....???? unsigned CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); //err_msg("SKYEYE: xscale cp15_cache_ops:OPC_2 = 0x%x CRm = 0x%x, Reg15 0x%x\n", OPC_2, CRm,state->Reg[15]); if (OPC_2 == 0 && CRm == 7) { mmu_cache_invalidate_all (state, I_CACHE ()); mmu_cache_invalidate_all (state, MAIN_D_CACHE ()); return; } if (OPC_2 == 0 && CRm == 5) { mmu_cache_invalidate_all (state, I_CACHE ()); return; } if (OPC_2 == 1 && CRm == 5) { mmu_cache_invalidate (state, I_CACHE (), value); return; } if (OPC_2 == 0 && CRm == 6) { mmu_cache_invalidate_all (state, MAIN_D_CACHE ()); return; } if (OPC_2 == 1 && CRm == 6) { mmu_cache_invalidate (state, MAIN_D_CACHE (), value); return; } if (OPC_2 == 1 && CRm == 0xa) { mmu_cache_clean (state, MAIN_D_CACHE (), value); return; } if (OPC_2 == 4 && CRm == 0xa) { mmu_wb_drain_all (state, WB ()); return; } if (OPC_2 == 6 && CRm == 5) { //chy 2004-07-19 shoud fix in the future????!!!! //printf("SKYEYE: xscale_cp15_cache_ops:invalidate BTB CANT!!!!!!!!!!\n"); //exit(-1); return; } if (OPC_2 == 5 && CRm == 2) { //printf("SKYEYE: cp15_c_o: A L in D C, value %x, reg15 %x\n",value, state->Reg[15]); //exit(-1); //chy 2003-09-01 for test mmu_cache_invalidate_all (state, MAIN_D_CACHE ()); return; } err_msg ("SKYEYE: xscale cp15_cache_ops:Unknown OPC_2 = 0x%x CRm = 0x%x, Reg15 0x%x\n", OPC_2, CRm, state->Reg[15]); skyeye_exit (-1); } static void xscale_cp15_tlb_ops (ARMul_State * state, ARMword instr, ARMword value) { int CRm, OPC_2; CRm = BITS (0, 3); OPC_2 = BITS (5, 7); //err_msg("SKYEYE:xscale_cp15_tlb_ops:OPC_2 = 0x%x CRm = 0x%x,Reg[15] 0x%x\n", OPC_2, CRm,state->Reg[15]); if (OPC_2 == 0 && CRm == 0x7) { mmu_tlb_invalidate_all (state, I_TLB ()); mmu_tlb_invalidate_all (state, D_TLB ()); return; } if (OPC_2 == 0 && CRm == 0x5) { mmu_tlb_invalidate_all (state, I_TLB ()); return; } if (OPC_2 == 1 && CRm == 0x5) { mmu_tlb_invalidate_entry (state, I_TLB (), value); return; } if (OPC_2 == 0 && CRm == 0x6) { mmu_tlb_invalidate_all (state, D_TLB ()); return; } if (OPC_2 == 1 && CRm == 0x6) { mmu_tlb_invalidate_entry (state, D_TLB (), value); return; } err_msg ("SKYEYE:xscale_cp15_tlb_ops:Unknow OPC_2 = 0x%x CRm = 0x%x,Reg[15] 0x%x\n", OPC_2, CRm, state->Reg[15]); skyeye_exit (-1); } ARMword xscale_cp15_mcr (ARMul_State * state, unsigned type, ARMword instr, ARMword value) { return xscale_mmu_mcr (state, instr, value); } ARMword xscale_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value) { ARMword data; unsigned opcode_2 = BITS (5, 7); unsigned CRm = BITS (0, 3); unsigned reg = BITS (16, 19); unsigned result; mmu_regnum_t creg = reg; //printf("SKYEYE: xscale_cp15_mcr: opcode_2 0x%x, CRm 0x%x, reg ox%x, value 0x%x, reg[15] 0x%x, instr 0x%x\n",opcode_2,CRm,reg, value, state->Reg[15], instr); switch (creg) { case MMU_CONTROL: //printf("mmu_mcr wrote CONTROL val 0x%x \n",value); state->mmu.control = (opcode_2 ? (value & 0x33) : (value & 0x3FFF)); break; case MMU_TRANSLATION_TABLE_BASE: //printf("mmu_mcr wrote TTB val 0x%x \n",value); state->mmu.translation_table_base = value & 0xFFFFC000; break; case MMU_DOMAIN_ACCESS_CONTROL: //printf("mmu_mcr wrote DACR val 0x%x \n",value); state->mmu.domain_access_control = value; break; case MMU_FAULT_STATUS: //printf("mmu_mcr wrote FS val 0x%x \n",value); state->mmu.fault_status = value & 0x6FF; break; case MMU_FAULT_ADDRESS: //printf("mmu_mcr wrote FA val 0x%x \n",value); state->mmu.fault_address = value; break; case MMU_CACHE_OPS: // printf("mmu_mcr wrote CO val 0x%x \n",value); xscale_cp15_cache_ops (state, instr, value); break; case MMU_TLB_OPS: //printf("mmu_mcr wrote TO val 0x%x \n",value); xscale_cp15_tlb_ops (state, instr, value); break; case MMU_PID: //printf("mmu_mcr wrote PID val 0x%x \n",value); state->mmu.process_id = value & 0xfe000000; break; case XSCALE_CP15_COPRO_ACCESS: //printf("xscale cp15 write coprocessor access val 0x %x\n",value); state->mmu.copro_access = value & 0x3ff; break; default: printf ("SKYEYE: xscale_cp15_mcr wrote UNKNOWN - reg %d, reg15 0x%x\n", creg, state->Reg[15]); break; } //printf("SKYEYE: xscale_cp15_mcr wrote val 0x%x\n", value); return 0; } //teawater add for arm2x86 2005.06.24------------------------------------------- static int xscale_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr) { fault_t fault; tlb_entry_t *tlb; virt_addr = mmu_pid_va_map (virt_addr); if (MMU_Enabled) { /*align check */ if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) { d_msg ("align\n"); return ALIGNMENT_FAULT; } else virt_addr &= ~(WORD_SIZE - 1); /*translate tlb */ fault = translate (state, virt_addr, I_TLB (), &tlb); if (fault) { d_msg ("translate\n"); return fault; } /*check access */ fault = check_access (state, virt_addr, tlb, 1); if (fault) { d_msg ("check_fault\n"); return fault; } } if (MMU_Disabled) { *phys_addr = virt_addr; } else { *phys_addr = tlb_va_to_pa (tlb, virt_addr); } return (0); } //AJ2D-------------------------------------------------------------------------- /*xscale mmu_ops_t*/ mmu_ops_t xscale_mmu_ops = { xscale_cp15_init, xscale_cp15_exit, xscale_mmu_read_byte, xscale_mmu_write_byte, xscale_mmu_read_halfword, xscale_mmu_write_halfword, xscale_mmu_read_word, xscale_mmu_write_word, xscale_mmu_load_instr, xscale_mmu_mcr, xscale_mmu_mrc, //teawater add for arm2x86 2005.06.24------------------------------------------- xscale_mmu_v2p_dbct, //AJ2D-------------------------------------------------------------------------- }; ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/mmu/cache.h��������������������������������������������������������0000644�0001750�0000144�00000007631�10541455476�017256� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _MMU_CACHE_H_ #define _MMU_CACHE_H_ typedef struct cache_line_t { ARMword tag; /* cache line align address | bit2: last half dirty bit1: first half dirty bit0: cache valid flag */ ARMword pa; /*physical address */ ARMword *data; /*array of cached data */ } cache_line_t; #define TAG_VALID_FLAG 0x00000001 #define TAG_FIRST_HALF_DIRTY 0x00000002 #define TAG_LAST_HALF_DIRTY 0x00000004 /*cache set association*/ typedef struct cache_set_s { cache_line_t *lines; int cycle; } cache_set_t; enum { CACHE_WRITE_BACK, CACHE_WRITE_THROUGH, }; typedef struct cache_s { int width; /*bytes in a line */ int way; /*way of set asscociate */ int set; /*num of set */ int w_mode; /*write back or write through */ //int a_mode; /*alloc mode: random or round-bin*/ cache_set_t *sets; /**/} cache_t; typedef struct cache_desc_s { int width; int way; int set; int w_mode; // int a_mode; } cache_desc_t; /*virtual address to cache set index*/ #define va_cache_set(va, cache_t) \ (((va) / (cache_t)->width) & ((cache_t)->set - 1)) /*virtual address to cahce line aligned*/ #define va_cache_align(va, cache_t) \ ((va) & ~((cache_t)->width - 1)) /*virtaul address to cache line word index*/ #define va_cache_index(va, cache_t) \ (((va) & ((cache_t)->width - 1)) >> WORD_SHT) /*see Page 558 in arm manual*/ /*set/index format value to cache set value*/ #define index_cache_set(index, cache_t) \ (((index) / (cache_t)->width) & ((cache_t)->set - 1)) /*************************cache********************/ /* mmu cache init * * @cache_t :cache_t to init * @width :cache line width in byte * @way :way of each cache set * @set :cache set num * @w_mode :cache w_mode * * $ -1: error * 0: sucess */ int mmu_cache_init (cache_t * cache_t, int width, int way, int set, int w_mode); /* free a cache_t's inner data, the ptr self is not freed, * when needed do like below: * mmu_cache_exit(cache); * free(cache_t); * * @cache_t : the cache_t to free */ void mmu_cache_exit (cache_t * cache_t); /* mmu cache search * * @state :ARMul_State * @cache_t :cache_t to search * @va :virtual address * * $ NULL: no cache match * cache :cache matched * */ cache_line_t *mmu_cache_search (ARMul_State * state, cache_t * cache_t, ARMword va); /* mmu cache search by set/index * * @state :ARMul_State * @cache_t :cache_t to search * @index :set/index value. * * $ NULL: no cache match * cache :cache matched * */ cache_line_t *mmu_cache_search_by_index (ARMul_State * state, cache_t * cache_t, ARMword index); /* mmu cache alloc * * @state :ARMul_State * @cache_t :cache_t to alloc from * @va :virtual address that require cache alloc, need not cache aligned * @pa :physical address of va * * $ cache_alloced, always alloc OK */ cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_t * cache_t, ARMword va, ARMword pa); /* mmu_cache_write_back write cache data to memory * * @state: * @cache_t :cache_t of the cache line * @cache : cache line */ void mmu_cache_write_back (ARMul_State * state, cache_t * cache_t, cache_line_t * cache); /* mmu_cache_clean: clean a cache of va in cache_t * * @state :ARMul_State * @cache_t :cache_t to clean * @va :virtaul address */ void mmu_cache_clean (ARMul_State * state, cache_t * cache_t, ARMword va); void mmu_cache_clean_by_index (ARMul_State * state, cache_t * cache_t, ARMword index); /* mmu_cache_invalidate : invalidate a cache of va * * @state :ARMul_State * @cache_t :cache_t to invalid * @va :virt_addr to invalid */ void mmu_cache_invalidate (ARMul_State * state, cache_t * cache_t, ARMword va); void mmu_cache_invalidate_by_index (ARMul_State * state, cache_t * cache_t, ARMword index); void mmu_cache_invalidate_all (ARMul_State * state, cache_t * cache_t); void mmu_cache_soft_flush (ARMul_State * state, cache_t * cache_t, ARMword pa); #endif /*_MMU_CACHE_H_*/ �������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armio.h������������������������������������������������������������0000644�0001750�0000144�00000002374�10541455476�016523� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armio.c - I/O registers and interrupt controller. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ARMIO_H_ #define _ARMIO_H_ void io_reset (ARMul_State * state); void io_do_cycle (ARMul_State * state); ARMword io_read_word (ARMul_State * state, ARMword addr); void io_write_word (ARMul_State * state, ARMword addr, ARMword data); unsigned char mem_read_char (ARMul_State * state, ARMword addr); void mem_write_char (ARMul_State * state, ARMword addr, unsigned char c); #endif /* _ARMIO_H_ */ ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armmem.h�����������������������������������������������������������0000644�0001750�0000144�00000005624�10541455476�016673� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armmem.c - Memory map decoding, ROM and RAM emulation. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ARMMEM_H_ #define _ARMMEM_H_ #define DRAM_BITS (23) /* 8MB of DRAM */ #define ROM_BANKS 16 #define ROM_BITS (28) /* 0x10000000 each bank */ typedef struct mem_state_t { ARMword *dram; ARMword *rom[ROM_BANKS]; unsigned int rom_size[ROM_BANKS]; //teawater add for arm2x86 2004.12.04------------------------------------------- uint8_t *tbp[ROM_BANKS]; //translate block pointer struct tb_s *tbt[ROM_BANKS]; //translate block structure pointer //AJ2D-------------------------------------------------------------------------- } mem_state_t; void mem_reset (ARMul_State * state); ARMword mem_read_word (ARMul_State * state, ARMword addr); void mem_write_word (ARMul_State * state, ARMword addr, ARMword data); ARMword fail_read_word (ARMul_State * state, ARMword addr); void fail_write_word (ARMul_State * state, ARMword addr, ARMword data); ARMword warn_read_word (ARMul_State * state, ARMword addr); void warn_write_byte (ARMul_State * state, ARMword addr, ARMword data); void warn_write_halfword (ARMul_State * state, ARMword addr, ARMword data); void warn_write_word (ARMul_State * state, ARMword addr, ARMword data); ARMword _read_word (ARMul_State * state, ARMword addr); void _write_word (ARMul_State * state, ARMword addr, ARMword data); ARMword real_read_byte (ARMul_State * state, ARMword addr); void real_write_byte (ARMul_State * state, ARMword addr, ARMword data); ARMword real_read_halfword (ARMul_State * state, ARMword addr); void real_write_halfword (ARMul_State * state, ARMword addr, ARMword data); ARMword real_read_word (ARMul_State * state, ARMword addr); void real_write_word (ARMul_State * state, ARMword addr, ARMword data); ARMword io_read_byte (ARMul_State * state, ARMword addr); void io_write_byte (ARMul_State * state, ARMword addr, ARMword data); ARMword io_read_halfword (ARMul_State * state, ARMword addr); void io_write_halfword (ARMul_State * state, ARMword addr, ARMword data); ARMword io_read_word (ARMul_State * state, ARMword addr); void io_write_word (ARMul_State * state, ARMword addr, ARMword data); #endif /* _ARMMEM_H_ */ ������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armos.h������������������������������������������������������������0000644�0001750�0000144�00000007650�10541455476�016537� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /***************************************************************************\ * Define the initial layout of memory * \***************************************************************************/ #define ADDRSUPERSTACK 0x800L /* supervisor stack space */ #define ADDRUSERSTACK 0x80000L /* default user stack start */ #define ADDRSOFTVECTORS 0x840L /* soft vectors are here */ #define ADDRCMDLINE 0xf00L /* command line is here after a SWI GetEnv */ #define ADDRSOFHANDLERS 0xad0L /* address and workspace for installed handlers */ #define SOFTVECTORCODE 0xb80L /* default handlers */ /***************************************************************************\ * SWI numbers * \***************************************************************************/ #define SWI_WriteC 0x0 #define SWI_Write0 0x2 #define SWI_ReadC 0x4 #define SWI_CLI 0x5 #define SWI_GetEnv 0x10 #define SWI_Exit 0x11 #define SWI_EnterOS 0x16 #define SWI_GetErrno 0x60 #define SWI_Clock 0x61 #define SWI_Time 0x63 #define SWI_Remove 0x64 #define SWI_Rename 0x65 #define SWI_Open 0x66 #define SWI_Close 0x68 #define SWI_Write 0x69 #define SWI_Read 0x6a #define SWI_Seek 0x6b #define SWI_Flen 0x6c #define SWI_IsTTY 0x6e #define SWI_TmpNam 0x6f #define SWI_InstallHandler 0x70 #define SWI_GenerateError 0x71 #define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */ #define AngelSWI_ARM 0x123456 #define AngelSWI_Thumb 0xAB /* The reason codes: */ #define AngelSWI_Reason_Open (0x01) #define AngelSWI_Reason_Close (0x02) #define AngelSWI_Reason_WriteC (0x03) #define AngelSWI_Reason_Write0 (0x04) #define AngelSWI_Reason_Write (0x05) #define AngelSWI_Reason_Read (0x06) #define AngelSWI_Reason_ReadC (0x07) #define AngelSWI_Reason_IsTTY (0x09) #define AngelSWI_Reason_Seek (0x0A) #define AngelSWI_Reason_FLen (0x0C) #define AngelSWI_Reason_TmpNam (0x0D) #define AngelSWI_Reason_Remove (0x0E) #define AngelSWI_Reason_Rename (0x0F) #define AngelSWI_Reason_Clock (0x10) #define AngelSWI_Reason_Time (0x11) #define AngelSWI_Reason_System (0x12) #define AngelSWI_Reason_Errno (0x13) #define AngelSWI_Reason_GetCmdLine (0x15) #define AngelSWI_Reason_HeapInfo (0x16) #define AngelSWI_Reason_EnterSVC (0x17) #define AngelSWI_Reason_ReportException (0x18) #define ADP_Stopped_ApplicationExit ((2 << 16) + 38) #define ADP_Stopped_RunTimeError ((2 << 16) + 34) #define FPESTART 0x2000L #define FPEEND 0x8000L #define FPEOLDVECT FPESTART + 0x100L + 8L * 16L + 4L /* stack + 8 regs + fpsr */ #define FPENEWVECT(addr) 0xea000000L + ((addr) >> 2) - 3L /* branch from 4 to 0x2400 */ extern unsigned int fpecode[]; extern unsigned int fpesize; ����������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armvirt.c����������������������������������������������������������0000644�0001750�0000144�00000051553�11006552446�017066� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* This file contains a complete ARMulator memory model, modelling a "virtual memory" system. A much simpler model can be found in armfast.c, and that model goes faster too, but has a fixed amount of memory. This model's memory has 64K pages, allocated on demand from a 64K entry page table. The routines PutWord and GetWord implement this. Pages are never freed as they might be needed again. A single area of memory may be defined to generate aborts. */ //chy 2005-09-12 disable the nouse armopts.h //#include "armopts.h" #include "armdefs.h" #include "ansidecl.h" #ifdef VALIDATE /* for running the validate suite */ #define TUBE 48 * 1024 * 1024 /* write a char on the screen */ #define ABORTS 1 #endif /* #define ABORTS */ #ifdef ABORTS /* the memory system will abort */ /* For the old test suite Abort between 32 Kbytes and 32 Mbytes For the new test suite Abort between 8 Mbytes and 26 Mbytes */ /* #define LOWABORT 32 * 1024 #define HIGHABORT 32 * 1024 * 1024 */ #define LOWABORT 8 * 1024 * 1024 #define HIGHABORT 26 * 1024 * 1024 #endif #define NUMPAGES 64 * 1024 #define PAGESIZE 64 * 1024 #define PAGEBITS 16 #define OFFSETBITS 0xffff //chy 2003-08-19: seems no use ???? int SWI_vector_installed = FALSE; extern ARMword skyeye_cachetype; /***************************************************************************\ * Get a byte into Virtual Memory, maybe allocating the page * \***************************************************************************/ static fault_t GetByte (ARMul_State * state, ARMword address, ARMword * data) { fault_t fault; fault = mmu_read_byte (state, address, data); if (fault) { //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? // printf("SKYEYE: GetByte fault %d \n", fault); } return fault; } /***************************************************************************\ * Get a halfword into Virtual Memory, maybe allocating the page * \***************************************************************************/ static fault_t GetHalfWord (ARMul_State * state, ARMword address, ARMword * data) { fault_t fault; fault = mmu_read_halfword (state, address, data); if (fault) { //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? // printf("SKYEYE: GetHalfWord fault %d \n", fault); } return fault; } /***************************************************************************\ * Get a Word from Virtual Memory, maybe allocating the page * \***************************************************************************/ static fault_t GetWord (ARMul_State * state, ARMword address, ARMword * data) { fault_t fault; fault = mmu_read_word (state, address, data); if (fault) { //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? #if 0 /* XXX */ extern int hack; hack = 1; #endif #if 0 printf ("mmu_read_word at 0x%08x: ", address); switch (fault) { case ALIGNMENT_FAULT: printf ("ALIGNMENT_FAULT"); break; case SECTION_TRANSLATION_FAULT: printf ("SECTION_TRANSLATION_FAULT"); break; case PAGE_TRANSLATION_FAULT: printf ("PAGE_TRANSLATION_FAULT"); break; case SECTION_DOMAIN_FAULT: printf ("SECTION_DOMAIN_FAULT"); break; case SECTION_PERMISSION_FAULT: printf ("SECTION_PERMISSION_FAULT"); break; case SUBPAGE_PERMISSION_FAULT: printf ("SUBPAGE_PERMISSION_FAULT"); break; default: printf ("Unrecognized fault number!"); } printf ("\tpc = 0x%08x\n", state->Reg[15]); #endif } return fault; } //2003-07-10 chy: lyh change /****************************************************************************\ * Load a Instrion Word into Virtual Memory * \****************************************************************************/ static fault_t LoadInstr (ARMul_State * state, ARMword address, ARMword * instr) { fault_t fault; fault = mmu_load_instr (state, address, instr); //if (fault) // log_msg("load_instr fault = %d, address = %x\n", fault, address); } /***************************************************************************\ * Put a byte into Virtual Memory, maybe allocating the page * \***************************************************************************/ static fault_t PutByte (ARMul_State * state, ARMword address, ARMword data) { fault_t fault; fault = mmu_write_byte (state, address, data); if (fault) { //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? // printf("SKYEYE: PutByte fault %d \n", fault); } return fault; } /***************************************************************************\ * Put a halfword into Virtual Memory, maybe allocating the page * \***************************************************************************/ static fault_t PutHalfWord (ARMul_State * state, ARMword address, ARMword data) { fault_t fault; fault = mmu_write_halfword (state, address, data); if (fault) { //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? // printf("SKYEYE: PutHalfWord fault %d \n", fault); } return fault; } /***************************************************************************\ * Put a Word into Virtual Memory, maybe allocating the page * \***************************************************************************/ static fault_t PutWord (ARMul_State * state, ARMword address, ARMword data) { fault_t fault; fault = mmu_write_word (state, address, data); if (fault) { //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? #if 0 /* XXX */ extern int hack; hack = 1; #endif #if 0 printf ("mmu_write_word at 0x%08x: ", address); switch (fault) { case ALIGNMENT_FAULT: printf ("ALIGNMENT_FAULT"); break; case SECTION_TRANSLATION_FAULT: printf ("SECTION_TRANSLATION_FAULT"); break; case PAGE_TRANSLATION_FAULT: printf ("PAGE_TRANSLATION_FAULT"); break; case SECTION_DOMAIN_FAULT: printf ("SECTION_DOMAIN_FAULT"); break; case SECTION_PERMISSION_FAULT: printf ("SECTION_PERMISSION_FAULT"); break; case SUBPAGE_PERMISSION_FAULT: printf ("SUBPAGE_PERMISSION_FAULT"); break; default: printf ("Unrecognized fault number!"); } printf ("\tpc = 0x%08x\n", state->Reg[15]); #endif } return fault; } /***************************************************************************\ * Initialise the memory interface * \***************************************************************************/ unsigned ARMul_MemoryInit (ARMul_State * state, unsigned int initmemsize) { return TRUE; } /***************************************************************************\ * Remove the memory interface * \***************************************************************************/ void ARMul_MemoryExit (ARMul_State * state) { } /***************************************************************************\ * ReLoad Instruction * \***************************************************************************/ ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize) { ARMword data; fault_t fault; #ifdef ABORTS if (address >= LOWABORT && address < HIGHABORT) { ARMul_PREFETCHABORT (address); return ARMul_ABORTWORD; } else { ARMul_CLEARABORT; } #endif if ((isize == 2) && (address & 0x2)) { ARMword lo, hi; if (!(skyeye_cachetype == INSTCACHE)) fault = GetWord (state, address, &lo); else fault = LoadInstr (state, address, &lo); if (!fault) { if (!(skyeye_cachetype == INSTCACHE)) fault = GetWord (state, address + 4, &hi); else fault = LoadInstr (state, address + 4, &hi); } if (fault) { ARMul_PREFETCHABORT (address); return ARMul_ABORTWORD; } else { ARMul_CLEARABORT; } if (state->bigendSig == HIGH) return (lo << 16) | (hi >> 16); else return ((hi & 0xFFFF) << 16) | (lo >> 16); } if (!(skyeye_cachetype == INSTCACHE)) fault = GetWord (state, address, &data); else fault = LoadInstr (state, address, &data); if (fault) { ARMul_PREFETCHABORT (address); return ARMul_ABORTWORD; } else { ARMul_CLEARABORT; } return data; } /***************************************************************************\ * Load Instruction, Sequential Cycle * \***************************************************************************/ ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize) { state->NumScycles++; #ifdef HOURGLASS if ((state->NumScycles & HOURGLASS_RATE) == 0) { HOURGLASS; } #endif return ARMul_ReLoadInstr (state, address, isize); } /***************************************************************************\ * Load Instruction, Non Sequential Cycle * \***************************************************************************/ ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize) { state->NumNcycles++; return ARMul_ReLoadInstr (state, address, isize); } /***************************************************************************\ * Read Word (but don't tell anyone!) * \***************************************************************************/ ARMword ARMul_ReadWord (ARMul_State * state, ARMword address) { ARMword data; fault_t fault; #ifdef ABORTS if (address >= LOWABORT && address < HIGHABORT) { ARMul_DATAABORT (address); return ARMul_ABORTWORD; } else { ARMul_CLEARABORT; } #endif fault = GetWord (state, address, &data); if (fault) { state->mmu.fault_status = (fault | (state->mmu.last_domain << 4)) & 0xFF; state->mmu.fault_address = address; ARMul_DATAABORT (address); return ARMul_ABORTWORD; } else { ARMul_CLEARABORT; } return data; } /***************************************************************************\ * Load Word, Sequential Cycle * \***************************************************************************/ ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address) { state->NumScycles++; return ARMul_ReadWord (state, address); } /***************************************************************************\ * Load Word, Non Sequential Cycle * \***************************************************************************/ ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address) { state->NumNcycles++; return ARMul_ReadWord (state, address); } /***************************************************************************\ * Load Halfword, (Non Sequential Cycle) * \***************************************************************************/ ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address) { ARMword data; fault_t fault; state->NumNcycles++; fault = GetHalfWord (state, address, &data); if (fault) { state->mmu.fault_status = (fault | (state->mmu.last_domain << 4)) & 0xFF; state->mmu.fault_address = address; ARMul_DATAABORT (address); return ARMul_ABORTWORD; } else { ARMul_CLEARABORT; } return data; } #if 0 ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address) { ARMword temp, offset; state->NumNcycles++; temp = ARMul_ReadWord (state, address); offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */ return (temp >> offset) & 0xffff; } #endif /***************************************************************************\ * Read Byte (but don't tell anyone!) * \***************************************************************************/ int ARMul_ICE_ReadByte(ARMul_State * state, ARMword address, ARMword *presult) { ARMword data; fault_t fault; fault = GetByte (state, address, &data); if (fault) { *presult=-1; fault=1; return fault; }else{ *(char *)presult=(unsigned char)(data & 0xff); fault=0; return fault; } } ARMword ARMul_ReadByte (ARMul_State * state, ARMword address) { ARMword data; fault_t fault; fault = GetByte (state, address, &data); if (fault) { state->mmu.fault_status = (fault | (state->mmu.last_domain << 4)) & 0xFF; state->mmu.fault_address = address; ARMul_DATAABORT (address); return ARMul_ABORTWORD; } else { ARMul_CLEARABORT; } return data; } #if 0 ARMword ARMul_ReadByte (ARMul_State * state, ARMword address) { ARMword temp, offset; temp = ARMul_ReadWord (state, address); offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */ return (temp >> offset & 0xffL); } #endif /***************************************************************************\ * Load Byte, (Non Sequential Cycle) * \***************************************************************************/ ARMword ARMul_LoadByte (ARMul_State * state, ARMword address) { state->NumNcycles++; return ARMul_ReadByte (state, address); } /***************************************************************************\ * Write Word (but don't tell anyone!) * \***************************************************************************/ void ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data) { fault_t fault; #ifdef ABORTS if (address >= LOWABORT && address < HIGHABORT) { ARMul_DATAABORT (address); return; } else { ARMul_CLEARABORT; } #endif fault = PutWord (state, address, data); if (fault) { state->mmu.fault_status = (fault | (state->mmu.last_domain << 4)) & 0xFF; state->mmu.fault_address = address; ARMul_DATAABORT (address); return; } else { ARMul_CLEARABORT; } } /***************************************************************************\ * Store Word, Sequential Cycle * \***************************************************************************/ void ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data) { state->NumScycles++; ARMul_WriteWord (state, address, data); } /***************************************************************************\ * Store Word, Non Sequential Cycle * \***************************************************************************/ void ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data) { state->NumNcycles++; ARMul_WriteWord (state, address, data); } #if 0 /***************************************************************************\ * test the virtual addr is or isn't IO address * \***************************************************************************/ //chy: 2003-05-26 //extern skyeye_config_t skyeye_config; int ARMul_notIOaddr (ARMul_State * state, ARMword address) { if (!(state->mmu.control & CONTROL_MMU)) { //chy: now is hacking, not very complete if (address >= skyeye_config.ioaddr.addr_begin && address <= skyeye_config.ioaddr.addr_end) return 0; else return 1; } else { printf ("ARMul_noIOaddr for mmuenable should do in the future!!!\n"); exit (-1); } } #endif /***************************************************************************\ * Store HalfWord, (Non Sequential Cycle) * \***************************************************************************/ void ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data) { fault_t fault; state->NumNcycles++; fault = PutHalfWord (state, address, data); if (fault) { state->mmu.fault_status = (fault | (state->mmu.last_domain << 4)) & 0xFF; state->mmu.fault_address = address; ARMul_DATAABORT (address); return; } else { ARMul_CLEARABORT; } } #if 0 void ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data) { ARMword temp, offset; state->NumNcycles++; #ifdef VALIDATE if (address == TUBE) { if (data == 4) state->Emulate = FALSE; else (void) putc ((char) data, stderr); /* Write Char */ return; } #endif //chy 2003-05-26, if the addr is io addr, then there is error(read io addr maybe change the io register value), so i change it. but now only support mmuless. for mmuenable, it will change again. if (ARMul_notIOaddr (state, address)) { temp = ARMul_ReadWord (state, address); } else { temp = 0; } offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */ PutWord (state, address, (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset)); } #endif //chy 2006-04-15 int ARMul_ICE_WriteByte (ARMul_State * state, ARMword address, ARMword data) { fault_t fault; fault = PutByte (state, address, data); if (fault) return 1; else return 0; } /***************************************************************************\ * Write Byte (but don't tell anyone!) * \***************************************************************************/ //chy 2003-07-10, add real write byte fun void ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data) { fault_t fault; fault = PutByte (state, address, data); if (fault) { state->mmu.fault_status = (fault | (state->mmu.last_domain << 4)) & 0xFF; state->mmu.fault_address = address; ARMul_DATAABORT (address); return; } else { ARMul_CLEARABORT; } } #if 0 void __ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data) { ARMword temp, offset; //chy 2003-05-26, if the addr is io addr, then there is error(read io addr maybe change the io register value), so i change it. but now only support mmuless. for mmuenable, it will change again. if (ARMul_notIOaddr (state, address)) { temp = ARMul_ReadWord (state, address); } else { temp = 0; } offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */ PutWord (state, address, (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset)); } #endif /***************************************************************************\ * Store Byte, (Non Sequential Cycle) * \***************************************************************************/ void ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data) { state->NumNcycles++; #ifdef VALIDATE if (address == TUBE) { if (data == 4) state->Emulate = FALSE; else (void) putc ((char) data, stderr); /* Write Char */ return; } #endif ARMul_WriteByte (state, address, data); } /***************************************************************************\ * Swap Word, (Two Non Sequential Cycles) * \***************************************************************************/ ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data) { ARMword temp; state->NumNcycles++; temp = ARMul_ReadWord (state, address); state->NumNcycles++; PutWord (state, address, data); return temp; } /***************************************************************************\ * Swap Byte, (Two Non Sequential Cycles) * \***************************************************************************/ ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data) { ARMword temp; temp = ARMul_LoadByte (state, address); ARMul_StoreByte (state, address, data); return temp; } /***************************************************************************\ * Count I Cycles * \***************************************************************************/ void ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED) { state->NumIcycles += number; ARMul_CLEARABORT; } /***************************************************************************\ * Count C Cycles * \***************************************************************************/ void ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED) { state->NumCcycles += number; ARMul_CLEARABORT; } �����������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/arminit.c����������������������������������������������������������0000644�0001750�0000144�00000043310�11006120657�017030� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <unistd.h> #include "armdefs.h" #include "armemu.h" /***************************************************************************\ * Definitions for the emulator architecture * \***************************************************************************/ void ARMul_EmulateInit (void); ARMul_State *ARMul_NewState (void); void ARMul_Reset (ARMul_State * state); ARMword ARMul_DoCycle (ARMul_State * state); unsigned ARMul_DoCoPro (ARMul_State * state); ARMword ARMul_DoProg (ARMul_State * state); ARMword ARMul_DoInstr (ARMul_State * state); void ARMul_Abort (ARMul_State * state, ARMword address); unsigned ARMul_MultTable[32] = { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 }; ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ char ARMul_BitList[256]; /* number of bits in a byte table */ //chy 2006-02-22 add test debugmode extern int debugmode; extern int remote_interrupt( void ); /***************************************************************************\ * Call this routine once to set up the emulator's tables. * \***************************************************************************/ void ARMul_EmulateInit (void) { unsigned int i, j; for (i = 0; i < 4096; i++) { /* the values of 12 bit dp rhs's */ ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); } for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ for (j = 1; j < 256; j <<= 1) for (i = 0; i < 256; i++) if ((i & j) > 0) ARMul_BitList[i]++; for (i = 0; i < 256; i++) ARMul_BitList[i] *= 4; /* you always need 4 times these values */ } /***************************************************************************\ * Returns a new instantiation of the ARMulator's state * \***************************************************************************/ ARMul_State * ARMul_NewState (void) { ARMul_State *state; unsigned i, j; state = (ARMul_State *) malloc (sizeof (ARMul_State)); if (state == NULL) { printf ("SKYEYE: ARMul_NewState malloc state error\n"); skyeye_exit (-1); } memset (state, 0, sizeof (ARMul_State)); state->Emulate = RUN; for (i = 0; i < 16; i++) { state->Reg[i] = 0; for (j = 0; j < 7; j++) state->RegBank[j][i] = 0; } for (i = 0; i < 7; i++) state->Spsr[i] = 0; state->Mode = 0; state->CallDebug = FALSE; state->Debug = FALSE; state->VectorCatch = 0; state->Aborted = FALSE; state->Reseted = FALSE; state->Inted = 3; state->LastInted = 3; state->MemInPtr = NULL; state->MemOutPtr = NULL; state->MemSparePtr = NULL; state->MemSize = 0; state->OSptr = NULL; state->CommandLine = NULL; state->EventSet = 0; state->Now = 0; state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * sizeof (struct EventNode *)); if (state->EventPtr == NULL) { printf ("SKYEYE: ARMul_NewState malloc state->EventPtr error\n"); skyeye_exit (-1); } for (i = 0; i < EVENTLISTSIZE; i++) *(state->EventPtr + i) = NULL; #ifdef ARM61 state->prog32Sig = LOW; state->data32Sig = LOW; #else state->prog32Sig = HIGH; state->data32Sig = HIGH; #endif state->lateabtSig = HIGH; state->bigendSig = LOW; //chy:2003-08-19 state->LastTime = 0; state->CP14R0_CCD = -1; //ARMul_Reset (state); /*ywc 2005-03-31 */ /* if(!skyeye_config.no_dbct){ //teawater add for arm2x86 2005.02.14------------------------------------------- state->tea_break_ok = 0; state->tea_break_addr = 0; state->tea_pc = 0; if (arm2x86_init()) { printf("SKYEYE: arm2x86_init error\n"); exit(-1); } //AJ2D-------------------------------------------------------------------------- } */ state->cpu = (cpu_config_t *) malloc (sizeof (cpu_config_t)); state->mem_bank = (mem_config_t *) malloc (sizeof (mem_config_t)); return (state); } /***************************************************************************\ * Call this routine to set ARMulator to model a certain processor * \***************************************************************************/ void ARMul_SelectProcessor (ARMul_State * state, unsigned properties) { if (properties & ARM_Fix26_Prop) { state->prog32Sig = LOW; state->data32Sig = LOW; } else { state->prog32Sig = HIGH; state->data32Sig = HIGH; } /* 2004-05-09 chy below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function */ // state->lateabtSig = HIGH; state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; state->is_v6 = LOW; state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; //chy 2005-09-19 state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW; /* Only initialse the coprocessor support once we know what kind of chip we are dealing with. */ ARMul_CoProInit (state); } /***************************************************************************\ * Call this routine to set up the initial machine state (or perform a RESET * \***************************************************************************/ void ARMul_Reset (ARMul_State * state) { //fprintf(stderr,"armul_reset 0: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); state->NextInstr = 0; if (state->prog32Sig) { state->Reg[15] = 0; state->Cpsr = INTBITS | SVC32MODE; state->Mode = SVC32MODE; } else { state->Reg[15] = R15INTBITS | SVC26MODE; state->Cpsr = INTBITS | SVC26MODE; state->Mode = SVC26MODE; } //fprintf(stderr,"armul_reset 1: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); ARMul_CPSRAltered (state); state->Bank = SVCBANK; FLUSHPIPE; state->EndCondition = 0; state->ErrorCode = 0; //fprintf(stderr,"armul_reset 2: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); state->NresetSig = HIGH; state->NfiqSig = HIGH; state->NirqSig = HIGH; state->NtransSig = (state->Mode & 3) ? HIGH : LOW; state->abortSig = LOW; state->AbortAddr = 1; state->NumInstrs = 0; state->NumNcycles = 0; state->NumScycles = 0; state->NumIcycles = 0; state->NumCcycles = 0; state->NumFcycles = 0; #ifdef ASIM (void) ARMul_MemoryInit (); ARMul_OSInit (state); #endif //fprintf(stderr,"armul_reset 3: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); mmu_reset (state); //fprintf(stderr,"armul_reset 4: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); mem_reset (state); //fprintf(stderr,"armul_reset 5: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); /*remove later. walimis 03.7.17 */ //io_reset(state); //lcd_disable(state); /*ywc 2005-04-07 move from ARMul_NewState , because skyeye_config.no_dbct will *be configured in skyeye_option_init and it is called after ARMul_NewState*/ state->tea_break_ok = 0; state->tea_break_addr = 0; state->tea_pc = 0; #ifdef DBCT if (!skyeye_config.no_dbct) { //teawater add for arm2x86 2005.02.14------------------------------------------- if (arm2x86_init (state)) { printf ("SKYEYE: arm2x86_init error\n"); skyeye_exit (-1); } //AJ2D-------------------------------------------------------------------------- } #endif } /***************************************************************************\ * Emulate the execution of an entire program. Start the correct emulator * * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * * address of the last instruction that is executed. * \***************************************************************************/ //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED static ARMul_State *dbct_test_speed_state = NULL; static void dbct_test_speed_sig(int signo) { printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count); skyeye_exit(0); } #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- ARMword ARMul_DoProg (ARMul_State * state) { ARMword pc = 0; /* * 2007-01-24 removed the term-io functions by Anthony Lee, * moved to "device/uart/skyeye_uart_stdio.c". */ //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- #ifdef DBCT_TEST_SPEED { if (!dbct_test_speed_state) { //init timer struct itimerval value; struct sigaction act; dbct_test_speed_state = state; state->instr_count = 0; act.sa_handler = dbct_test_speed_sig; act.sa_flags = SA_RESTART; //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF #ifndef __CYGWIN__ if (sigaction(SIGVTALRM, &act, NULL) == -1) { #else if (sigaction(SIGALRM, &act, NULL) == -1) { #endif //__CYGWIN__ fprintf(stderr, "init timer error.\n"); skyeye_exit(-1); } if (skyeye_config.dbct_test_speed_sec) { value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec; } else { value.it_value.tv_sec = DBCT_TEST_SPEED_SEC; } printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec); value.it_value.tv_usec = 0; value.it_interval.tv_sec = 0; value.it_interval.tv_usec = 0; #ifndef __CYGWIN__ if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) { #else if (setitimer(ITIMER_REAL, &value, NULL) == -1) { #endif //__CYGWIN__ fprintf(stderr, "init timer error.\n"); skyeye_exit(-1); } } } #endif //DBCT_TEST_SPEED //AJ2D-------------------------------------------------------------------------- state->Emulate = RUN; while (state->Emulate != STOP) { state->Emulate = RUN; /*ywc 2005-03-31 */ if (state->prog32Sig && ARMul_MODE32BIT) { #ifdef DBCT if (skyeye_config.no_dbct) { pc = ARMul_Emulate32 (state); } else { pc = ARMul_Emulate32_dbct (state); } #else pc = ARMul_Emulate32 (state); #endif } else pc = ARMul_Emulate26 (state); //chy 2006-02-22, should test debugmode first //chy 2006-04-14, put below codes in ARMul_Emulate #if 0 if(debugmode) if(remote_interrupt()) state->Emulate = STOP; #endif } /* * 2007-01-24 removed the term-io functions by Anthony Lee, * moved to "device/uart/skyeye_uart_stdio.c". */ return (pc); } /***************************************************************************\ * Emulate the execution of one instruction. Start the correct emulator * * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * * address of the instruction that is executed. * \***************************************************************************/ ARMword ARMul_DoInstr (ARMul_State * state) { ARMword pc = 0; state->Emulate = ONCE; /*ywc 2005-03-31 */ if (state->prog32Sig && ARMul_MODE32BIT) { #ifdef DBCT if (skyeye_config.no_dbct) { pc = ARMul_Emulate32 (state); } else { //teawater add compile switch for DBCT GDB RSP function 2005.10.21-------------- #ifndef DBCT_GDBRSP printf("DBCT GDBRSP function switch is off.\n"); printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n"); skyeye_exit(-1); #endif //DBCT_GDBRSP //AJ2D-------------------------------------------------------------------------- pc = ARMul_Emulate32_dbct (state); } #else pc = ARMul_Emulate32 (state); #endif } else pc = ARMul_Emulate26 (state); return (pc); } /***************************************************************************\ * This routine causes an Abort to occur, including selecting the correct * * mode, register bank, and the saving of registers. Call with the * * appropriate vector's memory address (0,4,8 ....) * \***************************************************************************/ #if 0 void ARMul_Abort (ARMul_State * state, ARMword vector) { ARMword temp; state->Aborted = FALSE; if (ARMul_OSException (state, vector, ARMul_GetPC (state))) return; if (state->prog32Sig) if (ARMul_MODE26BIT) temp = R15PC; else temp = state->Reg[15]; else temp = R15PC | ECC | ER15INT | EMODE; switch (vector) { case ARMul_ResetV: /* RESET */ state->Spsr[SVCBANK] = CPSR; SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp; break; case ARMul_UndefinedInstrV: /* Undefined Instruction */ state->Spsr[state->prog32Sig ? UNDEFBANK : SVCBANK] = CPSR; SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp - 4; break; case ARMul_SWIV: /* Software Interrupt */ state->Spsr[SVCBANK] = CPSR; SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp - 4; break; case ARMul_PrefetchAbortV: /* Prefetch Abort */ state->AbortAddr = 1; state->Spsr[state->prog32Sig ? ABORTBANK : SVCBANK] = CPSR; SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp - 4; break; case ARMul_DataAbortV: /* Data Abort */ state->Spsr[state->prog32Sig ? ABORTBANK : SVCBANK] = CPSR; SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp - 4; /* the PC must have been incremented */ break; case ARMul_AddrExceptnV: /* Address Exception */ state->Spsr[SVCBANK] = CPSR; SETABORT (IBIT, SVC26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp - 4; break; case ARMul_IRQV: /* IRQ */ state->Spsr[IRQBANK] = CPSR; SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp - 4; break; case ARMul_FIQV: /* FIQ */ state->Spsr[FIQBANK] = CPSR; SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE); ARMul_CPSRAltered (state); state->Reg[14] = temp - 4; break; } if (ARMul_MODE32BIT) { if (state->mmu.control & CONTROL_VECTOR) vector += 0xffff0000; //for v4 high exception address ARMul_SetR15 (state, vector); } else ARMul_SetR15 (state, R15CCINTMODE | vector); } #endif void ARMul_Abort (ARMul_State * state, ARMword vector) { ARMword temp; int isize = INSN_SIZE; int esize = (TFLAG ? 0 : 4); int e2size = (TFLAG ? -4 : 0); state->Aborted = FALSE; if (ARMul_OSException (state, vector, ARMul_GetPC (state))) return; if (state->prog32Sig) if (ARMul_MODE26BIT) temp = R15PC; else temp = state->Reg[15]; else temp = R15PC | ECC | ER15INT | EMODE; switch (vector) { case ARMul_ResetV: /* RESET */ SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0); break; case ARMul_UndefinedInstrV: /* Undefined Instruction */ SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize); break; case ARMul_SWIV: /* Software Interrupt */ SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize); break; case ARMul_PrefetchAbortV: /* Prefetch Abort */ state->AbortAddr = 1; SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize); break; case ARMul_DataAbortV: /* Data Abort */ SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size); break; case ARMul_AddrExceptnV: /* Address Exception */ SETABORT (IBIT, SVC26MODE, isize); break; case ARMul_IRQV: /* IRQ */ //chy 2003-09-02 the if sentence seems no use #if 0 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) || (temp & ARMul_CP13_R0_IRQ)) #endif SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize); break; case ARMul_FIQV: /* FIQ */ //chy 2003-09-02 the if sentence seems no use #if 0 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) || (temp & ARMul_CP13_R0_FIQ)) #endif SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize); break; } if (ARMul_MODE32BIT) { if (state->mmu.control & CONTROL_VECTOR) vector += 0xffff0000; //for v4 high exception address if (state->vector_remap_flag) vector += state->vector_remap_addr; /* support some remap function in LPC processor */ ARMul_SetR15 (state, vector); } else ARMul_SetR15 (state, R15CCINTMODE | vector); #if 0 if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0) { /* No vector has been installed. Rather than simulating whatever random bits might happen to be at address 0x20 onwards we elect to stop. */ switch (vector) { case ARMul_ResetV: state->EndCondition = RDIError_Reset; break; case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break; case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break; case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break; case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break; case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break; case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break; case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break; default: break; } state->Emulate = FALSE; } #endif } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armsupp.c����������������������������������������������������������0000644�0001750�0000144�00000052532�10541455476�017077� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "armdefs.h" #include "armemu.h" #include "ansidecl.h" //extern int skyeye_instr_debug; /* Definitions for the support routines. */ static ARMword ModeToBank (ARMword); static void EnvokeList (ARMul_State *, unsigned int, unsigned int); struct EventNode { /* An event list node. */ unsigned (*func) (ARMul_State *); /* The function to call. */ struct EventNode *next; }; /* This routine returns the value of a register from a mode. */ ARMword ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg) { mode &= MODEBITS; if (mode != state->Mode) return (state->RegBank[ModeToBank ((ARMword) mode)][reg]); else return (state->Reg[reg]); } /* This routine sets the value of a register for a mode. */ void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value) { mode &= MODEBITS; if (mode != state->Mode) state->RegBank[ModeToBank ((ARMword) mode)][reg] = value; else state->Reg[reg] = value; } /* This routine returns the value of the PC, mode independently. */ ARMword ARMul_GetPC (ARMul_State * state) { if (state->Mode > SVC26MODE) return state->Reg[15]; else return R15PC; } /* This routine returns the value of the PC, mode independently. */ ARMword ARMul_GetNextPC (ARMul_State * state) { if (state->Mode > SVC26MODE) return state->Reg[15] + isize; else return (state->Reg[15] + isize) & R15PCBITS; } /* This routine sets the value of the PC. */ void ARMul_SetPC (ARMul_State * state, ARMword value) { if (ARMul_MODE32BIT) state->Reg[15] = value & PCBITS; else state->Reg[15] = R15CCINTMODE | (value & R15PCBITS); FLUSHPIPE; } /* This routine returns the value of register 15, mode independently. */ ARMword ARMul_GetR15 (ARMul_State * state) { if (state->Mode > SVC26MODE) return (state->Reg[15]); else return (R15PC | ECC | ER15INT | EMODE); } /* This routine sets the value of Register 15. */ void ARMul_SetR15 (ARMul_State * state, ARMword value) { if (ARMul_MODE32BIT) state->Reg[15] = value & PCBITS; else { state->Reg[15] = value; ARMul_R15Altered (state); } FLUSHPIPE; } /* This routine returns the value of the CPSR. */ ARMword ARMul_GetCPSR (ARMul_State * state) { //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator //return (CPSR | state->Cpsr); for gdb20030716 return (CPSR); //had be tested in old skyeye with gdb5.0-5.3 } /* This routine sets the value of the CPSR. */ void ARMul_SetCPSR (ARMul_State * state, ARMword value) { state->Cpsr = value; ARMul_CPSRAltered (state); } /* This routine does all the nasty bits involved in a write to the CPSR, including updating the register bank, given a MSR instruction. */ void ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs) { state->Cpsr = ARMul_GetCPSR (state); //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode if (state->Mode != USER26MODE && state->Mode != USER32MODE ) { /* In user mode, only write flags. */ if (BIT (16)) SETPSR_C (state->Cpsr, rhs); if (BIT (17)) SETPSR_X (state->Cpsr, rhs); if (BIT (18)) SETPSR_S (state->Cpsr, rhs); } if (BIT (19)) SETPSR_F (state->Cpsr, rhs); ARMul_CPSRAltered (state); } /* Get an SPSR from the specified mode. */ ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode) { ARMword bank = ModeToBank (mode & MODEBITS); if (!BANK_CAN_ACCESS_SPSR (bank)) return ARMul_GetCPSR (state); return state->Spsr[bank]; } /* This routine does a write to an SPSR. */ void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value) { ARMword bank = ModeToBank (mode & MODEBITS); if (BANK_CAN_ACCESS_SPSR (bank)) state->Spsr[bank] = value; } /* This routine does a write to the current SPSR, given an MSR instruction. */ void ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs) { if (BANK_CAN_ACCESS_SPSR (state->Bank)) { if (BIT (16)) SETPSR_C (state->Spsr[state->Bank], rhs); if (BIT (17)) SETPSR_X (state->Spsr[state->Bank], rhs); if (BIT (18)) SETPSR_S (state->Spsr[state->Bank], rhs); if (BIT (19)) SETPSR_F (state->Spsr[state->Bank], rhs); } } /* This routine updates the state of the emulator after the Cpsr has been changed. Both the processor flags and register bank are updated. */ void ARMul_CPSRAltered (ARMul_State * state) { ARMword oldmode; if (state->prog32Sig == LOW) state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS); oldmode = state->Mode; if (state->Mode != (state->Cpsr & MODEBITS)) { state->Mode = ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS); state->NtransSig = (state->Mode & 3) ? HIGH : LOW; } //state->Cpsr &= ~MODEBITS; ASSIGNINT (state->Cpsr & INTBITS); //state->Cpsr &= ~INTBITS; ASSIGNN ((state->Cpsr & NBIT) != 0); //state->Cpsr &= ~NBIT; ASSIGNZ ((state->Cpsr & ZBIT) != 0); //state->Cpsr &= ~ZBIT; ASSIGNC ((state->Cpsr & CBIT) != 0); //state->Cpsr &= ~CBIT; ASSIGNV ((state->Cpsr & VBIT) != 0); //state->Cpsr &= ~VBIT; ASSIGNS ((state->Cpsr & SBIT) != 0); //state->Cpsr &= ~SBIT; #ifdef MODET ASSIGNT ((state->Cpsr & TBIT) != 0); //state->Cpsr &= ~TBIT; #endif if (oldmode > SVC26MODE) { if (state->Mode <= SVC26MODE) { state->Emulate = CHANGEMODE; state->Reg[15] = ECC | ER15INT | EMODE | R15PC; } } else { if (state->Mode > SVC26MODE) { state->Emulate = CHANGEMODE; state->Reg[15] = R15PC; } else state->Reg[15] = ECC | ER15INT | EMODE | R15PC; } } /* This routine updates the state of the emulator after register 15 has been changed. Both the processor flags and register bank are updated. This routine should only be called from a 26 bit mode. */ void ARMul_R15Altered (ARMul_State * state) { if (state->Mode != R15MODE) { state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE); state->NtransSig = (state->Mode & 3) ? HIGH : LOW; } if (state->Mode > SVC26MODE) state->Emulate = CHANGEMODE; ASSIGNR15INT (R15INT); ASSIGNN ((state->Reg[15] & NBIT) != 0); ASSIGNZ ((state->Reg[15] & ZBIT) != 0); ASSIGNC ((state->Reg[15] & CBIT) != 0); ASSIGNV ((state->Reg[15] & VBIT) != 0); } /* This routine controls the saving and restoring of registers across mode changes. The regbank matrix is largely unused, only rows 13 and 14 are used across all modes, 8 to 14 are used for FIQ, all others use the USER column. It's easier this way. old and new parameter are modes numbers. Notice the side effect of changing the Bank variable. */ ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode) { unsigned i; ARMword oldbank; ARMword newbank; oldbank = ModeToBank (oldmode); newbank = state->Bank = ModeToBank (newmode); /* Do we really need to do it? */ if (oldbank != newbank) { /* Save away the old registers. */ switch (oldbank) { case USERBANK: case IRQBANK: case SVCBANK: case ABORTBANK: case UNDEFBANK: if (newbank == FIQBANK) for (i = 8; i < 13; i++) state->RegBank[USERBANK][i] = state->Reg[i]; state->RegBank[oldbank][13] = state->Reg[13]; state->RegBank[oldbank][14] = state->Reg[14]; break; case FIQBANK: for (i = 8; i < 15; i++) state->RegBank[FIQBANK][i] = state->Reg[i]; break; case DUMMYBANK: for (i = 8; i < 15; i++) state->RegBank[DUMMYBANK][i] = 0; break; default: abort (); } /* Restore the new registers. */ switch (newbank) { case USERBANK: case IRQBANK: case SVCBANK: case ABORTBANK: case UNDEFBANK: if (oldbank == FIQBANK) for (i = 8; i < 13; i++) state->Reg[i] = state->RegBank[USERBANK][i]; state->Reg[13] = state->RegBank[newbank][13]; state->Reg[14] = state->RegBank[newbank][14]; break; case FIQBANK: for (i = 8; i < 15; i++) state->Reg[i] = state->RegBank[FIQBANK][i]; break; case DUMMYBANK: for (i = 8; i < 15; i++) state->Reg[i] = 0; break; default: abort (); } } return newmode; } /* Given a processor mode, this routine returns the register bank that will be accessed in that mode. */ static ARMword ModeToBank (ARMword mode) { static ARMword bankofmode[] = { USERBANK, FIQBANK, IRQBANK, SVCBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, USERBANK, FIQBANK, IRQBANK, SVCBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK }; if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0]))) return DUMMYBANK; return bankofmode[mode]; } /* Returns the register number of the nth register in a reg list. */ unsigned ARMul_NthReg (ARMword instr, unsigned number) { unsigned bit, upto; for (bit = 0, upto = 0; upto <= number; bit++) if (BIT (bit)) upto++; return (bit - 1); } /* Assigns the N and Z flags depending on the value of result. */ void ARMul_NegZero (ARMul_State * state, ARMword result) { if (NEG (result)) { SETN; CLEARZ; } else if (result == 0) { CLEARN; SETZ; } else { CLEARN; CLEARZ; } } /* Compute whether an addition of A and B, giving RESULT, overflowed. */ int AddOverflow (ARMword a, ARMword b, ARMword result) { return ((NEG (a) && NEG (b) && POS (result)) || (POS (a) && POS (b) && NEG (result))); } /* Compute whether a subtraction of A and B, giving RESULT, overflowed. */ int SubOverflow (ARMword a, ARMword b, ARMword result) { return ((NEG (a) && POS (b) && POS (result)) || (POS (a) && NEG (b) && NEG (result))); } /* Assigns the C flag after an addition of a and b to give result. */ void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) { ASSIGNC ((NEG (a) && NEG (b)) || (NEG (a) && POS (result)) || (NEG (b) && POS (result))); } /* Assigns the V flag after an addition of a and b to give result. */ void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) { ASSIGNV (AddOverflow (a, b, result)); } /* Assigns the C flag after an subtraction of a and b to give result. */ void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) { ASSIGNC ((NEG (a) && POS (b)) || (NEG (a) && POS (result)) || (POS (b) && POS (result))); } /* Assigns the V flag after an subtraction of a and b to give result. */ void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) { ASSIGNV (SubOverflow (a, b, result)); } /* This function does the work of generating the addresses used in an LDC instruction. The code here is always post-indexed, it's up to the caller to get the input address correct and to handle base register modification. It also handles the Busy-Waiting. */ void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address) { unsigned cpab; ARMword data; UNDEF_LSCPCBaseWb; //printf("SKYEYE ARMul_LDC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address); /*chy 2004-05-23 should update this function in the future,should concern dataabort*/ // chy 2004-05-25 , fix it now,so needn't printf // printf("SKYEYE ARMul_LDC, should update this function!!!!!\n"); //exit(-1); if (!CP_ACCESS_ALLOWED (state, CPNum)) { /* printf ("SKYEYE ARMul_LDC,NOT ALLOW, underinstr, CPnum is %x, instr %x, addr %x\n", CPNum, instr, address); */ ARMul_UndefInstr (state, instr); return; } if (ADDREXCEPT (address)) INTERNALABORT (address); cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0); while (cpab == ARMul_BUSY) { ARMul_Icycles (state, 1, 0); if (IntPending (state)) { cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, instr, 0); return; } else cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 0); } if (cpab == ARMul_CANT) { /* printf ("SKYEYE ARMul_LDC,NOT CAN, underinstr, CPnum is %x, instr %x, addr %x\n", CPNum, instr, address); */ CPTAKEABORT; return; } cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0); data = ARMul_LoadWordN (state, address); //chy 2004-05-25 if (state->abortSig || state->Aborted) goto L_ldc_takeabort; BUSUSEDINCPCN; //chy 2004-05-25 /* if (BIT (21)) LSBase = state->Base; */ cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); while (cpab == ARMul_INC) { address += 4; data = ARMul_LoadWordN (state, address); //chy 2004-05-25 if (state->abortSig || state->Aborted) goto L_ldc_takeabort; cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); } //chy 2004-05-25 L_ldc_takeabort: if (BIT (21)) { if (! ((state->abortSig || state->Aborted) && state->lateabtSig == LOW)) LSBase = state->Base; } if (state->abortSig || state->Aborted) TAKEABORT; } /* This function does the work of generating the addresses used in an STC instruction. The code here is always post-indexed, it's up to the caller to get the input address correct and to handle base register modification. It also handles the Busy-Waiting. */ void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address) { unsigned cpab; ARMword data; UNDEF_LSCPCBaseWb; //printf("SKYEYE ARMul_STC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address); /*chy 2004-05-23 should update this function in the future,should concern dataabort */ // skyeye_instr_debug=0;printf("SKYEYE debug end!!!!\n"); // chy 2004-05-25 , fix it now,so needn't printf // printf("SKYEYE ARMul_STC, should update this function!!!!!\n"); //exit(-1); if (!CP_ACCESS_ALLOWED (state, CPNum)) { /* printf ("SKYEYE ARMul_STC,NOT ALLOW, undefinstr, CPnum is %x, instr %x, addr %x\n", CPNum, instr, address); */ ARMul_UndefInstr (state, instr); return; } if (ADDREXCEPT (address) || VECTORACCESS (address)) INTERNALABORT (address); cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data); while (cpab == ARMul_BUSY) { ARMul_Icycles (state, 1, 0); if (IntPending (state)) { cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, instr, 0); return; } else cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, &data); } if (cpab == ARMul_CANT) { /* printf ("SKYEYE ARMul_STC,CANT, undefinstr, CPnum is %x, instr %x, addr %x\n", CPNum, instr, address); */ CPTAKEABORT; return; } #ifndef MODE32 if (ADDREXCEPT (address) || VECTORACCESS (address)) INTERNALABORT (address); #endif BUSUSEDINCPCN; //chy 2004-05-25 /* if (BIT (21)) LSBase = state->Base; */ cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); ARMul_StoreWordN (state, address, data); //chy 2004-05-25 if (state->abortSig || state->Aborted) goto L_stc_takeabort; while (cpab == ARMul_INC) { address += 4; cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); ARMul_StoreWordN (state, address, data); //chy 2004-05-25 if (state->abortSig || state->Aborted) goto L_stc_takeabort; } //chy 2004-05-25 L_stc_takeabort: if (BIT (21)) { if (! ((state->abortSig || state->Aborted) && state->lateabtSig == LOW)) LSBase = state->Base; } if (state->abortSig || state->Aborted) TAKEABORT; } /* This function does the Busy-Waiting for an MCR instruction. */ void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) { unsigned cpab; //printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source); if (!CP_ACCESS_ALLOWED (state, CPNum)) { //chy 2004-07-19 should fix in the future ????!!!! //printf("SKYEYE ARMul_MCR, ACCESS_not ALLOWed, UndefinedInstr CPnum is %x, source %x\n",CPNum, source); ARMul_UndefInstr (state, instr); return; } cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source); while (cpab == ARMul_BUSY) { ARMul_Icycles (state, 1, 0); if (IntPending (state)) { cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0); return; } else cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source); } if (cpab == ARMul_CANT) { printf ("SKYEYE ARMul_MCR, CANT, UndefinedInstr CPnum is %x, source %x\n", CPNum, source); ARMul_Abort (state, ARMul_UndefinedInstrV); } else { BUSUSEDINCPCN; ARMul_Ccycles (state, 1, 0); } } /* This function does the Busy-Waiting for an MRC instruction. */ ARMword ARMul_MRC (ARMul_State * state, ARMword instr) { unsigned cpab; ARMword result = 0; //printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr); if (!CP_ACCESS_ALLOWED (state, CPNum)) { //chy 2004-07-19 should fix in the future????!!!! //printf("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n",CPNum, instr); ARMul_UndefInstr (state, instr); return; } cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result); while (cpab == ARMul_BUSY) { ARMul_Icycles (state, 1, 0); if (IntPending (state)) { cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, instr, 0); return (0); } else cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, &result); } if (cpab == ARMul_CANT) { printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr); ARMul_Abort (state, ARMul_UndefinedInstrV); /* Parent will destroy the flags otherwise. */ result = ECC; } else { BUSUSEDINCPCN; ARMul_Ccycles (state, 1, 0); ARMul_Icycles (state, 1, 0); } return result; } /* This function does the Busy-Waiting for an CDP instruction. */ void ARMul_CDP (ARMul_State * state, ARMword instr) { unsigned cpab; if (!CP_ACCESS_ALLOWED (state, CPNum)) { ARMul_UndefInstr (state, instr); return; } cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr); while (cpab == ARMul_BUSY) { ARMul_Icycles (state, 1, 0); if (IntPending (state)) { cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, instr); return; } else cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr); } if (cpab == ARMul_CANT) ARMul_Abort (state, ARMul_UndefinedInstrV); else BUSUSEDN; } /* This function handles Undefined instructions, as CP isntruction. */ void ARMul_UndefInstr (ARMul_State * state, ARMword instr ATTRIBUTE_UNUSED) { ARMul_Abort (state, ARMul_UndefinedInstrV); } /* Return TRUE if an interrupt is pending, FALSE otherwise. */ unsigned IntPending (ARMul_State * state) { /* Any exceptions. */ if (state->NresetSig == LOW) { ARMul_Abort (state, ARMul_ResetV); return TRUE; } else if (!state->NfiqSig && !FFLAG) { ARMul_Abort (state, ARMul_FIQV); return TRUE; } else if (!state->NirqSig && !IFLAG) { ARMul_Abort (state, ARMul_IRQV); return TRUE; } return FALSE; } /* Align a word access to a non word boundary. */ ARMword ARMul_Align (state, address, data) ARMul_State *state ATTRIBUTE_UNUSED; ARMword address; ARMword data; { /* This code assumes the address is really unaligned, as a shift by 32 is undefined in C. */ address = (address & 3) << 3; /* Get the word address. */ return ((data >> address) | (data << (32 - address))); /* rot right */ } /* This routine is used to call another routine after a certain number of cycles have been executed. The first parameter is the number of cycles delay before the function is called, the second argument is a pointer to the function. A delay of zero doesn't work, just call the function. */ void ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay, unsigned (*what) (ARMul_State *)) { unsigned int when; struct EventNode *event; if (state->EventSet++ == 0) state->Now = ARMul_Time (state); when = (state->Now + delay) % EVENTLISTSIZE; event = (struct EventNode *) malloc (sizeof (struct EventNode)); if (!event) { printf ("SKYEYE:ARMul_ScheduleEvent: malloc event error\n"); skyeye_exit (-1); } event->func = what; event->next = *(state->EventPtr + when); *(state->EventPtr + when) = event; } /* This routine is called at the beginning of every cycle, to envoke scheduled events. */ void ARMul_EnvokeEvent (ARMul_State * state) { static unsigned int then; then = state->Now; state->Now = ARMul_Time (state) % EVENTLISTSIZE; if (then < state->Now) /* Schedule events. */ EnvokeList (state, then, state->Now); else if (then > state->Now) { /* Need to wrap around the list. */ EnvokeList (state, then, EVENTLISTSIZE - 1L); EnvokeList (state, 0L, state->Now); } } /* Envokes all the entries in a range. */ static void EnvokeList (ARMul_State * state, unsigned int from, unsigned int to) { for (; from <= to; from++) { struct EventNode *anevent; anevent = *(state->EventPtr + from); while (anevent) { (anevent->func) (state); state->EventSet--; anevent = anevent->next; } *(state->EventPtr + from) = NULL; } } /* This routine is returns the number of clock ticks since the last reset. */ unsigned int ARMul_Time (ARMul_State * state) { return (state->NumScycles + state->NumNcycles + state->NumIcycles + state->NumCcycles + state->NumFcycles); } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armemu.h�����������������������������������������������������������0000644�0001750�0000144�00000041666�11006120657�016674� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __ARMEMU_H__ #define __ARMEMU_H__ #include "armdefs.h" extern ARMword isize; /* Condition code values. */ #define EQ 0 #define NE 1 #define CS 2 #define CC 3 #define MI 4 #define PL 5 #define VS 6 #define VC 7 #define HI 8 #define LS 9 #define GE 10 #define LT 11 #define GT 12 #define LE 13 #define AL 14 #define NV 15 /* Shift Opcodes. */ #define LSL 0 #define LSR 1 #define ASR 2 #define ROR 3 /* Macros to twiddle the status flags and mode. */ #define NBIT ((unsigned)1L << 31) #define ZBIT (1L << 30) #define CBIT (1L << 29) #define VBIT (1L << 28) #define SBIT (1L << 27) #define IBIT (1L << 7) #define FBIT (1L << 6) #define IFBITS (3L << 6) #define R15IBIT (1L << 27) #define R15FBIT (1L << 26) #define R15IFBITS (3L << 26) #define POS(i) ( (~(i)) >> 31 ) #define NEG(i) ( (i) >> 31 ) #ifdef MODET /* Thumb support. */ /* ??? This bit is actually in the low order bit of the PC in the hardware. It isn't clear if the simulator needs to model that or not. */ #define TBIT (1L << 5) #define TFLAG state->TFlag #define SETT state->TFlag = 1 #define CLEART state->TFlag = 0 #define ASSIGNT(res) state->TFlag = res #define INSN_SIZE (TFLAG ? 2 : 4) #else #define INSN_SIZE 4 #endif #define NFLAG state->NFlag #define SETN state->NFlag = 1 #define CLEARN state->NFlag = 0 #define ASSIGNN(res) state->NFlag = res #define ZFLAG state->ZFlag #define SETZ state->ZFlag = 1 #define CLEARZ state->ZFlag = 0 #define ASSIGNZ(res) state->ZFlag = res #define CFLAG state->CFlag #define SETC state->CFlag = 1 #define CLEARC state->CFlag = 0 #define ASSIGNC(res) state->CFlag = res #define VFLAG state->VFlag #define SETV state->VFlag = 1 #define CLEARV state->VFlag = 0 #define ASSIGNV(res) state->VFlag = res #define SFLAG state->SFlag #define SETS state->SFlag = 1 #define CLEARS state->SFlag = 0 #define ASSIGNS(res) state->SFlag = res #define IFLAG (state->IFFlags >> 1) #define FFLAG (state->IFFlags & 1) #define IFFLAGS state->IFFlags #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3) #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ; #define PSR_FBITS (0xff000000L) #define PSR_SBITS (0x00ff0000L) #define PSR_XBITS (0x0000ff00L) #define PSR_CBITS (0x000000ffL) #if defined MODE32 || defined MODET #define CCBITS (0xf8000000L) #else #define CCBITS (0xf0000000L) #endif #define INTBITS (0xc0L) #if defined MODET && defined MODE32 #define PCBITS (0xffffffffL) #else #define PCBITS (0xfffffffcL) #endif #define MODEBITS (0x1fL) #define R15INTBITS (3L << 26) #if defined MODET && defined MODE32 #define R15PCBITS (0x03ffffffL) #else #define R15PCBITS (0x03fffffcL) #endif #define R15PCMODEBITS (0x03ffffffL) #define R15MODEBITS (0x3L) #ifdef MODE32 #define PCMASK PCBITS #define PCWRAP(pc) (pc) #else #define PCMASK R15PCBITS #define PCWRAP(pc) ((pc) & R15PCBITS) #endif #define PC (state->Reg[15] & PCMASK) #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) #define R15INT (state->Reg[15] & R15INTBITS) #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS)) #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS)) #define R15PC (state->Reg[15] & R15PCBITS) #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS)) #define R15MODE (state->Reg[15] & R15MODEBITS) #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27)) #define EINT (IFFLAGS << 6) #define ER15INT (IFFLAGS << 26) #define EMODE (state->Mode) #ifdef MODET #define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) #else #define CPSR (ECC | EINT | EMODE) #endif #ifdef MODE32 #define PATCHR15 #else #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC #endif #define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE)) #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS) #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS) #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS) #define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS) #define SETR15PSR(s) \ do \ { \ if (state->Mode == USER26MODE) \ { \ state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \ ASSIGNN ((state->Reg[15] & NBIT) != 0); \ ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \ ASSIGNC ((state->Reg[15] & CBIT) != 0); \ ASSIGNV ((state->Reg[15] & VBIT) != 0); \ } \ else \ { \ state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \ ARMul_R15Altered (state); \ } \ } \ while (0) #define SETABORT(i, m, d) \ do \ { \ int SETABORT_mode = (m); \ \ ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \ ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \ | (i) | SETABORT_mode)); \ state->Reg[14] = temp - (d); \ } \ while (0) #ifndef MODE32 #define VECTORS 0x20 #define LEGALADDR 0x03ffffff #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig) #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig) #endif #define INTERNALABORT(address) \ do \ { \ if (address < VECTORS) \ state->Aborted = ARMul_DataAbortV; \ else \ state->Aborted = ARMul_AddrExceptnV; \ } \ while (0) #ifdef MODE32 #define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV) #else #define TAKEABORT \ do \ { \ if (state->Aborted == ARMul_AddrExceptnV) \ ARMul_Abort (state, ARMul_AddrExceptnV); \ else \ ARMul_Abort (state, ARMul_DataAbortV); \ } \ while (0) #endif #define CPTAKEABORT \ do \ { \ if (!state->Aborted) \ ARMul_Abort (state, ARMul_UndefinedInstrV); \ else if (state->Aborted == ARMul_AddrExceptnV) \ ARMul_Abort (state, ARMul_AddrExceptnV); \ else \ ARMul_Abort (state, ARMul_DataAbortV); \ } \ while (0); /* Different ways to start the next instruction. */ #define SEQ 0 #define NONSEQ 1 #define PCINCEDSEQ 2 #define PCINCEDNONSEQ 3 #define PRIMEPIPE 4 #define RESUME 8 #define NORMALCYCLE state->NextInstr = 0 #define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */ #define BUSUSEDINCPCS \ do \ { \ if (! state->is_v4) \ { \ /* A standard PC inc and an S cycle. */ \ state->Reg[15] += isize; \ state->NextInstr = (state->NextInstr & 0xff) | 2; \ } \ } \ while (0) #define BUSUSEDINCPCN \ do \ { \ if (state->is_v4) \ BUSUSEDN; \ else \ { \ /* A standard PC inc and an N cycle. */ \ state->Reg[15] += isize; \ state->NextInstr |= 3; \ } \ } \ while (0) #define INCPC \ do \ { \ /* A standard PC inc. */ \ state->Reg[15] += isize; \ state->NextInstr |= 2; \ } \ while (0) #define FLUSHPIPE state->NextInstr |= PRIMEPIPE /* Cycle based emulation. */ #define OUTPUTCP(i,a,b) #define NCYCLE #define SCYCLE #define ICYCLE #define CCYCLE #define NEXTCYCLE(c) /* Macros to extract parts of instructions. */ #define DESTReg (BITS (12, 15)) #define LHSReg (BITS (16, 19)) #define RHSReg (BITS ( 0, 3)) #define DEST (state->Reg[DESTReg]) #ifdef MODE32 #ifdef MODET #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg])) #else #define LHS (state->Reg[LHSReg]) #endif #else #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg])) #endif #define MULDESTReg (BITS (16, 19)) #define MULLHSReg (BITS ( 0, 3)) #define MULRHSReg (BITS ( 8, 11)) #define MULACCReg (BITS (12, 15)) #define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)]) #define DPSImmRHS temp = BITS(0,11) ; \ rhs = ARMul_ImmedTable[temp] ; \ if (temp > 255) /* There was a shift. */ \ ASSIGNC (rhs >> 31) ; #ifdef MODE32 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ : GetDPRegRHS (state, instr)) #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ : GetDPSRegRHS (state, instr)) #else #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ : GetDPRegRHS (state, instr)) #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ : GetDPSRegRHS (state, instr)) #endif #define LSBase state->Reg[LHSReg] #define LSImmRHS (BITS(0,11)) #ifdef MODE32 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \ : GetLSRegRHS (state, instr)) #else #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ : GetLSRegRHS (state, instr)) #endif #define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \ (ARMword) ARMul_BitList[BITS (8, 15)] ) #define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \ (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0)) #define SWAPSRC (state->Reg[RHSReg]) #define LSCOff (BITS (0, 7) << 2) #define CPNum BITS (8, 11) /* Determine if access to coprocessor CP is permitted. The XScale has a register in CP15 which controls access to CP0 - CP13. */ //chy 2003-09-03, new CP_ACCESS_ALLOWED /* #define CP_ACCESS_ALLOWED(STATE, CP) \ ( ((CP) >= 14) \ || (! (STATE)->is_XScale) \ || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) */ #define CP_ACCESS_ALLOWED(STATE, CP) \ ( ((CP) >= 14) \ || (! (STATE)->is_XScale) \ || (xscale_cp15_cp_access_allowed(STATE,15,CP))) /* Macro to rotate n right by b bits. */ #define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) /* Macros to store results of instructions. */ #define WRITEDEST(d) \ do \ { \ if (DESTReg == 15) \ WriteR15 (state, d); \ else \ DEST = d; \ } \ while (0) #define WRITESDEST(d) \ do \ { \ if (DESTReg == 15) \ WriteSR15 (state, d); \ else \ { \ DEST = d; \ ARMul_NegZero (state, d); \ } \ } \ while (0) #define WRITEDESTB(d) \ do \ { \ if (DESTReg == 15) \ WriteR15Branch (state, d); \ else \ DEST = d; \ } \ while (0) #define BYTETOBUS(data) ((data & 0xff) | \ ((data & 0xff) << 8) | \ ((data & 0xff) << 16) | \ ((data & 0xff) << 24)) #define BUSTOBYTE(address, data) \ do \ { \ if (state->bigendSig) \ temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \ else \ temp = (data >> ((address & 3) << 3)) & 0xff; \ } \ while (0) #define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb) #define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb) #define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb) #define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb) #define POSBRANCH ((instr & 0x7fffff) << 2) #define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2) /* Values for Emulate. */ #define STOP 0 /* stop */ #define CHANGEMODE 1 /* change mode */ #define ONCE 2 /* execute just one interation */ #define RUN 3 /* continuous execution */ /* Stuff that is shared across modes. */ extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */ extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */ extern char ARMul_BitList[]; /* Number of bits in a byte table. */ #define EVENTLISTSIZE 1024L /* Thumb support. */ typedef enum { t_undefined, /* Undefined Thumb instruction. */ t_decoded, /* Instruction decoded to ARM equivalent. */ t_branch /* Thumb branch (already processed). */ } tdstate; /* Macros to scrutinize instructions. */ #define UNDEF_Test #define UNDEF_Shift #define UNDEF_MSRPC #define UNDEF_MRSPC #define UNDEF_MULPCDest #define UNDEF_MULDestEQOp1 #define UNDEF_LSRBPC #define UNDEF_LSRBaseEQOffWb #define UNDEF_LSRBaseEQDestWb #define UNDEF_LSRPCBaseWb #define UNDEF_LSRPCOffWb #define UNDEF_LSMNoRegs #define UNDEF_LSMPCBase #define UNDEF_LSMUserBankWb #define UNDEF_LSMBaseInListWb #define UNDEF_SWPPC #define UNDEF_CoProHS #define UNDEF_MCRPC #define UNDEF_LSCPCBaseWb #define UNDEF_UndefNotBounced #define UNDEF_ShortInt #define UNDEF_IllegalMode #define UNDEF_Prog32SigChange #define UNDEF_Data32SigChange /* Prototypes for exported functions. */ extern unsigned ARMul_NthReg (ARMword, unsigned); extern int AddOverflow (ARMword, ARMword, ARMword); extern int SubOverflow (ARMword, ARMword, ARMword); extern ARMword ARMul_Emulate26 (ARMul_State *); extern ARMword ARMul_Emulate32 (ARMul_State *); extern unsigned IntPending (ARMul_State *); extern void ARMul_CPSRAltered (ARMul_State *); extern void ARMul_R15Altered (ARMul_State *); extern ARMword ARMul_GetPC (ARMul_State *); extern ARMword ARMul_GetNextPC (ARMul_State *); extern ARMword ARMul_GetR15 (ARMul_State *); extern ARMword ARMul_GetCPSR (ARMul_State *); extern void ARMul_EnvokeEvent (ARMul_State *); extern unsigned int ARMul_Time (ARMul_State *); extern void ARMul_NegZero (ARMul_State *, ARMword); extern void ARMul_SetPC (ARMul_State *, ARMword); extern void ARMul_SetR15 (ARMul_State *, ARMword); extern void ARMul_SetCPSR (ARMul_State *, ARMword); extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword); extern void ARMul_Abort26 (ARMul_State *, ARMword); extern void ARMul_Abort32 (ARMul_State *, ARMword); extern ARMword ARMul_MRC (ARMul_State *, ARMword); extern void ARMul_CDP (ARMul_State *, ARMword); extern void ARMul_LDC (ARMul_State *, ARMword, ARMword); extern void ARMul_STC (ARMul_State *, ARMword, ARMword); extern void ARMul_MCR (ARMul_State *, ARMword, ARMword); extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword); extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword); extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword); extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword); extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword); extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword); extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword); extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); extern void ARMul_ScheduleEvent (ARMul_State *, unsigned int, unsigned (*)(ARMul_State *)); /* Coprocessor support functions. */ extern unsigned ARMul_CoProInit (ARMul_State *); extern void ARMul_CoProExit (ARMul_State *); extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *, ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *, ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *); extern void ARMul_CoProDetach (ARMul_State *, unsigned); extern ARMword read_cp15_reg (unsigned, unsigned, unsigned); extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword); extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword); extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *); extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *); extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword); extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword); extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *); extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword); extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *); extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword); extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword); extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *); extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword); #endif ��������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armos.c������������������������������������������������������������0000644�0001750�0000144�00000040675�10541455476�016536� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* This file contains a model of Demon, ARM Ltd's Debug Monitor, including all the SWI's required to support the C library. The code in it is not really for the faint-hearted (especially the abort handling code), but it is a complete example. Defining NOOS will disable all the fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI 0x11 to halt the emulator. */ //chy 2005-09-12 disable below line //#include "config.h" #include "ansidecl.h" #include <time.h> #include <errno.h> #include <string.h> #include <fcntl.h> #ifndef O_RDONLY #define O_RDONLY 0 #endif #ifndef O_WRONLY #define O_WRONLY 1 #endif #ifndef O_RDWR #define O_RDWR 2 #endif #ifndef O_BINARY #define O_BINARY 0 #endif #ifdef __STDC__ #define unlink(s) remove(s) #endif #ifdef HAVE_UNISTD_H #include <unistd.h> /* For SEEK_SET etc */ #endif #ifdef __riscos extern int _fisatty (FILE *); #define isatty_(f) _fisatty(f) #else #ifdef __ZTC__ #include <io.h> #define isatty_(f) isatty((f)->_file) #else #ifdef macintosh #include <ioctl.h> #define isatty_(f) (~ioctl ((f)->_file, FIOINTERACTIVE, NULL)) #else #define isatty_(f) isatty (fileno (f)) #endif #endif #endif #include "armdefs.h" #include "armos.h" #include "armemu.h" #ifndef NOOS #ifndef VALIDATE /* #ifndef ASIM */ //chy 2005-09-12 disable below line //#include "armfpe.h" /* #endif */ #endif #endif /* For RDIError_BreakpointReached. */ //chy 2005-09-12 disable below line //#include "dbg_rdi.h" extern unsigned ARMul_OSInit (ARMul_State * state); extern void ARMul_OSExit (ARMul_State * state); extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number); extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector, ARMword pc); extern ARMword ARMul_OSLastErrorP (ARMul_State * state); extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr); #define BUFFERSIZE 4096 #ifndef FOPEN_MAX #define FOPEN_MAX 64 #endif #define UNIQUETEMPS 256 /***************************************************************************\ * OS private Information * \***************************************************************************/ struct OSblock { ARMword Time0; ARMword ErrorP; ARMword ErrorNo; FILE *FileTable[FOPEN_MAX]; char FileFlags[FOPEN_MAX]; char *tempnames[UNIQUETEMPS]; }; #define NOOP 0 #define BINARY 1 #define READOP 2 #define WRITEOP 4 #ifdef macintosh #define FIXCRLF(t,c) ((t & BINARY) ? \ c : \ ((c == '\n' || c == '\r' ) ? (c ^ 7) : c) \ ) #else #define FIXCRLF(t,c) c #endif static ARMword softvectorcode[] = { /* basic: swi tidyexception + event; mov pc, lr; ldmia r11,{r11,pc}; swi generateexception + event. */ 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /*Reset */ 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /*Undef */ 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /*SWI */ 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /*Prefetch abort */ 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /*Data abort */ 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /*Address exception */ 0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /*IRQ*/ 0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /*FIQ*/ 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /*Error */ 0xe1a0f00e /* default handler */ }; /***************************************************************************\ * Time for the Operating System to initialise itself. * \***************************************************************************/ unsigned ARMul_OSInit (ARMul_State * state) { #if 0 // ndef NOOS #ifndef VALIDATE ARMword instr, i, j; struct OSblock *OSptr = (struct OSblock *) state->OSptr; if (state->OSptr == NULL) { state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock)); if (state->OSptr == NULL) { perror ("OS Memory"); exit (15); } } OSptr = (struct OSblock *) state->OSptr; OSptr->ErrorP = 0; state->Reg[13] = ADDRSUPERSTACK; /* set up a stack for the current mode */ ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK); /* and for supervisor mode */ ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK); /* and for abort 32 mode */ ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK); /* and for undef 32 mode */ instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* load pc from soft vector */ for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) ARMul_WriteWord (state, i, instr); /* write hardware vectors */ for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4) { ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4); ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L, SOFTVECTORCODE + sizeof (softvectorcode) - 4L); } for (i = 0; i < sizeof (softvectorcode); i += 4) ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]); for (i = 0; i < FOPEN_MAX; i++) OSptr->FileTable[i] = NULL; for (i = 0; i < UNIQUETEMPS; i++) OSptr->tempnames[i] = NULL; ARMul_ConsolePrint (state, ", Demon 1.01"); /* #ifndef ASIM */ /* install fpe */ for (i = 0; i < fpesize; i += 4) /* copy the code */ ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]); for (i = FPESTART + fpesize;; i -= 4) { /* reverse the error strings */ if ((j = ARMul_ReadWord (state, i)) == 0xffffffff) break; if (state->bigendSig && j < 0x80000000) { /* it's part of the string so swap it */ j = ((j >> 0x18) & 0x000000ff) | ((j >> 0x08) & 0x0000ff00) | ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000); ARMul_WriteWord (state, i, j); } } ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, 4)); /* copy old illegal instr vector */ ARMul_WriteWord (state, 4, FPENEWVECT (ARMul_ReadWord (state, i - 4))); /* install new vector */ ARMul_ConsolePrint (state, ", FPE"); /* #endif ASIM */ #endif /* VALIDATE */ #endif /* NOOS */ return (TRUE); } void ARMul_OSExit (ARMul_State * state) { if (state->OSptr) free ((char *) state->OSptr); } /***************************************************************************\ * Return the last Operating System Error. * \***************************************************************************/ ARMword ARMul_OSLastErrorP (ARMul_State * state) { return ((struct OSblock *) state->OSptr)->ErrorP; } static int translate_open_mode[] = { O_RDONLY, /* "r" */ O_RDONLY + O_BINARY, /* "rb" */ O_RDWR, /* "r+" */ O_RDWR + O_BINARY, /* "r+b" */ O_WRONLY + O_CREAT + O_TRUNC, /* "w" */ O_WRONLY + O_BINARY + O_CREAT + O_TRUNC, /* "wb" */ O_RDWR + O_CREAT + O_TRUNC, /* "w+" */ O_RDWR + O_BINARY + O_CREAT + O_TRUNC, /* "w+b" */ O_WRONLY + O_APPEND + O_CREAT, /* "a" */ O_WRONLY + O_BINARY + O_APPEND + O_CREAT, /* "ab" */ O_RDWR + O_APPEND + O_CREAT, /* "a+" */ O_RDWR + O_BINARY + O_APPEND + O_CREAT /* "a+b" */ }; static void SWIWrite0 (ARMul_State * state, ARMword addr) { ARMword temp; struct OSblock *OSptr = (struct OSblock *) state->OSptr; while ((temp = ARMul_ReadByte (state, addr++)) != 0) (void) fputc ((char) temp, stdout); OSptr->ErrorNo = errno; } static void WriteCommandLineTo (ARMul_State * state, ARMword addr) { ARMword temp; char *cptr = state->CommandLine; if (cptr == NULL) cptr = "\0"; do { temp = (ARMword) * cptr++; ARMul_WriteByte (state, addr++, temp); } while (temp != 0); } static void SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags) { struct OSblock *OSptr = (struct OSblock *) state->OSptr; char dummy[2000]; int flags; int i; for (i = 0; (dummy[i] = ARMul_ReadByte (state, name + i)); i++); /* Now we need to decode the Demon open mode */ flags = translate_open_mode[SWIflags]; /* Filename ":tt" is special: it denotes stdin/out */ if (strcmp (dummy, ":tt") == 0) { if (flags == O_RDONLY) /* opening tty "r" */ state->Reg[0] = 0; /* stdin */ else state->Reg[0] = 1; /* stdout */ } else { state->Reg[0] = (int) open (dummy, flags, 0666); OSptr->ErrorNo = errno; } } static void SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len) { struct OSblock *OSptr = (struct OSblock *) state->OSptr; int res; int i; char *local = malloc (len); if (local == NULL) { fprintf (stderr, "sim: Unable to read 0x%ulx bytes - out of memory\n", len); return; } res = read (f, local, len); if (res > 0) for (i = 0; i < res; i++) ARMul_WriteByte (state, ptr + i, local[i]); free (local); state->Reg[0] = res == -1 ? -1 : len - res; OSptr->ErrorNo = errno; } static void SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len) { struct OSblock *OSptr = (struct OSblock *) state->OSptr; int res; ARMword i; char *local = malloc (len); if (local == NULL) { fprintf (stderr, "sim: Unable to write 0x%lx bytes - out of memory\n", (int) len); return; } for (i = 0; i < len; i++) local[i] = ARMul_ReadByte (state, ptr + i); res = write (f, local, len); state->Reg[0] = res == -1 ? -1 : len - res; free (local); OSptr->ErrorNo = errno; } static void SWIflen (ARMul_State * state, ARMword fh) { struct OSblock *OSptr = (struct OSblock *) state->OSptr; ARMword addr; if (fh == 0 || fh > FOPEN_MAX) { OSptr->ErrorNo = EBADF; state->Reg[0] = -1L; return; } addr = lseek (fh, 0, SEEK_CUR); state->Reg[0] = lseek (fh, 0L, SEEK_END); (void) lseek (fh, addr, SEEK_SET); OSptr->ErrorNo = errno; } /***************************************************************************\ * The emulator calls this routine when a SWI instruction is encuntered. The * * parameter passed is the SWI number (lower 24 bits of the instruction). * \***************************************************************************/ unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number) { ARMword addr, temp; struct OSblock *OSptr = (struct OSblock *) state->OSptr; switch (number) { case SWI_Read: SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]); return TRUE; case SWI_Write: SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]); return TRUE; case SWI_Open: SWIopen (state, state->Reg[0], state->Reg[1]); return TRUE; case SWI_Clock: /* return number of centi-seconds... */ state->Reg[0] = #ifdef CLOCKS_PER_SEC (CLOCKS_PER_SEC >= 100) ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100)) : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC); #else /* presume unix... clock() returns microseconds */ (ARMword) (clock () / 10000); #endif OSptr->ErrorNo = errno; return (TRUE); case SWI_Time: state->Reg[0] = (ARMword) time (NULL); OSptr->ErrorNo = errno; return (TRUE); case SWI_Close: state->Reg[0] = close (state->Reg[0]); OSptr->ErrorNo = errno; return TRUE; case SWI_Flen: SWIflen (state, state->Reg[0]); return (TRUE); case SWI_Exit: state->Emulate = FALSE; return TRUE; case SWI_Seek: { /* We must return non-zero for failure */ state->Reg[0] = -1 >= lseek (state->Reg[0], state->Reg[1], SEEK_SET); OSptr->ErrorNo = errno; return TRUE; } case SWI_WriteC: (void) fputc ((int) state->Reg[0], stdout); OSptr->ErrorNo = errno; return (TRUE); case SWI_Write0: SWIWrite0 (state, state->Reg[0]); return (TRUE); case SWI_GetErrno: state->Reg[0] = OSptr->ErrorNo; return (TRUE); case SWI_Breakpoint: //chy 2005-09-12 change below line //state->EndCondition = RDIError_BreakpointReached; //printf ("SKYEYE: in armos.c : should not come here!!!!\n"); state->EndCondition = 0; /*modified by ksh to support breakpoiont*/ state->Emulate = STOP; return (TRUE); case SWI_GetEnv: state->Reg[0] = ADDRCMDLINE; if (state->MemSize) state->Reg[1] = state->MemSize; else state->Reg[1] = ADDRUSERSTACK; WriteCommandLineTo (state, state->Reg[0]); return (TRUE); /* Handle Angel SWIs as well as Demon ones */ case AngelSWI_ARM: case AngelSWI_Thumb: /* R1 is almost always a parameter block */ addr = state->Reg[1]; /* R0 is a reason code */ switch (state->Reg[0]) { /* Unimplemented reason codes */ case AngelSWI_Reason_ReadC: case AngelSWI_Reason_IsTTY: case AngelSWI_Reason_TmpNam: case AngelSWI_Reason_Remove: case AngelSWI_Reason_Rename: case AngelSWI_Reason_System: case AngelSWI_Reason_EnterSVC: default: state->Emulate = FALSE; return (FALSE); case AngelSWI_Reason_Clock: /* return number of centi-seconds... */ state->Reg[0] = #ifdef CLOCKS_PER_SEC (CLOCKS_PER_SEC >= 100) ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100)) : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC); #else /* presume unix... clock() returns microseconds */ (ARMword) (clock () / 10000); #endif OSptr->ErrorNo = errno; return (TRUE); case AngelSWI_Reason_Time: state->Reg[0] = (ARMword) time (NULL); OSptr->ErrorNo = errno; return (TRUE); case AngelSWI_Reason_WriteC: (void) fputc ((int) ARMul_ReadByte (state, addr), stdout); OSptr->ErrorNo = errno; return (TRUE); case AngelSWI_Reason_Write0: SWIWrite0 (state, addr); return (TRUE); case AngelSWI_Reason_Close: state->Reg[0] = close (ARMul_ReadWord (state, addr)); OSptr->ErrorNo = errno; return (TRUE); case AngelSWI_Reason_Seek: state->Reg[0] = -1 >= lseek (ARMul_ReadWord (state, addr), ARMul_ReadWord (state, addr + 4), SEEK_SET); OSptr->ErrorNo = errno; return (TRUE); case AngelSWI_Reason_FLen: SWIflen (state, ARMul_ReadWord (state, addr)); return (TRUE); case AngelSWI_Reason_GetCmdLine: WriteCommandLineTo (state, ARMul_ReadWord (state, addr)); return (TRUE); case AngelSWI_Reason_HeapInfo: /* R1 is a pointer to a pointer */ addr = ARMul_ReadWord (state, addr); /* Pick up the right memory limit */ if (state->MemSize) temp = state->MemSize; else temp = ADDRUSERSTACK; ARMul_WriteWord (state, addr, 0); /* Heap base */ ARMul_WriteWord (state, addr + 4, temp); /* Heap limit */ ARMul_WriteWord (state, addr + 8, temp); /* Stack base */ ARMul_WriteWord (state, addr + 12, temp); /* Stack limit */ return (TRUE); case AngelSWI_Reason_ReportException: if (state->Reg[1] == ADP_Stopped_ApplicationExit) state->Reg[0] = 0; else state->Reg[0] = -1; state->Emulate = FALSE; return TRUE; case ADP_Stopped_ApplicationExit: state->Reg[0] = 0; state->Emulate = FALSE; return (TRUE); case ADP_Stopped_RunTimeError: state->Reg[0] = -1; state->Emulate = FALSE; return (TRUE); case AngelSWI_Reason_Errno: state->Reg[0] = OSptr->ErrorNo; return (TRUE); case AngelSWI_Reason_Open: SWIopen (state, ARMul_ReadWord (state, addr), ARMul_ReadWord (state, addr + 4)); return TRUE; case AngelSWI_Reason_Read: SWIread (state, ARMul_ReadWord (state, addr), ARMul_ReadWord (state, addr + 4), ARMul_ReadWord (state, addr + 8)); return TRUE; case AngelSWI_Reason_Write: SWIwrite (state, ARMul_ReadWord (state, addr), ARMul_ReadWord (state, addr + 4), ARMul_ReadWord (state, addr + 8)); return TRUE; } default: #if 0 state->Emulate = FALSE; #endif return (FALSE); } } #ifndef NOOS #ifndef ASIM /***************************************************************************\ * The emulator calls this routine when an Exception occurs. The second * * parameter is the address of the relevant exception vector. Returning * * FALSE from this routine causes the trap to be taken, TRUE causes it to * * be ignored (so set state->Emulate to FALSE!). * \***************************************************************************/ unsigned ARMul_OSException (ARMul_State * state ATTRIBUTE_UNUSED, ARMword vector ATTRIBUTE_UNUSED, ARMword pc ATTRIBUTE_UNUSED) { /* don't use this here */ return (FALSE); } #endif #endif /* NOOS */ �������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/arm_arch_interface.c�����������������������������������������������0000644�0001750�0000144�00000030345�11006337710�021165� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include "armdefs.h" #include "skyeye_types.h" #include "armemu.h" ARMul_State *state; static int verbosity; extern int big_endian; static int mem_size = (1 << 21); static mem_config_t arm_mem; static cpu_config_t *p_arm_cpu; static ARMword preset_regfile[16]; extern ARMword skyeye_cachetype; //chy 2005-08-01, borrow from wlm's 2005-07-26's change ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr) { } void ARMul_ConsolePrint (ARMul_State * state, const char *format, ...) { } void ARMul_CallCheck (ARMul_State * state, ARMword cur_pc, ARMword to_pc, ARMword instr) { } static void base_termios_exit (void) { //koodailar remove it for mingw 2005.12.18-------------------------------------- #ifndef __MINGW32__ //tcsetattr (STDIN_FILENO, TCSANOW, &(state->base_termios)); #endif //end -------------------------------------------------------------------------- } static void arm_reset_state () { //chy 2003-01-14 seems another ARMul_Reset, the first is in ARMul_NewState //chy 2003-08-19 mach_init should call ARMul_SelectProcess //skyeye_config.mach->mach_init (state, skyeye_config.mach); //chy:2003-08-19, after mach_init, because ARMul_Reset should after ARMul_SelectProcess ARMul_Reset (state); state->NextInstr = 0; state->Emulate = 3; // add step disassemble code here :teawater state->disassemble = skyeye_config.can_step_disassemble; io_reset (state); /*from ARMul_Reset. */ /* set some register value */ if(preset_regfile[1]) state->Reg[1] = preset_regfile[1]; } static void arm_init_state () { ARMul_EmulateInit (); state = ARMul_NewState (); state->cpu = p_arm_cpu; state->mem_bank = &arm_mem; //chy 2005-08-01, borrow from wlm's 2005-07-26's change /* * 2007-01-24 removed the term-io functions by Anthony Lee, * moved to "device/uart/skyeye_uart_stdio.c". */ //it will be set in skyeye_config.mach->mach_init(state, skyeye_config.mach); state->abort_model = 0; //chy 2005-08-01 --------------------------------------------- state->bigendSig = (big_endian ? HIGH : LOW); ARMul_MemoryInit (state, mem_size); ARMul_OSInit (state); state->verbose = verbosity; /*some option should init before read config. e.g. uart option. */ //chy 2005-08-01 --------------------------------------------- // skyeye_option_init (&skyeye_config); // skyeye_read_config (); //chy 2005-08-01 commit and disable ksh's energy estimantion, will be recover in the future /*added by ksh for energy estimation,in 2004-11-26 */ state->energy.energy_prof = skyeye_config.energy.energy_prof; /*mach init */ skyeye_config.mach->mach_init (state, skyeye_config.mach); } static void arm_step_once () { //ARMul_DoInstr(state); state->NextInstr = RESUME; /* treat as PC change */ state->Reg[15] = ARMul_DoProg(state); FLUSHPIPE; } static void arm_set_pc (WORD pc) { state->Reg[15] = pc; } static WORD arm_get_pc(){ return (WORD)state->Reg[15]; } static int arm_ICE_write_byte (WORD addr, uint8_t v) { return (ARMul_ICE_WriteByte (state, (ARMword) addr, (ARMword) v)); } static int arm_ICE_read_byte (WORD addr, uint8_t *pv){ ARMword data; int ret; ret = ARMul_ICE_ReadByte (state, (ARMword) addr, &data); *pv = (uint8_t)data ; return (ret); } extern void at91_mach_init (); extern void ep7312_mach_init (); extern void lh79520_mach_init (); extern void ep9312_mach_init (); extern void s3c4510b_mach_init (); extern void s3c44b0x_mach_init (); extern void s3c3410x_mach_init (); extern void sa1100_mach_init (); extern void pxa250_mach_init (); extern void pxa270_mach_init (); extern void cs89712_mach_init (); extern void at91rm92_mach_init (); extern void s3c2410x_mach_init (); extern void s3c2440_mach_init (); extern void shp_mach_init (); extern void lpc_mach_init (); extern void ns9750_mach_init (); extern void lpc2210_mach_init(); extern void ps7500_mach_init(); extern void imx_mach_init(); extern void integrator_mach_init(); //chy 2003-08-11: the cpu_id can be found in linux/arch/arm/boot/compressed/head.S cpu_config_t arm_cpus[] = { {"armv3", "arm710", 0x41007100, 0xfff8ff00, DATACACHE}, {"armv3", "arm7tdmi", 0x41007700, 0xfff8ff00, NONCACHE}, {"armv4", "arm720t", 0x41807200, 0xffffff00, DATACACHE}, {"armv4", "sa1110", SA1110, 0xfffffff0, INSTCACHE}, {"armv4", "sa1100", SA1100, 0xffffffe0, INSTCACHE}, {"armv4", "arm920t", 0x41009200, 0xff00fff0, INSTCACHE}, {"armv5", "arm926ejs", 0x41069260, 0xff0ffff0, INSTCACHE}, {"xscale", "pxa25x", PXA250, 0xfffffff0, INSTCACHE}, {"xscale", "pxa27x", PXA270, 0xfffffff0, INSTCACHE}, {"armv6", "arm11", NULL,0x0,NULL} }; static int arm_parse_cpu (const char *params[]) { int i; for (i = 0; i < (sizeof (arm_cpus) / sizeof (cpu_config_t)); i++) { if (!strncmp (params[0], arm_cpus[i].cpu_name, MAX_PARAM_NAME)) { p_arm_cpu = &arm_cpus[i]; SKYEYE_INFO ("cpu info: %s, %s, %x, %x, %x \n", p_arm_cpu->cpu_arch_name, p_arm_cpu->cpu_name, p_arm_cpu->cpu_val, p_arm_cpu->cpu_mask, p_arm_cpu->cachetype); skyeye_cachetype = p_arm_cpu->cachetype; return 0; } } SKYEYE_ERR ("Error: Unkonw cpu name \"%s\"\n", params[0]); return -1; } machine_config_t arm_machines[] = { /* machine define for cpu without mmu */ {"at91", at91_mach_init, NULL, NULL, NULL}, /* ATMEL AT91X40 */ {"lpc", lpc_mach_init, NULL, NULL, NULL}, /* PHILIPS LPC2xxxx */ {"s3c4510b", s3c4510b_mach_init, NULL, NULL, NULL}, /* Samsung s3c4510b */ {"s3c44b0x", s3c44b0x_mach_init, NULL, NULL, NULL}, /* Samsung s3c44b0x */ {"s3c44b0", s3c44b0x_mach_init, NULL, NULL, NULL}, /* Samsung s3c44b0x */ {"s3c3410x", s3c3410x_mach_init, NULL, NULL, NULL}, /* Samsung s3c3410x */ /* machine define for cpu with mmu */ {"ep7312", ep7312_mach_init, NULL, NULL, NULL}, /* Cirrus Logic EP7312 */ {"lh79520", lh79520_mach_init, NULL, NULL, NULL}, /* sharp LH79520 */ {"ep9312", ep9312_mach_init, NULL, NULL, NULL}, /* Cirrus Logic EP9312 */ {"cs89712", cs89712_mach_init, NULL, NULL, NULL}, /* cs89712 */ {"sa1100", sa1100_mach_init, NULL, NULL, NULL}, /* sa1100 */ {"pxa_lubbock", pxa250_mach_init, NULL, NULL, NULL}, /* xscale pxa250 lubbock developboard */ {"pxa_mainstone", pxa270_mach_init, NULL, NULL, NULL}, /* xscale pxa270 mainstone developboard */ {"at91rm92", at91rm92_mach_init, NULL, NULL, NULL}, /* at91RM9200 */ {"s3c2410x", s3c2410x_mach_init, NULL, NULL, NULL}, /* s3c2410x */ {"s3c2440", s3c2440_mach_init, NULL, NULL, NULL}, /* s3c2440 */ {"sharp_lh7a400", shp_mach_init, NULL, NULL, NULL}, /* sharp lh7a400 developboard */ {"ns9750", ns9750_mach_init, NULL, NULL, NULL}, /* NetSilicon ns9750 */ {"lpc2210", lpc2210_mach_init, NULL, NULL, NULL}, /* Philips LPC2210 */ {"ps7500", ps7500_mach_init, NULL, NULL, NULL}, /* Cirrus Logic PS7500FE */ }; static int arm_parse_mach (machine_config_t * mach, const char *params[]) { int i; for (i = 0; i < (sizeof (arm_machines) / sizeof (machine_config_t)); i++) { if (!strncmp (params[0], arm_machines[i].machine_name, MAX_PARAM_NAME)) { skyeye_config.mach = &arm_machines[i]; SKYEYE_INFO ("mach info: name %s, mach_init addr %p\n", skyeye_config.mach->machine_name, skyeye_config.mach->mach_init); return 0; } } SKYEYE_ERR ("Error: Unkonw mach name \"%s\"\n", params[0]); return -1; } /*mem bank*/ extern ARMword real_read_word (ARMul_State * state, ARMword addr); extern void real_write_word (ARMul_State * state, ARMword addr, ARMword data); extern ARMword io_read_word (ARMul_State * state, ARMword addr); extern void io_write_word (ARMul_State * state, ARMword addr, ARMword data); /*ywc 2005-03-30*/ extern ARMword flash_read_byte (ARMul_State * state, ARMword addr); extern void flash_write_byte (ARMul_State * state, ARMword addr, ARMword data); extern ARMword flash_read_halfword (ARMul_State * state, ARMword addr); extern void flash_write_halfword (ARMul_State * state, ARMword addr, ARMword data); extern ARMword flash_read_word (ARMul_State * state, ARMword addr); extern void flash_write_word (ARMul_State * state, ARMword addr, ARMword data); static int arm_parse_mem (int num_params, const char *params[]) { char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, num; //chy 2003-09-12, now support more io bank // static int io_bank_num=0; //state->mem_bank = (mem_config_t *)malloc(sizeof(mem_config_t)); mem_config_t *mc = &arm_mem; mem_bank_t *mb = mc->mem_banks; mc->bank_num = mc->current_num++; num = mc->current_num - 1; /*mem_banks should begin from 0. */ mb[num].filename[0] = '\0'; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0) SKYEYE_ERR ("Error: mem_bank %d has wrong parameter \"%s\".\n", num, name); if (!strncmp ("map", name, strlen (name))) { if (!strncmp ("M", value, strlen (value))) { mb[num].read_byte = real_read_byte; mb[num].write_byte = real_write_byte; mb[num].read_halfword = real_read_halfword; mb[num].write_halfword = real_write_halfword; mb[num].read_word = real_read_word; mb[num].write_word = real_write_word; mb[num].type = MEMTYPE_RAM; } else if (!strncmp ("I", value, strlen (value))) { mb[num].read_byte = io_read_byte; mb[num].write_byte = io_write_byte; mb[num].read_halfword = io_read_halfword; mb[num].write_halfword = io_write_halfword; mb[num].read_word = io_read_word; mb[num].write_word = io_write_word; mb[num].type = MEMTYPE_IO; /*ywc 2005-03-30 */ } else if (!strncmp ("F", value, strlen (value))) { mb[num].read_byte = flash_read_byte; mb[num].write_byte = flash_write_byte; mb[num].read_halfword = flash_read_halfword; mb[num].write_halfword = flash_write_halfword; mb[num].read_word = flash_read_word; mb[num].write_word = flash_write_word; mb[num].type = MEMTYPE_FLASH; } else { SKYEYE_ERR ("Error: mem_bank %d \"%s\" parameter has wrong value \"%s\"\n", num, name, value); } } else if (!strncmp ("type", name, strlen (name))) { //chy 2003-09-21: process type if (!strncmp ("R", value, strlen (value))) { if (mb[num].type == MEMTYPE_RAM) mb[num].type = MEMTYPE_ROM; mb[num].write_byte = warn_write_byte; mb[num].write_halfword = warn_write_halfword; mb[num].write_word = warn_write_word; } } else if (!strncmp ("addr", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].addr = strtoul (value, NULL, 16); else mb[num].addr = strtoul (value, NULL, 10); } else if (!strncmp ("size", name, strlen (name))) { if (value[0] == '0' && value[1] == 'x') mb[num].len = strtoul (value, NULL, 16); else mb[num].len = strtoul (value, NULL, 10); } else if (!strncmp ("file", name, strlen (name))) { strncpy (mb[num].filename, value, strlen (value) + 1); } else if (!strncmp ("boot", name, strlen (name))) { /*this must be the last parameter. */ if (!strncmp ("yes", value, strlen (value))) skyeye_config.start_address = mb[num].addr; } else { SKYEYE_ERR ("Error: mem_bank %d has unknow parameter \"%s\".\n", num, name); } } return 0; } static int arm_parse_regfile (int num_params, const char *params[]){ char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME]; int i, num; int reg_value; for (i = 0; i < num_params; i++) { if (split_param (params[i], name, value) < 0){ SKYEYE_ERR ("Error: mem_bank %d has wrong parameter \"%s\".\n", num, name); } else if (!strncmp ("r1", name, strlen (name))) { //chy 2003-09-21: process type if (value[0] == '0' && value[1] == 'x') reg_value = strtoul (value, NULL, 16); else reg_value = strtoul (value, NULL, 10); preset_regfile[1] = reg_value; SKYEYE_INFO("R1 is set to %d.\n", reg_value); } else { SKYEYE_ERR ("Error: regfile %d has unknow parameter \"%s\".\n", num, name); } } return 0; } void init_arm_arch () { static arch_config_t arm_arch; arm_arch.arch_name = "arm"; arm_arch.init = arm_init_state; arm_arch.reset = arm_reset_state; arm_arch.set_pc = arm_set_pc; arm_arch.get_pc = arm_get_pc; arm_arch.step_once = arm_step_once; arm_arch.ICE_write_byte = arm_ICE_write_byte; arm_arch.ICE_read_byte = arm_ICE_read_byte; arm_arch.parse_cpu = arm_parse_cpu; arm_arch.parse_mach = arm_parse_mach; arm_arch.parse_mem = arm_parse_mem; arm_arch.parse_regfile = arm_parse_regfile; register_arch (&arm_arch); } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armengr.c����������������������������������������������������������0000644�0001750�0000144�00000017307�10541455476�017044� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armengr.c -- Main instruction emulation: SA11x Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. Modifications to add arch. v4 support by <jsmith@cygnus.com>. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "armdefs.h" #include "armemu.h" #include "armsym.h" /***************************************************************************\ * ARM Energy * \***************************************************************************/ /* Instruction current in mA */ static long long instr_current[256] = { 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 180, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 230, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170 }; //#define CLK_FREQ 206.0 //#define VDD 1.5 //static float mutilplier = 0; //#define INSTR_ENERGY(i) instr_current[i]*VDD/CLK_FREQ /* in nJ per cycle */ //#define INSTR_ENERGY(i) instr_current[i]*mutilplier // BUG200202071648: more accurate energy accounting #define MEM_ENERGY 400 // tried to calculate for 4.7nJ #define MEM_IDLE_ENERGY 40 // tried to calculate for 0.4nJ #define IDLE_ENERGY 30 #define UART_ENERGY 40 /*added by ksh in 2004-09-03,according to PXA250 Developer Manual*/ /********************************************* The following is the bitmap of CCCR,you can find it on the manual [31:10] reserved [9:7] N [6:5] M [4:0] L *************************************************/ float Calculate_Mutilplier (ARMul_State * state) { float Crystal_freq = 3.6864; int L, M; float N; float Core_freq; float Vdd; unsigned int cccr = state->energy.cccr; // printf("before calculate:cccr=0x%x,cccr&0x0=0x%x \n",cccr,cccr&0x0); switch ((cccr >> 7) & 0x7) { case 2: N = 1; break; case 3: N = 1.5; break; case 4: N = 2; break; case 6: N = 3; break; default: printf ("N is wrong\n "); N = 1; break; } //printf("before calculate:cccr=0x%x,cccr&0x0=0x%x \n",cccr,cccr&0x0); switch ((cccr >> 5) & 0x3) { case 1: M = 1; break; case 2: M = 2; break; default: printf ("M is wrong\n"); M = 1; break; } switch (cccr & 0x1f) { case 1: L = 27; break; case 2: L = 32; break; case 3: L = 36; break; case 4: L = 40; break; case 5: L = 45; break; default: printf ("L is wrong!\n"); L = 1; break; } Core_freq = L * M * N * Crystal_freq; // printf("L=%d,M=%d,N=%llf,Core_freq=%f",L,M,N,Core_freq); if (Core_freq < 100) { Vdd = 0.85; } else if (100 < Core_freq < 200) { Vdd = 1.0; } else if (200 < Core_freq < 300) { Vdd = 1.1; } else if (300 < Core_freq < 400) { Vdd = 1.3; } else { printf ("Core_freq is %f,exceed!\n", Core_freq); skyeye_exit (-1); } //printf("cccr=0x%x,L=%d,M=%d,N=%d,Vdd = %d,Core_freq=%d,cccr>>7&0x7=0x%x,cccr>>7=0x%x,cccr&0x380=0x%x,cccr&0x0=0x%x,cccr&0x1f=0x%x\n",cccr,L,M,N,Vdd,Core_freq,(cccr>>7)&0x7,cccr>>7,cccr&0x380,cccr&0x0,cccr&0x1f); //printf("before calculate 5:cccr=0x%x,cccr&0x380=0x%x,cccr&0x0=0x%x \n",cccr,cccr&0x380,cccr&0x0); // printf("Vdd=%f,Core_freq=%f\n",Vdd,Core_freq); return Vdd / Core_freq; } /*get Vdd,added by ksh in 2004-09-03*/ float get_Vdd (float Core_freq) { if (Core_freq < 100) { return 0.85; } if (Core_freq < 200) { return 1.0; } if (Core_freq < 300) { return 1.1; } if (Core_freq < 400) { return 1.3; } else { return 0.0; } } static long long pf_p_cyc, pf_p_energy; static int check_point = 0; void ARMul_EnergyInit (ARMul_State * state) { printf ("call ARMul_EnergyInit() \n"); state->energy.t_energy = 0; state->energy.tcycle = 0; state->energy.pcycle = 0; state->energy.t_mem_cycle = 0; state->energy.t_idle_cycle = 0; state->energy.t_uart_cycle = 0; state->energy.p_mem_cycle = 0; state->energy.p_idle_cycle = 0; state->energy.p_uart_cycle = 0; state->energy.p_io_update_tcycle = 0; pf_p_cyc = 0; pf_p_energy = 0; check_point = 1; return; } void ARMul_do_energy (ARMul_State * state, ARMword instr, ARMword pc) { int opcode; long long ex_cycle, timing_cycle; long long mem_cycle, idle_cycle, uart_cycle, mem_idle_cycle; float ex_energy; float mem_energy, idle_energy, uart_energy, mem_idle_energy; float cur_cyc_energy; TASK_STACK *tsp; if (!state->energy.energy_prof) { return; } if (check_point == 0) { printf ("failed check point\n"); skyeye_exit (-1); } if (state->energy.energy_prof) { // BUG200103282109 state->energy.tcycle = state->NumScycles + state->NumNcycles + state->NumIcycles; ex_cycle = state->energy.tcycle - state->energy.pcycle; mem_cycle = state->energy.t_mem_cycle - state->energy.p_mem_cycle; idle_cycle = state->energy.t_idle_cycle - state->energy.p_idle_cycle; uart_cycle = state->energy.t_uart_cycle - state->energy.p_uart_cycle; mem_idle_cycle = ex_cycle - mem_cycle; state->energy.pcycle = state->energy.tcycle; state->energy.p_mem_cycle = state->energy.t_mem_cycle; state->energy.p_idle_cycle = state->energy.t_idle_cycle; state->energy.p_uart_cycle = state->energy.t_uart_cycle; opcode = BITS (20, 27); /*added by ksh for calculate freq and vdd */ ex_energy = instr_current[opcode] * ex_cycle * Calculate_Mutilplier (state); /* <tktan> BUG200105232215 */ mem_energy = mem_cycle * MEM_ENERGY; idle_energy = idle_cycle * IDLE_ENERGY; uart_energy = uart_cycle * UART_ENERGY; mem_idle_energy = mem_idle_cycle * MEM_IDLE_ENERGY; cur_cyc_energy = ex_energy + mem_energy + idle_energy + uart_energy + mem_idle_energy; state->energy.t_energy += cur_cyc_energy; /*task energy profiling */ tsp = (TASK_STACK *) state->energy.cur_task; tsp->total_cycle += ex_cycle; tsp->total_energy += cur_cyc_energy; if (state->NextInstr >= PRIMEPIPE) { ARMul_CallCheck (state, pc, state->Reg[15], instr); /* BUG200104012116 */ } } //add by chy 2004-11-27 bug?? return; } /* void ARMul_do_cycle(ARMul_State *state) { do { io_do_cycle(state); } while (state->mmu.mode != RUN_MODE) ; }*/ �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armmmu.h�����������������������������������������������������������0000644�0001750�0000144�00000014002�10541455476�016701� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armmmu.c - Memory Management Unit emulation. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ARMMMU_H_ #define _ARMMMU_H_ #define WORD_SHT 2 #define WORD_SIZE (1<<WORD_SHT) /* The MMU is accessible with MCR and MRC operations to copro 15: */ #define MMU_COPRO (15) /* Register numbers in the MMU: */ typedef enum mmu_regnum_t { MMU_ID = 0, MMU_CONTROL = 1, MMU_TRANSLATION_TABLE_BASE = 2, MMU_DOMAIN_ACCESS_CONTROL = 3, MMU_FAULT_STATUS = 5, MMU_FAULT_ADDRESS = 6, MMU_CACHE_OPS = 7, MMU_TLB_OPS = 8, MMU_CACHE_LOCKDOWN = 9, MMU_TLB_LOCKDOWN = 10, MMU_PID = 13, /*MMU_V4 */ MMU_V4_CACHE_OPS = 7, MMU_V4_TLB_OPS = 8, /*MMU_V3 */ MMU_V3_FLUSH_TLB = 5, MMU_V3_FLUSH_TLB_ENTRY = 6, MMU_V3_FLUSH_CACHE = 7, /*MMU Intel SA-1100 */ MMU_SA_RB_OPS = 9, MMU_SA_DEBUG = 14, MMU_SA_CP15_R15 = 15, //chy 2003-08-24 /*Intel xscale CP15 */ XSCALE_CP15_CACHE_TYPE = 0, XSCALE_CP15_AUX_CONTROL = 1, XSCALE_CP15_COPRO_ACCESS = 15, } mmu_regnum_t; /* Bits in the control register */ #define CONTROL_MMU (1<<0) #define CONTROL_ALIGN_FAULT (1<<1) #define CONTROL_CACHE (1<<2) #define CONTROL_DATA_CACHE (1<<2) #define CONTROL_WRITE_BUFFER (1<<3) #define CONTROL_BIG_ENDIAN (1<<7) #define CONTROL_SYSTEM (1<<8) #define CONTROL_ROM (1<<9) #define CONTROL_UNDEFINED (1<<10) #define CONTROL_BRANCH_PREDICT (1<<11) #define CONTROL_INSTRUCTION_CACHE (1<<12) #define CONTROL_VECTOR (1<<13) #define CONTROL_RR (1<<14) #define CONTROL_L4 (1<<15) /*Macro defines for MMU state*/ #define MMU_CTL (state->mmu.control) #define MMU_Enabled (state->mmu.control & CONTROL_MMU) #define MMU_Disabled (!(MMU_Enabled)) #define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT) #define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE) #define MMU_ICacheDisabled (!(MMU_ICacheDisabled)) #define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE) #define MMU_DCacheDisabled (!(MMU_DCacheEnabled)) #define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE) #define MMU_CacheDisabled (!(MMU_CacheEnabled)) #define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER) #define MMU_WBDisabled (!(MMU_WBEnabled)) /*virt_addr exchange according to CP15.R13(process id virtul mapping)*/ #define PID_VA_MAP_MASK 0xfe000000 #define mmu_pid_va_map(va) ({\ ARMword ret; \ if ((va) & PID_VA_MAP_MASK)\ ret = (va); \ else \ ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\ ret;\ }) /* FS[3:0] in the fault status register: */ typedef enum fault_t { NO_FAULT = 0x0, ALIGNMENT_FAULT = 0x1, SECTION_TRANSLATION_FAULT = 0x5, PAGE_TRANSLATION_FAULT = 0x7, SECTION_DOMAIN_FAULT = 0x9, PAGE_DOMAIN_FAULT = 0xB, SECTION_PERMISSION_FAULT = 0xD, SUBPAGE_PERMISSION_FAULT = 0xF, } fault_t; typedef struct mmu_ops_s { /*initilization */ int (*init) (ARMul_State * state); /*free on exit */ void (*exit) (ARMul_State * state); /*read byte data */ fault_t (*read_byte) (ARMul_State * state, ARMword va, ARMword * data); /*write byte data */ fault_t (*write_byte) (ARMul_State * state, ARMword va, ARMword data); /*read halfword data */ fault_t (*read_halfword) (ARMul_State * state, ARMword va, ARMword * data); /*write halfword data */ fault_t (*write_halfword) (ARMul_State * state, ARMword va, ARMword data); /*read word data */ fault_t (*read_word) (ARMul_State * state, ARMword va, ARMword * data); /*write word data */ fault_t (*write_word) (ARMul_State * state, ARMword va, ARMword data); /*load instr */ fault_t (*load_instr) (ARMul_State * state, ARMword va, ARMword * instr); /*mcr */ ARMword (*mcr) (ARMul_State * state, ARMword instr, ARMword val); /*mrc */ ARMword (*mrc) (ARMul_State * state, ARMword instr, ARMword * val); /*ywc 2005-04-16 convert virtual address to physics address */ int (*v2p_dbct) (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr); } mmu_ops_t; #include "mmu/tlb.h" #include "mmu/rb.h" #include "mmu/wb.h" #include "mmu/cache.h" /*special process mmu.h*/ #include "mmu/sa_mmu.h" #include "mmu/arm7100_mmu.h" #include "mmu/arm920t_mmu.h" #include "mmu/arm926ejs_mmu.h" typedef struct mmu_state_t { ARMword control; ARMword translation_table_base; ARMword domain_access_control; ARMword fault_status; ARMword fault_address; ARMword last_domain; ARMword process_id; ARMword cache_locked_down; ARMword tlb_locked_down; //chy 2003-08-24 for xscale ARMword cache_type; // 0 ARMword aux_control; // 1 ARMword copro_access; // 15 mmu_ops_t ops; union { sa_mmu_t sa_mmu; arm7100_mmu_t arm7100_mmu; arm920t_mmu_t arm920t_mmu; arm926ejs_mmu_t arm926ejs_mmu; } u; } mmu_state_t; int mmu_init (ARMul_State * state); int mmu_reset (ARMul_State * state); void mmu_exit (ARMul_State * state); fault_t mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data); fault_t mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data); fault_t mmu_load_instr (ARMul_State * state, ARMword virt_addr, ARMword * instr); ARMword mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value); void mmu_mcr (ARMul_State * state, ARMword instr, ARMword value); /*ywc 20050416*/ int mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr); #endif /* _ARMMMU_H_ */ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/common/armmem.c�����������������������������������������������������������0000644�0001750�0000144�00000044214�11006365156�016654� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* armmem.c - Memory map decoding, ROM and RAM emulation. ARMulator extensions for the ARM7100 family. Copyright (C) 1999 Ben Williamson Changes to support running uClinux/Atmel AT91 targets Copyright (C) 2002 David McCullough <davidm@snapgear.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "armdefs.h" #include "code_cov.h" /*ywc 2005-03-30*/ #include "skyeye_flash.h" //chy 2004-03-11 extern void lcd_write (ARMul_State * state, ARMword addr, ARMword data); void mem_reset (ARMul_State * state) { int i, num, bank; FILE *f; unsigned char *p; int s; ARMword swap; mem_config_t *mc = state->mem_bank; mem_bank_t *mb = mc->mem_banks; num = mc->current_num; for (i = 0; i < num; i++) { bank = i; if (state->mem.rom[bank]) free (state->mem.rom[bank]); //chy 2003-09-21: if mem type =MEMTYPE_IO, we need not malloc space for it. state->mem.rom_size[bank] = mb[bank].len; if (mb[bank].type != MEMTYPE_IO) { state->mem.rom[bank] = malloc (mb[bank].len); if (!state->mem.rom[bank]) { fprintf (stderr, "SKYEYE: mem_reset: Error allocating mem for bank number %d.\n", bank); skyeye_exit (-1); } /*ywc 2005-04-01 */ #ifdef DBCT if (!skyeye_config.no_dbct) { //teawater add for arm2x86 2004.12.04------------------------------------------- if (mb[bank].len % TB_LEN) { fprintf (stderr, "SKYEYE: mem_reset: Bank number %d length error.\n", bank); skyeye_exit (-1); } state->mem.tbp[bank] = MAP_FAILED; state->mem.tbt[bank] = NULL; /* state->mem.tbp[bank] = mmap(NULL, mb[bank].len / sizeof(ARMword) * TB_INSN_LEN_MAX + mb[bank].len / TB_LEN * op_return.len, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0); if (state->mem.tbp[bank] == MAP_FAILED) { fprintf(stderr, "SKYEYE: mem_reset: Error allocating mem for bank number %d.\n", bank); exit(-1); } state->mem.tbt[bank] = malloc(mb[bank].len/TB_LEN*sizeof(tb_t)); if (!state->mem.tbt[bank]) { fprintf(stderr, "SKYEYE: mem_reset: Error allocating mem for bank number %d.\n", bank); exit(-1); } memset(state->mem.tbt[bank], 0, mb[bank].len/TB_LEN*sizeof(tb_t)); */ //AJ2D-------------------------------------------------------------------------- } #endif if (mb[bank].filename && (f = fopen (mb[bank].filename, "rb"))) { if (fread (state->mem.rom[bank], 1, mb[bank].len, f) <= 0) { perror ("fread"); fprintf (stderr, "Failed to load '%s'\n", mb[bank].filename); skyeye_exit (-1); } fclose (f); p = (char *) state->mem.rom[bank]; s = 0; while (s < state->mem.rom_size[bank]) { if (state->bigendSig == HIGH) /*big enddian? */ swap = ((ARMword) p[3]) | (((ARMword) p[2]) << 8) | (((ARMword) p[1]) << 16) | (((ARMword) p[0]) << 24); else swap = ((ARMword) p[0]) | (((ARMword) p[1]) << 8) | (((ARMword) p[2]) << 16) | (((ARMword) p[3]) << 24); *(ARMword *) p = swap; p += 4; s += 4; } /*ywc 2004-03-30 */ //printf("Loaded ROM %s\n", mb[bank].filename); if (mb[bank].type == MEMTYPE_FLASH) { printf ("Loaded FLASH %s\n", mb[bank].filename); } else if (mb[bank].type == MEMTYPE_RAM) { printf ("Loaded RAM %s\n", mb[bank].filename); } else if (mb[bank].type == MEMTYPE_ROM) { printf ("Loaded ROM %s\n", mb[bank].filename); } } else if (mb[bank].filename[0] != '\0') { perror (mb[bank].filename); fprintf (stderr, "bank %d, Couldn't open boot ROM %s - execution will " "commence with the debuger.\n", bank, mb[bank].filename); skyeye_exit (-1); } } } /*end for(i = 0;i < num; i++) */ } extern ARMul_State *state; // chy: can improve speed !!!! ???? // ywc 2005-04-22: Yes,teawater's code improve the speed, so I open it again. mem_bank_t * bank_ptr (ARMword addr) { // chy 2005-01-06 add teawater's codes for speed,but I tested it, can not find the big improve // chy 2005-01-06 maybe some one examines below. now I commit teatwater's codes //mem_bank_t *mbp; //---------teawater add for arm2ia32 2004.12.04----------------- //mem_bank_t *mbp; static mem_bank_t *mbp = NULL; if (mbp) { if (mbp->addr <= addr && (addr - mbp->addr) < mbp->len) return (mbp); } //AJ2D---------------------------------------------------------- for (mbp = state->mem_bank->mem_banks; mbp->len; mbp++) if (mbp->addr <= addr && (addr - mbp->addr) < mbp->len) return (mbp); return (NULL); } /*ywc 2005-04-22 , called by dbct/tb.c tb_find FUNCTION */ mem_bank_t * insn_bank_ptr (ARMword addr) { static mem_bank_t *mbp = NULL; if (mbp) { if (mbp->addr <= addr && (addr - mbp->addr) < mbp->len) return (mbp); } for (mbp = state->mem_bank->mem_banks; mbp->len; mbp++) if (mbp->addr <= addr && (addr - mbp->addr) < mbp->len) return (mbp); return (NULL); } /* ywc 2005-04-22, in order to reduce the bank_ptr call times, use a global variable to * store the bank_ptr result in mem_read/write_byte/halfword/word. The coresponding * real_read/write_byte/halfword/word just use the result directly, no need to call * bank_ptr again. */ mem_bank_t *global_mbp; ARMword mem_read_byte (ARMul_State * state, ARMword addr) { /* if addr is remaped to another place */ if (state->vector_remap_flag && (addr <= 0x0 + state->vector_remap_size)) /* Fixme:we only think the start addr of interrupt vector is 0x0, not think 0xffff0000 */ { addr += state->vector_remap_addr; /* support some remap function in LPC processor */ printf("KSDBG: remap read addr=0x%x\n", addr); } global_mbp = bank_ptr (addr); if (global_mbp && global_mbp->read_byte) //return mbp->read_byte(state, addr); return global_mbp->read_byte (state, addr); else { //fprintf(stderr, "SKYEYE:NumInstrs %llu, mem_read_byte addr = %x no bank\n",state->NumInstrs, addr); //chy 2003-09-03 //SKYEYE_OUTREGS(stderr); //exit(-1); return 0; } } ARMword mem_read_halfword (ARMul_State * state, ARMword addr) { /* if addr is remaped to another place */ if (state->vector_remap_flag && (addr <= 0x0 + state->vector_remap_size)) /* Fixme:we only think the start addr of interrupt vector is 0x0, not think 0xffff0000 */ { addr += state->vector_remap_addr; /* support some remap function in LPC processor */ // printf("KSDBG: remap read addr=0x%x\n", addr); } global_mbp = bank_ptr (addr); if (global_mbp && global_mbp->read_halfword) //return mbp->read_halfword(state, addr); return global_mbp->read_halfword (state, addr); else { //fprintf(stderr, "SKYEYE:NumInstrs %llu, mem_read_halfword addr = %x no bank\n",state->NumInstrs, addr); //chy 2003-09-03 //SKYEYE_OUTREGS(stderr); //exit(-1); return 0; } } ARMword mem_read_word (ARMul_State * state, ARMword addr) { if(skyeye_config.code_cov.prof_on) cov_prof(READ_FLAG, addr); /* if addr is remaped to another place */ if (state->vector_remap_flag && (addr <= 0x0 + state->vector_remap_size)) /* Fixme:we only think the start addr of interrupt vector is 0x0, not think 0xffff0000 */ { addr += state->vector_remap_addr; /* support some remap function in LPC processor */ } global_mbp = bank_ptr (addr); //if (mbp && mbp->read_word) if (global_mbp && global_mbp->read_word) //return mbp->read_word(state, addr); return global_mbp->read_word (state, addr); else { fprintf(stderr, "SKYEYE:Error in %s, no bank found, NumInstrs %llu, mem_read_word addr = %x no bank\n", __FUNCTION__, state->NumInstrs, addr); //SKYEYE_OUTREGS(stderr); //skyeye_exit(-1); return 0; } } void mem_write_byte (ARMul_State * state, ARMword addr, ARMword data) { //mem_bank_t *mbp = bank_ptr(addr); global_mbp = bank_ptr (addr); //if (mbp && mbp->write_byte){ if (global_mbp && global_mbp->write_byte) { /*ywc 2005-03-31 */ /*ywc 2005-04-22 move it to real_write_byte */ /* if(!skyeye_config.no_dbct){ //teawater add for arm2x86 2005.03.18---------------------------------- tb_setdirty(state, addr, mbp); //AJ2D---------------------------------------------------------- } */ global_mbp->write_byte (state, addr, data); //mbp->write_byte(state, addr, data); } else { fprintf(stderr, "SKYEYE:NumInstrs %llu, mem_write_byte addr = %x no bank\n",state->NumInstrs, addr); //chy 2003-09-03 //SKYEYE_OUTREGS(stderr); skyeye_exit(-1); } } void mem_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { //mem_bank_t *mbp = bank_ptr(addr); global_mbp = bank_ptr (addr); //if (mbp && mbp->write_halfword){ if (global_mbp && global_mbp->write_halfword) { /*ywc 2005-03-31 */ /*ywc 2005-04-22 move it to real_write_halfword */ /* if(!skyeye_config.no_dbct){ //teawater add for arm2x86 2005.03.18---------------------------------- tb_setdirty(state, addr, mbp); //AJ2D---------------------------------------------------------- } */ //mbp->write_halfword(state, addr, data); global_mbp->write_halfword (state, addr, data); } else { //fprintf(stderr, "SKYEYE:NumInstrs %llu, mem_write_halfword addr = %x no bank\n",state->NumInstrs, addr); //chy 2003-09-03 //SKYEYE_OUTREGS(stderr); //exit(-1); } } void mem_write_word (ARMul_State * state, ARMword addr, ARMword data) { //chy 2003-07-10 chy: lyh change // bank_ptr(addr)->write_word(state, addr, data); //mem_bank_t *mbp = bank_ptr(addr); if(skyeye_config.code_cov.prof_on) cov_prof(WRITE_FLAG, addr); global_mbp = bank_ptr (addr); //if (mbp && mbp->write_word){ if (global_mbp && global_mbp->write_word) { /*ywc 2005-03-31 */ /*ywc 2005-04-22 move it to real_write_word */ /* if(!skyeye_config.no_dbct){ //teawater add for arm2x86 2005.03.18---------------------------------- tb_setdirty(state, addr, mbp); //AJ2D---------------------------------------------------------- } */ //mbp->write_word(state, addr, data); global_mbp->write_word (state, addr, data); } else { //fprintf(stderr, "SKYEYE:NumInstrs %llu, mem_write_word addr = %x no bank\n",state->NumInstrs, addr); //chy 2003-09-03 //SKYEYE_OUTREGS(stderr); //exit(-1); } } /* if you want a wanring about strange accesses put this on the region */ ARMword warn_read_word (ARMul_State * state, ARMword addr) { fprintf (stderr, "WARNING: illegal read from 0x%x @ 0x%x\n", addr, state->pc); return (0xffffffff); } void warn_write_byte (ARMul_State * state, ARMword addr, ARMword data) { fprintf (stderr, "SKYEYE: WARNING: illegal write byte to 0x%x of 0x%x @ 0x%x\n", addr, data, state->pc); } void warn_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { fprintf (stderr, "SKYEYE: WARNING: illegal write halfword to 0x%x of 0x%x @ 0x%x\n", addr, data, state->pc); } void warn_write_word (ARMul_State * state, ARMword addr, ARMword data) { fprintf (stderr, "SKYEYE: WARNING: illegal write word to 0x%x of 0x%x @ 0x%x\n", addr, data, state->pc); } /* Accesses that map to gaps in the memory map go here: */ ARMword fail_read_word (ARMul_State * state, ARMword addr) { fprintf (stderr, "illegal read from 0x%x\n", addr); ARMul_Debug (state, 0, 0); return (0xffffffff); } void fail_write_word (ARMul_State * state, ARMword addr, ARMword data) { fprintf (stderr, "illegal write to 0x%x of 0x%x\n", addr, data); ARMul_Debug (state, 0, 0); } ARMword _read_word (ARMul_State * state, ARMword addr) { fprintf (stderr, "undefined read from 0x%x\n", addr); return (0xffffffff); } void _write_word (ARMul_State * state, ARMword addr, ARMword data) { fprintf (stderr, "undefined write to 0x%x of 0x%x\n", addr, data); } ARMword real_read_byte (ARMul_State * state, ARMword addr) { ARMword data, offset; /* mem_bank_t *mbp = bank_ptr(addr); if(!mbp) { fprintf(stderr, "real_read_byte. No bank at address 0x%x", addr); return 0; } */ //data = state->mem.rom[mbp - skyeye_config.mem.mem_banks][(addr - mbp->addr) >> 2]; data = state->mem.rom[global_mbp - state->mem_bank->mem_banks][(addr - global_mbp-> addr) >> 2]; offset = (((ARMword) state->bigendSig * 3) ^ (addr & 3)) << 3; /* bit offset into the word */ return (data >> offset & 0xffL); } ARMword real_read_halfword (ARMul_State * state, ARMword addr) { ARMword data, offset; /* mem_bank_t *mbp = bank_ptr(addr); if(!mbp) { fprintf(stderr, "real_read_halfword. No bank at address 0x%x", addr); return 0; } */ //data = state->mem.rom[mbp - skyeye_config.mem.mem_banks][(addr - mbp->addr) >> 2]; data = state->mem.rom[global_mbp - state->mem_bank->mem_banks][(addr - global_mbp-> addr) >> 2]; offset = (((ARMword) state->bigendSig * 2) ^ (addr & 2)) << 3; /* bit offset into the word */ return (data >> offset) & 0xffff; } ARMword real_read_word (ARMul_State * state, ARMword addr) { ARMword data; /* mem_bank_t *mbp = bank_ptr(addr); if(!mbp) { fprintf(stderr, "real_read_word. No bank at address 0x%x", addr); return 0; } */ //data = state->mem.rom[mbp - skyeye_config.mem.mem_banks][(addr - mbp->addr) >> 2]; data = state->mem.rom[global_mbp - state->mem_bank->mem_banks][(addr - global_mbp-> addr) >> 2]; return data; } void real_write_byte (ARMul_State * state, ARMword addr, ARMword data) { ARMword *temp, offset; /* mem_bank_t *mbp = bank_ptr(addr); if(!mbp) { fprintf(stderr, "real_write_byte. No bank at address 0x%x", addr); return; } */ /*ywc 2005-04-22, I move it from mem_write_byte to here */ #ifdef DBCT if (!skyeye_config.no_dbct) { //teawater add for arm2x86 2005.03.18---------------------------------- //tb_setdirty(state, addr, mbp); tb_setdirty (state, addr, global_mbp); //AJ2D---------------------------------------------------------- } #endif //temp = &state->mem.rom[mbp - skyeye_config.mem.mem_banks][(addr - mbp->addr) >> 2]; temp = &state->mem.rom[global_mbp - state->mem_bank->mem_banks][(addr - global_mbp-> addr) >> 2]; offset = (((ARMword) state->bigendSig * 3) ^ (addr & 3)) << 3; /* bit offset into the word */ //printf(stderr,"SKYEYE real_write_byte 1: temp %x,tempval %x,offset %x, addr %x, data %x\n",temp,*temp,offset,addr,data); *temp = (*temp & ~(0xffL << offset)) | ((data & 0xffL) << offset); //printf(stderr,"SKYEYE real_write_byte 2: temp %x,tempval %x,offset %x, addr %x, data %x\n",temp,*temp,offset,addr,data); //chy 2004-03-11: add lcd test //chy 2004-03-17 fix a bug: didn't test skyeye_config.no_lcd //chy 2004-09-29 disable blow lines /* if((!skyeye_config.no_lcd) && *(state->mach_io.lcd_is_enable) && addr >= *(state->mach_io.lcd_addr_begin) && addr <= *(state->mach_io.lcd_addr_end)){ //fprintf(stderr, "SKYEYE,lcd enabled write byte lcd memory addr %x, data %x\n",addr,*temp); skyeye_config.mach->mach_lcd_write(state,addr,*temp); } */ } void real_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { ARMword *temp, offset; /* mem_bank_t *mbp = bank_ptr(addr); if (!mbp) { fprintf(stderr, "real_write_halfword error. No bank at address 0x%x.\n", addr); return; } */ /*ywc 2005-04-22, I move it from mem_write_byte to here */ #ifdef DBCT if (!skyeye_config.no_dbct) { //teawater add for arm2x86 2005.03.18---------------------------------- //tb_setdirty(state, addr, mbp); tb_setdirty (state, addr, global_mbp); //AJ2D---------------------------------------------------------- } #endif //temp = &state->mem.rom[mbp - skyeye_config.mem.mem_banks][(addr - mbp->addr) >> 2]; temp = &state->mem.rom[global_mbp - state->mem_bank->mem_banks][(addr - global_mbp-> addr) >> 2]; offset = (((ARMword) state->bigendSig * 2) ^ (addr & 2)) << 3; /* bit offset into the word */ *temp = (*temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset); //chy 2004-03-11: add lcd test //chy 2004-03-17 fix a bug: didn't test skyeye_config.no_lcd //chy 2004-09-29 disable blow lines /* if((!skyeye_config.no_lcd) && *(state->mach_io.lcd_is_enable) && addr >= *(state->mach_io.lcd_addr_begin) && addr <= *(state->mach_io.lcd_addr_end)){ //fprintf(stderr, "SKYEYE,lcd enabled write byte lcd memory addr %x, data %x\n",addr,*temp); skyeye_config.mach->mach_lcd_write(state,addr,*temp); } */ } void real_write_word (ARMul_State * state, ARMword addr, ARMword data) { /* mem_bank_t *mbp = bank_ptr(addr); if(!mbp) { fprintf(stderr, "real_write_word. No bank at address 0x%x", addr); return ; } */ /*ywc 2005-04-22, I move it from mem_write_byte to here */ #ifdef DBCT if (!skyeye_config.no_dbct) { //teawater add for arm2x86 2005.03.18---------------------------------- //tb_setdirty(state, addr, mbp); tb_setdirty (state, addr, global_mbp); //AJ2D---------------------------------------------------------- } #endif //state->mem.rom[mbp - skyeye_config.mem.mem_banks][(addr - mbp->addr) >> 2] = data; state->mem.rom[global_mbp - state->mem_bank->mem_banks][(addr - global_mbp->addr) >> 2] = data; //chy 2004-03-11: add lcd test //chy 2004-03-17 fix a bug: didn't test skyeye_config.no_lcd //chy 2004-09-29 disable blow lines /* if((!skyeye_config.no_lcd) && *(state->mach_io.lcd_is_enable) && addr >= *(state->mach_io.lcd_addr_begin) && addr <= *(state->mach_io.lcd_addr_end)){ //fprintf(stderr, "SKYEYE,lcd enabled write byte lcd memory addr %x, data %x\n",addr,*temp); skyeye_config.mach->mach_lcd_write(state,addr,data); } */ } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/���������������������������������������������������������������������0000755�0001750�0000144�00000000000�11023514411�014632� 5����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_sharp.c��������������������������������������������������0000644�0001750�0000144�00000017352�10555732132�020517� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <sys/time.h> #include <sys/types.h> #include <unistd.h> #include "armdefs.h" #include "sharp.h" #define F_CORE (200 * 1024 * 1024) //core frequence #define F_OS 508469 //OS timer #define OS_SCALE (F_CORE / F_OS / 10) /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" typedef struct shp_io_t { INTCREGS intc; TIMERREGS timer1; TIMERREGS timer2; UARTREGS uart2; u32 timer1_scale; u32 timer2_scale; u32 uart_scale; } shp_io_t; static shp_io_t shp_io; static void refresh_irq (ARMul_State *); static void shp_io_reset () { memset (&shp_io, 0, sizeof (shp_io)); } static void shp_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { shp_ioregnum_t ioregaddr = addr; switch (ioregaddr) { case CPLDKEYSTATE: break; case CPLDINTSTATE: break; case CPLDINTMASK: break; case CPLDPWRIO: break; case CPLDEXTIO: break; default: printf ("SKYEYE: shp_io_write_byte %08x error, PC %x\n", addr, state->Reg[15]); } return; } static void shp_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { printf ("SKYEYE: shp_io_write_halfword error\n"); skyeye_exit (-1); } static void shp_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { shp_ioregnum_t ioregaddr = addr; switch (ioregaddr) { /* Interrupt controller */ case INTSR: //RO break; case INTRSR: //RO break; case INTENS: /* BUGBUG: Writing a bit as 1 in this register enables the corresponding interrupt source. Clearing a bit by writing a 0 in INTENS will not change that bit nor disable the interrupt. Use the INTENC register to disable interrupt sources. */ shp_io.intc.enableset = data; break; case INTENC: //WO /* BUGBUG: Reading this register returns 0. Set a bit to 1 in this register to clear the corresponding bit in INTENS and disable the corresponding interrupt source. An attempt to clear a bit by writing a 0 in this register does not change INTENS. */ shp_io.intc.enableclear = data; break; /* timer 1 */ case TIMERLOAD1: shp_io.timer1.load = data & 0xffff; shp_io.timer1.value = shp_io.timer1.load; //reset break; case TIMERVALUE1: //RO break; case TIMERCONTROL1: shp_io.timer1.control = data & 0xc4; break; case TIMERTCEOI1: //WO shp_io.timer1.clear = 0; break; /* timer 2 */ case TIMERLOAD2: shp_io.timer2.load = data & 0xffff; shp_io.timer2.value = shp_io.timer2.load; //reset break; case TIMERVALUE2: //RO break; case TIMERCONTROL2: shp_io.timer2.control = data & 0xc4; break; case TIMERTCEOI2: //WO shp_io.timer2.clear = 0; break; /*UART 2 */ case UART2DATA: shp_io.uart2.data = data & 0xfff; { unsigned char c = shp_io.uart2.data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); shp_io.uart2.status &= ~UART_STATUS_TXFF; } break; case UART2FCON: shp_io.uart2.lcr = data & 0xff; break; case UART2BRCON: shp_io.uart2.bcr = data & 0xffff; break; case UART2CON: shp_io.uart2.control = data & 0xff; break; case UART2STATUS: //RO break; case UART2RAWISR: //WO shp_io.uart2.intraw = 0; break; case UART2INTEN: shp_io.uart2.inte = data & 0xf; break; case UART2ISR: //RO break; default: printf ("SKYEYE: shp_io_write_word: unknown addr 0x%x, reg15 0x%x \n", addr, state->Reg[15]); } } static ARMword shp_io_read_byte (ARMul_State * state, ARMword addr) { u32 data = 0; shp_ioregnum_t ioregaddr = addr; switch (ioregaddr) { case CPLDKEYSTATE: break; case CPLDINTSTATE: break; case CPLDINTMASK: break; case CPLDPWRIO: break; case CPLDEXTIO: break; default: printf ("SKYEYE: shp_io_read_byte %08x error, PC %x\n", addr, state->Reg[15]); } // printf("SKYEYE: shp_io_read_byte error\n"); return data; } static ARMword shp_io_read_halfword (ARMul_State * state, ARMword addr) { printf ("SKYEYE: shp_io_read_halfword error\n"); skyeye_exit (-1); } static ARMword shp_io_read_word (ARMul_State * state, ARMword addr) { u32 data; shp_ioregnum_t ioregaddr = addr; switch (addr) { /* Interrupt controller */ case INTSR: //RO data = shp_io.intc.status; break; case INTRSR: //RO data = shp_io.intc.rawstatus; break; case INTENS: data = shp_io.intc.enableset; break; case INTENC: //WO break; /* timer 1 */ case TIMERLOAD1: data = shp_io.timer1.load & 0xffff; break; case TIMERVALUE1: //RO data = 0xffff; //shp_io.timer1.value & 0xffff; break; case TIMERCONTROL1: data = shp_io.timer1.control & 0xc4; break; case TIMERTCEOI1: //WO data = 0; break; /* timer 2 */ case TIMERLOAD2: data = shp_io.timer2.load & 0xffff; break; case TIMERVALUE2: //RO data = shp_io.timer2.value & 0xffff; break; case TIMERCONTROL2: data = shp_io.timer2.control & 0xc4; break; case TIMERTCEOI2: //WO data = 0; break; /*UART 2 */ case UART2DATA: data = shp_io.uart2.data & 0xfff; shp_io.uart2.status |= UART_STATUS_RXFE; break; case UART2FCON: data = shp_io.uart2.lcr & 0xff; break; case UART2BRCON: data = shp_io.uart2.bcr & 0xffff; break; case UART2CON: data = shp_io.uart2.control & 0xff; break; case UART2STATUS: data = shp_io.uart2.status & 0xff; break; case UART2RAWISR: //WO data = shp_io.uart2.intraw & 0xf; break; case UART2INTEN: data = shp_io.uart2.inte & 0xf; break; case UART2ISR: data = shp_io.uart2.intr & 0xf; break; default: printf ("SKYEYE: shp_io_read_word: unknown addr 0x%x, reg15 0x%x \n", addr, state->Reg[15]); } return data; } static void shp_io_do_cycle (ARMul_State * state) { /*timer1 */ if (++shp_io.timer1_scale >= 5000) { shp_io.timer1_scale = 0; if (shp_io.timer1.control & TIMER_CTRL_ENABLE) { if (shp_io.timer1.value-- == 0) { shp_io.timer1.clear = 1; //note timer intrrupt if (shp_io.timer1. control & TIMER_CTRL_PERIODIC) shp_io.timer1.value = shp_io.timer1.load; else shp_io.timer1.value = 0xffff; } } } /*timer2 */ if (++shp_io.timer2_scale >= 5000) { shp_io.timer2_scale = 0; if (shp_io.timer2.control & TIMER_CTRL_ENABLE) { if (shp_io.timer2.value-- == 0) { shp_io.timer2.clear = 1; //note timer intrrupt if (shp_io.timer2. control & TIMER_CTRL_PERIODIC) shp_io.timer2.value = shp_io.timer2.load; else shp_io.timer2.value = 0xffff; } } } /*uart2 */ if (++shp_io.uart_scale >= 512) { shp_io.uart_scale = 0; if (shp_io.uart2.control & UART_CONTROL_EN) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char c; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &c, 1, &tv, NULL) > 0) { shp_io.uart2.data = (int) c; shp_io.uart2.status &= ~UART_STATUS_RXFE; } } } /*reset interrupt pin status */ refresh_irq (state); }; static void refresh_irq (ARMul_State * state) { //BUGBUG: when update interrupt status? shp_io.intc.rawstatus = 0; /*timer1 */ if (shp_io.timer1.clear) { shp_io.intc.rawstatus |= INTC_TC1OINTR; } /*timer2 */ if (shp_io.timer2.clear) { shp_io.intc.rawstatus |= INTC_TC2OINTR; } shp_io.intc.status = shp_io.intc.rawstatus & shp_io.intc.enableset; state->NirqSig = shp_io.intc.status ? LOW : HIGH; } void shp_mach_init (ARMul_State * state, machine_config_t * mc) { ARMul_SelectProcessor (state, ARM_XScale_Prop | ARM_v5_Prop | ARM_v5e_Prop); state->lateabtSig = LOW; state->Reg[1] = 89; /*BUGBUG: lubbock machine id. */ shp_io_reset (); mc->mach_io_do_cycle = shp_io_do_cycle; mc->mach_io_reset = shp_io_reset; mc->mach_io_read_byte = shp_io_read_byte; mc->mach_io_write_byte = shp_io_write_byte; mc->mach_io_read_halfword = shp_io_read_halfword; mc->mach_io_write_halfword = shp_io_write_halfword; mc->mach_io_read_word = shp_io_read_word; mc->mach_io_write_word = shp_io_write_word; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/imx-regs.h�����������������������������������������������������������0000644�0001750�0000144�00000067723�10642317035�016566� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _IMX_REGS_H #define _IMX_REGS_H /* ------------------------------------------------------------------------ * Motorola IMX system registers * ------------------------------------------------------------------------ * */ /* * Register BASEs, based on OFFSETs * */ #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) /* PLL registers */ #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ #define CSCR_SPLL_RESTART (1<<22) #define CSCR_MPLL_RESTART (1<<21) #define CSCR_SYSTEM_SEL (1<<16) #define CSCR_BCLK_DIV (0xf<<10) #define CSCR_MPU_PRESC (1<<15) #define CSCR_SPEN (1<<1) #define CSCR_MPEN (1<<0) #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ /* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D */ #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) #define GPIO_PIN_MASK 0x1f #define GPIO_PORT_MASK (0x3 << 5) #define GPIO_PORT_SHIFT 5 #define GPIO_PORTA (0<<5) #define GPIO_PORTB (1<<5) #define GPIO_PORTC (2<<5) #define GPIO_PORTD (3<<5) #define GPIO_OUT (1<<7) #define GPIO_IN (0<<7) #define GPIO_PUEN (1<<8) #define GPIO_PF (0<<9) #define GPIO_AF (1<<9) #define GPIO_OCR_SHIFT 10 #define GPIO_OCR_MASK (3<<10) #define GPIO_AIN (0<<10) #define GPIO_BIN (1<<10) #define GPIO_CIN (2<<10) #define GPIO_DR (3<<10) #define GPIO_AOUT_SHIFT 12 #define GPIO_AOUT_MASK (3<<12) #define GPIO_AOUT (0<<12) #define GPIO_AOUT_ISR (1<<12) #define GPIO_AOUT_0 (2<<12) #define GPIO_AOUT_1 (3<<12) #define GPIO_BOUT_SHIFT 14 #define GPIO_BOUT_MASK (3<<14) #define GPIO_BOUT (0<<14) #define GPIO_BOUT_ISR (1<<14) #define GPIO_BOUT_0 (2<<14) #define GPIO_BOUT_1 (3<<14) #define GPIO_GIUS (1<<16) /* assignements for GPIO alternate/primary functions */ /* FIXME: This list is not completed. The correct directions are * missing on some (many) pins */ #define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) #define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) #define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) #define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) #define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) #define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) #define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) #define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) #define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) #define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) #define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) #define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) #define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) #define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) #define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) #define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) #define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) /* * PWM controller */ #define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ #define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ #define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ #define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ #define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ #define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ #define PWMC_SWR (0x01<<16) /* Software Reset */ #define PWMC_CLKSRC (0x01<<15) /* Clock Source */ #define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ #define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ #define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ #define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ #define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ #define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ #define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ /* * DMA Controller */ #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ #define DCR_DRST (1<<1) #define DCR_DEN (1<<0) #define DBTOCR_EN (1<<15) #define DBTOCR_CNT(x) ((x) & 0x7fff ) #define CNTR_CNT(x) ((x) & 0xffffff ) #define CCR_DMOD_LINEAR ( 0x0 << 12 ) #define CCR_DMOD_2D ( 0x1 << 12 ) #define CCR_DMOD_FIFO ( 0x2 << 12 ) #define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) #define CCR_SMOD_LINEAR ( 0x0 << 10 ) #define CCR_SMOD_2D ( 0x1 << 10 ) #define CCR_SMOD_FIFO ( 0x2 << 10 ) #define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) #define CCR_MDIR_DEC (1<<9) #define CCR_MSEL_B (1<<8) #define CCR_DSIZ_32 ( 0x0 << 6 ) #define CCR_DSIZ_8 ( 0x1 << 6 ) #define CCR_DSIZ_16 ( 0x2 << 6 ) #define CCR_SSIZ_32 ( 0x0 << 4 ) #define CCR_SSIZ_8 ( 0x1 << 4 ) #define CCR_SSIZ_16 ( 0x2 << 4 ) #define CCR_REN (1<<3) #define CCR_RPT (1<<2) #define CCR_FRC (1<<1) #define CCR_CEN (1<<0) #define RTOR_EN (1<<15) #define RTOR_CLK (1<<14) #define RTOR_PSC (1<<13) /* * Interrupt controller */ #define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) #define INTCNTL_FIAD (1<<19) #define INTCNTL_NIAD (1<<20) #define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) #define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) #define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) #define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) #define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) /* * General purpose timers */ #define IMX_TCTL(x) __REG( 0x00 + (x)) #define TCTL_SWR (1<<15) #define TCTL_FRR (1<<8) #define TCTL_CAP_RIS (1<<6) #define TCTL_CAP_FAL (2<<6) #define TCTL_CAP_RIS_FAL (3<<6) #define TCTL_OM (1<<5) #define TCTL_IRQEN (1<<4) #define TCTL_CLK_PCLK1 (1<<1) #define TCTL_CLK_PCLK1_16 (2<<1) #define TCTL_CLK_TIN (3<<1) #define TCTL_CLK_32 (4<<1) #define TCTL_TEN (1<<0) #define IMX_TPRER(x) __REG( 0x04 + (x)) #define IMX_TCMP(x) __REG( 0x08 + (x)) #define IMX_TCR(x) __REG( 0x0C + (x)) #define IMX_TCN(x) __REG( 0x10 + (x)) #define IMX_TSTAT(x) __REG( 0x14 + (x)) #define TSTAT_CAPT (1<<1) #define TSTAT_COMP (1<<0) /* * LCD Controller */ #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) #define SIZE_YMAX(y) ( (y) & 0x1ff ) #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) #define VPW_VPW(x) ( (x) & 0x3ff ) #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) #define CPOS_CC1 (1<<31) #define CPOS_CC0 (1<<30) #define CPOS_OP (1<<28) #define CPOS_CXP(x) (((x) & 3ff) << 16) #define CPOS_CYP(y) ((y) & 0x1ff) #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) #define LCWHB_BK_EN (1<<31) #define LCWHB_CW(w) (((w) & 0x1f) << 24) #define LCWHB_CH(h) (((h) & 0x1f) << 16) #define LCWHB_BD(x) ((x) & 0xff) #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) #define PCR_TFT (1<<31) #define PCR_COLOR (1<<30) #define PCR_PBSIZ_1 (0<<28) #define PCR_PBSIZ_2 (1<<28) #define PCR_PBSIZ_4 (2<<28) #define PCR_PBSIZ_8 (3<<28) #define PCR_BPIX_1 (0<<25) #define PCR_BPIX_2 (1<<25) #define PCR_BPIX_4 (2<<25) #define PCR_BPIX_8 (3<<25) #define PCR_BPIX_12 (4<<25) #define PCR_BPIX_16 (4<<25) #define PCR_PIXPOL (1<<24) #define PCR_FLMPOL (1<<23) #define PCR_LPPOL (1<<22) #define PCR_CLKPOL (1<<21) #define PCR_OEPOL (1<<20) #define PCR_SCLKIDLE (1<<19) #define PCR_END_SEL (1<<18) #define PCR_END_BYTE_SWAP (1<<17) #define PCR_REV_VS (1<<16) #define PCR_ACD_SEL (1<<15) #define PCR_ACD(x) (((x) & 0x7f) << 8) #define PCR_SCLK_SEL (1<<7) #define PCR_SHARP (1<<6) #define PCR_PCD(x) ((x) & 0x3f) #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) #define HCR_H_WAIT_2(x) ((x) & 0xff) #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) #define VCR_V_WAIT_2(x) ((x) & 0xff) #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) #define POS_POS(x) ((x) & 1f) #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) #define LSCR1_GRAY2(x) (((x) & 0xf) << 4) #define LSCR1_GRAY1(x) (((x) & 0xf)) #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) #define PWMR_CLS(x) (((x) & 0x1ff) << 16) #define PWMR_LDMSK (1<<15) #define PWMR_SCR1 (1<<10) #define PWMR_SCR0 (1<<9) #define PWMR_CC_EN (1<<8) #define PWMR_PW(x) ((x) & 0xff) #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) #define DMACR_BURST (1<<31) #define DMACR_HM(x) (((x) & 0xf) << 16) #define DMACR_TM(x) ((x) &0xf) #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) #define RMCR_LCDC_EN (1<<1) #define RMCR_SELF_REF (1<<0) #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) #define LCDICR_INT_SYN (1<<2) #define LCDICR_INT_CON (1) #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) #define LCDISR_UDR_ERR (1<<3) #define LCDISR_ERR_RES (1<<2) #define LCDISR_EOF (1<<1) #define LCDISR_BOF (1<<0) /* * UART Module. Takes the UART base address as argument */ #define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */ #define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */ #define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */ #define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */ #define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */ #define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */ #define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */ #define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */ #define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */ #define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */ #define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */ #define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */ #define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */ #define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */ #define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */ #define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */ #define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */ #define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */ #define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */ #define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */ #define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */ #define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */ #define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */ /* UART Control Register Bit Fields.*/ #define URXD_CHARRDY (1<<15) #define URXD_ERR (1<<14) #define URXD_OVRRUN (1<<13) #define URXD_FRMERR (1<<12) #define URXD_BRK (1<<11) #define URXD_PRERR (1<<10) #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ #define UCR1_IREN (1<<7) /* Infrared interface enable */ #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ #define UCR1_SNDBRK (1<<4) /* Send break */ #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ #define UCR1_DOZE (1<<1) /* Doze */ #define UCR1_UARTEN (1<<0) /* UART enabled */ #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ #define UCR2_CTSC (1<<13) /* CTS pin control */ #define UCR2_CTS (1<<12) /* Clear to send */ #define UCR2_ESCEN (1<<11) /* Escape enable */ #define UCR2_PREN (1<<8) /* Parity enable */ #define UCR2_PROE (1<<7) /* Parity odd/even */ #define UCR2_STPB (1<<6) /* Stop */ #define UCR2_WS (1<<5) /* Word size */ #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ #define UCR2_TXEN (1<<2) /* Transmitter enabled */ #define UCR2_RXEN (1<<1) /* Receiver enabled */ #define UCR2_SRST (1<<0) /* SW reset */ #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ #define UCR3_PARERREN (1<<12) /* Parity enable */ #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ #define UCR3_DSR (1<<10) /* Data set ready */ #define UCR3_DCD (1<<9) /* Data carrier detect */ #define UCR3_RI (1<<8) /* Ring indicator */ #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ #define UCR3_BPEN (1<<0) /* Preset registers enable */ #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ #define UCR4_INVR (1<<9) /* Inverted infrared reception */ #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ #define UCR4_IRSC (1<<5) /* IR special case */ #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ #define USR1_RTSD (1<<12) /* RTS delta */ #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ #define USR2_IDLE (1<<12) /* Idle condition */ #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ #define USR2_WAKE (1<<7) /* Wake */ #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ #define USR2_TXDC (1<<3) /* Transmitter complete */ #define USR2_BRCD (1<<2) /* Break condition */ #define USR2_ORE (1<<1) /* Overrun error */ #define USR2_RDR (1<<0) /* Recv data ready */ #define UTS_FRCPERR (1<<13) /* Force parity error */ #define UTS_LOOP (1<<12) /* Loop tx and rx */ #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ #define UTS_TXFULL (1<<4) /* TxFIFO full */ #define UTS_RXFULL (1<<3) /* RxFIFO full */ #define UTS_SOFTRST (1<<0) /* Software reset */ #endif // _IMX_REGS_H ���������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_at91rm92.c�����������������������������������������������0000644�0001750�0000144�00000032721�11022662204�020657� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_at91rm92.c - define machine AT91RM9200 for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 10/31/2004 complete UART, Timer, Interrupt, now it can boot ARMLinux successfully. * walimis <wlm@student.dlut.edu.cn> * 5/23/2004 init this file. * walimis <wlm@student.dlut.edu.cn> * * */ #include "armdefs.h" #include "at91rm92.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" #define UART_NUM 4 typedef struct at91rm92_io { u32 ivr; /*AIC Interrupt Vector Register */ u32 fvr; /*AIC FIQ Vector Register */ u32 isr; /*AIC Interrupt Status Register */ u32 ipr; /*AIC Interrupt Pending Register */ u32 imr; /*AIC Interrupt Mask Register */ u32 cisr; u32 iecr; u32 idcr; u32 iccr; u32 iscr; u32 eoicr; u32 spu; struct at91rm92_st_io st; /* system timer */ struct at91rm92_uart_io uart[UART_NUM]; /* uart */ struct at91rm92_dbgu_io dbgu; /* Debug unit */ struct at91rm92_pmc_io pmc; int tc_prescale; } at91rm92_io_t; static at91rm92_io_t at91rm92_io; #define io at91rm92_io static void at91rm92_update_int (ARMul_State * state) { ARMword requests = io.ipr & io.imr; state->NfiqSig = (requests & 0x00001) ? LOW : HIGH; state->NirqSig = (requests & 0xfffffffe) ? LOW : HIGH; } /* new added functions * */ static void at91rm92_set_intr (u32 interrupt) { io.ipr |= (1 << interrupt); } static int at91rm92_pending_intr (u32 interrupt) { return ((io.ipr & (1 << interrupt))); } #if 0 static void at91rm92_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; ARMword requests = io.ipr & io.imr; state->NfiqSig = (requests & 0x00001) ? LOW : HIGH; state->NirqSig = (requests & 0x3fffe) ? LOW : HIGH; } static int at91rm92_mem_read_byte (void *mach, u32 addr, u32 * data) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; *data = (u32) mem_read_char (state, addr); } static int at91rm92_mem_write_byte (void *mach, u32 addr, u32 data) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; mem_write_char (state, addr, (char) data); } #endif static void at91rm92_io_reset (ARMul_State * state) { int i = 0; for(;i < UART_NUM; i++){ io.uart[i].csr = 0x00000202; io.uart[i].mr = 0x000000c0; io.uart[i].brgr = 0x000000c0; } io.dbgu.sr = 0x22; io.pmc.ckgr_pllbr = 0x3F00; io.pmc.ckgr_pllar = 0x3F00; } /*at91rm92 io_do_cycle*/ static void at91rm92_io_do_cycle (ARMul_State * state) { if (io.st.pimr != 0) { if (io.st.piv_dc == 0) { io.st.sr |= AT91RM92_ST_PITS; if (io.st.imr & AT91RM92_ST_PITS) { io.ipr |= AT91RM92_ID_SYS; } io.st.piv_dc = io.st.pimr; } else { io.st.crtr++; io.st.piv_dc--; } } if (1) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { int i = 0; for(;i < UART_NUM; i++){ //if( (((io.uart[i].cr & 0x30) >> 4)) == 0x1 ) /* If RX is enabled */ if(1) /* workaround for receive issue */ { if(io.uart[i].imr & AT91RM92_US_RXRDY) { io.uart[i].rhr = (int) buf; /* Receiver Ready * */ io.uart[i].csr |= AT91RM92_US_RXRDY; /* pending usart0 interrupt * */ io.ipr |= AT91RM92_ID_US(i); } } } if(io.dbgu.cr & 0x10) /* If RXEN is set */ { /* at the same time we think DBGU is also waiting to receiving */ io.dbgu.rhr = (int) buf; io.dbgu.sr |= 0x1; /* set TXRDY bit */ } } } /* if (rcr > 0 && ... */ at91rm92_update_int (state); } static void at91rm92_uart_read (u32 offset, u32 * data) { int i = (offset >> 14) & 0x3; offset = offset & 0xFFF; switch (offset) { case US_MR: *data = io.uart[i].mr; break; case US_IMR: *data = io.uart[i].imr; break; case US_CSR: *data = io.uart[i].csr; break; case US_RHR: /* receive char * */ *data = io.uart[i].rhr; io.uart[i].csr &= (~AT91RM92_US_RXRDY); break; case US_BRGR: *data = io.uart[i].brgr; break; case US_RTOR: *data = io.uart[i].rtor; break; case US_TTGR: *data = io.uart[i].ttgr; break; case US_FIDI: *data = io.uart[i].fidi; break; case US_NER: *data = io.uart[i].ner; break; case US_IF: *data = io.uart[i].us_if; break; default: fprintf(stderr,"in %s, io error, offset=0x%x\n", __FUNCTION__, offset); skyeye_exit(-1); } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } static void at91rm92_uart_write (ARMul_State * state, u32 offset, u32 data) { SKYEYE_DBG ("at91rm92_uart_write(0x%x, 0x%x)\n", offset, data); int i = (offset >> 14) & 0x3; offset = offset & 0xFFF; switch (offset) { case US_CR: io.uart[i].cr = data; break; case US_MR: io.uart[i].mr = data; break; case US_IER: //io.uart0.ier = data; io.uart[i].imr |= (data & 0x000f3fff); if (io.uart[i].imr) { io.ipr |= AT91RM92_ID_US(i); at91rm92_update_int (state); } break; case US_IDR: /* disable usart0 corresponding interrupt * */ io.uart[i].imr &= (~data) & 0x000f3fff; break; case US_THR: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.uart[i].csr |= AT91RM92_US_TXRDY; } //io.uart0.thr = data; break; case US_BRGR: io.uart[i].brgr = data; break; case US_RTOR: io.uart[i].rtor = data; break; case US_TTGR: io.uart[i].ttgr = data; break; case US_FIDI: io.uart[i].fidi = data; break; case US_IF: io.uart[i].us_if = data; break; default: fprintf(stderr, "IO error in %s, offset=0x%x\n", __FUNCTION__, offset); skyeye_exit(-1); } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } static void at91rm92_st_read (u32 offset, u32 * data) { switch (offset) { case ST_PIMR: *data = io.st.pimr; break; case ST_WDMR: *data = io.st.wdmr; break; case ST_RTMR: *data = io.st.rtmr; break; case ST_SR: *data = io.st.sr; /* reinitialize it to zero */ io.st.sr = 0x0; break; case ST_IMR: *data = io.st.imr; break; case ST_RTAR: *data = io.st.rtar; break; case ST_CRTR: *data = io.st.crtr; break; default: fprintf(stderr, "IO error in %s, offset=0x%x\n", __FUNCTION__, offset); skyeye_exit(-1); } } static void at91rm92_st_write (ARMul_State * state, u32 offset, u32 data) { switch (offset) { case ST_CR: io.st.cr = data; io.st.wdv_dc = io.st.wdmr; break; case ST_PIMR: io.st.pimr = data; io.st.piv_dc = data; break; case ST_WDMR: io.st.wdmr = data; io.st.wdv_dc = data; break; case ST_RTMR: io.st.rtmr = data; io.st.rtpres_dc = data; break; case ST_IER: io.st.imr |= (data & 0x0000000f); if (io.st.imr) { io.ipr |= AT91RM92_ID_SYS; at91rm92_update_int (state); } break; case ST_IDR: io.st.imr &= (~data) & 0xf; break; case ST_RTAR: io.st.rtar = data; break; default: fprintf(stderr, "IO error in %s, offset=0x%x\n", __FUNCTION__, offset); skyeye_exit(-1); } } static ARMword at91rm92_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = -1; int i; /*uart0 */ if ((addr >= AT91RM92_UART_BASE) && (addr < (AT91RM92_UART_BASE + UART_NUM * AT91RM92_UART_SIZE))) { at91rm92_uart_read ((u32) (addr - AT91RM92_UART_BASE), (u32 *) & data); return data; } if ((addr >= AT91RM92_ST_BASE0) && (addr < (AT91RM92_ST_BASE0 + AT91RM92_ST_SIZE))) { at91rm92_st_read ((u32) (addr - AT91RM92_ST_BASE0), (u32 *) & data); return data; } switch (addr) { case AIC_IVR: /* IVR */ data = io.ipr; SKYEYE_DBG ("IVR irqs=%x ", data); for (i = 0; i < 32; i++) if (data & (1 << i)) break; if (i < 32) { data = i; io.ipr &= ~(1 << data); at91rm92_update_int (state); } else data = 0; io.ivr = data; SKYEYE_DBG ("read IVR=%d\n", data); break; case AIC_ISR: /* ISR: interrupt status register */ data = io.ivr; break; case AIC_IMR: /* IMR */ data = io.imr; break; case AIC_CISR: /* CISR: Core interrupt status register */ data = io.cisr; data = io.imr; SKYEYE_DBG ("read CISR=%x,%x\n", data, io.cisr); break; case DBGU_MR: data = io.dbgu.mr; break; case DBGU_IMR: data = io.dbgu.imr; break; case DBGU_RHR: data = io.dbgu.rhr; io.dbgu.sr &= ~(0x1); /*set RXRDY to zero */ break; case DBGU_SR: //fprintf(stderr, "read DBGU_SR\n"); data = io.dbgu.sr; break; case DBGU_CIDR: data = 0x4070080; /* RO register, see p331 of at914m9200 manual*/ break; case CKGR_PLLBR: data = io.pmc.ckgr_pllbr; break; case CKGR_PLLAR: data = io.pmc.ckgr_pllar; break; case PMC_MCKR: data = io.pmc.pmc_mckr; break; case PMC_SR: data = io.pmc.pmc_sr; fprintf(stderr,"read sr=0x%x\n", data); break; default: fprintf(stderr,"In %s, io error, addr=0x%x\n", __FUNCTION__, addr); break; } return data; } static ARMword at91rm92_io_read_byte (ARMul_State * state, ARMword addr) { SKYEYE_DBG ("SKYEYE: at91rm92_io_read_byte error\n"); at91rm92_io_read_word (state, addr); } static ARMword at91rm92_io_read_halfword (ARMul_State * state, ARMword addr) { SKYEYE_DBG ("SKYEYE: at91rm92_io_read_halfword error\n"); at91rm92_io_read_word (state, addr); } static void at91rm92_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { if ((addr >= AT91RM92_UART_BASE) && (addr < AT91RM92_UART_BASE + UART_NUM * AT91RM92_UART_SIZE)) { at91rm92_uart_write (state, addr - AT91RM92_UART_BASE, data); return; } if ((addr >= AT91RM92_ST_BASE0) && (addr < (AT91RM92_ST_BASE0 + AT91RM92_ST_SIZE))) { at91rm92_st_write (state, addr - AT91RM92_ST_BASE0, data); return; } switch (addr) { case AIC_IECR: /* IECR */ io.iecr = data; io.imr |= data; break; case AIC_IDCR: /* IDCR */ io.idcr = data; io.imr &= ~data; break; case AIC_ICCR: /* CLEAR interrupts */ io.iccr = data; io.ipr &= ~data; break; case AIC_EOICR: /* EOI */ io.eoicr = data; io.ipr &= ~data; at91rm92_update_int (state); break; case DBGU_IER: io.dbgu.ier = data; break; case DBGU_THR: io.dbgu.thr = data; char c = data; skyeye_uart_write(-1, &c, 1, NULL); io.dbgu.sr |= 0x2; /* set TXRDY bit */ io.dbgu.sr |= 0x20; /* set TXEMPTY bit */ break; case DBGU_CR: io.dbgu.cr = data; break; case DBGU_IDR: io.dbgu.idr = data; if(io.dbgu.idr & AT91RM92_US_TXEMPTY) io.dbgu.sr |= AT91RM92_US_TXEMPTY; break; case DBGU_MR: io.dbgu.mr = data; break; case DBGU_BRGR: io.dbgu.brgr = data; break; case CKGR_PLLBR: io.pmc.ckgr_pllbr = data; if(io.pmc.ckgr_pllbr) io.pmc.pmc_sr |= AT91_PMC_LOCKB; else io.pmc.pmc_sr &= ~AT91_PMC_LOCKB; break; default: //fprintf(stderr,"in %s, io error, addr=0x%x, pc = 0x%x\n", __FUNCTION__, addr, state->pc); //SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data); break; } } static void at91rm92_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: at91rm92_io_write_byte error\n"); at91rm92_io_write_word (state, addr, data); } static void at91rm92_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: at91rm92_io_write_halfword error\n"); at91rm92_io_write_word (state, addr, data); } void at91rm92_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v4_Prop); /* ARM920T uses LOW */ state->lateabtSig = LOW; state->Reg[1] = 251; //for AT91RM9200 state->Reg[1] = 262; //for AT91RM9200DK //state->Reg[1] = 705; // AT91RM9200EK this_mach->mach_io_do_cycle = at91rm92_io_do_cycle; this_mach->mach_io_reset = at91rm92_io_reset; this_mach->mach_io_read_byte = at91rm92_io_read_byte; this_mach->mach_io_write_byte = at91rm92_io_write_byte; this_mach->mach_io_read_halfword = at91rm92_io_read_halfword; this_mach->mach_io_write_halfword = at91rm92_io_write_halfword; this_mach->mach_io_read_word = at91rm92_io_read_word; this_mach->mach_io_write_word = at91rm92_io_write_word; this_mach->mach_update_int = at91rm92_update_int; at91rm92_io_reset(state); //this_mach->mach_set_intr = at91rm92_set_intr; //this_mach->mach_pending_intr = at91rm92_pending_intr; //this_mach->mach_update_intr = at91rm92_update_intr; //this_mach->mach_mem_read_byte = at91rm92_mem_read_byte; //this_mach->mach_mem_write_byte = at91rm92_mem_write_byte; //this_mach->state = (void *)state; } �����������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/clps7110.h�����������������������������������������������������������0000644�0001750�0000144�00000024624�10541455476�016310� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * linux/include/asm-arm/arch-clps7110/clps7110.h * * Written 1998,1999 by Werner Almesberger * * This file contains the hardware definitions of the CL-PS7110 chip */ #ifndef _ASM_ARCH_CLPS7110_H #define _ASM_ARCH_CLPS7110_H /* * CL-PS7110 internal registers * * The names will almost certainly clash with something else ... so we'll * probably have to prefix them with CLPS7110_ or something equally ugly later. */ #define PADR 0x0000 /* Port A Data register ---------------------------- */ #define PBDR 0x0001 /* Port B Data register ---------------------------- */ #define PCDR 0x0002 /* Port C Data register ---------------------------- */ #define PDDR 0x0003 /* Port D Data register ---------------------------- */ #define PADDR 0x0040 /* Port A Data Direction register ------------------ */ #define PBDDR 0x0041 /* Port B Data Direction register ------------------ */ #define PCDDR 0x0042 /* Port C Data Direction register ------------------ */ #define PDDDR 0x0043 /* Port D Data Direction register ------------------ */ #define PEDR 0x0080 /* Port E Data register ---------------------------- */ #define PEDDR 0x00c0 /* Port E Data Direction register ------------------ */ #define SYSCON 0x0100 /* System Control register ------------------------- */ #define KBDSCAN 0x0000000f /* Keyboard scan */ #define KBSC_HI 0x0 /* All driven high */ #define KBSC_LO 0x1 /* All driven low */ #define KBSC_X 0x2 /* All high impedance */ #define KBSC_COL0 0x8 /* Column 0 high, others high impedance */ #define KBSC_COL1 0x9 /* Column 1 high, others high impedance */ #define KBSC_COL2 0xa /* Column 2 high, others high impedance */ #define KBSC_COL3 0xb /* Column 3 high, others high impedance */ #define KBSC_COL4 0xc /* Column 4 high, others high impedance */ #define KBSC_COL5 0xd /* Column 5 high, others high impedance */ #define KBSC_COL6 0xe /* Column 6 high, others high impedance */ #define KBSC_COL7 0xf /* Column 7 high, others high impedance */ #define TC1M 0x00000010 /* TC1 mode (0: free-running, 1: prescale) */ #define TC1S 0x00000020 /* TC1 clock source (0: 2 kHz, 1: 512 kHz) */ #define TC2M 0x00000040 /* TC2 mode (0: free-running, 1: prescale) */ #define TC2S 0x00000080 /* TC2 clock source (0: 2 kHz, 1: 512 kHz) */ #define UARTEN 0x00000100 /* Internal UART enable */ #define BZTOG 0x00000200 /* Drive buzzer directly */ #define BZMOD 0x00000400 /* Buzzer drive mode (0: BZTOG, 1: TC1 under-flow) */ #define DBGEN 0x00000800 /* Debug mode */ #define LCDEN 0x00001000 /* LCD enable */ #define CDENTX 0x00002000 /* Codec interface enable Tx */ #define CDENRX 0x00004000 /* Codec interface enable Rx */ #define SIREN 0x00008000 /* HP SIR protocol encoding enable */ #define ADCKSEL 0x00030000 /* Microwire/SPI peripheral clock speed select */ #define ADCKSEL_SHIFT 16 #define ADCS_8 0x0 /* Sample 8 kHz, interface 4 kHz */ #define ADCS_32 0x1 /* 32/16 kHz */ #define ADCS_128 0x2 /* 128/64 kHz */ #define ADCS_256 0x3 /* 256/128 kHz */ #define EXCKEN 0x00040000 /* External expansion clock enable */ #define WAKEDIS 0x00080000 /* Disable switch-on through wake-up */ #define IRTXM 0x00100000 /* IrDA Tx mode (0: 3/16 of rate, 1: 1.63 us) */ #define SYSFLG 0x0140 /* System Status Flags register -------------------- */ #define MCDR 0x00000001 /* Media changed direct read */ #define DCDET 0x00000002 /* Main adapter is powering the system */ #define WUDR 0x00000004 /* Wake-up direct read */ #define WUON 0x00000008 /* Left standby on wake-up */ #define DID 0x000000f0 /* Display ID nibble */ #define DID_SHIFT 4 #define CTS 0x00000100 /* UART CTS */ #define DSR 0x00000200 /* UART DSR */ #define DCD 0x00000400 /* UART DCD */ #define UBUSY 0x00000800 /* UART transmitter busy */ #define NBFLG 0x00001000 /* New battery flag */ #define RSTFLG 0x00002000 /* Reset flag */ #define PFFLG 0x00004000 /* Power fail flag */ #define CLDFLG 0x00008000 /* Cold start flag */ #define RTCDIV 0x003f0000 /* 64 Hz ticks since last RTC increment */ #define RTCDIV_SHIFT 16 #define URXFE 0x00400000 /* UART receiver FIFO empty */ #define UTXFF 0x00800000 /* UART transmit FIFO full */ #define CRXFE 0x01000000 /* Codec Rx FIFO empty */ #define CTXFF 0x02000000 /* Codec Tx FIFO full */ #define SSIBUSY 0x04000000 /* Synchronous serial interface busy */ #define BOOT8BIT 0x80000000 /* Initial bus width (0: 32 bit, 1: 8 bit) */ #define VERID 0xc0000000 /* Version ID */ #define VERID_SHIFT 30 #define MEMCFG1 0x0180 /* Memory Configuration register 1 ----------------- */ #define MEMCFG2 0x01c0 /* Memory Configuration register 2 ----------------- */ #define CS_BW 0x03 /* Bus width */ #define CS_BW_BUS32_E0 0 /* 32 bit if E=0 */ #define CS_BW_BUS16_E0 1 /* 16 bit if E=0 */ #define CS_BW_BUS8_E0 2 /* 8 bit if E=0 */ #define CS_BW_PCMCIA_E0 3 /* PCMCIA if E=0 */ #define CS_BW_BUS8_E1 0 /* 8 bit if E=1 */ #define CS_BW_PCMCIA_E1 1 /* PCMCIA if E=1 */ #define CS_BW_BUS32_E1 2 /* 32 bit if E=1 */ #define CS_BW_BUS16_E1 3 /* 16 bit if E=1 */ #define CS_RAWT 0x0c /* Random Access Wait State */ #define CS_RAWT_SHIFT 2 /* WS = 4-N; speed = 50+50*WS ns */ #define CS_SAWR 0x30 /* Sequential Access Wait State */ #define CS_SAWR_SHIFT 4 /* WS = 3-N; speed[WS] = 40,80,120,150 ns */ #define CS_SQAEN 0x40 /* Sequential Access Enable */ #define CS_CLKEN 0x80 /* Expansion Clock Enable */ #define DRFPR 0x0200 #define INTSR 0x0240 /* Interrupt Status register ----------------------- */ #define EXTFIQ 0x00000001 /* External fast interrupt */ #define BLINT 0x00000002 /* Battery low interrupt */ #define WEINT 0x00000004 /* Watch dog expired interrupt */ #define MCINT 0x00000008 /* Media changed interrupt */ #define CSINT 0x00000010 /* Codec sound interrupt */ #define EINT1 0x00000020 /* External interrupt 1 */ #define EINT2 0x00000040 /* External interrupt 2 */ /*ywc 2004-04-02 used for touch screen interrupt */ #define EINT3 0x00000080 /* External interrupt 3 */ #define TC1OI 0x00000100 /* TC1 under-flow interrupt */ #define TC2OI 0x00000200 /* TC2 under-flow interrupt */ #define RTCMI 0x00000400 /* RTC compare match interrupt */ #define TINT 0x00000800 /* 64-Hz tick interrupt */ #define UTXINT 0x00001000 /* Internal UART transmit FIFO half-empty intr. */ #define URXINT 0x00002000 /* Internal UART receive FIFO half-full interrupt */ #define UMSINT 0x00004000 /* Internal UART modem status changed interrupt */ #define SSEOTI 0x00008000 /* Synchronous serial interface end-of-transfer */ //chy 2003-01-18 add the ext0 irq number offset is at91 isr //#define AT91_EXT0 0x00008000 /* Synchronous serial interface end-of-transfer */ #define INTMR 0x0280 /* Interrupt Mask register ------------------------- */ #define INTMR2 0x1280 #define INTMR3 0x2280 #define LCDCON 0x02c0 /* LCD Control register ---------------------------- */ #define VBUFSIZ 0x00001fff /* Video buffer size (bits/128-1) */ #define LINELEN 0x0007e000 /* Line length (pix/16-1) */ #define LINELEN_SHIFT 13 #define PIXPSC 0x01f80000 /* Pixel prescale (526628/pixels-1) */ #define PIXPSC_SHIFT 19 #define ACPSC 0x3e000000 /* AC prescale */ #define ACPSC_SHIFT 25 #define GSEN 0x40000000 /* Grayscale enable (0: monochrome) */ #define GSMD 0x80000000 /* Grayscale mode (0: 2 bit, 1: 4 bit) */ #define TC1D 0x0300 /* Timer Counter 1 Data register ------------------- */ #define TC_MASK 0x0000ffff #define TC2D 0x0340 /* Timer Counter 2 Data register ------------------- */ #define RTCDR 0x0380 /* Realtime Clock Data register -------------------- */ #define RTCMR 0x03c0 /* Realtime Clock Match register ------------------- */ #define PMPCON 0x0400 #define CODR 0x0440 /* Codec Interface Data register ------------------- */ #define UARTDR 0x0480 /* UART FIFO Data register ------------------------- */ #define RX_DATA 0x000000ff /* Rx data */ #define FRMERR 0x00000100 /* UART framing error */ #define PARERR 0x00000200 /* UART parity error */ #define OVERR 0x00000400 /* UART overrun error */ #define UBRLCR 0x04c0 /* UART Bit Rate and Line Control register --------- */ #define BRDIV 0x00000fff /* Bit rate divisor */ #define BR_115200 1 #define BR_57600 3 #define BR_38400 5 #define BR_19200 11 #define BR_9600 23 #define BR_2400 95 #define BR_1200 191 #define BREAK 0x00001000 /* Set Tx high */ #define PRTEN 0x00002000 /* Parity enable */ #define EVENPRT 0x00004000 /* Even parity */ #define XSTOP 0x00008000 /* Extra stop bit */ #define FIFOEN 0x00010000 /* Enable FIFO */ #define WRDLEN 0x00030000 /* Word length */ #define WRDLEN_SHIFT 17 #define WL_5 0x0 /* 5 bits */ #define WL_6 0x1 /* 6 bits */ #define WL_7 0x2 /* 7 bits */ #define WL_8 0x3 /* 8 bits */ #define SYNCIO 0x0500 #define TXFRMEN 0x00004000 /* Initiate data transfer */ #define SMCKEN 0x00002000 /* Enable sample clock on SMPLCK */ #define FRLEN 0x00001f00 /* Frame length */ #define FRLEN_SHIFT 8 #define ADCCFB 0x000000ff /* ADC Configuration byte */ #define ADCRSW 0x0000ffff /* ADC result word */ #define PALLSW 0x0540 /* Least-significant 32-bit word of LCD Palette reg. */ #define PALMSW 0x0580 /* Most-significant 32-bit word of LCD Palette reg. */ #define STFCLR 0x05c0 /* Write to clear all start up reason flags -------- */ #define BLEOI 0x0600 /* Write to clear Battery Low interrupt ------------ */ #define MCEOI 0x0640 /* Write to clear Media Changed interrupt ---------- */ #define TEOI 0x0680 /* Write to clear Tick and Watchdog interrupt ------ */ #define TC1EOI 0x06c0 /* Write to clear TC1 interrupt -------------------- */ #define TC2EOI 0x0700 /* Write to clear TC2 interrupt -------------------- */ #define RTCEOI 0x0740 /* Write to clear RTC Match interrupt -------------- */ #define UMSEOI 0x0780 /* Write to clear UART Modem Status Changed interrupt */ #define COEOI 0x07c0 /* Write to clear Codec Sound interrupt ------------ */ #define HALT 0x0800 /* Write to enter idle state ----------------------- */ #define STDBY 0x0840 /* Write to standby state -------------------------- */ /* * CL-PS7110 PCMCIA memory constants * * Need to #define PCMCIA_BASE before using these macros. */ #define PCMCIA_ATTR8(a) (PCMCIA_BASE+0x00000000+(a)) #define PCMCIA_MEM(a) (PCMCIA_BASE+0x04000000+(a)) #define PCMCIA_IO8(a) (PCMCIA_BASE+0x08000000+(a)) #define PCMCIA_IO16(a) (PCMCIA_BASE+0x0c000000+((a) & ~3)+(((a) & 2) << 24)) //ywc,2004-04-01 #define TSBUFFER 0xb000 /* this register contains the start address for touch screen data buffer, this register is not exist in the real hardware------ */ #endif ������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_s3c44b0x.c�����������������������������������������������0000644�0001750�0000144�00000116300�10704350434�020642� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_s3c44b0x.c - SAMSUNG's S3C44B0X simulation for skyeye Copyright (C) 2003 - 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 07/19/2003 original implementation by Walimis <wlm@student.dlut.edu.cn> * 03/04/2007 rewritten by Anthony Lee <don.anthony.lee+program@gmail.com> */ /* * COMPLETED: Interrupt, UART, PWM Timers, Watchdog Timer, LCD, NET, RTC, DMA, IIS * UNIMPLEMENTED: I/O Ports, etc. * * NOTE: * LCD: see "device/lcd/dev_lcd_s3c44b0x.c[h]" * SOUND: see "device/sound/dev_sound_s3c44b0x.c" * NET(RTL8019AS 8/16 bits): see "device/net/dev_net_rtl8019.c[h]" */ #include "armdefs.h" #include "armemu.h" #include "s3c44b0.h" #include "skyeye_uart.h" #include "portable/gettimeofday.h" #define S3C44B0X_DEBUG 0 #define PRINT(x...) printf("[S3C44B0X]: " x) #if S3C44B0X_DEBUG #define DEBUG(x...) printf("[S3C44B0X]: " x) #else #define DEBUG(x...) (void)0 #endif /* * CYCLE_TIMES_PER_SECOND: * It's near 40000 times on my machine, * you can change the value to fit your machine. */ #define CYCLE_TIMES_PER_SECOND (40000) #define MCLK (64) /* MHz */ #define TIMER_COUNT_DOWN_PER_SECOND ((1000000 * MCLK) >> 1) /* prescale=1, divider=1/2 */ #define TIMER_COUNT_DOWN_PER_CYCLE (TIMER_COUNT_DOWN_PER_SECOND / CYCLE_TIMES_PER_SECOND) #define BCD_TO_BIN(a) (((a) >> 4) * 10 + ((a) & 0xf)) #define BIN_TO_BCD(a) ((((a) / 10) << 4) | ((a) % 10)) #define HALFWORD_SWAP(x) (((x) >> 8) | ((x) << 8)) #define WORD_SWAP(x) ((HALFWORD_SWAP((x) & 0xffff) << 16) | HALFWORD_SWAP(((x) >> 16) & 0xffff)) struct s3c44b0x_uart_fifo { unsigned char rx[16]; unsigned char tx[16]; ARMword txcnt; }; typedef ARMword (s3c44b0x_dma_t)[8]; #define DMA_CON(dma) dma[0] #define DMA_ISRC(dma) dma[1] #define DMA_IDES(dma) dma[2] #define DMA_ICNT(dma) dma[3] #define DMA_CSRC(dma) dma[4] #define DMA_CDES(dma) dma[5] #define DMA_CCNT(dma) dma[6] #define DMA_FLY(dma) dma[7] extern ARMword mem_read_byte(ARMul_State*, ARMword); extern ARMword mem_read_halfword(ARMul_State*, ARMword); extern ARMword mem_read_word(ARMul_State*, ARMword); extern void mem_write_byte(ARMul_State*, ARMword, ARMword); extern void mem_write_halfword(ARMul_State*, ARMword, ARMword); extern void mem_write_word(ARMul_State*, ARMword, ARMword); extern ARMword io_read_byte(ARMul_State*, ARMword); extern ARMword io_read_halfword(ARMul_State*, ARMword); extern ARMword io_read_word(ARMul_State*, ARMword); extern void io_write_byte(ARMul_State*, ARMword, ARMword); extern void io_write_halfword(ARMul_State*, ARMword, ARMword); extern void io_write_word(ARMul_State*, ARMword, ARMword); typedef ARMword (*s3c44b0x_dma_read_func)(ARMul_State*, ARMword); typedef void (*s3c44b0x_dma_write_func)(ARMul_State*, ARMword, ARMword); static s3c44b0x_dma_read_func dma_read_funcs[12] = { /* ZDMA */ mem_read_byte, mem_read_halfword, mem_read_word, /* BDMA */ mem_read_byte, io_read_byte, io_read_byte, mem_read_halfword, io_read_halfword, io_read_halfword, mem_read_word, io_read_word, io_read_word, }; static s3c44b0x_dma_write_func dma_write_funcs[12] = { /* ZDMA */ mem_write_byte, mem_write_halfword, mem_write_word, /* BDMA */ io_write_byte, mem_write_byte, io_write_byte, io_write_halfword, mem_write_halfword, io_write_halfword, io_write_word, mem_write_word, io_write_word, }; /* S3C44B0X Internal IO Registers */ struct s3c44b0x_io_t { /* CPU Wrapper Registers : FIXME */ ARMword syscfg; ARMword ncachbe0; ARMword ncachbe1; ARMword sbuscon; /* Memory Controller Registers : FIXME */ ARMword bwscon; /* Interrupt Controller Registers */ ARMword intcon; ARMword intpnd; ARMword intmod; ARMword intmsk; ARMword i_pslv; ARMword i_pmst; ARMword i_cslv; ARMword i_cmst; /* UART Registers */ ARMword ulcon0; ARMword ulcon1; ARMword ucon0; ARMword ucon1; ARMword ufcon0; ARMword ufcon1; ARMword umcon0; ARMword umcon1; ARMword utrstat0; ARMword utrstat1; ARMword uerstat0; ARMword uerstat1; ARMword ufstat0; ARMword ufstat1; ARMword umstat0; ARMword umstat1; ARMword urxh0; ARMword urxh1; ARMword ubrdiv0; ARMword ubrdiv1; struct s3c44b0x_uart_fifo ufifo0; struct s3c44b0x_uart_fifo ufifo1; /* PWM Timers Registers */ ARMword tcfg0; ARMword tcfg1; ARMword tcnt_scaler[7]; ARMword tprescaler[7]; ARMword tdivider[7]; ARMword tcon; ARMword tcntb[6]; ARMword tcmpb[5]; ARMword tcnt[6]; ARMword tcmp[5]; /* Watchdog Timer Registers */ ARMword wtcon; ARMword wtdat; ARMword wtcnt; /* RTC Registers */ ARMword rtccon; ARMword rtcalm; ARMword rtcrst; ARMword ticint; ARMword tick_count; struct tm rtc_alarm; long int rtc_offset; /* DMA Registers */ s3c44b0x_dma_t dma[4]; /* IIS Registers */ ARMword iiscon; ARMword iismod; ARMword iispsr; ARMword iisfifcon; ARMhword iisfifo_rx[8]; ARMhword iisfifo_tx[8]; ARMword iisfifo_txcnt; }; static struct s3c44b0x_io_t s3c44b0x_io; ARMhword *s3c44b0x_iisfifo_tx = NULL; #define io s3c44b0x_io static int s3c44b0x_dma_is_valid(int index); static void s3c44b0x_dma_proccess(ARMul_State *state, int index); static void s3c44b0x_io_reset(ARMul_State *state) { memset(&io, 0, sizeof(io)); /* CPU Wrapper */ io.syscfg = 0x1; io.sbuscon = 0x80001b1b; /* Memory Controller */ io.bwscon = (state->bigendSig ? 0x1 : 0x0); /* Interrupt */ io.intcon = 0x7; io.intmsk = 0x7ffffff; io.i_pslv = 0x1b1b1b1b; io.i_pmst = 0x1f1b; io.i_cslv = 0x1b1b1b1b; io.i_cmst = 0x1b; /* UART */ io.utrstat0 = io.utrstat1 = 0x6; /* Watchdog Timer */ io.wtcon = 0x8020; /* here we disabled watchdog */ io.wtdat = 0x8000; io.wtcnt = 0x8000; io.tdivider[6] = 4; /* RTC */ io.rtc_alarm.tm_mday = 1; /* IIS */ io.iiscon = 0x100; s3c44b0x_iisfifo_tx = &io.iisfifo_tx[0]; } /* Interrupt Routine */ static void s3c44b0x_update_int(ARMul_State *state) { ARMword requests = (io.intmsk & (0x1 << INT_GLOBAL)) ? 0x0 : (io.intpnd & ~io.intmsk); ARMword vector, irq; state->NfiqSig = ((io.intcon & 0x1) == 0 ? ((requests & io.intmod) ? LOW : HIGH) : HIGH); state->NirqSig = ((io.intcon & 0x2) == 0 ? ((requests & ~io.intmod) ? LOW : HIGH) : HIGH); } static void s3c44b0x_update_intr(struct machine_config *mach) { /* leave me alone, do nothing ... */ } static int s3c44b0x_pending_intr(unsigned int irq) { /* Here we "return 1" so that the device won't do something for it */ if (!((io.intcon & 0x2) == 0x0 || (io.intcon & 0x5) == 0x4)) return 1; if (io.intmsk & (0x1 << INT_GLOBAL)) return 1; return ((io.intpnd & (0x1 << irq)) == 0 ? 0 : 1); } static void s3c44b0x_set_interrupt(unsigned int irq) { if ((io.intcon & 0x2) == 0x0 || (io.intcon & 0x5) == 0x4) { /* IRQ or FIQ enabled */ io.intpnd |= (0x1 << irq); } } static void s3c44b0x_interrupt_read(ARMword addr, ARMword *data) { int i; switch (addr) { case INTCON: *data = io.intcon; break; case INTPND: *data = ((io.intmsk & (0x1 << INT_GLOBAL)) ? 0x1 : io.intpnd); break; case INTMOD: *data = io.intmod; break; case INTMSK: *data = io.intmsk; break; case I_PSLV: *data = io.i_pslv; break; case I_PMST: *data = io.i_pmst; break; case I_CSLV: *data = io.i_cslv; break; case I_CMST: *data = io.i_cmst; break; case I_ISPR: *data = 0; if (io.intmsk & (0x1 << INT_GLOBAL)) break; if ((io.intcon & 0x2) != 0x0) break; for (i = 0; i < 26; i++) { /* find which interrupt is pending */ if (((io.intpnd & ~io.intmsk) & (0x1 << i)) & ~io.intmod) { *data = (0x1 << i); break; } } break; case F_ISPR: *data = 0; if (io.intmsk & (0x1 << INT_GLOBAL)) break; if ((io.intcon & 0x5) != 0x4) break; for (i = 0; i < 26; i++) { /* find which interrupt is pending */ if (((io.intpnd & ~io.intmsk) & (0x1 << i)) & io.intmod) { *data = (0x1 << i); break; } } break; default: break; } DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c44b0x_interrupt_write(ARMul_State *state, ARMword addr, ARMword data) { DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); switch (addr) { case INTCON: io.intcon = data; break; case INTMOD: io.intmod = data; break; case INTMSK: io.intmsk = data; break; case I_PSLV: io.i_pslv = data; break; case I_PMST: io.i_pmst = data; break; case I_ISPC: if ((io.intcon & 0x2) != 0x0 || ((data & 0x3ffffff) & ~io.intmod) == 0) break; io.intpnd &= (~data & 0x3ffffff); break; case F_ISPC: if ((io.intcon & 0x5) != 0x4 || ((data & 0x3ffffff) & io.intmod) == 0) break; io.intpnd &= (~data & 0x3ffffff); break; default: break; } } /* UART Routine */ static void s3c44b0x_uart_do_cycle(ARMul_State *state) { int read_uart0 = 1; struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; do { ARMword *pUfstat = (read_uart0 ? &io.ufstat0 : &io.ufstat1); ARMword *pUtrstat = (read_uart0 ? &io.utrstat0 : &io.utrstat1); ARMword *pUcon = (read_uart0 ? &io.ucon0 : &io.ucon1); ARMword *pUfcon = (read_uart0 ? &io.ufcon0 : &io.ufcon1); ARMword *pUrxh = (read_uart0 ? &io.urxh0 : &io.urxh1); ARMword bdma_mask = (read_uart0 ? 0x2 : 0x3); if ((*pUcon & 0x3) == bdma_mask || (*pUcon & 0xc) == (bdma_mask << 2)) { /* BDMA request */ ARMword utxhb = (read_uart0 ? UTXH0 : UTXH1) + state->bigendSig * 3; ARMword urxhb = (read_uart0 ? URXH0 : URXH1) + state->bigendSig * 3; int index = (read_uart0 ? 2 : 3); int rx_empty = ((*pUfcon & 0x1) ? ((*pUfstat & 0xf) == 0) : ((*pUtrstat & 0x1) == 0)); int tx_ready = ((*pUfcon & 0x1) ? ((*pUfstat & 0x200) == 0) : 1); ARMword mask = 0; if ((*pUcon & 0x3) == 0x0) rx_empty = 1; if ((*pUcon & 0xc) == 0x0) tx_ready = 0; do { if (s3c44b0x_dma_is_valid(index) != 1) break; if (((DMA_CCNT(io.dma[index]) >> 30) & 0x3) != 0x2) break; if ((DMA_CDES(io.dma[index]) & 0xfffffff) == utxhb && tx_ready) mask |= (bdma_mask << 2); if ((DMA_CSRC(io.dma[index]) & 0xfffffff) == urxhb && !rx_empty) mask |= bdma_mask; if ((*pUcon & mask) != 0) s3c44b0x_dma_proccess(state, index); } while (0); } if (*pUfcon & 0x1) { /* FIFO mode */ struct s3c44b0x_uart_fifo *pUfifo = (read_uart0 ? &io.ufifo0 : &io.ufifo1); int count, tmp_count; if ((*pUfstat & 0x100) == 0 && (*pUcon & 0x3) != 0x0) { /* FIFO not full */ tmp_count = count = (*pUfstat & 0xf); count += skyeye_uart_read(read_uart0 ? 0 : 1, &pUfifo->rx[count], 16 - count, &tv, NULL); if (count > tmp_count) { *pUfstat &= ~0xf; *pUfstat |= (count == 16 ? 0x10f : count); } } while ((count = ((*pUfstat & 0xf0) >> 4)) > 0 && (*pUcon & 0xc) != 0x0) { /* handling TX FIFO */ if (pUfifo->txcnt > 0) { pUfifo->txcnt -= 1; break; } if (*pUfstat & 0x200) count++; tmp_count = skyeye_uart_write(read_uart0 ? 0 : 1, &pUfifo->tx[0], count, NULL); if (tmp_count <= 0) break; count -= tmp_count; *pUfstat &= ~0x2f0; if (count > 0) { *pUfstat |= (count << 4); memmove(&pUfifo->tx[0], &pUfifo->tx[tmp_count], (size_t)count); } else { pUfifo->txcnt = 64; } if ((*pUcon & 0xc) == 0x4) { /* Transmit Mode: Interrupt request or polling mode */ s3c44b0x_set_interrupt(read_uart0 ? INT_UTXD0 : INT_UTXD1); } break; } if ((*pUfstat & 0xf) == 0) continue; *pUrxh = (ARMword)pUfifo->rx[0]; } else { /* non FIFO mode */ unsigned char buf; if ((*pUcon & 0x3) == 0x0) continue; if (*pUtrstat & 0x1) continue; if (skyeye_uart_read(read_uart0 ? 0 : 1, &buf, 1, &tv, NULL) <= 0) continue; *pUrxh = (ARMword)buf; *pUtrstat |= 0x1; } if ((*pUcon & 0x3) == 0x1) s3c44b0x_set_interrupt(read_uart0 ? INT_URXD0 : INT_URXD1); } while((read_uart0--) && skyeye_config.uart.count > 1); } static void s3c44b0x_uart_read(ARMword addr, ARMword *data) { switch (addr) { case ULCON0: *data = io.ulcon0; break; case ULCON1: *data = io.ulcon1; break; case UCON0: *data = io.ucon0; break; case UCON1: *data = io.ucon1; break; case UFCON0: *data = io.ufcon0; break; case UFCON1: *data = io.ufcon1; break; case UMCON0: *data = io.umcon0; break; case UMCON1: *data = io.umcon1; break; case UTRSTAT0: *data = io.utrstat0; break; case UTRSTAT1: *data = io.utrstat1; break; case UERSTAT0: *data = io.uerstat0; break; case UERSTAT1: *data = io.uerstat1; break; case UFSTAT0: *data = io.ufstat0; break; case UFSTAT1: *data = io.ufstat1; break; case UMSTAT0: *data = io.umstat0; break; case UMSTAT1: *data = io.umstat1; break; case URXH0: case URXH1: { ARMword *pUfstat = (addr == URXH0 ? &io.ufstat0 : &io.ufstat1); ARMword *pUtrstat = (addr == URXH0 ? &io.utrstat0 : &io.utrstat1); ARMword *pUfcon = (addr == URXH0 ? &io.ufcon0 : &io.ufcon1); ARMword *pUrxh = (addr == URXH0 ? &io.urxh0 : &io.urxh1); *data = (*pUrxh); if (*pUfcon & 0x1) { /* FIFO mode */ ARMword *pUcon = (addr == URXH0 ? &io.ucon0 : &io.ucon1); struct s3c44b0x_uart_fifo *pUfifo = (addr == URXH0 ? &io.ufifo0 : &io.ufifo1); int count = (*pUfstat & 0xf); if (count == 0) break; if (*pUfstat & 0x100) count++; *pUfstat &= ~0x10f; if (count == 1) break; *pUfstat |= (--count); memmove(&pUfifo->rx[0], &pUfifo->rx[1], (size_t)count); *pUrxh = (ARMword)pUfifo->rx[0]; } else { /* non FIFO mode */ *pUtrstat &= ~0x1; } } break; case UBRDIV0: *data = io.ubrdiv0; break; case UBRDIV1: *data = io.ubrdiv1; break; default: break; } DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c44b0x_uart_write(ARMul_State *state, ARMword addr, ARMword data) { DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); switch (addr) { case ULCON0: io.ulcon0 = data; break; case ULCON1: io.ulcon1 = data; break; case UCON0: io.ucon0 = data; break; case UCON1: io.ucon1 = data; break; case UFCON0: case UFCON1: { ARMword *pUfcon = (addr == UFCON0 ? &io.ufcon0 : &io.ufcon1); *pUfcon = (data & ~0x6); if (!((data & 0x1) == 0 || (data & 0x6) == 0)) { ARMword *pUfstat = (addr == UFCON0 ? &io.ufstat0 : &io.ufstat1); if (data & 0x2) *pUfstat &= ~0x10f; /* Rx FIFO reset */ if (data & 0x4) *pUfstat &= ~0x2f0; /* Tx FIFO reset */ } } break; case UMCON0: io.umcon0 = data; break; case UMCON1: io.umcon1 = data; break; case UTXH0: case UTXH1: { ARMword *pUtrstat = (addr == UTXH0 ? &io.utrstat0 : &io.utrstat1); ARMword *pUcon = (addr == UTXH0 ? &io.ucon0 : &io.ucon1); ARMword *pUfcon = (addr == UTXH0 ? &io.ufcon0 : &io.ufcon1); char tmp = data & 0xff; #if 0 /* Disabled the line to show some messages when booting use incorrect bootrom */ if ((*pUcon & 0xc) == 0x0) break; #endif if (*pUfcon & 0x1) { /* FIFO mode */ ARMword *pUfstat = (addr == UTXH0 ? &io.ufstat0 : &io.ufstat1); if ((*pUfstat & 0x200) == 0) { /* FIFO not full */ struct s3c44b0x_uart_fifo *pUfifo = (addr == UTXH0 ? &io.ufifo0 : &io.ufifo1); int count = ((*pUfstat >> 4) & 0xf); pUfifo->tx[count++] = tmp; *pUfstat &= ~0xf0; *pUfstat |= (count == 16 ? 0x2f0 : (count << 4)); } } else { /* non FIFO mode */ skyeye_uart_write(addr == UTXH0 ? 0 : 1, (void*)&tmp, 1, NULL); *pUtrstat |= 0x6; if ((*pUcon & 0xc) == 0x4) { /* Transmit Mode: Interrupt request or polling mode */ s3c44b0x_set_interrupt(addr == UTXH0 ? INT_UTXD0 : INT_UTXD1); } } } break; case UBRDIV0: io.ubrdiv0 = data; break; case UBRDIV1: io.ubrdiv1 = data; break; default: break; } } /* Timer Routine */ static int s3c44b0x_timer_check_state(int timer_index, int op_code) { int bit_offset; if (timer_index == 5) { switch (op_code) { case TIMER_OP_START: bit_offset = 24; break; case TIMER_OP_MANUAL: bit_offset = 25; break; case TIMER_OP_RELOAD: bit_offset = 26; break; default: return 0; /* invalid */ } } else { bit_offset = op_code + (timer_index == 0 ? 0 : 8 + 4 * (timer_index - 1)); } return (io.tcon & (0x1 << bit_offset)); } static void s3c44b0x_timer_do_cycle(ARMul_State *state) { int i, cnt_down, cnt_divider; for (i = 0; i < 6; i++) { if (s3c44b0x_timer_check_state(i, TIMER_OP_START) == 0) continue; cnt_divider = (io.tprescaler[i] + 1) << io.tdivider[i]; cnt_down = TIMER_COUNT_DOWN_PER_CYCLE / cnt_divider; if (cnt_down == 0) { if (io.tcnt_scaler[i] == 0) { io.tcnt_scaler[i] = cnt_divider / TIMER_COUNT_DOWN_PER_CYCLE; continue; } else if ((io.tcnt_scaler[i] -= 1) != 0) { continue; } cnt_down = 1; } if ((io.tcnt[i] -= min(io.tcnt[i], cnt_down)) > 0) continue; if (((io.tcfg1 >> 24) & 0xf) == i + 1) { /* BDMA request */ do { if (s3c44b0x_dma_is_valid(3) != 1) break; if (((DMA_CCNT(io.dma[3]) >> 30) & 0x3) != 0x1) break; s3c44b0x_dma_proccess(state, 3); } while (0); } else { /* interrupt mode */ s3c44b0x_set_interrupt(INT_TIMER0 - i); } if (s3c44b0x_timer_check_state(i, TIMER_OP_RELOAD) == 0) continue; io.tcnt[i] = io.tcntb[i]; if (i < 5) io.tcmp[i] = io.tcmpb[i]; } if (io.wtcon & 0x20) { cnt_divider = (io.tprescaler[6] + 1) << io.tdivider[6]; cnt_down = TIMER_COUNT_DOWN_PER_CYCLE / cnt_divider; if (cnt_down == 0) { if (io.tcnt_scaler[6] == 0) { io.tcnt_scaler[6] = cnt_divider / TIMER_COUNT_DOWN_PER_CYCLE; goto next; } else if ((io.tcnt_scaler[6] -= 1) != 0) { goto next; } cnt_down = 1; } if ((io.wtcnt -= min(io.wtcnt, cnt_down)) > 0) return; if ((io.wtcon & 0x4) != 0) { /* interrupt mode */ s3c44b0x_set_interrupt(INT_WDT); } if (io.wtcon & 0x1) { /* asserts reset signal */ state->NresetSig = LOW; PRINT("****************** WATCHDOG RESET ******************\n"); } io.wtcnt = io.wtdat; } next: return; } static void s3c44b0x_timer_read(ARMword addr, ARMword *data) { switch (addr) { case TCFG0: *data = io.tcfg0; break; case TCFG1: *data = io.tcfg1; break; case TCON: *data = io.tcon; break; case TCNTB0: case TCNTB1: case TCNTB2: case TCNTB3: case TCNTB4: case TCNTB5: *data = io.tcntb[(addr - TCNTB0) / 0xc]; break; case TCMPB0: case TCMPB1: case TCMPB2: case TCMPB3: case TCMPB4: *data = io.tcmpb[(addr - TCMPB0) / 0xc]; break; case TCNTO0: case TCNTO1: case TCNTO2: case TCNTO3: case TCNTO4: *data = io.tcnt[(addr - TCNTO0) / 0xc]; break; case TCNTO5: *data = io.tcnt[5]; break; case WTCON: *data = io.wtcon; break; case WTDAT: *data = io.wtdat; break; case WTCNT: *data = io.wtcnt; break; default: break; } DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c44b0x_timer_write(ARMul_State *state, ARMword addr, ARMword data) { int i, prescaler, divider; DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); switch (addr) { case TCFG0: case TCFG1: if (addr == TCFG0) { io.tcfg0 = data; } else { io.tcfg1 = data; } for (i = 0; i < 6; i++) { io.tprescaler[i] = ((io.tcfg0 >> ((i >> 1) << 3)) & 0xff); io.tdivider[i] = min(4, ((io.tcfg1 >> (i << 2)) & 0xf)); } break; case TCON: io.tcon = data; for (i = 0; i < 6; i++) { if (s3c44b0x_timer_check_state(i, TIMER_OP_MANUAL) != 0) { io.tcnt[i] = io.tcntb[i]; if (i < 5) io.tcmp[i] = io.tcmpb[i]; } } break; case TCNTB0: case TCNTB1: case TCNTB2: case TCNTB3: case TCNTB4: case TCNTB5: io.tcntb[(addr - TCNTB0) / 0xc] = min(data, 0xffff); break; case TCMPB0: case TCMPB1: case TCMPB2: case TCMPB3: case TCMPB4: io.tcmpb[(addr - TCMPB0) / 0xc] = data; break; case WTCON: io.wtcon = data; io.tprescaler[6] = ((io.wtcon >> 8) & 0xff); io.tdivider[6] = ((io.wtcon >> 3) & 0x3) + 4; break; case WTDAT: io.wtdat = data; break; case WTCNT: io.wtcnt = data; break; default: break; } } /* I/O Ports Routine */ static void s3c44b0x_ports_read(ARMword addr, ARMword *data) { /* TODO */ DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c44b0x_ports_write(ARMul_State *state, ARMword addr, ARMword data) { /* TODO */ DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); } /* RTC Routine */ static void s3c44b0x_rtc_do_cycle(ARMul_State *state) { if ((io.rtcalm & 0x40) != 0 && (io.rtcalm & 0x3f) != 0) { struct timeval curr_time; struct tm *curr_tm; time_t curr_timer; unsigned int almen = 0; if (gettimeofday(&curr_time, NULL) != 0 || ((curr_timer = (time_t)((long int)curr_time.tv_sec + io.rtc_offset)), (curr_tm = gmtime(&curr_timer))) == NULL) return; if (curr_tm->tm_sec >= io.rtc_alarm.tm_sec) almen |= 0x1; if (curr_tm->tm_min == io.rtc_alarm.tm_min) almen |= 0x2; if (curr_tm->tm_hour == io.rtc_alarm.tm_hour) almen |= 0x4; if (curr_tm->tm_mday == io.rtc_alarm.tm_mday) almen |= 0x8; if (curr_tm->tm_mon == io.rtc_alarm.tm_mon) almen |= 0x10; if (curr_tm->tm_year == io.rtc_alarm.tm_year) almen |= 0x20; if ((io.rtcalm & 0x3f) == almen) { io.rtcalm &= 0x3f; s3c44b0x_set_interrupt(INT_RTC); } } if ((io.ticint & 0x80) != 0) { /* WARNING: RTC tick is unexacting */ if (io.tick_count > 0) io.tick_count -= 1; if (io.tick_count == 0) s3c44b0x_set_interrupt(INT_TICK); } } static void s3c44b0x_rtc_read(ARMword addr, ARMword *data) { struct timeval curr_time; struct tm *curr_tm; time_t curr_timer; if (addr == RTCCON) { *data = io.rtccon; goto exit; } else if ((io.rtccon & 0x1) == 0) { goto exit; } switch (addr) { case RTCALM: *data = io.rtcalm; goto exit; case RTCRST: *data = io.rtcrst; goto exit; case TICINT: *data = io.ticint; goto exit; case ALMSEC: *data = BIN_TO_BCD(io.rtc_alarm.tm_sec); goto exit; case ALMMIN: *data = BIN_TO_BCD(io.rtc_alarm.tm_min); goto exit; case ALMHOUR: *data = BIN_TO_BCD(io.rtc_alarm.tm_hour); goto exit; case ALMDAY: *data = BIN_TO_BCD(io.rtc_alarm.tm_mday); goto exit; case ALMMON: *data = BIN_TO_BCD(io.rtc_alarm.tm_mon + 1); goto exit; case ALMYEAR: *data = io.rtc_alarm.tm_year - 100; goto exit; default: break; } if (gettimeofday(&curr_time, NULL) != 0 || ((curr_timer = (time_t)((long int)curr_time.tv_sec + io.rtc_offset)), (curr_tm = gmtime(&curr_timer))) == NULL) goto exit; switch (addr) { case BCDSEC: *data = BIN_TO_BCD(curr_tm->tm_sec); break; case BCDMIN: *data = BIN_TO_BCD(curr_tm->tm_min); break; case BCDHOUR: *data = BIN_TO_BCD(curr_tm->tm_hour); break; case BCDDAY: *data = BIN_TO_BCD(curr_tm->tm_mday); break; case BCDDATE: *data = (curr_tm->tm_wday == 0 ? 7 : curr_tm->tm_wday); break; case BCDMON: *data = BIN_TO_BCD(curr_tm->tm_mon + 1); break; case BCDYEAR: *data = curr_tm->tm_year - 100; break; default: goto exit; } exit: DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); return; } static void s3c44b0x_rtc_write(ARMul_State *state, ARMword addr, ARMword data) { struct timeval curr_time; struct tm *curr_tm; time_t curr_timer; DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); if (addr == RTCCON) { io.rtccon = data; goto exit; } else if ((io.rtccon & 0x1) == 0) { goto exit; } switch (addr) { case RTCALM: io.rtcalm = data; goto exit; case RTCRST: io.rtcrst = data; goto exit; case TICINT: io.ticint = data; io.tick_count = (data & 0x7f); io.tick_count *= (CYCLE_TIMES_PER_SECOND / 128); /* 1/128 sec per count down */ goto exit; case ALMSEC: io.rtc_alarm.tm_sec = BCD_TO_BIN(data); goto exit; case ALMMIN: io.rtc_alarm.tm_min = BCD_TO_BIN(data); goto exit; case ALMHOUR: io.rtc_alarm.tm_hour = BCD_TO_BIN(data); goto exit; case ALMDAY: io.rtc_alarm.tm_mday = BCD_TO_BIN(data); goto exit; case ALMMON: io.rtc_alarm.tm_mon = BCD_TO_BIN(data) - 1; goto exit; case ALMYEAR: io.rtc_alarm.tm_year = data + 100; goto exit; default: break; } if (gettimeofday(&curr_time, NULL) != 0 || ((curr_timer = (time_t)((long int)curr_time.tv_sec + io.rtc_offset)), (curr_tm = gmtime(&curr_timer))) == NULL) goto exit; switch (addr) { case BCDSEC: curr_tm->tm_sec = BCD_TO_BIN(data); break; case BCDMIN: curr_tm->tm_min = BCD_TO_BIN(data); break; case BCDHOUR: curr_tm->tm_hour = BCD_TO_BIN(data); break; case BCDDAY: curr_tm->tm_mday = BCD_TO_BIN(data); break; case BCDDATE: break; case BCDMON: curr_tm->tm_mon = BCD_TO_BIN(data) - 1; break; case BCDYEAR: curr_tm->tm_mon = data + 100; break; default: goto exit; } io.rtc_offset = (long int)mktime(curr_tm) - (long int)curr_time.tv_sec; exit: return; } /* DMA Routine */ static void s3c44b0x_dma_proccess(ARMul_State *state, int index) { int i = index; int dal, das, dst, opt_tdm; s3c44b0x_dma_read_func read_func; s3c44b0x_dma_write_func write_func; ARMword ccnt, src_addr, dst_addr, data; ccnt = DMA_CCNT(io.dma[i]); if ((ccnt & 0xfffff) == 0x0) { if ((ccnt & 0x200000) == 0x0) return; memcpy(&io.dma[i][4], &io.dma[i][1], 3 * sizeof(ARMword)); /* auto-reload */ DMA_CON(io.dma[i]) &= ~0x30; DMA_CCNT(io.dma[i]) &= ~0x3000000; return; } src_addr = DMA_CSRC(io.dma[i]); dst_addr = DMA_CDES(io.dma[i]); if ((dal = ((src_addr >> 28) & 0x3)) == 0x0) return; if ((das = ((dst_addr >> 28) & 0x3)) == 0x0) return; if ((dst = ((src_addr >> 30) & 0x3)) == 0x3) return; if (i < 2 && dst != 0x2 && ((ccnt >> 26) & 0x3) == 0x2) return; if ((opt_tdm = ((dst_addr >> 30) & 0x3)) == 0x0 && i >= 2) return; if ((ccnt & 0xfffff) >= (1 << dst)) { read_func = dma_read_funcs[i < 2 ? dst : (3 + (dst * 3) + (opt_tdm - 1))]; write_func = dma_write_funcs[i < 2 ? dst : (3 + (dst * 3) + (opt_tdm - 1))]; if (((ccnt >> 26) & 0x3) != 0x3 || ((ccnt >> 24) & 0x3) != 0x2) { /* read */ data = (*read_func)(state, (src_addr & 0xfffffff)); if (i < 2 && dst != 0 && (opt_tdm & 0x1) != 0x0) /* swap */ data = (dst == 1 ? HALFWORD_SWAP(data) : WORD_SWAP(data)); if (dal == 1) src_addr += min(0xfffffff - (src_addr & 0xfffffff), 1 << dst); else if (dal == 2) src_addr -= min((src_addr & 0xfffffff), 1 << dst); DMA_CSRC(io.dma[i]) = src_addr; } if (((ccnt >> 26) & 0x3) != 0x3 || ((ccnt >> 24) & 0x3) == 0x2) { /* write */ if (((ccnt >> 26) & 0x3) == 0x3) data = DMA_FLY(io.dma[i]); (*write_func)(state, (dst_addr & 0xfffffff), data); if (das == 1) dst_addr += min(0xfffffff - (dst_addr & 0xfffffff), 1 << dst); else if (das == 2) dst_addr -= min((dst_addr & 0xfffffff), 1 << dst); DMA_CDES(io.dma[i]) = dst_addr; } if (((ccnt >> 26) & 0x3) == 0x3) { /* on-the-fly mode */ if (((ccnt >> 24) & 0x3) != 0x2) { DMA_FLY(io.dma[i]) = data; ccnt &= ~0x3000000; ccnt |= 0x2000000; /* Read time */ } else { ccnt |= 0x3000000; /* Write time */ } } } if ((ccnt & 0xfffff) <= (1 << dst)) { /* terminated count */ ccnt &= ~0xfffff; if ((ccnt & 0x200000) == 0x0) ccnt &= ~0x100000; /* clear EN bit */ DMA_CON(io.dma[i]) &= ~0x30; DMA_CON(io.dma[i]) |= 0x20; if (((ccnt >> 22) & 0x3) > 1) s3c44b0x_set_interrupt(INT_ZDMA0 - i); } else { ccnt -= (1 << dst); if (((ccnt >> 22) & 0x3) == 2) s3c44b0x_set_interrupt(INT_ZDMA0 - i); } DMA_CCNT(io.dma[i]) = ccnt; } static int s3c44b0x_dma_is_valid(int index) { ARMword ccnt; if ((DMA_CON(io.dma[index]) & 0xc) != 0x0) return -1; if (((ccnt = DMA_CCNT(io.dma[index])) & 0x100000) == 0x0) return -1; if (index < 2) { /* ZDMA */ if (((ccnt >> 30) & 0x3) < 0x2) return 1; /* DMA request, till now it's impossible in simulation */ } else { /* BDMA */ if (((ccnt >> 26) & 0x3) == 0x3) return -1; /* don't support on-the-fly mode */ if (((ccnt >> 30) & 0x3) != 0x0) return 1; /* DMA request */ } return 0; } static void s3c44b0x_dma_do_cycle(ARMul_State *state) { int i; for (i = 0; i < 4; i++) { if (s3c44b0x_dma_is_valid(i) != 0) continue; s3c44b0x_dma_proccess(state, i); } } static void s3c44b0x_dma_read(ARMword addr, ARMword *data) { s3c44b0x_dma_t *dma = &io.dma[(addr & 0xff) / 0x20 + (addr <= ZDCCNT1 ? 0 : 2)]; ARMword *val = (ARMword*)dma + (((addr & 0xff) % 0x20) >> 2); *data = *val; DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c44b0x_dma_write(ARMul_State *state, ARMword addr, ARMword data) { s3c44b0x_dma_t *dma = &io.dma[(addr & 0xff) / 0x20 + (addr <= ZDCCNT1 ? 0 : 2)]; ARMword *val = (ARMword*)dma + (((addr & 0xff) % 0x20) >> 2); DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); if ((addr & 0xff) % 0x20 == 0x00) { /* CON */ *val = ((*val & 0x30) | (data & ~0x33)); if ((data & 0x3) == 0x3) DMA_CSRC((*dma)) &= ~0x100000; /* clear EN bit */ return; } else if ((addr & 0xff) % 0x20 < 0x10) { /* ISRC, IDES, ICNT */ *val = data; *(val + 3) = data; return; } PRINT("ERROR: %s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); } /* IIS Routine */ static int s3c44b0x_iis_write_to_device(ARMul_State *state, ARMhword *buf, int count) { ARMword data; if (buf != s3c44b0x_iisfifo_tx) memcpy(s3c44b0x_iisfifo_tx, buf, count * 2); io_write_word(state, IISFIF_TX_CONTROL, ((0xa << 8) | (0x1 << 4) | count)); #if 0 data = io_read_word(state, IISFIF_TX_CONTROL); if ((data & 0xff0) != 0xa20) return -1; return (int)(data & 0xf); #else /* don't care */ return count; #endif } static int s3c44b0x_iis_read_from_device(ARMul_State *state, ARMhword *data) { ARMword tmp; tmp = io_read_word(state, IISFIF_RX_CONTROL); if (((tmp >> 16) & 0xff) != 0x15) return -1; *data = (ARMhword)(tmp & 0xffff); return 0; } static void s3c44b0x_iis_do_cycle(ARMul_State *state) { int count; if ((io.iiscon & 0x1) == 0) return; while (((io.iismod >> 7) & 0x1) && (io.iisfifcon & 0x2f0) > 0x200) { /* handling TX FIFO */ int nWritten = -1; if (io.iisfifo_txcnt > 0) { io.iisfifo_txcnt -= 1; break; } count = (io.iisfifcon >> 4) & 0xf; nWritten = s3c44b0x_iis_write_to_device(state, &io.iisfifo_tx[0], count); if (nWritten <= 0) break; count -= nWritten; io.iisfifcon = ((io.iisfifcon & ~0xf0) | (count << 4)); if (count == 0) { io.iiscon &= ~0x80; io.iisfifo_txcnt = 8; } else { memmove(&io.iisfifo_tx[0], &io.iisfifo_tx[nWritten], count * 2); } break; } while (((io.iismod >> 6) & 0x1) && ((io.iisfifcon >> 8) & 0x1)) { /* handling RX FIFO */ ARMhword tmp; if ((count = io.iisfifcon & 0xf) >= 8) break; if (s3c44b0x_iis_read_from_device(state, &tmp) != 0) break; io.iisfifo_rx[count++] = tmp; io.iisfifcon = ((io.iisfifcon & ~0xf) | count); if (count == 8) io.iiscon &= ~0x40; break; } while ((io.iiscon & 0x30) != 0) { /* BDMA request */ int rx_empty = ((io.iisfifcon & 0x100) ? ((io.iisfifcon & 0xf) == 0) : 0); int tx_ready = ((io.iisfifcon & 0x100) ? (((io.iisfifcon >> 4) & 0xf) < 8) : 1); ARMword mask = 0; if (s3c44b0x_dma_is_valid(2) != 1) break; if (((DMA_CCNT(io.dma[2]) >> 30) & 0x3) != 0x1) break; if ((DMA_CDES(io.dma[2]) & 0xfffffff) == IISFIF + state->bigendSig * 2 && tx_ready) mask |= (0x1 << 5); if ((DMA_CSRC(io.dma[2]) & 0xfffffff) == IISFIF + state->bigendSig * 2 && !rx_empty) mask |= (0x1 << 4); if ((io.iiscon & mask) != 0) s3c44b0x_dma_proccess(state, 2); break; } } static void s3c44b0x_iis_read(ARMul_State *state, ARMword addr, ARMword *data) { switch (addr) { case IISCON: *data = io.iiscon; break; case IISMOD: *data = io.iismod; break; case IISPSR: *data = io.iispsr; break; case IISFIFCON: *data = io.iisfifcon; break; case IISFIF: if (!((io.iiscon & 0x1) && ((io.iismod >> 6) & 0x1))) break; if ((io.iisfifcon & 0x100) != 0) { /* FIFO */ int count = (io.iisfifcon & 0xf); if (count > 0) { *data = io.iisfifo_rx[0]; io.iisfifcon = ((io.iisfifcon & ~0xf) | (--count)); if (count > 0) memmove(&io.iisfifo_rx[0], &io.iisfifo_rx[1], count * 2); io.iiscon |= 0x40; } } else { /* non FIFO */ ARMhword tmp; if (s3c44b0x_iis_read_from_device(state, &tmp) == 0) *data = tmp; } break; default: break; } DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c44b0x_iis_write(ARMul_State *state, ARMword addr, ARMword data) { ARMhword tmp, count; DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); switch (addr) { case IISCON: io.iiscon = ((io.iiscon & 0x1c0) | (data & ~0x1c0)); break; case IISMOD: io.iismod = data; break; case IISPSR: io.iispsr = data; break; case IISFIFCON: io.iisfifcon = ((io.iisfifcon & 0xff) | (data & ~0xff)); break; case IISFIF: if (!((io.iiscon & 0x1) && ((io.iismod >> 7) & 0x1))) break; tmp = data & 0xffff; if ((io.iisfifcon & 0x200) != 0) { /* FIFO */ if ((count = ((io.iisfifcon >> 4) & 0xf)) < 8) { io.iisfifo_tx[count++] = tmp; io.iisfifcon = ((io.iisfifcon & ~0xf0) | (count << 4)); io.iiscon |= 0x80; } } else { /* non FIFO */ s3c44b0x_iis_write_to_device(state, &tmp, 1); } break; default: break; } } /* IO Read Routine */ static ARMword s3c44b0x_io_read_word(ARMul_State *state, ARMword addr) { ARMword data = -1; /* Interrupt */ if (addr >= INTCON && addr <= F_ISPC) { s3c44b0x_interrupt_read(addr, &data); return data; } /* UART */ if (addr >= ULCON0 && addr <= UBRDIV1) { s3c44b0x_uart_read(addr, &data); return data; } /* Timer */ if ((addr >= WTCON && addr <= WTCNT) || (addr >= TCFG0 && addr <= TCNTO5)) { s3c44b0x_timer_read(addr, &data); return data; } /* I/O Ports */ if (addr >= PCONA && addr <= EXTINTPND) { s3c44b0x_ports_read(addr, &data); return data; } /* RTC */ if (addr >= RTCCON && addr <= TICINT) { s3c44b0x_rtc_read(addr, &data); return data; } /* DMA */ if ((addr >= ZDCON0 && addr <= ZDCCNT1) || (addr >= BDCON0 && addr <= BDCCNT1)) { s3c44b0x_dma_read(addr, &data); return data; } /* IIS */ if (addr >= IISCON && addr <= IISFIF) { s3c44b0x_iis_read(state, addr, &data); return data; } /* TODO */ switch (addr) { case SYSCFG: data = 0x01; /* FIXME */ break; case NCACHBE0: data = io.ncachbe0; break; case NCACHBE1: data = io.ncachbe1; break; case SBUSCON: data = io.sbuscon; break; case BWSCON: data = io.bwscon; break; default: DEBUG("UNIMPLEMENTED: %s(addr:0x%08x)\n", __FUNCTION__, addr); break; } return data; } static ARMword s3c44b0x_io_read_byte(ARMul_State *state, ARMword addr) { ARMword data, offset; data = s3c44b0x_io_read_word(state, (addr & ~0x3)); /* bit offset into the word */ offset = ((state->bigendSig * 3) ^ (addr & 3)) << 3; return ((data >> offset) & 0xff); } static ARMword s3c44b0x_io_read_halfword(ARMul_State *state, ARMword addr) { ARMword data, offset; data = s3c44b0x_io_read_word(state, addr & ~0x3); /* bit offset into the word */ offset = ((state->bigendSig * 2) ^ (addr & 2)) << 3; return ((data >> offset) & 0xffff); } /* IO Write Routine */ static void s3c44b0x_io_write_word(ARMul_State *state, ARMword addr, ARMword data) { /* Interrupt */ if (addr >= INTCON && addr <= F_ISPC) { s3c44b0x_interrupt_write(state, addr, data); return; } /* UART */ if (addr >= ULCON0 && addr <= UBRDIV1) { s3c44b0x_uart_write(state, addr, data); return; } /* Timer */ if ((addr >= WTCON && addr <= WTCNT) || (addr >= TCFG0 && addr <= TCNTO5)) { s3c44b0x_timer_write(state, addr, data); return; } /* I/O Ports */ if (addr >= PCONA && addr <= EXTINTPND) { s3c44b0x_ports_write(state, addr, data); return; } /* RTC */ if (addr >= RTCCON && addr <= TICINT) { s3c44b0x_rtc_write(state, addr, data); return; } /* DMA */ if ((addr >= ZDCON0 && addr <= ZDCCNT1) || (addr >= BDCON0 && addr <= BDCCNT1)) { s3c44b0x_dma_write(state, addr, data); return; } /* IIS */ if (addr >= IISCON && addr <= IISFIF) { s3c44b0x_iis_write(state, addr, data); return; } /* TODO */ switch (addr) { case SYSCFG: io.syscfg = data; break; case NCACHBE0: io.ncachbe0 = data; break; case NCACHBE1: io.ncachbe1 = data; break; case SBUSCON: io.sbuscon = data; break; case BWSCON: io.bwscon = (io.bwscon & 0x1) | (data & ~0x1); break; default: DEBUG("UNIMPLEMENTED: %s(addr:0x%08x, data:0x%x)\n", __FUNCTION__, addr, data); break; } } static void s3c44b0x_io_write_byte(ARMul_State *state, ARMword addr, ARMword data) { if ((state->bigendSig * 3) == (addr & 3)) { s3c44b0x_io_write_word(state, addr & ~0x3, data); return; } DEBUG("ERROR: %s(addr:0x%08x, data:0x%x)\n", __FUNCTION__, addr, data); } static void s3c44b0x_io_write_halfword(ARMul_State *state, ARMword addr, ARMword data) { if ((state->bigendSig * 2) == (addr & 3)) { s3c44b0x_io_write_word(state, addr & ~0x3, data); return; } DEBUG("ERROR: %s(addr:0x%08x, data:0x%x)\n", __FUNCTION__, addr, data); } static void s3c44b0x_io_do_cycle(ARMul_State *state) { /* TODO */ s3c44b0x_uart_do_cycle(state); s3c44b0x_timer_do_cycle(state); s3c44b0x_rtc_do_cycle(state); s3c44b0x_dma_do_cycle(state); s3c44b0x_iis_do_cycle(state); s3c44b0x_update_int(state); } /* Machine Initialization */ #define MACH_IO_DO_CYCLE_FUNC(f) ((void (*)(void*))(f)) #define MACH_IO_RESET_FUNC(f) ((void (*)(void*))(f)) #define MACH_IO_READ_FUNC(f) ((uint32_t (*)(void*, uint32_t))(f)) #define MACH_IO_WRITE_FUNC(f) ((void (*)(void*, uint32_t, uint32_t))(f)) #define MACH_IO_UPDATE_INT_FUNC(f) ((void (*)(void*))(f)) #define MACH_IO_SET_INTR_FUNC(f) ((void (*)(u32))(f)) #define MACH_IO_PENDING_INTR_FUNC(f) ((int (*)(u32))(f)) #define MACH_IO_UPDATE_INTR_FUNC(f) ((void (*)(void*))(f)) void s3c44b0x_mach_init(ARMul_State *state, machine_config_t *this_mach) { ARMul_SelectProcessor(state, ARM_v4_Prop); state->lateabtSig = HIGH; state->Reg[1] = 178; /* R1: machine type : found in linux-2.6.x/include/asm/mach-types.h */ this_mach->mach_io_do_cycle = MACH_IO_DO_CYCLE_FUNC(s3c44b0x_io_do_cycle); this_mach->mach_io_reset = MACH_IO_RESET_FUNC(s3c44b0x_io_reset); this_mach->mach_io_read_word = MACH_IO_READ_FUNC(s3c44b0x_io_read_word); this_mach->mach_io_read_halfword = MACH_IO_READ_FUNC(s3c44b0x_io_read_halfword); this_mach->mach_io_read_byte = MACH_IO_READ_FUNC(s3c44b0x_io_read_byte); this_mach->mach_io_write_word = MACH_IO_WRITE_FUNC(s3c44b0x_io_write_word); this_mach->mach_io_write_halfword = MACH_IO_WRITE_FUNC(s3c44b0x_io_write_halfword); this_mach->mach_io_write_byte = MACH_IO_WRITE_FUNC(s3c44b0x_io_write_byte); this_mach->mach_update_int = MACH_IO_UPDATE_INT_FUNC(s3c44b0x_update_int); /* mach_set_intr, mach_pending_intr, mach_update_intr, state : for devices, such as NET,LCD etc. */ this_mach->mach_set_intr = MACH_IO_SET_INTR_FUNC(s3c44b0x_set_interrupt); this_mach->mach_pending_intr = MACH_IO_PENDING_INTR_FUNC(s3c44b0x_pending_intr); this_mach->mach_update_intr = MACH_IO_UPDATE_INTR_FUNC(s3c44b0x_update_intr); this_mach->state = (void*)state; } ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/s3c2410x.h�����������������������������������������������������������0000644�0001750�0000144�00000022472�10634526727�016225� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* s3c2410x.h - definitions of "s3c2410x" machine for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 12/30/2004 initial version * * Shi Yang <shy828301@126.com> * */ #ifndef __S3C2410X_H_ #define __S3C2410X_H_ #define REGW(addr) (*(volatile unsigned int *)(addr)) /******************************************** * Memory Controller Registers ********************************************/ #define MEM_CTL_BASE (0x48000000) #define MEM_CTL_SIZE (0x30) #define BWSCON MEM_CTL_BASE+(0x0) #define BANKCON0 MEM_CTL_BASE+(0x4) #define BANKCON1 MEM_CTL_BASE+(0x8) #define BANKCON2 MEM_CTL_BASE+(0xc) #define BANKCON3 MEM_CTL_BASE+(0x10) #define BANKCON4 MEM_CTL_BASE+(0x14) #define BANKCON5 MEM_CTL_BASE+(0x18) #define BANKCON6 MEM_CTL_BASE+(0x1c) #define BANKCON7 MEM_CTL_BASE+(0x20) #define REFRESH MEM_CTL_BASE+(0x24) #define BANKSIZE MEM_CTL_BASE+(0x28) #define MRSRB6 MEM_CTL_BASE+(0x2c) #define MRSRB7 MEM_CTL_BASE+(0x30) /******************************************** * LCD Controller Registers ********************************************/ #define LCD_CTL_BASE (0x4D000000) #define LCD_CTL_SIZE (0x60) /******************************************** * GPIO Controller Registers ********************************************/ #define GPIO_CTL_BASE (0x56000000) #define GPIO_CTL_SIZE (0xC0) #define GPACON GPIO_CTL_BASE+(0x0) #define GPADAT GPIO_CTL_BASE+(0x4) #define GPBCON GPIO_CTL_BASE+(0x10) #define GPBDAT GPIO_CTL_BASE+(0x14) #define GPBUP GPIO_CTL_BASE+(0x18) #define GPCCON GPIO_CTL_BASE+(0x20) #define GPCDAT GPIO_CTL_BASE+(0x24) #define GPCUP GPIO_CTL_BASE+(0x28) #define GPDCON GPIO_CTL_BASE+(0x30) #define GPDDAT GPIO_CTL_BASE+(0x34) #define GPDUP GPIO_CTL_BASE+(0x38) #define GPECON GPIO_CTL_BASE+(0x40) #define GPEDAT GPIO_CTL_BASE+(0x44) #define GPEUP GPIO_CTL_BASE+(0x48) #define GPFCON GPIO_CTL_BASE+(0x50) #define GPFDAT GPIO_CTL_BASE+(0x54) #define GPFUP GPIO_CTL_BASE+(0x58) #define GPGCON GPIO_CTL_BASE+(0x60) #define GPGDAT GPIO_CTL_BASE+(0x64) #define GPGUP GPIO_CTL_BASE+(0x68) #define GPHCON GPIO_CTL_BASE+(0x70) #define GPHDAT GPIO_CTL_BASE+(0x74) #define GPHUP GPIO_CTL_BASE+(0x78) #define MISCCR GPIO_CTL_BASE+(0x80) #define DCLKCON GPIO_CTL_BASE+(0x84) #define EXTINT0 GPIO_CTL_BASE+(0x88) #define EXTINT1 GPIO_CTL_BASE+(0x8c) #define EXTINT2 GPIO_CTL_BASE+(0x90) #define EINTFLT0 GPIO_CTL_BASE+(0x94) #define EINTFLT1 GPIO_CTL_BASE+(0x98) #define EINTFLT2 GPIO_CTL_BASE+(0x9c) #define EINTFLT3 GPIO_CTL_BASE+(0xa0) #define EINTMASK GPIO_CTL_BASE+(0xa4) #define EINTPEND GPIO_CTL_BASE+(0xa8) #define GSTATUS0 GPIO_CTL_BASE+(0xac) #define GSTATUS1 GPIO_CTL_BASE+(0xb0) #define GSTATUS2 GPIO_CTL_BASE+(0xb4) #define GSTATUS3 GPIO_CTL_BASE+(0xb8) #define GSTATUS4 GPIO_CTL_BASE+(0xbc) /******************************************** * Clock and Power Management Registers ********************************************/ #define CLK_CTL_BASE (0x4c000000) #define LOCKTIME CLK_CTL_BASE+(0x0) #define MPLLCON CLK_CTL_BASE+(0x4) #define UPLLCON CLK_CTL_BASE+(0x8) #define CLKCON CLK_CTL_BASE+(0xc) #define CLKSLOW CLK_CTL_BASE+(0x10) #define CLKDIVN CLK_CTL_BASE+(0x14) /******************************************** * UART Control Registers ********************************************/ #define UART_CTL_BASE0 (0x50000000) #define UART_CTL_SIZE (0x802c) #define ULCON (0x0) #define UCON (0x4) #define UFCON (0x8) #define UMCON (0xc) #define UTRSTAT (0x10) #define UERSTAT (0x14) #define UFSTAT (0x18) #define UMSTAT (0x1c) #define UTXH (0x20) #define URXH (0x24) #define UBRDIV (0x28) /**************************************/ /* Interrupt Controller Registers */ /**************************************/ #define INT_CTL_BASE (0x4a000000) #define SRCPND INT_CTL_BASE+(0x0) #define INTMOD INT_CTL_BASE+(0x4) #define INTMSK INT_CTL_BASE+(0x8) #define PRIORITY INT_CTL_BASE+(0xc) #define INTPND INT_CTL_BASE+(0x10) #define INTOFFSET INT_CTL_BASE+(0x14) #define SUBSRCPND INT_CTL_BASE+(0x18) #define INTSUBMSK INT_CTL_BASE+(0x1c) #define INT_ADCTC (1 << 31) /* ADC EOC interrupt */ #define INT_RTC (1 << 30) /* RTC alarm interrupt */ #define INT_SPI1 (1 << 29) /* UART1 transmit interrupt */ #define INT_UART0 (1 << 28) /* UART0 transmit interrupt */ #define INT_IIC (1 << 27) /* IIC interrupt */ #define INT_USBH (1 << 26) /* USB host interrupt */ #define INT_USBD (1 << 25) /* USB device interrupt */ #define INT_RESERVED24 (1 << 24) #define INT_UART1 (1 << 23) /* UART1 receive interrupt */ #define INT_SPI0 (1 << 22) /* SPI interrupt */ #define INT_MMC (1 << 21) /* MMC interrupt */ #define INT_DMA3 (1 << 20) /* DMA channel 3 interrupt */ #define INT_DMA2 (1 << 19) /* DMA channel 2 interrupt */ #define INT_DMA1 (1 << 18) /* DMA channel 1 interrupt */ #define INT_DMA0 (1 << 17) /* DMA channel 0 interrupt */ #define INT_LCD (1 << 16) /* reserved for future use */ #define INT_UART2 (1 << 15) /* UART 2 interrupt */ #define INT_TIMER4 (1 << 14) /* Timer 4 interrupt */ #define INT_TIMER3 (1 << 13) /* Timer 3 interrupt */ #define INT_TIMER2 (1 << 12) /* Timer 2 interrupt */ #define INT_TIMER1 (1 << 11) /* Timer 1 interrupt */ #define INT_TIMER0 (1 << 10) /* Timer 0 interrupt */ #define INT_WDT (1 << 9) /* Watch-Dog timer interrupt */ #define INT_TICK (1 << 8) /* RTC time tick interrupt */ #define INT_BAT_FLT (1 << 7) #define INT_RESERVED6 (1 << 6) /* Reserved for future use */ #define INT_EINT8_23 (1 << 5) /* External interrupt 8 ~ 23 */ #define INT_EINT4_7 (1 << 4) /* External interrupt 4 ~ 7 */ #define INT_EINT3 (1 << 3) /* External interrupt 3 */ #define INT_EINT2 (1 << 2) /* External interrupt 2 */ #define INT_EINT1 (1 << 1) /* External interrupt 1 */ #define INT_EINT0 (1 << 0) /* External interrupt 0 */ #define INT_ADC (1 << 10) #define INT_TC (1 << 9) #define INT_ERR2 (1 << 8) #define INT_TXD2 (1 << 7) #define INT_RXD2 (1 << 6) #define INT_ERR1 (1 << 5) #define INT_TXD1 (1 << 4) #define INT_RXD1 (1 << 3) #define INT_ERR0 (1 << 2) #define INT_TXD0 (1 << 1) #define INT_RXD0 (1 << 0) #define INT_MASK_INIT 0xffffffff #define INT_SUBMSK_INIT 0x7ff /*********************/ /* RTC Registers */ /*********************/ #define RTC_CTL_BASE (0x57000000) #define RTCCON RTC_CTL_BASE+(0x40) #define TICNT RTC_CTL_BASE+(0x44) #define RTCALM RTC_CTL_BASE+(0x50) #define ALMSEC RTC_CTL_BASE+(0x54) #define ALMMIN RTC_CTL_BASE+(0x58) #define ALMHOUR RTC_CTL_BASE+(0x5c) #define ALMDATE RTC_CTL_BASE+(0x60) #define ALMMON RTC_CTL_BASE+(0x64) #define ALMYEAR RTC_CTL_BASE+(0x68) #define RTCRST RTC_CTL_BASE+(0x6c) #define BCDSEC RTC_CTL_BASE+(0x70) #define BCDMIN RTC_CTL_BASE+(0x74) #define BCDHOUR RTC_CtL_BASE+(0x78) #define BCDDATE RTC_CTL_BASE+(0x7c) #define BCDDAY RTC_CTL_BASE+(0x80) #define BCDMON RTC_CTL_BASE+(0x84) #define BCDYEAR RTC_CTL_BASE+(0x88) /***************************/ /* WatchDog Timer Registers */ /***************************/ #define WD_TIMER_BASE 0x53000000 #define WDCON (WD_TIMER_BASE + 0) #define WDDAT (WD_TIMER_BASE + 0x4) #define WDCNT (WD_TIMER_BASE + 0x8) /***************************/ /* PWM Timer Registers */ /***************************/ #define PWM_CTL_BASE (0x51000000) #define PWM_CTL_SIZE (0x44) #define TCFG0 (0x0) #define TCFG1 (0x4) #define TCON (0x8) #define TCNTB0 (0xc) #define TCMPB0 (0x10) #define TCNTO0 (0x14) #define TCNTB1 (0x18) #define TCMPB1 (0x1c) #define TCNTO1 (0x20) #define TCNTB2 (0x24) #define TCMPB2 (0x28) #define TCNTO2 (0x2c) #define TCNTB3 (0x30) #define TCMPB3 (0x34) #define TCNTO3 (0x38) #define TCNTB4 (0x3c) #define TCNTO4 (0x40) #define S3C2410_TIMER_NUM 5 struct s3c2410x_clkpower { u32 locktime; u32 mpllcon; u32 upllcon; u32 clkcon; u32 clkslow; u32 clkdivn; }; struct s3c2410x_timer_io { u32 tcfg0; u32 tcfg1; u32 tcon; int tcnt[S3C2410_TIMER_NUM]; int tcmp[S3C2410_TIMER_NUM]; int tcntb[S3C2410_TIMER_NUM]; int tcmpb[S3C2410_TIMER_NUM]; int tcnto[S3C2410_TIMER_NUM]; }; struct s3c2410x_uart_io { u32 ulcon; /* UART line control register */ u32 ucon; /* UART control register */ u32 ufcon; /* UART FIFO control register */ u32 umcon; /* UART Modem control register */ u32 utrstat; /* UART Tx/Rx status register */ u32 uerstat; /* UART Rx error status register */ u32 ufstat; /* UART FIFO status register */ u32 umstat; /* UART Modem status register */ u32 utxh; /* UART transmit buffer register */ u32 urxh; /* UART receive buffer register */ u32 ubrdiv; /* Baud rate divisor register 0 */ }; #define UART_INT_RXD 0x1 #define UART_INT_TXD 0x2 #define UART_INT_EXD 0x4 #define UART_UCON_INIT 0x5 #define UART_ULCON_INIT 0x3 //8N1 #define UART_UTRSTAT_INIT 0x6 #endif /* __S3C2410X_H_ */ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_s3c2410x.c�����������������������������������������������0000644�0001750�0000144�00000040746�11006120657�020567� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_s3c2410x.c - define machine S3C2410X for skyeye Copyright (C) 2005 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "armdefs.h" #include "s3c2410x.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" typedef struct s3c2410_memctl_s{ uint32_t bwscon; uint32_t bankcon[8]; uint32_t refresh; uint32_t banksize; uint32_t mrsrb6; uint32_t mrsrb7; }s3c2410_memctl_t; typedef struct s3c2410_wd_timer_s{ uint32_t wtcon; uint32_t wtdat; uint32_t wtcnt; }s3c2410_wd_timer_t; typedef struct s3c2410x_io { u32 srcpnd; /* Indicate the interrupt request status */ u32 intmod; /* Interrupt mode register */ u32 intmsk; /* Determine which interrupt source is masked */ u32 priority; /* IRQ priority control register */ u32 intpnd; /* Indicate the interrupt request status */ u32 intoffset; /* Indicate the IRQ interrupt request source */ u32 subsrcpnd; /* Indicate the interrupt request status */ u32 intsubmsk; /* Determin which interrupt source is masked */ u32 eintmask; /* Interrupt pending register for 20 external interrupts (EINT[23:4]) */ u32 eintpend; /* Interrupt mask register for 20 external interrupts (EINT[23:4]). */ struct s3c2410x_timer_io timer; /* Timer */ struct s3c2410x_uart_io uart[3]; /* uart */ struct s3c2410x_clkpower clkpower; /* clock and power management */ s3c2410_memctl_t memctl; s3c2410_wd_timer_t wd_timer; uint32_t gpio_ctl[0xc0]; /* GPIO control register */ } s3c2410x_io_t; static s3c2410x_io_t s3c2410x_io; #define io s3c2410x_io static inline void s3c2410x_set_subsrcint (unsigned int irq) { io.subsrcpnd |= irq; } static inline void s3c2410x_update_subsrcint () { u32 requests; s3c2410x_set_subsrcint (UART_INT_TXD << (0 * 3)); s3c2410x_set_subsrcint (UART_INT_TXD << (1 * 3)); s3c2410x_set_subsrcint (UART_INT_TXD << (2 * 3)); requests = ((io.subsrcpnd & (~io.intsubmsk)) & 0x7fff); if (requests & 0x7) io.srcpnd |= INT_UART0; if (requests & 0x38) io.srcpnd |= INT_UART1; if (requests & 0x1c0) io.srcpnd |= INT_UART2; if (requests & 0x600) io.srcpnd |= INT_ADC; } static inline void s3c2410x_update_extint () { u32 requests = ((io.eintpend & (~io.eintmask))); if (requests & 0xF0) io.srcpnd |= INT_EINT4_7; if (requests & 0xFFFF00) io.srcpnd |= INT_EINT8_23; } static void s3c2410x_update_int (ARMul_State * state) { ARMword requests; s3c2410x_update_subsrcint (); s3c2410x_update_extint (); requests = io.srcpnd & (~io.intmsk & INT_MASK_INIT); state->NfiqSig = (requests & io.intmod) ? LOW : HIGH; state->NirqSig = (requests & ~io.intmod) ? LOW : HIGH; } static void s3c2410x_set_ext_intr (u32 interrupt) { io.eintpend |= (1 << interrupt); } static int s3c2410x_pending_ext_intr (u32 interrupt) { return ((io.eintpend & (1 << interrupt))); } static void s3c2410x_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; s3c2410x_update_int (state); } static void s3c2410x_io_reset (ARMul_State * state) { int i; memset (&s3c2410x_io, 0, sizeof (s3c2410x_io)); for (i = 0; i < 3; i++) { io.uart[i].ulcon = UART_ULCON_INIT; io.uart[i].utrstat = UART_UTRSTAT_INIT; } //io.timer.tcnt[4] = 25350; io.clkpower.locktime = 0x00FFFFFF; //io.clkpower.mpllcon = 0x00070022; /* That is a value mizi required */ io.clkpower.mpllcon = 0x0002c080; /* workaround for linux-2.6.10 by ksh */ io.clkpower.upllcon = 0x00028080; io.clkpower.clkcon = 0x7FFF0; io.clkpower.clkslow = 0x4; io.intmsk = INT_MASK_INIT; io.intpnd = 0x0; io.eintmask = 0x00FFFFF0; /* ARM920T uses LOW */ state->lateabtSig = LOW; state->Reg[1] = 193; //for SMDK2410 //state->Reg[1] = 395; //for SMDK2410TK //state->Reg[1] = 241; //ARCH_S3C2440 } /* s3c2410x io_do_cycle */ static void s3c2410x_io_do_cycle (ARMul_State * state) { int i; if ((io.timer.tcon & 0x100000) != 0) { io.timer.tcnt[4]--; if (io.timer.tcnt[4] < 0) { io.timer.tcnt[4] = io.timer.tcntb[4]; /*timer 4 hasn't tcmp */ //io.timer.tcmp[4] = io.timer.tcmpb[4]; io.timer.tcnto[4] = io.timer.tcntb[4]; io.srcpnd |= INT_TIMER4; s3c2410x_update_int (state); return; } } for (i = 0; i < 3; i++) { if (((io.uart[i].utrstat & 0x1) == 0x0) && ((io.uart[i].ucon & 0x3) == 0x1)) { struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if (skyeye_uart_read(i, &buf, 1, &tv, NULL) > 0) { /* convert ctrl+c to ctrl+a. */ if (buf == 1) buf = 3; io.uart[i].urxh = buf; /* Receiver Ready * */ io.uart[i].utrstat |= (0x1); io.uart[i].ufstat |= (0x1); /* 2007-02-09 by Anthony Lee : for 1 bytes */ /* pending usart0 interrupt * */ s3c2410x_set_subsrcint (UART_INT_RXD << (i * 3)); //io.srcpnd |= INT_UART0; s3c2410x_update_int (state); } } } //s3c2410x_update_int (state); } static void s3c2410x_uart_read (u32 offset, u32 * data, int index) { switch (offset) { case ULCON: *data = io.uart[index].ulcon; break; case UCON: *data = io.uart[index].ucon; break; case UFCON: *data = io.uart[index].ufcon; break; case UMCON: *data = io.uart[index].umcon; break; case UTRSTAT: *data = io.uart[index].utrstat; break; case UERSTAT: *data = io.uart[index].uerstat; break; case UFSTAT: *data = io.uart[index].ufstat; break; case UMSTAT: *data = io.uart[index].umstat; break; case URXH: /* receive char * */ *data = io.uart[index].urxh; io.uart[index].utrstat &= (~0x1); /* clear strstat register bit[0] */ io.uart[index].ufstat &= ~(0x1); /* 2007-02-09 by Anthony Lee : for 0 bytes */ break; case UBRDIV: *data = io.uart[index].ubrdiv; break; default: break; } SKYEYE_DBG ("%s(UART%d: 0x%x, 0x%x)\n", __FUNCTION__, index, offset, data); } static void s3c2410x_uart_write (ARMul_State * state, u32 offset, u32 data, int index) { SKYEYE_DBG ("%s(UART%d: 0x%x, 0x%x)\n", __FUNCTION__, index, offset, data); switch (offset) { case ULCON: io.uart[index].ulcon = data; break; case UCON: io.uart[index].ucon = data; break; case UFCON: io.uart[index].ufcon = data; break; case UMCON: io.uart[index].umcon = data; break; case UTRSTAT: io.uart[index].utrstat = data; break; case UERSTAT: io.uart[index].uerstat = data; break; case UFSTAT: io.uart[index].ufstat = data; break; case UMSTAT: io.uart[index].umstat = data; break; case UTXH: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(index, &c, 1, NULL); io.uart[index].utrstat |= 0x6; //set strstat register bit[0] if ((io.uart[index].ucon & 0xc) == 0x4) { s3c2410x_set_subsrcint (UART_INT_TXD << (index * 3)); s3c2410x_update_int (state); } } break; case UBRDIV: io.uart[index].ubrdiv = data; break; default: break; } } static void s3c2410x_timer_read (u32 offset, u32 * data) { switch (offset) { case TCFG0: *data = io.timer.tcfg0; break; case TCFG1: *data = io.timer.tcfg1; break; case TCON: *data = io.timer.tcon; break; case TCNTB0: case TCNTB1: case TCNTB2: case TCNTB3: case TCNTB4: { int n = (offset - 0xC) / 0xC; *data = io.timer.tcntb[n]; } break; case TCMPB0: case TCMPB1: case TCMPB2: case TCMPB3: { int n = (offset - 0x10) / 0xC; *data = io.timer.tcmpb[n]; } break; case TCNTO0: case TCNTO1: case TCNTO2: case TCNTO3: { int n = (offset - 0x10) / 0xC; *data = io.timer.tcnto[n]; } break; case TCNTO4: *data = io.timer.tcnt[4]; break; default: break; } } static void s3c2410x_timer_write (ARMul_State * state, u32 offset, u32 data) { switch (offset) { case TCFG0: io.timer.tcfg0 = data; break; case TCFG1: io.timer.tcfg1 = data; break; case TCON: { io.timer.tcon = data; if (io.timer.tcon) { } } break; case TCNTB0: case TCNTB1: case TCNTB2: case TCNTB3: case TCNTB4: { int n = (offset - 0xC) / 0xC; //io.timer.tcntb[n] = data; /* temp data taken from linux source */ io.timer.tcntb[n] = 25350 / 20; } break; case TCMPB0: case TCMPB1: case TCMPB2: case TCMPB3: { int n = (offset - 0x10) / 0xC; io.timer.tcmpb[n] = data; } break; default: break; } } static ARMword s3c2410x_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = -1; int i; /* uart */ if ((addr >= UART_CTL_BASE0) && (addr < (UART_CTL_BASE0 + UART_CTL_SIZE))) { s3c2410x_uart_read ((u32) ((addr - UART_CTL_BASE0) % 0x4000), (u32 *) & data, (addr - UART_CTL_BASE0) / 0x4000); return data; } if ((addr >= PWM_CTL_BASE) && (addr < (PWM_CTL_BASE + PWM_CTL_SIZE))) { s3c2410x_timer_read ((u32) (addr - PWM_CTL_BASE), (u32 *) & data); return data; } /* * 2007-02-09 by Anthony Lee * changed 0xC0 to 0xA4 for running linux-2.6.20, * because GSTATUS1 is 0xB0, the "0xC0" make it like S3C2400 */ if((addr >= GPIO_CTL_BASE) && (addr < (GPIO_CTL_BASE + 0xA4))){ int offset = addr - GPIO_CTL_BASE; return io.gpio_ctl[offset]; } switch (addr) { case SRCPND: data = io.srcpnd; break; case INTMOD: data = io.intmod; break; case INTMSK: data = io.intmsk; break; case PRIORITY: data = io.priority; break; case INTPND: case INTOFFSET: { /*find which interrupt is pending */ int i; for (i = 0; i < 32; i++) { if (io.srcpnd & (1 << i)) break; } if (i < 32) { io.intoffset = i; io.intpnd = (1 << i); if (addr == INTPND) data = (1 << i); else data = i; } else data = 0; } io.intpnd = (1 << io.intoffset); //printf ("io.intoffset:%x, io.intpnd:%x (0x%08x) = 0x%08x\n", io.intoffset, io.intpnd, addr, data); break; case SUBSRCPND: data = io.subsrcpnd; break; case INTSUBMSK: data = io.intsubmsk; break; case EINTMASK: data = io.eintmask; break; case EINTPEND: data = io.eintpend; break; /* GPIO Register */ case GSTATUS1: data = 0x32410000; break; /* Clock and Power Management Registers */ case LOCKTIME: data = io.clkpower.locktime; break; case MPLLCON: data = io.clkpower.mpllcon; break; case UPLLCON: data = io.clkpower.upllcon; break; case CLKCON: data = io.clkpower.clkcon; break; case CLKSLOW: data = io.clkpower.clkslow; break; case CLKDIVN: data = io.clkpower.clkdivn; break; case BWSCON: data = io.memctl.bwscon; break; case BANKCON0: data = io.memctl.bankcon[0]; break; case BANKCON1: data = io.memctl.bankcon[1]; break; case BANKCON2: data = io.memctl.bankcon[2]; break; case BANKCON3: data = io.memctl.bankcon[3]; break; case BANKCON4: data = io.memctl.bankcon[4]; break; case BANKCON5: data = io.memctl.bankcon[5]; break; case BANKCON6: data = io.memctl.bankcon[6]; break; case BANKCON7: data = io.memctl.bankcon[7]; break; case REFRESH: data = io.memctl.refresh; break; case BANKSIZE: data = io.memctl.banksize; break; case MRSRB6: data = io.memctl.mrsrb6; break; case MRSRB7: data = io.memctl.mrsrb7; break; case WDCON: data = io.wd_timer.wtcon; break; case WDDAT: data = io.wd_timer.wtdat; break; case WDCNT: data = io.wd_timer.wtcnt; break; default: //fprintf(stderr, "ERROR: %s(0x%08x) \n", __FUNCTION__, addr); break; } return data; } static ARMword s3c2410x_io_read_byte (ARMul_State * state, ARMword addr) { s3c2410x_io_read_word (state, addr); } static ARMword s3c2410x_io_read_halfword (ARMul_State * state, ARMword addr) { s3c2410x_io_read_word (state, addr); } static void s3c2410x_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { if ((addr >= UART_CTL_BASE0) && (addr < UART_CTL_BASE0 + UART_CTL_SIZE)) { s3c2410x_uart_write (state, (addr - UART_CTL_BASE0) % 0x4000, data, (addr - UART_CTL_BASE0) / 0x4000); return; } if ((addr >= PWM_CTL_BASE) && (addr < (PWM_CTL_BASE + PWM_CTL_SIZE))) { s3c2410x_timer_write (state, addr - PWM_CTL_BASE, data); return; } /* * 2007-02-09 by Anthony Lee * changed 0xC0 to 0xA4 for running linux-2.6.20, * because GSTATUS1 is 0xB0, the "0xC0" make it like S3C2400 */ if((addr >= GPIO_CTL_BASE) && (addr < (GPIO_CTL_BASE + 0xA4))){ int offset = addr - GPIO_CTL_BASE; io.gpio_ctl[offset] = data; return; } switch (addr) { case SRCPND: io.srcpnd &= (~data & INT_MASK_INIT); //2006-04-04 chy, for eCos on s3c2410. SRCPND will change the INTPND, INTOFFSET, so when write SRCPND, the interrupt should be update s3c2410x_update_int (state); break; case INTMOD: io.intmod = data; break; case INTMSK: io.intmsk = data; s3c2410x_update_int (state); break; case PRIORITY: io.priority = data; break; case INTPND: io.intpnd &= (~data & INT_MASK_INIT); io.intoffset = 0; //printf ("io.intoffset:%x, io.intpnd:%x (0x%08x) = 0x%08x, pc:%x\n", io.intoffset, io.intpnd, addr, data, state->pc); break; /*read only */ //case INTOFFSET: // break; case SUBSRCPND: io.subsrcpnd &= (~data & INT_SUBMSK_INIT); break; case INTSUBMSK: io.intsubmsk = data; break; /* ext interrupt */ case EINTMASK: io.eintmask = data; break; case EINTPEND: io.eintpend &= (~data & 0x00FFFFF0); break; case CLKCON: io.clkpower.clkcon = data; break; case CLKSLOW: io.clkpower.clkslow = data; break; case CLKDIVN: io.clkpower.clkdivn = data; break; case BWSCON: io.memctl.bwscon = data; break; case MPLLCON: io.clkpower.mpllcon = data; break; case BANKCON0: io.memctl.bankcon[0] = data; break; case BANKCON1: io.memctl.bankcon[1] = data; break; case BANKCON2: io.memctl.bankcon[2] = data; break; case BANKCON3: io.memctl.bankcon[3] = data; break; case BANKCON4: io.memctl.bankcon[4] = data; break; case BANKCON5: io.memctl.bankcon[5] = data; break; case BANKCON6: io.memctl.bankcon[6] = data; break; case BANKCON7: io.memctl.bankcon[7] = data; break; case REFRESH: io.memctl.refresh = data; break; case BANKSIZE: io.memctl.banksize = data; break; case MRSRB6: io.memctl.mrsrb6 = data; break; case MRSRB7: io.memctl.mrsrb7 = data; break; case WDCON: io.wd_timer.wtcon = data; break; case WDDAT: io.wd_timer.wtdat = data; break; case WDCNT: io.wd_timer.wtcnt = data; break; default: SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data); fprintf(stderr, "ERROR: %s(0x%08x) = 0x%08x\n", __FUNCTION__, addr ,data); break; } } static void s3c2410x_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: s3c2410x_io_write_byte error\n"); s3c2410x_io_write_word (state, addr, data); } static void s3c2410x_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: s3c2410x_io_write_halfword error\n"); s3c2410x_io_write_word (state, addr, data); } void s3c2410x_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v4_Prop); this_mach->mach_io_do_cycle = s3c2410x_io_do_cycle; this_mach->mach_io_reset = s3c2410x_io_reset; this_mach->mach_io_read_byte = s3c2410x_io_read_byte; this_mach->mach_io_write_byte = s3c2410x_io_write_byte; this_mach->mach_io_read_halfword = s3c2410x_io_read_halfword; this_mach->mach_io_write_halfword = s3c2410x_io_write_halfword; this_mach->mach_io_read_word = s3c2410x_io_read_word; this_mach->mach_io_write_word = s3c2410x_io_write_word; this_mach->mach_update_int = s3c2410x_update_int; this_mach->mach_set_intr = s3c2410x_set_ext_intr; this_mach->mach_pending_intr = s3c2410x_pending_ext_intr; this_mach->mach_update_intr = s3c2410x_update_intr; this_mach->state = (void *) state; } ��������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_9238imx.c������������������������������������������������0000644�0001750�0000144�00000010674�10642317035�020523� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_imx.c - imx machine simulation Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/02/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include "armdefs.h" typedef struct imx_timer_s{ uint32_t tctl; uint32_t tprer; uint32_t tcmp; uint32_t tcr; uint32_t tcn; uint32_t tstat; }imx_timer_t; typedef struct imx_uart_s{ uint32_t urx; uint32_t utx; uint32_t ucr[4]; uint32_t ufcr; uint32_t usr[2]; uint32_t uesc; uint32_t utim; uint32_t ubir; uint32_t ubmr; uint32_t ubrc; uint32_t bipr[4]; uint32_t bmpr[4]; uint32_t uts; }imx_uart_t; typedef struct imx_aitc_s{ uint32_t intcntl; uint32_t nimask; uint32_t intennum; uint32_t intdisnum; uint32_t intenableh; uint32_t intenablel; uint32_t inttypeh; uint32_t inttypel; uint32_t nipriority[8]; uint32_t nivecsr; uint32_t fivecsr; uint32_t intsrch; uint32_t intsrcl; uint32_t intfrch; uint32_t intfrcl; uint32_t nipndh; uint32_t nipndl; uint32_t fipndh; uint32_t fipndl; }imx_aitc_t; typedef struct imx_io_s{ imx_timer_t timer[2]; imx_uart_t uart[3]; imx_aitc_t aitc; }imx_io_t; void imx_io_do_cycle(){} static ARMword aitc_read_word(void * state, ARMword addr){ int offset = addr - 0x00223000; ARMword data; switch(offset){ default: fprintf(stderr, "io error in %s, addr=0x%x\n", __FUNCTION__, addr); skyeye_exit(-1); } return data; } static void aitc_write_word(void * state, ARMword addr, ARMword data){ int offset = addr - 0x00223000; switch(offset){ default: fprintf(stderr, "io error in %s, addr=0x%x\n", __FUNCTION__, addr); skyeye_exit(-1); } return; } static ARMword imx_io_read_word (void * state, ARMword addr) { ARMword data; switch(addr){ default: fprintf(stderr, "io error in %s, addr=0x%x\n", __FUNCTION__, addr); skyeye_exit(-1); } return data; } static ARMword imx_io_read_byte (void * state, ARMword addr) { return imx_io_read_word (state, addr); } ARMword imx_io_read_halfword (void * state, ARMword addr) { return imx_io_read_word (state, addr); } void imx_io_write_word (void * state, ARMword addr, ARMword data) { /* * The imx system registers */ if(addr >= 0x0022300 && addr <= 0x00223064) return aitc_write_word(state, addr, data); switch(addr){ default: fprintf(stderr, "io error in %s, addr=0x%x\n", __FUNCTION__, addr); skyeye_exit(-1); } return ; } void imx_io_write_byte (void * state, ARMword addr, ARMword data) { imx_io_write_word (state, addr, data); //SKYEYE_OUTREGS(stderr); //exit(-1); } void imx_io_write_halfword (void * state, ARMword addr, ARMword data) { imx_io_write_word (state, addr, data); //SKYEYE_OUTREGS(stderr); //exit(-1); } static void imx_io_reset (void * curr_state) { } void imx_mach_init (ARMul_State * state, machine_config_t * this_mach) { //chy 2003-08-19, setprocessor ARMul_SelectProcessor (state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; state->Reg[1] = 160; /* MACH_TYPE_MX1ADS 160 */ this_mach->mach_io_do_cycle = imx_io_do_cycle; this_mach->mach_io_reset = imx_io_reset; this_mach->mach_io_read_byte = imx_io_read_byte; this_mach->mach_io_write_byte = imx_io_write_byte; this_mach->mach_io_read_halfword = imx_io_read_halfword; this_mach->mach_io_write_halfword = imx_io_write_halfword; this_mach->mach_io_read_word = imx_io_read_word; this_mach->mach_io_write_word = imx_io_write_word; //this_mach->mach_update_int = imx_update_int; } ��������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_lpc.c����������������������������������������������������0000644�0001750�0000144�00000033466�10634527266�020174� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_lpc.c - define machine lpc for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 3/24/2003 init this file. * add machine lpc's function.Most taken from original armio.c * include: lpc_mach_init, lpc_io_do_cycle * lpc_io_read_word, lpc_io_write_word * walimis <walimi@peoplemail.com.cn> * *3/24/2003 chenyu <chenyu-tmlinux@hpclab.cs.tsinghua.edu.cn> has done the * necessary work to armio.c * */ #include "armdefs.h" #include "lpc.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" //teawater add for arm2x86 2005.03.18------------------------------------------- //make gcc-3.4 can compile this file ARMword lpc_io_read_word (ARMul_State * state, ARMword addr); void lpc_io_write_word (ARMul_State * state, ARMword addr, ARMword data); //AJ2D-------------------------------------------------------------------------- #define DEBUG 0 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr, ##a) #else #define DBG_PRINT(a...) #endif typedef struct timer { ARMword ir; ARMword tcr; ARMword tc; ARMword pr; ARMword pc; ARMword mcr; ARMword mr0; ARMword mr1; ARMword mr2; ARMword mr3; ARMword ccr; ARMword cr0; ARMword cr1; ARMword cr2; ARMword cr3; ARMword emr; } lpc_timer_t; typedef struct uart { ARMword rbr; ARMword thr; ARMword ier; ARMword iir; ARMword fcr; ARMword lcr; ARMword lsr; ARMword msr; ARMword scr; ARMword dll; ARMword dlm; char t_fifo[16]; char r_fifo[16]; } lpc_uart_t; typedef struct pll { ARMword con; ARMword cfg; ARMword stat; ARMword feed; } lpc_pll_t; typedef struct vic { ARMword isr; ARMword fsr; ARMword risr; ARMword islr; ARMword ier; ARMword iecr; ARMword sir; ARMword sicr; ARMword per; ARMword var; ARMword dvar; ARMword va[15]; ARMword vc[15]; } lpc_vic_t; typedef struct lpc_io { ARMword syscon; /* System control */ ARMword sysflg; /* System status flags */ lpc_pll_t pll; lpc_timer_t timer[2]; lpc_vic_t vic; ARMword pinsel0; lpc_uart_t uart[2]; /* Receive data register */ ARMword memmap; /*Memory mapping control register */ } lpc_io_t; static lpc_io_t lpc_io; #define io lpc_io static void lpc_update_int (ARMul_State * state) { u32 irq = 0; // state->NfiqSig = (~(io.vic.risr&io.vic.ier& io.vic.)) ? LOW : HIGH; irq = io.vic.risr & io.vic.ier; io.vic.isr = irq & ~io.vic.islr; io.vic.fsr = irq & io.vic.islr; if (io.vic.isr & IRQ_UART0) { io.vic.var = io.vic.va[6]; } if (io.vic.isr & IRQ_TC0) { io.vic.var = io.vic.va[4]; } state->NirqSig = io.vic.isr ? LOW : HIGH; state->NfiqSig = io.vic.fsr ? LOW : HIGH; } static void lpc_io_reset (ARMul_State * state) { io.timer[0].pr = 500000; /*prescale value */ io.vic.isr = 0; io.vic.fsr = 0; io.vic.risr = 0; io.uart[0].lsr = 0x60; io.uart[0].iir = 0x01; io.pinsel0 = 0; } /*lpc io_do_cycle*/ void lpc_io_do_cycle (ARMul_State * state) { int t; io.timer[0].pc++; io.timer[1].pc++; if (!(io.vic.risr & IRQ_TC0)) { if (io.timer[0].pc >= io.timer[0].pr + 1) { // if (io.timer[0].pc >= 5000+1) { io.timer[0].tc++; io.timer[0].pc = 0; if (io.timer[0].tc == io.timer[0].mr0) { // if(io.timer[0].tc == 20){ io.vic.risr |= IRQ_TC0; io.timer[0].tc = 0; } lpc_update_int (state); } } if (io.timer[0].pc == 0) { if (!(io.vic.risr & IRQ_UART0)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { //printf("SKYEYE:get input is %c\n",buf); io.uart[0].rbr = buf; io.uart[0].lsr |= 0x1; io.vic.risr |= IRQ_UART0; lpc_update_int (state); } } /* if (rcr > 0 && ... */ } } ARMword lpc_fix_int (ARMword val) { /* ARMword ret = 0; if (val & (1 << 2)) ret |= URXINT; if (val & (1 << 5)) ret |= TC1OI; if (val & (1 << 6)) ret |= TC2OI; if (val & (1 << 16)) ret |= AT91_EXT0;*/ return (val); } ARMword lpc_unfix_int (ARMword val) { /* ARMword ret = 0; if (val & URXINT) ret |= (1 << 2); if (val & TC1OI) ret |= (1 << 5); if (val & TC2OI) ret |= (1 << 6); if (val & AT91_EXT0) ret |= (1 << 16); */ return (val); } ARMword lpc_uart_read (ARMul_State * state, ARMword addr, int i) { ARMword data; //printf("lpc_uart_read,addr=%x\n",addr); switch ((addr & 0xfff) >> 2) { case 0x0: // RbR io.uart[i].lsr &= ~0x1; if (i == 0) io.vic.risr &= ~IRQ_UART0; else io.vic.risr &= ~IRQ_UART1; lpc_update_int (state); data = io.uart[i].rbr; break; case 0x1: // ier data = io.uart[i].ier; break; case 0x2: // iir data = io.uart[i].iir; break; case 0x3: // IDR case 0x4: // IMR case 0x5: // LSR data = io.uart[i].lsr; break; case 0x6: // MSR data = io.uart[i].msr; break; case 0x7: // SCR data = io.uart[i].scr; break; default: DBG_PRINT ("uart_read(%s=0x%08x)\n", "uart_reg", addr); break; } return (data); } void lpc_uart_write (ARMul_State * state, ARMword addr, ARMword data, int i) { static ARMword tx_buf = 0; //DBG_PRINT("uart_write(0x%x, 0x%x)\n", (addr & 0xfff) >> 2, data); switch ((addr & 0xfff) >> 2) { case 0x0: // THR { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); //io.uart[0].lsr |= 0x40; io.uart[0].lsr |= 0x20; } case 0x2: //FCR { io.uart[i].fcr = data; break; } case 0x7: // SCR io.uart[i].scr = data; break; default: //printf("%c", data); fflush(stdout); DBG_PRINT ("uart_write(%s=0x%08x)\n", "uart_reg", addr); break; } } ARMword lpc_io_read_word (ARMul_State * state, ARMword addr) { /* * * The LPC system registers * */ ARMword data = -1; static ARMword current_ivr = 0; /* mega hack, 2.0 needs this */ int i; ARMword dataimr = 0; switch (addr) { case 0xfffff000: /* ISR */ // data = unfix_int(io.intsr); // dataimr = unfix_int(io.intmr); data = io.vic.isr; DBG_PRINT ("read ISR=%d\n", data); break; case 0xfffff004: /* interrupt status register */ data = io.vic.fsr; DBG_PRINT ("SKYEYE:read ISR=%x,%x\n", data, io.vic.fsr); break; case 0xfffff008: /* IMR */ data = io.vic.risr; break; case 0xfffff00c: /* CORE interrupt status register */ data = io.vic.islr; break; case 0xfffff010: /* IER */ data = io.vic.ier; DBG_PRINT ("read IER=%x,after update ier=%x\n", data, io.vic.ier); break; case 0xfffff014: /* IECR */ data = io.vic.iecr; lpc_update_int (state); break; case 0xfffff034: /* DVAR */ data = io.vic.dvar; break; case 0xfffff030: /* VAR */ data = io.vic.var; break; /*Timer0 */ case 0xe0004000: data = io.timer[0].ir; break; case 0xe0004004: data = io.timer[0].tcr; break; case 0xe0004008: data = io.timer[0].tc; //io.vic.risr &= ~IRQ_TC0; //printf("SKYEYE:Clear TC Interrupt,tc=%x,risr=%x,\n",data,io.vic.risr); //lpc_update_int(state); break; case 0xe000400c: data = io.timer[0].pr; break; case 0xe0004010: data = io.timer[0].pc; break; case 0xe0004014: data = io.timer[0].mcr; break; case 0xe0004018: data = io.timer[0].mr0; break; /*pll*/ case 0xe01fc080: data = io.pll.con; break; case 0xe01fc084: data = io.pll.cfg; break; case 0xe01fc088: data = io.pll.stat; break; case 0xe01fc08c: data = io.pll.feed; case 0xe002c000: data = io.pinsel0; break; default: if (addr >= 0xe000c000 && addr <= 0xe000c01c) { data = lpc_uart_read (state, addr, 0); break; } if (addr >= 0xe0001000 && addr <= 0xe000101c) { data = lpc_uart_read (state, addr, 1); break; } if (addr - 0xfffff100 <= 0x3c && addr - 0xfffff100 >= 0) { data = io.vic.va[(addr - 0xfffff100) / 4]; break; } if (addr - 0xfffff200 <= 0x3c && addr - 0xfffff200 >= 0) { data = io.vic.vc[(addr - 0xfffff200) / 4]; break; } printf ("ERROR:io_read: addr = %x\n", addr); /*fprintf(stderr,"NumInstr %llu, io_read_word unknown addr(0x%08x) = 0x%08x\n", state->NumInstrs, addr, data); */ SKYEYE_OUTREGS (stderr); //ARMul_Debug(state, 0, 0); break; } return data; } ARMword lpc_io_read_byte (ARMul_State * state, ARMword addr) { return lpc_io_read_word (state, addr); // SKYEYE_OUTREGS(stderr); //exit(-1); } ARMword lpc_io_read_halfword (ARMul_State * state, ARMword addr) { return lpc_io_read_word (state, addr); //SKYEYE_OUTREGS(stderr); //exit(-1); } void lpc_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { /* * The lpc system registers */ switch (addr) { case 0xfffff000: /* ISR */ DBG_PRINT ("SKYEYE:can not write ISR,it is RO,=%d\n", data); break; case 0xfffff004: /* interrupt status register */ //io.vic.fsr = data ; // DBG_PRINT("read ISR=%x,%x\n", data, io.intsr); DBG_PRINT ("can not write fsr,it is RO,=%d\n", data); break; case 0xfffff008: /* IMR */ //io.vic.risr = data; DBG_PRINT ("can not write risr,it is RO,=%d\n", data); break; case 0xfffff00c: /* CORE interrupt status register */ io.vic.islr = data; break; case 0xfffff010: /* IER */ io.vic.ier = data; io.vic.iecr = ~data; lpc_update_int (state); // data = unfix_int(io.intmr); DBG_PRINT ("write IER=%x,after update ier=%x\n", data, io.vic.ier); break; case 0xfffff014: /* IECR */ io.vic.iecr = data; io.vic.ier = ~data; lpc_update_int (state); break; case 0xfffff018: /* SIR */ io.vic.sir = data; break; case 0xfffff01c: /* SICR */ io.vic.sicr = data; break; case 0xfffff020: /* PER */ io.vic.per = data; break; case 0xfffff030: /* VAR */ io.vic.var = data; break; case 0xfffff034: /* DVAR */ io.vic.dvar = data; break; /*Timer0 */ case 0xe0004000: io.timer[0].ir = data; if (io.timer[0].ir & 0x1) { io.timer[0].ir &= 0x0; io.vic.risr &= ~IRQ_TC0; } lpc_update_int (state); break; case 0xe0004004: io.timer[0].tcr = data; break; case 0xe0004008: io.timer[0].tc = data; break; case 0xe000400c: io.timer[0].pr = data; break; case 0xe0004010: io.timer[0].pc = data; break; case 0xe0004014: io.timer[0].mcr = data; break; case 0xe0004018: io.timer[0].mr0 = data; break; /*pll */ case 0xe01fc080: io.pll.con = data; break; case 0xe01fc084: io.pll.cfg = data; break; case 0xe01fc088: io.pll.stat = data; break; case 0xe01fc08c: io.pll.feed = data; break; /*memory map control */ case 0xe01fc040: io.memmap = data; switch(io.memmap & 0x3){ #if 0 case 0: /* Bootloader mode, vector is remaped to Boot Block */ case 1: /* User Flash mode, vector is not remapped */ case 3: /* User external memory module, vector is remapped to external memory */ #endif case 2: /* User ram mode, vector is remapped to static ram */ state->vector_remap_flag = 1; state->vector_remap_addr = 0x40000000; break; default: printf ("ERROR:io_write memmap register to invalid value: data = %x\n", data); } break; case 0xe002c000: io.pinsel0 = data; break; default: if (addr >= 0xe000c000 && addr <= 0xe000c01c) { lpc_uart_write (state, addr, data, 0); break; } if (addr >= 0xe0001000 && addr <= 0xe000101c) { lpc_uart_write (state, addr, data, 1); break; } if (addr - 0xfffff100 <= 0x3c && addr - 0xfffff100 >= 0) { io.vic.va[(addr - 0xfffff100) / 4] = data; break; } if (addr - 0xfffff200 <= 0x3c && addr - 0xfffff200 >= 0) { io.vic.vc[(addr - 0xfffff200) / 4] = data; break; } printf ("ERROR:io_write a non-exsiting addr:addr = %x, data = %x\n", addr, data); /* fprintf(stderr,"NumInstr %llu,io_write_word unknown addr(1x%08x) = 0x%08x\n", state->NumInstrs, addr, data); */ //SKYEYE_OUTREGS(stderr); //ARMul_Debug(state, 0, 0); break; } } void lpc_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { lpc_io_write_word (state, addr, data); //SKYEYE_OUTREGS(stderr); //exit(-1); } void lpc_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { lpc_io_write_word (state, addr, data); //SKYEYE_OUTREGS(stderr); //exit(-1); } void lpc_mach_init (ARMul_State * state, machine_config_t * this_mach) { //chy 2003-08-19, setprocessor ARMul_SelectProcessor (state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; this_mach->mach_io_do_cycle = lpc_io_do_cycle; this_mach->mach_io_reset = lpc_io_reset; this_mach->mach_io_read_byte = lpc_io_read_byte; this_mach->mach_io_write_byte = lpc_io_write_byte; this_mach->mach_io_read_halfword = lpc_io_read_halfword; this_mach->mach_io_write_halfword = lpc_io_write_halfword; this_mach->mach_io_read_word = lpc_io_read_word; this_mach->mach_io_write_word = lpc_io_write_word; this_mach->mach_update_int = lpc_update_int; //ksh 2004-2-7 state->mach_io.instr = (ARMword *) & io.vic.isr; //*state->io.instr = (ARMword *)&io.intsr; //state->io->net_flags = (ARMword *)&io.net_flags; //state->mach_io.net_int = (ARMword *)&io.net_int; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/lpc.h����������������������������������������������������������������0000644�0001750�0000144�00000102457�10541455476�015615� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* one part from clps7110 and another from at91. * should modify it only for at91. * walimis. 2003/7/18 * */ /* * linux/include/asm-arm/arch-lpc/hardware.h * for lpc * 2004-06-19 added by ksh,tsinghua */ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H /* 0=TC0, 1=TC1*/ #define KERNEL_TIMER 0 #define LPC_TC_BASE 0xe0004000 /* * added by ksh,2004-06-18,defined interrupt register */ #define VIC_BASE 0xfffff000 #define VIC_ISR (VIC_BASE+0x000) #define VIC_FSR (VIC_BASE+0x004) #define VIC_RISR (VIC_BASE+0x008) #define VIC_ISLR (VIC_BASE+0x00c) //interrupt select register #define VIC_IER (VIC_BASE+0x010) #define VIC_IECR (VIC_BASE+0x014) #define VIC_SIR (VIC_BASE+0x018) #define VIC_SICR (VIC_BASE+0x01c) #define VIC_PER (VIC_BASE+0x020) #define VIC_DVAR (VIC_BASE+0x030) #define VIC_VAR(i) (VIC_BASE+0x100+i*4) #define VIC_VCR(i) (VIC_BASE+0x200+i*4) /* EXTERNAL MEMORY CONTROLLER (EMC) */ /* Íⲿ×ÜÏß¿ØÖÆÆ÷ */ #define BCFG0 (*((volatile unsigned int *) 0xFFE00000)) /* lpc22xx only */ #define BCFG1 (*((volatile unsigned int *) 0xFFE00004)) /* lpc22xx only */ #define BCFG2 (*((volatile unsigned int *) 0xFFE00008)) /* lpc22xx only */ #define BCFG3 (*((volatile unsigned int *) 0xFFE0000C)) /* lpc22xx only */ /* External Interrupts */ /* ÍⲿÖжϿØÖƼĴæÆ÷ */ #define EXTINT (*((volatile unsigned char *) 0xE01FC140)) #define EXTWAKE (*((volatile unsigned char *) 0xE01FC144)) #define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x */ #define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x */ /* SMemory mapping control. */ /* ÄÚ´æremap¿ØÖƼĴæÆ÷ */ #define MEMMAP (*((volatile unsigned int *) 0xE01FC040)) /* Phase Locked Loop (PLL) */ /* PLL¿ØÖƼĴæÆ÷ */ #define PLLCON (*((volatile unsigned char *) 0xE01FC080)) #define PLLCFG (*((volatile unsigned char *) 0xE01FC084)) #define PLLSTAT (*((volatile unsigned short*) 0xE01FC088)) #define PLLFEED (*((volatile unsigned char *) 0xE01FC08C)) /* Power Control */ /* ¹¦ÂÊ¿ØÖƼĴæÆ÷ */ #define PCON (*((volatile unsigned char *) 0xE01FC0C0)) #define PCONP (*((volatile unsigned int *) 0xE01FC0C4)) /* VPB Divider */ /* VLSIÍâÉè×ÜÏߣ¨VPB£©·ÖƵ¼Ä´æÆ÷ */ #define VPBDIV (*((volatile unsigned char *) 0xE01FC100)) /* Memory Accelerator Module (MAM) */ /* ´æ´¢Æ÷¼ÓËÙÄ£¿é */ #define MAMCR (*((volatile unsigned char *) 0xE01FC000)) #define MAMTIM (*((volatile unsigned char *) 0xE01FC004)) /* Vectored Interrupt Controller (VIC) */ /* ÏòÁ¿ÖжϿØÖÆÆ÷(VIC)µÄÌØÊâ¼Ä´æÆ÷ */ #define VICIRQStatus (*((volatile unsigned int *) 0xFFFFF000)) #define VICFIQStatus (*((volatile unsigned int *) 0xFFFFF004)) #define VICRawIntr (*((volatile unsigned int *) 0xFFFFF008)) #define VICIntSelect (*((volatile unsigned int *) 0xFFFFF00C)) #define VICIntEnable (*((volatile unsigned int *) 0xFFFFF010)) #define VICIntEnClr (*((volatile unsigned int *) 0xFFFFF014)) #define VICSoftInt (*((volatile unsigned int *) 0xFFFFF018)) #define VICSoftIntClear (*((volatile unsigned int *) 0xFFFFF01C)) #define VICProtection (*((volatile unsigned int *) 0xFFFFF020)) #define VICVectAddr (*((volatile unsigned int *) 0xFFFFF030)) #define VICDefVectAddr (*((volatile unsigned int *) 0xFFFFF034)) #define VICVectAddr0 (*((volatile unsigned int *) 0xFFFFF100)) #define VICVectAddr1 (*((volatile unsigned int *) 0xFFFFF104)) #define VICVectAddr2 (*((volatile unsigned int *) 0xFFFFF108)) #define VICVectAddr3 (*((volatile unsigned int *) 0xFFFFF10C)) #define VICVectAddr4 (*((volatile unsigned int *) 0xFFFFF110)) #define VICVectAddr5 (*((volatile unsigned int *) 0xFFFFF114)) #define VICVectAddr6 (*((volatile unsigned int *) 0xFFFFF118)) #define VICVectAddr7 (*((volatile unsigned int *) 0xFFFFF11C)) #define VICVectAddr8 (*((volatile unsigned int *) 0xFFFFF120)) #define VICVectAddr9 (*((volatile unsigned int *) 0xFFFFF124)) #define VICVectAddr10 (*((volatile unsigned int *) 0xFFFFF128)) #define VICVectAddr11 (*((volatile unsigned int *) 0xFFFFF12C)) #define VICVectAddr12 (*((volatile unsigned int *) 0xFFFFF130)) #define VICVectAddr13 (*((volatile unsigned int *) 0xFFFFF134)) #define VICVectAddr14 (*((volatile unsigned int *) 0xFFFFF138)) #define VICVectAddr15 (*((volatile unsigned int *) 0xFFFFF13C)) #define VICVectCntl0 (*((volatile unsigned int *) 0xFFFFF200)) #define VICVectCntl1 (*((volatile unsigned int *) 0xFFFFF204)) #define VICVectCntl2 (*((volatile unsigned int *) 0xFFFFF208)) #define VICVectCntl3 (*((volatile unsigned int *) 0xFFFFF20C)) #define VICVectCntl4 (*((volatile unsigned int *) 0xFFFFF210)) #define VICVectCntl5 (*((volatile unsigned int *) 0xFFFFF214)) #define VICVectCntl6 (*((volatile unsigned int *) 0xFFFFF218)) #define VICVectCntl7 (*((volatile unsigned int *) 0xFFFFF21C)) #define VICVectCntl8 (*((volatile unsigned int *) 0xFFFFF220)) #define VICVectCntl9 (*((volatile unsigned int *) 0xFFFFF224)) #define VICVectCntl10 (*((volatile unsigned int *) 0xFFFFF228)) #define VICVectCntl11 (*((volatile unsigned int *) 0xFFFFF22C)) #define VICVectCntl12 (*((volatile unsigned int *) 0xFFFFF230)) #define VICVectCntl13 (*((volatile unsigned int *) 0xFFFFF234)) #define VICVectCntl14 (*((volatile unsigned int *) 0xFFFFF238)) #define VICVectCntl15 (*((volatile unsigned int *) 0xFFFFF23C)) /* Pin Connect Block */ /* ¹Ü½ÅÁ¬½ÓÄ£¿é¿ØÖƼĴæÆ÷ */ #define PINSEL0 (*((volatile unsigned int *) 0xE002C000)) #define PINSEL1 (*((volatile unsigned int *) 0xE002C004)) #define PINSEL2 (*((volatile unsigned int *) 0xE002C014)) /* no in lpc210x */ /* General Purpose Input/Output (GPIO) */ /* ͨÓò¢ÐÐIO¿ÚµÄÌØÊâ¼Ä´æÆ÷ */ #define IOPIN (*((volatile unsigned int *) 0xE0028000)) /* lpc210x only */ #define IOSET (*((volatile unsigned int *) 0xE0028004)) /* lpc210x only */ #define IODIR (*((volatile unsigned int *) 0xE0028008)) /* lpc210x only */ #define IOCLR (*((volatile unsigned int *) 0xE002800C)) /* lpc210x only */ #define IO0PIN (*((volatile unsigned int *) 0xE0028000)) /* no in lpc210x */ #define IO0SET (*((volatile unsigned int *) 0xE0028004)) /* no in lpc210x */ #define IO0DIR (*((volatile unsigned int *) 0xE0028008)) /* no in lpc210x */ #define IO0CLR (*((volatile unsigned int *) 0xE002800C)) /* no in lpc210x */ #define IO1PIN (*((volatile unsigned int *) 0xE0028010)) /* no in lpc210x */ #define IO1SET (*((volatile unsigned int *) 0xE0028014)) /* no in lpc210x */ #define IO1DIR (*((volatile unsigned int *) 0xE0028018)) /* no in lpc210x */ #define IO1CLR (*((volatile unsigned int *) 0xE002801C)) /* no in lpc210x */ #define IO2PIN (*((volatile unsigned int *) 0xE0028020)) /* lpc22xx only */ #define IO2SET (*((volatile unsigned int *) 0xE0028024)) /* lpc22xx only */ #define IO2DIR (*((volatile unsigned int *) 0xE0028028)) /* lpc22xx only */ #define IO2CLR (*((volatile unsigned int *) 0xE002802C)) /* lpc22xx only */ #define IO3PIN (*((volatile unsigned int *) 0xE0028030)) /* lpc22xx only */ #define IO3SET (*((volatile unsigned int *) 0xE0028034)) /* lpc22xx only */ #define IO3DIR (*((volatile unsigned int *) 0xE0028038)) /* lpc22xx only */ #define IO3CLR (*((volatile unsigned int *) 0xE002803C)) /* lpc22xx only */ /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ /* ͨÓÃÒì²½´®ÐпÚ0(UART0)µÄÌØÊâ¼Ä´æÆ÷ */ #define U0RBR (*((volatile unsigned char *) 0xE000C000)) #define U0THR (*((volatile unsigned char *) 0xE000C000)) #define U0IER (*((volatile unsigned char *) 0xE000C004)) #define U0IIR (*((volatile unsigned char *) 0xE000C008)) #define U0FCR (*((volatile unsigned char *) 0xE000C008)) #define U0LCR (*((volatile unsigned char *) 0xE000C00C)) #define U0LSR (*((volatile unsigned char *) 0xE000C014)) #define U0SCR (*((volatile unsigned char *) 0xE000C01C)) #define U0DLL (*((volatile unsigned char *) 0xE000C000)) #define U0DLM (*((volatile unsigned char *) 0xE000C004)) /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ /* ͨÓÃÒì²½´®ÐпÚ1(UART1)µÄÌØÊâ¼Ä´æÆ÷ */ #define U1RBR (*((volatile unsigned char *) 0xE0010000)) #define U1THR (*((volatile unsigned char *) 0xE0010000)) #define U1IER (*((volatile unsigned char *) 0xE0010004)) #define U1IIR (*((volatile unsigned char *) 0xE0010008)) #define U1FCR (*((volatile unsigned char *) 0xE0010008)) #define U1LCR (*((volatile unsigned char *) 0xE001000C)) #define U1MCR (*((volatile unsigned char *) 0xE0010010)) #define U1LSR (*((volatile unsigned char *) 0xE0010014)) #define U1MSR (*((volatile unsigned char *) 0xE0010018)) #define U1SCR (*((volatile unsigned char *) 0xE001001C)) #define U1DLL (*((volatile unsigned char *) 0xE0010000)) #define U1DLM (*((volatile unsigned char *) 0xE0010004)) /* I2C (8/16 bit data bus) */ /* оƬ¼ä×ÜÏߣ¨I2C£©µÄÌØÊâ¼Ä´æÆ÷ */ #define I2CONSET (*((volatile unsigned int *) 0xE001C000)) #define I2STAT (*((volatile unsigned int *) 0xE001C004)) #define I2DAT (*((volatile unsigned int *) 0xE001C008)) #define I2ADR (*((volatile unsigned int *) 0xE001C00C)) #define I2SCLH (*((volatile unsigned int *) 0xE001C010)) #define I2SCLL (*((volatile unsigned int *) 0xE001C014)) #define I2CONCLR (*((volatile unsigned int *) 0xE001C018)) /* SPI (Serial Peripheral Interface) */ /* SPI×ÜÏß½Ó¿ÚµÄÌØÊâ¼Ä´æÆ÷ */ /* only for lpc210x */ #define SPI_SPCR (*((volatile unsigned char *) 0xE0020000)) #define SPI_SPSR (*((volatile unsigned char *) 0xE0020004)) #define SPI_SPDR (*((volatile unsigned char *) 0xE0020008)) #define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C)) #define SPI_SPINT (*((volatile unsigned char *) 0xE002001C)) #define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x */ #define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x */ #define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x */ #define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x */ #define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x */ #define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x */ #define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x */ #define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x */ #define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x */ #define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x */ /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ /* CAN¿ØÖÆÆ÷ºÍ½ÓÊÕ·²¨Æ÷ */ #define CAN1MOD (*((volatile unsigned char *) 0xE0044000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1CMR (*((volatile unsigned char *) 0xE0044004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1GSR (*((volatile unsigned char *) 0xE0044008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1ICR (*((volatile unsigned char *) 0xE004400C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1IER (*((volatile unsigned char *) 0xE0044010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1BTR (*((volatile unsigned char *) 0xE0044014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1EWL (*((volatile unsigned char *) 0xE004401C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1SR (*((volatile unsigned char *) 0xE0044020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1RFS (*((volatile unsigned char *) 0xE0044024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1RDA (*((volatile unsigned char *) 0xE0044028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1RDB (*((volatile unsigned char *) 0xE004402C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TFI1 (*((volatile unsigned char *) 0xE0044030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TID1 (*((volatile unsigned char *) 0xE0044034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TDA1 (*((volatile unsigned char *) 0xE0044038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TDB1 (*((volatile unsigned char *) 0xE004403C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TFI2 (*((volatile unsigned char *) 0xE0044040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TID2 (*((volatile unsigned char *) 0xE0044044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TDA2 (*((volatile unsigned char *) 0xE0044048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TDB2 (*((volatile unsigned char *) 0xE004404C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TFI3 (*((volatile unsigned char *) 0xE0044050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TID3 (*((volatile unsigned char *) 0xE0044054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TDA3 (*((volatile unsigned char *) 0xE0044058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN1TDB3 (*((volatile unsigned char *) 0xE004405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2MOD (*((volatile unsigned char *) 0xE0048000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2CMR (*((volatile unsigned char *) 0xE0048004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2GSR (*((volatile unsigned char *) 0xE0048008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2ICR (*((volatile unsigned char *) 0xE004800C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2IER (*((volatile unsigned char *) 0xE0048010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2BTR (*((volatile unsigned char *) 0xE0048014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2EWL (*((volatile unsigned char *) 0xE004801C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2SR (*((volatile unsigned char *) 0xE0048020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2RFS (*((volatile unsigned char *) 0xE0048024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2RDA (*((volatile unsigned char *) 0xE0048028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2RDB (*((volatile unsigned char *) 0xE004802C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TFI1 (*((volatile unsigned char *) 0xE0048030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TID1 (*((volatile unsigned char *) 0xE0048034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TDA1 (*((volatile unsigned char *) 0xE0048038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TDB1 (*((volatile unsigned char *) 0xE004803C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TFI2 (*((volatile unsigned char *) 0xE0048040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TID2 (*((volatile unsigned char *) 0xE0048044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TDA2 (*((volatile unsigned char *) 0xE0048048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TDB2 (*((volatile unsigned char *) 0xE004804C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TFI3 (*((volatile unsigned char *) 0xE0048050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TID3 (*((volatile unsigned char *) 0xE0048054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TDA3 (*((volatile unsigned char *) 0xE0048058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN2TDB3 (*((volatile unsigned char *) 0xE004805C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3MOD (*((volatile unsigned char *) 0xE004C000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3CMR (*((volatile unsigned char *) 0xE004C004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3GSR (*((volatile unsigned char *) 0xE004C008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3ICR (*((volatile unsigned char *) 0xE004C00C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3IER (*((volatile unsigned char *) 0xE004C010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3BTR (*((volatile unsigned char *) 0xE004C014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3EWL (*((volatile unsigned char *) 0xE004C01C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3SR (*((volatile unsigned char *) 0xE004C020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3RFS (*((volatile unsigned char *) 0xE004C024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3RDA (*((volatile unsigned char *) 0xE004C028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3RDB (*((volatile unsigned char *) 0xE004C02C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TFI1 (*((volatile unsigned char *) 0xE004C030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TID1 (*((volatile unsigned char *) 0xE004C034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TDA1 (*((volatile unsigned char *) 0xE004C038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TDB1 (*((volatile unsigned char *) 0xE004C03C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TFI2 (*((volatile unsigned char *) 0xE004C040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TID2 (*((volatile unsigned char *) 0xE004C044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TDA2 (*((volatile unsigned char *) 0xE004C048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TDB2 (*((volatile unsigned char *) 0xE004C04C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TFI3 (*((volatile unsigned char *) 0xE004C050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TID3 (*((volatile unsigned char *) 0xE004C054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TDA3 (*((volatile unsigned char *) 0xE004C058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN3TDB3 (*((volatile unsigned char *) 0xE004C05C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4MOD (*((volatile unsigned char *) 0xE0050000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4CMR (*((volatile unsigned char *) 0xE0050004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4GSR (*((volatile unsigned char *) 0xE0050008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4ICR (*((volatile unsigned char *) 0xE005000C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4IER (*((volatile unsigned char *) 0xE0050010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4BTR (*((volatile unsigned char *) 0xE0050014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4EWL (*((volatile unsigned char *) 0xE005001C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4SR (*((volatile unsigned char *) 0xE0050020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4RFS (*((volatile unsigned char *) 0xE0050024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4RDA (*((volatile unsigned char *) 0xE0050028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4RDB (*((volatile unsigned char *) 0xE005002C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TFI1 (*((volatile unsigned char *) 0xE0050030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TID1 (*((volatile unsigned char *) 0xE0050034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TDA1 (*((volatile unsigned char *) 0xE0050038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TDB1 (*((volatile unsigned char *) 0xE005003C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TFI2 (*((volatile unsigned char *) 0xE0050040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TID2 (*((volatile unsigned char *) 0xE0050044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TDA2 (*((volatile unsigned char *) 0xE0050048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TDB2 (*((volatile unsigned char *) 0xE005004C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TFI3 (*((volatile unsigned char *) 0xE0050050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TID3 (*((volatile unsigned char *) 0xE0050054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TDA3 (*((volatile unsigned char *) 0xE0050058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN4TDB3 (*((volatile unsigned char *) 0xE005005C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5MOD (*((volatile unsigned char *) 0xE0054000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5CMR (*((volatile unsigned char *) 0xE0054004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5GSR (*((volatile unsigned char *) 0xE0054008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5ICR (*((volatile unsigned char *) 0xE005400C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5IER (*((volatile unsigned char *) 0xE0054010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5BTR (*((volatile unsigned char *) 0xE0054014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5EWL (*((volatile unsigned char *) 0xE005401C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5SR (*((volatile unsigned char *) 0xE0054020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5RFS (*((volatile unsigned char *) 0xE0054024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5RDA (*((volatile unsigned char *) 0xE0054028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5RDB (*((volatile unsigned char *) 0xE005402C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TFI1 (*((volatile unsigned char *) 0xE0054030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TID1 (*((volatile unsigned char *) 0xE0054034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDA1 (*((volatile unsigned char *) 0xE0054038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDB1 (*((volatile unsigned char *) 0xE005403C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TFI2 (*((volatile unsigned char *) 0xE0054040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TID2 (*((volatile unsigned char *) 0xE0054044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDA2 (*((volatile unsigned char *) 0xE0054048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDB2 (*((volatile unsigned char *) 0xE005404C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TFI3 (*((volatile unsigned char *) 0xE0054050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TID3 (*((volatile unsigned char *) 0xE0054054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDA3 (*((volatile unsigned char *) 0xE0054058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDB3 (*((volatile unsigned char *) 0xE005405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN6MOD (*((volatile unsigned char *) 0xE0058000)) /* lpc2292\lpc2294 only */ #define CAN6CMR (*((volatile unsigned char *) 0xE0058004)) /* lpc2292\lpc2294 only */ #define CAN6GSR (*((volatile unsigned char *) 0xE0058008)) /* lpc2292\lpc2294 only */ #define CAN6ICR (*((volatile unsigned char *) 0xE005800C)) /* lpc2292\lpc2294 only */ #define CAN6IER (*((volatile unsigned char *) 0xE0058010)) /* lpc2292\lpc2294 only */ #define CAN6BTR (*((volatile unsigned char *) 0xE0058014)) /* lpc2292\lpc2294 only */ #define CAN6EWL (*((volatile unsigned char *) 0xE005801C)) /* lpc2292\lpc2294 only */ #define CAN6SR (*((volatile unsigned char *) 0xE0058020)) /* lpc2292\lpc2294 only */ #define CAN6RFS (*((volatile unsigned char *) 0xE0058024)) /* lpc2292\lpc2294 only */ #define CAN6RDA (*((volatile unsigned char *) 0xE0058028)) /* lpc2292\lpc2294 only */ #define CAN6RDB (*((volatile unsigned char *) 0xE005802C)) /* lpc2292\lpc2294 only */ #define CAN6TFI1 (*((volatile unsigned char *) 0xE0058030)) /* lpc2292\lpc2294 only */ #define CAN6TID1 (*((volatile unsigned char *) 0xE0058034)) /* lpc2292\lpc2294 only */ #define CAN6TDA1 (*((volatile unsigned char *) 0xE0058038)) /* lpc2292\lpc2294 only */ #define CAN6TDB1 (*((volatile unsigned char *) 0xE005803C)) /* lpc2292\lpc2294 only */ #define CAN6TFI2 (*((volatile unsigned char *) 0xE0058040)) /* lpc2292\lpc2294 only */ #define CAN6TID2 (*((volatile unsigned char *) 0xE0058044)) /* lpc2292\lpc2294 only */ #define CAN6TDA2 (*((volatile unsigned char *) 0xE0058048)) /* lpc2292\lpc2294 only */ #define CAN6TDB2 (*((volatile unsigned char *) 0xE005804C)) /* lpc2292\lpc2294 only */ #define CAN6TFI3 (*((volatile unsigned char *) 0xE0058050)) /* lpc2292\lpc2294 only */ #define CAN6TID3 (*((volatile unsigned char *) 0xE0058054)) /* lpc2292\lpc2294 only */ #define CAN6TDA3 (*((volatile unsigned char *) 0xE0058058)) /* lpc2292\lpc2294 only */ #define CAN6TDB3 (*((volatile unsigned char *) 0xE005805C)) /* lpc2292\lpc2294 only */ #define CANTxSR (*((volatile unsigned char *) 0xE0040000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANRxSR (*((volatile unsigned char *) 0xE0040004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANMSR (*((volatile unsigned char *) 0xE0040008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANSFF_sa (*((volatile unsigned char *) 0xE003C004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANSFF_GRP_sa (*((volatile unsigned char *) 0xE003C008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANEFF_sa (*((volatile unsigned char *) 0xE003C00C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANEFF_GRP_sa (*((volatile unsigned char *) 0xE003C010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANENDofTable (*((volatile unsigned char *) 0xE003C014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANLUTerrAd (*((volatile unsigned char *) 0xE003C018)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ /* Timer 0 */ /* ¶¨Ê±Æ÷0µÄÌØÊâ¼Ä´æÆ÷ */ #define T0IR (*((volatile unsigned int *) 0xE0004000)) #define T0TCR (*((volatile unsigned int *) 0xE0004004)) #define T0TC (*((volatile unsigned int *) 0xE0004008)) #define T0PR (*((volatile unsigned int *) 0xE000400C)) #define T0PC (*((volatile unsigned int *) 0xE0004010)) #define T0MCR (*((volatile unsigned int *) 0xE0004014)) #define T0MR0 (*((volatile unsigned int *) 0xE0004018)) #define T0MR1 (*((volatile unsigned int *) 0xE000401C)) #define T0MR2 (*((volatile unsigned int *) 0xE0004020)) #define T0MR3 (*((volatile unsigned int *) 0xE0004024)) #define T0CCR (*((volatile unsigned int *) 0xE0004028)) #define T0CR0 (*((volatile unsigned int *) 0xE000402C)) #define T0CR1 (*((volatile unsigned int *) 0xE0004030)) #define T0CR2 (*((volatile unsigned int *) 0xE0004034)) #define T0CR3 (*((volatile unsigned int *) 0xE0004038)) #define T0EMR (*((volatile unsigned int *) 0xE000403C)) /* Timer 1 */ /* ¶¨Ê±Æ÷1µÄÌØÊâ¼Ä´æÆ÷ */ #define T1IR (*((volatile unsigned int *) 0xE0008000)) #define T1TCR (*((volatile unsigned int *) 0xE0008004)) #define T1TC (*((volatile unsigned int *) 0xE0008008)) #define T1PR (*((volatile unsigned int *) 0xE000800C)) #define T1PC (*((volatile unsigned int *) 0xE0008010)) #define T1MCR (*((volatile unsigned int *) 0xE0008014)) #define T1MR0 (*((volatile unsigned int *) 0xE0008018)) #define T1MR1 (*((volatile unsigned int *) 0xE000801C)) #define T1MR2 (*((volatile unsigned int *) 0xE0008020)) #define T1MR3 (*((volatile unsigned int *) 0xE0008024)) #define T1CCR (*((volatile unsigned int *) 0xE0008028)) #define T1CR0 (*((volatile unsigned int *) 0xE000802C)) #define T1CR1 (*((volatile unsigned int *) 0xE0008030)) #define T1CR2 (*((volatile unsigned int *) 0xE0008034)) #define T1CR3 (*((volatile unsigned int *) 0xE0008038)) #define T1EMR (*((volatile unsigned int *) 0xE000803C)) /* Pulse Width Modulator (PWM) */ /* Âö¿íµ÷ÖÆÆ÷µÄÌØÊâ¼Ä´æÆ÷ */ #define PWMIR (*((volatile unsigned int *) 0xE0014000)) #define PWMTCR (*((volatile unsigned int *) 0xE0014004)) #define PWMTC (*((volatile unsigned int *) 0xE0014008)) #define PWMPR (*((volatile unsigned int *) 0xE001400C)) #define PWMPC (*((volatile unsigned int *) 0xE0014010)) #define PWMMCR (*((volatile unsigned int *) 0xE0014014)) #define PWMMR0 (*((volatile unsigned int *) 0xE0014018)) #define PWMMR1 (*((volatile unsigned int *) 0xE001401C)) #define PWMMR2 (*((volatile unsigned int *) 0xE0014020)) #define PWMMR3 (*((volatile unsigned int *) 0xE0014024)) #define PWMMR4 (*((volatile unsigned int *) 0xE0014040)) #define PWMMR5 (*((volatile unsigned int *) 0xE0014044)) #define PWMMR6 (*((volatile unsigned int *) 0xE0014048)) #define PWMPCR (*((volatile unsigned int *) 0xE001404C)) #define PWMLER (*((volatile unsigned int *) 0xE0014050)) /* A/D CONVERTER */ /* A/Dת»»Æ÷ */ #define ADCR (*((volatile unsigned int *) 0xE0034000)) /* no in lpc210x */ #define ADDR (*((volatile unsigned int *) 0xE0034004)) /* no in lpc210x */ /* Real Time Clock */ /* ʵʱʱÖÓµÄÌØÊâ¼Ä´æÆ÷ */ #define ILR (*((volatile unsigned char *) 0xE0024000)) #define CTC (*((volatile unsigned short*) 0xE0024004)) #define CCR (*((volatile unsigned char *) 0xE0024008)) #define CIIR (*((volatile unsigned char *) 0xE002400C)) #define AMR (*((volatile unsigned char *) 0xE0024010)) #define CTIME0 (*((volatile unsigned int *) 0xE0024014)) #define CTIME1 (*((volatile unsigned int *) 0xE0024018)) #define CTIME2 (*((volatile unsigned int *) 0xE002401C)) #define SEC (*((volatile unsigned char *) 0xE0024020)) #define MIN (*((volatile unsigned char *) 0xE0024024)) #define HOUR (*((volatile unsigned char *) 0xE0024028)) #define DOM (*((volatile unsigned char *) 0xE002402C)) #define DOW (*((volatile unsigned char *) 0xE0024030)) #define DOY (*((volatile unsigned short*) 0xE0024034)) #define MONTH (*((volatile unsigned char *) 0xE0024038)) #define YEAR (*((volatile unsigned short*) 0xE002403C)) #define ALSEC (*((volatile unsigned char *) 0xE0024060)) #define ALMIN (*((volatile unsigned char *) 0xE0024064)) #define ALHOUR (*((volatile unsigned char *) 0xE0024068)) #define ALDOM (*((volatile unsigned char *) 0xE002406C)) #define ALDOW (*((volatile unsigned char *) 0xE0024070)) #define ALDOY (*((volatile unsigned short*) 0xE0024074)) #define ALMON (*((volatile unsigned char *) 0xE0024078)) #define ALYEAR (*((volatile unsigned short*) 0xE002407C)) #define PREINT (*((volatile unsigned short*) 0xE0024080)) #define PREFRAC (*((volatile unsigned short*) 0xE0024084)) /* Watchdog */ /* ¿´ÃŹ·µÄÌØÊâ¼Ä´æÆ÷ */ #define WDMOD (*((volatile unsigned char *) 0xE0000000)) #define WDTC (*((volatile unsigned int *) 0xE0000004)) #define WDFEED (*((volatile unsigned char *) 0xE0000008)) #define WDTV (*((volatile unsigned int *) 0xE000000C)) /* Define firmware Functions */ /* ¶¨Òå¹Ì¼þº¯Êý */ #define rm_init_entry() ((void (*)())(0x7fffff91))() #define rm_undef_handler() ((void (*)())(0x7fffffa0))() #define rm_prefetchabort_handler() ((void (*)())(0x7fffffb0))() #define rm_dataabort_handler() ((void (*)())(0x7fffffc0))() #define rm_irqhandler() ((void (*)())(0x7fffffd0))() #define rm_irqhandler2() ((void (*)())(0x7fffffe0))() #define iap_entry(a, b) ((void (*)())(0x7ffffff1))(a, b) struct lpc_timers { unsigned int ir; // unsigned int tcr; // unsigned int tc; // unsigned int pr; // unsigned int pc; // unsigned int mcr; // unsigned int mr0; // unsigned int mr1; // unsigned int mr2; // unsigned int mr3; // unsigned int ccr; // unsigned int cr0; // unsigned int cr1; // unsigned int cr2; // unsigned int cr3; // unsigned int emr; // }; #define IRQ_WD 0 //#define IRQ_SWI 1 //#define IRQ_USART0 2 //#define IRQ_USART1 3 //#define IRQ_TC0 (1<<4) #define IRQ_TC0 0x10 #define IRQ_TC1 5 #define IRQ_UART0 (1 << 6) #define IRQ_UART1 7 #define IRQ_PWM 8 #define IRQ_I2C 9 #define IRQ_SPI0 10 #define IRQ_SPI1 11 #define IRQ_PLL 12 #define IRQ_RTC 13 #define IRQ_EXT0 14 #define IRQ_EXT1 15 #define IRQ_EXT2 16 #define IRQ_EXT3 17 #define IRQ_AD 18 #endif �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/serial_amba_pl011.h��������������������������������������������������0000644�0001750�0000144�00000012766�10541455476�020216� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * linux/include/asm-arm/hardware/serial_amba_pl011.h * * Internal header file for AMBA PrimeCell PL011 serial ports * * Copyright (C) 2002 Lineo, Inc. * * Based on serial_amba.h, which is: * Copyright (C) ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_PL011_H #define ASM_ARM_HARDWARE_SERIAL_AMBA_PL011_H /* ------------------------------------------------------------------------------- * From AMBA UART (PL011) TRM * ------------------------------------------------------------------------------- * UART Register Offsets. */ #define AMBA_UARTDR 0x00 /* Data read or written from the interface. */ #define AMBA_UARTRSR 0x04 /* Receive status register (Read). */ #define AMBA_UARTECR 0x04 /* Error clear register (Write). */ #define AMBA_UARTFR 0x18 /* Flag register (Read only). */ #define AMBA_UARTILPR 0x20 /* IrDA low power counter register. */ #define AMBA_UARTIBRD 0x24 /* Integer baud rate divisor. */ #define AMBA_UARTFBRD 0x28 /* Fractional baud rate divisor. */ #define AMBA_UARTLCR_H 0x2C /* Line control register, high byte. */ #define AMBA_UARTCR 0x30 /* Control register. */ #define AMBA_UARTIFLS 0x34 /* Interrupt FIFO level select. */ #define AMBA_UARTIMSC 0x38 /* Interrupt Mask Set/Clear. */ #define AMBA_UARTRIS 0x3C /* Raw Interrupt status register (Read). */ #define AMBA_UARTMIS 0x40 /* Masked Interrupt status register (Read). */ #define AMBA_UARTICR 0x44 /* Interrupt clear register (Write). */ #define AMBA_UARTRSR_OE 0x0800 /* Overrun error */ #define AMBA_UARTRSR_BE 0x0400 /* Break error */ #define AMBA_UARTRSR_PE 0x0200 /* Parity error */ #define AMBA_UARTRSR_FE 0x0100 /* framing error */ #define AMBA_UARTFR_TXFF 0x20 /* Tx FIFO full */ #define AMBA_UARTFR_RXFE 0x10 /* Rx FIFO empty */ #define AMBA_UARTFR_BUSY 0x08 /* busy xmitting */ #define AMBA_UARTFR_DCD 0x04 #define AMBA_UARTFR_DSR 0x02 #define AMBA_UARTFR_CTS 0x01 #define AMBA_UARTFR_TMSK (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY) /* Interrupt Mask Set/Clear register bits */ #define AMBA_UARTIMSC_RTIM 0x40 /* Rx timeout interrupt mask */ #define AMBA_UARTIMSC_TXIM 0x20 /* Tx interrupt mask */ #define AMBA_UARTIMSC_RXIM 0x10 /* Rx interrupt mask */ #define AMBA_UARTIMSC_DSRMIM 0x08 /* DSR Modem Interrupt mask */ #define AMBA_UARTIMSC_DCDMIM 0x04 /* DCD Modem Interrupt mask */ #define AMBA_UARTIMSC_CTSMIM 0x02 /* CTS Modem Interrupt mask */ #define AMBA_UARTIMSC_RIMIM 0x01 /* RI Modem Interrupt mask */ /* all modem mask bits */ #define AMBA_UARTIMSC_Modem (AMBA_UARTIMSC_DSRMIM |AMBA_UARTIMSC_DCDMIM | \ AMBA_UARTIMSC_CTSMIM |AMBA_UARTIMSC_RIMIM) /* Control Register bits */ #define AMBA_UARTCR_RTS 0x800 /* nRTS */ #define AMBA_UARTCR_DTR 0x400 /* nDTR */ #define AMBA_UARTCR_RXE 0x200 /* Rx enable */ #define AMBA_UARTCR_TXE 0x100 /* Tx enable */ #define AMBA_UARTCR_LBE 0x080 /* Loopback enable */ #define AMBA_UARTCR_SIRLP 0x004 /* IR SIR Low Power Mode */ #define AMBA_UARTCR_SIREN 0x002 /* IR SIR enable */ #define AMBA_UARTCR_UARTEN 0x001 /* UART enable */ #define AMBA_UARTLCR_H_WLEN_8 0x60 #define AMBA_UARTLCR_H_WLEN_7 0x40 #define AMBA_UARTLCR_H_WLEN_6 0x20 #define AMBA_UARTLCR_H_WLEN_5 0x00 #define AMBA_UARTLCR_H_FEN 0x10 #define AMBA_UARTLCR_H_STP2 0x08 #define AMBA_UARTLCR_H_EPS 0x04 #define AMBA_UARTLCR_H_PEN 0x02 #define AMBA_UARTLCR_H_BRK 0x01 /* Raw/Masked Interrupt Status Register bits*/ #define AMBA_UART_IS_RT 0x40 #define AMBA_UART_IS_TX 0x20 #define AMBA_UART_IS_RX 0x10 #define AMBA_UART_IS_DSR 0x08 #define AMBA_UART_IS_DCD 0x04 #define AMBA_UART_IS_CTS 0x02 #define AMBA_UART_IS_RI 0x01 #define AMBA_UART_IS_MI (AMBA_UART_IS_DSR | AMBA_UART_IS_DCD | \ AMBA_UART_IS_CTS | AMBA_UART_IS_RI ) #define AMBA_UARTRSR_ANY (AMBA_UARTRSR_OE|AMBA_UARTRSR_BE|AMBA_UARTRSR_PE|AMBA_UARTRSR_FE) #define AMBA_UARTFR_MODEM_ANY (AMBA_UARTFR_DCD|AMBA_UARTFR_DSR|AMBA_UARTFR_CTS) #endif /* ASM_ARM_HARDWARE_SERIAL_AMBA_PL011_H */ ����������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_ep7312.c�������������������������������������������������0000644�0001750�0000144�00000024401�10704350434�020311� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_ep7312.c - define machine ep7312 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 3/24/2003 init this file. * add machine ep7312's function. Most taken from original armio.c. * include: ep7312_mach_init, ep7312_io_do_cycle * ep7312_io_read_word, ep7312_io_write_word * walimis <walimi@peoplemail.com.cn> * * */ #include "armdefs.h" #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include "clps7110.h" //zzc: #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; inttv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" //ywc 2004-04-01 extern unsigned int Pen_buffer[8]; // defined in skyeye_lcd.c #define DEBUG 1 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr,##a) #else #define DBG_PRINT(a...) #endif /*Internal IO Register*/ typedef struct ep7312_io { ARMword syscon; /* System control */ ARMword sysflg; /* System status flags */ ARMword intsr; /* Interrupt status reg */ ARMword intmr; /* Interrupt mask reg */ ARMword intmr2; ARMword intmr3; ARMword tcd[2]; /* Timer/counter data */ ARMword tcd_reload[2]; /* Last value written */ ARMword uartdr; /* Receive data register */ //ywc,2004-04-01 ARMword ts_int; /* ywc 2004-04-02 */ ARMword ts_buffer[8]; //ARMword tsaddr; /* ??? touch srceen data buffer start address*/ ARMword ts_addr_begin; ARMword ts_addr_end; //2004-06-21 ARMword padr; ARMword pbdr; ARMword pddr; ARMword paddr; ARMword pbddr; ARMword pdddr; ARMword pedr; ARMword peddr; } ep7312_io_t; static ep7312_io_t ep7312_io; #define io ep7312_io static void ep7312_update_int (ARMul_State * state) { ARMword requests = io.intsr & io.intmr; state->NfiqSig = (requests & 0x0001) ? LOW : HIGH; state->NirqSig = (requests & 0xfffe) ? LOW : HIGH; } static void ep7312_io_reset (ARMul_State * state) { memset(&io, 0, sizeof(io)); io.syscon = LCDEN; io.sysflg = URXFE; io.intmr = 0; io.intsr = UTXINT; /* always ready to transmit */ io.tcd[0] = 0xffff; io.tcd[1] = 0xffff; io.tcd_reload[0] = 0xffff; io.tcd_reload[1] = 0xffff; io.uartdr = 0; //ywc 2004-04-01 //io.tsaddr =0x0; io.ts_int = EINT2; /* ywc 2004-04-02 use EINT2 as touch screen interrupt */ io.ts_addr_begin = 0x8000b000; io.ts_addr_end = 0x8000b01f; } void ep7312_io_do_cycle (ARMul_State * state) { int t; for (t = 0; t < 2; t++) { if (io.tcd[t] == 0) { if (io.syscon & (t ? TC2M : TC1M)) { io.tcd[t] = io.tcd_reload[t]; } else { io.tcd[t] = 0xffff; } io.intsr |= (t ? TC2OI : TC1OI); ep7312_update_int (state); } else { io.tcd[t]--; } } if (!(io.intsr & URXINT)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.uartdr = (int) buf; io.sysflg &= ~URXFE; io.intsr |= URXINT; ep7312_update_int (state); } } //if (!(io.intsr & URXINT)) // ywc 2004-04-01 for touch screen interrupt #ifndef NO_LCD { if (!(io.intsr & io.ts_int)) { //if now has no ts interrupt,then query if (Pen_buffer[6] == 1) { //should trigger a interrupt *(io.ts_buffer + 0) = Pen_buffer[0]; *(io.ts_buffer + 1) = Pen_buffer[1]; *(io.ts_buffer + 4) = Pen_buffer[4]; *(io.ts_buffer + 6) = Pen_buffer[6]; //set EINT2 bit to trigger a interrupt,ts driver will clear it io.intsr |= io.ts_int; Pen_buffer[6] = 0; } } } #endif } ARMword ep7312_io_read_byte (ARMul_State * state, ARMword addr) { ARMword data = -1; unsigned char offset = 0; unsigned char ret; switch (addr - 0x80000000) { case PADR: data = io.padr; break; case PBDR: data = io.pbdr; break; case PDDR: data = io.pddr; break; case PADDR: data = io.paddr; break; case PBDDR: data = io.pbddr; break; case PDDDR: data = io.pdddr; break; case PEDR: data = io.pedr; break; case PEDDR: data = io.peddr; break; default: printf ("SKYEYE: ep7312_io_read_byte error\n"); printf ("SKYEYE: state->pc=%x,state->instr=%x,addr=%x\n", state->pc, state->instr, addr); skyeye_exit (-1); break; } return data; } ARMword ep7312_io_read_halfword (ARMul_State * state, ARMword addr) { printf ("SKYEYE: ep7312_io_read_halfword error\n"); skyeye_exit (-1); } ARMword ep7312_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = 0; ARMword ts_addr; //ywc 2004-04-01 read the touch srceen data buffer,return to the ts device driver ts_addr = addr & ~3; // 1 word==4 byte if (ts_addr >= io.ts_addr_begin && ts_addr <= io.ts_addr_end) { data = io.ts_buffer[(ts_addr - io.ts_addr_begin) / 4]; return data; } switch (addr - 0x80000000) { case SYSCON: data = io.syscon; break; case SYSFLG: data = io.sysflg; break; /* case MEMCFG1: * case MEMCFG2: * case DRFPR */ case INTSR: data = io.intsr; break; case INTMR: data = io.intmr; break; case TC1D: data = io.tcd[0]; break; case TC2D: data = io.tcd[1]; break; /* case RTCDR: * case RTCMR: * case PMPCON : * case CODR:*/ case UARTDR: data = io.uartdr; io.sysflg |= URXFE; io.intsr &= ~URXINT; ep7312_update_int (state); break; /* case UBRLCR: */ case SYNCIO: /* if we return zero here, the battery voltage calculation * results in a divide-by-zero that messes up the kernel */ data = 1; break; /* case PALLSW: * case PALMSW:*/ /* write-only: */ case STFCLR: case BLEOI: case MCEOI: case TEOI: case TC1EOI: case TC2EOI: case RTCEOI: case UMSEOI: case COEOI: case HALT: case STDBY: break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? //SKYEYE_DBG("io_read_word(0x%08x) = 0x%08x\n", addr, data); break; } return data; } void ep7312_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { //fprintf(stderr,"skyeye:ep7312_io_write_byte,@addr is %x",addr); unsigned char offset = 0; unsigned char ret; switch (addr - 0x80000000) { case PADR: io.padr = data; break; case PBDR: io.pbdr = data; break; case PDDR: io.pddr = data; break; case PADDR: io.paddr = data; break; case PBDDR: io.pbddr = data; break; case PDDDR: io.pdddr = data; break; case PEDR: data = io.pedr; break; case PEDDR: io.peddr = data; break; case INTMR3: io.intmr3 = data; break; case INTMR2: io.intmr2 = data; break; default: printf ("SKYEYE: ep7312_io_write_byte error@@@@@@@\n"); SKYEYE_OUTREGS (stderr); skyeye_exit (-1); break; } } void ep7312_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { printf ("SKYEYE: ep7312_io_write_halfword error\n"); skyeye_exit (-1); } void ep7312_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { ARMword tmp; switch (addr - 0x80000000) { case SYSCON: tmp = io.syscon; io.syscon = data; //chy 2004-03-11 if ((tmp & LCDEN) != (data & LCDEN)) { // by ywc 2004-07-07 printf ("\n\n SYSCON:will call ep7312_update_lcd()"); //ep7312_update_lcd (state); } break; case SYSFLG: break; case INTSR: //DBG_PRINT("write INTSR=0x%x\n", data); io.intsr = data; // printf("SKYEYE: write INTSR=0x%x\n", io.intsr); break; case INTMR: //DBG_PRINT("write INTMR=0x%x\n", data); //if(data != 0x2000 && data != 0x2200) //printf("SKYEYE: write INTMR=0x%x\n", data); io.intmr = data; ep7312_update_int (state); break; case TC1D: io.tcd[0] = io.tcd_reload[0] = data & 0xffff; SKYEYE_DBG ("TC1D 0x%x\n", data & 0xffff); break; case TC2D: io.tcd[1] = io.tcd_reload[1] = data & 0xffff; SKYEYE_DBG ("TC2D 0x%x\n", data & 0xffff); break; case UARTDR: /* The UART writes chars to console */ { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } break; /* case BLEOI: printf("BLEOI\n"); break; case MCEOI: printf("MCEOI\n"); break; case TEOI: printf("TEOI\n"); break;*/ case TC1EOI: io.intsr &= ~TC1OI; ep7312_update_int (state); SKYEYE_DBG ("TC1EOI\n"); break; case TC2EOI: io.intsr &= ~TC2OI; ep7312_update_int (state); SKYEYE_DBG ("TC2EOI\n"); break; //case RTCEOI: printf("RTCEOI\n"); break; //case UMSEOI: printf("UMSEOI\n"); break; //case COEOI: printf("COEOI\n"); break; case 0x2000: /* Not a real register, for debugging only: */ SKYEYE_DBG ("io_write_word debug: 0x%08lx\n", data); break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? //printf("SKYEYE:unknown io addr, io_write_word(0x%08x, 0x%08x), pc %x \n", addr, data,state->Reg[15]); break; } } void ep7312_mach_init (ARMul_State * state, machine_config_t * this_mach) { state->abort_model = 2; //chy 2003-08-19, setprocessor ARMul_SelectProcessor (state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; state->Reg[1] = 91; //for EP7212/EP7312 arch id this_mach->mach_io_do_cycle = ep7312_io_do_cycle; this_mach->mach_io_reset = ep7312_io_reset; this_mach->mach_io_read_byte = ep7312_io_read_byte; this_mach->mach_io_write_byte = ep7312_io_write_byte; this_mach->mach_io_read_halfword = ep7312_io_read_halfword; this_mach->mach_io_write_halfword = ep7312_io_write_halfword; this_mach->mach_io_read_word = ep7312_io_read_word; this_mach->mach_io_write_word = ep7312_io_write_word; this_mach->mach_update_int = ep7312_update_int; this_mach->state = (void *) state; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_s3c2440.c������������������������������������������������0000644�0001750�0000144�00000026701�10555732132�020402� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_s3c2440.c - define machine S3C2440 for skyeye Copyright (C) 2005 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "armdefs.h" #include "s3c2440.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" #define TC_DIVISOR (1) /* Set your BogoMips here :) may move elsewhere */ typedef struct s3c2440_io { u32 srcpnd; /* Indicate the interrupt request status */ u32 intmod; /* Interrupt mode register */ u32 intmsk; /* Determine which interrupt source is masked */ u32 priority; /* IRQ priority control register */ u32 intpnd; /* Indicate the interrupt request status */ u32 intoffset; /* Indicate the IRQ interrupt request source */ u32 subsrcpnd; /* Indicate the interrupt request status */ u32 intsubmsk; /* Determin which interrupt source is masked */ struct s3c2440_timer_io timer; /* Timer */ struct s3c2440_uart_io uart0; /* uart0 */ struct s3c2440_clkpower clkpower; /* clock and power management */ int tc_prescale; } s3c2440_io_t; static s3c2440_io_t s3c2440_io; #define io s3c2440_io static inline void s3c2440_set_subsrcint (unsigned int irq) { io.subsrcpnd |= irq; } static inline void s3c2440_update_subsrcint () { u32 requests; s3c2440_set_subsrcint (UART_INT_TXD << (0 * 3)); s3c2440_set_subsrcint (UART_INT_TXD << (1 * 3)); s3c2440_set_subsrcint (UART_INT_TXD << (2 * 3)); requests = ((io.subsrcpnd & (~io.intsubmsk)) & 0x7fff); if (requests & 0x7) io.srcpnd |= INT_UART0; if (requests & 0x38) io.srcpnd |= INT_UART1; if (requests & 0x1c0) io.srcpnd |= INT_UART2; if (requests & 0x600) io.srcpnd |= INT_ADC; } static void s3c2440_update_int (ARMul_State * state) { ARMword requests; s3c2440_update_subsrcint (); requests = io.srcpnd & (~io.intmsk & INT_MASK_INIT); state->NfiqSig = (requests & io.intmod) ? LOW : HIGH; state->NirqSig = (requests & ~io.intmod) ? LOW : HIGH; } static void s3c2440_io_reset (ARMul_State * state) { memset (&s3c2440_io, 0, sizeof (s3c2440_io)); io.tc_prescale = TC_DIVISOR; io.uart0.ulcon = UART_ULCON_INIT; io.uart0.utrstat = UART_UTRSTAT_INIT; //io.timer.tcnt[4] = 25350; io.clkpower.locktime = 0x00FFFFFF; io.clkpower.mpllcon = 0x0005C080; io.clkpower.upllcon = 0x00028080; io.clkpower.clkcon = 0x7FFF0; io.clkpower.clkslow = 0x4; io.intmsk = INT_MASK_INIT; io.intpnd = 0x0; } /* s3c2440 io_do_cycle */ static void s3c2440_io_do_cycle (ARMul_State * state) { io.tc_prescale--; if (io.tc_prescale < 0) { io.tc_prescale = TC_DIVISOR; if ((io.timer.tcon & 0x100000) != 0) { io.timer.tcnt[4]--; if (io.timer.tcnt[4] < 0) { io.timer.tcnt[4] = io.timer.tcntb[4]; /*timer 4 hasn't tcmp */ //io.timer.tcmp[4] = io.timer.tcmpb[4]; io.timer.tcnto[4] = io.timer.tcntb[4]; io.srcpnd |= INT_TIMER4; s3c2440_update_int (state); return; } } if (((io.uart0.utrstat & 0x1) == 0x0) && ((io.uart0.ucon & 0x3) == 0x1)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.uart0.urxh = (int) buf; /* Receiver Ready * */ io.uart0.utrstat |= (0x1); /* pending usart0 interrupt * */ s3c2440_set_subsrcint (UART_INT_RXD << (0 * 3)); //io.srcpnd |= INT_UART0; s3c2440_update_int (state); return; } } //s3c2440_update_int (state); } /* if (io.tc_prescale < 0) */ } static void s3c2440_uart_read (u32 offset, u32 * data) { switch (offset) { case ULCON: *data = io.uart0.ulcon; break; case UCON: *data = io.uart0.ucon; break; case UFCON: *data = io.uart0.ufcon; break; case UMCON: *data = io.uart0.umcon; break; case UTRSTAT: *data = io.uart0.utrstat; break; case UERSTAT: *data = io.uart0.uerstat; break; case UFSTAT: *data = io.uart0.ufstat; break; case UMSTAT: *data = io.uart0.umstat; break; case URXH: /* receive char * */ *data = io.uart0.urxh; io.uart0.utrstat &= (~0x1); /* clear strstat register bit[0] */ break; case UBRDIV: *data = io.uart0.ubrdiv; break; default: break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } static void s3c2440_uart_write (ARMul_State * state, u32 offset, u32 data) { SKYEYE_DBG ("s3c2440_uart_write(0x%x, 0x%x)\n", offset, data); switch (offset) { case ULCON: io.uart0.ulcon = data; break; case UCON: io.uart0.ucon = data; break; case UFCON: io.uart0.ufcon = data; break; case UMCON: io.uart0.umcon = data; break; case UTRSTAT: io.uart0.utrstat = data; break; case UERSTAT: io.uart0.uerstat = data; break; case UFSTAT: io.uart0.ufstat = data; break; case UMSTAT: io.uart0.umstat = data; break; case UTXH: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.uart0.utrstat |= 0x6; //set strstat register bit[0] if ((io.uart0.ucon & 0xc) == 0x4) { s3c2440_set_subsrcint (UART_INT_TXD << (0 * 3)); s3c2440_update_int (state); } } break; case UBRDIV: io.uart0.ubrdiv = data; break; default: break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } static void s3c2440_timer_read (u32 offset, u32 * data) { switch (offset) { case TCFG0: *data = io.timer.tcfg0; break; case TCFG1: *data = io.timer.tcfg1; break; case TCON: *data = io.timer.tcon; break; case TCNTB0: case TCNTB1: case TCNTB2: case TCNTB3: case TCNTB4: { int n = (offset - 0xC) / 0xC; *data = io.timer.tcntb[n]; } break; case TCMPB0: case TCMPB1: case TCMPB2: case TCMPB3: { int n = (offset - 0x10) / 0xC; *data = io.timer.tcmpb[n]; } break; case TCNTO0: case TCNTO1: case TCNTO2: case TCNTO3: { int n = (offset - 0x10) / 0xC; *data = io.timer.tcnto[n]; } break; case TCNTO4: *data = io.timer.tcnto[4]; break; default: break; } } static void s3c2440_timer_write (ARMul_State * state, u32 offset, u32 data) { switch (offset) { case TCFG0: io.timer.tcfg0 = data; break; case TCFG1: io.timer.tcfg1 = data; break; case TCON: { io.timer.tcon = data; if (io.timer.tcon) { } } break; case TCNTB0: case TCNTB1: case TCNTB2: case TCNTB3: case TCNTB4: { int n = (offset - 0xC) / 0xC; //io.timer.tcntb[n] = data; io.timer.tcntb[n] = 25350; } break; case TCMPB0: case TCMPB1: case TCMPB2: case TCMPB3: { int n = (offset - 0x10) / 0xC; io.timer.tcmpb[n] = data; } break; default: break; } } static ARMword s3c2440_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = -1; int i; /*uart0 */ if ((addr >= UART_CTL_BASE0) && (addr < (UART_CTL_BASE0 + UART_CTL_SIZE))) { s3c2440_uart_read ((u32) (addr - UART_CTL_BASE0), (u32 *) & data); } if ((addr >= PWM_CTL_BASE) && (addr < (PWM_CTL_BASE + PWM_CTL_SIZE))) { s3c2440_timer_read ((u32) (addr - PWM_CTL_BASE), (u32 *) & data); } switch (addr) { case SRCPND: data = io.srcpnd; break; case INTMOD: data = io.intmod; break; case INTMSK: data = io.intmsk; break; case PRIORITY: data = io.priority; break; case INTPND: case INTOFFSET: { /*find which interrupt is pending */ int i; for (i = 0; i < 32; i++) { if (io.srcpnd & (1 << i)) break; } if (i < 32) { io.intoffset = i; io.intpnd = (1 << i); if (addr == INTPND) data = (1 << i); else data = i; } else data = 0; } io.intpnd = (1 << io.intoffset); //printf ("io.intoffset:%x, io.intpnd:%x (0x%08x) = 0x%08x\n", io.intoffset, io.intpnd, addr, data); break; case SUBSRCPND: data = io.subsrcpnd; break; case INTSUBMSK: data = io.intsubmsk; break; /* GPIO Register */ case GSTATUS1: data = 0x32410000; break; /* Clock and Power Management Registers */ case LOCKTIME: data = io.clkpower.locktime; break; case MPLLCON: data = io.clkpower.mpllcon; break; case UPLLCON: data = io.clkpower.upllcon; break; case CLKCON: data = io.clkpower.clkcon; break; case CLKSLOW: data = io.clkpower.clkslow; break; case CLKDIVN: data = io.clkpower.clkdivn; break; default: break; } return data; } static ARMword s3c2440_io_read_byte (ARMul_State * state, ARMword addr) { s3c2440_io_read_word (state, addr); } static ARMword s3c2440_io_read_halfword (ARMul_State * state, ARMword addr) { s3c2440_io_read_word (state, addr); } static void s3c2440_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { if ((addr >= UART_CTL_BASE0) && (addr < UART_CTL_BASE0 + UART_CTL_SIZE)) { s3c2440_uart_write (state, addr - UART_CTL_BASE0, data); } if ((addr >= PWM_CTL_BASE) && (addr < (PWM_CTL_BASE + PWM_CTL_SIZE))) { s3c2440_timer_write (state, addr - PWM_CTL_BASE, data); } switch (addr) { case SRCPND: io.srcpnd &= (~data & INT_MASK_INIT); break; case INTMOD: io.intmod = data; break; case INTMSK: io.intmsk = data; s3c2440_update_int (state); break; case PRIORITY: io.priority = data; break; case INTPND: io.intpnd &= (~data & INT_MASK_INIT); io.intoffset = 0; //printf ("io.intoffset:%x, io.intpnd:%x (0x%08x) = 0x%08x, pc:%x\n", io.intoffset, io.intpnd, addr, data, state->pc); break; /*read only */ //case INTOFFSET: // break; case SUBSRCPND: io.subsrcpnd &= (~data & INT_SUBMSK_INIT); break; case INTSUBMSK: io.intsubmsk = data; break; default: SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data); break; } } static void s3c2440_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: s3c2440_io_write_byte error\n"); s3c2440_io_write_word (state, addr, data); } static void s3c2440_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: s3c2440_io_write_halfword error\n"); s3c2440_io_write_word (state, addr, data); } void s3c2440_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v4_Prop); /* ARM920T uses LOW */ state->lateabtSig = LOW; state->Reg[1] = 241; //ARCH_S3C2440 this_mach->mach_io_do_cycle = s3c2440_io_do_cycle; this_mach->mach_io_reset = s3c2440_io_reset; this_mach->mach_io_read_byte = s3c2440_io_read_byte; this_mach->mach_io_write_byte = s3c2440_io_write_byte; this_mach->mach_io_read_halfword = s3c2440_io_read_halfword; this_mach->mach_io_write_halfword = s3c2440_io_write_halfword; this_mach->mach_io_read_word = s3c2440_io_read_word; this_mach->mach_io_write_word = s3c2440_io_write_word; this_mach->mach_update_int = s3c2440_update_int; } ���������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_integrator.c���������������������������������������������0000644�0001750�0000144�00000007601�10634526727�021565� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_integrator.c - integrator machine simulation Copyright (C) 2003-2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/02/2007 Michael.Kang <blackfin.kang@gmail.com> */ #include "armdefs.h" typedef struct integrator_timer_s{ uint32_t timer_load; uint32_t timer_value; uint32_t timer_control; uint32_t timer_intclr; uint32_t timer_ris; uint32_t timer_mis; uint32_t timer_bgload; }integrator_timer_t; typedef struct uart_s{ uint32_t uartdr; uint32_t uartrsr; uint32_t uartfr; uint32_t uartilpr; uint32_t uartibrd; uint32_t uartfbrd; uint32_t uartlcr_h; uint32_t uartcr; uint32_t uartifls; uint32_t uartimsc; uint32_t uartris; uint32_t uartmis; uint32_t uarticr; uint32_t uartdmacr; uint32_t uartperiphID[4]; uint32_t uartpcellID[4]; }uart_t; typedef struct pic_s{ uint32_t irq_status; uint32_t irq_rawstatus; uint32_t irq_enableset; uint32_t irq_enableclr; uint32_t int_softset; uint32_t int_softclr; uint32_t fiq_status; uint32_t fiq_rawstat; uint32_t fiq_enableset; uint32_t fiq_enableclr; }pic_t; typedef struct integrator_io_s{ integrator_timer_t timer[3]; uart_t uart[2]; pic_t pic; }integrator_io_t; void integrator_io_do_cycle(){} ARMword integrator_io_read_word (void * state, ARMword addr) { /* * * The LPC system registers * */ ARMword data = -1; static ARMword current_ivr = 0; /* mega hack, 2.0 needs this */ int i; ARMword dataimr = 0; return data; } ARMword integrator_io_read_byte (void * state, ARMword addr) { return integrator_io_read_word (state, addr); // SKYEYE_OUTREGS(stderr); //exit(-1); } ARMword integrator_io_read_halfword (void * state, ARMword addr) { return integrator_io_read_word (state, addr); //SKYEYE_OUTREGS(stderr); //exit(-1); } void integrator_io_write_word (void * state, ARMword addr, ARMword data) { /* * The integrator system registers */ } void integrator_io_write_byte (void * state, ARMword addr, ARMword data) { integrator_io_write_word (state, addr, data); //SKYEYE_OUTREGS(stderr); //exit(-1); } void integrator_io_write_halfword (void * state, ARMword addr, ARMword data) { integrator_io_write_word (state, addr, data); //SKYEYE_OUTREGS(stderr); //exit(-1); } static void integrator_io_reset (void * curr_state) { } void integrator_mach_init (ARMul_State * state, machine_config_t * this_mach) { //chy 2003-08-19, setprocessor ARMul_SelectProcessor (state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; state->Reg[1] = 21; /* MACH_TYPE_INTEGRATOR defined in linux source */ this_mach->mach_io_do_cycle = integrator_io_do_cycle; this_mach->mach_io_reset = integrator_io_reset; this_mach->mach_io_read_byte = integrator_io_read_byte; this_mach->mach_io_write_byte = integrator_io_write_byte; this_mach->mach_io_read_halfword = integrator_io_read_halfword; this_mach->mach_io_write_halfword = integrator_io_write_halfword; this_mach->mach_io_read_word = integrator_io_read_word; this_mach->mach_io_write_word = integrator_io_write_word; //this_mach->mach_update_int = integrator_update_int; } �������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_at91.c���������������������������������������������������0000644�0001750�0000144�00000040126�10664210265�020152� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_at91.c - define machine at91 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/15/2005 rewrite interrupt simulation * walimis <wlm@student.dlut.edu.cn> * * 3/24/2003 init this file. * add machine at91's function.Most taken from original armio.c * include: at91_mach_init, at91_io_do_cycle * at91_io_read_word, at91_io_write_word * walimis <wlm@student.dlut.edu.cn> * *3/24/2003 chenyu <chenyu-tmlinux@hpclab.cs.tsinghua.edu.cn> has done the * necessary work to armio.c * */ #include "armdefs.h" #include "at91.h" #define DEBUG 0 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr, ##a) #else #define DBG_PRINT(a...) #endif //chy 2005-07-28 //zzc:2005-1-1 #ifdef __CYGWIN__ #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" extern unsigned int Pen_buffer[8]; typedef struct at91_timer_s{ ARMword ccr; ARMword cmr; ARMword cv; ARMword ra; ARMword rb; ARMword rc; ARMword sr; ARMword ier; ARMword idr; ARMword imr; }at91_timer_t; typedef struct at91_io { ARMword syscon; /* System control */ ARMword sysflg; /* System status flags */ /* rewrite interrupt code. * */ u32 ivr; u32 fvr; u32 isr; u32 ipr; u32 imr; u32 cisr; u32 iecr; u32 idcr; u32 iccr; u32 iscr; u32 eoicr; u32 spu; ARMword tcd[3]; /* Timer/counter data */ ARMword tcd_reload[3]; /* Last value written */ at91_timer_t tc_channel[3]; ARMword uartdr; /* Receive data register */ ARMword lcdcon; /* LCD control */ ARMword lcd_limit; /* 0xc0000000 <= LCD buffer < lcd_limi t */ ARMword ts_buffer[8]; ARMword ts_addr_begin; ARMword ts_addr_end; } at91_io_t; static at91_io_t at91_io; #define io at91_io static void at91_update_int (ARMul_State * state) { ARMword requests = io.ipr & io.imr; state->NfiqSig = (requests & 0x00001) ? LOW : HIGH; state->NirqSig = (requests & 0x3fffe) ? LOW : HIGH; } /* new added functions * */ static void at91_set_intr (u32 interrupt) { io.ipr |= (1 << interrupt); } static int at91_pending_intr (u32 interrupt) { return ((io.ipr & (1 << interrupt))); } static void at91_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; ARMword requests = io.ipr & io.imr; state->NfiqSig = (requests & 0x00001) ? LOW : HIGH; state->NirqSig = (requests & 0x3fffe) ? LOW : HIGH; } static int at91_mem_read_byte (void *mach, u32 addr, u32 * data) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; *data = (u32) mem_read_char (state, addr); } static int at91_mem_write_byte (void *mach, u32 addr, u32 data) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; mem_write_char (state, addr, (char) data); } static void at91_io_reset (void * curr_state) { ARMul_State * state = (ARMul_State *)curr_state; io.syscon = 0; io.sysflg = URXFE; io.tcd[0] = 0xffff; io.tcd[1] = 0xffff; io.tcd[2] = 0xffff; io.tcd_reload[0] = 0xffff; io.tcd_reload[1] = 0xffff; io.tcd_reload[2] = 0xffff; io.uartdr = 0; io.lcdcon = 0; io.lcd_limit = 0; io.ts_addr_begin = 0xff00b000; io.ts_addr_end = 0xff00b01f; } static ARMword rpr; int rcr; /*at91 io_do_cycle*/ void at91_io_do_cycle (void * curr_state) { int t; ARMul_State * state = curr_state; for (t = 0; t < 3; t++) { if (io.tcd[t] == 0) { if (io.syscon & (t ? TC2M : TC1M)) { io.tcd[t] = io.tcd_reload[t]; } else { io.tcd[t] = 0xffff; } at91_set_intr (t ? IRQ_TC2 : IRQ_TC1); at91_update_int (state); io.tc_channel[2].sr |= 0x10; /* Set CPCS bit of SR */ } else { io.tcd[t]--; if(io.tcd[t] == 0x1000){ io.tc_channel[t].sr |= 0x10; /* Set CPCS bit of SR */ } } } if (rcr > 0 && !(io.ipr & IRQ_USART0)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf[16]; int n, i; tv.tv_sec = 0; tv.tv_usec = 0; if((n = skyeye_uart_read(-1, buf, rcr > sizeof (buf) ? sizeof (buf) : rcr, &tv, NULL)) > 0) { for (i = 0; i < n; i++, rcr--, rpr++) mem_write_char (state, rpr, buf[i]); if (rcr == 0) io.sysflg &= ~URXFE; at91_set_intr (IRQ_USART0); at91_update_int (state); } } /* if (rcr > 0 && ... */ #ifndef NO_LCD if (!(io.ipr & IRQ_EXT1)) { //if now has no ts interrupt,then query if (Pen_buffer[6] == 1) { //should trigger a interrupt *(io.ts_buffer + 0) = Pen_buffer[0]; *(io.ts_buffer + 1) = Pen_buffer[1]; *(io.ts_buffer + 4) = Pen_buffer[4]; *(io.ts_buffer + 6) = Pen_buffer[6]; at91_set_intr (IRQ_EXT1); Pen_buffer[6] = 0; } } #endif at91_update_int (state); } /* * * Atmel serial support for uClinux console. * */ static char *uart_reg[] = { "CR", "MR", "IER", "IDR", "IMR", "CSR", "RHR", "THR", "BRGR", "RTOR", "TTGR", "RES1", "RPR", "RCR", "TPR", "TCR", }; static ARMword uart_read (ARMul_State * state, ARMword addr) { ARMword data; switch ((addr & 0xfff) >> 2) { case 0xd: // RCR data = rcr; break; case 0xf: // TCR data = 0; break; case 0x5: // CSR data = (1 << 9) | (1 << 1) | /* always empty and ready */ (rcr ? ((1 << 3) | (1 << 0)) : 0); break; case 0x0: // CR case 0x1: // MR case 0x2: // IER case 0x3: // IDR case 0x4: // IMR case 0x6: // RHR case 0x7: // THR case 0x8: // BRGR case 0x9: // RTOR case 0xa: // TTGR case 0xb: // RES1 case 0xc: // RPR case 0xe: // TPR DBG_PRINT ("uart_read(%s=0x%08x)\n", uart_reg[(addr & 0xfff) >> 2], addr); break; default: fprintf(stderr, "IO erro in %s, addr=0x%x\n", __FUNCTION__, addr); // skyeye_exit(-1); } return (data); } static void uart_write (ARMul_State * state, ARMword addr, ARMword data) { static ARMword tx_buf = 0; DBG_PRINT ("uart_write(0x%x, 0x%x)\n", (addr & 0xfff) >> 2, data); switch ((addr & 0xfff) >> 2) { case 0x0: // CR case 0x3: // IDR case 0x9: // RTOR case 0x2: // IER break; case 0x1: // MR case 0x4: // IMR case 0x5: // CSR case 0x6: // RHR DBG_PRINT ("uart_write(%s=0x%x) = 0x%08x\n", uart_reg[(addr & 0xfff) >> 2], addr, data); break; case 0x7: // THR { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } //printf("%c", data); fflush(stdout); break; case 0x8: // BRGR case 0xa: // TTGR case 0xb: // RES1 DBG_PRINT ("uart_write(%s=0x%x) = 0x%08x\n", uart_reg[(addr & 0xfff) >> 2], addr, data); break; case 0xd: // RCR rcr = data; if (rcr == 0) io.sysflg &= ~URXFE; else io.sysflg |= URXFE; break; case 0xc: // RPR DBG_PRINT ("uart_write(%s=0x%x) = 0x%08x\n", uart_reg[(addr & 0xfff) >> 2], addr, data); rpr = data; break; case 0xe: // TPR tx_buf = data; break; case 0xf: // TCR for (; tx_buf && data > 0; data--) { char c = mem_read_char (state, tx_buf++); /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); //printf("%c", mem_read_char(state, tx_buf++)); //fflush(stdout); } tx_buf = 0; break; default: fprintf(stderr, "IO erro in %s\n", __FUNCTION__); skyeye_exit(-1); } } static ARMword timer_read(int index, ARMul_State * state, int offset){ ARMword data; at91_timer_t * timer = &io.tc_channel[index]; switch(offset){ case 0x0: /* TIMER 1 CCR */ data = timer->ccr; break; case 0x4: /* TIMER 1 CMR */ data = timer->cmr; break; case 0x10: /* TIMER 1 CV */ data = timer->cv; data = io.tcd[0]; break; case 0x14: /* TIMER 1 RA */ data = timer->ra; break; case 0x18: /* TIMER 1 RB */ data = timer->rb; break; case 0x1c: /* TIMER 1 RC */ data = timer->rc; break; case 0x20: /* TIMER 1 SR */ data = timer->sr; if(timer->sr & 0x10) timer->sr &= ~0x10; //fprintf(stderr, "timer %d read sr,data=0x%x\n",index, data); //io.ipr &= ~(1<<IRQ_TC1); break; case 0x24: /* TIMER 1 IER */ data = timer->ier; break; case 0x28: /* TIMER 1 IDR */ data = timer->idr; break; case 0x2C: /* TIMER 1 IMR */ data = timer->imr; break; default: fprintf(stderr, "IO erro in %s, offset=0x%x\n", __FUNCTION__, offset); //skyeye_exit(-1); } return data; } static void timer_write(int index, ARMul_State * state, int offset, ARMword data){ at91_timer_t * timer = &io.tc_channel[index]; switch(offset){ case 0x0: /* TIMER 1 CCR */ timer->ccr = data; if (data & 0x2) { io.syscon &= ~TC1M; } else { io.syscon |= TC1M; } break; case 0x4: /* TIMER 1 CMR */ timer->cmr = data; break; case 0x10: /* TIMER 1 CV */ timer->cv = data ; io.tcd[0] = io.tcd_reload[0] = data & 0xffff; break; case 0x14: /* TIMER 1 RA */ timer->ra = data; break; case 0x18: /* TIMER 1 RB */ timer->rb = data; break; case 0x1c: /* TIMER 1 RC */ timer->rc = data; io.tcd[0] = io.tcd_reload[0] = data & 0xffff; break; case 0x20: /* TIMER 1 SR */ timer->sr = data; //io.ipr &= ~(1<<IRQ_TC1); break; case 0x24: /* TIMER 1 IER */ timer->ier = data; break; case 0x28: /* TIMER 1 IDR */ timer->idr = data; break; case 0x2C: /* TIMER 1 IMR */ timer->imr = data; break; default: fprintf(stderr, "IO erro in %s ,addr=0x%x\n", __FUNCTION__, offset); //skyeye_exit(-1); } } static ARMword at91_io_read_byte (ARMul_State * state, ARMword addr) { fprintf(stderr, "IO erro in %s, addr=0x%x\n", __FUNCTION__,addr); return 0; } ARMword at91_io_read_halfword (ARMul_State * state, ARMword addr) { fprintf(stderr, "IO erro in %s\n", __FUNCTION__); return 0; } ARMword at91_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = -1; int i; ARMword ts_addr; ts_addr = addr & ~3; // 1 word==4 byte if (ts_addr >= io.ts_addr_begin && ts_addr <= io.ts_addr_end) { data = io.ts_buffer[(ts_addr - io.ts_addr_begin) / 4]; return data; } switch (addr) { case 0xfffff100: /* IVR */ data = io.ipr; DBG_PRINT ("IVR irqs=%x ", data); for (i = 0; i < 32; i++) if (data & (1 << i)) break; if (i < 32) { data = i; io.ipr &= ~(1 << data); at91_update_int (state); } else data = 0; io.ivr = data; //current_ivr = data; DBG_PRINT ("read IVR=%d\n", data); break; case 0xfffff108: /* interrupt status register */ // data = current_ivr; data = io.ivr; break; case 0xfffff110: /* IMR */ data = io.imr; break; case 0xfffff114: /* CORE interrupt status register */ data = io.cisr; data = io.imr; break; case 0xfffff120: /* IECR */ data = io.iecr; data = io.imr; break; case 0xfffff124: /* IDCR */ break; case 0xfff00000: /* CPU ID */ data = 0x2078aa0; data = 0x14000040; break; case 0xfffe00c0: /* TIMER 1 BCR */ DBG_PRINT ("T1-BCR io_read_word(0x%08x) = 0x%08x\n", addr, data); break; case 0xfffe00c4: /* TIMER 1 BMR */ DBG_PRINT ("T1-BMR io_read_word(0x%08x) = 0x%08x\n", addr, data); break; default: if ((addr & 0xffffff00) == 0xfffff000) break; if ((addr & 0xfffff000) == 0xfffd0000) { return uart_read (state, addr); } if ((addr & 0xfffff000) == 0xfffcc000) { //return uart_read (state, addr); break; } if(addr >= 0xfffe0000 && addr < 0xfffe00c0){ return timer_read(((addr & 0xc0) >> 6), state, (addr & 0x3f)); } //fprintf (stderr, // "NumInstr %llu, io_read_word unknown addr(0x%08x) = 0x%08x\n", // state->NumInstrs, addr, data); //SKYEYE_OUTREGS (stderr); //ARMul_Debug(state, 0, 0); break; } return data; } void at91_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { fprintf(stderr," IO error in %s,addr=0x%x\n", __FUNCTION__); return; } void at91_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { fprintf(stderr," IO error in %s\n", __FUNCTION__); return; } void at91_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { /* * The Atmel system registers */ if(addr >= 0xfffe0000 && addr < 0xfffe00c0){ timer_write((addr & 0xc0), state, (addr & 0x3f), data); return; } switch (addr) { case 0xfffff108: /* ISR */ //DBG_PRINT("write ISR=0x%x\n", data); //io.isr = data; break; case 0xfffff110: /* IMR */ //io.imr = data; break; case 0xfffff114: /* CORE interrupt status register */ //io.cisr = data; DBG_PRINT ("write CISR=0x%x\n", data); break; case 0xfffff120: /* IECR */ DBG_PRINT ("IECR=0x%x\n", data); io.iecr = data; io.imr |= data; break; case 0xfffff124: /* IDCR */ DBG_PRINT ("IDCR=0x%x\n", data); io.idcr = data; io.imr &= ~data; break; case 0xfffff128: /* CLEAR interrupts */ DBG_PRINT ("ICCR=0x%x\n", data); io.iccr = data; io.ipr &= ~data; break; case 0xfffff130: /* EOI */ DBG_PRINT (stderr, "EOI=0x%x\n", data); /** * 2.4.32 in uClinux is broken somehow and always sends * 0xfffff130 as both address and data, sometimes clearing * not yet processed interrupt. Anyway, the thing * works without the following */ #if 0 io.eoicr = data; io.ipr &= ~data; #endif at91_update_int (state); break; case 0xfff00000: /* CPU ID */ break; case 0xfffe00c0: /* TIMER 1 BCR */ DBG_PRINT ("T1-BCR io_write_word(0x%08x) = 0x%08x\n", addr, data); break; case 0xfffe00c4: /* TIMER 1 BMR */ DBG_PRINT ("T1-BMR io_write_word(0x%08x) = 0x%08x\n", addr, data); break; default: if ((addr & 0xfffff000) == 0xfffd0000) { uart_write (state, addr, data); break; } if ((addr & 0xfffff000) == 0xfffcc000) { //uart_write (state, addr, data); break; } if ((addr & 0xffffff00) == 0xfffff000) break; if ((addr & 0xffff0000) == 0xffff0000) { DBG_PRINT ("io_write_word(0x%08x) = 0x%08x\n", addr, data); break; } //DBG_PRINT("io_write_word(0x%08x) = 0x%08x\n", addr, data); //fprintf (stderr, // "NumInstr %llu,io_write_word unknown addr(0x%08x) = 0x%08x\n", // state->NumInstrs, addr, data); //SKYEYE_OUTREGS (stderr); //ARMul_Debug(state, 0, 0); break; } } void at91_mach_init (void * curr_state, machine_config_t * this_mach) { ARMul_State *state = (ARMul_State *)curr_state; //chy 2003-08-19, setprocessor ARMul_SelectProcessor (state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; this_mach->mach_io_do_cycle = at91_io_do_cycle; this_mach->mach_io_reset = at91_io_reset; this_mach->mach_io_read_byte = at91_io_read_byte; this_mach->mach_io_write_byte = at91_io_write_byte; this_mach->mach_io_read_halfword = at91_io_read_halfword; this_mach->mach_io_write_halfword = at91_io_write_halfword; this_mach->mach_io_read_word = at91_io_read_word; this_mach->mach_io_write_word = at91_io_write_word; this_mach->mach_update_int = at91_update_int; this_mach->mach_set_intr = at91_set_intr; this_mach->mach_pending_intr = at91_pending_intr; this_mach->mach_update_intr = at91_update_intr; this_mach->mach_mem_read_byte = at91_mem_read_byte; this_mach->mach_mem_write_byte = at91_mem_write_byte; this_mach->state = (void *) state; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/s3c44b0.h������������������������������������������������������������0000644�0001750�0000144�00000025770�10602441302�016100� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* taken from http://www.start-web.net/tpu/. many thanks to tpu <tapu@371.net> * add by walimis. <wlm@student.dlut.edu.cn> * */ /********************************************************/ /* */ /* Samsung S3C44B0 */ /* tpu <tapu@371.net> */ /* */ /********************************************************/ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H #define REGBASE 0x01c00000 #define REGL(addr) ((REGBASE+addr)) #define REGW(addr) ((REGBASE+addr)) #define REGB(addr) ((REGBASE+addr)) /*****************************/ /* CPU Wrapper Registers */ /*****************************/ #define SYSCFG REGL(0x000000) #define NCACHBE0 REGL(0x000004) #define NCACHBE1 REGL(0x000008) #define SBUSCON REGL(0x040000) /************************************/ /* Memory Controller Registers */ /************************************/ #define BWSCON REGL(0x080000) #define BANKCON0 REGL(0x080004) #define BANKCON1 REGL(0x080008) #define BANKCON2 REGL(0x08000c) #define BANKCON3 REGL(0x080010) #define BANKCON4 REGL(0x080014) #define BANKCON5 REGL(0x080018) #define BANKCON6 REGL(0x08001c) #define BANKCON7 REGL(0x080020) #define REFRESH REGL(0x080024) #define BANKSIZE REGL(0x080028) #define MRSRB6 REGL(0x08002c) #define MRSRB7 REGL(0x080030) /*********************/ /* UART Registers */ /*********************/ #define ULCON0 REGL(0x100000) #define ULCON1 REGL(0x104000) #define UCON0 REGL(0x100004) #define UCON1 REGL(0x104004) #define UFCON0 REGL(0x100008) #define UFCON1 REGL(0x104008) #define UMCON0 REGL(0x10000c) #define UMCON1 REGL(0x10400c) #define UTRSTAT0 REGL(0x100010) #define UTRSTAT1 REGL(0x104010) #define UERSTAT0 REGL(0x100014) #define UERSTAT1 REGL(0x104014) #define UFSTAT0 REGL(0x100018) #define UFSTAT1 REGL(0x104018) #define UMSTAT0 REGL(0x10001c) #define UMSTAT1 REGL(0x10401c) #define UTXH0 REGB(0x100020) #define UTXH1 REGB(0x104020) #define URXH0 REGB(0x100024) #define URXH1 REGB(0x104024) #define UBRDIV0 REGL(0x100028) #define UBRDIV1 REGL(0x104028) /*******************/ /* SIO Registers */ /*******************/ #define SIOCON REGL(0x114000) #define SIODAT REGL(0x114004) #define SBRDR REGL(0x114008) #define ITVCNT REGL(0x11400c) #define DCNTZ REGL(0x114010) /********************/ /* IIS Registers */ /********************/ #define IISCON REGL(0x118000) #define IISMOD REGL(0x118004) #define IISPSR REGL(0x118008) #define IISFIFCON REGL(0x11800c) #define IISFIF REGW(0x118010) /**************************/ /* I/O Ports Registers */ /**************************/ #define PCONA REGL(0x120000) #define PDATA REGL(0x120004) #define PCONB REGL(0x120008) #define PDATB REGL(0x12000c) #define PCONC REGL(0x120010) #define PDATC REGL(0x120014) #define PUPC REGL(0x120018) #define PCOND REGL(0x12001c) #define PDATD REGL(0x120020) #define PUPD REGL(0x120024) #define PCONE REGL(0x120028) #define PDATE REGL(0x12002c) #define PUPE REGL(0x120030) #define PCONF REGL(0x120034) #define PDATF REGL(0x120038) #define PUPF REGL(0x12003c) #define PCONG REGL(0x120040) #define PDATG REGL(0x120044) #define PUPG REGL(0x120048) #define SPUCR REGL(0x12004c) #define EXTINT REGL(0x120050) #define EXTINTPND REGL(0x120054) /*********************************/ /* WatchDog Timers Registers */ /*********************************/ #define WTCON REGL(0x130000) #define WTDAT REGL(0x130004) #define WTCNT REGL(0x130008) /*********************************/ /* A/D Converter Registers */ /*********************************/ #define ADCCON REGL(0x140000) #define ADCPSR REGL(0x140004) #define ADCDAT REGL(0x140008) /***************************/ /* PWM Timer Registers */ /***************************/ #define TCFG0 REGL(0x150000) #define TCFG1 REGL(0x150004) #define TCON REGL(0x150008) #define TCNTB0 REGL(0x15000c) #define TCMPB0 REGL(0x150010) #define TCNTO0 REGL(0x150014) #define TCNTB1 REGL(0x150018) #define TCMPB1 REGL(0x15001c) #define TCNTO1 REGL(0x150020) #define TCNTB2 REGL(0x150024) #define TCMPB2 REGL(0x150028) #define TCNTO2 REGL(0x15002c) #define TCNTB3 REGL(0x150030) #define TCMPB3 REGL(0x150034) #define TCNTO3 REGL(0x150038) #define TCNTB4 REGL(0x15003c) #define TCMPB4 REGL(0x150040) #define TCNTO4 REGL(0x150044) #define TCNTB5 REGL(0x150048) #define TCNTO5 REGL(0x15004c) /*********************/ /* IIC Registers */ /*********************/ #define IICCON REGL(0x160000) #define IICSTAT REGL(0x160004) #define IICADD REGL(0x160008) #define IICDS REGL(0x16000c) /*********************/ /* RTC Registers */ /*********************/ #define RTCCON REGB(0x170040) #define RTCALM REGB(0x170050) #define ALMSEC REGB(0x170054) #define ALMMIN REGB(0x170058) #define ALMHOUR REGB(0x17005c) #define ALMDAY REGB(0x170060) #define ALMMON REGB(0x170064) #define ALMYEAR REGB(0x170068) #define RTCRST REGB(0x17006c) #define BCDSEC REGB(0x170070) #define BCDMIN REGB(0x170074) #define BCDHOUR REGB(0x170078) #define BCDDAY REGB(0x17007c) #define BCDDATE REGB(0x170080) #define BCDMON REGB(0x170084) #define BCDYEAR REGB(0x170088) #define TICINT REGB(0x17008c) /*********************************/ /* Clock & Power Registers */ /*********************************/ #define PLLCON REGL(0x180000) #define CLKCON REGL(0x180004) #define CLKSLOW REGL(0x180008) #define LOCKTIME REGL(0x18000c) /**************************************/ /* Interrupt Controller Registers */ /**************************************/ #define INTCON REGL(0x200000) #define INTPND REGL(0x200004) #define INTMOD REGL(0x200008) #define INTMSK REGL(0x20000c) #define I_PSLV REGL(0x200010) #define I_PMST REGL(0x200014) #define I_CSLV REGL(0x200018) #define I_CMST REGL(0x20001c) #define I_ISPR REGL(0x200020) #define I_ISPC REGL(0x200024) #define F_ISPR REGL(0x200038) #define F_ISPC REGL(0x20003c) /********************************/ /* LCD Controller Registers */ /********************************/ #define LCDCON1 REGL(0x300000) #define LCDCON2 REGL(0x300004) #define LCDSADDR1 REGL(0x300008) #define LCDSADDR2 REGL(0x30000c) #define LCDSADDR3 REGL(0x300010) #define REDLUT REGL(0x300014) #define GREENLUT REGL(0x300018) #define BLUELUT REGL(0x30001c) #define DP1_2 REGL(0x300020) #define DP4_7 REGL(0x300024) #define DP3_5 REGL(0x300028) #define DP2_3 REGL(0x30002c) #define DP5_7 REGL(0x300030) #define DP3_4 REGL(0x300034) #define DP4_5 REGL(0x300038) #define DP6_7 REGL(0x30003c) #define LCDCON3 REGL(0x300040) #define DITHMODE REGL(0x300044) /*********************/ /* DMA Registers */ /*********************/ #define ZDCON0 REGL(0x280000) #define ZDISRC0 REGL(0x280004) #define ZDIDES0 REGL(0x280008) #define ZDICNT0 REGL(0x28000c) #define ZDCSRC0 REGL(0x280010) #define ZDCDES0 REGL(0x280014) #define ZDCCNT0 REGL(0x280018) #define ZDCON1 REGL(0x280020) #define ZDISRC1 REGL(0x280024) #define ZDIDES1 REGL(0x280028) #define ZDICNT1 REGL(0x28002c) #define ZDCSRC1 REGL(0x280030) #define ZDCDES1 REGL(0x280034) #define ZDCCNT1 REGL(0x280038) #define BDCON0 REGL(0x380000) #define BDISRC0 REGL(0x380004) #define BDIDES0 REGL(0x380008) #define BDICNT0 REGL(0x38000c) #define BDCSRC0 REGL(0x380010) #define BDCDES0 REGL(0x380014) #define BDCCNT0 REGL(0x380018) #define BDCON1 REGL(0x380020) #define BDISRC1 REGL(0x380024) #define BDIDES1 REGL(0x380028) #define BDICNT1 REGL(0x38002c) #define BDCSRC1 REGL(0x380030) #define BDCDES1 REGL(0x380034) #define BDCCNT1 REGL(0x380038) #define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) #define INT_ENABLE(n) INTMSK &= ~(1<<(n)) #define INT_DISABLE(n) INTMSK |= (1<<(n)) #define HARD_RESET_NOW() /* below add by walimis. * */ /*Interrupt Pendings*/ #define INT_MASK_INIT 0x07FFFFFF #define INT_ADC (0) #define INT_RTC (1) #define INT_UTXD1 (2) #define INT_UTXD0 (3) #define INT_SIO (4) #define INT_IIC (5) #define INT_URXD1 (6) #define INT_URXD0 (7) #define INT_TIMER5 (8) #define INT_TIMER4 (9) #define INT_TIMER3 (10) #define INT_TIMER2 (11) #define INT_TIMER1 (12) #define INT_TIMER0 (13) #define INT_UERR01 (14) #define INT_WDT (15) #define INT_BDMA1 (16) #define INT_BDMA0 (17) #define INT_ZDMA1 (18) #define INT_ZDMA0 (19) #define INT_TICK (20) #define INT_EINT4567 (21) #define INT_EINT3 (22) #define INT_EINT2 (23) #define INT_EINT1 (24) #define INT_EINT0 (25) #define INT_GLOBAL (26) /*UART TX/RX STATUS register*/ #define UART_LSR_DR 0x01 // Receive data ready #define UART_LSR_THRE 0x02 // Transmit buffer register empty #define UART_LSR_TEMT 0x04 // Transmit complete /*Timer*/ #define TIMER_NUM 6 #define TIMER_INT(n) INT_TIMER##n #define TIMER_OP_START 0x0 #define TIMER_OP_MANUAL 0x1 #define TIMER_OP_INVERTER 0x2 #define TIMER_OP_RELOAD 0x3 #define TIMER_OP(tcon, n, op) (tcon) & ((1 << (op)) << (4 * (n))) /* * IIS extended registers: For device simulation in SkyEye. * 2007-03-25 Added by Anthony Lee. * * Register Bit Description * IISFIF_RX_CONTROL(R) * [20:17] should be 1010 * [16] 0 - empty * 1 - not empty * [15:0] data * * IISFIF_TX_CONTROL(R/W) * [11:8] should be 1010 * [7:4] 0001 - Start to transmit * 0010 - Request state * [3:0] data count */ #define IISFIF_RX_CONTROL (IISFIF + 0x04) #define IISFIF_TX_CONTROL (IISFIF + 0x08) #endif /* __ASM_ARCH_HARDWARE_H */ ��������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_s3c3410x.c�����������������������������������������������0000644�0001750�0000144�00000051433�10607337647�020602� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_s3c3410x.c - SAMSUNG's S3C3410X simulation for skyeye Copyright (C) 2007 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 03/04/2007 Written by Anthony Lee */ /* * COMPLETED: Interrupt, WatchDog, Timer, UART, DMA * UNIMPLEMENTED: I/O Port, etc. */ #include "armdefs.h" #include "armemu.h" #include "s3c3410x.h" #include "skyeye_uart.h" #define S3C3410X_DEBUG 0 #define PRINT(x...) printf("[S3C3410X]: " x) #if S3C3410X_DEBUG #define DEBUG(x...) printf("[S3C3410X]: " x) #else #define DEBUG(x...) (void)0 #endif /* * CYCLE_TIMES_PER_SECOND: * It's near 40000 times on my machine, * you can change the value to fit your machine. */ #define CYCLE_TIMES_PER_SECOND (40000) #define MCLK (40) /* MHz */ #define TIMER_COUNT_UP_PER_SECOND (1000000 * MCLK) /* prescale=1, divider=1 */ #define TIMER_COUNT_UP_PER_CYCLE (TIMER_COUNT_UP_PER_SECOND / CYCLE_TIMES_PER_SECOND) struct s3c3410x_timer_t { ARMword tdat; ARMword tpre; ARMword tcon; ARMword tcnt; ARMword tcnt_scaler; }; struct s3c3410x_dma_t { ARMword con; ARMword src; ARMword dst; ARMword cnt; }; /* S3C3410X Internal IO Registers */ struct s3c3410x_io_t { /* System Registers */ ARMword syscfg; ARMword syscon; /* Interrupt Controller Registers */ ARMword intmod; ARMword intpnd; ARMword intmsk; ARMword intpri[8]; /* Timer Registers */ ARMword btcon; ARMword btcnt; ARMword btcnt_scaler; struct s3c3410x_timer_t timer[5]; ARMword tfcon; ARMword tfstat; uint64_t tf4; ARMword tf4_repeat[2]; /* UART Registers */ ARMword ulcon; ARMword ucon; ARMword ustat; ARMword ufcon; ARMword ufstat; ARMword urxh; ARMword ubrdiv; /* DMA Registers */ struct s3c3410x_dma_t dma[2]; }; static struct s3c3410x_io_t s3c3410x_io; #define io s3c3410x_io extern ARMword mem_read_byte(ARMul_State*, ARMword); extern ARMword mem_read_halfword(ARMul_State*, ARMword); extern ARMword mem_read_word(ARMul_State*, ARMword); extern void mem_write_byte(ARMul_State*, ARMword, ARMword); extern void mem_write_halfword(ARMul_State*, ARMword, ARMword); extern void mem_write_word(ARMul_State*, ARMword, ARMword); static int s3c3410x_dma_is_valid(int index); static void s3c3410x_dma_proccess(ARMul_State *state, int index); static void s3c3410x_io_reset(ARMul_State *state) { int i; memset(&io, 0, sizeof(io)); /* System */ io.syscfg = 0xfff1; /* Interrupt */ io.intpri[0] = 0x03020100; io.intpri[1] = 0x07060504; io.intpri[2] = 0x0b0a0908; io.intpri[3] = 0x0f0e0d0c; io.intpri[4] = 0x13121110; io.intpri[5] = 0x17161514; io.intpri[6] = 0x1b1a1918; io.intpri[7] = 0x1f1e1d1c; /* Timer */ for (i = 0; i < 5; i++) io.timer[i].tpre = 0xff; for (i = 0; i < 3; i++) io.timer[i].tdat = 0xffff; for (i = 3; i < 5; i++) io.timer[i].tdat = 0xff; /* UART */ io.ustat = 0xc0; } /* Interrupt Routine */ static void s3c3410x_update_int(ARMul_State *state) { ARMword requests = (io.syscon & 0x40) ? (io.intpnd & io.intmsk) : 0x0; state->NfiqSig = (requests & io.intmod) ? LOW : HIGH; state->NirqSig = (requests & ~io.intmod) ? LOW : HIGH; } static void s3c3410x_set_interrupt(unsigned int irq) { io.intpnd |= (0x1 << irq); } static void s3c3410x_interrupt_read(ARMword addr, ARMword *data) { switch (addr) { case INTMOD: *data = io.intmod; break; case INTPND: *data = io.intpnd; break; case INTMSK: *data = io.intmsk; break; case INTPRI0: case INTPRI1: case INTPRI2: case INTPRI3: case INTPRI4: case INTPRI5: case INTPRI6: case INTPRI7: *data = io.intpri[(addr - INTPRI0) / 0x4]; break; default: break; } DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c3410x_interrupt_write(ARMul_State *state, ARMword addr, ARMword data) { DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); switch (addr) { case INTMOD: io.intmod = data; break; case INTPND: io.intpnd &= data; break; case INTMSK: io.intmsk = data; break; case INTPRI0: case INTPRI1: case INTPRI2: case INTPRI3: case INTPRI4: case INTPRI5: case INTPRI6: case INTPRI7: io.intpri[(addr - INTPRI0) / 0x4] = data; break; default: break; } } /* Timer Routine */ static void s3c3410x_timer_do_cycle(ARMul_State *state) { int i, k; ARMword tdat, count, empty_count; ARMword cnt_up, cnt_divider, cnt_clock_divider = 1; #if 0 switch ((io.syscon >> 3) & 0x7) { case 0: cnt_clock_divider = 16; break; case 1: cnt_clock_divider = 8; break; case 2: cnt_clock_divider = 2; break; case 4: cnt_clock_divider = 1024; break; default: break; } #endif for (i = 0; i < 5; i++) { if ((io.timer[i].tcon & 0x80) == 0) continue; if (i < 4 || (io.tfcon & 0x1) == 0) { tdat = io.timer[i].tdat; } else { if ((count = (io.tfstat & 0x7)) == 0) break; if (io.timer[4].tcnt == (tdat = (io.tf4 & 0xff))) { if (io.tf4_repeat[0] == 0) { io.tf4_repeat[0] = io.tf4_repeat[1]; if ((empty_count = ((io.tfcon >> 2) & 0x3)) > 0) { if (empty_count == 3) empty_count = 4; if (io.tfstat & 0x8) count++; io.tfstat = count - min(empty_count, count); io.tf4 >>= (empty_count << 3); } s3c3410x_set_interrupt(INT_TF); } else { io.tf4_repeat[0] -= 1; } } } cnt_divider = cnt_clock_divider * (io.timer[i].tpre + 1) << (i < 3 ? 0 : (1 << (4 - (io.timer[i].tcon & 0x3)))); cnt_up = TIMER_COUNT_UP_PER_CYCLE / cnt_divider; if (cnt_up == 0) { if (io.timer[i].tcnt_scaler == 0) { io.timer[i].tcnt_scaler = cnt_divider / TIMER_COUNT_UP_PER_CYCLE; continue; } else if ((io.timer[i].tcnt_scaler -= 1) != 0) { continue; } cnt_up = 1; } switch ((io.timer[i].tcon >> 3) & 0x7) { case 0: /* Interval Mode */ if (io.timer[i].tcnt == tdat) { s3c3410x_set_interrupt(INT_TMC0 + i * 2); io.timer[i].tcnt = 0; break; } if (io.timer[i].tcnt > tdat) break; io.timer[i].tcnt += min(tdat - io.timer[i].tcnt, cnt_up); break; case 1: /* Match & overflow mode (Timer0/1/2), PWM mode (Timer3/4) */ if (io.timer[i].tcnt == tdat) { s3c3410x_set_interrupt(INT_TMC0 + i * 2); } if (io.timer[i].tcnt == (i < 3 ? 0xffff : 0xff)) { s3c3410x_set_interrupt(INT_TOF0 + i * 2); io.timer[i].tcnt = 0; break; } io.timer[i].tcnt += min((io.timer[i].tcnt < tdat ? tdat : (i < 3 ? 0xffff : 0xff)) - io.timer[i].tcnt, cnt_up); break; case 2: /* Match & DMA mode */ if (!(i == 1 || i == 3)) break; for (k = 0; k < 2; k++) { if (s3c3410x_dma_is_valid(k) != 1) continue; if (((io.dma[k].con >> 2) & 0x3) != 0x3) continue; if (i == 1 && io.dma[k].dst == TDAT1) break; if (i == 3 && io.dma[k].dst == TDAT3) break; } if (k == 2) break; if (io.timer[i].tcnt == tdat) { s3c3410x_set_interrupt(INT_TMC0 + i * 2); io.timer[i].tcnt = 0; s3c3410x_dma_proccess(state, k); break; } if (io.timer[i].tcnt > tdat) break; io.timer[i].tcnt += min(tdat - io.timer[i].tcnt, cnt_up); break; default: /* Other mode unimplemented yet */ break; } } /* Basic Timer and WatchDog */ cnt_divider = 1 << (13 - ((io.btcon >> 2) & 0x3)); cnt_up = TIMER_COUNT_UP_PER_CYCLE / cnt_divider; if (cnt_up == 0) { if (io.btcnt_scaler == 0) { io.btcnt_scaler = cnt_divider / TIMER_COUNT_UP_PER_CYCLE; goto next; } else if ((io.btcnt_scaler -= 1) != 0) { goto next; } cnt_up = 1; } if (io.btcnt == 0xff) { io.btcnt = 0; s3c3410x_set_interrupt(INT_BT); } else { io.btcnt += min(0xff - io.btcnt, cnt_up); } if (io.btcon & 0x10000) { ARMword wdt = (io.btcon >> 8) & 0xff; if (wdt == 0xff) { /* asserts reset signal */ state->NresetSig = LOW; PRINT("****************** WATCHDOG RESET ******************\n"); } else { io.btcon = (io.btcon & ~0xff00) | ((wdt + min(0xff - wdt, cnt_up)) << 8); } } next: return; } static void s3c3410x_timer_read(ARMword offset, ARMword *data, int index) { switch (offset) { case 0: /* TDAT */ *data = io.timer[index].tdat; break; case 2: /* TPRE */ *data = io.timer[index].tpre; break; case 3: /* TCON */ *data = io.timer[index].tcon; break; case 6: /* TCNT */ *data = io.timer[index].tcnt; break; case 0x8: /* TFW4 */ if (index != 4) break; if ((io.tfcon & 0x1) == 0 || io.tfstat == 0) break; *data = io.tf4 & 0xffffffff; io.tf4 >>= 32; io.tfstat = (io.tfstat < 7 ? (io.tfstat - min(io.tfstat, 4)) : (io.tfstat & ~0x8)); break; case 0xa: /* TFHW4 */ if (index != 4) break; if ((io.tfcon & 0x1) == 0 || io.tfstat == 0) break; *data = io.tf4 & 0xffff; io.tf4 >>= 16; io.tfstat = (io.tfstat < 7 ? (io.tfstat - min(io.tfstat, 2)) : (io.tfstat & ~0x8)); break; case 0xb: /* TFB4 */ if (index != 4) break; if ((io.tfcon & 0x1) == 0 || io.tfstat == 0) break; *data = io.tf4 & 0xff; io.tf4 >>= 8; io.tfstat = (io.tfstat < 7 ? (io.tfstat - 1) : (io.tfstat & ~0x8)); break; case 0xe: /* TFSTAT */ if (index == 4) *data = io.tfstat; break; case 0xf: /* TFCON */ if (index == 4) *data = io.tfcon; break; default: break; } DEBUG("%s(Timer%d, offset:0x%x, data:0x%x)\n", __FUNCTION__, index, offset, *data); } static void s3c3410x_timer_write(ARMul_State *state, ARMword offset, ARMword data, int index) { DEBUG("%s(Timer%d, offset:0x%x, data:0x%x)\n", __FUNCTION__, index, offset, data); switch (offset) { case 0: /* TDAT */ io.timer[index].tdat = min(data, (index < 3 ? 0xffff : 0xff)); break; case 2: /* TPRE */ io.timer[index].tpre = min(data, 0xff); break; case 3: /* TCON */ io.timer[index].tcon = min((data & ~0x40), 0xff); if (data & 0x40) io.timer[index].tcnt = 0; break; case 0x8: /* TFW4 */ if (index != 4) break; if ((io.tfcon & 0x1) == 0 || io.tfstat > 7) break; io.tf4 &= ~(((uint64_t)0xffffffff) << (io.tfstat << 3)); io.tf4 |= (((uint64_t)data) << (io.tfstat << 3)); io.tfstat += (io.tfstat < 4 ? 4 : 8); break; case 0xa: /* TFHW4 */ if (index != 4) break; if ((io.tfcon & 0x1) == 0 || io.tfstat > 7) break; io.tf4 &= ~(((uint64_t)0xffff) << (io.tfstat << 3)); io.tf4 |= (((uint64_t)min(data, 0xffff)) << (io.tfstat << 3)); io.tfstat += (io.tfstat < 6 ? 2 : 8); break; case 0xb: /* TFB4 */ if (index != 4) break; if ((io.tfcon & 0x1) == 0 || io.tfstat > 7) break; io.tf4 &= ~(((uint64_t)0xff) << (io.tfstat << 3)); io.tf4 |= (((uint64_t)min(data, 0xff)) << (io.tfstat << 3)); io.tfstat += (io.tfstat < 7 ? 1 : 8); break; case 0xf: /* TFCON */ if (index == 4) { io.tfcon = min((data & ~0x2), 0xff); if (data & 0x2) io.tfstat = 0; if (data & 0x1) { io.tf4_repeat[1] = (1 << ((data >> 4) & 0x3)) - 1; io.tf4_repeat[0] = io.tf4_repeat[1]; } } break; default: break; } } /* UART Routine */ static void s3c3410x_uart_do_cycle(ARMul_State *state) { int i; unsigned char buf; struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; if ((io.ustat & 0x20) == 0 && (io.ucon & 0x3) != 0) { if (skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.urxh = buf; io.ustat |= 0x20; io.ufstat = (io.ufstat & ~0x7) | 0x1; if ((io.ucon & 0x3) == 0x1) s3c3410x_set_interrupt(INT_URX); } } for (i = 0; i < 2; i++) { /* DMA request */ if ((io.ucon & 0x3) == 0x2 + i || (io.ucon & 0xc) == 0x8 + i) { int rx_empty = ((io.ucon & 0x3) != 0x0 ? ((io.ustat & 0x20) == 0) : 1); int tx_ready = ((io.ucon & 0xc) != 0x0 ? 1 : 0); ARMword mask = 0; do { if (s3c3410x_dma_is_valid(i) != 1) break; if (((io.dma[i].con >> 2) & 0x3) != 0x2) break; if ((io.dma[i].dst == UTXH || io.dma[i].dst == UTXH_HW || io.dma[i].dst == UTXH_W) && tx_ready) mask |= 0x2 + i; if ((io.dma[i].src == URXH || io.dma[i].src == URXH_HW || io.dma[i].src == URXH_W) && !rx_empty) mask |= 0x8 + i; if ((io.ucon & mask) != 0) s3c3410x_dma_proccess(state, i); } while (0); } } } static void s3c3410x_uart_read(ARMword addr, ARMword *data) { switch (addr) { case ULCON: *data = io.ulcon; break; case UCON: *data = io.ucon; break; case USTAT: *data = io.ustat; break; case UFCON: *data = io.ufcon; break; case UFSTAT: *data = io.ufstat; break; case URXH_W: case URXH_HW: case URXH: *data = io.urxh; io.ustat &= ~0x20; io.ufstat &= ~0x7; break; case UBRDIV: *data = io.ubrdiv; break; default: break; } DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data); } static void s3c3410x_uart_write(ARMul_State *state, ARMword addr, ARMword data) { int cnt = 0; DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data); switch (addr) { case ULCON: io.ulcon = data; break; case UCON: io.ucon = data; break; case UFCON: io.ufcon = data; break; case UTXH_W: cnt = 4; break; case UTXH_HW: cnt = 2; break; case UTXH: cnt = 1; break; case UBRDIV: io.ubrdiv = data; break; default: break; } if (cnt > 0 && (io.ucon & 0xc)) { do { char tmp = data & 0xff; data >>= 8; skyeye_uart_write(-1, (void*)&tmp, 1, NULL); } while (--cnt > 0); if ((io.ucon & 0xc) == 0x4) s3c3410x_set_interrupt(INT_UTX); } } /* DMA Routine */ static int s3c3410x_dma_is_valid(int index) { if (!(io.dma[index].con & 0x1)) return -1; if (io.dma[index].cnt == 0) return -1; if (((io.dma[index].con >> 2) & 0x3) == 0x1) return -1; if (((io.dma[index].con >> 2) & 0x3) != 0x0) return 1; return 0; } static void s3c3410x_dma_proccess(ARMul_State *state, int index) { ARMword data, bytes, n = 0; if (io.dma[index].cnt == 0) return; io.dma[index].con |= 0x2; restart: switch ((bytes = (1 << ((io.dma[index].con >> 12) & 0x3)))) { case 1: data = mem_read_byte(state, io.dma[index].src); mem_write_byte(state, io.dma[index].dst, data); break; case 2: data = mem_read_halfword(state, io.dma[index].src); mem_write_halfword(state, io.dma[index].dst, data); break; case 4: data = mem_read_word(state, io.dma[index].src); mem_write_word(state, io.dma[index].dst, data); break; default: return; } if (!((io.dma[index].con >> 7) & 0x1)) { if (((io.dma[index].con >> 5) & 0x1) && io.dma[index].src >= bytes) io.dma[index].src -= bytes; else if (io.dma[index].src <= 0xffffffe - bytes) io.dma[index].src++; } if (!((io.dma[index].con >> 6) & 0x1)) { if (((io.dma[index].con >> 4) & 0x1) && io.dma[index].dst >= bytes) io.dma[index].dst -= bytes; else if (io.dma[index].dst <= 0xffffffe - bytes) io.dma[index].dst++; } if (((io.dma[index].con >> 9) & 0x1) && ++n < 4) goto restart; io.dma[index].cnt -= 1; if (io.dma[index].cnt != 0 && ((io.dma[index].con >> 14) & 0x1)) { if (((io.dma[index].con >> 2) & 0x3) == 0x0) { n = 0; goto restart; } } if (io.dma[index].cnt == 0) { io.dma[index].con &= ~0x3; s3c3410x_set_interrupt(INT_DMA0 + index); } } static void s3c3410x_dma_do_cycle(ARMul_State *state) { int i; for (i = 0; i < 2; i++) { if (s3c3410x_dma_is_valid(i) != 0) continue; s3c3410x_dma_proccess(state, i); } } static void s3c3410x_dma_read(ARMword offset, ARMword *data, int index) { switch (offset) { case 0x0: /* DMASRC */ *data = io.dma[index].src; break; case 0x4: /* DMADST */ *data = io.dma[index].dst; break; case 0x8: /* DMACNT */ *data = io.dma[index].cnt; break; case 0xc: /* DMACON */ *data = io.dma[index].con; break; default: break; } DEBUG("%s(DMA%d, offset:0x%x, data:0x%x)\n", __FUNCTION__, index, offset, *data); } static void s3c3410x_dma_write(ARMul_State *state, ARMword offset, ARMword data, int index) { DEBUG("%s(DMA%d, offset:0x%x, data:0x%x)\n", __FUNCTION__, index, offset, data); switch (offset) { case 0x0: /* DMASRC */ io.dma[index].src = (data & 0xffffffe); break; case 0x4: /* DMADST */ io.dma[index].dst = (data & 0xffffffe); break; case 0x8: /* DMACNT */ io.dma[index].cnt = (data & 0x7ffffff); break; case 0xc: /* DMACON */ io.dma[index].con = (io.dma[index].con & 0x2) | (data & ~0x2); if ((data & 0x1) == 0) { /* stop */ io.dma[index].con &= ~0x2; if (data & 0x100) s3c3410x_set_interrupt(INT_DMA0 + index); } break; default: break; } } /* IO Read Routine */ static ARMword s3c3410x_io_read_word(ARMul_State *state, ARMword addr) { ARMword data = -1; /* Interrupt */ if (addr >= INTMOD && addr <= INTPRI7) { s3c3410x_interrupt_read(addr, &data); return data; } /* Timer */ if (addr >= TDAT0 && addr <= TFW4) { s3c3410x_timer_read(addr & 0xf, &data, (addr >> 4) & 0xf); return data; } else if (addr == BTCON) { return (io.btcon & 0xffff); } else if (addr == BTCNT) { return io.btcnt; } /* UART */ if (addr >= ULCON && addr <= UBRDIV) { s3c3410x_uart_read(addr, &data); return data; } /* DMA */ if (addr >= DMASRC0 && addr <= DMACON1 && (addr & 0xfff) <= 0xc) { s3c3410x_dma_read(addr & 0xf, &data, ((addr >> 12) & 0xf) - 3); return data; } switch (addr) { case SYSCFG: data = io.syscfg; break; case SYSCON: data = io.syscon; break; default: DEBUG("UNIMPLEMENTED: %s(addr:0x%08x)\n", __FUNCTION__, addr); break; } return data; } static ARMword s3c3410x_io_read_byte(ARMul_State *state, ARMword addr) { return s3c3410x_io_read_word(state, addr); } static ARMword s3c3410x_io_read_halfword(ARMul_State *state, ARMword addr) { return s3c3410x_io_read_word(state, addr); } /* IO Write Routine */ static void s3c3410x_io_write_word(ARMul_State *state, ARMword addr, ARMword data) { /* Interrupt */ if (addr >= INTMOD && addr <= INTPRI7) { s3c3410x_interrupt_write(state, addr, data); return; } /* Timer */ if (addr >= TDAT0 && addr <= TFW4) { s3c3410x_timer_write(state, addr & 0xf, data, (addr >> 4) & 0xf); return; } else if (addr == BTCON) { io.btcon &= ~0xffff; io.btcon |= (data & ~0x1ff03); if (((data >> 8) & 0xff) == 0xa5) io.btcon &= ~0x10000; else if ((data & 0x1) == 0) io.btcon |= ((data & 0xff00) | 0x10000); if (data & 0x2) io.btcnt = 0; return; } /* UART */ if (addr >= ULCON && addr <= UBRDIV) { s3c3410x_uart_write(state, addr, data); return; } /* DMA */ if (addr >= DMASRC0 && addr <= DMACON1 && (addr & 0xfff) <= 0xc) { s3c3410x_dma_write(state, addr & 0xf, data, ((addr >> 12) & 0xf) - 3); return; } switch (addr) { case SYSCFG: io.syscfg = data; break; case SYSCON: io.syscon = data; break; default: DEBUG("UNIMPLEMENTED: %s(addr:0x%08x, data:0x%x)\n", __FUNCTION__, addr, data); break; } } static void s3c3410x_io_write_byte(ARMul_State *state, ARMword addr, ARMword data) { s3c3410x_io_write_word(state, addr, data); } static void s3c3410x_io_write_halfword(ARMul_State *state, ARMword addr, ARMword data) { s3c3410x_io_write_word(state, addr, data); } static void s3c3410x_io_do_cycle(ARMul_State *state) { s3c3410x_timer_do_cycle(state); s3c3410x_uart_do_cycle(state); s3c3410x_dma_do_cycle(state); s3c3410x_update_int(state); } /* Machine Initialization */ #define MACH_IO_DO_CYCLE_FUNC(f) ((void (*)(void*))(f)) #define MACH_IO_RESET_FUNC(f) ((void (*)(void*))(f)) #define MACH_IO_READ_FUNC(f) ((uint32_t (*)(void*, uint32_t))(f)) #define MACH_IO_WRITE_FUNC(f) ((void (*)(void*, uint32_t, uint32_t))(f)) #define MACH_IO_UPDATE_INT_FUNC(f) ((void (*)(void*))(f)) void s3c3410x_mach_init(ARMul_State *state, machine_config_t *this_mach) { if (state->bigendSig != HIGH) { PRINT("*** ERROR: Only support big endian, maybe you need to use \"-b\" option !!!\n"); skyeye_exit(-1); } ARMul_SelectProcessor(state, ARM_v4_Prop); state->lateabtSig = HIGH; state->Reg[1] = 377; this_mach->mach_io_do_cycle = MACH_IO_DO_CYCLE_FUNC(s3c3410x_io_do_cycle); this_mach->mach_io_reset = MACH_IO_RESET_FUNC(s3c3410x_io_reset); this_mach->mach_io_read_word = MACH_IO_READ_FUNC(s3c3410x_io_read_word); this_mach->mach_io_read_halfword = MACH_IO_READ_FUNC(s3c3410x_io_read_halfword); this_mach->mach_io_read_byte = MACH_IO_READ_FUNC(s3c3410x_io_read_byte); this_mach->mach_io_write_word = MACH_IO_WRITE_FUNC(s3c3410x_io_write_word); this_mach->mach_io_write_halfword = MACH_IO_WRITE_FUNC(s3c3410x_io_write_halfword); this_mach->mach_io_write_byte = MACH_IO_WRITE_FUNC(s3c3410x_io_write_byte); this_mach->mach_update_int = MACH_IO_UPDATE_INT_FUNC(s3c3410x_update_int); this_mach->state = (void*)state; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/at91.h���������������������������������������������������������������0000644�0001750�0000144�00000045100�10541455476�015604� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* one part from clps7110 and another from at91. * should modify it only for at91. * walimis. 2003/7/18 * */ /* * linux/include/asm-arm/arch-clps7110/clps7110.h * * Written 1998,1999 by Werner Almesberger * * This file contains the hardware definitions of the CL-PS7110 chip */ #ifndef _ASM_ARCH_CLPS7110_H #define _ASM_ARCH_CLPS7110_H /* * CL-PS7110 internal registers * * The names will almost certainly clash with something else ... so we'll * probably have to prefix them with CLPS7110_ or something equally ugly later. */ #define PADR 0x0000 /* Port A Data register ---------------------------- */ #define PBDR 0x0001 /* Port B Data register ---------------------------- */ #define PCDR 0x0002 /* Port C Data register ---------------------------- */ #define PDDR 0x0003 /* Port D Data register ---------------------------- */ #define PADDR 0x0040 /* Port A Data Direction register ------------------ */ #define PBDDR 0x0041 /* Port B Data Direction register ------------------ */ #define PCDDR 0x0042 /* Port C Data Direction register ------------------ */ #define PDDDR 0x0043 /* Port D Data Direction register ------------------ */ #define PEDR 0x0080 /* Port E Data register ---------------------------- */ #define PEDDR 0x00c0 /* Port E Data Direction register ------------------ */ #define SYSCON 0x0100 /* System Control register ------------------------- */ #define KBDSCAN 0x0000000f /* Keyboard scan */ #define KBSC_HI 0x0 /* All driven high */ #define KBSC_LO 0x1 /* All driven low */ #define KBSC_X 0x2 /* All high impedance */ #define KBSC_COL0 0x8 /* Column 0 high, others high impedance */ #define KBSC_COL1 0x9 /* Column 1 high, others high impedance */ #define KBSC_COL2 0xa /* Column 2 high, others high impedance */ #define KBSC_COL3 0xb /* Column 3 high, others high impedance */ #define KBSC_COL4 0xc /* Column 4 high, others high impedance */ #define KBSC_COL5 0xd /* Column 5 high, others high impedance */ #define KBSC_COL6 0xe /* Column 6 high, others high impedance */ #define KBSC_COL7 0xf /* Column 7 high, others high impedance */ #define TC1M 0x00000010 /* TC1 mode (0: free-running, 1: prescale) */ #define TC1S 0x00000020 /* TC1 clock source (0: 2 kHz, 1: 512 kHz) */ #define TC2M 0x00000040 /* TC2 mode (0: free-running, 1: prescale) */ #define TC2S 0x00000080 /* TC2 clock source (0: 2 kHz, 1: 512 kHz) */ #define UARTEN 0x00000100 /* Internal UART enable */ #define BZTOG 0x00000200 /* Drive buzzer directly */ #define BZMOD 0x00000400 /* Buzzer drive mode (0: BZTOG, 1: TC1 under-flow) */ #define DBGEN 0x00000800 /* Debug mode */ #define LCDEN 0x00001000 /* LCD enable */ #define CDENTX 0x00002000 /* Codec interface enable Tx */ #define CDENRX 0x00004000 /* Codec interface enable Rx */ #define SIREN 0x00008000 /* HP SIR protocol encoding enable */ #define ADCKSEL 0x00030000 /* Microwire/SPI peripheral clock speed select */ #define ADCKSEL_SHIFT 16 #define ADCS_8 0x0 /* Sample 8 kHz, interface 4 kHz */ #define ADCS_32 0x1 /* 32/16 kHz */ #define ADCS_128 0x2 /* 128/64 kHz */ #define ADCS_256 0x3 /* 256/128 kHz */ #define EXCKEN 0x00040000 /* External expansion clock enable */ #define WAKEDIS 0x00080000 /* Disable switch-on through wake-up */ #define IRTXM 0x00100000 /* IrDA Tx mode (0: 3/16 of rate, 1: 1.63 us) */ #define SYSFLG 0x0140 /* System Status Flags register -------------------- */ #define MCDR 0x00000001 /* Media changed direct read */ #define DCDET 0x00000002 /* Main adapter is powering the system */ #define WUDR 0x00000004 /* Wake-up direct read */ #define WUON 0x00000008 /* Left standby on wake-up */ #define DID 0x000000f0 /* Display ID nibble */ #define DID_SHIFT 4 #define CTS 0x00000100 /* UART CTS */ #define DSR 0x00000200 /* UART DSR */ #define DCD 0x00000400 /* UART DCD */ #define UBUSY 0x00000800 /* UART transmitter busy */ #define NBFLG 0x00001000 /* New battery flag */ #define RSTFLG 0x00002000 /* Reset flag */ #define PFFLG 0x00004000 /* Power fail flag */ #define CLDFLG 0x00008000 /* Cold start flag */ #define RTCDIV 0x003f0000 /* 64 Hz ticks since last RTC increment */ #define RTCDIV_SHIFT 16 #define URXFE 0x00400000 /* UART receiver FIFO empty */ #define UTXFF 0x00800000 /* UART transmit FIFO full */ #define CRXFE 0x01000000 /* Codec Rx FIFO empty */ #define CTXFF 0x02000000 /* Codec Tx FIFO full */ #define SSIBUSY 0x04000000 /* Synchronous serial interface busy */ #define BOOT8BIT 0x80000000 /* Initial bus width (0: 32 bit, 1: 8 bit) */ #define VERID 0xc0000000 /* Version ID */ #define VERID_SHIFT 30 #define MEMCFG1 0x0180 /* Memory Configuration register 1 ----------------- */ #define MEMCFG2 0x01c0 /* Memory Configuration register 2 ----------------- */ #define CS_BW 0x03 /* Bus width */ #define CS_BW_BUS32_E0 0 /* 32 bit if E=0 */ #define CS_BW_BUS16_E0 1 /* 16 bit if E=0 */ #define CS_BW_BUS8_E0 2 /* 8 bit if E=0 */ #define CS_BW_PCMCIA_E0 3 /* PCMCIA if E=0 */ #define CS_BW_BUS8_E1 0 /* 8 bit if E=1 */ #define CS_BW_PCMCIA_E1 1 /* PCMCIA if E=1 */ #define CS_BW_BUS32_E1 2 /* 32 bit if E=1 */ #define CS_BW_BUS16_E1 3 /* 16 bit if E=1 */ #define CS_RAWT 0x0c /* Random Access Wait State */ #define CS_RAWT_SHIFT 2 /* WS = 4-N; speed = 50+50*WS ns */ #define CS_SAWR 0x30 /* Sequential Access Wait State */ #define CS_SAWR_SHIFT 4 /* WS = 3-N; speed[WS] = 40,80,120,150 ns */ #define CS_SQAEN 0x40 /* Sequential Access Enable */ #define CS_CLKEN 0x80 /* Expansion Clock Enable */ #define DRFPR 0x0200 #define INTSR 0x0240 /* Interrupt Status register ----------------------- */ #define EXTFIQ 0x00000001 /* External fast interrupt */ #define BLINT 0x00000002 /* Battery low interrupt */ #define WEINT 0x00000004 /* Watch dog expired interrupt */ #define MCINT 0x00000008 /* Media changed interrupt */ #define CSINT 0x00000010 /* Codec sound interrupt */ #define EINT1 0x00000020 /* External interrupt 1 */ #define EINT2 0x00000040 /* External interrupt 2 */ #define EINT3 0x00000080 /* External interrupt 3 */ #define TC1OI 0x00000100 /* TC1 under-flow interrupt */ #define TC2OI 0x00000200 /* TC2 under-flow interrupt */ #define RTCMI 0x00000400 /* RTC compare match interrupt */ #define TINT 0x00000800 /* 64-Hz tick interrupt */ #define UTXINT 0x00001000 /* Internal UART transmit FIFO half-empty intr. */ #define URXINT 0x00002000 /* Internal UART receive FIFO half-full interrupt */ #define UMSINT 0x00004000 /* Internal UART modem status changed interrupt */ #define SSEOTI 0x00008000 /* Synchronous serial interface end-of-transfer */ #define INTMR 0x0280 /* Interrupt Mask register ------------------------- */ #define LCDCON 0x02c0 /* LCD Control register ---------------------------- */ #define VBUFSIZ 0x00001fff /* Video buffer size (bits/128-1) */ #define LINELEN 0x0007e000 /* Line length (pix/16-1) */ #define LINELEN_SHIFT 13 #define PIXPSC 0x01f80000 /* Pixel prescale (526628/pixels-1) */ #define PIXPSC_SHIFT 19 #define ACPSC 0x3e000000 /* AC prescale */ #define ACPSC_SHIFT 25 #define GSEN 0x40000000 /* Grayscale enable (0: monochrome) */ #define GSMD 0x80000000 /* Grayscale mode (0: 2 bit, 1: 4 bit) */ #define TC1D 0x0300 /* Timer Counter 1 Data register ------------------- */ #define TC_MASK 0x0000ffff #define TC2D 0x0340 /* Timer Counter 2 Data register ------------------- */ #define RTCDR 0x0380 /* Realtime Clock Data register -------------------- */ #define RTCMR 0x03c0 /* Realtime Clock Match register ------------------- */ #define PMPCON 0x0400 #define CODR 0x0440 /* Codec Interface Data register ------------------- */ #define UARTDR 0x0480 /* UART FIFO Data register ------------------------- */ #define RX_DATA 0x000000ff /* Rx data */ #define FRMERR 0x00000100 /* UART framing error */ #define PARERR 0x00000200 /* UART parity error */ #define OVERR 0x00000400 /* UART overrun error */ #define UBRLCR 0x04c0 /* UART Bit Rate and Line Control register --------- */ #define BRDIV 0x00000fff /* Bit rate divisor */ #define BR_115200 1 #define BR_57600 3 #define BR_38400 5 #define BR_19200 11 #define BR_9600 23 #define BR_2400 95 #define BR_1200 191 #define BREAK 0x00001000 /* Set Tx high */ #define PRTEN 0x00002000 /* Parity enable */ #define EVENPRT 0x00004000 /* Even parity */ #define XSTOP 0x00008000 /* Extra stop bit */ #define FIFOEN 0x00010000 /* Enable FIFO */ #define WRDLEN 0x00030000 /* Word length */ #define WRDLEN_SHIFT 17 #define WL_5 0x0 /* 5 bits */ #define WL_6 0x1 /* 6 bits */ #define WL_7 0x2 /* 7 bits */ #define WL_8 0x3 /* 8 bits */ #define SYNCIO 0x0500 #define TXFRMEN 0x00004000 /* Initiate data transfer */ #define SMCKEN 0x00002000 /* Enable sample clock on SMPLCK */ #define FRLEN 0x00001f00 /* Frame length */ #define FRLEN_SHIFT 8 #define ADCCFB 0x000000ff /* ADC Configuration byte */ #define ADCRSW 0x0000ffff /* ADC result word */ #define PALLSW 0x0540 /* Least-significant 32-bit word of LCD Palette reg. */ #define PALMSW 0x0580 /* Most-significant 32-bit word of LCD Palette reg. */ #define STFCLR 0x05c0 /* Write to clear all start up reason flags -------- */ #define BLEOI 0x0600 /* Write to clear Battery Low interrupt ------------ */ #define MCEOI 0x0640 /* Write to clear Media Changed interrupt ---------- */ #define TEOI 0x0680 /* Write to clear Tick and Watchdog interrupt ------ */ #define TC1EOI 0x06c0 /* Write to clear TC1 interrupt -------------------- */ #define TC2EOI 0x0700 /* Write to clear TC2 interrupt -------------------- */ #define RTCEOI 0x0740 /* Write to clear RTC Match interrupt -------------- */ #define UMSEOI 0x0780 /* Write to clear UART Modem Status Changed interrupt */ #define COEOI 0x07c0 /* Write to clear Codec Sound interrupt ------------ */ #define HALT 0x0800 /* Write to enter idle state ----------------------- */ #define STDBY 0x0840 /* Write to standby state -------------------------- */ /* * CL-PS7110 PCMCIA memory constants * * Need to #define PCMCIA_BASE before using these macros. */ #define PCMCIA_ATTR8(a) (PCMCIA_BASE+0x00000000+(a)) #define PCMCIA_MEM(a) (PCMCIA_BASE+0x04000000+(a)) #define PCMCIA_IO8(a) (PCMCIA_BASE+0x08000000+(a)) #define PCMCIA_IO16(a) (PCMCIA_BASE+0x0c000000+((a) & ~3)+(((a) & 2) << 24)) /* below from linux/include/asm-arm/arch-atmel/hardware.h * skyeye_mach_at91.c should use it. * walimis. 2003/7/18 * */ /* * linux/include/asm-arm/arch-atmel/hardware.h * for Atmel AT91 series * 2001 Erwin Authried */ /* 0=TC0, 1=TC1, 2=TC2 */ #define KERNEL_TIMER 1 #ifdef CONFIG_CPU_AT91X40 /* ******************* AT91x40xxx ******************** */ #define ARM_CLK (32768000) #define AT91_USART_CNT 2 #define AT91_USART0_BASE (0xfffd0000) #define AT91_USART1_BASE (0xfffcc000) #define AT91_TC_BASE (0xfffe0000) #define AIC_BASE (0xfffff000) #define AT91_PIOA_BASE (0xffff0000) #define AT91_SF_CIDR (0xfff00000) #define HARD_RESET_NOW() #define HW_AT91_TIMER_INIT(timer) /* no PMC */ /* use TC0 as hardware timer to create high resolution timestamps for debugging. * Timer 0 must be set up as a free running counter, e.g. in the bootloader */ #define HW_COUNTER (((struct at91_timers *)AT91_TC_BASE)->chans[0].ch.cv) /* enable US0,US1 */ #define HW_AT91_USART_INIT ((volatile struct pio_regs *)AT91_PIOA_BASE)->pdr = \ PIOA_RXD0|PIOA_TXD0|PIOA_RXD1|PIOA_TXD1; /* PIOA bit allocation */ #define PIOA_TCLK0 (1<<0) #define PIOA_TI0A0 (1<<1) #define PIOA_TI0B0 (1<<2) #define PIOA_TCLK1 (1<<3) #define PIOA_TIOA1 (1<<4) #define PIOA_TIOB1 (1<<5) #define PIOA_TCLK2 (1<<6) #define PIOA_TIOA2 (1<<7) #define PIOA_TIOB2 (1<<8) #define PIOA_IRQ0 (1<<9) #define PIOA_IRQ1 (1<<10) #define PIOA_IRQ2 (1<<11) #define PIOA_FIQ (1<<12) #define PIOA_SCK0 (1<<13) #define PIOA_TXD0 (1<<14) #define PIOA_RXD0 (1<<15) #define PIOA_SCK1 (1<<20) #define PIOA_TXD1 (1<<21) #define PIOA_RXD1 (1<<22) #define PIOA_MCK0 (1<<25) #define PIOA_NCS2 (1<<26) #define PIOA_NCS3 (1<<27) #define PIOA_A20_CS7 (1<<28) #define PIOA_A21_CS6 (1<<29) #define PIOA_A22_CS5 (1<<30) #define PIOA_A23_CS4 (1<<31) #elif CONFIG_CPU_AT91X63 /* ******************* AT91x63xxx ******************** */ #define ARM_CLK (25000000) #define AT91_USART_CNT 2 #define AT91_USART0_BASE (0xfffc0000) #define AT91_USART1_BASE (0xfffc4000) #define AT91_TC_BASE (0xfffd0000) #define AIC_BASE (0xfffff000) #define AT91_PIOA_BASE (0xfffec000) #define AT91_PIOB_BASE (0xffff0000) #define AT91_PMC_BASE (0xffff4000) #define HARD_RESET_NOW() /* enable US0,US1 */ #define HW_AT91_USART_INIT ((volatile struct pmc_regs *)AT91_PMC_BASE)->pcer = \ (1<<2) | (1<<3) | (1<<13); \ ((volatile struct pio_regs *)AT91_PIOA_BASE)->pdr = \ PIOA_RXD0|PIOA_TXD0|PIOA_RXD1|PIOA_TXD1; #define HW_AT91_TIMER_INIT(timer) ((volatile struct pmc_regs *)AT91_PMC_BASE)->pcer = \ 1<<(timer+6); /* PIOA bit allocation */ #define PIOA_TCLK3 (1<<0) #define PIOA_TI0A3 (1<<1) #define PIOA_TI0B3 (1<<2) #define PIOA_TCLK4 (1<<3) #define PIOA_TI0A4 (1<<4) #define PIOA_TI0B4 (1<<5) #define PIOA_TCLK5 (1<<6) #define PIOA_TI0A5 (1<<7) #define PIOA_TI0B5 (1<<8) #define PIOA_IRQ0 (1<<9) #define PIOA_IRQ1 (1<<10) #define PIOA_IRQ2 (1<<11) #define PIOA_IRQ3 (1<<12) #define PIOA_FIQ (1<<13) #define PIOA_SCK0 (1<<14) #define PIOA_TXD0 (1<<15) #define PIOA_RXD0 (1<<16) #define PIOA_SCK1 (1<<17) #define PIOA_TXD1 (1<<18) #define PIOA_RXD1 (1<<19) #define PIOA_SCK2 (1<<20) #define PIOA_TXD2 (1<<21) #define PIOA_RXD2 (1<<22) #define PIOA_SPCK (1<<23) #define PIOA_MISO (1<<24) #define PIOA_MOSI (1<<25) #define PIOA_NPCS0 (1<<26) #define PIOA_NPCS1 (1<<27) #define PIOA_NPCS2 (1<<28) #define PIOA_NPCS3 (1<<29) /* PIOB bit allocation */ #define PIOB_MPI_NOE (1<<0) #define PIOB_MPI_NLB (1<<1) #define PIOB_MPI_NUB (1<<2) #define PIOB_MCK0 (1<<17) #define PIOB_BMS (1<<18) #define PIOB_TCLK0 (1<<19) #define PIOB_TIOA0 (1<<20) #define PIOB_TIOB0 (1<<21) #define PIOB_TCLK1 (1<<22) #define PIOB_TIOA1 (1<<23) #define PIOB_TIOB1 (1<<24) #define PIOB_TCLK2 (1<<25) #define PIOB_TIOA2 (1<<26) #define PIOB_TIOB2 (1<<27) #else // #error "Configuration error: No CPU defined" #endif /* ******************* COMMON PART ******************** */ #define AIC_SMR(i) (AIC_BASE+i*4) #define AIC_IVR (AIC_BASE+0x100) #define AIC_FVR (AIC_BASE+0x104) #define AIC_ISR (AIC_BASE+0x108) #define AIC_IPR (AIC_BASE+0x10C) #define AIC_IMR (AIC_BASE+0x110) #define AIC_CISR (AIC_BASE+0x114) #define AIC_IECR (AIC_BASE+0x120) #define AIC_IDCR (AIC_BASE+0x124) #define AIC_ICCR (AIC_BASE+0x128) #define AIC_ISCR (AIC_BASE+0x12C) #define AIC_EOICR (AIC_BASE+0x130) #ifndef __ASSEMBLER__ struct at91_timer_channel { unsigned int ccr; // channel control register (WO) unsigned int cmr; // channel mode register (RW) unsigned int reserved[2]; unsigned int cv; // counter value (RW) unsigned int ra; // register A (RW) unsigned int rb; // register B (RW) unsigned int rc; // register C (RW) unsigned int sr; // status register (RO) unsigned int ier; // interrupt enable register (WO) unsigned int idr; // interrupt disable register (WO) unsigned int imr; // interrupt mask register (RO) }; struct at91_timers { struct { struct at91_timer_channel ch; unsigned char padding[0x40 - sizeof (struct at91_timer_channel)]; } chans[3]; unsigned int bcr; // block control register (WO) unsigned int bmr; // block mode register (RW) }; #endif #define IRQ_FIQ 0 #define IRQ_SWI 1 #define IRQ_USART0 2 #define IRQ_USART1 3 #define IRQ_TC0 4 #define IRQ_TC1 5 #define IRQ_TC2 6 #define IRQ_WD 7 #define IRQ_PIOA 8 #define IRQ_EXT0 16 #define IRQ_EXT1 17 #define IRQ_EXT2 18 /* TC control register */ #define TC_SYNC (1) /* TC mode register */ #define TC2XC2S(x) (x & 0x3) #define TC1XC1S(x) (x<<2 & 0xc) #define TC0XC0S(x) (x<<4 & 0x30) #define TCNXCNS(timer,v) ((v) << (timer<<1)) /* TC channel control */ #define TC_CLKEN (1) #define TC_CLKDIS (1<<1) #define TC_SWTRG (1<<2) /* TC interrupts enable/disable/mask and status registers */ #define TC_MTIOB (1<<18) #define TC_MTIOA (1<<17) #define TC_CLKSTA (1<<16) #define TC_ETRGS (1<<7) #define TC_LDRBS (1<<6) #define TC_LDRAS (1<<5) #define TC_CPCS (1<<4) #define TC_CPBS (1<<3) #define TC_CPAS (1<<2) #define TC_LOVRS (1<<1) #define TC_COVFS (1) /* * USART registers */ /* US control register */ #define US_SENDA (1<<12) #define US_STTO (1<<11) #define US_STPBRK (1<<10) #define US_STTBRK (1<<9) #define US_RSTSTA (1<<8) #define US_TXDIS (1<<7) #define US_TXEN (1<<6) #define US_RXDIS (1<<5) #define US_RXEN (1<<4) #define US_RSTTX (1<<3) #define US_RSTRX (1<<2) /* US mode register */ #define US_CLK0 (1<<18) #define US_MODE9 (1<<17) #define US_CHMODE(x)(x<<14 & 0xc000) #define US_NBSTOP(x)(x<<12 & 0x3000) #define US_PAR(x) (x<<9 & 0xe00) #define US_SYNC (1<<8) #define US_CHRL(x) (x<<6 & 0xc0) #define US_USCLKS(x)(x<<4 & 0x30) /* US interrupts enable/disable/mask and status register */ #define US_DMSI (1<<10) #define US_TXEMPTY (1<<9) #define US_TIMEOUT (1<<8) #define US_PARE (1<<7) #define US_FRAME (1<<6) #define US_OVRE (1<<5) #define US_ENDTX (1<<4) #define US_ENDRX (1<<3) #define US_RXBRK (1<<2) #define US_TXRDY (1<<1) #define US_RXRDY (1) #define US_ALL_INTS (US_DMSI|US_TXEMPTY|US_TIMEOUT|US_PARE|US_FRAME|US_OVRE|US_ENDTX|US_ENDRX|US_RXBRK|US_TXRDY|US_RXRDY) #ifndef __ASSEMBLER__ struct atmel_usart_regs { unsigned int cr; // control unsigned int mr; // mode unsigned int ier; // interrupt enable unsigned int idr; // interrupt disable unsigned int imr; // interrupt mask unsigned int csr; // channel status unsigned int rhr; // receive holding unsigned int thr; // tramsmit holding unsigned int brgr; // baud rate generator unsigned int rtor; // rx time-out unsigned int ttgr; // tx time-guard unsigned int res1; unsigned int rpr; // rx pointer unsigned int rcr; // rx counter unsigned int tpr; // tx pointer unsigned int tcr; // tx counter }; #endif #define PIO(i) (1<<i) #ifndef __ASSEMBLER__ struct pio_regs { unsigned int per; unsigned int pdr; unsigned int psr; unsigned int res1; unsigned int oer; unsigned int odr; unsigned int osr; unsigned int res2; unsigned int ifer; unsigned int ifdr; unsigned int ifsr; unsigned int res3; unsigned int sodr; unsigned int codr; unsigned int odsr; unsigned int pdsr; unsigned int ier; unsigned int idr; unsigned int imr; unsigned int isr; }; #endif #ifndef __ASSEMBLER__ struct pmc_regs { unsigned int scer; unsigned int scdr; unsigned int scsr; unsigned int reserved; unsigned int pcer; unsigned int pcdr; unsigned int pcsr; }; #endif #endif ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_pxa250.c�������������������������������������������������0000644�0001750�0000144�00000035103�10555732132�020413� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <sys/time.h> #include <sys/types.h> #include <unistd.h> #include "armdefs.h" #include "pxa.h" /*ywc 2005-03-30*/ #include "skyeye_flash.h" #define F_CORE (100 * 1024 * 1024) //core frequence #define F_RTC 32768 //RTC #define F_OS 3686400 //OS timer #define RT_SCALE (F_CORE / F_RTC) / 50 #define OS_SCALE (F_CORE / F_OS / 10) / 50 #define FF_SCALE 200 //FF UART /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" //ywc,2004-11-30,declare a external array which stores touchscreen event information extern unsigned int Pen_buffer[8]; // defined in skyeye_lcd.c //ywc,2004-11-30,declare a external array which stores touchscreen event information,end //chy: lubbock, cerf, idp are different board // I can add a union to cover the difference in the future //chy: refer to linux/include/asm-arm/arch-pxa/pxa-regs.h //chy 2005-09-19, the define of pxa27x_io_t is in pxa.h static pxa250_io_t pxa250_io; static void refresh_irq (ARMul_State *); static void pxa250_io_reset () { memset (&pxa250_io, 0, sizeof (pxa250_io)); //chy 2003-08-25 pxa250_io.cccr = 0x121; // 1 0010 0001 pxa250_io.cken = 0x17def; pxa250_io.ts_int = 1 << 15; pxa250_io.ts_addr_begin = 0x40000300; pxa250_io.ts_addr_end = 0x4000031f; //ywc,2004-11-30,evaluate io of LCD and Touchscreen,end }; void pxa250_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { return; } void pxa250_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { return; } pxa_set_intr (u32 interrupt) { pxa250_io.icpr |= (1 << interrupt); } static int pxa_pending_intr (u32 interrupt) { return ((pxa250_io.icpr & (1 << interrupt))); } static void pxa_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; pxa250_io.icip = (pxa250_io.icmr & pxa250_io.icpr) & ~pxa250_io.iclr; pxa250_io.icfp = (pxa250_io.icmr & pxa250_io.icpr) & pxa250_io.iclr; state->NirqSig = pxa250_io.icip ? LOW : HIGH; state->NfiqSig = pxa250_io.icfp ? LOW : HIGH; } static void pxa250_update_int (ARMul_State * state) { pxa250_io.icip = (pxa250_io.icmr & pxa250_io.icpr) & ~pxa250_io.iclr; pxa250_io.icfp = (pxa250_io.icmr & pxa250_io.icpr) & pxa250_io.iclr; state->NirqSig = pxa250_io.icip ? LOW : HIGH; state->NfiqSig = pxa250_io.icfp ? LOW : HIGH; } static void pxa250_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { pxa_ioregnum_t ioregaddr = addr; //printf("SKYEYE:pxa250_io_write_word: io addr 0x%x, RCNR 0x%x\n",ioregaddr,RCNR); switch (ioregaddr) { /*RTC*/ case RCNR: pxa250_io.rcnr = data; break; case RTAR: pxa250_io.rtar = data; break; case RTSR: pxa250_io.rtsr |= (data & 0xc); pxa250_io.rtsr &= ~(data & 0x3); break; case RTTR: pxa250_io.rttr = data & 0x3ffffff; break; /*OS timer */ case OSCR: pxa250_io.oscr = data; break; case OSMR0: pxa250_io.osmr0 = data; break; case OSMR1: pxa250_io.osmr1 = data; break; case OSMR2: pxa250_io.osmr2 = data; break; case OSMR3: pxa250_io.osmr3 = data; break; case OWER: pxa250_io.ower |= data & 0x1; break; case OSSR: /* When the status register is updated, the results are seen immediately in the icpr */ pxa250_io.ossr &= ~(data & 0xf); pxa250_io.icpr &= ~(0xf << OS_IRQ_SHF); pxa250_io.icpr |= (pxa250_io.ossr << OS_IRQ_SHF); break; case OIER: pxa250_io.oier = data & 0xf; break; /*interrupt control */ //ywc,2004-11-30,for touchscreen use ICPR case ICPR: /*read only - see 4.2.2.5 Intel PXA255 Processor Developer's Manual */ break; case ICMR: pxa250_io.icmr = data; break; case ICLR: pxa250_io.iclr = data; break; //ffuart contril case FFTHR: { /*static tx_cnt=0; */ unsigned char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); /*chy 2004-07-21 from luzhetao: after write char, should set some value */ pxa250_io.ffiir &= ~0x2; pxa250_io.ffiir |= 0x1; pxa250_io.fflsr &= ~0x60; //tx_cnt++; //pxa250_io.ffier|=0x2; /* if(tx_cnt>63){ tx_cnt=0; pxa250_io.ffiir|=0x2; pxa250_io.fflsr|=0x60; refresh_irq(state); } */ //printf("SKYEYE: write FFTHR %x, iir %x,lsr %x, ier %x\n",data, pxa250_io.ffiir,pxa250_io.fflsr,pxa250_io.ffier); } break; case FFIER: pxa250_io.ffier = data & 0xff; break; case FFFCR: //write only pxa250_io.fffcr = data & 0xc7; //pxa250_io.ffiir = data & 0xc7 ; //if(pxa250_io.fffcr & 2 //printf("SKYEYE: write FFFCR %x, but is ffiir %x\n",pxa250_io.fffcr,pxa250_io.ffiir); break; case FFLCR: pxa250_io.fflcr = data & 0xff; break; //core clock case FFMCR: pxa250_io.ffmcr = data & 0x1f; break; //core clock case CCCR: pxa250_io.cccr = data & 0x3ff; break; case CKEN: pxa250_io.cken = data & 0x17def; break; case OSCC: pxa250_io.oscc = data & 0x3; break; //ywc,2004-11-30,add for pxa's LCD simulation #if 0 case LCCR0: tmp = pxa250_io.lccr0; pxa250_io.lccr0 = data; if ((!(tmp & LCCR0_ENB)) && (pxa250_io.lccr0 & LCCR0_ENB)) { if (once) break; once++; /* printf("\nFDADR0=%x,FDADR1=%x",pxa250_io.fdadr0,pxa250_io.fdadr1); printf("\n"); pxa250_io.lcd_addr_begin = pxa250_io.fdadr0 + 16*(2+2); printf("\nlcd_addr_begin=%x",pxa250_io.lcd_addr_begin); printf("\n"); */ pxa250_update_lcd (state); } break; case LCCR1: pxa250_io.lccr1 = data; break; case LCCR2: pxa250_io.lccr2 = data; break; case LCCR3: pxa250_io.lccr3 = data; break; case FDADR0: pxa250_io.fdadr0 = data; //printf("\nFDADR0=%x",pxa250_io.fdadr0); //printf("\n"); /* mbp = bank_ptr(pxa250_io.fdadr0); if(!mbp){ fprintf(stderr, "No bank at address 0x%x", pxa250_io.fdadr0); return; } fdadr0ADDRESS=(u32 *) &state->mem.rom[mbp - skyeye_config.mem.mem_banks][(pxa250_io.fdadr0 - mbp->addr)]; printf("\n %p",fdadr0ADDRESS); */ // printf("\n 0: %x",*((u32 *)fdadr0ADDRESS)); // printf("\n 1: %x",*((u32 *)fdadr0ADDRESS+1)); // printf("\n 2: %x",*((u32 *)fdadr0ADDRESS+2)); // printf("\n 3: %x",*((u32 *)fdadr0ADDRESS+3)); //printf("\n"); break; case FDADR1: pxa250_io.fdadr1 = data; //printf("\nFDADR1=%x",pxa250_io.fdadr1); //printf("\n"); break; case FSADR0: pxa250_io.fsadr0 = data; //printf("\nFSADR0=%x",pxa250_io.fsadr0); //printf("\n"); break; case FSADR1: pxa250_io.fsadr1 = data; //printf("\nFSADR1=%x",pxa250_io.fsadr1); //printf("\n"); break; #endif //ywc,2004-11-30,add for pxa's LCD simulation,end #if 0 case FFIIR: //read only case FFMSR: //read only no use case FFSPR: // no use case FFISR: // no use #endif default: //chy 2003-09-03 if debug, uncommit it //log_msg("SKYEYE: pxa250_io_write_word: unknown addr 0x%x, reg15 0x%x \n", addr,state->Reg[15]); ; }; }; ARMword pxa250_io_read_byte (ARMul_State * state, ARMword addr) { return 0; } ARMword pxa250_io_read_halfword (ARMul_State * state, ARMword addr) { return 0; } ARMword pxa250_io_read_word (ARMul_State * state, ARMword addr) { u32 data; pxa_ioregnum_t ioregaddr = addr; //ywc,2004-11-30,add for pxa's Touchscreen simulation u32 ts_addr; //ywc,2004-11-30,add for pxa's Touchscreen simulation,end //ywc 2004-11-30 read the touch srceen data buffer,return to the ts device driver ts_addr = addr & ~3; // 1 word==4 byte if (ts_addr >= pxa250_io.ts_addr_begin && ts_addr <= pxa250_io.ts_addr_end) { data = pxa250_io. ts_buffer[(ts_addr - pxa250_io.ts_addr_begin) / 4]; return data; } //ywc 2004-11-30 read the touch srceen data buffer,return to the ts device driver,end switch (addr) { /*RTC*/ case RCNR: data = pxa250_io.rcnr; break; case RTAR: data = pxa250_io.rtar; break; case RTSR: data = pxa250_io.rtsr; break; case RTTR: data = pxa250_io.rttr; break; /*OS timer */ case OSCR: data = pxa250_io.oscr; break; case OSMR0: data = pxa250_io.osmr0; break; case OSMR1: data = pxa250_io.osmr1; break; case OSMR2: data = pxa250_io.osmr2; break; case OSMR3: data = pxa250_io.osmr3; break; case OWER: data = pxa250_io.ower; break; case OSSR: data = pxa250_io.ossr; break; case OIER: data = pxa250_io.oier; break; /*interrupt controler */ case ICPR: data = pxa250_io.icpr; break; case ICIP: data = (pxa250_io.icmr & pxa250_io.icpr) & ~pxa250_io.iclr; break; case ICFP: data = (pxa250_io.icmr & pxa250_io.icpr) & pxa250_io.iclr; break; case ICMR: data = pxa250_io.icmr; break; case ICLR: data = pxa250_io.iclr; break; /* ffuart control */ case FFRBR: //chy: 2003-08-24 have some question, maybe skyeye will be locked here ???? { //unsigned char c; //read(skyeye_config.uart.fd_in, &c, 1); //data = c; data = pxa250_io.ffrbr & 0xff; pxa250_io.icpr &= ~FFUART_IRQ; pxa250_io.icip &= ~FFUART_IRQ; pxa250_io.ffiir &= ~0x4; /*chy 2004-07-21 from lzt, afte read char, should set this bit */ pxa250_io.ffiir |= 0x1; //printf("SKYEYE: read FFRBR, but set ffiir and ~04, now %x\n",pxa250_io.ffiir); pxa250_io.fflsr &= ~0x1; }; break; case FFIER: data = pxa250_io.ffier; break; case FFIIR: //read only data = pxa250_io.ffiir & 0xcf; pxa250_io.icpr &= ~FFUART_IRQ; pxa250_io.icip &= ~FFUART_IRQ; //printf("SKYEYE: read FFIIR %x\n",data); break; case FFLCR: data = pxa250_io.fflcr; break; case FFMCR: data = pxa250_io.ffmcr; break; case FFLSR: //read only //chy 2003-08-24 NOTICE! //fixed by ksh 2004-05-09,for FFUART can input char,I am not sure? //pxa250_io.fflsr=1<<5; // LSR's TDRQ =1 , then the cpu can write char again pxa250_io.fflsr |= 0x60; // chy 2003-09-02 for LSR_TEMT|LSR_THRE 0x40|0x20 data = pxa250_io.fflsr & 0xff; break; // core clock case CCCR: data = pxa250_io.cccr; break; case CKEN: data = pxa250_io.cken; break; case OSCC: data = pxa250_io.oscc; break; //ywc,2004-11-30,add for pxa's LCD simulation #if 0 case LCCR0: data = pxa250_io.lccr0; break; case LCCR1: data = pxa250_io.lccr1; break; case LCCR2: data = pxa250_io.lccr2; break; case LCCR3: data = pxa250_io.lccr3; break; case FDADR0: data = pxa250_io.fdadr0; break; case FDADR1: data = pxa250_io.fdadr1; break; case FSADR0: data = pxa250_io.fsadr0; break; case FSADR1: data = pxa250_io.fsadr1; break; #endif //ywc,2004-11-30,add for pxa's LCD simulation,end #if 0 case FFFCR: //write only case FFMSR: //read only no use case FFSPR: // no use case FFISR: // no use #endif default: data = 0; //chy 2003-09-03 if debug, uncommit it //log_msg("SKYEYE: pxa250_io_read_word: unknown addr 0x%x, reg15 0x%x \n", addr,state->Reg[15]); }; return data; }; static void pxa250_io_do_cycle (ARMul_State * state) { /*RTC*/ if (++pxa250_io.rt_scale >= RT_SCALE) { pxa250_io.rt_scale = 0; if (pxa250_io.rt_count++ == (pxa250_io.rttr & 0xffff)) { pxa250_io.rt_count = 0; if (pxa250_io.rcnr++ == pxa250_io.rtar) { if (pxa250_io.rtsr & 0x4) { pxa250_io.rtsr |= 0x1; }; } if (pxa250_io.rtsr & 0x8) { pxa250_io.rtsr |= 0x2; } } if ((pxa250_io.rtsr & 0x1) && (pxa250_io.rtsr & 0x4)) pxa250_io.icpr |= RTC_ALARM_IRQ; if ((pxa250_io.rtsr & 0x2) && (pxa250_io.rtsr & 0x8)) pxa250_io.icpr |= RTC_HZ_IRQ; } /*OS timer */ if (++pxa250_io.os_scale >= OS_SCALE) { u32 mask = 0; u32 count; pxa250_io.os_scale = 0; count = pxa250_io.oscr++; if (count == pxa250_io.osmr0) mask = 1; if (count == pxa250_io.osmr1) mask |= 0x2; if (count == pxa250_io.osmr2) mask |= 0x4; if (count == pxa250_io.osmr3) { mask |= 0x8; if (pxa250_io.ower & 1) { state->NresetSig = LOW; printf ("************SKYEYE: WatchDog reset!!!!!!!**************\n"); } } pxa250_io.ossr |= mask; mask = pxa250_io.oier & pxa250_io.ossr; pxa250_io.icpr |= (mask << OS_IRQ_SHF); } /*FF UART */ //pxa250_io.utsr0 = 1; /*always TFS, no others*/ //pxa250_io.utsr1 = 0x4; /*TNF*/ if (++pxa250_io.ff_scale >= FF_SCALE) { pxa250_io.ff_scale = 0; if (!(FFUART_IRQ & pxa250_io.icpr)) { int int_enable = pxa250_io.ffmcr & 0x18; // UART interrupt enable /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char c; tv.tv_sec = 0; tv.tv_usec = 0; //pxa250_io.utsr1 |= 0x2; //RNE //pxa250_io.utsr0 |= 0x4; //Rx idle //added by ksh,2004-4-25,get uart data and set the interrupt if(skyeye_uart_read(-1, &c, 1, &tv, NULL) > 0) { pxa250_io.ffrbr = (int) c; pxa250_io.ffiir |= 0x4; //Rx idle //printf("SKYEYE: io_do_cycle set ffiir or 04, now %x\n",pxa250_io.ffiir); pxa250_io.fflsr |= 0x01; //Data ready } if ((pxa250_io.ffier & 0x1) && (pxa250_io.ffiir & 0x4)) { if (int_enable) pxa250_io.icpr |= FFUART_IRQ; pxa250_io.ffiir &= ~0x1; } /*chy 2004-07-21 from luzhetao: produce a IRQ and ox2 should clean by OS driver */ if (pxa250_io.ffier & 0x2) { if (int_enable) pxa250_io.icpr |= FFUART_IRQ; pxa250_io.ffiir |= 0x2; pxa250_io.ffiir &= ~0x1; pxa250_io.fflsr |= 0x60; } } //ywc,2004-11-30,check and get the mouse event #ifndef NO_LCD if (!(pxa250_io.icpr & pxa250_io.ts_int)) { //if now has no ts interrupt,then query if (Pen_buffer[6] == 1) { //should trigger a interrupt *(pxa250_io.ts_buffer + 0) = Pen_buffer[0]; *(pxa250_io.ts_buffer + 1) = Pen_buffer[1]; *(pxa250_io.ts_buffer + 4) = Pen_buffer[4]; *(pxa250_io.ts_buffer + 6) = Pen_buffer[6]; //set EINT2 bit to trigger a interrupt,ts driver will clear it pxa250_io.icpr |= pxa250_io.ts_int; Pen_buffer[6] = 0; } } #endif //ywc,2004-11-30,check and get the mouse event,end } pxa250_update_int (state); /*reset interrupt pin status */ //refresh_irq (state); }; void pxa250_mach_init (ARMul_State * state, machine_config_t * mc) { //chy 2003-08-19, setprocessor ARMul_SelectProcessor (state, ARM_XScale_Prop | ARM_v5_Prop | ARM_v5e_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = LOW; state->Reg[1] = 89; /*lubbock machine id. */ pxa250_io_reset (); /*added by ksh for energy estimation in 2004-11-26 */ state->energy.cccr = pxa250_io.cccr; mc->mach_io_do_cycle = pxa250_io_do_cycle; mc->mach_io_reset = pxa250_io_reset; mc->mach_io_read_byte = pxa250_io_read_byte; mc->mach_io_write_byte = pxa250_io_write_byte; mc->mach_io_read_halfword = pxa250_io_read_halfword; mc->mach_io_write_halfword = pxa250_io_write_halfword; mc->mach_io_read_word = pxa250_io_read_word; mc->mach_io_write_word = pxa250_io_write_word; mc->mach_set_intr = pxa_set_intr; mc->mach_pending_intr = pxa_pending_intr; mc->mach_update_intr = pxa_update_intr; mc->state = (void *) state; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/ps7500.h�������������������������������������������������������������0000644�0001750�0000144�00000011211�10541455476�015760� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������ #define IOMD_CONTROL (0x000) #define IOMD_KARTTX (0x004) #define IOMD_KARTRX (0x004) #define IOMD_KCTRL (0x008) #define IOMD_IOLINES (0x00C) #define IOMD_IRQSTATA (0x010) #define IOMD_IRQREQA (0x014) #define IOMD_IRQCLRA (0x014) #define IOMD_IRQMASKA (0x018) #define IOMD_SUSMODE (0x01C) #define IOMD_IRQSTATB (0x020) #define IOMD_IRQREQB (0x024) #define IOMD_IRQMASKB (0x028) #define IOMD_FIQSTAT (0x030) #define IOMD_FIQREQ (0x034) #define IOMD_FIQMASK (0x038) #define IOMD_CLKCTL (0x03C) #define IOMD_T0CNTL (0x040) #define IOMD_T0LTCHL (0x040) #define IOMD_T0CNTH (0x044) #define IOMD_T0LTCHH (0x044) #define IOMD_T0GO (0x048) #define IOMD_T0LATCH (0x04c) #define IOMD_T1CNTL (0x050) #define IOMD_T1LTCHL (0x050) #define IOMD_T1CNTH (0x054) #define IOMD_T1LTCHH (0x054) #define IOMD_T1GO (0x058) #define IOMD_T1LATCH (0x05c) #define IOMD_IRQSTATC (0x060) #define IOMD_IRQREQC (0x064) #define IOMD_IRQMASKC (0x068) #define IOMD_VIDMUX (0x06c) #define IOMD_IRQSTATD (0x070) #define IOMD_IRQREQD (0x074) #define IOMD_IRQMASKD (0x078) #define IOMD_ROMCR0 (0x080) #define IOMD_ROMCR1 (0x084) #define IOMD_REFCR (0x08C) #define IOMD_FSIZE (0x090) #define IOMD_ID0 (0x094) #define IOMD_ID1 (0x098) #define IOMD_VERSION (0x09C) #define IOMD_MOUSEX (0x0A0) #define IOMD_MOUSEY (0x0A4) #define IOMD_MSEDAT (0x0A8) #define IOMD_MSECTL (0x0Ac) #define IOMD_DMATCR (0x0C0) #define IOMD_IOTCR (0x0C4) #define IOMD_ECTCR (0x0C8) #define IOMD_DMAEXT (0x0CC) #define IOMD_ASTCR (0x0CC) #define IOMD_DRAMCR (0x0D0) #define IOMD_SELFREF (0x0D4) #define IOMD_ATODICR (0x0E0) #define IOMD_ATODSR (0x0E4) #define IOMD_ATODCC (0x0E8) #define IOMD_ATODCNT1 (0x0EC) #define IOMD_ATODCNT2 (0x0F0) #define IOMD_ATODCNT3 (0x0F4) #define IOMD_ATODCNT4 (0x0F8) #define DMA_EXT_IO0 1 #define DMA_EXT_IO1 2 #define DMA_EXT_IO2 4 #define DMA_EXT_IO3 8 #define IOMD_IO0CURA (0x100) #define IOMD_IO0ENDA (0x104) #define IOMD_IO0CURB (0x108) #define IOMD_IO0ENDB (0x10C) #define IOMD_IO0CR (0x110) #define IOMD_IO0ST (0x114) #define IOMD_IO1CURA (0x120) #define IOMD_IO1ENDA (0x124) #define IOMD_IO1CURB (0x128) #define IOMD_IO1ENDB (0x12C) #define IOMD_IO1CR (0x130) #define IOMD_IO1ST (0x134) #define IOMD_IO2CURA (0x140) #define IOMD_IO2ENDA (0x144) #define IOMD_IO2CURB (0x148) #define IOMD_IO2ENDB (0x14C) #define IOMD_IO2CR (0x150) #define IOMD_IO2ST (0x154) #define IOMD_IO3CURA (0x160) #define IOMD_IO3ENDA (0x164) #define IOMD_IO3CURB (0x168) #define IOMD_IO3ENDB (0x16C) #define IOMD_IO3CR (0x170) #define IOMD_IO3ST (0x174) #define IOMD_SD0CURA (0x180) #define IOMD_SD0ENDA (0x184) #define IOMD_SD0CURB (0x188) #define IOMD_SD0ENDB (0x18C) #define IOMD_SD0CR (0x190) #define IOMD_SD0ST (0x194) #define IOMD_SD1CURA (0x1A0) #define IOMD_SD1ENDA (0x1A4) #define IOMD_SD1CURB (0x1A8) #define IOMD_SD1ENDB (0x1AC) #define IOMD_SD1CR (0x1B0) #define IOMD_SD1ST (0x1B4) #define IOMD_CURSCUR (0x1C0) #define IOMD_CURSINIT (0x1C4) #define IOMD_VIDCUR (0x1D0) #define IOMD_VIDEND (0x1D4) #define IOMD_VIDSTART (0x1D8) #define IOMD_VIDINIT (0x1DC) #define IOMD_VIDCR (0x1E0) #define IOMD_DMASTAT (0x1F0) #define IOMD_DMAREQ (0x1F4) #define IOMD_DMAMASK (0x1F8) #define IRQ_INT2 0 //IRQA #define IRQ_INT1 2 #define IRQ_VSYNCPULSE 3 #define IRQ_POWERON 4 #define IRQ_TIMER0 5 #define IRQ_TIMER1 6 #define IRQ_FORCE 7 #define IRQ_INT8 8 //IRQB #define IRQ_ISA 9 #define IRQ_INT6 10 #define IRQ_INT5 11 #define IRQ_INT4 12 #define IRQ_INT3 13 #define IRQ_KEYBOARDTX 14 #define IRQ_KEYBOARDRX 15 #define IRQ_DMA0 16 //DMA #define IRQ_DMA1 17 #define IRQ_DMA2 18 #define IRQ_DMA3 19 #define IRQ_DMAS0 20 #define IRQ_DMAS1 21 #define IRQ_IOP0 24 //IRQC #define IRQ_IOP1 25 #define IRQ_IOP2 26 #define IRQ_IOP3 27 #define IRQ_IOP4 28 #define IRQ_IOP5 29 #define IRQ_IOP6 30 #define IRQ_IOP7 31 #define IRQ_MOUSERX 40 //IRQD #define IRQ_MOUSETX 41 #define IRQ_ADC 42 #define IRQ_EVENT1 43 #define IRQ_EVENT2 44 #define FIQ_INT9 0 // FIQ #define FIQ_INT5 1 #define FIQ_INT6 4 #define FIQ_INT8 6 #define FIQ_FORCE 7 // KCTRL bits #define KB_SKC 0x01 #define KB_SKD 0x02 #define KB_RXP 0x04 #define KB_ENA 0x08 #define KB_RXB 0x10 #define KB_RXF 0x20 #define KB_TXB 0x40 #define KB_TXE 0x80 ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_sa.c�����������������������������������������������������0000644�0001750�0000144�00000016026�10555732132�020002� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <sys/time.h> #include <sys/types.h> #include <unistd.h> #include "armdefs.h" #include "sa1100.h" #define F_CORE (100 * 1024 * 1024) //core frequence #define F_RTC 32768 //RTC #define F_OS 3686400 //OS timer #define RT_SCALE (F_CORE / F_RTC) #define OS_SCALE (F_CORE / F_OS / 10) #define UART3_SCALE 200 /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" typedef struct sa_io_t { /*interrupt controller */ u32 icpr; u32 icip; u32 icfp; u32 icmr; u32 iccr; u32 iclr; /*real time clock(RTC) */ u32 rcnr; u32 rtar; u32 rtsr; u32 rttr; u32 rt_scale; /*core frequence to 32.768K */ u32 rt_count; /*os timer */ u32 oscr; u32 osmr0, osmr1, osmr2, osmr3; u32 ower; u32 ossr; u32 oier; u32 os_scale; /*uart3 controller */ u32 utcr0; u32 utcr1; u32 utcr2; u32 utcr3; u32 utdr; u32 utsr0; u32 utsr1; u32 uart3_scale; /* 2007-01-21 added by Anthony Lee */ u8 uart3_buf; } sa_io_t; static sa_io_t sa_io; static void refresh_irq (ARMul_State *); static void sa_io_reset () { memset (&sa_io, 0, sizeof (sa_io)); sa_io.utsr0 = 1; /*always TFS, no others */ sa_io.utsr1 = 0x4; /*TNF*/}; void sa_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { printf ("SKYEYE: sa_io_write_byte error\n"); skyeye_exit (-1); } void sa_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { printf ("SKYEYE: sa_io_write_halfword error\n"); skyeye_exit (-1); } static void sa_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { switch (addr) { /*RTC*/ case RCNR: sa_io.rcnr = data; break; case RTAR: sa_io.rtar = data; break; case RTSR: sa_io.rtsr |= (data & 0xc); sa_io.rtsr &= ~(data & 0x3); break; case RTTR: sa_io.rttr = data & 0x3ffffff; break; /*OS timer */ case OSCR: sa_io.oscr = data; break; case OSMR0: sa_io.osmr0 = data; break; case OSMR1: sa_io.osmr1 = data; break; case OSMR2: sa_io.osmr2 = data; break; case OSMR3: sa_io.osmr3 = data; break; case OWER: sa_io.ower |= data & 0x1; break; case OSSR: sa_io.ossr &= ~(data & 0xf); break; case OIER: sa_io.oier = data & 0xf; break; /*interrupt control */ case ICPR: case ICIP: case ICFP: /*read only */ break; case ICMR: sa_io.icmr = data; break; case ICLR: sa_io.iclr = data; break; /*UART 3 */ case UTCR0: sa_io.utcr0 = data & 0x7f; break; case UTCR1: sa_io.utcr1 = data & 0xf; break; case UTCR2: sa_io.utcr2 = data & 0xff; break; case UTCR3: sa_io.utcr3 = data & 0x3f; break; case UTDR: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); //log_msg("UTDR write\n"); } break; case UTSR0: sa_io.utsr0 &= ~(data & 0x1b); break; default: //log_msg("addr %x unknow\n", addr); ; }; }; ARMword sa_io_read_byte (ARMul_State * state, ARMword addr) { printf ("SKYEYE: sa_io_read_byte error\n"); skyeye_exit (-1); } ARMword sa_io_read_halfword (ARMul_State * state, ARMword addr) { printf ("SKYEYE: sa_io_read_halfword error\n"); skyeye_exit (-1); } ARMword sa_io_read_word (ARMul_State * state, ARMword addr) { u32 data; switch (addr) { /*RTC*/ case RCNR: data = sa_io.rcnr; break; case RTAR: data = sa_io.rtar; break; case RTSR: data = sa_io.rtsr; break; case RTTR: data = sa_io.rttr; break; /*OS timer */ case OSCR: data = sa_io.oscr; break; case OSMR0: data = sa_io.osmr0; break; case OSMR1: data = sa_io.osmr1; break; case OSMR2: data = sa_io.osmr2; break; case OSMR3: data = sa_io.osmr3; break; case OWER: data = sa_io.ower; break; case OSSR: data = sa_io.ossr; break; case OIER: data = sa_io.oier; break; /*interrupt controler */ case ICPR: data = sa_io.icpr; break; case ICIP: data = (sa_io.icmr & sa_io.icpr) & ~sa_io.iclr; break; case ICFP: data = (sa_io.icmr & sa_io.icpr) & sa_io.iclr; break; case ICMR: data = sa_io.icmr; break; case ICLR: data = sa_io.iclr; break; /*UART 3 */ case UTCR0: data = sa_io.utcr0; break; case UTCR1: data = sa_io.utcr1; break; case UTCR2: data = sa_io.utcr2; break; case UTCR3: data = sa_io.utcr3; break; case UTDR: /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ data = (u32)sa_io.uart3_buf; sa_io.utsr0 = 1; /*always TFS, no others */ sa_io.utsr1 = 0x4; /*TNF*/ break; case UTSR0: data = sa_io.utsr0; break; case UTSR1: data = sa_io.utsr1; break; default: //log_msg("addr %x unknow\n", addr); data = 0; }; return data; }; static void sa_io_do_cycle (ARMul_State * state) { /*RTC*/ if (++sa_io.rt_scale >= RT_SCALE) { sa_io.rt_scale = 0; if (sa_io.rt_count++ == (sa_io.rttr & 0xffff)) { sa_io.rt_count = 0; if (sa_io.rcnr++ == sa_io.rtar) { if (sa_io.rtsr & 0x4) { sa_io.rtsr |= 0x1; }; } if (sa_io.rtsr & 0x8) { sa_io.rtsr |= 0x2; } } }; /*OS timer */ if (++sa_io.os_scale >= OS_SCALE) { u32 mask = 0; u32 count; sa_io.os_scale = 0; count = sa_io.oscr++; if (count == sa_io.osmr0) mask = 1; if (count == sa_io.osmr1) mask |= 0x2; if (count == sa_io.osmr2) mask |= 0x4; if (count == sa_io.osmr3) { mask |= 0x8; if (sa_io.ower & 1) state->NresetSig = LOW; } sa_io.ossr |= mask; } /*UART 3 */ if (++sa_io.uart3_scale > UART3_SCALE) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; sa_io.utsr0 |= 1; /*always TFS, no others */ sa_io.utsr1 |= 0x4; /*TNF*/ sa_io.uart3_scale = 0; if(skyeye_uart_read(-1, &sa_io.uart3_buf, 1, &tv, NULL) > 0) { sa_io.utsr1 |= 0x2; //RNE sa_io.utsr0 |= 0x4; //RID } } /*reset interrupt pin status */ refresh_irq (state); }; static void refresh_irq (ARMul_State * state) { u32 irq = 0; u32 mask; /*RTC*/ if ((sa_io.rtsr & 0x1) && (sa_io.rtsr & 0x4)) irq |= RTC_ALARM_IRQ; if ((sa_io.rtsr & 0x2) && (sa_io.rtsr & 0x8)) irq |= RTC_HZ_IRQ; /*OS time */ mask = sa_io.oier & sa_io.ossr; irq |= (mask << OS_IRQ_SHF); /*UART3 */ if ((sa_io.utcr3 & 0x8) && (sa_io.utsr0 & 0x6)) irq |= UART3_IRQ; if (sa_io.utsr0 & 0x38) irq |= UART3_IRQ; if ((sa_io.utcr3 & 0x10) && (sa_io.utsr0 & 0x1)) irq |= UART3_IRQ; sa_io.icpr = irq; sa_io.icip = (sa_io.icmr & sa_io.icpr) & ~sa_io.iclr; sa_io.icfp = (sa_io.icmr & sa_io.icpr) & sa_io.iclr; state->NirqSig = sa_io.icip ? LOW : HIGH; state->NfiqSig = sa_io.icfp ? LOW : HIGH; } void sa1100_mach_init (ARMul_State * state, machine_config_t * mc) { //chy 2003-08-19, setprocessor ARMul_SelectProcessor (state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = LOW; state->Reg[1] = 109; /*adsbitsy machine id. */ sa_io_reset (); mc->mach_io_do_cycle = sa_io_do_cycle; mc->mach_io_reset = sa_io_reset; mc->mach_io_read_byte = sa_io_read_byte; mc->mach_io_write_byte = sa_io_write_byte; mc->mach_io_read_halfword = sa_io_read_halfword; mc->mach_io_write_halfword = sa_io_write_halfword; mc->mach_io_read_word = sa_io_read_word; mc->mach_io_write_word = sa_io_write_word; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/cs89712.h������������������������������������������������������������0000644�0001750�0000144�00000003430�10541455476�016046� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * linux/include/asm-arm/hardware/cs89712.h * * This file contains the hardware definitions of the CS89712 * additional internal registers. * * Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de> * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_CS89712_H #define __ASM_HARDWARE_CS89712_H /* * CS89712 additional registers */ #define PCDR 0x0002 /* Port C Data register ---------------------------- */ #define PCDDR 0x0042 /* Port C Data Direction register ------------------ */ #define SDCONF 0x2300 /* SDRAM Configuration register --------------------- */ #define SDRFPR 0x2340 /* SDRAM Refresh period register -------------------- */ #define SDCONF_ACTIVE (1 << 10) #define SDCONF_CLKCTL (1 << 9) #define SDCONF_WIDTH_4 (0 << 7) #define SDCONF_WIDTH_8 (1 << 7) #define SDCONF_WIDTH_16 (2 << 7) #define SDCONF_WIDTH_32 (3 << 7) #define SDCONF_SIZE_16 (0 << 5) #define SDCONF_SIZE_64 (1 << 5) #define SDCONF_SIZE_128 (2 << 5) #define SDCONF_SIZE_256 (3 << 5) #define SDCONF_CASLAT_2 (2) #define SDCONF_CASLAT_3 (3) #endif /* __ASM_HARDWARE_CS89712_H */ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/sharp.h��������������������������������������������������������������0000644�0001750�0000144�00000026657�10541455476�016163� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _SHARP_H_ #define _SHARP_H_ enum { RTC_ALARM_IRQ = (1 << 31), RTC_HZ_IRQ = (1 << 30), OS_IRQ_SHF = 26, FFUART_IRQ = (1 << 22), }; typedef enum shp_ioregnum_t { /* Interrupt controller */ INTSR = 0x80000500, /* Interrupt Status Register */ INTRSR = 0x80000504, /* Interrupt Raw Status Register */ INTENS = 0x80000508, /* Interrupt Enable Set Register */ INTENC = 0x8000050C, /* Interrupt Enable Clear Register */ /* os timer 1 */ TIMERLOAD1 = 0x80000C00, /* Allows setting or reading the initial Timer2Value */ TIMERVALUE1 = 0x80000C04, /* Allows reading the current Timer2 value */ TIMERCONTROL1 = 0x80000C08, /* Allows setting or reading the Timer2 configuration */ TIMERTCEOI1 = 0x80000c0C, /* Clears the Timer2 interrupt */ /* os timer 2 */ TIMERLOAD2 = 0x80000C20, /* Allows setting or reading the initial Timer2Value */ TIMERVALUE2 = 0x80000C24, /* Allows reading the current Timer2 value */ TIMERCONTROL2 = 0x80000C28, /* Allows setting or reading the Timer2 configuration */ TIMERTCEOI2 = 0x80000c2C, /* Clears the Timer2 interrupt */ /*UART 2 */ UART2DATA = 0x80000700, /* Data Register */ UART2FCON = 0x80000704, /* FIFO Control Register */ UART2BRCON = 0x80000708, /* Baud Rate Control Register */ UART2CON = 0x8000070C, /* Control Register */ UART2STATUS = 0x80000710, /* Status Register */ UART2RAWISR = 0x80000714, /* Raw Interrupt Status Register */ UART2INTEN = 0x80000718, /* Interrupt Mask Register */ UART2ISR = 0x8000071C, /* Interrupt Status Register */ CPLDKEYSTATE = 0x20000000, CPLDINTSTATE = 0x20000004, CPLDINTMASK = 0x20000008, CPLDPWRIO = 0x2000000c, CPLDEXTIO = 0x20000010, } shp_ioregnum_t; #define _BIT(n) (1 << (n)) /* * Interrupt Controller Module Register Structure */ typedef struct { volatile u32 status; volatile u32 rawstatus; volatile u32 enableset; volatile u32 enableclear; } INTCREGS; /********************************************************************** * Interrupt Controller Register Bit Fields *********************************************************************/ /* INTC Interrupt Sources */ #define INTC_GPIO0FIQ_BIT 0 #define INTC_BLINTR_BIT 1 #define INTC_WEINTR_BIT 2 #define INTC_MCINTR_BIT 3 #define INTC_CSINTR_BIT 4 #define INTC_GPIO1INTR_BIT 5 #define INTC_GPIO2INTR_BIT 6 #define INTC_GPIO3INTR_BIT 7 #define INTC_TC1OINTR_BIT 8 #define INTC_TC2OINTR_BIT 9 #define INTC_RTCMINTR_BIT 10 #define INTC_TICKINTR_BIT 11 #define INTC_UART1INTR_BIT 12 #define INTC_UART2INTR_BIT 13 #define INTC_LCDINTR_BIT 14 #define INTC_SSEOTINTR_BIT 15 #define INTC_UART3INTR_BIT 16 #define INTC_SCIINTR_BIT 17 #define INTC_AACINTR_BIT 18 #define INTC_MMCINTR_BIT 19 #define INTC_USBINTR_BIT 20 #define INTC_DMAINTR_BIT 21 #define INTC_TC3OINTR_BIT 22 #define INTC_GPIO4INTR_BIT 23 #define INTC_GPIO5INTR_BIT 24 #define INTC_GPIO6INTR_BIT 25 #define INTC_GPIO7INTR_BIT 26 #define INTC_BMIINTR_BIT 27 #define INTC_GPIO0FIQ _BIT(INTC_GPIO0FIQ_BIT) #define INTC_BLINTR _BIT(INTC_BLINTR_BIT) #define INTC_WEINTR _BIT(INTC_WEINTR_BIT) #define INTC_MCINTR _BIT(INTC_MCINTR_BIT) #define INTC_CSINTR _BIT(INTC_CSINTR_BIT) #define INTC_GPIO1INTR _BIT(INTC_GPIO1INTR_BIT) #define INTC_GPIO2INTR _BIT(INTC_GPIO2INTR_BIT) #define INTC_GPIO3INTR _BIT(INTC_GPIO3INTR_BIT) #define INTC_TC1OINTR _BIT(INTC_TC1OINTR_BIT) #define INTC_TC2OINTR _BIT(INTC_TC2OINTR_BIT) #define INTC_RTCMINTR _BIT(INTC_RTCMINTR_BIT) #define INTC_TICKINTR _BIT(INTC_TICKINTR_BIT) #define INTC_UART1INTR _BIT(INTC_UART1INTR_BIT) #define INTC_UART2INTR _BIT(INTC_UART2INTR_BIT) #define INTC_LCDINTR _BIT(INTC_LCDINTR_BIT) #define INTC_SSEOTINTR _BIT(INTC_SSEOTINTR_BIT) #define INTC_UART3INTR _BIT(INTC_UART3INTR_BIT) #define INTC_SCIINTR _BIT(INTC_SCIINTR_BIT) #define INTC_AACINTR _BIT(INTC_AACINTR_BIT) #define INTC_MMCINTR _BIT(INTC_MMCINTR_BIT) #define INTC_USBINTR _BIT(INTC_USBINTR_BIT) #define INTC_DMAINTR _BIT(INTC_DMAINTR_BIT) #define INTC_TC3OINTR _BIT(INTC_TC3OINTR_BIT) #define INTC_GPIO4INTR _BIT(INTC_GPIO4INTR_BIT) #define INTC_GPIO5INTR _BIT(INTC_GPIO5INTR_BIT) #define INTC_GPIO6INTR _BIT(INTC_GPIO6INTR_BIT) #define INTC_GPIO7INTR _BIT(INTC_GPIO7INTR_BIT) #define INTC_BMIINTR _BIT(INTC_BMIINTR_BIT) /********************************************************************** * Defines for block access to interrupt sources *********************************************************************/ #define INTC_ALL_FIQS ( \ INTC_GPIO0FIQ | \ INTC_BLINTR | \ INTC_WEINTR | \ INTC_MCINTR) #define INTC_ALL_IRQS ( \ INTC_CSINTR | \ INTC_GPIO1INTR | \ INTC_GPIO2INTR | \ INTC_GPIO3INTR | \ INTC_TC1OINTR | \ INTC_TC2OINTR | \ INTC_RTCMINTR | \ INTC_TICKINTR | \ INTC_UART1INTR | \ INTC_UART2INTR | \ INTC_LCDINTR | \ INTC_SSEOTINTR | \ INTC_UART3INTR | \ INTC_SCIINTR | \ INTC_AACINTR | \ INTC_MMCINTR | \ INTC_USBINTR | \ INTC_DMAINTR | \ INTC_TC3OINTR | \ INTC_GPIO4INTR | \ INTC_GPIO5INTR | \ INTC_GPIO6INTR | \ INTC_GPIO7INTR | \ INTC_BMIINTR) #define INTC_ALL_INTS (INTC_ALL_FIQS | INTC_ALL_IRQS) /********************************************************************** * Interrupt Enable Set, Interrupt Enable Clear Registers Bit Fields *********************************************************************/ #define INTC_INT_ENABLE(n) _BIT(n) #define INTC_INT_CLEAR(n) _BIT(n) /* * Timer Module Register Structure */ typedef struct { volatile u32 load; /* RW */ volatile u32 value; /* RO */ volatile u32 control; /* RW */ volatile u32 clear; /* WO */ } TIMERREGS; /********************************************************************** * Timer Load Register Bit Fields *********************************************************************/ #define TIMER_MAXCOUNT (0xFFFF) #define TIMER_LOAD(n) ((n) & TIMER_MAXCOUNT) /********************************************************************** * Timer Control Register Bit Fields *********************************************************************/ #define TIMER_CTRL_ENABLE _BIT(7) #define TIMER_CTRL_DISABLE (0) #define TIMER_CTRL_PERIODIC _BIT(6) #define TIMER_CTRL_FREERUN (0) #define TIMER_CTRL_508K _BIT(3) #define TIMER_CTRL_2K (0) /* * UART Module Register Structure */ typedef struct { volatile u32 data; // 0 Data volatile u32 lcr; // 4 Line Control volatile u32 bcr; // 8 Baud Rate Control volatile u32 control; // c Control volatile u32 status; // 10 Status Flag volatile u32 intraw; // 14 Raw Interrupt volatile u32 inte; // 18 Interrupt Enable volatile u32 intr; // 1c Resultant Interrupt } UARTREGS; #define UART_NUM_MAX 3 // maximum number of UART's /*********************************************************************** * UART Data Register Bit Fields **********************************************************************/ #define UART_DATA_BE _BIT(11) // Break Error #define UART_DATA_OE _BIT(10) // Overrun Error #define UART_DATA_PE _BIT(9) // Parity Error #define UART_DATA_FE _BIT(8) // Framing Error #define UART_DATA_MASK (0xFF) // Data (8 bits) /*********************************************************************** * UART Line Control Register Bit Fields **********************************************************************/ #define UART_LCR_WLEN(n) ((_SBF(5,((n) - 5))) & 0x60) #define UART_LCR_WLEN5 _SBF(5,0) // 5 bits #define UART_LCR_WLEN6 _SBF(5,1) // 6 bits #define UART_LCR_WLEN7 _SBF(5,2) // 7 bits #define UART_LCR_WLEN8 _SBF(5,3) // 8 bits #define UART_LCR_FEN _SBF(4,1) // FIFO Enable #define UART_LCR_STP1 _SBF(3,0) // One Stop Bits Select #define UART_LCR_STP2 _SBF(3,1) // Two Stop Bits Select #define UART_LCR_EPS _SBF(2,1) // Even Parity Select #define UART_LCR_PEVEN _SBF(2,1) // Even Parity Select #define UART_LCR_PODD _SBF(2,0) // Odd Parity Select #define UART_LCR_PEN _SBF(1,1) // Parity Enable #define UART_LCR_PNONE _SBF(1,0) // Parity None #define UART_LCR_SENDBRK _SBF(0,1) // Assert Break /*********************************************************************** * UART Baud Rate Control Register Bit Field **********************************************************************/ #define UART_BCR(n) ((7372800 / (16 * (n))) - 1) // The following values assume a UART clock frequency of 7.3728 MHz #define UART_BCR_2400 0xBF #define UART_BCR_4800 0x5F #define UART_BCR_9600 0x2F #define UART_BCR_19200 0x17 #define UART_BCR_28800 0xF #define UART_BCR_38400 0xB #define UART_BCR_57600 0x7 #define UART_BCR_115200 0x3 #define UART_BCR_153600 0x2 #define UART_BCR_230400 0x1 #define UART_BCR_460800 0x0 /*********************************************************************** * UART Control Register Bit Fields **********************************************************************/ #define UART_CONTROL_SIRBD _BIT(7) // SIR Blanking Disable #define UART_CONTROL_LBE _BIT(6) // Loop Back Enable #define UART_CONTROL_MXP _BIT(5) // Modem Polarity Select #define UART_CONTROL_TXP _BIT(4) // Xmit Pin Polarity Select #define UART_CONTROL_RXP _BIT(3) // Receive Pin Polarity Select #define UART_CONTROL_SIRLP _BIT(2) // IrDA SIR Low Power Mode #define UART_CONTROL_SIR_ENABLE 0 // SIR Enable #define UART_CONTROL_SIR_DISABLE _BIT(1) // SIR Disable #define UART_CONTROL_SIREN _BIT(1) // SIR !DISABLE! bit #define UART_CONTROL_EN _BIT(0) // UART Enable #define UART_CONTROL_UART_ENABLE _BIT(0) // UART Enable /*********************************************************************** * UART Status Register Bit Fields **********************************************************************/ #define UART_STATUS_TXFE _BIT(7) // Transmit FIFO Empty #define UART_STATUS_RXFF _BIT(6) // Receive FIFO Full #define UART_STATUS_TXFF _BIT(5) // Transmit FIFO Full #define UART_STATUS_RXFE _BIT(4) // Receive FIFO Empty #define UART_STATUS_BUSY _BIT(3) // Transmitter Busy #define UART_STATUS_DCD _BIT(2) // Data Carrier Detect #define UART_STATUS_DSR _BIT(1) // Data Set Ready #define UART_STATUS_CTS _BIT(0) // Clear To Send /*********************************************************************** * UART Interrupt Registers Bit Fields * intraw, inte, intr **********************************************************************/ #define UART_INTR_RTI _BIT(3) // Receive Timeout Interrupt #define UART_INTR_MI _BIT(2) // Modem Interrupt #define UART_INTR_TI _BIT(1) // Transmit Interrupt #define UART_INTR_RI _BIT(0) // Receive Interrupt #endif ���������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/s3c2440.h������������������������������������������������������������0000644�0001750�0000144�00000021416�10541455476�016034� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* s3c2440.h - definitions of "s3c2440" machine for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __S3C2440_H_ #define __S3C2440_H_ #define REGW(addr) (*(volatile unsigned int *)(addr)) /******************************************** * Memory Controller Registers ********************************************/ #define MEM_CTL_BASE (0x48000000) #define BWSCON MEM_CTL_BASE+(0x0) #define BANKCON0 MEM_CTL_BASE+(0x4) #define BANKCON1 MEM_CTL_BASE+(0x8) #define BANKCON2 MEM_CTL_BASE+(0xc) #define BANKCON3 MEM_CTL_BASE+(0x10) #define BANKCON4 MEM_CTL_BASE+(0x14) #define BANKCON5 MEM_CTL_BASE+(0x18) #define BANKCON6 MEM_CTL_BASE+(0x1c) #define BANKCON7 MEM_CTL_BASE+(0x20) #define REFRESH MEM_CTL_BASE+(0x24) #define BANKSIZE MEM_CTL_BASE+(0x28) #define MRSRB6 MEM_CTL_BASE+(0x2c) #define MRSRB7 MEM_CTL_BASE+(0x30) /******************************************** * GPIO Controller Registers ********************************************/ #define GPIO_CTL_BASE (0x56000000) #define GPIO_CTL_SIZE (0xC0) #define GPACON GPIO_CTL_BASE+(0x0) #define GPADAT GPIO_CTL_BASE+(0x4) #define GPBCON GPIO_CTL_BASE+(0x10) #define GPBDAT GPIO_CTL_BASE+(0x14) #define GPBUP GPIO_CTL_BASE+(0x18) #define GPCCON GPIO_CTL_BASE+(0x20) #define GPCDAT GPIO_CTL_BASE+(0x24) #define GPCUP GPIO_CTL_BASE+(0x28) #define GPDCON GPIO_CTL_BASE+(0x30) #define GPDDAT GPIO_CTL_BASE+(0x34) #define GPDUP GPIO_CTL_BASE+(0x38) #define GPECON GPIO_CTL_BASE+(0x40) #define GPEDAT GPIO_CTL_BASE+(0x44) #define GPEUP GPIO_CTL_BASE+(0x48) #define GPFCON GPIO_CTL_BASE+(0x50) #define GPFDAT GPIO_CTL_BASE+(0x54) #define GPFUP GPIO_CTL_BASE+(0x58) #define GPGCON GPIO_CTL_BASE+(0x60) #define GPGDAT GPIO_CTL_BASE+(0x64) #define GPGUP GPIO_CTL_BASE+(0x68) #define GPHCON GPIO_CTL_BASE+(0x70) #define GPHDAT GPIO_CTL_BASE+(0x74) #define GPHUP GPIO_CTL_BASE+(0x78) #define MISCCR GPIO_CTL_BASE+(0x80) #define DCLKCON GPIO_CTL_BASE+(0x84) #define EXTINT0 GPIO_CTL_BASE+(0x88) #define EXTINT1 GPIO_CTL_BASE+(0x8c) #define EXTINT2 GPIO_CTL_BASE+(0x90) #define EINTFLT0 GPIO_CTL_BASE+(0x94) #define EINTFLT1 GPIO_CTL_BASE+(0x98) #define EINTFLT2 GPIO_CTL_BASE+(0x9c) #define EINTFLT3 GPIO_CTL_BASE+(0xa0) #define EINTMASK GPIO_CTL_BASE+(0xa4) #define EINTPEND GPIO_CTL_BASE+(0xa8) #define GSTATUS0 GPIO_CTL_BASE+(0xac) #define GSTATUS1 GPIO_CTL_BASE+(0xb0) #define GSTATUS2 GPIO_CTL_BASE+(0xb4) #define GSTATUS3 GPIO_CTL_BASE+(0xb8) #define GSTATUS4 GPIO_CTL_BASE+(0xbc) /******************************************** * Clock and Power Management Registers ********************************************/ #define CLK_CTL_BASE (0x4c000000) #define LOCKTIME CLK_CTL_BASE+(0x0) #define MPLLCON CLK_CTL_BASE+(0x4) #define UPLLCON CLK_CTL_BASE+(0x8) #define CLKCON CLK_CTL_BASE+(0xc) #define CLKSLOW CLK_CTL_BASE+(0x10) #define CLKDIVN CLK_CTL_BASE+(0x14) /******************************************** * UART Control Registers ********************************************/ #define UART_CTL_BASE0 (0x50000000) #define UART_CTL_SIZE (0x802c) #define ULCON (0x0) #define UCON (0x4) #define UFCON (0x8) #define UMCON (0xc) #define UTRSTAT (0x10) #define UERSTAT (0x14) #define UFSTAT (0x18) #define UMSTAT (0x1c) #define UTXH (0x20) #define URXH (0x24) #define UBRDIV (0x28) /**************************************/ /* Interrupt Controller Registers */ /**************************************/ #define INT_CTL_BASE (0x4a000000) #define SRCPND INT_CTL_BASE+(0x0) #define INTMOD INT_CTL_BASE+(0x4) #define INTMSK INT_CTL_BASE+(0x8) #define PRIORITY INT_CTL_BASE+(0xc) #define INTPND INT_CTL_BASE+(0x10) #define INTOFFSET INT_CTL_BASE+(0x14) #define SUBSRCPND INT_CTL_BASE+(0x18) #define INTSUBMSK INT_CTL_BASE+(0x1c) #define INT_ADCTC (1 << 31) /* ADC EOC interrupt */ #define INT_RTC (1 << 30) /* RTC alarm interrupt */ #define INT_SPI1 (1 << 29) /* UART1 transmit interrupt */ #define INT_UART0 (1 << 28) /* UART0 transmit interrupt */ #define INT_IIC (1 << 27) /* IIC interrupt */ #define INT_USBH (1 << 26) /* USB host interrupt */ #define INT_USBD (1 << 25) /* USB device interrupt */ #define INT_RESERVED24 (1 << 24) #define INT_UART1 (1 << 23) /* UART1 receive interrupt */ #define INT_SPI0 (1 << 22) /* SPI interrupt */ #define INT_MMC (1 << 21) /* MMC interrupt */ #define INT_DMA3 (1 << 20) /* DMA channel 3 interrupt */ #define INT_DMA2 (1 << 19) /* DMA channel 2 interrupt */ #define INT_DMA1 (1 << 18) /* DMA channel 1 interrupt */ #define INT_DMA0 (1 << 17) /* DMA channel 0 interrupt */ #define INT_LCD (1 << 16) /* reserved for future use */ #define INT_UART2 (1 << 15) /* UART 2 interrupt */ #define INT_TIMER4 (1 << 14) /* Timer 4 interrupt */ #define INT_TIMER3 (1 << 13) /* Timer 3 interrupt */ #define INT_TIMER2 (1 << 12) /* Timer 2 interrupt */ #define INT_TIMER1 (1 << 11) /* Timer 1 interrupt */ #define INT_TIMER0 (1 << 10) /* Timer 0 interrupt */ #define INT_WDT (1 << 9) /* Watch-Dog timer interrupt */ #define INT_TICK (1 << 8) /* RTC time tick interrupt */ #define INT_BAT_FLT (1 << 7) #define INT_RESERVED6 (1 << 6) /* Reserved for future use */ #define INT_EINT8_23 (1 << 5) /* External interrupt 8 ~ 23 */ #define INT_EINT4_7 (1 << 4) /* External interrupt 4 ~ 7 */ #define INT_EINT3 (1 << 3) /* External interrupt 3 */ #define INT_EINT2 (1 << 2) /* External interrupt 2 */ #define INT_EINT1 (1 << 1) /* External interrupt 1 */ #define INT_EINT0 (1 << 0) /* External interrupt 0 */ #define INT_ADC (1 << 10) #define INT_TC (1 << 9) #define INT_ERR2 (1 << 8) #define INT_TXD2 (1 << 7) #define INT_RXD2 (1 << 6) #define INT_ERR1 (1 << 5) #define INT_TXD1 (1 << 4) #define INT_RXD1 (1 << 3) #define INT_ERR0 (1 << 2) #define INT_TXD0 (1 << 1) #define INT_RXD0 (1 << 0) #define INT_MASK_INIT 0xffffffff #define INT_SUBMSK_INIT 0x7ff /*********************/ /* RTC Registers */ /*********************/ #define RTC_CTL_BASE (0x57000000) #define RTCCON RTC_CTL_BASE+(0x40) #define TICNT RTC_CTL_BASE+(0x44) #define RTCALM RTC_CTL_BASE+(0x50) #define ALMSEC RTC_CTL_BASE+(0x54) #define ALMMIN RTC_CTL_BASE+(0x58) #define ALMHOUR RTC_CTL_BASE+(0x5c) #define ALMDATE RTC_CTL_BASE+(0x60) #define ALMMON RTC_CTL_BASE+(0x64) #define ALMYEAR RTC_CTL_BASE+(0x68) #define RTCRST RTC_CTL_BASE+(0x6c) #define BCDSEC RTC_CTL_BASE+(0x70) #define BCDMIN RTC_CTL_BASE+(0x74) #define BCDHOUR RTC_CtL_BASE+(0x78) #define BCDDATE RTC_CTL_BASE+(0x7c) #define BCDDAY RTC_CTL_BASE+(0x80) #define BCDMON RTC_CTL_BASE+(0x84) #define BCDYEAR RTC_CTL_BASE+(0x88) /***************************/ /* PWM Timer Registers */ /***************************/ #define PWM_CTL_BASE (0x51000000) #define PWM_CTL_SIZE (0x44) #define TCFG0 (0x0) #define TCFG1 (0x4) #define TCON (0x8) #define TCNTB0 (0xc) #define TCMPB0 (0x10) #define TCNTO0 (0x14) #define TCNTB1 (0x18) #define TCMPB1 (0x1c) #define TCNTO1 (0x20) #define TCNTB2 (0x24) #define TCMPB2 (0x28) #define TCNTO2 (0x2c) #define TCNTB3 (0x30) #define TCMPB3 (0x34) #define TCNTO3 (0x38) #define TCNTB4 (0x3c) #define TCNTO4 (0x40) #define S3C2410_TIMER_NUM 5 struct s3c2440_clkpower { u32 locktime; u32 mpllcon; u32 upllcon; u32 clkcon; u32 clkslow; u32 clkdivn; }; struct s3c2440_timer_io { u32 tcfg0; u32 tcfg1; u32 tcon; int tcnt[S3C2410_TIMER_NUM]; int tcmp[S3C2410_TIMER_NUM]; int tcntb[S3C2410_TIMER_NUM]; int tcmpb[S3C2410_TIMER_NUM]; int tcnto[S3C2410_TIMER_NUM]; }; struct s3c2440_uart_io { u32 ulcon; /* UART line control register */ u32 ucon; /* UART control register */ u32 ufcon; /* UART FIFO control register */ u32 umcon; /* UART Modem control register */ u32 utrstat; /* UART Tx/Rx status register */ u32 uerstat; /* UART Rx error status register */ u32 ufstat; /* UART FIFO status register */ u32 umstat; /* UART Modem status register */ u32 utxh; /* UART transmit buffer register */ u32 urxh; /* UART receive buffer register */ u32 ubrdiv; /* Baud rate divisor register 0 */ }; #define UART_INT_RXD 0x1 #define UART_INT_TXD 0x2 #define UART_INT_EXD 0x4 #define UART_UCON_INIT 0x5 #define UART_ULCON_INIT 0x3 //8N1 #define UART_UTRSTAT_INIT 0x6 #endif /* __S3C2440_H_ */ ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_lpc2210.c������������������������������������������������0000644�0001750�0000144�00000045166�10702125437�020467� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_lpc2210.c - define machine lpc2210 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 10/02/2007 Add support for RTEMS/lpc2210 bsp. Be care that the clock in * skyeye lpc2210 support is 1000 times faster than the real hardware * clock * rayx <rayx.cn@gmail.com> * 3/24/2003 init this file. * add machine lpc's function.Most taken from original armio.c * include: lpc_mach_init, lpc_io_do_cycle * lpc_io_read_word, lpc_io_write_word * walimis <walimi@peoplemail.com.cn> * *3/24/2003 chenyu <chenyu-tmlinux@hpclab.cs.tsinghua.edu.cn> has done the * necessary work to armio.c * */ #include "armdefs.h" #include "lpc.h" //#include "skyeye-ne2k.h" /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" #define TC_DIVISOR (50) /* Set your BogoMips here :) may move elsewhere*/ #define DEBUG 0 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr,##a) #else #define DBG_PRINT(a...) #endif typedef struct timer{ ARMword ir; ARMword tcr; ARMword tc; ARMword pr; ARMword pc; ARMword mcr; ARMword mr0; ARMword mr1; ARMword mr2; ARMword mr3; ARMword ccr; ARMword cr0; ARMword cr1; ARMword cr2; ARMword cr3; ARMword emr; } lpc2210_timer_t; typedef struct uart{ ARMword rbr; ARMword thr; ARMword ier; ARMword iir; ARMword fcr; ARMword lcr; ARMword lsr; ARMword msr; ARMword scr; ARMword dll; ARMword dlm; char t_fifo[16]; char r_fifo[16]; } lpc2210_uart_t; typedef struct pll{ ARMword con; ARMword cfg; ARMword stat; ARMword feed; } lpc2210_pll_t; typedef struct vic{ ARMword IRQStatus; ARMword FIQStatus; ARMword RawIntr; ARMword IntSelect; ARMword IntEnable; ARMword IntEnClr; ARMword SoftInt; ARMword SoftIntClear; ARMword Protection; ARMword Vect_Addr; ARMword DefVectAddr; ARMword VectAddr[15]; ARMword VectCntl[15]; } lpc2210_vic_t; typedef struct lpc2210_io { ARMword syscon; /* System control */ ARMword sysflg; /* System status flags */ lpc2210_pll_t pll; lpc2210_timer_t timer[2]; lpc2210_vic_t vic; ARMword pinsel0; /*Pin Select Register*/ ARMword pinsel1; ARMword pinsel2; ARMword bcfg[4]; /*BCFG Extend Mem control*/ ARMword vpbdiv; /*VPB Divider control*/ int tc_prescale; lpc2210_uart_t uart[2]; /* Receive data register */ ARMword mmcr; /*Memory mapping control register*/ ARMword vibdiv; /*real time regs*/ ARMword sec; ARMword min; ARMword hour; ARMword dom; ARMword dow; ARMword doy; ARMword month; ARMword year; ARMword preint; ARMword prefrac; ARMword ccr; /*mam accelerator module*/ ARMword mamcr; ARMword mamtim; } lpc2210_io_t; static lpc2210_io_t lpc2210_io; #define io lpc2210_io void lpc2210_io_write_word(ARMul_State *state, ARMword addr, ARMword data); static void lpc2210_update_int(ARMul_State *state) { u32 irq = 0; int i; //state->NfiqSig = (~(io.vic.RawIntr&io.vic.IntEnable& io.vic.)) ? LOW : HIGH; irq = io.vic.RawIntr & io.vic.IntEnable ; //add by linxz //printf("SKYEYE:RawIntr:0x%x,IntEnable:0x%x\n", io.vic.RawIntr, io.vic.IntEnable); io.vic.IRQStatus = irq & ~io.vic.IntSelect; io.vic.FIQStatus = irq & io.vic.IntSelect; //here only deals some important int: //uart0 and timer0, other peripheral's int reqs are ignored. //added and rmked by linxz //UART0, Int src: 6 if(io.vic.IRQStatus &IRQ_UART0){ for ( i = 0; i<=15; i++ ) { if ( ((io.vic.VectCntl[i] & 0xf) == 6 ) && (io.vic.VectCntl[i] & 0x20) ) break; } if ( ((io.vic.VectCntl[i] & 0xf) == 6 ) && (io.vic.VectCntl[i] & 0x20) ) io.vic.Vect_Addr = io.vic.VectAddr[i]; } //TIMER0, Int src: 4 if(io.vic.IRQStatus &IRQ_TC0){ for ( i = 0; i<=15; i++ ) { if ( ((io.vic.VectCntl[i] & 0xf) == 4 ) && (io.vic.VectCntl[i] & 0x20) ) break; } if ( ((io.vic.VectCntl[i] & 0xf) == 4 ) && (io.vic.VectCntl[i] & 0x20) ) { io.vic.Vect_Addr = io.vic.VectAddr[i]; //printf("VicVect load vectaddr%d:%08x", i, io.vic.Vect_Addr); } } state->NirqSig = io.vic.IRQStatus ? LOW:HIGH; state->NfiqSig = io.vic.FIQStatus ? LOW:HIGH; } static void lpc2210_io_reset(ARMul_State *state) { //io.timer[0].pr = 500000;/*prescale value*/ //rmked by linxz io.timer[0].pr = 0; io.pll.stat |= 1<<10; /*PLL state register should be 1<<10 when hardware ready*/ io.vic.IRQStatus = 0; io.vic.FIQStatus = 0; io.vic.RawIntr = 0; //added by linxz io.vic.IntSelect = 0; io.uart[0].lsr |= 0x60; io.uart[0].iir = 0x01; io.pinsel0 = 0; io.pinsel1 = 0x15400000; //io.pinsel2 = FIX ME io.bcfg[0] = 0x0000fbef; io.bcfg[1] = 0x2000fbef; io.bcfg[2] = 0x1000fbef; io.bcfg[3] = 0x0000fbef; io.vibdiv = 0; } /*lpc2210 io_do_cycle*/ void lpc2210_io_do_cycle(ARMul_State *state) { int t; io.timer[0].pc++; io.timer[1].pc++; //add by linxz //printf("SKYEYE:Timer0 PC:%d, TC:%d\n", io.timer[0].pc, io.timer[0].tc); //printf(",MR0:%d,PR:%d,RISR:%d,IER:%d,ISLR:%d,ISR:%d\n", io.timer[0].mr0, io.timer[0].pr, io.vic.RawIntr, io.vic.IntEnable, io.vic.IntSelect, io.vic.IRQStatus); if (!(io.vic.RawIntr & IRQ_TC0)) { //no timer0 int yet if (io.timer[0].pc >= io.timer[0].pr+1) { io.timer[0].tc++; io.timer[0].pc = 0; if(io.timer[0].tc >= io.timer[0].mr0/1000) /*Skyeye's clock is far more slow than the real Ocs. I have to make the clock interrupt come quicker*/{ // if(io.timer[0].tc == 20){ io.vic.RawIntr |= IRQ_TC0; io.timer[0].tc = 0; //add by linxz //printf("\r\nI\r\n"); } lpc2210_update_int(state); } } if(io.timer[0].pc == 0){ if (!(io.vic.RawIntr & IRQ_UART0)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { //printf("SKYEYE:get input is %c\n",buf); io.uart[0].rbr = buf; io.uart[0].lsr |= 0x1; io.vic.RawIntr |= IRQ_UART0; lpc2210_update_int(state); } }/* if (rcr > 0 && ...*/ } } ARMword lpc2210_fix_int(ARMword val) { /* ARMword ret = 0; if (val & (1 << 2)) ret |= URXINT; if (val & (1 << 5)) ret |= TC1OI; if (val & (1 << 6)) ret |= TC2OI; if (val & (1 << 16)) ret |= AT91_EXT0;*/ return(val); } ARMword lpc2210_unfix_int(ARMword val) { /* ARMword ret = 0; if (val & URXINT) ret |= (1 << 2); if (val & TC1OI) ret |= (1 << 5); if (val & TC2OI) ret |= (1 << 6); if (val & AT91_EXT0) ret |= (1 << 16); */ return(val); } ARMword lpc2210_uart_read(ARMul_State *state, ARMword addr,int i) { ARMword data; //printf("lpc2210_uart_read,addr=%x\n",addr); switch ((addr & 0xfff) >> 2) { case 0x0: // RbR io.uart[i].lsr &= ~0x1; if(i==0) io.vic.RawIntr &= ~IRQ_UART0; else io.vic.RawIntr &= ~IRQ_UART1; lpc2210_update_int(state); data = io.uart[i].rbr; break; case 0x1: // ier data = io.uart[i].ier; break; case 0x2: // iir data = io.uart[i].iir; break; case 0x3: // IDR case 0x4: // IMR case 0x5: // LSR data = io.uart[i].lsr; break; case 0x6: // MSR data = io.uart[i].msr; break; case 0x7: // SCR data = io.uart[i].scr; break; default: DBG_PRINT("uart_read(%s=0x%08x)\n", "uart_reg", addr); break; } return(data); } void lpc2210_uart_write(ARMul_State *state, ARMword addr, ARMword data,int i) { static ARMword tx_buf = 0; //DBG_PRINT("uart_write(0x%x, 0x%x)\n", (addr & 0xfff) >> 2, data); switch ((addr & 0xfff) >> 2) { case 0x0: // THR { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); //io.uart[0].lsr |= 0x40; io.uart[0].lsr |= 0x20; } case 0x2: //FCR { io.uart[i].fcr = data; break; } case 0x7: // SCR io.uart[i].scr = data; break; default: //printf("%c", data); fflush(stdout); DBG_PRINT("uart_write(%s=0x%08x)\n", "uart_reg", addr); break; } } ARMword lpc2210_io_read_word(ARMul_State *state, ARMword addr) { /* * * The lpc2210 system registers * */ ARMword data = -1; static ARMword current_ivr = 0; /* mega hack, 2.0 needs this */ int i; ARMword dataimr = 0; switch (addr) { case 0xfffff000: /* ISR */ // data = unfix_int(io.intsr); // dataimr = unfix_int(io.intmr); data = io.vic.IRQStatus; DBG_PRINT("read ISR=%d\n", data); break; case 0xfffff004: /* interrupt status register */ data = io.vic.FIQStatus; DBG_PRINT("SKYEYE:read ISR=%x,%x\n", data, io.vic.FIQStatus); break; case 0xfffff008: /* IMR */ data = io.vic.RawIntr; break; case 0xfffff00c: /* CORE interrupt status register */ data = io.vic.IntSelect; break; case 0xfffff010: /* IER */ data = io.vic.IntEnable; DBG_PRINT("read IER=%x,after update IntEnable=%x\n", data,io.vic.IntEnable); break; case 0xfffff014: /* Int Enable Clr Reg */ data = io.vic.IntEnClr; lpc2210_update_int(state); break; case 0xfffff034: /* Default Vector Addr Reg */ data = io.vic.DefVectAddr ; break; case 0xfffff030: /* VAR */ data = io.vic.Vect_Addr ; break; case 0xfffff100: /* VicVectAddr0*/ data = io.vic.VectAddr[0] ; break; case 0xfffff200: /*VicVectCntl0*/ data = io.vic.VectCntl[0]; break; /*Timer0 */ case 0xe0004000: data = io.timer[0].ir; break; case 0xe0004004: data = io.timer[0].tcr; break; case 0xe0004008: data = io.timer[0].tc; //io.vic.RawIntr &= ~IRQ_TC0; //printf("SKYEYE:Clear TC Interrupt,tc=%x,RawIntr=%x,\n",data,io.vic.RawIntr); //lpc2210_update_int(state); break; case 0xe000400c: data = io.timer[0].pr; break; case 0xe0004010: data = io.timer[0].pc; break; case 0xe0004014: data = io.timer[0].mcr; break; case 0xe0004018: data = io.timer[0].mr0; break; /*pll*/ case 0xe01fc080: data = io.pll.con; break; case 0xe01fc084: data = io.pll.cfg; break; case 0xe01fc088: data = io.pll.stat|1<<10; /*skyeye should aways return a pll ready*/ break; case 0xe01fc08c: data = io.pll.feed; /*Pin Select Control*/ case 0xe002c000: data = io.pinsel0; break; case 0xE002C004: data = io.pinsel1; break; case 0xE002C014: data = io.pinsel2; break; /*Extend Mem control*/ case 0xFFE00000: data = io.bcfg[0]; break; case 0xFFE00004: data = io.bcfg[1]; break; case 0xFFE00008: data = io.bcfg[2]; break; case 0xFFE0000c: data = io.bcfg[3]; break; /*VIBDIV*/ case 0xe01fc100: data = io.vibdiv; break; /*Real timer*/ case 0xe0024080: data = io.preint; break; case 0xe0024084: data = io.prefrac; break; case 0xe0024008: data = io.ccr; break; case 0xe0024020: data = io.sec; break; case 0xe0024024: data = io.min; break; case 0xe0024028: data = io.hour; break; case 0xe002402c: data = io.dom; break; case 0xe0024030: data = io.dow; break; case 0xe0024034: data = io.doy; break; case 0xe0024038: data = io.month; break; case 0xe002403c: data = io.year; break; /*Mem accelerator regs*/ case 0xe01fc000: data = io.mamcr; break; case 0xe01fc004: data = io.mamtim; break; default: if (addr >=0xe000c000 && addr <= 0xe000c01c) { data = lpc2210_uart_read(state, addr,0); break; } if (addr >=0xe0001000 && addr <= 0xe000101c) { data = lpc2210_uart_read(state, addr,1); break; } if(addr-0xfffff100 <=0x3c && addr-0xfffff100 >=0){ data = io.vic.VectAddr[(addr-0xfffff100)/4] ; break; } if(addr-0xfffff200 <=0x3c && addr-0xfffff200>=0){ data = io.vic.VectCntl[(addr-0xfffff200)/4] ; break; } printf("ERROR:io_read: addr = %x\n", addr); /*fprintf(stderr,"NumInstr %llu, io_read_word unknown addr(0x%08x) = 0x%08x\n", state->NumInstrs, addr, data);*/ SKYEYE_OUTREGS(stderr); //ARMul_Debug(state, 0, 0); break; } return data; } ARMword lpc2210_io_read_byte(ARMul_State *state, ARMword addr) { return lpc2210_io_read_word(state,addr); // SKYEYE_OUTREGS(stderr); //exit(-1); } ARMword lpc2210_io_read_halfword(ARMul_State *state, ARMword addr) { return lpc2210_io_read_word(state,addr); //SKYEYE_OUTREGS(stderr); //exit(-1); } void lpc2210_io_write_byte(ARMul_State *state, ARMword addr, ARMword data) { lpc2210_io_write_word(state,addr,data); //SKYEYE_OUTREGS(stderr); //exit(-1); } void lpc2210_io_write_halfword(ARMul_State *state, ARMword addr, ARMword data) { lpc2210_io_write_word(state,addr,data); //SKYEYE_OUTREGS(stderr); //exit(-1); } void lpc2210_io_write_word(ARMul_State *state, ARMword addr, ARMword data) { int i, mask, nIRQNum, nHighestIRQ; /* * The lpc2210 system registers */ switch (addr) { case 0xfffff000: /* ISR */ DBG_PRINT("SKYEYE:can not write ISR,it is RO,=%d\n", data); break; case 0xfffff004: /* interrupt status register */ //io.vic.FIQStatus = data ; // DBG_PRINT("read ISR=%x,%x\n", data, io.intsr); DBG_PRINT("can not write FIQStatus,it is RO,=%d\n", data); break; case 0xfffff008: /* IMR */ //io.vic.RawIntr = data; DBG_PRINT("can not write RawIntr,it is RO,=%d\n", data); break; case 0xfffff00c: /* CORE interrupt status register */ io.vic.IntSelect = data; break; case 0xfffff010: /* IER */ io.vic.IntEnable = data; io.vic.IntEnClr = ~data; lpc2210_update_int(state); // data = unfix_int(io.intmr); DBG_PRINT("write IER=%x,after update IntEnable=%x\n", data,io.vic.IntEnable); break; case 0xfffff014: /* IECR */ io.vic.IntEnClr = data; io.vic.IntEnable = ~data; lpc2210_update_int(state); break; case 0xfffff018: /* SIR */ io.vic.SoftInt = data; break; case 0xfffff01c: /* SICR */ io.vic.SoftIntClear = data; break; case 0xfffff020: /* PER */ io.vic.Protection = data; break; case 0xfffff030: /* VAR */ //io.vic.Vect_Addr = data; //rmk by linxz, write VAR with any data will clear current int states //FIQ interrupt //FIXME:clear all bits of FIQStatus? if ( io.vic.FIQStatus ) { io.vic.FIQStatus = 0; break; } //find the current IRQ number: which has the highest priority. mask = 1; nHighestIRQ = 0xffff; for ( i = 0; i<=15; i++ ) { nIRQNum = io.vic.VectCntl[i] & 0xf; if ( (nIRQNum<<mask) & io.vic.IRQStatus ) { if ( nIRQNum < nHighestIRQ ) nHighestIRQ = nIRQNum; } } //If there's at least one IRQ now, clean status and raw //status register. if ( nHighestIRQ != 0xffff ) { io.vic.IRQStatus &= ~( nHighestIRQ << mask ); io.vic.RawIntr &= ~( nHighestIRQ << mask); } break; case 0xfffff034: /* DVAR */ io.vic.DefVectAddr = data; break; /*Timer0 */ case 0xe0004000: io.timer[0].ir = data; if(io.timer[0].ir&0x1){ io.vic.RawIntr &= ~IRQ_TC0; } lpc2210_update_int(state); break; case 0xe0004004: io.timer[0].tcr = data; break; case 0xe0004008: io.timer[0].tc = data; break; case 0xe000400c: io.timer[0].pr = data; break; case 0xe0004010: io.timer[0].pc = data; break; case 0xe0004014: io.timer[0].mcr = data; break; case 0xe0004018: io.timer[0].mr0 = data; break; /*pll*/ case 0xe01fc080: io.pll.con = data; break; case 0xe01fc084: io.pll.cfg = data; break; case 0xe01fc088: io.pll.stat = data; break; case 0xe01fc08c: io.pll.feed = data; break; /*memory map control*/ case 0xe01fc040: io.mmcr = data; break; /*Pin select control*/ case 0xe002c000: io.pinsel0 = data; break; case 0xE002C004: io.pinsel1 = data; break; case 0xE002C014: io.pinsel2 = data; break; /*Extend Mem control*/ case 0xFFE00000: io.bcfg[0] = data; break; case 0xFFE00004: io.bcfg[1] = data; break; case 0xFFE00008: io.bcfg[2] = data; break; case 0xFFE0000c: io.bcfg[3] = data; break; /*VIBDIV*/ case 0xe01fc100: io.vibdiv = data; break; /*Real timer*/ case 0xe0024008: io.ccr = data; break; case 0xe0024080: io.preint = data; break; case 0xe0024084: io.prefrac = data; break; case 0xe0024020: io.sec = data; break; case 0xe0024024: io.min = data; break; case 0xe0024028: io.hour = data; break; case 0xe002402c: io.dom = data; break; case 0xe0024030: io.dow = data; break; case 0xe0024034: io.doy = data; break; case 0xe0024038: io.month = data; break; case 0xe002403c: io.year = data; break; /*Mem accelerator regs*/ case 0xe01fc000: io.mamcr = data; break; case 0xe01fc004: io.mamtim = data; break; default: if (addr >=0xe000c000 && addr <= 0xe000c01c) { lpc2210_uart_write(state, addr, data,0); break; } if (addr >=0xe0001000 && addr <= 0xe000101c) { lpc2210_uart_write(state, addr, data,1); break; } if(addr-0xfffff100 <=0x3c && addr-0xfffff100 >=0){ io.vic.VectAddr[(addr-0xfffff100)/4] = data; break; } if(addr-0xfffff200 <=0x3c && addr-0xfffff200>=0){ io.vic.VectCntl[(addr-0xfffff200)/4] = data; break; } printf("ERROR:io_write a non-exsiting addr:addr = %x, data = %x\n", addr, data); /* fprintf(stderr,"NumInstr %llu,io_write_word unknown addr(1x%08x) = 0x%08x\n", state->NumInstrs, addr, data);*/ //SKYEYE_OUTREGS(stderr); //ARMul_Debug(state, 0, 0); break; } } void lpc2210_mach_init(ARMul_State *state, machine_config_t *this_mach) { //chy 2003-08-19, setprocessor ARMul_SelectProcessor(state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; this_mach->mach_io_do_cycle = lpc2210_io_do_cycle; this_mach->mach_io_reset = lpc2210_io_reset; this_mach->mach_io_read_byte = lpc2210_io_read_byte; this_mach->mach_io_write_byte = lpc2210_io_write_byte; this_mach->mach_io_read_halfword = lpc2210_io_read_halfword; this_mach->mach_io_write_halfword = lpc2210_io_write_halfword; this_mach->mach_io_read_word = lpc2210_io_read_word; this_mach->mach_io_write_word = lpc2210_io_write_word; this_mach->mach_update_int = lpc2210_update_int; //ksh 2004-2-7 state->mach_io.instr = (ARMword *)&io.vic.IRQStatus; //*state->io.instr = (ARMword *)&io.intsr; //state->io->net_flags = (ARMword *)&io.net_flags; //state->mach_io.net_int = (ARMword *)&io.net_int; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_s3c4510b.c�����������������������������������������������0000644�0001750�0000144�00000024345�10555732132�020546� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_s3c4510b.c - define machine s3c4510b for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 06/20/2005 move ethernet simulation to dev_net_s3c4510b.c * walimis <wlm@student.dlut.edu.cn> * * 9/05/2004 add ethernet controller support. * get patch from <telpro2003@yahoo.com.cn> * walimis <wlm@student.dlut.edu.cn> * * 10/05/2003 correct interrupt support. now it can boot uclinux to invoke shell. * walimis <wlm@student.dlut.edu.cn> * * 7/21/2003 correct timer support. * now it can boot uclinux. * walimis <wlm@student.dlut.edu.cn> * * 7/17/2003 add interrupt, timer and uart support. * walimis <wlm@student.dlut.edu.cn> * * 3/28/2003 init this file. * add machine s3c4510b's function.Most taken from original armio.c * include: s3c4510b_mach_init, s3c4510b_io_do_cycle * s3c4510b_io_read_word, s3c4510b_io_write_word * walimis <walimi@peoplemail.com.cn> * * */ #include "armdefs.h" #include "s3c4510b.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* */ /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" ARMword s3c4510b_io_read_word (ARMul_State * state, ARMword addr); void s3c4510b_io_write_word (ARMul_State * state, ARMword addr, ARMword data); /* s3c4510b Internal IO Registers * */ typedef struct s3c4510b_io { /*System Manager control */ ARMword syscfg; ARMword clkcon; /*Interrupt Controller Registers */ ARMword intmod; ARMword intpnd; ARMword intmsk; ARMword intoffset; ARMword intpndtst; ARMword intoset_fiq; ARMword intoset_irq; /*UART Registers */ ARMword ulcon0; ARMword ulcon1; ARMword ucon0; ARMword ucon1; ARMword ustat0; ARMword ustat1; ARMword utxbuf0; ARMword utxbuf1; ARMword urxbuf0; ARMword urxbuf1; ARMword ubrdiv0; ARMword ubrdiv1; /*Timers Registers */ ARMword tmod; ARMword tdata0; ARMword tdata1; int tcnt0; int tcnt1; } s3c4510b_io_t; static s3c4510b_io_t s3c4510b_io; #define io s3c4510b_io #define ENABLE_TIMER0 io.tmod & 0x1 #define ENABLE_TIMER1 io.tmod & 0x8 //extern int skyeye_net_on; static unsigned char mac_buf[4096]; static void s3c4510b_update_int (ARMul_State * state) { ARMword requests = io.intpnd & (~io.intmsk & INT_MASK_INIT); state->NfiqSig = (requests & io.intmod) ? LOW : HIGH; state->NirqSig = (requests & ~io.intmod) ? LOW : HIGH; } static void s3c4510b_set_interrupt (unsigned int irq) { io.intpnd |= (1 << irq); } static int s3c4510b_pending_intr (u32 interrupt) { return ((io.intpnd & (1 << interrupt))); } static void s3c4510b_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; s3c4510b_update_int (state); } static void s3c4510b_io_reset (ARMul_State * state) { memset (&s3c4510b_io, 0, sizeof (s3c4510b_io)); io.syscfg = 0x37ffff91; io.intmsk = INT_MASK_INIT; io.intoffset = io.intoset_fiq = io.intoset_irq = 0x00000054; io.ustat0 = io.ustat1 = 0xc0; io.tcnt0 = io.tcnt1 = 0xffffffff; }; /*s3c4510b io_do_cycle */ void s3c4510b_io_do_cycle (ARMul_State * state) { /*Timer */ if (ENABLE_TIMER0) { io.tcnt0--; if (io.tcnt0 < 0) { io.tcnt0 = io.tdata0; s3c4510b_set_interrupt (INT_TIMER0); s3c4510b_update_int (state); return; } } if (ENABLE_TIMER1) { if (--io.tcnt1 < 0) { io.tcnt1 = io.tdata1; s3c4510b_set_interrupt (INT_TIMER1); s3c4510b_update_int (state); } } /*UART*/ { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { //ctrl_c support,replace by ctrl_a if (buf == 1) buf = 3; io.urxbuf0 = io.urxbuf1 = (int) buf; io.ustat0 |= UART_LSR_DR; io.ustat1 |= UART_LSR_DR; if (!(io.intpnd & (1 << INT_UARTRX0)) || !(io.intpnd & (1 << INT_UARTRX1))) { if ((io.ucon0 & 0x3) == 0x1) { s3c4510b_set_interrupt (INT_UARTRX0); s3c4510b_update_int (state); return; } if ((io.ucon1 & 0x3) == 0x1) { s3c4510b_set_interrupt (INT_UARTRX1); s3c4510b_update_int (state); return; } } } } s3c4510b_update_int (state); } /* IO Read Routine * */ ARMword s3c4510b_io_read_byte (ARMul_State * state, ARMword addr) { //printf("SKYEYE: s3c4510b_io_read_byte error\n"); s3c4510b_io_read_word (state, addr); } ARMword s3c4510b_io_read_halfword (ARMul_State * state, ARMword addr) { //printf("SKYEYE: s3c4510b_io_read_halfword error\n"); s3c4510b_io_read_word (state, addr); } ARMword s3c4510b_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = -1; switch (addr) { case SYSCFG: data = io.syscfg; break; case CLKCON: data = io.clkcon; break; case INTMOD: data = io.intmod; break; case INTPND: data = io.intpnd; break; case INTMSK: data = io.intmsk; break; case INTOFFSET: case INTPNDTST: data = io.intpndtst; break; case INTOSET_FIQ: data = io.intoset_fiq; break; case INTOSET_IRQ: { /*find which interrupt is pending */ int i; for (i = 0; i < 26; i++) { if (io.intpnd & (1 << i)) break; } if (i < 26) { data = (i << 2); } else data = 0x54; /*no interrupt is pending, 0x54 is init data. */ } //data = io.intoset_irq; break; /*UART*/ case ULCON0: data = io.ulcon0; break; case ULCON1: data = io.ulcon1; break; case UCON0: data = io.ucon0; break; case UCON1: data = io.ucon1; break; case USTAT0: data = io.ustat0; io.ustat0 &= ~0xf; break; case USTAT1: data = io.ustat1; io.ustat1 &= ~0xf; break; //case UTXBUF0: //case UTXBUF1: case URXBUF0: data = io.urxbuf0; io.ustat0 &= ~UART_LSR_DR; break; case URXBUF1: data = io.urxbuf1; io.ustat1 &= ~UART_LSR_DR; break; case UBRDIV0: data = io.ubrdiv0; break; case UBRDIV1: data = io.ubrdiv1; break; /*Timer */ case TMOD: data = io.tmod; break; case TDATA0: data = io.tdata0; break; case TDATA1: data = io.tdata1; break; case TCNT0: data = io.tcnt0; break; case TCNT1: data = io.tcnt1; break; default: SKYEYE_DBG ("%s (addr = 0x%08x)\n", __FUNCTION__, addr); break; } return data; } /* IO Write Routine * */ void s3c4510b_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { //printf("SKYEYE: s3c4510b_io_write_byte error\n"); s3c4510b_io_write_word (state, addr, data); } void s3c4510b_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { //printf("SKYEYE: s3c4510b_io_write_halfword error\n"); s3c4510b_io_write_word (state, addr, data); } void s3c4510b_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { switch (addr) { case SYSCFG: io.syscfg = data; break; case CLKCON: io.clkcon = data; break; case INTMOD: io.intmod = data; break; case INTPND: /*when write bit 1, we clear apropiate pendind bit. * */ io.intpnd &= (~data & INT_MASK_INIT); break; case INTMSK: io.intmsk = data; break; case INTOFFSET: case INTPNDTST: io.intpndtst = io.intpnd = data; break; case INTOSET_FIQ: io.intoset_fiq = data; break; case INTOSET_IRQ: io.intoset_irq = data; break; /*UART*/ case ULCON0: io.ulcon0 = data; break; case ULCON1: io.ulcon1 = data; break; case UCON0: io.ucon0 = data; break; case UCON1: io.ucon1 = data; break; case USTAT0: io.ustat0 = data; break; case USTAT1: io.ustat1 = data; break; case UTXBUF0: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.ustat0 |= (UART_LSR_THRE | UART_LSR_TEMT); if ((io.ucon0 & 0xc) == 0xc) { /*enable interrupt */ s3c4510b_set_interrupt (INT_UARTTX0); s3c4510b_update_int (state); } } break; case UTXBUF1: break; case UBRDIV0: io.ubrdiv0 = data; break; case UBRDIV1: io.ubrdiv1 = data; break; /*Timer */ case TMOD: io.tmod = data; if (ENABLE_TIMER0) io.tcnt0 = io.tdata0; if (ENABLE_TIMER1) io.tcnt1 = io.tdata1; break; case TDATA0: if (!ENABLE_TIMER0) io.tdata0 = data; /*we manually set tdata0 register, uclinux's data is so big */ io.tdata0 = 0xfff; break; case TDATA1: //if (!ENABLE_TIMER1) io.tdata1 = data; break; case TCNT0: io.tcnt0 = data; break; case TCNT1: io.tcnt1 = data; break; default: SKYEYE_DBG ("%s(0x%08x) = 0x%08x\n", __FUNCTION__, addr, data); break; } } void s3c4510b_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v4_Prop); state->lateabtSig = HIGH; this_mach->mach_io_do_cycle = s3c4510b_io_do_cycle; this_mach->mach_io_reset = s3c4510b_io_reset; this_mach->mach_io_read_word = s3c4510b_io_read_word; this_mach->mach_io_write_word = s3c4510b_io_write_word; this_mach->mach_io_read_halfword = s3c4510b_io_read_halfword; this_mach->mach_io_write_halfword = s3c4510b_io_write_halfword; this_mach->mach_io_read_byte = s3c4510b_io_read_byte; this_mach->mach_io_write_byte = s3c4510b_io_write_byte; this_mach->mach_update_int = s3c4510b_update_int; this_mach->mach_set_intr = s3c4510b_set_interrupt; this_mach->mach_pending_intr = s3c4510b_pending_intr; this_mach->mach_update_intr = s3c4510b_update_intr; //this_mach->mach_mem_read_byte = s3c4510b_mem_read_byte; //this_mach->mach_mem_write_byte = s3c4510b_mem_write_byte; this_mach->state = (void *) state; } �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/clps9312.h�����������������������������������������������������������0000644�0001750�0000144�00000222014�10541455476�016307� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * File: linux/include/asm-arm/arch-ep93xx/regmap.h * * Copyright (C) 2003 Cirrus Logic, Inc * * Copyright (C) 1999 ARM Limited. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_REGMAP_H #define __ASM_ARCH_REGMAP_H /* * Here's the rules: * - EP93xx register addresses in regmap.h are physical addresses. * * - IO_ADDRESS translates a physical address to a virtual one for the * EP93xx's register space only. Don't use it for actual memory. * * - The regs_*.h files in include/asm-arm/arch-ep93xx use IO_ADDRESS to * translate physical register addresses to virtual addresses. * * - If you do i/o using any of the i/o macros in include/asm-arm/io.h * then supply a physical address as these use __io which is the same * as IO_ADDRESS * */ /* * Where in virtual memory the IO devices (timers, system controllers * and so on). This gets used in arch/arm/mach-ep93xx/mm.c. * * Note: IO is 1-1 mapping, but use IO_VIRT() on all IO addresses * so that it can be moved in the future. */ #define IO_BASE_VIRT 0xE0000000 // Virtual address of IO #define IO_BASE_PHYS 0x80000000 // Physical address of IO #define IO_SIZE 0x0A000000 // How much? #define PCMCIA_BASE_VIRT 0xD0000000 // Virtual address of PCMCIA #define PCMCIA_BASE_PHYS 0xA0000000 // Physical address of PCMCIA #define PCMCIA_SIZE 0x10000000 // How much? /* * The HW_REG macro assumes that the param is a virtual address */ #define HW_REG(reg) ((unsigned int volatile *)reg) /* * Macro to get at IO space when running virtually. * (Translates a physical address to a virtual address) */ #define IO_ADDRESS(pa) (pa - IO_BASE_PHYS + IO_BASE_VIRT) #define IO32(a) (*(volatile unsigned int *)IO_ADDRESS(a)) /******************************************************************/ /* EP93xx Memory Map and Register list */ /******************************************************************/ /* */ /* 0000_0000 - 0000_03ff: Internal ROM Memory (Remap Low) */ /* 0000_0400 - 1fff_ffff: External DRAM Memory (Remap Low) */ /* 0000_0000 - 1fff_ffff: External DRAM Memory (Remap High) */ /* 2000_0000 - 7fff_ffff: External SRAM Memory */ /* 8800_0000 - 8fff_ffff: Expansion Device Memory and Registers */ /* 9000_0000 - 9fff_ffff: Expansion memory */ /* A000_0000 - Afff_ffff: PCMCIA Memory, I/O, and Attribute space */ /* B000_0000 - ffff_ffff: External SRAM memory */ /******************************************************************/ /* EP93xx AHB Blocks Base Address */ /******************************************************************/ /* */ /* The AHB device address map is: */ /* Start End Size Usage */ /* 8000_0000 8000_FFFF: 64 K DMA control registers */ /* 8001_0000 8001_FFFF: 64 K Ethernet MAC control registers */ /* 8002_0000 8002_FFFF: 64 K USB Host control registers */ /* 8003_0000 8003_FFFF: 64 K Raster control registers */ /* 8004_0000 8004_FFFF: 64 K Graphics control registers */ /* 8005_0000 8005_FFFF: 64 K Reserved */ /* 8006_0000 8006_FFFF: 64 K SDRAM control registes */ /* 8007_0000 8007_FFFF: 64 K ARM920T slave */ /* 8008_0000 8008_FFFF: 64 K SMC_PCMCIA control registers */ /* 8009_0000 8009_FFFF: 64 K Boot ROM physical address */ /* 800A_0000 800A_FFFF: 64 K IDE control registers */ /* 800B_0000 800B_FFFF: 64 K VIC1 control registers */ /* 800C_0000 800C_FFFF: 64 K VIC2 control registers */ /* TAG: literal */ #define EP93XX_AHB_BASE (IO_BASE_PHYS) /* ARM920T Address Description */ /* */ /* 0x8000.0000 -> 0x8000.003C M2P Channel 0 Registers (Tx) */ /* 0x8000.0040 -> 0x8000.007C M2P Channel 1 Registers (Rx) */ /* 0x8000.0080 -> 0x8000.00BC M2P Channel 2 Registers (Tx) */ /* 0x8000.00C0 -> 0x8000.00FC M2P Channel 3 Registers (Rx) */ /* 0x8000.0100 -> 0x8000.013C M2M Channel 0 Registers */ /* 0x8000.0140 -> 0x8000.017C M2M Channel 1 Registers */ /* 0x8000.0180 -> 0x8000.01BC Not Used */ /* 0x8000.01C0 -> 0x8000.01FC Not Used */ /* 0x8000.0200 -> 0x8000.023C M2P Channel 5 Registers (Rx) */ /* 0x8000.0240 -> 0x8000.027C M2P Channel 4 Registers (Tx) */ /* 0x8000.0280 -> 0x8000.02BC M2P Channel 7 Registers (Rx) */ /* 0x8000.02C0 -> 0x8000.02FC M2P Channel 6 Registers (Tx) */ /* 0x8000.0300 -> 0x8000.033C M2P Channel 9 Registers (Rx) */ /* 0x8000.0340 -> 0x8000.037C M2P Channel 8 Registers (Tx) */ /* 0x8000.0380 DMA Channel Arbitration register */ /* 0x8000.03C0 DMA Global Interrupt register */ /* 0x8000.03C4 -> 0x8000.03FC Not Used */ /* Internal M2P/P2M Channel Register Map */ /* Offset Name Access Bits Reset Value */ /* 0x00 CONTROL R/W 6 0 */ /* 0x04 INTERRUPT R/W TC* 3 0 */ /* 0x08 PPALLOC R/W 4 channel dependant */ /* (see reg description) */ /* 0x0C STATUS RO 8 0 */ /* 0x10 reserved */ /* 0x14 REMAIN RO 16 0 */ /* 0X18 Reserved */ /* 0X1C Reserved */ /* 0x20 MAXCNT0 R/W 16 0 */ /* 0x24 BASE0 R/W 32 0 */ /* 0x28 CURRENT0 RO 32 0 */ /* 0x2C Reserved */ /* 0x30 MAXCNT1 R/W 16 0 */ /* 0x34 BASE1 R/W 32 0 */ /* 0X38 CURRENT1 RO 32 0 */ /* 0X3C Reserved */ /* */ /* M2M Channel Register Map */ /* Offset Name Access Bits Reset Value */ /* */ /* 0x00 CONTROL R/W 22 0 */ /* 0x04 INTERRUPT R/W TC* 3 0 */ /* 0x08 Reserved */ /* 0x0C STATUS R/W TC* 14 0 */ /* 0x10 BCR0 R/W 16 0 */ /* 0x14 BCR1 R/W 16 0 */ /* 0x18 SAR_BASE0 R/W 32 0 */ /* 0x1C SAR_BASE1 R/W 32 0 */ /* 0x20 Reserved */ /* 0x24 SAR_CURRENT0 RO 32 0 */ /* 0x28 SAR_CURRENT1 RO 32 0 */ /* 0x2C DAR_BASE0 R/W 32 0 */ /* 0x30 DAR_BASE1 R/W 32 0 */ /* 0x34 DAR_CURRENT0 RO 32 0 */ /* 0X38 Reserved */ /* 0X3C DAR_CURRENT1 RO 32 0 */ /* * Write this location once to clear the bit (see */ /* Interrupt/Status register description for which bits */ /* this rule applies to). */ /*---------------------------------------------------------*/ /* Changed to start at offset 0 from base of AHB Space */ /* clc */ /* 8000_0000 - 8000_ffff: DMA */ #define DMA_OFFSET 0x000000 #define DMA_BASE (EP93XX_AHB_BASE|DMA_OFFSET) #define DMAMP_TX_0_CONTROL (DMA_BASE+0x0000) #define DMAMP_TX_0_INTERRUPT (DMA_BASE+0x0004) #define DMAMP_TX_0_PPALLOC (DMA_BASE+0x0008) #define DMAMP_TX_0_STATUS (DMA_BASE+0x000C) #define DMAMP_TX_0_REMAIN (DMA_BASE+0x0014) #define DMAMP_TX_0_MAXCNT0 (DMA_BASE+0x0020) #define DMAMP_TX_0_BASE0 (DMA_BASE+0x0024) #define DMAMP_TX_0_CURRENT0 (DMA_BASE+0x0028) #define DMAMP_TX_0_MAXCNT1 (DMA_BASE+0x0030) #define DMAMP_TX_0_BASE1 (DMA_BASE+0x0034) #define DMAMP_TX_0_CURRENT1 (DMA_BASE+0x0038) #define DMAMP_RX_1_CONTROL (DMA_BASE+0x0040) #define DMAMP_RX_1_INTERRUPT (DMA_BASE+0x0044) #define DMAMP_RX_1_PPALLOC (DMA_BASE+0x0048) #define DMAMP_RX_1_STATUS (DMA_BASE+0x004C) #define DMAMP_RX_1_REMAIN (DMA_BASE+0x0054) #define DMAMP_RX_1_MAXCNT0 (DMA_BASE+0x0060) #define DMAMP_RX_1_BASE0 (DMA_BASE+0x0064) #define DMAMP_RX_1_CURRENT0 (DMA_BASE+0x0068) #define DMAMP_RX_1_MAXCNT1 (DMA_BASE+0x0070) #define DMAMP_RX_1_BASE1 (DMA_BASE+0x0074) #define DMAMP_RX_1_CURRENT1 (DMA_BASE+0x0078) #define DMAMP_TX_2_CONTROL (DMA_BASE+0x0080) #define DMAMP_TX_2_INTERRUPT (DMA_BASE+0x0084) #define DMAMP_TX_2_PPALLOC (DMA_BASE+0x0088) #define DMAMP_TX_2_STATUS (DMA_BASE+0x008C) #define DMAMP_TX_2_REMAIN (DMA_BASE+0x0094) #define DMAMP_TX_2_MAXCNT0 (DMA_BASE+0x00A0) #define DMAMP_TX_2_BASE0 (DMA_BASE+0x00A4) #define DMAMP_TX_2_CURRENT0 (DMA_BASE+0x00A8) #define DMAMP_TX_2_MAXCNT1 (DMA_BASE+0x00B0) #define DMAMP_TX_2_BASE1 (DMA_BASE+0x00B4) #define DMAMP_TX_2_CURRENT1 (DMA_BASE+0x00B8) #define DMAMP_RX_3_CONTROL (DMA_BASE+0x00C0) #define DMAMP_RX_3_INTERRUPT (DMA_BASE+0x00C4) #define DMAMP_RX_3_PPALLOC (DMA_BASE+0x00C8) #define DMAMP_RX_3_STATUS (DMA_BASE+0x00CC) #define DMAMP_RX_3_REMAIN (DMA_BASE+0x00D4) #define DMAMP_RX_3_MAXCNT0 (DMA_BASE+0x00E0) #define DMAMP_RX_3_BASE0 (DMA_BASE+0x00E4) #define DMAMP_RX_3_CURRENT0 (DMA_BASE+0x00E8) #define DMAMP_RX_3_MAXCNT1 (DMA_BASE+0x00F0) #define DMAMP_RX_3_BASE1 (DMA_BASE+0x00F4) #define DMAMP_RX_3_CURRENT1 (DMA_BASE+0x00F8) #define DMAMM_0_CONTROL (DMA_BASE+0x0100) #define DMAMM_0_INTERRUPT (DMA_BASE+0x0104) #define DMAMM_0_STATUS (DMA_BASE+0x010C) #define DMAMM_0_BCR0 (DMA_BASE+0x0110) #define DMAMM_0_BCR1 (DMA_BASE+0x0114) #define DMAMM_0_SAR_BASE0 (DMA_BASE+0x0118) #define DMAMM_0_SAR_BASE1 (DMA_BASE+0x011C) #define DMAMM_0_SAR_CURRENT0 (DMA_BASE+0x0124) #define DMAMM_0_SAR_CURRENT1 (DMA_BASE+0x0128) #define DMAMM_0_DAR_BASE0 (DMA_BASE+0x012C) #define DMAMM_0_DAR_BASE1 (DMA_BASE+0x0130) #define DMAMM_0_DAR_CURRENT0 (DMA_BASE+0x0134) #define DMAMM_0_DAR_CURRENT1 (DMA_BASE+0x013C) #define DMAMM_1_CONTROL (DMA_BASE+0x0140) #define DMAMM_1_INTERRUPT (DMA_BASE+0x0144) #define DMAMM_1_STATUS (DMA_BASE+0x014C) #define DMAMM_1_BCR0 (DMA_BASE+0x0150) #define DMAMM_1_BCR1 (DMA_BASE+0x0154) #define DMAMM_1_SAR_BASE0 (DMA_BASE+0x0158) #define DMAMM_1_SAR_BASE1 (DMA_BASE+0x015C) #define DMAMM_1_SAR_CURRENT0 (DMA_BASE+0x0164) #define DMAMM_1_SAR_CURRENT1 (DMA_BASE+0x0168) #define DMAMM_1_DAR_BASE0 (DMA_BASE+0x016C) #define DMAMM_1_DAR_BASE1 (DMA_BASE+0x0170) #define DMAMM_1_DAR_CURRENT0 (DMA_BASE+0x0174) #define DMAMM_1_DAR_CURRENT1 (DMA_BASE+0x017C) #define DMAMP_RX_5_CONTROL (DMA_BASE+0x0200) #define DMAMP_RX_5_INTERRUPT (DMA_BASE+0x0204) #define DMAMP_RX_5_PPALLOC (DMA_BASE+0x0208) #define DMAMP_RX_5_STATUS (DMA_BASE+0x020C) #define DMAMP_RX_5_REMAIN (DMA_BASE+0x0214) #define DMAMP_RX_5_MAXCNT0 (DMA_BASE+0x0220) #define DMAMP_RX_5_BASE0 (DMA_BASE+0x0224) #define DMAMP_RX_5_CURRENT0 (DMA_BASE+0x0228) #define DMAMP_RX_5_MAXCNT1 (DMA_BASE+0x0230) #define DMAMP_RX_5_BASE1 (DMA_BASE+0x0234) #define DMAMP_RX_5_CURRENT1 (DMA_BASE+0x0238) #define DMAMP_TX_4_CONTROL (DMA_BASE+0x0240) #define DMAMP_TX_4_INTERRUPT (DMA_BASE+0x0244) #define DMAMP_TX_4_PPALLOC (DMA_BASE+0x0248) #define DMAMP_TX_4_STATUS (DMA_BASE+0x024C) #define DMAMP_TX_4_REMAIN (DMA_BASE+0x0254) #define DMAMP_TX_4_MAXCNT0 (DMA_BASE+0x0260) #define DMAMP_TX_4_BASE0 (DMA_BASE+0x0264) #define DMAMP_TX_4_CURRENT0 (DMA_BASE+0x0268) #define DMAMP_TX_4_MAXCNT1 (DMA_BASE+0x0270) #define DMAMP_TX_4_BASE1 (DMA_BASE+0x0274) #define DMAMP_TX_4_CURRENT1 (DMA_BASE+0x0278) #define DMAMP_RX_7_CONTROL (DMA_BASE+0x0280) #define DMAMP_RX_7_INTERRUPT (DMA_BASE+0x0284) #define DMAMP_RX_7_PPALLOC (DMA_BASE+0x0288) #define DMAMP_RX_7_STATUS (DMA_BASE+0x028C) #define DMAMP_RX_7_REMAIN (DMA_BASE+0x0294) #define DMAMP_RX_7_MAXCNT0 (DMA_BASE+0x02A0) #define DMAMP_RX_7_BASE0 (DMA_BASE+0x02A4) #define DMAMP_RX_7_CURRENT0 (DMA_BASE+0x02A8) #define DMAMP_RX_7_MAXCNT1 (DMA_BASE+0x02B0) #define DMAMP_RX_7_BASE1 (DMA_BASE+0x02B4) #define DMAMP_RX_7_CURRENT1 (DMA_BASE+0x02B8) #define DMAMP_TX_6_CONTROL (DMA_BASE+0x02C0) #define DMAMP_TX_6_INTERRUPT (DMA_BASE+0x02C4) #define DMAMP_TX_6_PPALLOC (DMA_BASE+0x02C8) #define DMAMP_TX_6_STATUS (DMA_BASE+0x02CC) #define DMAMP_TX_6_REMAIN (DMA_BASE+0x02D4) #define DMAMP_TX_6_MAXCNT0 (DMA_BASE+0x02E0) #define DMAMP_TX_6_BASE0 (DMA_BASE+0x02E4) #define DMAMP_TX_6_CURRENT0 (DMA_BASE+0x02E8) #define DMAMP_TX_6_MAXCNT1 (DMA_BASE+0x02F0) #define DMAMP_TX_6_BASE1 (DMA_BASE+0x02F4) #define DMAMP_TX_6_CURRENT1 (DMA_BASE+0x02F8) #define DMAMP_RX_9_CONTROL (DMA_BASE+0x0300) #define DMAMP_RX_9_INTERRUPT (DMA_BASE+0x0304) #define DMAMP_RX_9_PPALLOC (DMA_BASE+0x0308) #define DMAMP_RX_9_STATUS (DMA_BASE+0x030C) #define DMAMP_RX_9_REMAIN (DMA_BASE+0x0314) #define DMAMP_RX_9_MAXCNT0 (DMA_BASE+0x0320) #define DMAMP_RX_9_BASE0 (DMA_BASE+0x0324) #define DMAMP_RX_9_CURRENT0 (DMA_BASE+0x0328) #define DMAMP_RX_9_MAXCNT1 (DMA_BASE+0x0330) #define DMAMP_RX_9_BASE1 (DMA_BASE+0x0334) #define DMAMP_RX_9_CURRENT1 (DMA_BASE+0x0338) #define DMAMP_TX_8_CONTROL (DMA_BASE+0x0340) #define DMAMP_TX_8_INTERRUPT (DMA_BASE+0x0344) #define DMAMP_TX_8_PPALLOC (DMA_BASE+0x0348) #define DMAMP_TX_8_STATUS (DMA_BASE+0x034C) #define DMAMP_TX_8_REMAIN (DMA_BASE+0x0354) #define DMAMP_TX_8_MAXCNT0 (DMA_BASE+0x0360) #define DMAMP_TX_8_BASE0 (DMA_BASE+0x0364) #define DMAMP_TX_8_CURRENT0 (DMA_BASE+0x0368) #define DMAMP_TX_8_MAXCNT1 (DMA_BASE+0x0370) #define DMAMP_TX_8_BASE1 (DMA_BASE+0x0374) #define DMAMP_TX_8_CURRENT1 (DMA_BASE+0x0378) #define DMA_ARBITRATION (DMA_BASE+0x0380) #define DMA_INTERRUPT (DMA_BASE+0x03C0) /* 8001_0000 - 8001_ffff: Ether MAC */ #define MAC_OFFSET 0x010000 #define MAC_BASE (EP93XX_AHB_BASE|MAC_OFFSET) #define MAC_RXCTL (MAC_BASE+0x00) /* 2-RW Rx Control */ #define MAC_TXCTL (MAC_BASE+0x04) /* 1-RW Tx Control */ #define MAC_TESTCTL (MAC_BASE+0x08) /* 1-RW Test Control */ #define MAC_MIICMD (MAC_BASE+0x10) /* 2-RW MII(Media Independent Intf) Command */ #define MAC_MIIDATA (MAC_BASE+0x14) /* 2-RW MII Data */ #define MAC_MIISTS (MAC_BASE+0x18) /* 1-RO MII Status */ #define MAC_SELFCTL (MAC_BASE+0x20) /* 1-RW Self Control for LED interface */ #define MAC_INTEN (MAC_BASE+0x24) /* 4-RW Intrrpt Enable */ #define MAC_INTSTSP (MAC_BASE+0x28) /* 4-RW Intrrpt Status Preserve */ #define MAC_INTSTSC (MAC_BASE+0x2C) /* 4-RO Intrrpt Status Clear */ #define MAC_DIAGAD (MAC_BASE+0x38) /* 4-RW Diag Addr (debug only) */ #define MAC_DIAGDATA (MAC_BASE+0x3C) /* 4-RW Diag Data (debug only) */ #define MAC_GT (MAC_BASE+0x40) /* 4-RW General Timer */ #define MAC_FCT (MAC_BASE+0x44) /* 4-RO Flow Control Timer */ #define MAC_FCF (MAC_BASE+0x48) /* 4-RW Flow Control Format */ #define MAC_AFP (MAC_BASE+0x4C) /* 1-RW Addr Filter Pointer */ #define MAC_HASHTB (MAC_BASE+0x50) /* 8-RW Logical Addr Filter (Hash Table) */ #define MAC_INDAD (MAC_BASE+0x50) /* 6-RW Individual Addr, IA */ #define MAC_INDAD_UPPER (MAC_BASE+0x54) /* 6-RW Individual Addr, IA */ #define MAC_FER (MAC_BASE+0x60) /* 4-RW Cardbus Functn Event Reg */ #define MAC_FERMASK (MAC_BASE+0x64) /* 4-RW Cardbus Functn Event Mask Reg */ #define MAC_FPSR (MAC_BASE+0x68) /* 4-RO Cardbus Functn Present Status Reg */ #define MAC_FFER (MAC_BASE+0x6C) /* 4-RW Cardbus Functn Force Event Reg */ #define MAC_TXCOLLCNT (MAC_BASE+0x70) /* 2-RW Tx Collision Count */ #define MAC_RXMISSCNT (MAC_BASE+0x74) /* 2-RW Rx Miss Count */ #define MAC_RXRUNTCNT (MAC_BASE+0x78) /* 2-RW Rx Runt Count */ #define MAC_BMCTL (MAC_BASE+0x80) /* 1-RW Bus Master Control */ #define MAC_BMSTS (MAC_BASE+0x84) /* 1-RO Bus Master Status */ #define MAC_RXBCA (MAC_BASE+0x88) /* 4-RO Rx buffer current address */ #define MAC_TXBCA (MAC_BASE+0x8C) /* 4-RO Tx buffer current address */ #define MAC_RXDBA (MAC_BASE+0x90) /* 4-RW Rx Descrptr Queue Base Addr */ #define MAC_RXDBL (UINT16*)(MAC_BASE+0x94) /* 2-RW Rx Descrptr Queue Base Length */ #define MAC_RXDCA (MAC_BASE+0x98) /* 4-RW Rx Descrptr Current Addr */ #define MAC_RXDEQ (MAC_BASE+0x9C) /* 2-RW Rx Descrptr Enqueue */ #define MAC_RXSBA (MAC_BASE+0xA0) /* 4-RW Rx Status Queue Base Addr */ #define MAC_RXSBL (UINT16*)(MAC_BASE+0xA4) /* 2-RW Rx Status Queue Base Length */ #define MAC_RXSCA (MAC_BASE+0xA8) /* 4-RW Rx Status Current Addr */ #define MAC_RXSEQ (MAC_BASE+0xAC) /* 2-RW Rx Status Enqueue */ #define MAC_TXDBA (MAC_BASE+0xB0) /* 4-RW Tx Descrptr Queue Base Addr */ #define MAC_TXDBL (MAC_BASE+0xB4) /* 2-RW Tx Descrptr Queue Base Length */ #define MAC_TXDCL (MAC_BASE+0xB6) /* 2-RW Tx Descrptr Queue Current Length */ #define MAC_TXDCA (MAC_BASE+0xB8) /* 4-RW Tx Descrptr Current Addr */ #define MAC_TXDEQ (MAC_BASE+0xBC) /* 2-RW Tx Descrptr Enqueue */ #define MAC_TXSBA (MAC_BASE+0xC0) /* 4-RW Tx status Queue Base Addr */ #define MAC_TXSBL (MAC_BASE+0xC4) /* 2-RW Tx Status Queue Base Length */ #define MAC_TXSCL (MAC_BASE+0xC6) /* 2-RW Tx Status Queue Current Length */ #define MAC_TXSCA (MAC_BASE+0xC8) /* 4-RW Tx Status Current Addr */ #define MAC_TXSEQ (MAC_BASE+0xCC) /* 4-RW Tx Status Current Addr */ #define MAC_RXBTH (MAC_BASE+0xD0) /* 4-RW Rx Buffer Thrshold */ #define MAC_TXBTH (MAC_BASE+0xD4) /* 4-RW Tx Buffer Thrshold */ #define MAC_RXSTH (MAC_BASE+0xD8) /* 4-RW Rx Status Thrshold */ #define MAC_TXSTH (MAC_BASE+0xDC) /* 4-RW Tx Status Thrshold */ #define MAC_RXDTH (MAC_BASE+0xE0) /* 4-RW Rx Descrptr Thrshold */ #define MAC_TXDTH (MAC_BASE+0xE4) /* 4-RW Tx Descrptr Thrshold */ #define MAC_MAXFL (MAC_BASE+0xE8) /* 4-RW Maximum Frame Length */ #define MAC_RXHLEN (MAC_BASE+0xEC) /* 2-RW Rx Header Length */ #define MAC_CFG_REG0 (MAC_BASE+0x100) /* config registers 0-2 */ #define MAC_CFG_REG1 (MAC_BASE+0x104) /* */ #define MAC_CFG_REG2 (MAC_BASE+0x108) /* */ /* 8002_0000 - 8002_ffff: USH */ #define USB_OFFSET 0x020000 #define USB_BASE (EP93XX_AHB_BASE|USB_OFFSET) #define HCREVISION (USB_BASE+0x00) #define HCCONTROL (USB_BASE+0x04) #define HCCOMMANDSTATUS (USB_BASE+0x08) #define HCINTERRUPTSTATUS (USB_BASE+0x0C) #define HCINTERRUPTENABLE (USB_BASE+0x10) #define HCINTERRUPTDISABLE (USB_BASE+0x14) #define HCHCCA (USB_BASE+0x18) #define HCPERIODCURRENTED (USB_BASE+0x1C) #define HCCONTROLHEADED (USB_BASE+0x20) #define HCCONTROLCURRENTED (USB_BASE+0x24) #define HCBULKHEADED (USB_BASE+0x28) #define HCBULKCURRENTED (USB_BASE+0x2C) #define HCDONEHEAD (USB_BASE+0x30) #define HCFMINTERVAL (USB_BASE+0x34) #define HCFMREMAINING (USB_BASE+0x38) #define HCFMNUMBER (USB_BASE+0x3C) #define HCPERIODICSTART (USB_BASE+0x40) #define HCLSTHRESHOLD (USB_BASE+0x44) #define HCRHDESCRIPTORA (USB_BASE+0x48) #define HCRHDESCRIPTORB (USB_BASE+0x4C) #define HCRHSTATUS (USB_BASE+0x50) #define HCRHPORTSTATUS0 (USB_BASE+0x54) #define HCRHPORTSTATUS1 (USB_BASE+0x58) #define HCRHPORTSTATUS2 (USB_BASE+0x5C) /* some tests used these registers names which are typos of original ones */ #define HCRHPROTSTATUS0 (USB_BASE+0x54) #define HCRHPROTSTATUS1 (USB_BASE+0x58) #define HCRHPROTSTATUS2 (USB_BASE+0x5C) /* additional registers for controlling the AHB-HCI interface */ #define USBCTRL (USB_BASE+0x80) #define USBHCI (USB_BASE+0x84) #define USBTXTEST (USB_BASE+0x88) #define USBRXTEST (USB_BASE+0x8C) /* 8003_0000 - 8003_ffff: Raster */ #define RASTER_OFFSET 0x030000 #define RASTER_BASE (EP93XX_AHB_BASE|RASTER_OFFSET) ///#define VLINESTOTAL (RASTER_BASE+0x00) ///#define VSYNCSTRTSTOP (RASTER_BASE+0x04) ///#define VACTIVESTRTSTOP (RASTER_BASE+0x08) ///#define VCLKSTRTSTOP (RASTER_BASE+0x0C) ///#define HCLKSTOTAL (RASTER_BASE+0x10) ///#define HSYNCSTRTSTOP (RASTER_BASE+0x14) ///#define HACTIVESTRTSTOP (RASTER_BASE+0x18) ///#define HCLKSTRTSTOP (RASTER_BASE+0x1C) ///#define BRIGHTNESS (RASTER_BASE+0x20) ///#define VIDEOATTRIBS (RASTER_BASE+0x24) ///#define VIDSCRNPAGE (RASTER_BASE+0x28) ///#define VIDSCRNHPG (RASTER_BASE+0x2C) ///#define SCRNLINES (RASTER_BASE+0x30) ///#define LINELENGTH (RASTER_BASE+0x34) ///#define VLINESTEP (RASTER_BASE+0x38) ///#define LINECARRY (RASTER_BASE+0x3C) ///#define BLINKRATE (RASTER_BASE+0x40) ///#define BLINKMASK (RASTER_BASE+0x44) ///#define BLINKPATTRN (RASTER_BASE+0x48) ///#define PATTRNMASK (RASTER_BASE+0x4C) ///#define BG_OFFSET (RASTER_BASE+0x50) ///#define PIXELMODE (RASTER_BASE+0x54) ///#define PARLLIFOUT (RASTER_BASE+0x58) ///#define PARLLIFIN (RASTER_BASE+0x5C) ///#define CURSOR_ADR_START (RASTER_BASE+0x60) ///#define CURSOR_ADR_RESET (RASTER_BASE+0x64) ///#define CURSORSIZE (RASTER_BASE+0x68) ///#define CURSORCOLOR1 (RASTER_BASE+0x6C) ///#define CURSORCOLOR2 (RASTER_BASE+0x70) ///#define CURSORXYLOC (RASTER_BASE+0x74) ///#define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78) ///#define REALITI_SWLOCK (RASTER_BASE+0x7C) ///#define GS_LUT (RASTER_BASE+0x80) ///#define REALITI_TCR (RASTER_BASE+0x100) ///#define REALITI_TISRA (RASTER_BASE+0x104) ///#define REALITI_TISRB (RASTER_BASE+0x108) ///#define CURSOR_TISR (RASTER_BASE+0x10C) ///#define REALITI_TOCRA (RASTER_BASE+0x110) ///#define REALITI_TOCRB (RASTER_BASE+0x114) ///#define FIFO_TOCRA (RASTER_BASE+0x118) ///#define FIFO_TOCRB (RASTER_BASE+0x11C) ///#define BLINK_TISR (RASTER_BASE+0x120) ///#define DAC_TISRA (RASTER_BASE+0x124) ///#define DAC_TISRB (RASTER_BASE+0x128) ///#define SHIFT_TISR (RASTER_BASE+0x12C) ///#define DACMUX_TOCRA (RASTER_BASE+0x130) ///#define DACMUX_TOCRB (RASTER_BASE+0x134) ///#define PELMUX_TOCR (RASTER_BASE+0x138) ///#define VIDEO_TOCRA (RASTER_BASE+0x13C) ///#define VIDEO_TOCRB (RASTER_BASE+0x140) ///#define YCRCB_TOCR (RASTER_BASE+0x144) ///#define CURSOR_TOCR (RASTER_BASE+0x148) ///#define VIDEO_TOCRC (RASTER_BASE+0x14C) ///#define SHIFT_TOCR (RASTER_BASE+0x150) ///#define BLINK_TOCR (RASTER_BASE+0x154) ///#define REALITI_TCER (RASTER_BASE+0x180) ///#define SIGVAL (RASTER_BASE+0x200) ///#define SIGCTL (RASTER_BASE+0x204) ///#define VSIGSTRTSTOP (RASTER_BASE+0x208) ///#define HSIGSTRTSTOP (RASTER_BASE+0x20C) ///#define SIGCLR (RASTER_BASE+0x210) ///#define ACRATE (RASTER_BASE+0x214) ///#define LUTCONT (RASTER_BASE+0x218) ///#define VBLANKSTRTSTOP (RASTER_BASE+0x228) ///#define HBLANKSTRTSTOP (RASTER_BASE+0x22C) ///#define LUT (RASTER_BASE+0x400) ///#define CURSORBLINK1 (RASTER_BASE+0x21C) ///#define CURSORBLINK2 (RASTER_BASE+0x220) ///#define CURSORBLINK (RASTER_BASE+0x224) ///#define EOLOFFSET (RASTER_BASE+0x230) ///#define FIFOLEVEL (RASTER_BASE+0x234) ///#define GS_LUT2 (RASTER_BASE+0x280) ///#define GS_LUT3 (RASTER_BASE+0x300) /* 8004_0000 - 8004_ffff: Graphics */ #define GRAPHICS_OFFSET 0x040000 #define GRAPHICS_BASE (EP93XX_AHB_BASE|GRAPHICS_OFFSET) ///#define SRCPIXELSTRT (GRAPHICS_BASE+0x00) ///#define DESTPIXELSTRT (GRAPHICS_BASE+0x04) ///#define BLKSRCSTRT (GRAPHICS_BASE+0x08) ///#define BLKDSTSTRT (GRAPHICS_BASE+0x0C) ///#define BLKSRCWIDTH (GRAPHICS_BASE+0x10) ///#define SRCLINELENGTH (GRAPHICS_BASE+0x14) ///#define BLKDESTWIDTH (GRAPHICS_BASE+0x18) ///#define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C) ///#define DESTLINELENGTH (GRAPHICS_BASE+0x20) ///#define BLOCKCTRL (GRAPHICS_BASE+0x24) ///#define TRANSPATTRN (GRAPHICS_BASE+0x28) ///#define BLOCKMASK (GRAPHICS_BASE+0x2C) ///#define BACKGROUND (GRAPHICS_BASE+0x30) ///#define LINEINC (GRAPHICS_BASE+0x34) ///#define LINEINIT (GRAPHICS_BASE+0x38) ///#define LINEPATTRN (GRAPHICS_BASE+0x3C) ///#define GOATTCR (GRAPHICS_BASE+0x40) ///#define GOATTISRA (GRAPHICS_BASE+0x44) ///#define GOATTISRB (GRAPHICS_BASE+0x48) ///#define GOATTOCRA (GRAPHICS_BASE+0x4C) ///#define GOATTOCRB (GRAPHICS_BASE+0x50) ///#define GOATTOCRC (GRAPHICS_BASE+0x54) ///#define GOATTCER (GRAPHICS_BASE+0x80) /* 8005_0000 - 8005_ffff: Reserved */ /*8006_0000 - 8006_ffff: SDRAM */ #define SDRAM_OFFSET 0x060000 #define SDRAM_BASE (EP93XX_AHB_BASE|SDRAM_OFFSET) //#define SDRAMRESERVED (SDRAM_BASE+0x00) /* Reserved */ #define SDRAMGLOBALCFG (SDRAM_BASE+0x04) #define SDRAMREFRESHTIME (SDRAM_BASE+0x08) /* Refresh Timer */ #define SDRAMBOOTSTATUS (SDRAM_BASE+0x0C) #define SDRAMCFG0 (SDRAM_BASE+0x10) /* Configuration Register 0 (nSDCS0) */ #define SDRAMCFG1 (SDRAM_BASE+0x14) /* Configuration Register 1 (nSDCS1) */ #define SDRAMCFG2 (SDRAM_BASE+0x18) /* Configuration Register 2 (nSDCS2) */ #define SDRAMCFG3 (SDRAM_BASE+0x1C) /* Configuration Register 3 (nSDCS3) */ /* 8007_0000 - 8007_ffff: ARM920T Slave */ /* 8008_0000 - 8008_ffff: SRAM CS */ /* SMC register map */ /* Address Read Location Write Location */ /* 0x8000.2000 SMCBCR0(Bank config register 0) SMCBCR0(Bank config register 0) */ /* 0x8000.2004 SMCBCR1(Bank config register 1) SMCBCR1(Bank config register 1) */ /* 0x8000.2008 SMCBCR2(Bank config register 2) SMCBCR2(Bank config register 2) */ /* 0x8000.200C SMCBCR3(Bank config register 3) SMCBCR3(Bank config register 3) */ /* 0x8000.2010 Reserved, RAZ Reserved, RAZ */ /* 0x8000.2014 Reserved, RAZ Reserved, RAZ */ /* 0x8000.2018 SMCBCR6(Bank config register 6) SMCBCR6(Bank config register 6) */ /* 0x8000.201C SMCBCR7(Bank config register 7) SMCBCR7(Bank config register 7) */ /* 0x8000.2020 PC1Attribute Register PC1Attribute */ /* 0x8000.2024 PC1Common Register PC1Common */ /* 0x8000.2028 PC1IO Register PC1IO */ /* 0x8000.202C Reserved, RAZ Reserved, RAZ */ /* 0x8000.2030 PC2Attribute Register PC2Attribute */ /* 0x8000.2034 PC2Common Register PC2Common */ /* 0x8000.2038 PC2IO Register PC2IO */ /* 0x8000.203C Reserved, RAZ Reserved, RAZ */ /* 0x8000.2040 PCMCIA control register PCMCIA control register */ #define SRAM_OFFSET 0x080000 #define SRAM_BASE (EP93XX_AHB_BASE|SRAM_OFFSET) #define SMCBCR0 (SRAM_BASE+0x00) /* 0x8000.2000 Bank config register 0 */ #define SMCBCR1 (SRAM_BASE+0x04) /* 0x8000.2004 Bank config register 1 */ #define SMCBCR2 (SRAM_BASE+0x08) /* 0x8000.2008 Bank config register 2 */ #define SMCBCR3 (SRAM_BASE+0x0C) /* 0x8000.200C Bank config register 3 */ /* 0x8000.2010 Reserved, RAZ */ /* 0x8000.2014 Reserved, RAZ */ #define SMCBCR6 (SRAM_BASE+0x18) /* 0x8000.2018 Bank config register 6 */ #define SMCBCR7 (SRAM_BASE+0x1C) /* 0x8000.201C Bank config register 7 */ #define PC1ATTRIB (SRAM_BASE+0x20) /* 0x8000.2020 PC1 Attribute Register */ #define PC1COMMON (SRAM_BASE+0x24) /* 0x8000.2024 PC1 Common Register */ #define PC1IO (SRAM_BASE+0x28) /* 0x8000.2028 PC1 IO Register */ /* 0x8000.202C Reserved, RAZ */ #define PC2ATTRIB (SRAM_BASE+0x30) /* 0x8000.2030 PC2 Attribute Register */ #define PC2COMMON (SRAM_BASE+0x34) /* 0x8000.2034 PC2 Common Register */ #define PC2IO (SRAM_BASE+0x38) /* 0x8000.2038 PC2 IO Register */ /* 0x8000.203C Reserved, RAZ */ #define PCMCIACNT (SRAM_BASE+0x40) /* 0x8000.2040 PCMCIA control register */ /* 8009_0000 - 8009_ffff: Boot ROM (Remap low or high) */ /* 0000 - 8009_0FFF - Boot ROM code */ /* 0FFF - 8009_FFFF - Reserved */ #define BOOT_OFFSET 0x090000 #define BOOT_BASE (EP93XX_AHB_BASE|BOOT_OFFSET) #define BOOT (BOOT_BASE+0x00) /* 800A_0000 - 800A_ffff: IDE Interface */ #define IDE_OFFSET 0x0a0000 #define IDE_BASE (EP93XX_AHB_BASE|IDE_OFFSET) ///#define IDECR (IDE_BASE+0x00) ///#define IDECFG (IDE_BASE+0x04) ///#define IDEMDMAOP (IDE_BASE+0x08) ///#define IDEUDMAOP (IDE_BASE+0x0C) ///#define IDEDATAOUT (IDE_BASE+0x10) ///#define IDEDATAIN (IDE_BASE+0x14) ///#define IDEMDMADATAOUT (IDE_BASE+0x18) ///#define IDEMDMADATAIN (IDE_BASE+0x1C) ///#define IDEUDMADATAOUT (IDE_BASE+0x20) ///#define IDEUDMADATAIN (IDE_BASE+0x24) ///#define IDEUDMASTATUS (IDE_BASE+0x28) ///#define IDEUDMADEBUG (IDE_BASE+0x2C) ///#define IDEUDMAWFST (IDE_BASE+0x30) ///#define IDEUDMARFST (IDE_BASE+0x34) /* 800B_0000 - 800B_FFFF: VIC 0 */ #define VIC0_OFFSET 0x0B0000 #define VIC0_BASE (EP93XX_AHB_BASE|VIC0_OFFSET) #define VIC0 (VIC0_BASE+0x000) #define VIC0IRQSTATUS (VIC0_BASE+0x000) /* R IRQ status register */ #define VIC0FIQSTATUS (VIC0_BASE+0x004) /* R FIQ status register */ #define VIC0RAWINTR (VIC0_BASE+0x008) /* R Raw interrupt status register */ #define VIC0INTSELECT (VIC0_BASE+0x00C) /* R/W Interrupt select register */ #define VIC0INTENABLE (VIC0_BASE+0x010) /* R/W Interrupt enable register */ #define VIC0INTENCLEAR (VIC0_BASE+0x014) /* W Interrupt enable clear register */ #define VIC0SOFTINT (VIC0_BASE+0x018) /* R/W Software interrupt register */ #define VIC0SOFTINTCLEAR (VIC0_BASE+0x01C) /* R/W Software interrupt clear register */ #define VIC0PROTECTION (VIC0_BASE+0x020) /* R/W Protection enable register */ #define VIC0VECTADDR (VIC0_BASE+0x030) /* R/W Vector address register */ #define VIC0DEFVECTADDR (VIC0_BASE+0x034) /* R/W Default vector address register */ #define VIC0VECTADDR00 (VIC0_BASE+0x100) /* R/W Vector address 00 register */ #define VIC0VECTADDR01 (VIC0_BASE+0x104) /* R/W Vector address 01 register */ #define VIC0VECTADDR02 (VIC0_BASE+0x108) /* R/W Vector address 02 register */ #define VIC0VECTADDR03 (VIC0_BASE+0x10C) /* R/W Vector address 03 register */ #define VIC0VECTADDR04 (VIC0_BASE+0x110) /* R/W Vector address 04 register */ #define VIC0VECTADDR05 (VIC0_BASE+0x114) /* R/W Vector address 05 register */ #define VIC0VECTADDR06 (VIC0_BASE+0x118) /* R/W Vector address 06 register */ #define VIC0VECTADDR07 (VIC0_BASE+0x11C) /* R/W Vector address 07 register */ #define VIC0VECTADDR08 (VIC0_BASE+0x120) /* R/W Vector address 08 register */ #define VIC0VECTADDR09 (VIC0_BASE+0x124) /* R/W Vector address 09 register */ #define VIC0VECTADDR10 (VIC0_BASE+0x128) /* R/W Vector address 10 register */ #define VIC0VECTADDR11 (VIC0_BASE+0x12C) /* R/W Vector address 11 register */ #define VIC0VECTADDR12 (VIC0_BASE+0x130) /* R/W Vector address 12 register */ #define VIC0VECTADDR13 (VIC0_BASE+0x134) /* R/W Vector address 13 register */ #define VIC0VECTADDR14 (VIC0_BASE+0x138) /* R/W Vector address 14 register */ #define VIC0VECTADDR15 (VIC0_BASE+0x13C) /* R/W Vector address 15 register */ #define VIC0VECTCNTL00 (VIC0_BASE+0x200) /* R/W Vector control 00 register */ #define VIC0VECTCNTL01 (VIC0_BASE+0x204) /* R/W Vector control 01 register */ #define VIC0VECTCNTL02 (VIC0_BASE+0x208) /* R/W Vector control 02 register */ #define VIC0VECTCNTL03 (VIC0_BASE+0x20C) /* R/W Vector control 03 register */ #define VIC0VECTCNTL04 (VIC0_BASE+0x210) /* R/W Vector control 04 register */ #define VIC0VECTCNTL05 (VIC0_BASE+0x214) /* R/W Vector control 05 register */ #define VIC0VECTCNTL06 (VIC0_BASE+0x218) /* R/W Vector control 06 register */ #define VIC0VECTCNTL07 (VIC0_BASE+0x21C) /* R/W Vector control 07 register */ #define VIC0VECTCNTL08 (VIC0_BASE+0x220) /* R/W Vector control 08 register */ #define VIC0VECTCNTL09 (VIC0_BASE+0x224) /* R/W Vector control 09 register */ #define VIC0VECTCNTL10 (VIC0_BASE+0x228) /* R/W Vector control 10 register */ #define VIC0VECTCNTL11 (VIC0_BASE+0x22C) /* R/W Vector control 11 register */ #define VIC0VECTCNTL12 (VIC0_BASE+0x230) /* R/W Vector control 12 register */ #define VIC0VECTCNTL13 (VIC0_BASE+0x234) /* R/W Vector control 13 register */ #define VIC0VECTCNTL14 (VIC0_BASE+0x238) /* R/W Vector control 14 register */ #define VIC0VECTCNTL15 (VIC0_BASE+0x23C) /* R/W Vector control 15 register */ #define VIC0ITCR (VIC0_BASE+0x300) /* R/W Test control register */ #define VIC0ITIP1 (VIC0_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN) */ #define VIC0ITIP2 (VIC0_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ #define VIC0ITOP1 (VIC0_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ #define VIC0ITOP2 (VIC0_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ #define VIC0PERIPHID0 (VIC0_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ #define VIC0PERIPHID1 (VIC0_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ #define VIC0PERIPHID2 (VIC0_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ #define VIC0PERIPHID3 (VIC0_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ /* 800C_0000 - 800C_FFFF: VIC 0 */ #define VIC1_OFFSET 0x0C0000 #define VIC1_BASE (EP93XX_AHB_BASE|VIC1_OFFSET) #define VIC1 (VIC1_BASE+0x000) #define VIC1IRQSTATUS (VIC1_BASE+0x000) /* R IRQ status register */ #define VIC1FIQSTATUS (VIC1_BASE+0x004) /* R FIQ status register */ #define VIC1RAWINTR (VIC1_BASE+0x008) /* R Raw interrupt status register */ #define VIC1INTSELECT (VIC1_BASE+0x00C) /* R/W Interrupt select register */ #define VIC1INTENABLE (VIC1_BASE+0x010) /* R/W Interrupt enable register */ #define VIC1INTENCLEAR (VIC1_BASE+0x014) /* W Interrupt enable clear register */ #define VIC1SOFTINT (VIC1_BASE+0x018) /* R/W Software interrupt register */ #define VIC1SOFTINTCLEAR (VIC1_BASE+0x01C) /* R/W Software interrupt clear register */ #define VIC1PROTECTION (VIC1_BASE+0x020) /* R/W Protection enable register */ #define VIC1VECTADDR (VIC1_BASE+0x030) /* R/W Vector address register */ #define VIC1DEFVECTADDR (VIC1_BASE+0x034) /* R/W Default vector address register */ #define VIC1VECTADDR00 (VIC1_BASE+0x100) /* R/W Vector address 00 register */ #define VIC1VECTADDR01 (VIC1_BASE+0x104) /* R/W Vector address 01 register */ #define VIC1VECTADDR02 (VIC1_BASE+0x108) /* R/W Vector address 02 register */ #define VIC1VECTADDR03 (VIC1_BASE+0x10C) /* R/W Vector address 03 register */ #define VIC1VECTADDR04 (VIC1_BASE+0x110) /* R/W Vector address 04 register */ #define VIC1VECTADDR05 (VIC1_BASE+0x114) /* R/W Vector address 05 register */ #define VIC1VECTADDR06 (VIC1_BASE+0x118) /* R/W Vector address 06 register */ #define VIC1VECTADDR07 (VIC1_BASE+0x11C) /* R/W Vector address 07 register */ #define VIC1VECTADDR08 (VIC1_BASE+0x120) /* R/W Vector address 08 register */ #define VIC1VECTADDR09 (VIC1_BASE+0x124) /* R/W Vector address 09 register */ #define VIC1VECTADDR10 (VIC1_BASE+0x128) /* R/W Vector address 10 register */ #define VIC1VECTADDR11 (VIC1_BASE+0x12C) /* R/W Vector address 11 register */ #define VIC1VECTADDR12 (VIC1_BASE+0x130) /* R/W Vector address 12 register */ #define VIC1VECTADDR13 (VIC1_BASE+0x134) /* R/W Vector address 13 register */ #define VIC1VECTADDR14 (VIC1_BASE+0x138) /* R/W Vector address 14 register */ #define VIC1VECTADDR15 (VIC1_BASE+0x13C) /* R/W Vector address 15 register */ #define VIC1VECTCNTL00 (VIC1_BASE+0x200) /* R/W Vector control 00 register */ #define VIC1VECTCNTL01 (VIC1_BASE+0x204) /* R/W Vector control 01 register */ #define VIC1VECTCNTL02 (VIC1_BASE+0x208) /* R/W Vector control 02 register */ #define VIC1VECTCNTL03 (VIC1_BASE+0x20C) /* R/W Vector control 03 register */ #define VIC1VECTCNTL04 (VIC1_BASE+0x210) /* R/W Vector control 04 register */ #define VIC1VECTCNTL05 (VIC1_BASE+0x214) /* R/W Vector control 05 register */ #define VIC1VECTCNTL06 (VIC1_BASE+0x218) /* R/W Vector control 06 register */ #define VIC1VECTCNTL07 (VIC1_BASE+0x21C) /* R/W Vector control 07 register */ #define VIC1VECTCNTL08 (VIC1_BASE+0x220) /* R/W Vector control 08 register */ #define VIC1VECTCNTL09 (VIC1_BASE+0x224) /* R/W Vector control 09 register */ #define VIC1VECTCNTL10 (VIC1_BASE+0x228) /* R/W Vector control 10 register */ #define VIC1VECTCNTL11 (VIC1_BASE+0x22C) /* R/W Vector control 11 register */ #define VIC1VECTCNTL12 (VIC1_BASE+0x230) /* R/W Vector control 12 register */ #define VIC1VECTCNTL13 (VIC1_BASE+0x234) /* R/W Vector control 13 register */ #define VIC1VECTCNTL14 (VIC1_BASE+0x238) /* R/W Vector control 14 register */ #define VIC1VECTCNTL15 (VIC1_BASE+0x23C) /* R/W Vector control 15 register */ #define VIC1ITCR (VIC1_BASE+0x300) /* R/W Test control register */ #define VIC1ITIP1 (VIC1_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN) */ #define VIC1ITIP2 (VIC1_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ #define VIC1ITOP1 (VIC1_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ #define VIC1ITOP2 (VIC1_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ #define VIC1PERIPHID0 (VIC1_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ #define VIC1PERIPHID1 (VIC1_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ #define VIC1PERIPHID2 (VIC1_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ #define VIC1PERIPHID3 (VIC1_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ /*800D_0000 - 807F_FFFF: Reserved AHB space */ /******************************************************************/ /******************************************************************/ /* EP93xx APB Blocks Base Addrs */ /* The APB address map is: */ /* Start End Size Usage */ /* 8080_0000 8080_FFFF: 64 K Reserved */ /* 8081_0000 8081_FFFF: 64 K Timer control registers */ /* 8082_0000 8082_FFFF: 64 K I2S control registers */ /* 8083_0000 8083_FFFF: 64 K Reserved */ /* 8084_0000 8084_FFFF: 64 K GPIO control registers */ /* 8085_0000 8085_FFFF: 64 K Reserved */ /* 8086_0000 8086_FFFF: 64 K Reserved */ /* 8087_0000 8087_FFFF: 64 K Reserved */ /* 8088_0000 8088_FFFF: 64 K AAC control registers */ /* 8089_0000 8089_FFFF: 64 K Reserved */ /* 808A_0000 808A_FFFF: 64 K SPI1 control registers */ /* 808B_0000 808B_FFFF: 64 K IrDA control registers */ /* 808C_0000 808C_FFFF: 64 K UART1 control registers */ /* 808D_0000 808D_FFFF: 64 K UART2 control registers */ /* 808E_0000 808E_FFFF: 64 K UART3 control registers */ /* 808F_0000 808F_FFFF: 64 K Key Matrix control registers */ /* 8090_0000 8090_FFFF: 64 K Touch Screen control registers */ /* 8091_0000 8091_FFFF: 64 K PWM control registers */ /* 8092_0000 8092_FFFF: 64 K Real Time Clock control registers */ /* 8093_0000 8093_1FFF: 64 K Syscon control registers */ /* 8093_2000 8093_FFFF: 64 K Security control registers */ /* 8094_0000 8094_FFFF: 64 K Watchdog control registers */ /* 8095_0000 8FFF_FFFF: 128M Reserved */ #define EP93XX_APB_BASE (IO_BASE_PHYS | 0x00800000) /* 8080_0000 - 8080_ffff: Reserved */ /* 8081_0000 - 8081_ffff: Timers */ #define TIMERS_OFFSET 0x010000 #define TIMERS_BASE (EP93XX_APB_BASE|TIMERS_OFFSET) #define TIMER1LOAD (TIMERS_BASE+0x00) #define TIMER1VALUE (TIMERS_BASE+0x04) #define TIMER1CONTROL (TIMERS_BASE+0x08) #define TIMER1CLEAR (TIMERS_BASE+0x0C) #define TIMER1TEST (TIMERS_BASE+0x10) #define TIMER2LOAD (TIMERS_BASE+0x20) #define TIMER2VALUE (TIMERS_BASE+0x24) #define TIMER2CONTROL (TIMERS_BASE+0x28) #define TIMER2CLEAR (TIMERS_BASE+0x2C) #define TIMER2TEST (TIMERS_BASE+0x30) #define TIMER3LOAD (TIMERS_BASE+0x80) #define TIMER3VALUE (TIMERS_BASE+0x84) #define TIMER3CONTROL (TIMERS_BASE+0x88) #define TIMER3CLEAR (TIMERS_BASE+0x8C) #define TIMER3TEST (TIMERS_BASE+0x90) #define TTIMERBZCONT (TIMERS_BASE+0x40) #define TIMER4VALUELOW (TIMERS_BASE+0x60) #define TIMER4VALUEHIGH (TIMERS_BASE+0x64) /* 8082_0000 - 8082_ffff: SAI (I2S) */ #define SAI_OFFSET 0x020000 #define SAI_BASE (EP93XX_APB_BASE|SAI_OFFSET) #define SAI (SAI_BASE+0x00) #define SAI_TX_CLK_CFG (SAI_BASE+0x00) /* 8082.0000 R/W Transmitter clock config register */ #define SAI_RX_CLK_CFG (SAI_BASE+0x04) /* 8082.0004 R/W Receiver clock config register */ #define SAI_CSR (SAI_BASE+0x08) /* 8082.0008 R/W SAI Global Status register. This */ /* reflects the status of the 3 RX */ /* FIFOs and the 3 TX FIFOs */ #define SAI_GCR (SAI_BASE+0x0C) /* 8082.000C R/W SAI Global Control register */ #define SAI_TX0_LEFT (SAI_BASE+0x10) /* 8082.0010 R/W Left TX data reg for channel 0 */ #define SAI_TX0_RIGHT (SAI_BASE+0x14) /* 8082.0014 R/W Right TX data reg for channel 0 */ #define SAI_TX1_LEFT (SAI_BASE+0x18) /* 8082.0018 R/W Left TX data reg for channel 1 */ #define SAI_TX1_RIGHT (SAI_BASE+0x1C) /* 8082.001C R/W Right TX data reg for channel 1 */ #define SAI_TX2_LEFT (SAI_BASE+0x20) /* 8082.0020 R/W Left TX data reg for channel 2 */ #define SAI_TX2_RIGHT (SAI_BASE+0x24) /* 8082.0024 R/W Right TX data reg for channel 2 */ #define SAI_TX_LCR (SAI_BASE+0x28) /* 8082.0028 R/W TX Line Control data register */ #define SAI_TX_CR (SAI_BASE+0x2C) /* 8082.002C R/W TX Control register */ #define SAI_TX_WL (SAI_BASE+0x30) /* 8082.0030 R/W TX Word Length */ #define SAI_TX_EN0 (SAI_BASE+0x34) /* 8082.0034 R/W TX0 Channel Enable */ #define SAI_TX_EN1 (SAI_BASE+0x38) /* 8082.0038 R/W TX1 Channel Enable */ #define SAI_TX_EN2 (SAI_BASE+0x3C) /* 8082.003C R/W TX2 Channel Enable */ #define SAI_RX0_LEFT (SAI_BASE+0x40) /* 8082.0040 R Left RX data reg for channel 0 */ #define SAI_RX0_RIGHT (SAI_BASE+0x44) /* 8082.0044 R Right RX data reg for channel 0 */ #define SAI_RX1_LEFT (SAI_BASE+0x48) /* 8082.0048 R Left RX data reg for channel 1 */ #define SAI_RX1_RIGHT (SAI_BASE+0x4C) /* 8082.004c R Right RX data reg for channel 1 */ #define SAI_RX2_LEFT (SAI_BASE+0x50) /* 8082.0050 R Left RX data reg for channel 2 */ #define SAI_RX2_RIGHT (SAI_BASE+0x54) /* 8082.0054 R Right RX data reg for channel 2 */ #define SAI_RX_LCR (SAI_BASE+0x58) /* 8082.0058 R/W RX Line Control data register */ #define SAI_RX_CR (SAI_BASE+0x5C) /* 8082.005C R/W RX Control register */ #define SAI_RX_WL (SAI_BASE+0x60) /* 8082.0060 R/W RX Word Length */ #define SAI_RX_EN0 (SAI_BASE+0x64) /* 8082.0064 R/W RX0 Channel Enable */ #define SAI_RX_EN1 (SAI_BASE+0x68) /* 8082.0068 R/W RX1 Channel Enable */ #define SAI_RX_EN2 (SAI_BASE+0x6C) /* 8082.006C R/W RX2 Channel Enable */ /* 8083_0000 - 8083_ffff: Security Block */ #define SECURITY_OFFSET 0x030000 #define SECURITY_BASE (EP93XX_APB_BASE|SECURITY_OFFSET) #define SECFLG (SECURITY_BASE+0x2400) #define SECEN (SECURITY_BASE+0x2410) #define UNIQID (SECURITY_BASE+0x2440) #define UNIQCHK (SECURITY_BASE+0x2450) #define UNIQVAL (SECURITY_BASE+0x2460) #define CLINBOOT (SECURITY_BASE+0x2480) #define CLINVADDR (SECURITY_BASE+0x2484) #define CLSETSKRNL (SECURITY_BASE+0x2488) #define CLSKRNL (SECURITY_BASE+0x248C) #define ITTMP (SECURITY_BASE+0x2490) #define ETBL1 (SECURITY_BASE+0x24A0) #define ETCL1 (SECURITY_BASE+0x24A4) #define ETAPL1 (SECURITY_BASE+0x24A8) #define ETSPTREG1 (SECURITY_BASE+0x24B0) #define ETSPTREG2 (SECURITY_BASE+0x24B4) #define ETSPTREG3 (SECURITY_BASE+0x24B8) #define SECID1 (SECURITY_BASE+0x2500) #define SECID2 (SECURITY_BASE+0x2504) #define SECCHK1 (SECURITY_BASE+0x2520) #define SECCHK2 (SECURITY_BASE+0x2524) #define SECVAL1 (SECURITY_BASE+0x2540) #define SECVAL2 (SECURITY_BASE+0x2544) #define UNIQID2 (SECURITY_BASE+0x2700) #define UNIQID3 (SECURITY_BASE+0x2704) #define UNIQID4 (SECURITY_BASE+0x2708) #define UNIQID5 (SECURITY_BASE+0x270C) #define UNIQCHK2 (SECURITY_BASE+0x2710) #define USRFLG (SECURITY_BASE+0x2714) #define UNIQVAL2 (SECURITY_BASE+0x2720) #define UNIQVAL3 (SECURITY_BASE+0x2724) #define UNIQVAL4 (SECURITY_BASE+0x2728) #define TESTVAL (SECURITY_BASE+0x2744) #define TESTCHK (SECURITY_BASE+0x2754) #define ACHK1 (SECURITY_BASE+0x27A0) #define ACHK2 (SECURITY_BASE+0x27A4) #define PROCRESET (SECURITY_BASE+0x27A8) #define TESTIDR (SECURITY_BASE+0x27AC) #define AVAL1 (SECURITY_BASE+0x27B0) #define AVAL2 (SECURITY_BASE+0x27B4) #define AID1 (SECURITY_BASE+0x27C4) #define AID2 (SECURITY_BASE+0x27C8) #define ADYNREMAP (SECURITY_BASE+0x27D0) #define ALTTMP (SECURITY_BASE+0x27D4) #define PROCSIGN (SECURITY_BASE+0x27F0) #define ECLIDX (SECURITY_BASE+0x2800) #define ECLINE0 (SECURITY_BASE+0x2810) #define ECLINE1 (SECURITY_BASE+0x2814) #define ECLINE2 (SECURITY_BASE+0x2818) #define ECLINE3 (SECURITY_BASE+0x281C) #define ECLINE4 (SECURITY_BASE+0x2820) #define ECLINE5 (SECURITY_BASE+0x2824) #define ECLINE6 (SECURITY_BASE+0x2828) #define ECLINE7 (SECURITY_BASE+0x282C) #define ETWIDX1 (SECURITY_BASE+0x2840) #define ETWL1 (SECURITY_BASE+0x2844) #define ETWIDX2 (SECURITY_BASE+0x2848) #define ETWL2 (SECURITY_BASE+0x284C) #define ETSPT10 (SECURITY_BASE+0x4000) #define ETSPT11 (SECURITY_BASE+0x4004) #define ETSPT12 (SECURITY_BASE+0x4008) #define ETSPT13 (SECURITY_BASE+0x400C) #define ETSPT2000 (SECURITY_BASE+0x6000) #define ETSPT2020 (SECURITY_BASE+0x6020) #define ETSPT2024 (SECURITY_BASE+0x6024) /* 8084_0000 - 8084_ffff: GPIO */ #define GPIO_OFFSET 0x040000 #define GPIO_BASE (EP93XX_APB_BASE|GPIO_OFFSET) #define GPIO_PADR HW_REG(GPIO_BASE+0x00) #define GPIO_PBDR HW_REG(GPIO_BASE+0x04) #define GPIO_PCDR HW_REG(GPIO_BASE+0x08) #define GPIO_PDDR HW_REG(GPIO_BASE+0x0C) #define GPIO_PADDR HW_REG(GPIO_BASE+0x10) #define GPIO_PBDDR HW_REG(GPIO_BASE+0x14) #define GPIO_PCDDR HW_REG(GPIO_BASE+0x18) #define GPIO_PDDDR HW_REG(GPIO_BASE+0x1C) #define GPIO_PEDR HW_REG(GPIO_BASE+0x20) #define GPIO_PEDDR HW_REG(GPIO_BASE+0x24) // #define 0x8084.0028 Reserved // #define 0x8084.002C Reserved #define GPIO_PFDR HW_REG(GPIO_BASE+0x30) #define GPIO_PFDDR HW_REG(GPIO_BASE+0x34) #define GPIO_PGDR HW_REG(GPIO_BASE+0x38) #define GPIO_PGDDR HW_REG(GPIO_BASE+0x3C) #define GPIO_PHDR HW_REG(GPIO_BASE+0x40) #define GPIO_PHDDR HW_REG(GPIO_BASE+0x44) // #define 0x8084.0048 RAZ RAZ #define GPIO_INTTYPE1 HW_REG(GPIO_BASE+0x4C) #define GPIO_INTTYPE2 HW_REG(GPIO_BASE+0x50) #define GPIO_FEOI HW_REG(GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */ #define GPIO_INTEN HW_REG(GPIO_BASE+0x58) #define GPIO_INTSTATUS HW_REG(GPIO_BASE+0x5C) #define GPIO_RAWINTSTASUS HW_REG(GPIO_BASE+0x60) #define GPIO_FDB HW_REG(GPIO_BASE+0x64) #define GPIO_PAPINDR HW_REG(GPIO_BASE+0x68) #define GPIO_PBPINDR HW_REG(GPIO_BASE+0x6C) #define GPIO_PCPINDR HW_REG(GPIO_BASE+0x70) #define GPIO_PDPINDR HW_REG(GPIO_BASE+0x74) #define GPIO_PEPINDR HW_REG(GPIO_BASE+0x78) #define GPIO_PFPINDR HW_REG(GPIO_BASE+0x7C) #define GPIO_PGPINDR HW_REG(GPIO_BASE+0x80) #define GPIO_PHPINDR HW_REG(GPIO_BASE+0x84) #define GPIO_AINTTYPE1 HW_REG(GPIO_BASE+0x90) /* */ #define GPIO_AINTTYPE2 HW_REG(GPIO_BASE+0x94) /* */ #define GPIO_AEOI HW_REG(GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */ #define GPIO_AINTEN HW_REG(GPIO_BASE+0x9C) /* */ #define GPIO_INTSTATUSA HW_REG(GPIO_BASE+0xA0) /* */ #define GPIO_RAWINTSTSTISA HW_REG(GPIO_BASE+0xA4) /* */ #define GPIO_ADB HW_REG(GPIO_BASE+0xA8) /* */ #define GPIO_BINTTYPE1 HW_REG(GPIO_BASE+0xAC) /* */ #define GPIO_BINTTYPE2 HW_REG(GPIO_BASE+0xB0) /* */ #define GPIO_BEOI HW_REG(GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */ #define GPIO_BINTEN HW_REG(GPIO_BASE+0xB8) /* */ #define GPIO_INTSTATUSB HW_REG(GPIO_BASE+0xBC) /* */ #define GPIO_RAWINTSTSTISB HW_REG(GPIO_BASE+0xC0) /* */ #define GPIO_BDB HW_REG(GPIO_BASE+0xC4) /* */ #define GPIO_EEDRIVE HW_REG(GPIO_BASE+0xC8) /* */ //#define Reserved (GPIO_BASE+0xCC) #define GPIO_TCR HW_REG(GPIO_BASE+0xD0) /* Test Registers */ #define GPIO_TISRA HW_REG(GPIO_BASE+0xD4) /* Test Registers */ #define GPIO_TISRB HW_REG(GPIO_BASE+0xD8) /* Test Registers */ #define GPIO_TISRC HW_REG(GPIO_BASE+0xDC) /* Test Registers */ #define GPIO_TISRD HW_REG(GPIO_BASE+0xE0) /* Test Registers */ #define GPIO_TISRE HW_REG(GPIO_BASE+0xE4) /* Test Registers */ #define GPIO_TISRF HW_REG(GPIO_BASE+0xE8) /* Test Registers */ #define GPIO_TISRG HW_REG(GPIO_BASE+0xEC) /* Test Registers */ #define GPIO_TISRH HW_REG(GPIO_BASE+0xF0) /* Test Registers */ #define GPIO_TCER HW_REG(GPIO_BASE+0xF4) /* Test Registers */ /* 8085_0000 - 8085_ffff: Reserved */ /* 8086_0000 - 8086_ffff: Reserved */ /* 8087_0000 - 8087_ffff: Reserved */ /* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */ #define AAC_OFFSET 0x080000 #define AAC_BASE (EP93XX_APB_BASE|AAC_OFFSET) #define AACDR1 (AAC_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1 */ #define AACRXCR1 (AAC_BASE+0x04) /* 8088.0004 R/W Control register for receive */ #define AACTXCR1 (AAC_BASE+0x08) /* 8088.0008 R/W Control register for transmit */ #define AACSR1 (AAC_BASE+0x0C) /* 8088.000C R Status register */ #define AACRISR1 (AAC_BASE+0x10) /* 8088.0010 R Raw interrupt status register */ #define AACISR1 (AAC_BASE+0x14) /* 8088.0014 R Interrupt Status */ #define AACIE1 (AAC_BASE+0x18) /* 8088.0018 R/W Interrupt Enable */ /* 8088.001C Reserved - RAZ */ #define AACDR2 (AAC_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */ #define AACRXCR2 (AAC_BASE+0x24) /* 8088.0024 R/W Control register for receive */ #define AACTXCR2 (AAC_BASE+0x28) /* 8088.0028 R/W Control register for transmit */ #define AACSR2 (AAC_BASE+0x2C) /* 8088.002C R Status register */ #define AACRISR2 (AAC_BASE+0x30) /* 8088.0030 R Raw interrupt status register */ #define AACISR2 (AAC_BASE+0x34) /* 8088.0034 R Interrupt Status */ #define AACIE2 (AAC_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ /* 8088.003C Reserved - RAZ */ #define AACDR3 (AAC_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */ #define AACRXCR3 (AAC_BASE+0x44) /* 8088.0044 R/W Control register for receive */ #define AACTXCR3 (AAC_BASE+0x48) /* 8088.0048 R/W Control register for transmit */ #define AACSR3 (AAC_BASE+0x4C) /* 8088.004C R Status register */ #define AACRISR3 (AAC_BASE+0x50) /* 8088.0050 R Raw interrupt status register */ #define AACISR3 (AAC_BASE+0x54) /* 8088.0054 R Interrupt Status */ #define AACIE3 (AAC_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ /* 8088.005C Reserved - RAZ */ #define AACDR4 (AAC_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */ #define AACRXCR4 (AAC_BASE+0x64) /* 8088.0064 R/W Control register for receive */ #define AACTXCR4 (AAC_BASE+0x68) /* 8088.0068 R/W Control register for transmit */ #define AACSR4 (AAC_BASE+0x6C) /* 8088.006C R Status register */ #define AACRISR4 (AAC_BASE+0x70) /* 8088.0070 R Raw interrupt status register */ #define AACISR4 (AAC_BASE+0x74) /* 8088.0074 R Interrupt Status */ #define AACIE4 (AAC_BASE+0x78) /* 8088.0078 R/W Interrupt Enable */ /* 8088.007C Reserved - RAZ */ #define AACS1DATA (AAC_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1 */ #define AACS2DATA (AAC_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2 */ #define AACS12DATA (AAC_BASE+0x88) /* 8088.0088 R/W Data received/transmitted on SLOT12 */ #define AACRGIS (AAC_BASE+0x8C) /* 8088.008C R/W Raw Global interrupt status register */ #define AACGIS (AAC_BASE+0x90) /* 8088.0090 R Global interrupt status register */ #define AACIM (AAC_BASE+0x94) /* 8088.0094 R/W Interrupt mask register */ #define AACEOI (AAC_BASE+0x98) /* 8088.0098 W Interrupt clear register */ #define AACGCR (AAC_BASE+0x9C) /* 8088.009C R/W Main Control register */ #define AACRESET (AAC_BASE+0xA0) /* 8088.00A0 R/W RESET control register. */ #define AACSYNC (AAC_BASE+0xA4) /* 8088.00A4 R/W SYNC control register. */ #define AACGCIS (AAC_BASE+0xA8) /* 8088.00A8 R Global chan FIFO int status register */ /* 8089_0000 - 8089_ffff: Reserved */ /* 808A_0000 - 808A_ffff: SSP - (SPI) */ #define SSP_OFFSET 0x0A0000 #define SSP_BASE (EP93XX_APB_BASE|SSP_OFFSET) ///#define SSPCR0 HW_REG(SSP_BASE+0x00) /* 0x808A.0000 R/W Control register 0 */ ///#define SSPCR1 HW_REG(SSP_BASE+0x04) /* 0x808A.0004 R/W Control register 1. */ ///#define SSPIIR HW_REG(SSP_BASE+0x08) /* 0x808A.0008 R Interrupt ID register */ ///#define SSPICR HW_REG(SSP_BASE+0x08) /* 0x808A.0008 W Interrupt clear register */ ///#define SSPDR HW_REG(SSP_BASE+0x0C) /* 0x808A.000C R/W Receive FIFO (Read) */ /// /* Transmit FIFO (Write) */ ///#define SSPCPSR HW_REG(SSP_BASE+0x10) /* 0x808A.0010 R/W Clock prescale register */ ///#define SSPSR HW_REG(SSP_BASE+0x14) /* 0x808A.0014 R Status register */ /*808B_0000 - 808B_ffff: IrDA */ #define IRDA_OFFSET 0x0B0000 #define IRDA_BASE (EP93XX_APB_BASE|IRDA_OFFSET) //#define IRENABLE (IRDA_BASE+0x00) //#define IRCON (IRDA_BASE+0x04) //#define IRAMV (IRDA_BASE+0x08) //#define IRFLAG (IRDA_BASE+0x0C) //#define IRDATA (IRDA_BASE+0x10) //#define IRDATATAIL1 (IRDA_BASE+0x14) //#define IRDATATAIL2 (IRDA_BASE+0x18) //#define IRDATATAIL3 (IRDA_BASE+0x1c) //#define IRRIB (IRDA_BASE+0x20) //#define IRTR0 (IRDA_BASE+0x24) //#define IRDMACR (IRDA_BASE+0x28) //#define SIRTR0 (IRDA_BASE+0x30) //#define MISR (IRDA_BASE+0x80) //#define MIMR (IRDA_BASE+0x84) //#define MIIR (IRDA_BASE+0x88) //#define MITR0 (IRDA_BASE+0x90) //#define MITR1 (IRDA_BASE+0x94) //#define MITR2 (IRDA_BASE+0x98) //#define MITR3 (IRDA_BASE+0x9c) //#define MITR4 (IRDA_BASE+0xa0) //#define FISR (IRDA_BASE+0x180) //#define FIMR (IRDA_BASE+0x184) //#define FIIR (IRDA_BASE+0x188) //#define FITR0 (IRDA_BASE+0x190) //#define FITR1 (IRDA_BASE+0x194) //#define FITR2 (IRDA_BASE+0x198) //#define FITR3 (IRDA_BASE+0x19c) //#define FITR4 (IRDA_BASE+0x1a0) /* 808C_0000 - 808C_ffff: UART1 */ #define UART1_OFFSET 0x0C0000 #define UART1_BASE (EP93XX_APB_BASE|UART1_OFFSET) #define UART1DR (UART1_BASE+0x000) #define UART1RSR (UART1_BASE+0x004) /* Read */ #define UART1ECR (UART1_BASE+0x004) /* Write */ #define UART1CR_H (UART1_BASE+0x008) #define UART1CR_M (UART1_BASE+0x00C) #define UART1CR_L (UART1_BASE+0x010) #define UART1CR (UART1_BASE+0x014) #define UART1FR (UART1_BASE+0x018) #define UART1IIR (UART1_BASE+0x01C) /* Read */ #define UART1ICR (UART1_BASE+0x01C) /* Write */ #define UART1ILPR (UART1_BASE+0x020) #define UART1DMACR (UART1_BASE+0x028) #define UART1TMR (UART1_BASE+0x084) #define UART1MCR (UART1_BASE+0x100) /* Modem Control Reg */ #define UART1MSR (UART1_BASE+0x104) /* Modem Status Reg */ #define UART1TCR (UART1_BASE+0x108) #define UART1TISR (UART1_BASE+0x10C) #define UART1TOCR (UART1_BASE+0x110) #define HDLC1CR (UART1_BASE+0x20c) #define HDLC1AMV (UART1_BASE+0x210) #define HDLC1AMSK (UART1_BASE+0x214) #define HDLC1RIB (UART1_BASE+0x218) #define HDLC1SR (UART1_BASE+0x21c) /* 808d_0000 - 808d_ffff: UART2 */ #define UART2_OFFSET 0x0D0000 #define UART2_BASE (EP93XX_APB_BASE|UART2_OFFSET) #define UART2DR (UART2_BASE+0x00) #define UART2RSR (UART2_BASE+0x04) /* Read */ #define UART2ECR (UART2_BASE+0x04) /* Write */ #define UART2CR_H (UART2_BASE+0x08) #define UART2CR_M (UART2_BASE+0x0C) #define UART2CR_L (UART2_BASE+0x10) #define UART2CR (UART2_BASE+0x14) #define UART2FR (UART2_BASE+0x18) #define UART2IIR (UART2_BASE+0x1C) /* Read */ #define UART2ICR (UART2_BASE+0x1C) /* Write */ #define UART2ILPR (UART2_BASE+0x20) #define UART2DMACR (UART2_BASE+0x28) #define UART2TMR (UART2_BASE+0x84) /* 808e_0000 - 808e_ffff: UART3 */ #define UART3_OFFSET 0x0E0000 #define UART3_BASE (EP93XX_APB_BASE|UART3_OFFSET) #define UART3DR (UART3_BASE+0x00) #define UART3RSR (UART3_BASE+0x04) /* Read */ #define UART3ECR (UART3_BASE+0x04) /* Write */ #define UART3CR_H (UART3_BASE+0x08) #define UART3CR_M (UART3_BASE+0x0C) #define UART3CR_L (UART3_BASE+0x10) #define UART3CR (UART3_BASE+0x14) #define UART3FR (UART3_BASE+0x18) #define UART3IIR (UART3_BASE+0x1C) /* Read */ #define UART3ICR (UART3_BASE+0x1C) /* Write */ #define UART3ILPR (UART3_BASE+0x20) #define UART3DMACR (UART3_BASE+0x28) #define UART3TCR (UART3_BASE+0x80) #define UART3TISR (UART3_BASE+0x88) #define UART3TOCR (UART3_BASE+0x8C) #define UART3TMR (UART3_BASE+0x84) #define UART3MCR (UART3_BASE+0x100) /* Modem Control Reg */ #define UART3MSR (UART3_BASE+0x104) /* Modem Status Reg */ #define UART3HDLCCR (UART3_BASE+0x20C) /* HDLC Registers */ #define UART3HDLCAMV (UART3_BASE+0x210) /* HDLC Registers */ #define UART3HDLCAMSK (UART3_BASE+0x214) /* HDLC Registers */ #define UART3HDLCCRIB (UART3_BASE+0x218) /* HDLC Registers */ #define UART3HDLCSR (UART3_BASE+0x21C) /* HDLC Registers */ /* 808f_0000 - 808f_ffff: KEY Matrix */ #define KEY_OFFSET 0x0F0000 #define KEY_BASE (EP93XX_APB_BASE|KEY_OFFSET) //#define SCANINIT (KEY_BASE+0x00) //#define DIAG (KEY_BASE+0x04) //#define KEYS_REG (KEY_BASE+0x08) //#define KEY_TCR (KEY_BASE+0x10) //#define KEY_TISR (KEY_BASE+0x14) //#define KEY_TOCR (KEY_BASE+0x18) //#define KEY_TCER00 (KEY_BASE+0x40) //#define KEY_TCER01 (KEY_BASE+0x44) //#define KEY_TCER02 (KEY_BASE+0x48) //#define KEY_TCER03 (KEY_BASE+0x4C) //#define KEY_TCER04 (KEY_BASE+0x50) //#define KEY_TCER05 (KEY_BASE+0x54) //#define KEY_TCER06 (KEY_BASE+0x58) //#define KEY_TCER07 (KEY_BASE+0x5C) //#define KEY_TCER08 (KEY_BASE+0x60) //#define KEY_TCER09 (KEY_BASE+0x64) //#define KEY_TCER10 (KEY_BASE+0x68) //#define KEY_TCER11 (KEY_BASE+0x6C) //#define KEY_TCER12 (KEY_BASE+0x70) //#define KEY_TCER13 (KEY_BASE+0x74) //#define KEY_TCER14 (KEY_BASE+0x78) //#define KEY_TCER15 (KEY_BASE+0x7C) /* 8090_0000 - 8090_ffff: Analog Resistive Touchscreen */ #define TOUCH_OFFSET 0x100000 #define TOUCH_BASE (EP93XX_APB_BASE|TOUCH_OFFSET) //#define TSSETUP (TOUCH_BASE+0x00) /* R/W touchscreen controller setup control register. */ //#define TSXYMAXMIN (TOUCH_BASE+0x04) /* R/W touchscreen controller max/min register. */ //#define TSXYRESULT (TOUCH_BASE+0x08) /* R touchscreen controller result register. */ //#define TSDISCHARGE (TOUCH_BASE+0x0C) /* LOCKED R/W touchscreen Switch Matrix control register. */ //#define TSXSAMPLE (TOUCH_BASE+0x10) /* LOCKED R/W touchscreen Switch Matrix control register. */ //#define TSYSAMPLE (TOUCH_BASE+0x14) /* LOCKED R/W touchscreen Switch Matrix control register. */ //#define TSDIRECT (TOUCH_BASE+0x18) /* LOCKED R/W touchscreen Switch Matrix control register. */ //#define TSDETECT (TOUCH_BASE+0x1C) /* LOCKED R/W touchscreen Switch Matrix control register. */ //#define TSSWLOCK (TOUCH_BASE+0x20) /* NA R/W touchscreen software lock register. */ //#define TSSETUP2 (TOUCH_BASE+0x24) /* R/W touchscreen setup control register #2. */ /* 8091_0000 - 8091_ffff: PWM */ #define PWM_OFFSET 0x110000 #define PWM_BASE (EP93XX_APB_BASE|PWM_OFFSET) #define PWM0_TC (PWM_BASE+0x00) /* 80910000 R/W PWM_0 Terminal Count */ #define PWM0_DC (PWM_BASE+0x04) /* 80910004 R/W PWM_0 Duty Cycle */ #define PWM0_EN (PWM_BASE+0x08) /* 80910008 R/W PWM_0 Enable */ #define PWM0_INV (PWM_BASE+0x0C) /* 8091000C R/W PWM_0 Invert */ #define PWM0_SYNC (PWM_BASE+0x10) /* 80910010 R/W PWM_0 Synchronous */ #define PWM1_TC (PWM_BASE+0x20) /* 80910020 R/W PWM_1 Terminal Count */ #define PWM1_DC (PWM_BASE+0x24) /* 80910024 R/W PWM_1 Duty Cycle */ #define PWM1_EN (PWM_BASE+0x28) /* 80910028 R/W PWM_1 Enable */ #define PWM1_INV (PWM_BASE+0x2C) /* 8091002C R/W PWM_1 Invert */ #define PWM1_SYNC (PWM_BASE+0x30) /* 80910030 R/W PWM_1 Synchronous */ /* 8092_0000 - 8092_ffff: RTC */ #define RTC_OFFSET 0x120000 #define RTC_BASE (EP93XX_APB_BASE|RTC_OFFSET) #define RTCDR (RTC_BASE+0x00) #define RTCMR (RTC_BASE+0x04) #define RTCSTAT (RTC_BASE+0x08) /* Read */ #define RTCEOI (RTC_BASE+0x08) /* Write */ #define RTCLR (RTC_BASE+0x0C) #define RTCCR (RTC_BASE+0x10) #define RTCSCOMP (RTC_BASE+0x108) /* 8093_0000 - 8093_ffff: CSC/Syscon PLL, clock control, & misc. stuff */ #define SYSCON_OFFSET 0x130000 #define SYSCON_BASE (EP93XX_APB_BASE|SYSCON_OFFSET) #define SYSCON_PWRSR (SYSCON_BASE+0x0000) #define SYSCON_PWRCNT (SYSCON_BASE+0x0004) #define SYSCON_HALT (SYSCON_BASE+0x0008) #define SYSCON_STBY (SYSCON_BASE+0x000c) #define SYSCON_BLEOI (SYSCON_BASE+0x0010) #define SYSCON_MCEOI (SYSCON_BASE+0x0014) #define SYSCON_TEOI (SYSCON_BASE+0x0018) #define SYSCON_STFCLR (SYSCON_BASE+0x001c) #define SYSCON_CLKSET1 (SYSCON_BASE+0x0020) #define SYSCON_CLKSET2 (SYSCON_BASE+0x0024) #define SYSCON_RESV00 (SYSCON_BASE+0x0028) #define SYSCON_RESV01 (SYSCON_BASE+0x002c) #define SYSCON_RESV02 (SYSCON_BASE+0x0030) #define SYSCON_RESV03 (SYSCON_BASE+0x0034) #define SYSCON_RESV04 (SYSCON_BASE+0x0038) #define SYSCON_RESV05 (SYSCON_BASE+0x003c) #define SYSCON_SCRREG0 (SYSCON_BASE+0x0040) #define SYSCON_SCRREG1 (SYSCON_BASE+0x0044) #define SYSCON_CLKTEST (SYSCON_BASE+0x0048) #define SYSCON_USBRESET (SYSCON_BASE+0x004c) #define SYSCON_APBWAIT (SYSCON_BASE+0x0050) #define SYSCON_BMAR (SYSCON_BASE+0x0054) #define SYSCON_BOOTCLR (SYSCON_BASE+0x0058) #define SYSCON_DEVCFG (SYSCON_BASE+0x0080) #define SYSCON_VIDDIV (SYSCON_BASE+0x0084) #define SYSCON_MIRDIV (SYSCON_BASE+0x0088) #define SYSCON_I2SDIV (SYSCON_BASE+0x008C) #define SYSCON_KTDIV (SYSCON_BASE+0x0090) #define SYSCON_CHIPID (SYSCON_BASE+0x0094) #define SYSCON_TSTCR (SYSCON_BASE+0x0098) #define SYSCON_SYSCFG (SYSCON_BASE+0x009C) #define CSC_SYSCON_SWLOCK (SYSCON_BASE+0x00C0) #define SYSCON_DEVCFG_KEYS 0x00000002 #define SYSCON_DEVCFG_RasOnP3 0x00000010 #define SYSCON_DEVCFG_GONK 0x08000000 #define SYSCON_KTDIV_KEN 0x00008000 /* 8094_0000 - 8094_ffff: Watchdog */ #define WATCHDOG_OFFSET 0x140000 #define WATCHDOG_BASE (EP93XX_APB_BASE|WATCHDOG_OFFSET) #define WATCHDOG (WATCHDOG_BASE+0x00) #define WDSTATUS (WATCHDOG_BASE+0x04) #define WD_TCR (WATCHDOG_BASE+0x08) #define WD_TISR (WATCHDOG_BASE+0x0C) #define WDTOCR (WATCHDOG_BASE+0x10) /* 8095_0000 - 87ff_ffff: Reserved APB space */ #endif /* __ASM_ARCH_HARDWARE_H */ ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_ps7500.c�������������������������������������������������0000644�0001750�0000144�00000047502�11006120657�020333� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_ps7500.c - define machine ps7500 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 3/2005 init this file. * add machine ps7500's function. Most taken from original armio.c. * include: ps7500_mach_init, ps7500_io_do_cycle * ps7500_io_read_word, ps7500_io_write_word * Most taken from skyeye_mach_ep7312.c * */ #include "armdefs.h" #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include "ps7500.h" /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" extern int skyeye_net_maxfd; extern int skyeye_net_on; #define TC_DIVISOR (32) /* Set your BogoMips here :) */ #define FLYBACK_DIVISOR (1000000) #define SOMETIMES_DIVISOR (100) #define NET_ADDR_START 0x03010C00 #define NET_ADDR_END (NET_ADDR_START + 0x00000400) #define IOMD_ADDR_START 0x03200000 #define IOMD_ADDR_END (IOMD_ADDR_START + 0x00001000) #define VIDEO_ADDR 0x03400000 //zzc:2005-1-1 #ifdef __CYGWIN__ #include <sys/time.h> #endif #define PC (state->Reg[15]) #define DEBUG 1 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr,##a) #else #define DBG_PRINT(a...) #endif /*Internal IO Register*/ typedef struct ps7500_io { ARMword flyback; ARMword prescale; ARMword sometimes; ARMbyte irq[5], irqmask[5]; ARMbyte fiq[1], fiqmask[1]; ARMbyte iocr_write; ARMbyte iocr_read; ARMword tcd_reload[2]; /* Timer load register */ ARMword tcd[2]; /* Timer data */ int tc_prescale; /* Timer prescale */ ARMword vidstart, vidend, vidinit; ARMbyte vidcr; ARMword lcd_is_enable; ARMword lcd_addr_begin; ARMword lcd_addr_end; ARMword ts_int; ARMword ts_is_enable; ARMword ts_addr_begin; ARMbyte net_int[5]; ARMword net_flag; ARMbyte kb_stat; ARMbyte kb_data; ARMbyte kb_queued[4096]; ARMword kb_count; ARMbyte kb_delay; ARMbyte lcd_started; } ps7500_io_t; static ps7500_io_t ps7500_io; #define io ps7500_io // Macros for setting/clearing interrupt bits // I used an array since there were more than 32 interrupt sources // and so it didn't fit in a ARMword. Thus, the network interrupt // source must be less than 32. #define SET_BIT(v, x) (v)[(x) / 8] |= (1 << ((x) % 8)) #define CLR_BIT(v, x) (v)[(x) / 8] &= ~(1 << ((x) % 8)) #define SET_IRQ(x) SET_BIT(io.irq, x); ps7500_update_int(state) #define CLR_IRQ(x) CLR_BIT(io.irq, x); ps7500_update_int(state) #define SET_IRQMASK(x) SET_BIT(io.irqmask); ps7500_update_int(state) #define CLR_IRQMASK(x) CLR_BIT(io.irqmask); ps7500_update_int(state) #define SET_FIQ(x) SET_BIT(io.fiq, x); ps7500_update_int(state) #define CLR_FIQ(x) CLR_BIT(io.fiq, x); ps7500_update_int(state) #define SET_FIQMASK(x) SET_BIT(io.fiqmask, x); ps7500_update_int(state) #define CLR_FIQMASK(x) CLR_BIT(io.fiqmask, x); ps7500_update_int(state) // Indexes into IRQ array. This must match IRQ numbers in ps7500.h #define IRQA 0 #define IRQB 1 #define IRQDMA 2 #define IRQC 3 #define IRQD 4 #define FIQ 0 extern ARMul_State * state; ARMbyte ps7500_getcode(ARMbyte); static void ps7500_update_int(ARMul_State *state) { int i; //if (io.irq[IRQB] & io.net_int[IRQB]) { // printf("Network interrupt set\n"); // for (i=0; i < 5; i++) { // printf("IRQ[%d] %02x IRQMASK[%d] %02x\n", // i, io.irq[i], i, io.irqmask[i]); // } //} state->NfiqSig = (io.fiq[FIQ] & io.fiqmask[FIQ]) ? LOW : HIGH; state->NirqSig = ((io.irq[IRQA] & io.irqmask[IRQA]) || (io.irq[IRQB] & io.irqmask[IRQB]) || (io.irq[IRQC] & io.irqmask[IRQC]) || (io.irq[IRQD] & io.irqmask[IRQD]) || (io.irq[IRQDMA] & io.irqmask[IRQDMA])) ? LOW : HIGH; } /* * added some functions for device simulation by ksh * */ static void ps7500_set_intr (u32 interrupt) { //io.irq |= (1 << interrupt); SET_IRQ(interrupt); } static int ps7500_pending_intr (u32 interrupt) { return io.irq[interrupt]; } static void ps7500_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; state->NfiqSig = (io.fiq[FIQ] & io.fiqmask[FIQ]) ? LOW : HIGH; state->NirqSig = ((io.irq[IRQA] & io.irqmask[IRQA]) || (io.irq[IRQB] & io.irqmask[IRQB]) || (io.irq[IRQC] & io.irqmask[IRQC]) || (io.irq[IRQD] & io.irqmask[IRQD]) || (io.irq[IRQDMA] & io.irqmask[IRQDMA])) ? LOW : HIGH; } static void ps7500_io_reset(ARMul_State *state) { int i; for (i=0; i < 4; i++) io.irqmask[i] = io.irq[i] = 0; io.fiqmask[FIQ] = io.fiq[FIQ] = 0; io.irq[IRQA] = 0x80; // SWI bit always true io.tcd[0] = io.tcd[1] = 0xffff; io.tcd_reload[0] = io.tcd_reload[1] = 0xffff; io.tc_prescale = TC_DIVISOR; io.lcd_addr_begin =0x10000000; io.lcd_addr_end =0x10004000; SET_BIT(io.net_int, IRQ_INT5); // Network interrupt bit printf("netint %02x\n", io.net_int[IRQB]); io.sometimes = SOMETIMES_DIVISOR; io.lcd_started = 0; //state->Exception = TRUE; } ps7500_kb_queue(ARMul_State *state, ARMbyte c) { io.kb_queued[io.kb_count++] = c; if ((io.kb_stat & (KB_TXB | KB_RXF)) == 0) ps7500_kb_next(state); } ps7500_kb_next(ARMul_State *state) { int i; int p; if (io.kb_count) { io.kb_data = io.kb_queued[0]; p = 0; for (i=0; i < 8; i++) if (io.kb_data & (1 << i)) p++; if (p % 2) io.kb_stat &= ~KB_RXP; else io.kb_stat |= KB_RXP; io.kb_stat |= KB_RXF; SET_IRQ(IRQ_KEYBOARDRX); io.kb_count--; if (io.kb_count) for (i=0; i < io.kb_count; i++) io.kb_queued[i] = io.kb_queued[i+1]; } } void ps7500_uart_cycle(ARMul_State *state) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf, c; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { printf("read something %02x\n", buf); c = ps7500_getcode(buf); ps7500_kb_queue(state, c); ps7500_kb_queue(state, 0xf0); ps7500_kb_queue(state, c); } } void ps7500_io_do_cycle(ARMul_State *state) { int t; // Timers io.tc_prescale--; if (io.tc_prescale < 0) { io.tc_prescale = TC_DIVISOR; // 64 Mhz -> 2 Mhz for (t=0; t < 2; t++) { if (io.tcd[t] == 0) { io.tcd[t] = io.tcd_reload[t]; //DBG_PRINT("Timer %d interrupt\n", t); SET_IRQ(t ? IRQ_TIMER1 : IRQ_TIMER0); } else { io.tcd[t]--; } } } io.iocr_write |= 0x80; // Flyback bit always true // VSYNC pulse interrupt if (io.flyback == 0) { io.flyback = FLYBACK_DIVISOR; //DBG_PRINT("Flyback interrupt\n"); SET_IRQ(IRQ_VSYNCPULSE); } else { io.flyback--; } // Make sure SWI interrupt bit stays set if ((io.irq[IRQA] & 0x80) == 0) { io.irq[IRQA] |= 0x80; ps7500_update_int(state); } // Keyboard if (io.kb_delay != 0) { io.kb_delay--; if (io.kb_delay == 0) { io.kb_stat &= ~KB_TXB; io.kb_stat |= KB_TXE; SET_IRQ(IRQ_KEYBOARDTX); ps7500_kb_next(state); } } if (io.sometimes == 0) { ps7500_uart_cycle(state); io.sometimes = SOMETIMES_DIVISOR; } else { io.sometimes--; } } ARMword ps7500_io_read_byte(ARMul_State *state, ARMword addr) { ARMword data = 0; ARMword offset; if ((addr >= IOMD_ADDR_START) && (addr < IOMD_ADDR_END)) { offset = addr - IOMD_ADDR_START; switch (offset) { case IOMD_CONTROL: data = io.iocr_write | io.iocr_read; //DBG_PRINT("@0x%08x: IOCR(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQMASKA: data = io.irqmask[IRQA]; //DBG_PRINT("@0x%08x: IRQMASKA(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQSTATA: data = io.irq[IRQA]; //DBG_PRINT("@0x%08x: IRQSTATA(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQREQA: data = io.irq[IRQA] & io.irqmask[IRQA]; //DBG_PRINT("@0x%08x: IRQREQA(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQMASKB: data = io.irqmask[IRQB]; //DBG_PRINT("@0x%08x: IRQMASKB(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQSTATB: data = io.irq[IRQB]; //DBG_PRINT("@0x%08x: IRQSTATB(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQREQB: data = io.irq[IRQB] & io.irqmask[IRQB]; //DBG_PRINT("@0x%08x: IRQREQB(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQMASKC: data = io.irqmask[IRQC]; //DBG_PRINT("@0x%08x: IRQMASKC(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQSTATC: data = io.irq[IRQC]; //DBG_PRINT("@0x%08x: IRQSTATC(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQREQC: data = io.irq[IRQC] & io.irqmask[IRQC]; //DBG_PRINT("@0x%08x: IRQREQC(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQMASKD: data = io.irqmask[IRQD]; //DBG_PRINT("@0x%08x: IRQMASKD(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQSTATD: data = io.irq[IRQD]; //DBG_PRINT("@0x%08x: IRQSTATD(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_IRQREQD: data = io.irq[IRQD] & io.irqmask[IRQD]; //DBG_PRINT("@0x%08x: IRQREQD(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_DMAMASK: data = io.irqmask[IRQDMA]; //DBG_PRINT("@0x%08x: DMAMASK(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_DMASTAT: data = io.irq[IRQDMA]; //DBG_PRINT("@0x%08x: DMASTAT(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_DMAREQ: data = io.irq[IRQDMA] & io.irqmask[IRQDMA]; //DBG_PRINT("@0x%08x: DMAREQ(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_FIQSTAT: data = io.fiq[FIQ]; //DBG_PRINT("@0x%08x: FIQSTAT(0x%08x) -> %02x\n", // PC - 8, addr, data ); break; case IOMD_FIQREQ: data = io.fiqmask[FIQ] & io.fiqmask[FIQ]; //DBG_PRINT("@0x%08x: FIQREQ(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_KCTRL: data = io.kb_stat; //DBG_PRINT("@0x%08x: KCTRL(0x%08x) -> %02x\n", // PC - 8, addr, data); break; case IOMD_KARTRX: io.kb_stat &= ~KB_RXF; CLR_IRQ(IRQ_KEYBOARDRX); data = io.kb_data; ps7500_kb_next(state); //DBG_PRINT("@0x%08x: KARTRX(0x%08x) -> %02x\n", // PC - 8, addr, data); break; } return data; } if ((addr >= NET_ADDR_START) && (addr < NET_ADDR_END)) { offset = (addr - NET_ADDR_START) >> 2; DBG_PRINT("@0x%08x: Ethernet reg %03x read byte start\n", PC - 8, offset); //data = nic_read(0, state, offset); DBG_PRINT("@0x%08x: Ethernet reg %03x read byte 0x%02x\n", PC - 8, offset, data); return data; } DBG_PRINT("@0x%08x: io_read_byte(0x%08x) -> 0x%02x\n", PC - 8, addr, data); return data; } ARMword ps7500_io_read_halfword(ARMul_State *state, ARMword addr) { DBG_PRINT("SKYEYE: ps7500_io_read_halfword error\n"); } FILE *fo = NULL; #define RAMSTART 0x10000000 #define BANKOFFSET 0x04000000 #define BANKSIZE 0x00400000 ARMword ps7500_io_read_word(ARMul_State *state, ARMword addr) { ARMword data = 0; ARMword data2; ARMword b; ARMword i; if (fo == NULL) { DBG_PRINT("Dumping memory\n"); fo = fopen("mem.dump", "w"); for (b=0; b < 4; b++) { for (i=0; i < BANKSIZE; i = i + 4) { data2 = real_read_word(state, RAMSTART + (b * BANKOFFSET) + i); fwrite(&data2, 4, 1, fo); } } fclose(fo); DBG_PRINT("Done\n"); } DBG_PRINT("io_read_word(0x%08x) = 0x%08x\n", addr, data); return data; } void ps7500_io_write_byte(ARMul_State *state, ARMword addr, ARMword data) { ARMword offset; if ((addr >= IOMD_ADDR_START) && (addr < IOMD_ADDR_END)) { offset = addr - IOMD_ADDR_START; switch (offset) { case IOMD_CONTROL: io.iocr_write = data & 0x03; DBG_PRINT("@0x%08x: IOCR(0x%08x) <- 0x%02x\n", PC - 8, addr, data); break; case IOMD_IRQMASKA: io.irqmask[IRQA] = data; ps7500_update_int(state); //DBG_PRINT("@0x%08x: IRQMASKA(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_IRQCLRA: io.irq[IRQA] &= ~data; ps7500_update_int(state); //DBG_PRINT("@0x%08x: IRQCLRA(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_IRQMASKB: io.irqmask[IRQB]= data; ps7500_update_int(state); //DBG_PRINT("@0x%08x: IRQMSKB(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_IRQMASKC: io.irqmask[IRQC] = data; ps7500_update_int(state); //DBG_PRINT("@0x%08x: IRQMASKC(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_IRQMASKD: io.irqmask[IRQD] = data; ps7500_update_int(state); //DBG_PRINT("@0x%08x: IRQMASKD(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_DMAMASK: io.irqmask[IRQDMA] = data; ps7500_update_int(state); //DBG_PRINT("@0x%08x: DMAMSK(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_FIQMASK: io.fiqmask[FIQ] = data; ps7500_update_int(state); //DBG_PRINT("@0x%08x: FIQMSK(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_CLKCTL: //DBG_PRINT("@0x%08x: CLKCTL(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_T0CNTL: io.tcd_reload[0] = (io.tcd_reload[0] & 0xff00) | data; //DBG_PRINT("@0x%08x: T0CNTL(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_T0CNTH: io.tcd_reload[0] = (io.tcd_reload[0] & 0x00ff) | data; //DBG_PRINT("T0CNTH(0x%08x) <- 0x%02x\n", PC - 8, addr, data); break; case IOMD_T0GO: io.tcd[0] = io.tcd_reload[0]; //DBG_PRINT("@0x%08x: T0GO(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_T1CNTL: io.tcd_reload[1] = (io.tcd_reload[1] & 0xff00) | data; DBG_PRINT("@0x%08x: T1CNTL(0x%08x) <- 0x%02x\n", PC - 8, addr, data); break; case IOMD_T1CNTH: io.tcd_reload[1] = (io.tcd_reload[1] & 0x00ff) | data; //DBG_PRINT("T1CNTH(0x%08x) <- 0x%02x\n", PC - 8, addr, data); break; case IOMD_T1GO: io.tcd[1] = io.tcd_reload[1]; //DBG_PRINT("@0x%08x: T1GO(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_ROMCR0: //DBG_PRINT("@0x%08x: ROMCR0(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_ROMCR1: //DBG_PRINT("@0x%08x: ROMCR1(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_DRAMCR: //DBG_PRINT("@0x%08x: DRAMCR(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_VIDCR: DBG_PRINT("@0x%08x: VIDCR(0x%08x) <- 0x%02x\n", PC - 8, addr, data); if ((data & 0x20) && (io.lcd_started == 0)) { DBG_PRINT("Start LCD\n"); //lcd_enable(state, 640, 480, 8); io.lcd_started = 1; } io.vidcr = data; break; case IOMD_KCTRL: if (data & 0x08) // Enable io.kb_stat = KB_SKC | KB_SKD | KB_ENA | KB_TXE; else // Disable io.kb_stat = 0; //DBG_PRINT("@0x%08x: KCTRL(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); break; case IOMD_KARTTX: //DBG_PRINT("@0x%08x: KARTTX(0x%08x) <- 0x%02x\n", // PC - 8, addr, data); // Send a character to PS2 keyboard. // This is a keyboard command. // Clear TXEmpty, clear TX interrupt, set TXBusy // Queue an ACK (0xfa) response // If command is RESET (0xff), then // also queue a reset done (0xaa) response io.kb_stat &= ~ KB_TXE; CLR_IRQ(IRQ_KEYBOARDTX); io.kb_stat |= KB_TXB ; io.kb_delay = 10; ps7500_kb_queue(state, 0xfa); if (data == 0xff) ps7500_kb_queue(state, 0xaa); break; default: DBG_PRINT("@0x%08x: io_write_byte(0x%08x) <- 0x%02x\n", PC - 8, addr, data); break; } return; } if (addr == VIDEO_ADDR) { DBG_PRINT("@0x%08x: Video register write 0x%08x\n", PC - 8, data); return; } if ((addr >= NET_ADDR_START) && (addr <= NET_ADDR_END)) { offset = (addr - NET_ADDR_START) >> 2; DBG_PRINT("@0x%08x: Ethernet reg %03x write byte 0x%02x\n", PC - 8, offset, data); //nic_write(0, state, offset, data); return; } DBG_PRINT("@0x%08x: io_write_byte(0x%08x) <- 0x%08x\n", PC - 8, addr, data); } void ps7500_io_write_halfword(ARMul_State *state, ARMword addr, ARMword data) { DBG_PRINT("io_write_halfword(0x%08x) <- 0x%08x\n", addr, data); } void ps7500_io_write_word(ARMul_State *state, ARMword addr, ARMword data) { ARMword offset; if ((addr >= IOMD_ADDR_START) && ( addr < IOMD_ADDR_END)) { offset = addr - IOMD_ADDR_START; switch (offset) { case IOMD_CURSINIT: DBG_PRINT("CURSINIT <- 0x%08x\n", data); break; case IOMD_VIDEND: io.vidend = data; DBG_PRINT("VIDEND <- 0x%08x\n", data); break; case IOMD_VIDSTART: io.vidstart = data; io.lcd_addr_begin = data; DBG_PRINT("VIDSTART <- 0x%08x\n", data); break; case IOMD_VIDINIT: io.vidinit = data; DBG_PRINT("VIDINIT <- 0x%08x\n", data); break; default: DBG_PRINT("io_write_word(0x%08x) <- 0x%08x\n", addr - 0x03200000, data); break; } return; } if (addr == VIDEO_ADDR) { DBG_PRINT("Video register write <- 0x%08x\n", data); return; } // Network data sometimes written in 16 bit pieces if ((addr >= NET_ADDR_START) && (addr < NET_ADDR_END)) { offset = (addr - NET_ADDR_START) >> 2; if (offset != 0x10) { printf("Net word write at bad address\n"); exit(1); } DBG_PRINT("Net data write <- 0x%04x\n", data & 0xffff); //nic_write(0, state, offset, data & 0xff); //nic_write(0, state, offset, (data >> 8) & 0xff); return; } DBG_PRINT("io_write_word(0x%08x) <- 0x%08x\n", addr, data); } void ps7500_mach_init(ARMul_State *state, machine_config_t *this_mach) { ARMul_SelectProcessor(state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; this_mach->mach_io_do_cycle = ps7500_io_do_cycle; this_mach->mach_io_reset = ps7500_io_reset; this_mach->mach_io_read_byte = ps7500_io_read_byte; this_mach->mach_io_write_byte = ps7500_io_write_byte; this_mach->mach_io_read_halfword = ps7500_io_read_halfword; this_mach->mach_io_write_halfword = ps7500_io_write_halfword; this_mach->mach_io_read_word = ps7500_io_read_word; this_mach->mach_io_write_word = ps7500_io_write_word; this_mach->mach_update_int = ps7500_update_int; this_mach->mach_set_intr = ps7500_set_intr; this_mach->mach_pending_intr = ps7500_pending_intr; this_mach->mach_update_intr = ps7500_update_intr; /* state->mach_io.lcd_is_enable = (ARMword *)&io.lcd_is_enable; state->mach_io.lcd_addr_begin = (ARMword *)&io.lcd_addr_begin; state->mach_io.lcd_addr_end = (ARMword *)&io.lcd_addr_end; */ state->mach_io.ts_int =(ARMword *)&io.ts_int; state->mach_io.ts_is_enable =(ARMword *)&io.ts_is_enable; state->mach_io.ts_addr_begin =(ARMword *)&io.ts_addr_begin; state->mach_io.instr =(ARMword *)io.irq; state->mach_io.net_int =(ARMword *)io.net_int; state->mach_io.net_flag =(ARMword *)&io.net_flag; state->Reg[1] = 14; printf("%02x %02x\n", state->mach_io.instr, state->mach_io.net_int); } ARMbyte scancode_alpha[] = { 0x1c, 0x32, 0x21, 0x23, 0x24, 0x2b, 0x34, 0x33, 0x43, 0x3b, 0x42, 0x4b, 0x3a, 0x31, 0x44, 0x4d, 0x15, 0x2d, 0x1b, 0x2c, 0x3c, 0x2a, 0x1d, 0x22, 0x35, 0x1a}; ARMbyte scancode_number[] = { 0x45, 0x16, 0x1e, 0x26, 0x25, 0x2e, 0x36, 0x3d, 0x3e, 0x46}; ARMbyte ps7500_getcode(ARMbyte c) { if ((c >= 'a') && (c <= 'z')) return scancode_alpha[c - 'a']; if ((c >= '0') && (c <= '9')) return scancode_number[c - '0']; if (c == '\n') return 0x5a; if (c == '.') return 0x49; if (c == '/') return 0x4a; return 0x49; } ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/lh79520_irq.h��������������������������������������������������������0000644�0001750�0000144�00000006174�10541455476�016723� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * lh79520_vic.h - LH79520 Virtual Interrupt Controller channel definitions * Copyright (C) 2006 Dwayne C. Litzenberger <dlitz@dlitz.net> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * */ #ifndef ARCH_ARM_MACH_LH79520_IRQ_H #define ARCH_ARM_MACH_LH79520_IRQ_H // Virtual Interrupt Controller (VIC) Channels // Note that these aren't really IRQs (ARM only has a single IRQ line), but // it's easier for people to understand if we call them IRQs. #define IRQ_EXTINT0 0 // External Interrupt 0 #define IRQ_EXTINT1 1 // External Interrupt 1 #define IRQ_EXTINT2 2 // External Interrupt 2 #define IRQ_EXTINT3 3 // External Interrupt 3 #define IRQ_EXTINT4 4 // External Interrupt 4 #define IRQ_EXTINT5 5 // External Interrupt 5 #define IRQ_EXTINT6 6 // External Interrupt 6 #define IRQ_EXTINT7 7 // External Interrupt 7 #define IRQ_SPARE0 8 // Spare Internal Interrupt 0 #define IRQ_COMRX 9 // COMRx Interrupt (intended for debugger) #define IRQ_COMTX 10 // COMTx Interrupt (intended for debugger) #define IRQ_SSPRXTO 11 // Sync. Serial Port Rx Timeout for DMA xfer #define IRQ_CLCD 12 // Color LCD Combined Interrupt #define IRQ_SSPTXINTR 13 // Sync. Serial Port Tx Interrupt #define IRQ_SSPRXINTR 14 // Sync. Serial Port Rx Interrupt #define IRQ_SSPRORINTR 15 // Sync. Serial Port Rx Overrun Interrupt #define IRQ_SSPINTR 16 // Sync. Serial Port Combined Interrupt #define IRQ_TIMER0 17 // Timer 0 Interrupt #define IRQ_TIMER1 18 // Timer 1 Interrupt #define IRQ_TIMER2 19 // Timer 2 Interrupt #define IRQ_TIMER3 20 // Timer 3 Interrupt #define IRQ_UART0RX 21 // UART0 Rx Combined Interrupt #define IRQ_UART0TX 22 // UART0 Tx Combined Interrupt #define IRQ_UART0 23 // UART0 Combined Interrupt #define IRQ_UART1 24 // UART1 Combined Interrupt #define IRQ_UART2 25 // UART2 Combined Interrupt #define IRQ_DMA 26 // DMA Combined Interrupt #define IRQ_SPARE4 27 // Space Internal Interrupt 4 #define IRQ_SPARE5 28 // Space Internal Interrupt 5 #define IRQ_SPARE6 29 // Space Internal Interrupt 6 #define IRQ_RTC 30 // Real Time Clock Interrupt #define IRQ_WDT 31 // Watchdog Timer Interrupt #endif /* ARCH_ARM_MACH_LH79520_IRQS_H */ /* vim:set tabstop=8 shiftwidth=4 softtabstop=4 expandtab: */ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/at91rm92.h�����������������������������������������������������������0000644�0001750�0000144�00000017757�11006120657�016322� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* at91rm92.h - definitions of "at91rm9200" machine for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 05/29/2004 initial version * * walimis <wlm@student.dlut.edu.cn> * */ #ifndef __AT91RM9200_H_ #define __AT91RM9200_H_ /******************************************** * Advanced Interrupt Controller(AIC) ********************************************/ #define AT91RM92_AIC_BASE0 (0xfffff000) #define AT91RM92_AIC_SIZE 0x1000 #define AIC_SMR AT91RM92_AIC_BASE0+(0) // Source Mode Register #define AIC_SVR AT91RM92_AIC_BASE0+(128) // Source Vector Register #define AIC_IVR AT91RM92_AIC_BASE0+(256) // IRQ Vector Register #define AIC_FVR AT91RM92_AIC_BASE0+(260) // FIQ Vector Register #define AIC_ISR AT91RM92_AIC_BASE0+(264) // Interrupt Status Register #define AIC_IPR AT91RM92_AIC_BASE0+(268) // Interrupt Pending Register #define AIC_IMR AT91RM92_AIC_BASE0+(272) // Interrupt Mask Register #define AIC_CISR AT91RM92_AIC_BASE0+(276) // Core Interrupt Status Register #define AIC_IECR AT91RM92_AIC_BASE0+(288) // Interrupt Enable Command Register #define AIC_IDCR AT91RM92_AIC_BASE0+(292) // Interrupt Disable Command Register #define AIC_ICCR AT91RM92_AIC_BASE0+(296) // Interrupt Clear Command Register #define AIC_ISCR AT91RM92_AIC_BASE0+(300) // Interrupt Set Command Register #define AIC_EOICR AT91RM92_AIC_BASE0+(304) // End of Interrupt Command Register #define AIC_SPU AT91RM92_AIC_BASE0+(308) // Spurious Vector Register #define AIC_DCR AT91RM92_AIC_BASE0+(312) // Debug Control Register (Protect) #define AIC_FFER AT91RM92_AIC_BASE0+(320) // Fast Forcing Enable Register #define AIC_FFDR AT91RM92_AIC_BASE0+(324) // Fast Forcing Disable Register #define AIC_FFSR AT91RM92_AIC_BASE0+(328) // Fast Forcing Status Register /******************************************** * System Timer definition ********************************************/ #define AT91RM92_ST_BASE0 (0xfffffd00) #define AT91RM92_ST_SIZE 0x100 /* System I/O register * */ #define ST_CR 0x0 #define ST_PIMR 0x4 #define ST_WDMR 0x8 #define ST_RTMR 0xC #define ST_SR 0x10 #define ST_IER 0x14 #define ST_IDR 0x18 #define ST_IMR 0x1C #define ST_RTAR 0x20 #define ST_CRTR 0x24 /* ST interrupt use "sys" interrupt * */ #define AT91RM92_ID_SYS (0x1 << 1) // System Peripheral #define AT91RM92_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt #define AT91RM92_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow #define AT91RM92_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment #define AT91RM92_ST_ALMS (0x1 << 3) // (ST) Alarm Status struct at91rm92_st_io { /* I/O register * */ u32 cr; /* control */ u32 pimr; /* Period Interval Mode */ u32 wdmr; /* Watchdog Mode Register */ u32 rtmr; /* Real-time Mode Register */ u32 sr; /* Status Register */ u32 ier; /* Interrupt Enable Register */ u32 idr; /* Interrupt Disable Register */ u32 imr; /* Interrupt Mask Register */ u32 rtar; /* Real-time Alarm Register */ u32 crtr; /* Current Real-time Register */ u16 piv_dc; /*Period Interval Value down count */ u16 wdv_dc; /*Watchdog Counter Value down count */ u16 rtpres_dc; /*Real-time Timer Prescaler Value down count */ }; /******************************************** * USART definition ********************************************/ /* I/O register Offset * */ #define US_CR 0x0 #define US_MR 0x4 #define US_IER 0x8 #define US_IDR 0xC #define US_IMR 0x10 #define US_CSR 0x14 #define US_RHR 0x18 #define US_THR 0x1C #define US_BRGR 0x20 #define US_RTOR 0x24 #define US_TTGR 0x28 #define US_FIDI 0x40 #define US_NER 0x44 #define US_IF 0x4C #define AT91RM92_US_RXRDY ( 0x1 << 0) // (USART) RXRDY Interrupt #define AT91RM92_US_TXRDY ( 0x1 << 1) // (USART) TXRDY Interrupt #define AT91RM92_US_RXBRK ( 0x1 << 2) // (USART) Break Received/End of Break #define AT91RM92_US_ENDRX ( 0x1 << 3) // (USART) End of Receive Transfer Interrupt #define AT91RM92_US_ENDTX ( 0x1 << 4) // (USART) End of Transmit Interrupt #define AT91RM92_US_OVRE ( 0x1 << 5) // (USART) Overrun Interrupt #define AT91RM92_US_FRAME ( 0x1 << 6) // (USART) Framing Error Interrupt #define AT91RM92_US_PARE ( 0x1 << 7) // (USART) Parity Error Interrupt #define AT91RM92_US_TIMEOUT ( 0x1 << 8) // (USART) Receiver Time-out #define AT91RM92_US_TXEMPTY ( 0x1 << 9) // (USART) TXEMPTY Interrupt #define AT91RM92_US_ITERATION ( 0x1 << 10) // (USART) Max number of Repetitions Reached #define AT91RM92_US_TXBUFE ( 0x1 << 11) // (USART) TXBUFE Interrupt #define AT91RM92_US_RXBUFF ( 0x1 << 12) // (USART) RXBUFF Interrupt #define AT91RM92_US_NACK ( 0x1 << 13) // (USART) Non Acknowledge #define AT91RM92_US_RIIC ( 0x1 << 16) // (USART) Ring INdicator Input Change Flag #define AT91RM92_US_DSRIC ( 0x1 << 17) // (USART) Data Set Ready Input Change Flag #define AT91RM92_US_DCDIC ( 0x1 << 18) // (USART) Data Carrier Flag #define AT91RM92_US_CTSIC ( 0x1 << 19) // (USART) Clear To Send Input Change Flag /* default base address for uart0 and uart1 * at91rm9200 use "USART" instead of "UART". we here use name "UART". * */ #define AT91RM92_UART_BASE (0xfffc0000) #define AT91RM92_UART_SIZE 0x4000 #define AT91RM92_ID_US0 ( 0x1 << 6) // USART 0 #define AT91RM92_ID_US1 ( 0x1 << 7) // USART 1 #define AT91RM92_ID_US2 ( 0x1 << 8) // USART 2 #define AT91RM92_ID_US3 ( 0x1 << 9) // USART 3 #define AT91RM92_ID_US(i) (0x1 << (6 + i)) /* DBGU Register Defination */ #define DBGU_BASE 0xFFFFF200 #define DBGU_CR (DBGU_BASE + 0x0) #define DBGU_MR (DBGU_BASE + 0x4) #define DBGU_IER (DBGU_BASE + 0x8) #define DBGU_IDR (DBGU_BASE + 0xC) #define DBGU_IMR (DBGU_BASE + 0x10) #define DBGU_SR (DBGU_BASE + 0x14) #define DBGU_RHR (DBGU_BASE + 0x18) #define DBGU_THR (DBGU_BASE + 0x1C) #define DBGU_BRGR (DBGU_BASE + 0x20) #define DBGU_CIDR (DBGU_BASE + 0x40) /* Power Management Controller */ #define PMC_BASE 0xFFFFFC00 #define CKGR_PLLAR (PMC_BASE + 0x28) #define CKGR_PLLBR (PMC_BASE + 0x2C) #define PMC_MCKR (PMC_BASE + 0x30) #define PMC_SR (PMC_BASE + 0x68) #define AT91_PMC_LOCKB (1 << 2) struct at91rm92_uart_io { /* I/O register * */ u32 cr; /* control */ u32 mr; /* mode */ u32 ier; /* interrupt enable */ u32 idr; /* interrupt disable */ u32 imr; /* interrupt mask */ u32 csr; /* channel status */ u32 rhr; /* receive holding */ u32 thr; /* tramsmit holding */ u32 brgr; /* baud rate generator */ u32 rtor; /* rx time-out */ u32 ttgr; /* tx time-guard */ u32 fidi; u32 ner; u32 us_if; u32 sysflg; }; struct at91rm92_dbgu_io { /* I/O register * */ u32 cr; /* Control register */ u32 mr; /* Mode register */ u32 ier; /* Interrupt enable register */ u32 idr; /* Interrupt disable register*/ u32 imr; /* Interrupt mask register */ u32 sr; u32 rhr; u32 thr; u32 brgr; u32 cidr; u32 exid; }; struct at91rm92_pmc_io{ u32 ckgr_pllar; u32 ckgr_pllbr; u32 pmc_mckr; u32 pmc_sr; }; #endif /*__AT91RM9200_H_ */ �����������������skyeye-1.2.5_REL/arch/arm/mach/lh79520.h������������������������������������������������������������0000644�0001750�0000144�00000003465�10541455476�016050� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������ #ifndef __LH79520_H__ #define __LH79520_H__ #define TC1OI (1<<IRQ_TIMER0) #define TC2OI (1<<IRQ_TIMER1) #define UART1INT (1<<IRQ_UART1) #define VIC_IRQStatus (VIC_BASE+0x000) #define VIC_IntSelect (VIC_BASE+0x00c) #define VIC_IntEnable (VIC_BASE+0x010) #define VIC_IntEnClear (VIC_BASE+0x014) #define VIC_VectAddr (VIC_BASE+0x100) #define VIC_VectCntl (VIC_BASE+0x200) #define RCPC_control (RCPC_PHYS+0x00) #define RCPC_idString (RCPC_PHYS+0x04) //Chip ID #define RCPC_HCLKPrescale (RCPC_PHYS+0x18) #define RCPC_periphClkCtrl (RCPC_PHYS+0x24) #define RCPC_intClear (RCPC_PHYS+0x84) #define RCPC_intConfig (RCPC_PHYS+0x80) #define IOCON_MiscMux (IOCON_PHYS+0x08) #define IOCON_UARTMux (IOCON_PHYS+0x10) #define UARTDR 0x000 //Data read from or written to the UART #define UARTRSR 0x004 //Receive Status Register (when Read). #define UARTECR 0x004 //Error Clear Register (when Written). #define UARTFR 0x018 //Flag Register #define UARTIBRD 0x024 //Integer Baud Rate Divisor Register #define UARTFBRD 0x028 //Fractional Baud Rate Divisor Register #define UARTLCR_H 0x02C //Line Control Register, HIGH byte #define UARTCR 0x030 //Control Register #define UARTIMSC 0x038 //Interrupt Mask Set/Clear #define UARTMIS 0x040 //Masked Interrupt Status Register #define UARTICR 0x044 //Interrupt Clear Register #define AMBA_UARTFR_TXFE (1<<7) /* Tx FIFO Empty */ #define TIMER0_LOAD (TIMER0_PHYS+0x00) #define TIMER0_VALUE (TIMER0_PHYS+0x04) #define TIMER0_CONTROL (TIMER0_PHYS+0x08) #define TIMER0_CLEAR (TIMER0_PHYS+0x0C) #define TIMER1_LOAD (TIMER0_PHYS+0x20) #define TIMER1_VALUE (TIMER0_PHYS+0x24) #define TIMER1_CONTROL (TIMER0_PHYS+0x28) #define TIMER1_CLEAR (TIMER0_PHYS+0x2C) #define TIMER2_CONTROL (TIMER1_PHYS+0x08) #define TIMER3_CONTROL (TIMER1_PHYS+0x28) #define TIMER_CONTROL_MODE (1<<6) #endif // �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_ep9312.c�������������������������������������������������0000644�0001750�0000144�00000026420�10555732132�020321� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_ep9312.c - define machine ep9312 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 11/06/2004 clean some codes * wlm <wlm@student.dlut.edu.cn> * 10/8/2004 init this file. * add machine ep9312's function. * Cai Qiang <caiqiang@ustc.edu> * * */ #include "armdefs.h" #include "clps9312.h" #include "ep9312.h" #include "serial_amba.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" void ep9312_io_write_word (ARMul_State * state, ARMword addr, ARMword data); ARMword ep9312_io_read_word (ARMul_State * state, ARMword addr); #define NR_UART 3 #define UART_FR_TXFE (1<<7) #define UART_FR_RXFE (1<<4) #define UART_IIR_RIS (1<<1) #define UART_IIR_TIS (1<<2) const int TCOI[2] = { 1 << 4, 1 << 5 }; const int UART_RXINTR[3] = { 1 << 23, 1 << 25, 1 << 27 }; const int UART_TXINTR[3] = { 1 << 24, 1 << 26, 1 << 28 }; const int INT_UART[3] = { 1 << (52 - 32), 1 << (54 - 32), 1 << (55 - 32) }; const int iConsole = 0; //index of uart of serial console /*Internal IO Register*/ typedef struct ep9312_io { ARMword syscon_devcfg; /* System control */ ARMword intsr[2]; /* Interrupt status reg */ ARMword intmr[2]; /* Interrupt mask reg */ struct ep9312_tc_io tc[4]; struct ep9312_uart_io uart[NR_UART]; } ep9312_io_t; static ep9312_io_t ep9312_io; #define io ep9312_io static void ep9312_update_int (ARMul_State * state) { ARMword requests = io.intsr[0] & io.intmr[0]; requests |= io.intsr[1] & io.intmr[1]; state->NfiqSig = (requests & 0x0001) ? LOW : HIGH; state->NirqSig = (requests & 0xfffe) ? LOW : HIGH; } static void ep9312_io_reset (ARMul_State * state) { int i; io.syscon_devcfg = 0; io.intmr[0] = 0; io.intmr[1] = 0; /* reset TC register */ io.tc[0].value = 0; io.tc[1].value = 0; io.tc[2].value = 0; io.tc[0].mod_value = 0xffff; io.tc[1].mod_value = 0xffff; io.tc[2].mod_value = 0xffffffff; for (i = 0; i < NR_UART; i++) { io.uart[i].dr = 0; io.uart[i].fr = UART_FR_TXFE; } } void ep9312_io_do_cycle (ARMul_State * state) { int i; /* We must implement TC1, TC2 and TC4 */ for (i = 0; i < 2; i++) { if (io.tc[i].value == 0) { if (io.tc[i].ctl & TC_CTL_MODE) io.tc[i].value = io.tc[i].load; else io.tc[i].value = io.tc[i].mod_value; io.intsr[0] |= TCOI[i]; ep9312_update_int (state); } else { io.tc[i].value--; } } io.tc[3].load++; if (!(io.intsr[0] & (UART_RXINTR[iConsole])) && io.uart[iConsole].dr == 0) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.uart[iConsole].dr = (int) buf; io.intsr[0] |= UART_RXINTR[iConsole]; io.intmr[0] |= UART_RXINTR[iConsole]; io.intsr[1] |= INT_UART[iConsole]; io.intmr[1] |= INT_UART[iConsole]; io.uart[iConsole].iir |= UART_IIR_RIS; io.uart[iConsole].fr &= ~UART_FR_RXFE; ep9312_update_int (state); } } //if (!(io.intsr & URXINT)) } static void ep9312_uart_read (ARMul_State * state, u32 offset, u32 * data, int index) { switch (offset) { case UART_DR: *data = io.uart[index].dr; io.uart[index].dr = 0; io.intsr[0] &= ~(UART_RXINTR[index]); io.intsr[1] &= ~(INT_UART[index]); io.uart[index].iir &= ~UART_IIR_RIS; io.uart[index].fr |= UART_FR_RXFE; ep9312_update_int (state); break; case UART_RSR: *data = io.uart[index].rsr; break; //case UART_ECR: case UART_CR_H: case UART_CR_M: case UART_CR_L: break; case UART_CR: *data = io.uart[index].cr; break; case UART_FR: *data = io.uart[index].fr; break; case UART_IIR: *data = io.uart[index].iir; break; //case UART_ICR: case UART_ILPR: case UART_DMACR: case UART_TCR: case UART_TISR: case UART_TOCR: case UART_TMR: case UART_MCR: case UART_MSR: break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } } static void ep9312_uart_write (ARMul_State * state, u32 offset, u32 data, int index) { switch (offset) { case UART_DR: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } case UART_RSR: //case UART_ECR: case UART_CR_H: case UART_CR_M: case UART_CR_L: break; case UART_CR: { io.uart[index].cr = data; if ((data & AMBA_UARTCR_TIE) == 0) { io.intmr[0] &= ~(UART_TXINTR[index]); io.intsr[0] &= ~(UART_TXINTR[index]); io.intsr[1] &= ~(INT_UART[index]); io.intmr[1] &= ~(INT_UART[index]); io.uart[index].iir &= ~(UART_IIR_TIS); //Interrupt Identification and Clear } else { io.intmr[0] |= (UART_TXINTR[index]); io.intsr[0] |= (UART_TXINTR[index]); io.intsr[1] = (INT_UART[index]); io.intmr[1] = (INT_UART[index]); io.uart[index].iir |= (UART_IIR_TIS); } ep9312_update_int (state); } break; case UART_FR: case UART_IIR: io.uart[index].iir = data; break; //case UART_ICR: case UART_ILPR: case UART_DMACR: case UART_TCR: case UART_TISR: case UART_TOCR: case UART_TMR: case UART_MCR: case UART_MSR: break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } } /* Timer read/write register */ static void ep9312_tc_read (u32 offset, u32 * data, int index) { if (index == 4) { if (offset == TC_VALUELOW) *data = io.tc[index].load; else if (offset == TC_VALUEHIGH) *data = io.tc[index].value; } switch (offset) { case TC_LOAD: *data = io.tc[index].load; break; case TC_VALUE: *data = io.tc[index].value; break; case TC_CTL: *data = io.tc[index].ctl; break; case TC_CLEAR: SKYEYE_DBG ("%s(0x%x, 0x%x): read WO register\n", __func__, offset, data); break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } } static void ep9312_tc_write (ARMul_State * state, u32 offset, u32 data, int index) { switch (offset) { case TC_LOAD: io.tc[index].load = data; break; case TC_VALUE: SKYEYE_DBG ("%s(0x%x, 0x%x): write RO register\n", __func__, offset, data); break; case TC_CTL: io.tc[index].ctl = data; break; case TC_CLEAR: io.intsr[0] &= ~TCOI[index]; ep9312_update_int (state); break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } } ARMword ep9312_io_read_byte (ARMul_State * state, ARMword addr) { return ep9312_io_read_word (state, addr); } ARMword ep9312_io_read_halfword (ARMul_State * state, ARMword addr) { SKYEYE_DBG ("SKYEYE: %s error\n", __func__); } ARMword ep9312_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = 0; /* TC1 */ if ((addr >= EP9312_TC_BASE1) && (addr < (EP9312_TC_BASE1 + EP9312_TC_SIZE))) { ep9312_tc_read ((u32) (addr - EP9312_TC_BASE1), (u32 *) & data, 0); } /* TC2 */ if ((addr >= EP9312_TC_BASE4) && (addr < (EP9312_TC_BASE4 + EP9312_TC_SIZE))) { ep9312_tc_read ((u32) (addr - EP9312_TC_BASE4), (u32 *) & data, 3); } /* UART1 */ if ((addr >= EP9312_UART_BASE1) && (addr < (EP9312_UART_BASE1 + EP9312_UART_SIZE))) { ep9312_uart_read (state, (u32) (addr - EP9312_UART_BASE1), (u32 *) & data, 0); return data; } /* UART3 */ if ((addr >= EP9312_UART_BASE3) && (addr < (EP9312_UART_BASE3 + EP9312_UART_SIZE))) { ep9312_uart_read (state, (u32) (addr - EP9312_UART_BASE3), (u32 *) & data, 2); return data; } switch (addr) { case SYSCON_PWRCNT: break; case VIC0INTENABLE: data = io.intmr[0]; // printf("%s(0x%08x) = 0x%08x\n", __func__, addr, data); break; case VIC0IRQSTATUS: data = io.intsr[0]; io.intsr[0] = 0; //!!! break; case VIC1IRQSTATUS: data = io.intsr[1]; io.intsr[1] = 0; break; case RTCDR: case AACGCR: case AACRGIS: // printf("%s(0x%08x) = 0x%08x\n", __func__, addr, data); break; case SYSCON_DEVCFG: data = io.syscon_devcfg; break; default: SKYEYE_DBG ("SKYEYE:unknown io addr, %s(0x%08x) = 0x%08x\n", __func__, addr, data); break; } return data; } void ep9312_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { ep9312_io_write_word (state, addr, data); } void ep9312_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: %s error\n", __func__); } void ep9312_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { ARMword tmp; if ((addr >= EP9312_TC_BASE1) && (addr < (EP9312_TC_BASE1 + EP9312_TC_SIZE))) { ep9312_tc_write (state, (u32) (addr - EP9312_TC_BASE1), data, 0); } if ((addr >= EP9312_UART_BASE1) && (addr < (EP9312_UART_BASE1 + EP9312_UART_SIZE))) { ep9312_uart_write (state, (u32) (addr - EP9312_UART_BASE1), data, 0); } if ((addr >= EP9312_UART_BASE3) && (addr < (EP9312_UART_BASE3 + EP9312_UART_SIZE))) { ep9312_uart_write (state, (u32) (addr - EP9312_UART_BASE3), data, 2); } switch (addr) { case SYSCON_CLKSET1: break; case SYSCON_CLKSET2: case SYSCON_PWRCNT: break; case VIC0INTENABLE: io.intmr[0] = data; if (data != 0x10 && data != 0x20) printf ("SKYEYE: write VIC0INTENABLE=0x%x\n", data); ep9312_update_int (state); break; case VIC1INTENABLE: io.intmr[1] = data; // printf("SKYEYE: write VIC1INTENABLE=0x%x\n", data); ep9312_update_int (state); break; case VIC0INTENCLEAR: io.intmr[0] ^= data; ep9312_update_int (state); break; case VIC1INTENCLEAR: io.intmr[1] ^= data; ep9312_update_int (state); break; case SYSCON_DEVCFG: io.syscon_devcfg = data; break; default: SKYEYE_DBG ("SKYEYE:unknown io addr, %s(0x%08x, 0x%08x), pc %x \n", __func__, addr, data, state->Reg[15]); break; } } void ep9312_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v4_Prop); /* ARM920T uses LOW */ state->lateabtSig = LOW; // state->Reg[1] = 282; //for EP9312 2.4.x arch id state->Reg[1] = 451; //for EP9312 2.6.x arch id //state->Reg[1] = 386; //for EP9315 2.4.x arch id this_mach->mach_io_do_cycle = ep9312_io_do_cycle; this_mach->mach_io_reset = ep9312_io_reset; this_mach->mach_io_read_byte = ep9312_io_read_byte; this_mach->mach_io_write_byte = ep9312_io_write_byte; this_mach->mach_io_read_halfword = ep9312_io_read_halfword; this_mach->mach_io_write_halfword = ep9312_io_write_halfword; this_mach->mach_io_read_word = ep9312_io_read_word; this_mach->mach_io_write_word = ep9312_io_write_word; this_mach->mach_update_int = ep9312_update_int; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_pxa270.c�������������������������������������������������0000644�0001750�0000144�00000040537�10555732132�020424� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#include <sys/time.h> #include <sys/types.h> #include <unistd.h> #include "armdefs.h" #include "pxa.h" /*ywc 2005-03-30*/ #include "skyeye_flash.h" #define F_CORE (100 * 1024 * 1024) //core frequence #define F_RTC 32768 //RTC #define F_OS 3686400 //OS timer #define RT_SCALE (F_CORE / F_RTC) / 50 #define OS_SCALE (F_CORE / F_OS / 10) / 50 #define FF_SCALE 200 //FF UART /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" //ywc,2004-11-30,declare a external array which stores touchscreen event information extern unsigned int Pen_buffer[8]; // defined in skyeye_lcd.c //ywc,2004-11-30,declare a external array which stores touchscreen event information,end //chy 2005-09-19, the define of pxa27x_io_t is in pxa.h //static pxa270_io_t pxa270_io; pxa270_io_t pxa270_io; static void refresh_irq (ARMul_State *); static void pxa270_io_reset () { memset (&pxa270_io, 0, sizeof (pxa270_io)); //chy 2003-08-25 pxa270_io.cccr = 0x121; // 1 0010 0001 pxa270_io.cken = 0x17def; pxa270_io.ts_int = 1 << 15; pxa270_io.ts_addr_begin = 0x40000300; pxa270_io.ts_addr_end = 0x4000031f; //ywc,2004-11-30,evaluate io of LCD and Touchscreen,end }; void pxa270_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { return; } void pxa270_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { return; } static pxa_set_intr (u32 interrupt) { pxa270_io.icpr |= (1 << interrupt); } static int pxa_pending_intr (u32 interrupt) { return ((pxa270_io.icpr & (1 << interrupt))); } static void pxa_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; pxa270_io.icip = (pxa270_io.icmr & pxa270_io.icpr) & ~pxa270_io.iclr; pxa270_io.icfp = (pxa270_io.icmr & pxa270_io.icpr) & pxa270_io.iclr; state->NirqSig = pxa270_io.icip ? LOW : HIGH; state->NfiqSig = pxa270_io.icfp ? LOW : HIGH; } static void pxa270_update_int (ARMul_State * state) { pxa270_io.icip = (pxa270_io.icmr & pxa270_io.icpr) & ~pxa270_io.iclr; pxa270_io.icfp = (pxa270_io.icmr & pxa270_io.icpr) & pxa270_io.iclr; state->NirqSig = pxa270_io.icip ? LOW : HIGH; state->NfiqSig = pxa270_io.icfp ? LOW : HIGH; } static void pxa270_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { pxa_ioregnum_t ioregaddr = addr; //ywc,2004-11-30,add for pxa's LCD simulation u32 tmp; mem_bank_t *mbp; //ywc,2004-11-30,add for pxa's LCD simulation,end //printf("SKYEYE:pxa270_io_write_word: io addr 0x%x, value 0x%x\n",ioregaddr,data); switch (ioregaddr) { /*RTC*/ case RCNR: pxa270_io.rcnr = data; break; case RTAR: pxa270_io.rtar = data; break; case RTSR: pxa270_io.rtsr |= (data & 0xc); pxa270_io.rtsr &= ~(data & 0x3); break; case RTTR: pxa270_io.rttr = data & 0x3ffffff; break; /*OS timer */ case OSCR: pxa270_io.oscr = data; break; case OSMR0: pxa270_io.osmr0 = data; break; case OSMR1: pxa270_io.osmr1 = data; break; case OSMR2: pxa270_io.osmr2 = data; break; case OSMR3: pxa270_io.osmr3 = data; break; case OWER: pxa270_io.ower |= data & 0x1; break; case OSSR: pxa270_io.ossr &= ~(data & 0xf); break; case OIER: pxa270_io.oier = data & 0xf; break; /*interrupt control */ //ywc,2004-11-30,for touchscreen use ICPR case ICPR: pxa270_io.icpr = data; //printf("\n write ICPR=%x",pxa270_io.icpr); //printf("\n"); break; //ywc,2004-11-30,for touchscreen use ICPR,end //case ICIP: //case ICFP: /*read only */ // break; case ICMR: pxa270_io.icmr = data; pxa270_io.icpr &= ~data; break; case ICLR: pxa270_io.iclr = data; break; //ffuart contril case FFTHR: { /*static tx_cnt=0; */ unsigned char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); /*chy 2004-07-21 from luzhetao: after write char, should set some value */ pxa270_io.ffiir &= ~0x2; pxa270_io.ffiir |= 0x1; pxa270_io.fflsr &= ~0x60; //tx_cnt++; //pxa270_io.ffier|=0x2; /* if(tx_cnt>63){ tx_cnt=0; pxa270_io.ffiir|=0x2; pxa270_io.fflsr|=0x60; refresh_irq(state); } */ //printf("SKYEYE: write FFTHR %x, iir %x,lsr %x, ier %x\n",data, pxa270_io.ffiir,pxa270_io.fflsr,pxa270_io.ffier); } break; case FFIER: pxa270_io.ffier = data & 0xff; break; case FFFCR: //write only pxa270_io.fffcr = data & 0xc7; //pxa270_io.ffiir = data & 0xc7 ; //if(pxa270_io.fffcr & 2 //printf("SKYEYE: write FFFCR %x, but is ffiir %x\n",pxa270_io.fffcr,pxa270_io.ffiir); break; case FFLCR: pxa270_io.fflcr = data & 0xff; break; //core clock case CCCR: pxa270_io.cccr = data & 0x3ff; break; case CKEN: pxa270_io.cken = data & 0x17def; break; case OSCC: pxa270_io.oscc = data & 0x3; break; //ywc,2004-11-30,add for pxa's LCD simulation #if 0 case LCCR0: tmp = pxa270_io.lccr0; pxa270_io.lccr0 = data; if ((!(tmp & LCCR0_ENB)) && (pxa270_io.lccr0 & LCCR0_ENB)) { if (once) break; once++; /* printf("\nFDADR0=%x,FDADR1=%x",pxa270_io.fdadr0,pxa270_io.fdadr1); printf("\n"); pxa270_io.lcd_addr_begin = pxa270_io.fdadr0 + 16*(2+2); printf("\nlcd_addr_begin=%x",pxa270_io.lcd_addr_begin); printf("\n"); */ pxa270_update_lcd (state); } break; case LCCR1: pxa270_io.lccr1 = data; break; case LCCR2: pxa270_io.lccr2 = data; break; case LCCR3: pxa270_io.lccr3 = data; break; case FDADR0: pxa270_io.fdadr0 = data; //printf("\nFDADR0=%x",pxa270_io.fdadr0); //printf("\n"); /* mbp = bank_ptr(pxa270_io.fdadr0); if(!mbp){ fprintf(stderr, "No bank at address 0x%x", pxa270_io.fdadr0); return; } fdadr0ADDRESS=(u32 *) &state->mem.rom[mbp - skyeye_config.mem.mem_banks][(pxa270_io.fdadr0 - mbp->addr)]; printf("\n %p",fdadr0ADDRESS); */ // printf("\n 0: %x",*((u32 *)fdadr0ADDRESS)); // printf("\n 1: %x",*((u32 *)fdadr0ADDRESS+1)); // printf("\n 2: %x",*((u32 *)fdadr0ADDRESS+2)); // printf("\n 3: %x",*((u32 *)fdadr0ADDRESS+3)); //printf("\n"); break; case FDADR1: pxa270_io.fdadr1 = data; //printf("\nFDADR1=%x",pxa270_io.fdadr1); //printf("\n"); break; case FSADR0: pxa270_io.fsadr0 = data; //printf("\nFSADR0=%x",pxa270_io.fsadr0); //printf("\n"); break; case FSADR1: pxa270_io.fsadr1 = data; //printf("\nFSADR1=%x",pxa270_io.fsadr1); //printf("\n"); break; #endif //ywc,2004-11-30,add for pxa's LCD simulation,end #if 0 case FFIIR: //read only case FFMCR: //no use case FFMSR: //read only no use case FFSPR: // no use case FFISR: // no use #endif default: //chy 2003-09-03 if debug, uncommit it //printf("SKYEYE: pxa270_io_write_word: unknown addr 0x%x, reg15 0x%x \n", addr,state->Reg[15]); ; }; }; ARMword pxa270_io_read_byte (ARMul_State * state, ARMword addr) { return 0; } ARMword pxa270_io_read_halfword (ARMul_State * state, ARMword addr) { return 0; } ARMword pxa270_io_read_word (ARMul_State * state, ARMword addr) { u32 data; pxa_ioregnum_t ioregaddr = addr; //ywc,2004-11-30,add for pxa's Touchscreen simulation u32 ts_addr; //printf("SKYEYE:pxa270_io_read_word: begin io addr 0x%x \n",ioregaddr); //ywc,2004-11-30,add for pxa's Touchscreen simulation,end //ywc 2004-11-30 read the touch srceen data buffer,return to the ts device driver ts_addr = addr & ~3; // 1 word==4 byte if (ts_addr >= pxa270_io.ts_addr_begin && ts_addr <= pxa270_io.ts_addr_end) { data = pxa270_io. ts_buffer[(ts_addr - pxa270_io.ts_addr_begin) / 4]; return data; } //ywc 2004-11-30 read the touch srceen data buffer,return to the ts device driver,end switch (addr) { /*RTC*/ case RCNR: data = pxa270_io.rcnr; break; case RTAR: data = pxa270_io.rtar; break; case RTSR: data = pxa270_io.rtsr; break; case RTTR: data = pxa270_io.rttr; break; /*OS timer */ case OSCR: data = pxa270_io.oscr; break; case OSMR0: data = pxa270_io.osmr0; break; case OSMR1: data = pxa270_io.osmr1; break; case OSMR2: data = pxa270_io.osmr2; break; case OSMR3: data = pxa270_io.osmr3; break; case OWER: data = pxa270_io.ower; break; case OSSR: data = pxa270_io.ossr; break; case OIER: data = pxa270_io.oier; break; /*interrupt controler */ case ICPR: data = pxa270_io.icpr; break; case ICIP: data = (pxa270_io.icmr & pxa270_io.icpr) & ~pxa270_io.iclr; break; case ICFP: data = (pxa270_io.icmr & pxa270_io.icpr) & pxa270_io.iclr; break; case ICMR: data = pxa270_io.icmr; break; case ICLR: data = pxa270_io.iclr; break; /* ffuart control */ case FFRBR: //chy: 2003-08-24 have some question, maybe skyeye will be locked here ???? { //unsigned char c; //read(skyeye_config.uart.fd_in, &c, 1); //data = c; data = pxa270_io.ffrbr & 0xff; pxa270_io.icpr &= ~FFUART_IRQ; pxa270_io.icip &= ~FFUART_IRQ; pxa270_io.ffiir &= ~0x4; /*chy 2004-07-21 from lzt, afte read char, should set this bit */ pxa270_io.ffiir |= 0x1; //printf("SKYEYE: read FFRBR, but set ffiir and ~04, now %x\n",pxa270_io.ffiir); pxa270_io.fflsr &= ~0x1; }; break; case FFIER: data = pxa270_io.ffier; break; case FFIIR: //read only data = pxa270_io.ffiir & 0xcf; pxa270_io.icpr &= ~FFUART_IRQ; pxa270_io.icip &= ~FFUART_IRQ; //printf("SKYEYE: read FFIIR %x\n",data); break; case FFLCR: data = pxa270_io.fflcr; break; case FFLSR: //read only //chy 2003-08-24 NOTICE! //fixed by ksh 2004-05-09,for FFUART can input char,I am not sure? //pxa270_io.fflsr=1<<5; // LSR's TDRQ =1 , then the cpu can write char again pxa270_io.fflsr |= 0x60; // chy 2003-09-02 for LSR_TEMT|LSR_THRE 0x40|0x20 data = pxa270_io.fflsr & 0xff; break; // core clock case CCCR: data = pxa270_io.cccr; break; case CKEN: data = pxa270_io.cken; break; case OSCC: data = pxa270_io.oscc; break; //ywc,2004-11-30,add for pxa's LCD simulation #if 0 case LCCR0: data = pxa270_io.lccr0; break; case LCCR1: data = pxa270_io.lccr1; break; case LCCR2: data = pxa270_io.lccr2; break; case LCCR3: data = pxa270_io.lccr3; break; case FDADR0: data = pxa270_io.fdadr0; break; case FDADR1: data = pxa270_io.fdadr1; break; case FSADR0: data = pxa270_io.fsadr0; break; case FSADR1: data = pxa270_io.fsadr1; break; #endif //ywc,2004-11-30,add for pxa's LCD simulation,end #if 0 case FFFCR: //write only case FFMCR: //no use case FFMSR: //read only no use case FFSPR: // no use case FFISR: // no use #endif default: data = 0; //chy 2003-09-03 if debug, uncommit it //printf("SKYEYE: pxa270_io_read_word: unknown addr 0x%x, reg15 0x%x \n", addr,state->Reg[15]); }; //printf("SKYEYE:pxa270_io_read_word: end io addr 0x%x data 0x%x\n",ioregaddr,data); return data; }; static void pxa270_io_do_cycle (ARMul_State * state) { /*RTC*/ if (++pxa270_io.rt_scale >= RT_SCALE) { pxa270_io.rt_scale = 0; if (pxa270_io.rt_count++ == (pxa270_io.rttr & 0xffff)) { pxa270_io.rt_count = 0; if (pxa270_io.rcnr++ == pxa270_io.rtar) { if (pxa270_io.rtsr & 0x4) { pxa270_io.rtsr |= 0x1; }; } if (pxa270_io.rtsr & 0x8) { pxa270_io.rtsr |= 0x2; } } if ((pxa270_io.rtsr & 0x1) && (pxa270_io.rtsr & 0x4)) pxa270_io.icpr |= RTC_ALARM_IRQ; if ((pxa270_io.rtsr & 0x2) && (pxa270_io.rtsr & 0x8)) pxa270_io.icpr |= RTC_HZ_IRQ; } /* OS timer */ if (++pxa270_io.os_scale >= OS_SCALE) { u32 mask = 0; u32 count; pxa270_io.os_scale = 0; count = pxa270_io.oscr; if (count == pxa270_io.osmr0){ mask = 1; } if (count == pxa270_io.osmr1) mask |= 0x2; if (count == pxa270_io.osmr2) mask |= 0x4; if (count == pxa270_io.osmr3) { mask |= 0x8; if (pxa270_io.ower & 1) { state->NresetSig = LOW; printf ("************SKYEYE: WatchDog reset!!!!!!!**************\n"); } } pxa270_io.oscr++; pxa270_io.ossr |= mask; mask = pxa270_io.oier & pxa270_io.ossr; pxa270_io.icpr |= (mask << OS_IRQ_SHF); } /*FF UART */ //pxa270_io.utsr0 = 1; /*always TFS, no others*/ //pxa270_io.utsr1 = 0x4; /*TNF*/ if (++pxa270_io.ff_scale >= FF_SCALE) { pxa270_io.ff_scale = 0; if (!(FFUART_IRQ & pxa270_io.icpr)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char c; tv.tv_sec = 0; tv.tv_usec = 0; //pxa270_io.utsr1 |= 0x2; //RNE //pxa270_io.utsr0 |= 0x4; //Rx idle //added by ksh,2004-4-25,get uart data and set the interrupt if(skyeye_uart_read(-1, &c, 1, &tv, NULL) > 0) { pxa270_io.ffrbr = (int) c; pxa270_io.ffiir |= 0x4; //Rx idle //printf("SKYEYE: io_do_cycle set ffiir or 04, now %x\n",pxa270_io.ffiir); pxa270_io.fflsr |= 0x01; //Data ready } if ((pxa270_io.ffier & 0x1) && (pxa270_io.ffiir & 0x4)) { pxa270_io.icpr |= FFUART_IRQ; pxa270_io.ffiir &= ~0x1; } /*chy 2004-07-21 from luzhetao: produce a IRQ and ox2 should clean by OS driver */ if (pxa270_io.ffier & 0x2) { pxa270_io.icpr |= FFUART_IRQ; pxa270_io.ffiir |= 0x2; pxa270_io.ffiir &= ~0x1; pxa270_io.fflsr |= 0x60; } } //ywc,2004-11-30,check and get the mouse event #ifndef NO_LCD if (!(pxa270_io.icpr & pxa270_io.ts_int)) { //if now has no ts interrupt,then query if (Pen_buffer[6] == 1) { //should trigger a interrupt *(pxa270_io.ts_buffer + 0) = Pen_buffer[0]; *(pxa270_io.ts_buffer + 1) = Pen_buffer[1]; *(pxa270_io.ts_buffer + 4) = Pen_buffer[4]; *(pxa270_io.ts_buffer + 6) = Pen_buffer[6]; //set EINT2 bit to trigger a interrupt,ts driver will clear it pxa270_io.icpr |= pxa270_io.ts_int; Pen_buffer[6] = 0; } } #endif //ywc,2004-11-30,check and get the mouse event,end } pxa270_update_int (state); /*reset interrupt pin status */ //refresh_irq (state); }; static void refresh_irq (ARMul_State * state) { u32 irq = 0; u32 mask; /*RTC*/ if ((pxa270_io.rtsr & 0x1) && (pxa270_io.rtsr & 0x4)) irq |= RTC_ALARM_IRQ; if ((pxa270_io.rtsr & 0x2) && (pxa270_io.rtsr & 0x8)) irq |= RTC_HZ_IRQ; /*OS time */ mask = pxa270_io.oier & pxa270_io.ossr; irq |= (mask << OS_IRQ_SHF); #if 0 /*UART3 */ if ((pxa270_io.utcr3 & 0x8) && (pxa270_io.utsr0 & 0x6)) irq |= UART3_IRQ; if (pxa270_io.utsr0 & 0x38) irq |= UART3_IRQ; if ((pxa270_io.utcr3 & 0x10) && (pxa270_io.utsr0 & 0x1)) irq |= UART3_IRQ; #endif /*FFUART*/ //chy 2004-07-19 luzetao find a solution: if (pxa270_io.ffier&0x2){ irq |= FFUART_IRQ; } //chy 2004-07-19 then linux-2.6.x can run correctly! //chy 2004-06-23 FFIER TIE or RAVIE, so shoud be 3, FFIIR 0x4 or 0x2=0x6 /* chy 2004-07-21 from luzhetao if((pxa270_io.ffier&0x02)||((pxa270_io.ffier&0x3) && (pxa270_io.ffiir&0x6))){ irq |= FFUART_IRQ; } */ /*chy 2004-07-21 from luzhetao: produce a IRQ */ if ((pxa270_io.ffier & 0x1) && (pxa270_io.ffiir & 0x4)) { irq |= FFUART_IRQ; pxa270_io.ffiir &= ~0x1; } /*chy 2004-07-21 from luzhetao: produce a IRQ and ox2 should clean by OS driver */ if (pxa270_io.ffier & 0x2) { irq |= FFUART_IRQ; pxa270_io.ffiir |= 0x2; pxa270_io.ffiir &= ~0x1; pxa270_io.fflsr |= 0x60; } //ywc,2004-11-30,produce a touchsreen IRQ if (pxa270_io.icpr & pxa270_io.ts_int) { irq |= pxa270_io.ts_int; } //ywc,2004-11-30,produce a touchsreen IRQ,end pxa270_io.icpr = irq; pxa270_io.icip = (pxa270_io.icmr & pxa270_io.icpr) & ~pxa270_io.iclr; pxa270_io.icfp = (pxa270_io.icmr & pxa270_io.icpr) & pxa270_io.iclr; state->NirqSig = pxa270_io.icip ? LOW : HIGH; state->NfiqSig = pxa270_io.icfp ? LOW : HIGH; } void pxa270_mach_init (ARMul_State * state, machine_config_t * mc) { //chy 2003-08-19, setprocessor //chy 2005-09-19 add PXA27X_Prop ARMul_SelectProcessor (state, ARM_XScale_Prop | ARM_v5_Prop | ARM_v5e_Prop | ARM_PXA27X_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = LOW; state->Reg[1] = 406; /*mainstone machine id. */ pxa270_io_reset (); /*added by ksh for energy estimation in 2004-11-26 */ state->energy.cccr = pxa270_io.cccr; mc->mach_io_do_cycle = pxa270_io_do_cycle; mc->mach_io_reset = pxa270_io_reset; mc->mach_io_read_byte = pxa270_io_read_byte; mc->mach_io_write_byte = pxa270_io_write_byte; mc->mach_io_read_halfword = pxa270_io_read_halfword; mc->mach_io_write_halfword = pxa270_io_write_halfword; mc->mach_io_read_word = pxa270_io_read_word; mc->mach_io_write_word = pxa270_io_write_word; mc->mach_set_intr = pxa_set_intr; mc->mach_pending_intr = pxa_pending_intr; mc->mach_update_intr = pxa_update_intr; mc->state = (void *) state; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/pxa.h����������������������������������������������������������������0000644�0001750�0000144�00000017103�10541455476�015620� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _PXA_H_ #define _PXA_H_ //chy: refer to linux/include/asm-arm/arch-pxa/irq.h enum { RTC_ALARM_IRQ = (1 << 31), RTC_HZ_IRQ = (1 << 30), OS_IRQ_SHF = 26, FFUART_IRQ = (1 << 22), }; //chy: refer to linux/include/asm-arm/arch-pxa/pxa-regs.h typedef enum pxa_ioregnum_t { ICIP = 0x40D00000, /* Interrupt Controller IRQ Pending Register */ ICMR = 0x40D00004, /* Interrupt Controller Mask Register */ ICLR = 0x40D00008, /* Interrupt Controller Level Register */ ICFP = 0x40D0000C, /* Interrupt Controller FIQ Pending Register */ ICPR = 0x40D00010, /* Interrupt Controller Pending Register */ ICCR = 0x40D00014, /* Interrupt Controller Control Register */ RCNR = 0x40900000, /* RTC Count Register */ RTAR = 0x40900004, /* RTC Alarm Register */ RTSR = 0x40900008, /* RTC Status Register */ RTTR = 0x4090000C, /* RTC Timer Trim Register */ OSMR0 = 0x40A00000, OSMR1 = 0x40A00004, OSMR2 = 0x40A00008, OSMR3 = 0x40A0000C, OSCR = 0x40A00010, /* OS Timer Counter Register */ OSSR = 0x40A00014, /* OS Timer Status Register */ OWER = 0x40A00018, /* OS Timer Watchdog Enable Register */ OIER = 0x40A0001C, /* OS Timer Interrupt Enable Register */ /*Full Function UART */ FFRBR = 0x40100000, /* Receive Buffer Register (read only) */ FFTHR = 0x40100000, /* Transmit Holding Register (write only) */ FFIER = 0x40100004, /* Interrupt Enable Register (read/write) */ FFIIR = 0x40100008, /* Interrupt ID Register (read only) */ FFFCR = 0x40100008, /* FIFO Control Register (write only) */ FFLCR = 0x4010000C, /* Line Control Register (read/write) */ FFMCR = 0x40100010, /* Modem Control Register (read/write) */ FFLSR = 0x40100014, /* Line Status Register (read only) */ FFMSR = 0x40100018, /* Reserved */ FFSPR = 0x4010001C, /* Scratch Pad Register (read/write) */ FFISR = 0x40100020, /* Infrared Selection Register (read/write) */ FFDLL = 0x40100000, /* Divisor Latch Low Register (DLAB = 1) (read/write) */ FFDLH = 0x40100004, /* Divisor Latch High Register (DLAB = 1) (read/write) */ /*Standard UART */ BTRBR = 0x40200000, /* Receive Buffer Register (read only) */ BTTHR = 0x40200000, /* Transmit Holding Register (write only) */ BTIER = 0x40200004, /* Interrupt Enable Register (read/write) */ BTIIR = 0x40200008, /* Interrupt ID Register (read only) */ BTFCR = 0x40200008, /* FIFO Control Register (write only) */ BTLCR = 0x4020000C, /* Line Control Register (read/write) */ BTMCR = 0x40200010, /* Modem Control Register (read/write) */ BTLSR = 0x40200014, /* Line Status Register (read only) */ BTMSR = 0x40200018, /* Reserved */ BTSPR = 0x4020001C, /* Scratch Pad Register (read/write) */ BTISR = 0x40200020, /* Infrared Selection Register (read/write) */ BTDLL = 0x40200000, /* Divisor Latch Low Register (DLAB = 1) (read/write) */ BTDLH = 0x40200004, /* Divisor Latch High Register (DLAB = 1) (read/write) */ /*Standard UART */ STRBR = 0x40700000, /* Receive Buffer Register (read only) */ STTHR = 0x40700000, /* Transmit Holding Register (write only) */ STIER = 0x40700004, /* Interrupt Enable Register (read/write) */ STIIR = 0x40700008, /* Interrupt ID Register (read only) */ STFCR = 0x40700008, /* FIFO Control Register (write only) */ STLCR = 0x4070000C, /* Line Control Register (read/write) */ STMCR = 0x40700010, /* Modem Control Register (read/write) */ STLSR = 0x40700014, /* Line Status Register (read only) */ STMSR = 0x40700018, /* Reserved */ STSPR = 0x4070001C, /* Scratch Pad Register (read/write) */ STISR = 0x40700020, /* Infrared Selection Register (read/write) */ STDLL = 0x40700000, /* Divisor Latch Low Register (DLAB = 1) (read/write) */ STDLH = 0x40700004, /* Divisor Latch High Register (DLAB = 1) (read/write) */ //core clock regs CCCR = 0x41300000, /* Core Clock Configuration Register */ CKEN = 0x41300004, /* Clock Enable Register */ OSCC = 0x41300008, /* Oscillator Configuration Register */ //ywc,2004-11-30, add LCD control register LCCR0 = 0x44000000, LCCR1 = 0x44000004, LCCR2 = 0x44000008, LCCR3 = 0x4400000C, FDADR0 = 0x44000200, FSADR0 = 0x44000204, FIDR0 = 0x44000208, LDCMD0 = 0x4400020C, FDADR1 = 0x44000210, FSADR1 = 0x44000214, FIDR1 = 0x44000218, LDCMD1 = 0x4400021C //ywc,2004-11-30, add LCD control register,end } pxa_ioregnum_t; //ywc,2004-11-30, add macro definition for LCD #define LCCR0_ENB 0x00000001 #define LCCR1_PPL 0x000003FF #define LCCR2_LPP 0x000003FF #define LCCR3_BPP 0x07000000 //ywc,2004-11-30, add macro definition for LCD,end //chy 2009-09-19 from skyeye_mach_pxa250.c to here typedef struct pxa250_io_t { /*interrupt controller */ u32 icpr; u32 icip; u32 icfp; u32 icmr; u32 iccr; u32 iclr; /*real time clock(RTC) */ u32 rcnr; u32 rtar; u32 rtsr; u32 rttr; //chy: maybe not regs ???? u32 rt_scale; /*core frequence to 32.768K */ u32 rt_count; /*os timer */ u32 oscr; u32 osmr0, osmr1, osmr2, osmr3; u32 ower; u32 ossr; u32 oier; //chy: maybe not regs ???? u32 os_scale; //chy: I can not find it in pxa-regs.h???? /*full function uart controller */ u32 ffrbr; u32 ffthr; u32 ffier; u32 ffiir; u32 fffcr; u32 fflcr; u32 ffmcr; u32 fflsr; u32 ffmsr; u32 ffspr; u32 ffisr; u32 ffdll; u32 ffdlh; u32 ff_scale; /*bluetooth function uart controller */ u32 btrbr; u32 btthr; u32 btier; u32 btiir; u32 btfcr; u32 btlcr; u32 btmcr; u32 btlsr; u32 btmsr; u32 btspr; u32 btisr; u32 btdll; u32 btdlh; /*standard uart controller */ u32 strbr; u32 stthr; u32 stier; u32 stiir; u32 stfcr; u32 stlcr; u32 stmcr; u32 stlsr; u32 stmsr; u32 stspr; u32 stisr; u32 stdll; u32 stdlh; /*core clock */ u32 cccr; u32 cken; u32 oscc; //ywc,2004-11-30,add io of LCD and Touchscreen /*LCD*/ /* remove them later. */ u32 lccr0; u32 lccr1; u32 lccr2; u32 lccr3; u32 fdadr0; u32 fdadr1; u32 fsadr0; u32 fsadr1; /*TouchScreen */ u32 ts_int; u32 ts_buffer[8]; u32 ts_addr_begin; u32 ts_addr_end; //ywc,2004-11-30,add io of LCD and Touchscreen,end } pxa250_io_t; //chy 2009-09-19 from skyeye_mach_pxa270.c to here //chy: lubbock, cerf, idp are different board // I can add a union to cover the difference in the future //chy: refer to linux/include/asm-arm/arch-pxa/pxa-regs.h typedef struct pxa270_io_t { /*interrupt controller */ u32 icpr; u32 icip; u32 icfp; u32 icmr; u32 iccr; u32 iclr; /*real time clock(RTC) */ u32 rcnr; u32 rtar; u32 rtsr; u32 rttr; //chy: maybe not regs ???? u32 rt_scale; /*core frequence to 32.768K */ u32 rt_count; /*os timer */ u32 oscr; u32 osmr0, osmr1, osmr2, osmr3; u32 ower; u32 ossr; u32 oier; //chy: maybe not regs ???? u32 os_scale; //chy: I can not find it in pxa-regs.h???? /*full function uart controller */ u32 ffrbr; u32 ffthr; u32 ffier; u32 ffiir; u32 fffcr; u32 fflcr; u32 ffmcr; u32 fflsr; u32 ffmsr; u32 ffspr; u32 ffisr; u32 ffdll; u32 ffdlh; u32 ff_scale; /*bluetooth function uart controller */ u32 btrbr; u32 btthr; u32 btier; u32 btiir; u32 btfcr; u32 btlcr; u32 btmcr; u32 btlsr; u32 btmsr; u32 btspr; u32 btisr; u32 btdll; u32 btdlh; /*standard uart controller */ u32 strbr; u32 stthr; u32 stier; u32 stiir; u32 stfcr; u32 stlcr; u32 stmcr; u32 stlsr; u32 stmsr; u32 stspr; u32 stisr; u32 stdll; u32 stdlh; /*core clock */ u32 cccr; u32 cken; u32 oscc; //ywc,2004-11-30,add io of LCD and Touchscreen /*LCD*/ /* remove them later. */ u32 lccr0; u32 lccr1; u32 lccr2; u32 lccr3; u32 fdadr0; u32 fdadr1; u32 fsadr0; u32 fsadr1; /*TouchScreen */ u32 ts_int; u32 ts_buffer[8]; u32 ts_addr_begin; u32 ts_addr_end; //ywc,2004-11-30,add io of LCD and Touchscreen,end } pxa270_io_t; //chy 2009-09-19 from skyeye_mach_pxa270.c to here-----end #endif �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_cs89712.c������������������������������������������������0000644�0001750�0000144�00000017225�10555732132�020421� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_cs89712.c - define machine cs89712 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 3/24/2003 init this file. * add machine cs89712's function. Most taken from original armio.c. * include: cs89712_mach_init, cs89712_io_do_cycle * cs89712_io_read_word, cs89712_io_write_word * Most taken from skyeye_mach_ep7312.c * <trilok_soni@yahoo.co.in> * */ #include "armdefs.h" #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include "clps7110.h" #include "ep7212.h" #include "cs89712.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" /*Internal IO Register*/ typedef struct cs89712_io { ARMword syscon; /* System control */ ARMword sysflg; /* System status flags */ ARMword intsr; /* Interrupt status reg */ ARMword intmr; /* Interrupt mask reg */ ARMword tcd[2]; /* Timer/counter data */ ARMword tcd_reload[2]; /* Last value written */ int tc_prescale; ARMword uartdr; /* Receive data register */ ARMword lcdcon; /* LCD control */ ARMword lcd_limit; /* 0xc0000000 <= LCD buffer < lcd_limit */ } cs89712_io_t; static cs89712_io_t cs89712_io; #define io cs89712_io static void cs89712_update_int (ARMul_State * state) { ARMword requests = io.intsr & io.intmr; state->NfiqSig = (requests & 0x0001) ? LOW : HIGH; state->NirqSig = (requests & 0xfffe) ? LOW : HIGH; } static void cs89712_io_reset (ARMul_State * state) { io.syscon = 0; io.sysflg = URXFE; io.intmr = 0; io.intsr = UTXINT; /* always ready to transmit */ io.tcd[0] = 0xffff; io.tcd[1] = 0xffff; io.tcd_reload[0] = 0xffff; io.tcd_reload[1] = 0xffff; io.uartdr = 0; io.lcdcon = 0; io.lcd_limit = 0; } void cs89712_io_do_cycle (ARMul_State * state) { int t; for (t = 0; t < 2; t++) { if (io.tcd[t] == 0) { if (io.syscon & (t ? TC2M : TC1M)) { io.tcd[t] = io.tcd_reload[t]; } else { io.tcd[t] = 0xffff; } io.intsr |= (t ? TC2OI : TC1OI); cs89712_update_int (state); } else { io.tcd[t]--; } } if (!(io.intsr & URXINT)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.uartdr = (int) buf; io.sysflg &= ~URXFE; io.intsr |= URXINT; cs89712_update_int (state); } } } ARMword cs89712_io_read_byte (ARMul_State * state, ARMword addr) { /*printf("SKYEYE: cs89712_io_read_byte error\n"); */ skyeye_exit (-1); } ARMword cs89712_io_read_halfword (ARMul_State * state, ARMword addr) { /*printf("SKYEYE: cs89712_io_read_halfword error\n"); */ skyeye_exit (-1); } ARMword cs89712_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = 0; switch (addr - 0x80000000) { case SYSCON: data = io.syscon; break; case SYSFLG: data = io.sysflg; break; /* case MEMCFG1: * case MEMCFG2: * case DRFPR */ case INTSR: data = io.intsr; break; case INTMR: data = io.intmr; break; case LCDCON: data = io.lcdcon; break; case TC1D: data = io.tcd[0]; break; case TC2D: data = io.tcd[1]; break; /* case RTCDR: * case RTCMR: * case PMPCON : * case CODR:*/ case UARTDR: data = io.uartdr; io.sysflg |= URXFE; io.intsr &= ~URXINT; cs89712_update_int (state); break; /* case UBRLCR: */ case SYNCIO: /* if we return zero here, the battery voltage calculation * results in a divide-by-zero that messes up the kernel */ data = 1; break; /* case PALLSW: * case PALMSW:*/ /* write-only: */ case STFCLR: case BLEOI: case MCEOI: case TEOI: case TC1EOI: case TC2EOI: case RTCEOI: case UMSEOI: case COEOI: case HALT: case STDBY: break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? //SKYEYE_DBG("io_read_word(0x%08x) = 0x%08x\n", addr, data); break; } return data; } void cs89712_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { printf ("SKYEYE: cs89712_io_write_byte error\n"); skyeye_exit (-1); } void cs89712_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { printf ("SKYEYE: cs89712_io_write_halfword error\n"); skyeye_exit (-1); } void cs89712_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { ARMword tmp; switch (addr - 0x80000000) { case SYSCON: tmp = io.syscon; io.syscon = data; /*if ((tmp & LCDEN) != (data & LCDEN)) { update_lcd(state); } */ break; case SYSFLG: break; case INTSR: break; case INTMR: io.intmr = data; cs89712_update_int (state); break; case LCDCON: tmp = io.lcdcon; io.lcdcon = data; if ((tmp & (VBUFSIZ | LINELEN | GSEN | GSMD)) != (tmp & (VBUFSIZ | LINELEN | GSEN | GSMD))) { //chy 2005-01-07 no use now /* update_lcd(state); */ } break; case TC1D: io.tcd[0] = io.tcd_reload[0] = data & 0xffff; SKYEYE_DBG ("TC1D 0x%x\n", data & 0xffff); break; case TC2D: io.tcd[1] = io.tcd_reload[1] = data & 0xffff; SKYEYE_DBG ("TC2D 0x%x\n", data & 0xffff); break; case UARTDR: /* The UART writes chars to console */ { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } break; /* case BLEOI: printf("BLEOI\n"); break; case MCEOI: printf("MCEOI\n"); break; case TEOI: printf("TEOI\n"); break;*/ case TC1EOI: io.intsr &= ~TC1OI; cs89712_update_int (state); SKYEYE_DBG ("TC1EOI\n"); break; case TC2EOI: io.intsr &= ~TC2OI; cs89712_update_int (state); SKYEYE_DBG ("TC2EOI\n"); break; //case RTCEOI: printf("RTCEOI\n"); break; //case UMSEOI: printf("UMSEOI\n"); break; //case COEOI: printf("COEOI\n"); break; case 0x2000: /* Not a real register, for debugging only: */ SKYEYE_DBG ("io_write_word debug: 0x%08lx\n", data); break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? //printf("unknown io addr, io_write_word(0x%08x, 0x%08x), pc %x \n", addr, data,state->Reg[15]); break; } } void cs89712_mach_init (ARMul_State * state, machine_config_t * this_mach) { state->abort_model = 2; ARMul_SelectProcessor (state, ARM_v4_Prop); //chy 2004-05-09, set lateabtSig state->lateabtSig = HIGH; state->Reg[1] = 107; //for cdb89712 arch id this_mach->mach_io_do_cycle = cs89712_io_do_cycle; this_mach->mach_io_reset = cs89712_io_reset; this_mach->mach_io_read_byte = cs89712_io_read_byte; this_mach->mach_io_write_byte = cs89712_io_write_byte; this_mach->mach_io_read_halfword = cs89712_io_read_halfword; this_mach->mach_io_write_halfword = cs89712_io_write_halfword; this_mach->mach_io_read_word = cs89712_io_read_word; this_mach->mach_io_write_word = cs89712_io_write_word; this_mach->mach_update_int = cs89712_update_int; } ���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_ep9315.c�������������������������������������������������0000644�0001750�0000144�00000026500�10555732132�020323� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_ep9315.c - define machine ep9315 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "armdefs.h" #include "clps9312.h" #include "ep9315.h" #include "serial_amba.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" #define TC_DIVISOR (50) /* Set your BogoMips here :) */ void ep9315_io_write_word (ARMul_State * state, ARMword addr, ARMword data); ARMword ep9315_io_read_word (ARMul_State * state, ARMword addr); #define NR_UART 3 #define UART_FR_TXFE (1<<7) #define UART_FR_RXFE (1<<4) #define UART_IIR_RIS (1<<1) #define UART_IIR_TIS (1<<2) const int TCOI[2] = { 1 << 4, 1 << 5 }; const int UART_RXINTR[3] = { 1 << 23, 1 << 25, 1 << 27 }; const int UART_TXINTR[3] = { 1 << 24, 1 << 26, 1 << 28 }; const int INT_UART[3] = { 1 << (52 - 32), 1 << (54 - 32), 1 << (55 - 32) }; const int iConsole = 0; //index of uart of serial console /*Internal IO Register*/ typedef struct ep9315_io { ARMword syscon_devcfg; /* System control */ ARMword intsr[2]; /* Interrupt status reg */ ARMword intmr[2]; /* Interrupt mask reg */ struct ep9315_tc_io tc[4]; struct ep9315_uart_io uart[NR_UART]; int tc_prescale; } ep9315_io_t; static ep9315_io_t ep9315_io; #define io ep9315_io static void ep9315_update_int (ARMul_State * state) { ARMword requests = io.intsr[0] & io.intmr[0]; requests |= io.intsr[1] & io.intmr[1]; state->NfiqSig = (requests & 0x0001) ? LOW : HIGH; state->NirqSig = (requests & 0xfffe) ? LOW : HIGH; } static void ep9315_io_reset (ARMul_State * state) { int i; io.syscon_devcfg = 0; io.intmr[0] = 0; io.intmr[1] = 0; /* reset TC register */ io.tc[0].value = 0; io.tc[1].value = 0; io.tc[2].value = 0; io.tc[0].mod_value = 0xffff; io.tc[1].mod_value = 0xffff; io.tc[2].mod_value = 0xffffffff; io.tc_prescale = TC_DIVISOR; for (i = 0; i < NR_UART; i++) { io.uart[i].dr = 0; io.uart[i].fr = UART_FR_TXFE; } } void ep9315_io_do_cycle (ARMul_State * state) { int i; io.tc_prescale--; if (io.tc_prescale < 0) { io.tc_prescale = TC_DIVISOR; /* We must implement TC1, TC2 and TC4 */ for (i = 0; i < 2; i++) { if (io.tc[i].value == 0) { if (io.tc[i].ctl & TC_CTL_MODE) io.tc[i].value = io.tc[i].load; else io.tc[i].value = io.tc[i].mod_value; io.intsr[0] |= TCOI[i]; ep9315_update_int (state); } else { io.tc[i].value--; } } io.tc[3].load++; if (!(io.intsr[0] & (UART_RXINTR[iConsole])) && io.uart[iConsole].dr == 0) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.uart[iConsole].dr = (int) buf; io.intsr[0] |= UART_RXINTR[iConsole]; io.intmr[0] |= UART_RXINTR[iConsole]; io.intsr[1] |= INT_UART[iConsole]; io.intmr[1] |= INT_UART[iConsole]; io.uart[iConsole].iir |= UART_IIR_RIS; io.uart[iConsole].fr &= ~UART_FR_RXFE; ep9315_update_int (state); } } //if (!(io.intsr & URXINT)) } } static void ep9315_uart_read (ARMul_State * state, u32 offset, u32 * data, int index) { switch (offset) { case UART_DR: *data = io.uart[index].dr; io.uart[index].dr = 0; io.intsr[0] &= ~(UART_RXINTR[index]); io.intsr[1] &= ~(INT_UART[index]); io.uart[index].iir &= ~UART_IIR_RIS; io.uart[index].fr |= UART_FR_RXFE; ep9315_update_int (state); break; case UART_RSR: *data = io.uart[index].rsr; break; //case UART_ECR: case UART_CR_H: case UART_CR_M: case UART_CR_L: break; case UART_CR: *data = io.uart[index].cr; break; case UART_FR: *data = io.uart[index].fr; break; case UART_IIR: *data = io.uart[index].iir; break; //case UART_ICR: case UART_ILPR: case UART_DMACR: case UART_TCR: case UART_TISR: case UART_TOCR: case UART_TMR: case UART_MCR: case UART_MSR: break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } } static void ep9315_uart_write (ARMul_State * state, u32 offset, u32 data, int index) { switch (offset) { case UART_DR: { char c = data; #if 0 write (skyeye_config.uart.fd_out, &c, 1); #else /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); #endif } case UART_RSR: //case UART_ECR: case UART_CR_H: case UART_CR_M: case UART_CR_L: break; case UART_CR: { io.uart[index].cr = data; if ((data & AMBA_UARTCR_TIE) == 0) { io.intmr[0] &= ~(UART_TXINTR[index]); io.intsr[0] &= ~(UART_TXINTR[index]); io.intsr[1] &= ~(INT_UART[index]); io.intmr[1] &= ~(INT_UART[index]); io.uart[index].iir &= ~(UART_IIR_TIS); //Interrupt Identification and Clear } else { io.intmr[0] |= (UART_TXINTR[index]); io.intsr[0] |= (UART_TXINTR[index]); io.intsr[1] = (INT_UART[index]); io.intmr[1] = (INT_UART[index]); io.uart[index].iir |= (UART_IIR_TIS); } ep9315_update_int (state); } break; case UART_FR: case UART_IIR: io.uart[index].iir = data; break; //case UART_ICR: case UART_ILPR: case UART_DMACR: case UART_TCR: case UART_TISR: case UART_TOCR: case UART_TMR: case UART_MCR: case UART_MSR: break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } } /* Timer read/write register */ static void ep9315_tc_read (u32 offset, u32 * data, int index) { if (index == 4) { if (offset == TC_VALUELOW) *data = io.tc[index].load; else if (offset == TC_VALUEHIGH) *data = io.tc[index].value; } switch (offset) { case TC_LOAD: *data = io.tc[index].load; break; case TC_VALUE: *data = io.tc[index].value; break; case TC_CTL: *data = io.tc[index].ctl; break; case TC_CLEAR: SKYEYE_DBG ("%s(0x%x, 0x%x): read WO register\n", __func__, offset, data); break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } } static void ep9315_tc_write (ARMul_State * state, u32 offset, u32 data, int index) { switch (offset) { case TC_LOAD: io.tc[index].load = data; break; case TC_VALUE: SKYEYE_DBG ("%s(0x%x, 0x%x): write RO register\n", __func__, offset, data); break; case TC_CTL: io.tc[index].ctl = data; break; case TC_CLEAR: io.intsr[0] &= ~TCOI[index]; ep9315_update_int (state); break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } } ARMword ep9315_io_read_byte (ARMul_State * state, ARMword addr) { return ep9315_io_read_word (state, addr); } ARMword ep9315_io_read_halfword (ARMul_State * state, ARMword addr) { SKYEYE_DBG ("SKYEYE: %s error\n", __func__); } ARMword ep9315_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = 0; /* TC1 */ if ((addr >= EP9315_TC_BASE1) && (addr < (EP9315_TC_BASE1 + EP9315_TC_SIZE))) { ep9315_tc_read ((u32) (addr - EP9315_TC_BASE1), (u32 *) & data, 0); } /* TC2 */ if ((addr >= EP9315_TC_BASE4) && (addr < (EP9315_TC_BASE4 + EP9315_TC_SIZE))) { ep9315_tc_read ((u32) (addr - EP9315_TC_BASE4), (u32 *) & data, 3); } /* UART1 */ if ((addr >= EP9315_UART_BASE1) && (addr < (EP9315_UART_BASE1 + EP9315_UART_SIZE))) { ep9315_uart_read (state, (u32) (addr - EP9315_UART_BASE1), (u32 *) & data, 0); return data; } /* UART3 */ if ((addr >= EP9315_UART_BASE3) && (addr < (EP9315_UART_BASE3 + EP9315_UART_SIZE))) { ep9315_uart_read (state, (u32) (addr - EP9315_UART_BASE3), (u32 *) & data, 2); return data; } switch (addr) { case SYSCON_PWRCNT: break; case VIC0INTENABLE: data = io.intmr[0]; // printf("%s(0x%08x) = 0x%08x\n", __func__, addr, data); break; case VIC0IRQSTATUS: data = io.intsr[0]; io.intsr[0] = 0; //!!! break; case VIC1IRQSTATUS: data = io.intsr[1]; io.intsr[1] = 0; break; case RTCDR: case AACGCR: case AACRGIS: // printf("%s(0x%08x) = 0x%08x\n", __func__, addr, data); break; case SYSCON_DEVCFG: data = io.syscon_devcfg; break; default: SKYEYE_DBG ("SKYEYE:unknown io addr, %s(0x%08x) = 0x%08x\n", __func__, addr, data); break; } return data; } void ep9315_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { ep9315_io_write_word (state, addr, data); } void ep9315_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: %s error\n", __func__); } void ep9315_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { ARMword tmp; if ((addr >= EP9315_TC_BASE1) && (addr < (EP9315_TC_BASE1 + EP9315_TC_SIZE))) { ep9315_tc_write (state, (u32) (addr - EP9315_TC_BASE1), data, 0); } if ((addr >= EP9315_UART_BASE1) && (addr < (EP9315_UART_BASE1 + EP9315_UART_SIZE))) { ep9315_uart_write (state, (u32) (addr - EP9315_UART_BASE1), data, 0); } if ((addr >= EP9315_UART_BASE3) && (addr < (EP9315_UART_BASE3 + EP9315_UART_SIZE))) { ep9315_uart_write (state, (u32) (addr - EP9315_UART_BASE3), data, 2); } switch (addr) { case SYSCON_CLKSET1: break; case SYSCON_CLKSET2: case SYSCON_PWRCNT: break; case VIC0INTENABLE: io.intmr[0] = data; if (data != 0x10 && data != 0x20) printf ("SKYEYE: write VIC0INTENABLE=0x%x\n", data); ep9315_update_int (state); break; case VIC1INTENABLE: io.intmr[1] = data; // printf("SKYEYE: write VIC1INTENABLE=0x%x\n", data); ep9315_update_int (state); break; case VIC0INTENCLEAR: io.intmr[0] ^= data; ep9315_update_int (state); break; case VIC1INTENCLEAR: io.intmr[1] ^= data; ep9315_update_int (state); break; case SYSCON_DEVCFG: io.syscon_devcfg = data; break; default: SKYEYE_DBG ("SKYEYE:unknown io addr, %s(0x%08x, 0x%08x), pc %x \n", __func__, addr, data, state->Reg[15]); break; } } void ep9315_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v4_Prop); /* ARM920T uses LOW */ state->lateabtSig = LOW; // state->Reg[1] = 282; //for EP9315 2.4.x arch id state->Reg[1] = 451; //for EP9315 2.6.x arch id this_mach->mach_io_do_cycle = ep9315_io_do_cycle; this_mach->mach_io_reset = ep9315_io_reset; this_mach->mach_io_read_byte = ep9315_io_read_byte; this_mach->mach_io_write_byte = ep9315_io_write_byte; this_mach->mach_io_read_halfword = ep9315_io_read_halfword; this_mach->mach_io_write_halfword = ep9315_io_write_halfword; this_mach->mach_io_read_word = ep9315_io_read_word; this_mach->mach_io_write_word = ep9315_io_write_word; this_mach->mach_update_int = ep9315_update_int; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_ns9750.c�������������������������������������������������0000644�0001750�0000144�00000025033�10571722736�020351� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_ns9750.c - define machine NS9750 for skyeye Copyright (C) 2003 - 2005 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 10/31/2004 complete UART, Timer, Interrupt, now it can boot ARMLinux successfully. * walimis <wlm@student.dlut.edu.cn> * 5/23/2004 init this file. * walimis <wlm@student.dlut.edu.cn> * * */ #include "armdefs.h" #include "ns9750.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" typedef struct ns9750_io { u32 ivr; /*AIC Interrupt Vector Register */ u32 fvr; /*AIC FIQ Vector Register */ u32 isr; /*AIC Interrupt Status Register */ u32 ipr; /*AIC Interrupt Pending Register */ u32 imr; /*AIC Interrupt Mask Register */ u32 cisr; u32 iecr; u32 idcr; u32 iccr; u32 iscr; u32 eoicr; u32 spu; struct ns9750_st_io st; /*system timer */ struct ns9750_uart_io uart0; /*uart0 */ int tc_prescale; } ns9750_io_t; static ns9750_io_t ns9750_io; #define io ns9750_io static void ns9750_update_int (ARMul_State * state) { ARMword requests = io.ipr & io.imr; state->NfiqSig = (requests & 0x00001) ? LOW : HIGH; state->NirqSig = (requests & 0xfffffffe) ? LOW : HIGH; } /* new added functions * */ static void ns9750_set_intr (u32 interrupt) { io.ipr |= (1 << interrupt); } static int ns9750_pending_intr (u32 interrupt) { return ((io.ipr & (1 << interrupt))); } #if 0 static void ns9750_update_intr (void *mach) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; ARMword requests = io.ipr & io.imr; state->NfiqSig = (requests & 0x00001) ? LOW : HIGH; state->NirqSig = (requests & 0x3fffe) ? LOW : HIGH; } static int ns9750_mem_read_byte (void *mach, u32 addr, u32 * data) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; *data = (u32) mem_read_char (state, addr); } static int ns9750_mem_write_byte (void *mach, u32 addr, u32 data) { struct machine_config *mc = (struct machine_config *) mach; ARMul_State *state = (ARMul_State *) mc->state; mem_write_char (state, addr, (char) data); } #endif static void ns9750_io_reset (ARMul_State * state) { io.uart0.csr = 0x00000202; /* CHRL : 11 8bit * */ io.uart0.mr = 0x000000c0; io.uart0.brgr = 0x000000c0; } /*ns9750 io_do_cycle*/ static void ns9750_io_do_cycle (ARMul_State * state) { #if 1 if (io.st.pimr != 0) { if (io.st.piv_dc == 0) { io.st.sr |= AT91RM92_ST_PITS; if (io.st.imr & AT91RM92_ST_PITS) { io.ipr |= AT91RM92_ID_SYS; } io.st.piv_dc = io.st.pimr; } else { io.st.piv_dc--; } } if ((io.uart0.imr & AT91RM92_US_RXRDY)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.uart0.rhr = (int) buf; /* Receiver Ready * */ io.uart0.csr |= AT91RM92_US_RXRDY; /* pending usart0 interrupt * */ io.ipr |= AT91RM92_ID_US0; } } /* if (rcr > 0 && ... */ ns9750_update_int (state); #endif } static void ns9750_uart_read (u32 offset, u32 * data) { switch (offset) { case US_MR: *data = io.uart0.mr; break; case US_IMR: *data = io.uart0.imr; break; case US_CSR: *data = io.uart0.csr; break; case US_RHR: /* receive char * */ *data = io.uart0.rhr; io.uart0.csr &= (~AT91RM92_US_RXRDY); break; case US_BRGR: *data = io.uart0.brgr; break; case US_RTOR: *data = io.uart0.rtor; break; case US_TTGR: *data = io.uart0.ttgr; break; case US_FIDI: *data = io.uart0.fidi; break; case US_NER: *data = io.uart0.ner; break; case US_IF: *data = io.uart0.us_if; break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } static void ns9750_uart_write (ARMul_State * state, u32 offset, u32 data) { SKYEYE_DBG ("ns9750_uart_write(0x%x, 0x%x)\n", offset, data); switch (offset) { case US_CR: io.uart0.cr = data; break; case US_MR: io.uart0.mr = data; break; case US_IER: //io.uart0.ier = data; io.uart0.imr |= (data & 0x000f3fff); if (io.uart0.imr) { io.ipr |= AT91RM92_ID_US0; ns9750_update_int (state); } break; case US_IDR: /* disable usart0 corresponding interrupt * */ io.uart0.imr &= (~data) & 0x000f3fff; break; case US_THR: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.uart0.csr |= AT91RM92_US_TXRDY; } //io.uart0.thr = data; break; case US_BRGR: io.uart0.brgr = data; break; case US_RTOR: io.uart0.rtor = data; break; case US_TTGR: io.uart0.ttgr = data; break; case US_FIDI: io.uart0.fidi = data; break; case US_IF: io.uart0.us_if = data; break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } static void ns9750_st_read (u32 offset, u32 * data) { switch (offset) { case ST_PIMR: *data = io.st.pimr; break; case ST_WDMR: *data = io.st.wdmr; break; case ST_RTMR: *data = io.st.rtmr; break; case ST_SR: *data = io.st.sr; /* reinitialize it to zero */ io.st.sr = 0x0; break; case ST_IMR: *data = io.st.imr; break; case ST_RTAR: *data = io.st.rtar; break; case ST_CRTR: *data = io.st.crtr; break; } } static void ns9750_st_write (ARMul_State * state, u32 offset, u32 data) { switch (offset) { case ST_CR: io.st.cr = data; io.st.wdv_dc = io.st.wdmr; break; case ST_PIMR: io.st.pimr = data; io.st.piv_dc = data; break; case ST_WDMR: io.st.wdmr = data; io.st.wdv_dc = data; break; case ST_RTMR: io.st.rtmr = data; io.st.rtpres_dc = data; break; case ST_IER: io.st.imr |= (data & 0x0000000f); if (io.st.imr) { io.ipr |= AT91RM92_ID_SYS; ns9750_update_int (state); } break; case ST_IDR: io.st.imr &= (~data) & 0xf; break; case ST_RTAR: io.st.rtar = data; break; } } static ARMword ns9750_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = -1; int i; /*uart0 */ if ((addr >= AT91RM92_UART_BASE0) && (addr < (AT91RM92_UART_BASE0 + AT91RM92_UART_SIZE))) { ns9750_uart_read ((u32) (addr - AT91RM92_UART_BASE0), (u32 *) & data); } if ((addr >= AT91RM92_ST_BASE0) && (addr < (AT91RM92_ST_BASE0 + AT91RM92_ST_SIZE))) { ns9750_st_read ((u32) (addr - AT91RM92_ST_BASE0), (u32 *) & data); } switch (addr) { case AIC_IVR: /* IVR */ data = io.ipr; SKYEYE_DBG ("IVR irqs=%x ", data); for (i = 0; i < 32; i++) if (data & (1 << i)) break; if (i < 32) { data = i; io.ipr &= ~(1 << data); ns9750_update_int (state); } else data = 0; io.ivr = data; SKYEYE_DBG ("read IVR=%d\n", data); break; case AIC_ISR: /* ISR: interrupt status register */ data = io.ivr; break; case AIC_IMR: /* IMR */ data = io.imr; break; case AIC_CISR: /* CISR: Core interrupt status register */ data = io.cisr; data = io.imr; SKYEYE_DBG ("read CISR=%x,%x\n", data, io.cisr); break; default: break; } return data; } static ARMword ns9750_io_read_byte (ARMul_State * state, ARMword addr) { SKYEYE_DBG ("SKYEYE: ns9750_io_read_byte error\n"); ns9750_io_read_word (state, addr); } static ARMword ns9750_io_read_halfword (ARMul_State * state, ARMword addr) { SKYEYE_DBG ("SKYEYE: ns9750_io_read_halfword error\n"); ns9750_io_read_word (state, addr); } static void ns9750_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { if ((addr >= AT91RM92_UART_BASE0) && (addr < AT91RM92_UART_BASE0 + AT91RM92_UART_SIZE)) { ns9750_uart_write (state, addr - AT91RM92_UART_BASE0, data); } if ((addr >= AT91RM92_ST_BASE0) && (addr < (AT91RM92_ST_BASE0 + AT91RM92_ST_SIZE))) { ns9750_st_write (state, addr - AT91RM92_ST_BASE0, data); } switch (addr) { case AIC_IECR: /* IECR */ io.iecr = data; io.imr |= data; break; case AIC_IDCR: /* IDCR */ io.idcr = data; io.imr &= ~data; break; case AIC_ICCR: /* CLEAR interrupts */ io.iccr = data; io.ipr &= ~data; break; case AIC_EOICR: /* EOI */ io.eoicr = data; io.ipr &= ~data; ns9750_update_int (state); break; default: SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data); break; } } static void ns9750_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: ns9750_io_write_byte error\n"); ns9750_io_write_word (state, addr, data); } static void ns9750_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: ns9750_io_write_halfword error\n"); ns9750_io_write_word (state, addr, data); } void ns9750_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop); /* FIXME:ARM926EJS uses LOW? */ state->lateabtSig = LOW; state->Reg[1] = 552; //for NS9750 //state->Reg[1] = 627; //for NS9750 //state->Reg[1] = 196; //for NS9750 this_mach->mach_io_do_cycle = ns9750_io_do_cycle; this_mach->mach_io_reset = ns9750_io_reset; this_mach->mach_io_read_byte = ns9750_io_read_byte; this_mach->mach_io_write_byte = ns9750_io_write_byte; this_mach->mach_io_read_halfword = ns9750_io_read_halfword; this_mach->mach_io_write_halfword = ns9750_io_write_halfword; this_mach->mach_io_read_word = ns9750_io_read_word; this_mach->mach_io_write_word = ns9750_io_write_word; this_mach->mach_update_int = ns9750_update_int; //this_mach->mach_set_intr = ns9750_set_intr; //this_mach->mach_pending_intr = ns9750_pending_intr; //this_mach->mach_update_intr = ns9750_update_intr; //this_mach->mach_mem_read_byte = ns9750_mem_read_byte; //this_mach->mach_mem_write_byte = ns9750_mem_write_byte; //this_mach->state = (void *)state; } �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/s3c4510b.h�����������������������������������������������������������0000644�0001750�0000144�00000024536�10541455476�016204� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/********************************************************/ /* */ /* Samsung KS32C4510b */ /* Mac Wang <mac@os.nctu.edu.tw> */ /* */ /********************************************************/ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H /* * define S3C4510b CPU master clock */ #define MHz 1000000 #define fMCLK_MHz (50 * MHz) #define fMCLK (fMCLK_MHz / MHz) #define MCLK2 (fMCLK_MHz / 2) /* * ASIC Address Definition */ #define Base_Addr 0x3FF0000 #define VPint *(volatile unsigned int *) #define VPshort *(volatile unsigned short *) #define VPchar *(volatile unsigned char *) #ifndef CSR_WRITE # define CSR_WRITE(addr,data) (VPint(addr) = (data)) #endif #ifndef CSR_READ # define CSR_READ(addr) (VPint(addr)) #endif #ifndef CAM_Reg # define CAM_Reg(x) (VPint(CAMBASE+(x*0x4))) #endif /* ************************ */ /* System Manager Registers */ /* ************************ */ #define SYSCFG (Base_Addr+0x0000) #define CLKCON (Base_Addr+0x3000) #define EXTACON0 (Base_Addr+0x3008) #define EXTACON1 (Base_Addr+0x300C) #define EXTDBWTH (Base_Addr+0x3010) #define ROMCON0 (Base_Addr+0x3014) #define ROMCON1 (Base_Addr+0x3018) #define ROMCON2 (Base_Addr+0x301C) #define ROMCON3 (Base_Addr+0x3020) #define ROMCON4 (Base_Addr+0x3024) #define ROMCON5 (Base_Addr+0x3028) #define DRAMCON0 (Base_Addr+0x302C) #define DRAMCON1 (Base_Addr+0x3030) #define DRAMCON2 (Base_Addr+0x3034) #define DRAMCON3 (Base_Addr+0x3038) #define REFEXTCON (Base_Addr+0x303C) /* *********************** */ /* Ethernet BDMA Registers */ /* *********************** */ #define BDMATXCON (Base_Addr+0x9000) #define BDMARXCON (Base_Addr+0x9004) #define BDMATXPTR (Base_Addr+0x9008) #define BDMARXPTR (Base_Addr+0x900C) #define BDMARXLSZ (Base_Addr+0x9010) #define BDMASTAT (Base_Addr+0x9014) #define CAMBASE (Base_Addr+0x9100) /* * CAM 0x9100 ~ 0x917C * BDMATXBUF 0x9200 ~ 0x92FC * BDMARXBUF 0x9800 ~ 0x99FC */ /* ********************** */ /* Ethernet MAC Registers */ /* ********************** */ #define MACON (Base_Addr+0xA000) #define CAMCON (Base_Addr+0xA004) #define MACTXCON (Base_Addr+0xA008) #define MACTXSTAT (Base_Addr+0xA00C) #define MACRXCON (Base_Addr+0xA010) #define MACRXSTAT (Base_Addr+0xA014) #define STADATA (Base_Addr+0xA018) #define STACON (Base_Addr+0xA01C) #define CAMEN (Base_Addr+0xA028) #define EMISSCNT (Base_Addr+0xA03C) #define EPZCNT (Base_Addr+0xA040) #define ERMPZCNT (Base_Addr+0xA044) #define EXTSTAT (Base_Addr+0x9040) /* ************************ */ /* HDLC Channel A Registers */ /* ************************ */ /* ************************ */ /* HDLC Channel B Registers */ /* ************************ */ /* ******************* */ /* I/O Ports Registers */ /* ******************* */ #define IOPMOD (Base_Addr+0x5000) #define IOPCON (Base_Addr+0x5004) #define IOPDATA (Base_Addr+0x5008) /* ****************************** */ /* Interrupt Controller Registers */ /* ****************************** */ #define INTMOD (Base_Addr+0x4000) #define INTPND (Base_Addr+0x4004) #define INTMSK (Base_Addr+0x4008) #define INTPRI0 (Base_Addr+0x400C) #define INTPRI1 (Base_Addr+0x4010) #define INTPRI2 (Base_Addr+0x4014) #define INTPRI3 (Base_Addr+0x4018) #define INTPRI4 (Base_Addr+0x401C) #define INTPRI5 (Base_Addr+0x4020) #define INTOFFSET (Base_Addr+0x4024) #define INTPNDTST (Base_Addr+0x402C) #define INTOSET_FIQ (Base_Addr+0x4030) #define INTOSET_IRQ (Base_Addr+0x4034) #define IntMode (VPint(INTMOD)) #define IntPend (VPint(INTPND)) #define IntMask (VPint(INTMSK)) #define IntOffset (VPint(INTOFFSET)) #define IntPndTst (VPint(INTPNDTST)) #define IntOffset_FIQ (VPint(INTOSET_FIQ)) #define IntOffset_IRQ (VPint(INTOSET_IRQ)) #define INT_MODE_IRQ 0x000000 #define INT_MODE_FIQ 0x1FFFFF #define INT_MASK_DIS 0x1FFFFF #define INT_MASK_ENA 0x000000 #define INT_ENABLE(n) IntMask &= ~(1<<(n)) #define INT_DISABLE(n) IntMask |= (1<<(n)) #define CLEAR_PEND_INT(n) IntPend = (1<<(n)) #define SET_PEND_INT(n) IntPndTst |= (1<<(n)) /* ***************** */ /* I2C Bus Registers */ /* ***************** */ /* ************** */ /* GDMA Registers */ /* ************** */ /* ************** */ /* UART Registers */ /* ************** */ #define DEBUG_CONSOLE (0) #define ULCON0 (Base_Addr+0xD000) #define ULCON1 (Base_Addr+0xE000) #define UCON0 (Base_Addr+0xD004) #define UCON1 (Base_Addr+0xE004) #define USTAT0 (Base_Addr+0xD008) #define USTAT1 (Base_Addr+0xE008) #define UTXBUF0 (Base_Addr+0xD00C) #define UTXBUF1 (Base_Addr+0xE00C) #define URXBUF0 (Base_Addr+0xD010) #define URXBUF1 (Base_Addr+0xE010) #define UBRDIV0 (Base_Addr+0xD014) #define UBRDIV1 (Base_Addr+0xE014) #define UART_BASE0 ULCON0 #define UART_BASE1 ULCON1 #if DEBUG_CONSOLE == 0 #define DEBUG_TX_BUFF_BASE UTXBUF0 #define DEBUG_RX_BUFF_BASE URXBUF0 #define DEBUG_UARTLCON_BASE ULCON0 #define DEBUG_UARTCONT_BASE UCON0 #define DEBUG_UARTBRD_BASE UBRDIV0 #define DEBUG_CHK_STAT_BASE USTAT0 #elif DEBUG_CONSOLE == 1 #define DEBUG_TX_BUFF_BASE UTXBUF1 #define DEBUG_RX_BUFF_BASE URXBUF1 #define DEBUG_UARTLCON_BASE ULCON1 #define DEBUG_UARTCONT_BASE UCON1 #define DEBUG_UARTBRD_BASE UBRDIV1 #define DEBUG_CHK_STAT_BASE USTAT1 #endif #define DEBUG_ULCON_REG_VAL (0x3) #define DEBUG_UCON_REG_VAL (0x9) #define DEBUG_UBRDIV_REG_VAL (0x500) #define DEBUG_RX_CHECK_BIT (0X20) #define DEBUG_TX_CAN_CHECK_BIT (0X40) #define DEBUG_TX_DONE_CHECK_BIT (0X80) /* **************** */ /* Timers Registers */ /* **************** */ #define TMOD (Base_Addr+0x6000) #define TDATA0 (Base_Addr+0x6004) #define TDATA1 (Base_Addr+0x6008) #define TCNT0 (Base_Addr+0x600C) #define TCNT1 (Base_Addr+0x6010) /*******************/ /* SYSCFG Register */ /*******************/ #define SYS_INIT_BASE EXTDBWTH #define rSYSCFG (0x87FFFF90) /* disable Cache/Write buffer */ /**********************************/ /* System Memory Control Register */ /**********************************/ #define DSR0 (2<<0) /* ROM Bank0 */ #define DSR1 (0<<2) /* 0: Disable, 1: Byte, 2: Half-Word, 3: Word */ #define DSR2 (0<<4) #define DSR3 (0<<6) #define DSR4 (0<<8) #define DSR5 (0<<10) #define DSD0 (2<<12) /* RAM Bank0 */ #define DSD1 (0<<14) #define DSD2 (0<<16) #define DSD3 (0<<18) #define DSX0 (0<<20) /* EXTIO0 */ #define DSX1 (0<<22) #define DSX2 (0<<24) #define DSX3 (0<<26) #define rEXTDBWTH (DSR0|DSR1|DSR2|DSR3|DSR4|DSR5 | DSD0|DSD1|DSD2|DSD3 | DSX0|DSX1|DSX2|DSX3) /****************************************/ /* ROMCON0: ROM Bank 0 Control Register */ /****************************************/ #define PMC0 (0x0<<0) /*00: Normal ROM 01: 4 word page */ /*10: 8 word page 11:16 word page */ #define tPA0 (0x0<<2) /*00: 5 cycles 01: 2 cycles */ /*10: 3 cycles 11: 4 cycles */ #define tACC0 (0x6<<4) /*000: Disable bank 001: 2 cycles */ /*010: 3 cycles 011: 4 cycles */ /*110: 7 cycles 111: Reserved */ #define ROM_BASE0_R ((0x00000000>>16)<<10) #define ROM_NEXT0_R ((0x00200000>>16)<<20) #define ROM_BASE0_B ((0x01000000>>16)<<10) #define ROM_NEXT0_B ((0x01200000>>16)<<20) #define rROMCON0_R (ROM_NEXT0_R|ROM_BASE0_R|tACC0|tPA0|PMC0) #define rROMCON0_B (ROM_NEXT0_B|ROM_BASE0_B|tACC0|tPA0|PMC0) #define rROMCON1 0x0 #define rROMCON2 0x0 #define rROMCON3 0x0 #define rROMCON4 0x0 #define rROMCON5 0x0 /********************************************/ /* SDRAMCON0: SDRAM Bank 0 Control Register */ /********************************************/ #define StRC0 (0x1<<7) #define StRP0 (0x3<<8) #define SDRAM_BASE0_R ((0x01000000>>16)<<10) #define SDRAM_NEXT0_R ((0x01800000>>16)<<20) #define SDRAM_BASE0_B ((0x00000000>>16)<<10) #define SDRAM_NEXT0_B ((0x00800000>>16)<<20) #define SCAN0 (0x0<<30) #define rSDRAMCON0_R (SCAN0|SDRAM_NEXT0_R|SDRAM_BASE0_R|StRP0|StRC0) #define rSDRAMCON0_B (SCAN0|SDRAM_NEXT0_B|SDRAM_BASE0_B|StRP0|StRC0) #define rSDRAMCON1 0x0 #define rSDRAMCON2 0x0 #define rSDRAMCON3 0x0 /************************************************/ /* DRAM Refresh & External I/O Control Register */ /************************************************/ #define ExtIOBase (0x360<<0) #define VSF (0x1<<15) #define REN (0x1<<16) #define tCHR (0x0<<17) #define tCSR (0x0<<20) #define RefCountValue ((2048+1-(16*fMCLK))<<21) #define rREFEXTCON (RefCountValue|tCSR|tCHR|REN|VSF|ExtIOBase) /********/ /* Misc */ /********/ #define HARD_RESET_NOW() #define TMOD_TIMER0_VAL 0x3 /* Timer0 TOGGLE, and Run */ #define TAG_BASE 0x11000000 /********/ /* IRQs */ /********/ /* taken from uclinux * linux-2.4.x/include/asm/arch-snds100/irqs.h*/ #define NR_IRQS 21 #define VALID_IRQ(i) (i<=8 ||(i>=16 && i<NR_IRQS)) /* #define INT_EXTINT0 0x00000001 #define INT_EXTINT1 0x00000002 #define INT_EXTINT2 0x00000004 #define INT_EXTINT3 0x00000008 #define INT_UARTTX0 0x00000010 #define INT_UARTRX0 0x00000020 #define INT_UARTTX1 0x00000040 #define INT_UARTRX1 0x00000080 #define INT_GDMA0 0x00000100 #define INT_GDMA1 0x00000200 #define INT_TIMER0 0x00000400 #define INT_TIMER1 0x00000800 #define INT_HDLCTXA 0x00001000 #define INT_HDLCRXA 0x00002000 #define INT_HDLCTXB 0x00004000 #define INT_HDLCRXB 0x00008000 #define INT_BDMATX 0x00010000 #define INT_BDMARX 0x00020000 #define INT_MACTX 0x00040000 #define INT_MACRX 0x00080000 #define INT_IIC 0x00100000 #define INT_GLOBAL 0x00200000 */ #define INT_EXTINT0 0 #define INT_EXTINT1 1 #define INT_EXTINT2 2 #define INT_EXTINT3 3 #define INT_UARTTX0 4 #define INT_UARTRX0 5 #define INT_UARTTX1 6 #define INT_UARTRX1 7 #define INT_GDMA0 8 #define INT_GDMA1 9 #define INT_TIMER0 10 #define INT_TIMER1 11 #define INT_HDLCTXA 12 #define INT_HDLCRXA 13 #define INT_HDLCTXB 14 #define INT_HDLCRXB 15 #define INT_BDMATX 16 #define INT_BDMARX 17 #define INT_MACTX 18 #define INT_MACRX 19 #define INT_IIC 20 #define INT_GLOBAL 21 #define IRQ_TIMER INT_TIMER0 /*add by walimis.*/ #define INT_MASK_INIT 0x003FFFFF /* UART USTAT Register * taken from linux-2.4.x/include/asm/arch-snds100/serial.h */ #define UART_LSR_OE 0x01 // Overrun error #define UART_LSR_PE 0x02 // Parity error #define UART_LSR_FE 0x04 // Frame error #define UART_LSR_BI 0x08 // Break detect #define UART_LSR_DTR 0x10 // Data terminal ready #define UART_LSR_DR 0x20 // Receive data ready #define UART_LSR_THRE 0x40 // Transmit buffer register empty #define UART_LSR_TEMT 0x80 // Transmit complete #endif /* __ASM_ARCH_HARDWARE_H */ ������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/skyeye_mach_lh79520.c������������������������������������������������0000644�0001750�0000144�00000022324�10555732132�020407� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* skyeye_mach_lh79520.c - define machine lh79520 for skyeye Copyright (C) 2003 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 11/17/2004 init this file. * add machine lh79520's function. * include: lh79520_mach_init, lh79520_io_do_cycle * lh79520_io_read_word, lh79520_io_write_word * Cai Qiang <caiqiang@ustc.edu> * * */ #include "armdefs.h" #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include "lh79520-hardware.h" #include "lh79520_irq.h" #include "serial_amba_pl011.h" #include "lh79520.h" //zzc:2005-1-1 #ifdef __CYGWIN__ //chy 2005-07-28 #include <time.h> //teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- /*struct timeval { int tv_sec; int tv_usec; };*/ //AJ2D-------------------------------------------------------------------------- #endif /* 2007-01-18 added by Anthony Lee : for new uart device frame */ #include "skyeye_uart.h" #define REVISION "$Revision: 1.10 $" #define TC_DIVISOR (50) /* Set your BogoMips here :) */ #define DEBUG 1 #if DEBUG #define DBG_PRINT(a...) fprintf(stderr,##a) #else #define DBG_PRINT(a...) #endif /*Internal IO Register*/ typedef struct lh79520_io { ARMword intsr; /* Interrupt status reg */ ARMword intmr; /* Interrupt mask reg */ ARMword tcd[2]; /* Timer/counter data */ ARMword tcd_reload[2]; /* Last value written */ ARMword tcd_ctrl[2]; /* Timer Control Register */ int tc_prescale; ARMword uartdr; /* Receive Data Register */ ARMword uartfr; /* Flag Register */ ARMword uartcr; /* Control Register */ ARMword uartimsc; /* Interrupt Mask Set/Clear register */ ARMword uartmis; /* Masked Interrupt Status Register */ } lh79520_io_t; static lh79520_io_t lh79520_io; #define io lh79520_io static void lh79520_update_int (ARMul_State * state) { ARMword requests = io.intsr & io.intmr; state->NfiqSig = (requests & 0x0001) ? LOW : HIGH; state->NirqSig = (requests & 0xfffffffe) ? LOW : HIGH; } static void lh79520_io_reset (ARMul_State * state) { int i; io.intmr = 0; io.intsr = 0; for (i = 0; i < 2; i++) { io.tcd[i] = 0xffff; io.tcd_reload[i] = 0xffff; io.tcd_ctrl[i] = 0; } io.tc_prescale = TC_DIVISOR; io.uartdr = 0; io.uartfr = AMBA_UARTFR_TXFE; } static void UART2VIC (ARMul_State * state) { if (io.uartmis) io.intsr |= UART1INT; else io.intsr &= ~UART1INT; lh79520_update_int (state); } void lh79520_io_do_cycle (ARMul_State * state) { int t; io.tc_prescale--; if (io.tc_prescale < 0) { io.tc_prescale = TC_DIVISOR; for (t = 0; t < 2 - 1; t++) { //only timer0 be supported now if (io.tcd[t] == 0) { if (io.tcd_ctrl[t] & TIMER_CONTROL_MODE) { //Periodic mode io.tcd[t] = io.tcd_reload[t]; } else { //Free-Running mode io.tcd[t] = 0xffff; } io.intsr |= (t ? TC2OI : TC1OI); lh79520_update_int (state); } else { io.tcd[t]--; } } if (!(io.intsr & UART1INT)) { /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0) { io.uartdr = (int) buf; io.uartfr &= ~AMBA_UARTFR_RXFE; io.uartmis |= AMBA_UART_IS_RX; UART2VIC (state); } } //if (!(io.intsr & UART1INT)) } } ARMword lh79520_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = 0; switch (addr) { case RCPC_PHYS: case RCPC_HCLKPrescale: case RCPC_periphClkCtrl: case IOCON_UARTMux: case UART1_PHYS + UARTLCR_H: // printf("%s(%x)\n", __func__, addr); break; case UART1_PHYS + UARTCR: data = io.uartcr; break; case UART0_PHYS + UARTFR: case UART1_PHYS + UARTFR: data = io.uartfr; break; case UART1_PHYS + UARTRSR: data = 0; break; case UART1_PHYS + UARTIMSC: //5: TXIM 4: RXIM data = io.uartimsc; break; case UART1_PHYS + UARTMIS: //5: TXIM 4: RXIM data = io.uartmis; break; case UART1_PHYS + UARTDR: data = io.uartdr; io.uartfr |= AMBA_UARTFR_RXFE; io.uartmis &= ~AMBA_UART_IS_RX; UART2VIC (state); break; case VIC_IRQStatus: data = io.intsr; break; case VIC_IntEnable: data = io.intmr; break; case RCPC_idString: data = 0x5200; // Chip ID break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? printf ("SKYEYE:unknown io addr, %s(0x%08x), pc %x \n", __func__, addr, state->Reg[15]); //SKYEYE_DBG("io_read_word(0x%08x) = 0x%08x\n", addr, data); break; } return data; } ARMword lh79520_io_read_byte (ARMul_State * state, ARMword addr) { //some parts of kernel such as printascii use byte operation if (addr >= UART1_PHYS + UARTDR && addr <= UART1_PHYS + UARTICR) return lh79520_io_read_word (state, addr); else { printf ("SKYEYE: %s error\n", __func__); printf ("SKYEYE: state->pc=%x,state->instr=%x,addr=%x\n", state->pc, state->instr, addr); system ("stty sane"); skyeye_exit (-1); } } ARMword lh79520_io_read_halfword (ARMul_State * state, ARMword addr) { //some parts of kernel use it if (addr >= UART1_PHYS + UARTDR && addr <= UART1_PHYS + UARTICR) return lh79520_io_read_word (state, addr); else { printf ("SKYEYE: %s error %x\n", __func__, addr); system ("stty sane"); skyeye_exit (-1); } } void lh79520_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { ARMword tmp; if (addr >= VIC_VectAddr && addr <= VIC_VectAddr + 0x3c) { // printf("%s VectAddr(%x %x)\n", __func__, addr, data); return; } if (addr >= VIC_VectCntl && addr <= VIC_VectCntl + 0x3c) { // printf("%s VectCntl(%x %x)\n", __func__, addr, data); return; } if (addr >= DMAC_PHYS && addr < RCPC_PHYS) { // printf("%s DMAC(%x %x)\n", __func__, addr, data); return; } switch (addr) { case VIC_IntSelect: case IOCON_MiscMux: case IOCON_UARTMux: case RCPC_PHYS: case RCPC_idString: case RCPC_intClear: case RCPC_intConfig: case RCPC_HCLKPrescale: case RCPC_periphClkCtrl: case TIMER0_LOAD: case TIMER0_VALUE: case TIMER1_LOAD: case TIMER1_VALUE: case TIMER1_CONTROL: case TIMER1_CLEAR: case TIMER2_CONTROL: case TIMER3_CONTROL: case UART1_PHYS + UARTIBRD: case UART1_PHYS + UARTLCR_H: // printf("%s(%x %x)\n", __func__, addr, data); break; case TIMER0_CONTROL: io.tcd_ctrl[0] = data; break; case TIMER0_CLEAR: io.intsr &= ~TC1OI; lh79520_update_int (state); break; case VIC_IntEnable: io.intmr = data; lh79520_update_int (state); break; case VIC_IntEnClear: io.intmr &= ~data; lh79520_update_int (state); break; case UART0_PHYS: case UART1_PHYS: /* The UART writes chars to console */ { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } break; case UART1_PHYS + UARTCR: io.uartcr = data; break; case UART1_PHYS + UARTIMSC: //5: TXIM 4: RXIM io.uartimsc = data; if (data & AMBA_UART_IS_TX) io.uartmis |= AMBA_UART_IS_TX; else io.uartmis &= ~AMBA_UART_IS_TX; UART2VIC (state); break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? printf ("SKYEYE:unknown io addr, %s(0x%08x, 0x%08x), pc %x \n", __func__, addr, data, state->Reg[15]); break; } } void lh79520_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { //some parts of kernel such as printascii use byte operation if (addr >= UART1_PHYS + UARTDR && addr <= UART1_PHYS + UARTICR) return lh79520_io_write_word (state, addr, data); else { printf ("SKYEYE: %s(%x %x) error\n", __func__, addr, data); SKYEYE_OUTREGS (stderr); system ("stty sane"); skyeye_exit (-1); } } void lh79520_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { printf ("SKYEYE: %s error %x %x\n", __func__, addr, data); skyeye_exit (-1); } void lh79520_mach_init (ARMul_State * state, machine_config_t * this_mach) { ARMul_SelectProcessor (state, ARM_v4_Prop); state->lateabtSig = HIGH; // state->Reg[1] = 999; //MACH_TYPE_LH79520EVB state->Reg[1] = 997; //MACH_TYPE_LH79520LPD this_mach->mach_io_do_cycle = lh79520_io_do_cycle; this_mach->mach_io_reset = lh79520_io_reset; this_mach->mach_io_read_byte = lh79520_io_read_byte; this_mach->mach_io_write_byte = lh79520_io_write_byte; this_mach->mach_io_read_halfword = lh79520_io_read_halfword; this_mach->mach_io_write_halfword = lh79520_io_write_halfword; this_mach->mach_io_read_word = lh79520_io_read_word; this_mach->mach_io_write_word = lh79520_io_write_word; this_mach->mach_update_int = lh79520_update_int; state->mach_io.instr = (ARMword *) & io.intsr; } ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/lh79520-hardware.h���������������������������������������������������0000644�0001750�0000144�00000026320�10541455476�017636� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * linux/include/asm-arm/arch-lh79520/hardware.h * * Copyright (C) 2001 Sharp Microelectronics of the Americas, Inc. * CAMAS, WA * Portions Copyright (C) 2002 Lineo, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * References: * (1) Sharp LH79520 Universal Microcontroller User's Guide, * Version 1.x, Sharp Microelectronics of the Americas, Inc. * */ #ifndef _BIT #define _BIT(n) (1 << (n)) #endif #ifndef _SBF #define _SBF(f,v) ((v) << (f)) #endif #ifndef _BITMASK #define _BITMASK(field_width) ( _BIT(field_width) - 1) #endif /* Hardware addresses of major areas. * *_START is the physical address * *_SIZE is the size of the region * *_BASE is the virtual address */ /* * we can do an identity mapping (V=P) of all of I/O * space, except for the VIC. * * One of the places you can find the VIC is at 0xffff0000, * which is the same place the interrupt vectors want to live, * so we'll leave a hole there, and use the VIC at it's other * address: 0xfffff000. */ #define APB_START 0xfffc0000 /* Physical address of APB I/O space */ #define APB_BASE 0xfffc0000 /* Virtual address of APB I/O space */ #define APB_SIZE 0x00026000 /* its size (up to 0xfffe6000) */ #define AHB_START 0xffff1000 /* Physical address of AHB I/O space */ #define AHB_BASE 0xffff1000 /* Virtual address of AHB I/O space */ #define AHB_SIZE 0x00004000 /* its size (up to 0xffff5000) */ #define VIC_START VIC_PHYS /* Physical address of VIC */ #define VIC_BASE 0xfffff000 /* Virtual address of VIC */ #define VIC_SIZE 0x1000 /* its size */ #define FLASH_START 0x40000000 /* Flash on SMC bank 0 */ #define FLASH_BASE 0xf4000000 #define FLASH_SIZE (4 * 1024 * 1024) #if defined(CONFIG_LPD_79520_10) #define LPD_CPLD_START 0x54200000 /* CPLD on SMC bank 5 */ #define LPD_CPLD_BASE 0xf5000000 #define LPD_CPLD_SIZE 0x01400000 #define SMC91c111_START 0x54000000 /* Ethernet on SMC bank 3 */ #define SMC91c111_BASE 0xf4800000 #define SMC91c111_SIZE 4096 #define IDE_START 0x50200000 /* CF/IDE on SMC bank 4 + lpd_cpld offset */ #define IDE_BASE 0xf6400000 #define IDE_SIZE 0x00002000 #endif #define UNUSED_START 0x58000000 /* unused on SMC bank 6 */ #define RESERVED_START 0x5C000000 /* reserved on SMC bank 7 */ #define INT_SRAM_START 0x60000000 /* on-chip SRAM */ #define INT_SRAM_BASE 0xf6800000 #define INT_SRAM_SIZE (32 * 1024) #define IO_START APB_START #define IO_BASE APB_BASE /* macro to get at IO space when running virtually */ #define IO_ADDRESS(phys) (phys) #define PCIO_BASE IO_BASE /********************************************************************** * AHB BASES *********************************************************************/ #define AHB_PHYS (0xFFFF0000) #define VIC_PHYS_MIRROR (AHB_PHYS + 0x0000) #define SMC_REGS_PHYS (AHB_PHYS + 0x1000) #define SDRAM_REGS_PHYS (AHB_PHYS + 0x2000) #define LCD_PHYS (AHB_PHYS + 0x4000) #define VIC_PHYS (AHB_PHYS + 0xF000) /********************************************************************** * APB PHYSS *********************************************************************/ #define APB_PHYS (0xFFFC0000) #define UART0_PHYS (APB_PHYS + 0x00000) #define UART1_PHYS (APB_PHYS + 0x01000) #define UART2_PHYS (APB_PHYS + 0x02000) #define PWM_PHYS (APB_PHYS + 0x03000) #define TIMER0_PHYS (APB_PHYS + 0x04000) #define TIMER1_PHYS (APB_PHYS + 0x05000) #define SSP_PHYS (APB_PHYS + 0x06000) #define GPIO3_PHYS (APB_PHYS + 0x1C000) #define GPIO2_PHYS (APB_PHYS + 0x1D000) #define GPIO1_PHYS (APB_PHYS + 0x1E000) #define GPIO0_PHYS (APB_PHYS + 0x1F000) #define RTC_PHYS (APB_PHYS + 0x20000) #define DMAC_PHYS (APB_PHYS + 0x21000) #define RCPC_PHYS (APB_PHYS + 0x22000) #define WDTIMER_PHYS (APB_PHYS + 0x23000) #define LCDICP_PHYS (APB_PHYS + 0x24000) #define IOCON_PHYS (APB_PHYS + 0x25000) /********************************************************************** * REMAPping *********************************************************************/ #define SDRAM_MEM_PHYS (0x20000000) #define SMC_MEM_PHYS (0x40000000) #define INTERNAL_MEM_PHYS (0x60000000) // DDD #if REMAP == 0 #define SMC_MIRROR_MEM_PHYS (0x00000000) // DDD #elif REMAP == 1 // DDD #define SDRAM_MIRROR_MEM_PHYS (0x00000000) // DDD #elif REMAP == 2 // DDD #define INTERNAL_MIRROR_MEM_PHYS (0x00000000) // DDD #else // DDD #error REMAP must be defined as 0, 1, or 2 // DDD #endif /********************************************************************** * xSPR bits *********************************************************************/ #define CORE_IRQ _BIT(7) #define CORE_FIQ _BIT(6) /********************************************************************** * SMC Memory Bank Address Space Bases *********************************************************************/ #define SMC_BANK0_PHYS (SMC_MEM_PHYS + 0x00000000) #define SMC_BANK1_PHYS (SMC_MEM_PHYS + 0x04000000) #define SMC_BANK2_PHYS (SMC_MEM_PHYS + 0x08000000) #define SMC_BANK3_PHYS (SMC_MEM_PHYS + 0x0C000000) #define SMC_BANK4_PHYS (SMC_MEM_PHYS + 0x10000000) #define SMC_BANK5_PHYS (SMC_MEM_PHYS + 0x14000000) #define SMC_BANK6_PHYS (SMC_MEM_PHYS + 0x18000000) #define SMC_BANK7_PHYS (SMC_MEM_PHYS + 0x1C000000) /********************************************************************** * SDRAMC Memory Bank Address Space Bases *********************************************************************/ #define SDRAM_BANK0_PHYS (SDRAM_MEM_PHYS + 0x00000000) #define SDRAM_BANK1_PHYS (SDRAM_MEM_PHYS + 0x08000000) /********************************************************************** * Vectored Interrupt Controller (VIC) *********************************************************************/ #define VICID_OFFSET (0xFE0) // DDD #define VIC ((VICREGS *)(VIC_PHYS)) // DDD #define VICID ((VICIDREGS *)(VIC_PHYS + VICID_OFFSET)) #define VIC_INT_TYPE_IRQ 0 #define VIC_INT_TYPE_FIQ 1 /* VIC Interrupt Sources */ #define VIC_EXTINT0 0 #define VIC_EXTINT1 1 #define VIC_EXTINT2 2 #define VIC_EXTINT3 3 #define VIC_EXTINT4 4 #define VIC_EXTINT5 5 #define VIC_EXTINT6 6 #define VIC_EXTINT7 7 #define VIC_SPEXTINT0 8 #define VIC_SPEXTINT1 9 #define VIC_SPEXTINT2 10 #define VIC_SPEXTINT3 11 #define VIC_CLCDC 12 #define VIC_SSPTXINTR 13 #define VIC_SSPRXINTR 14 #define VIC_SSPRORINTR 15 #define VIC_SSPINTR 16 #define VIC_TIMER0 17 #define VIC_TIMER1 18 #define VIC_TIMER2 19 #define VIC_TIMER3 20 #define VIC_UART0_RX 21 #define VIC_UART0_TX 22 #define VIC_UART0 23 #define VIC_UART1 24 #define VIC_UART2 25 #define VIC_DMA0 26 #define VIC_DMA1 27 #define VIC_DMA2 28 #define VIC_DMA3 29 #define VIC_RTC 30 #define VIC_WDT 31 /* VIC Vectors */ #define VIC_VECT_0 0 #define VIC_VECT_1 1 #define VIC_VECT_2 2 #define VIC_VECT_3 3 #define VIC_VECT_4 4 #define VIC_VECT_5 5 #define VIC_VECT_6 6 #define VIC_VECT_7 7 #define VIC_VECT_8 8 #define VIC_VECT_9 9 #define VIC_VECT_10 10 #define VIC_VECT_11 11 #define VIC_VECT_12 12 #define VIC_VECT_13 13 #define VIC_VECT_14 14 #define VIC_VECT_15 15 #define VIC_VECT_MAX VIC_VECT_15 #define VIC_VECT_DEFAULT ~(0) #define XTAL_IN 14745600 /* 14.7456 MHz crystal */ #define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ /********************************************************************** * UART'S *********************************************************************/ #define UARTID_OFFSET (0xFE0) // DDD #define UART0 ((UARTREGS *)(UART0_PHYS)) // DDD #define UART1 ((UARTREGS *)(UART1_PHYS)) // DDD #define UART2 ((UARTREGS *)(UART2_PHYS)) // DDD #define UART0ID ((UARTIDREGS *)(UART0_PHYS + UARTID_OFFSET)) // DDD #define UART1ID ((UARTIDREGS *)(UART1_PHYS + UARTID_OFFSET)) // DDD #define UART2ID ((UARTIDREGS *)(UART2_PHYS + UARTID_OFFSET)) /********************************************************************** * IRDA *********************************************************************/ // DDD #define IRDA0 ((UARTREGS *)(UART0_PHYS)) // DDD #define IRDA1 ((UARTREGS *)(UART1_PHYS)) // DDD #define IRDA2 ((UARTREGS *)(UART2_PHYS)) /********************************************************************** * Pulse Width Modulator (PWM) *********************************************************************/ // DDD #define PWMX_OFFSET (0x20) // DDD #define PWM ((PWMREGS *)(PWM_PHYS)) // DDD #define PWM0 ((PWMXREGS *)(PWM_PHYS)) // DDD #define PWM1 ((PWMXREGS *)(PWM_PHYS + PWMX_OFFSET)) /********************************************************************** * TIMER *********************************************************************/ // DDD #define TIMER2_OFFSET (0x20) // DDD #define TIMER0 ((TIMERREG *)(TIMER0_PHYS)) // DDD #define TIMER1 ((volatile TIMERREG *)(TIMER0_PHYS + TIMER2_OFFSET)) // DDD #define TIMER2 ((TIMERREG *)(TIMER1_PHYS)) // DDD #define TIMER3 ((TIMERREG *)(TIMER1_PHYS + TIMER2_OFFSET)) /********************************************************************** * Synchronous Serial Port (SSP) *********************************************************************/ // DDD #define SSP ((SSPREGS *)(SSP_PHYS)) /********************************************************************** * General Purpose Input/Output (GPIO) *********************************************************************/ // DDD #define GPIOA ((GPIOPAREGS *)(GPIO0_PHYS)) // DDD #define GPIOB ((GPIOPBREGS *)(GPIO0_PHYS)) // DDD #define GPIOC ((GPIOPAREGS *)(GPIO1_PHYS)) // DDD #define GPIOD ((GPIOPBREGS *)(GPIO1_PHYS)) // DDD #define GPIOE ((GPIOPAREGS *)(GPIO2_PHYS)) // DDD #define GPIOF ((GPIOPBREGS *)(GPIO2_PHYS)) // DDD #define GPIOG ((GPIOPAREGS *)(GPIO3_PHYS)) // DDD #define GPIOH ((GPIOPBREGS *)(GPIO3_PHYS)) /********************************************************************** * Real Time Clock (RTC) *********************************************************************/ // DDD #define RTC ((RTCREGS *)(RTC_PHYS)) /********************************************************************** * DMA Controller (DMAC) *********************************************************************/ // DDD #define DMAC ((DMACREGS *)(DMAC_PHYS)) /********************************************************************** * Reset, Clock, and Power Controller (RCPC) *********************************************************************/ // DDD #define RCPC ((RCPCREGS *)(RCPC_PHYS)) /********************************************************************** * Watchdog Timer (WDTIMER) *********************************************************************/ // DDD #define WDTIMER ((WDTIMERREGS *)(WDTIMER_PHYS)) /********************************************************************** * LCD Interface Control Processor (LCDICP) *********************************************************************/ // DDD #define LCDICP ((LCDICPREGS *)(LCDICP_PHYS)) /********************************************************************** * IOCON *********************************************************************/ // DDD #define IOCON ((IOCONREGS *)(IOCON_PHYS)) ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/sa1100.h�������������������������������������������������������������0000644�0001750�0000144�00000001260�10541455476�015732� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������#ifndef _SA1100_H_ #define _SA1100_H_ enum { RTC_ALARM_IRQ = (1 << 31), RTC_HZ_IRQ = (1 << 30), OS_IRQ_SHF = 26, UART3_IRQ = (1 << 17), }; enum { ICIP = 0x90050000, ICMR = 0x90050004, ICLR = 0x90050008, ICFP = 0x90050010, ICPR = 0x90050020, ICCR = 0x9005000C, RTAR = 0x90010000, RCNR = 0x90010004, RTTR = 0x90010008, RTSR = 0x90010010, OSMR0 = 0x90000000, OSMR1 = 0x90000004, OSMR2 = 0x90000008, OSMR3 = 0x9000000C, OSCR = 0x90000010, OSSR = 0x90000014, OWER = 0x90000018, OIER = 0x9000001C, /*UART3 */ UTCR0 = 0x80050000, UTCR1 = 0x80050004, UTCR2 = 0x80050008, UTCR3 = 0x8005000C, UTDR = 0x80050014, UTSR0 = 0x8005001C, UTSR1 = 0x80050020, }; #endif ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/s3c3410x.h�����������������������������������������������������������0000644�0001750�0000144�00000012320�10605545103�016200� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/************************************************************************/ /* S3C3410X Special Function Register Difinition */ /************************************************************************/ /* Modified and programmed by Yong-Hyeon Kim */ /* Description : 1999. 12. 20 first edited */ /************************************************************************/ #ifndef __40100_H__ #define __40100_H__ #define REGBASE 0x07ff0000 #define REGL(addr) (REGBASE+addr) #define REGW(addr) (REGBASE+addr) #define REGB(addr) (REGBASE+addr) /* System */ #define SYSCFG REGL(0x1000) #define EXTCON0 REGL(0x2030) #define EXTCON1 REGL(0x2034) #define EXTPOT REGW(0x203e) #define EXTDAT0 REGW(0x202c) #define EXTDAT1 REGW(0x202e) /* DMA0 Control */ #define DMASRC0 REGL(0x3000) #define DMADST0 REGL(0x3004) #define DMACNT0 REGL(0x3008) #define DMACON0 REGL(0x300c) /* DMA1 Control */ #define DMASRC1 REGL(0x4000) #define DMADST1 REGL(0x4004) #define DMACNT1 REGL(0x4008) #define DMACON1 REGL(0x400c) /* I/O Port */ #define PCON0 REGW(0xb010) #define PDAT0 REGB(0xb000) #define PUR0 REGB(0xb028) #define PCON1 REGW(0xb012) #define PDAT1 REGB(0xb001) #define PDR1 REGB(0xb029) #define PCON2 REGW(0xb014) #define PDAT2 REGB(0xb002) #define PUR2 REGB(0xb02a) #define PCON3 REGW(0xb016) #define PDAT3 REGB(0xb003) #define PUR3 REGB(0xb02b) #define PCON4 REGW(0xb018) #define PDAT4 REGB(0xb004) #define PDR4 REGB(0xb02c) #define PCON5 REGL(0xb01c) #define PDAT5 REGB(0xb005) #define PUR5 REGB(0xb02d) #define PCON6 REGL(0xb020) #define PDAT6 REGB(0xb006) #define PUR6 REGB(0xb02e) #define PCON7 REGW(0xb024) #define PDAT7 REGB(0xb007) #define PUR7 REGB(0xb02f) #define PCON8 REGB(0xb026) #define PDAT8 REGB(0xb008) #define PUR8 REGB(0xb03c) #define PCON9 REGB(0xb027) #define PDAT9 REGB(0xb009) #define EINTPND REGB(0xb031) #define EINTCON REGW(0xb032) #define EINTMOD REGL(0xb034) /* Timer 0 */ #define TDAT0 REGW(0x9000) #define TPRE0 REGB(0x9002) #define TCON0 REGB(0x9003) #define TCNT0 REGW(0x9006) /* Timer 1 */ #define TDAT1 REGW(0x9010) #define TPRE1 REGB(0x9012) #define TCON1 REGB(0x9013) #define TCNT1 REGW(0x9016) /* Timer 2 */ #define TDAT2 REGW(0x9020) #define TPRE2 REGB(0x9022) #define TCON2 REGB(0x9023) #define TCNT2 REGW(0x9026) /* Timer 3 */ #define TDAT3 REGB(0x9031) #define TPRE3 REGB(0x9032) #define TCON3 REGB(0x9033) #define TCNT3 REGB(0x9037) /* Timer 4 */ #define TDAT4 REGB(0x9041) #define TPRE4 REGB(0x9042) #define TCON4 REGB(0x9043) #define TCNT4 REGB(0x9047) #define TFCON REGB(0x904f) #define TFSTAT REGB(0x904e) #define TFB4 REGB(0x904b) #define TFHW4 REGW(0x904a) #define TFW4 REGL(0x9048) /* UART */ #define ULCON REGB(0x5003) #define UCON REGB(0x5007) #define USTAT REGB(0x500b) #define UFCON REGB(0x500f) #define UFSTAT REGB(0x5012) #define UTXH REGB(0x5017) #define UTXH_HW REGW(0x5016) #define UTXH_W REGL(0x5014) #define URXH REGB(0x501b) #define URXH_HW REGW(0x501a) #define URXH_W REGL(0x5018) #define UBRDIV REGW(0x501e) /* SIO 0 */ #define ITVCNT0 REGB(0x6000) #define SBRDR0 REGB(0x6001) #define SIODAT0 REGB(0x6002) #define SIOCON0 REGB(0x6003) /* SIO 1 */ #define ITVCNT1 REGB(0x7000) #define SBRDR1 REGB(0x7001) #define SIODAT1 REGB(0x7002) #define SIOCON1 REGB(0x7003) /* Interrupt Control */ #define INTMOD REGL(0xc000) #define INTPND REGL(0xc004) #define INTMSK REGL(0xc008) #define INTPRI0 REGL(0xc00c) #define INTPRI1 REGL(0xc010) #define INTPRI2 REGL(0xc014) #define INTPRI3 REGL(0xc018) #define INTPRI4 REGL(0xc01c) #define INTPRI5 REGL(0xc020) #define INTPRI6 REGL(0xc024) #define INTPRI7 REGL(0xc028) /* ADC */ #define ADCCON REGW(0x8002) #define ADCDAT REGW(0x8006) /* Basic Timer */ #define BTCON REGW(0xa002) #define BTCNT REGB(0xa007) /* IIC */ #define IICCON REGB(0xe000) #define IICSTAT REGB(0xe001) #define IICADD REGB(0xe003) #define IICDS REGB(0xe002) #define IICPS REGB(0xe004) #define IICPCNT REGB(0xe005) /* Power Manager */ #define SYSCON REGB(0xd003) /* RTC */ #define RTCCON REGB(0xa013) #define RTCALM REGB(0xa012) #define RINTCON REGB(0xa011) #define RINTPND REGB(0xa010) #define ALMSEC REGB(0xa033) #define ALMMIN REGB(0xa032) #define ALMHOUR REGB(0xa031) #define ALMDAY REGB(0xa037) #define ALMMON REGB(0xa036) #define ALMYEAR REGB(0xa035) #define BCDSEC REGB(0xa023) #define BCDMIN REGB(0xa022) #define BCDHOUR REGB(0xa021) #define BCDDAY REGB(0xa027) #define BCDDATE REGB(0xa020) #define BCDMON REGB(0xa026) #define BCDYEAR REGB(0xa025) #define INT_EINT0 (0) #define INT_EINT1 (1) #define INT_URX (2) #define INT_UTX (3) #define INT_UERR (4) #define INT_DMA0 (5) #define INT_DMA1 (6) #define INT_TOF0 (7) #define INT_TMC0 (8) #define INT_TOF1 (9) #define INT_TMC1 (10) #define INT_TOF2 (11) #define INT_TMC2 (12) #define INT_TOF3 (13) #define INT_TMC3 (14) #define INT_TOF4 (15) #define INT_TMC4 (16) #define INT_BT (17) #define INT_SIO0 (18) #define INT_SIO1 (19) #define INT_IIC (20) #define INT_RTCA (21) #define INT_RTCT (22) #define INT_TF (23) #define INT_EINT2 (24) #define INT_EINT3 (25) #define INT_EINT4 (26) #define INT_ADC (27) #define INT_EINT8 (28) #define INT_EINT9 (29) #define INT_EINT10 (30) #define INT_EINT11 (31) #endif /*__41000_H___*/ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/serial_amba.h��������������������������������������������������������0000644�0001750�0000144�00000010214�10541455476�017263� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * linux/include/asm-arm/hardware/serial_amba.h * * Internal header file for AMBA serial ports * * Copyright (C) ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H #define ASM_ARM_HARDWARE_SERIAL_AMBA_H /* ------------------------------------------------------------------------------- * From AMBA UART (PL010) Block Specification (ARM-0001-CUST-DSPC-A03) * ------------------------------------------------------------------------------- * UART Register Offsets. */ #define AMBA_UARTDR 0x00 /* Data read or written from the interface. */ #define AMBA_UARTRSR 0x04 /* Receive status register (Read). */ #define AMBA_UARTECR 0x04 /* Error clear register (Write). */ #define AMBA_UARTLCR_H 0x08 /* Line control register, high byte. */ #define AMBA_UARTLCR_M 0x0C /* Line control register, middle byte. */ #define AMBA_UARTLCR_L 0x10 /* Line control register, low byte. */ #define AMBA_UARTCR 0x14 /* Control register. */ #define AMBA_UARTFR 0x18 /* Flag register (Read only). */ #define AMBA_UARTIIR 0x1C /* Interrupt indentification register (Read). */ #define AMBA_UARTICR 0x1C /* Interrupt clear register (Write). */ #define AMBA_UARTILPR 0x20 /* IrDA low power counter register. */ #define AMBA_UARTRSR_OE 0x08 #define AMBA_UARTRSR_BE 0x04 #define AMBA_UARTRSR_PE 0x02 #define AMBA_UARTRSR_FE 0x01 #define AMBA_UARTFR_TXFF 0x20 #define AMBA_UARTFR_RXFE 0x10 #define AMBA_UARTFR_BUSY 0x08 #define AMBA_UARTFR_DCD 0x04 #define AMBA_UARTFR_DSR 0x02 #define AMBA_UARTFR_CTS 0x01 #define AMBA_UARTFR_TMSK (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY) #define AMBA_UARTCR_RTIE 0x40 #define AMBA_UARTCR_TIE 0x20 #define AMBA_UARTCR_RIE 0x10 #define AMBA_UARTCR_MSIE 0x08 #define AMBA_UARTCR_IIRLP 0x04 #define AMBA_UARTCR_SIREN 0x02 #define AMBA_UARTCR_UARTEN 0x01 #define AMBA_UARTLCR_H_WLEN_8 0x60 #define AMBA_UARTLCR_H_WLEN_7 0x40 #define AMBA_UARTLCR_H_WLEN_6 0x20 #define AMBA_UARTLCR_H_WLEN_5 0x00 #define AMBA_UARTLCR_H_FEN 0x10 #define AMBA_UARTLCR_H_STP2 0x08 #define AMBA_UARTLCR_H_EPS 0x04 #define AMBA_UARTLCR_H_PEN 0x02 #define AMBA_UARTLCR_H_BRK 0x01 #define AMBA_UARTIIR_RTIS 0x08 #define AMBA_UARTIIR_TIS 0x04 #define AMBA_UARTIIR_RIS 0x02 #define AMBA_UARTIIR_MIS 0x01 #define ARM_BAUD_460800 1 #define ARM_BAUD_230400 3 #define ARM_BAUD_115200 7 #define ARM_BAUD_57600 15 #define ARM_BAUD_38400 23 #define ARM_BAUD_19200 47 #define ARM_BAUD_14400 63 #define ARM_BAUD_9600 95 #define ARM_BAUD_4800 191 #define ARM_BAUD_2400 383 #define ARM_BAUD_1200 767 #define AMBA_UARTRSR_ANY (AMBA_UARTRSR_OE|AMBA_UARTRSR_BE|AMBA_UARTRSR_PE|AMBA_UARTRSR_FE) #define AMBA_UARTFR_MODEM_ANY (AMBA_UARTFR_DCD|AMBA_UARTFR_DSR|AMBA_UARTFR_CTS) #endif /* */ ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/ep9312.h�������������������������������������������������������������0000644�0001750�0000144�00000007347�10541455476�015764� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ep9312.h - definitions of "ep9312" machine for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 11/04/2004 initial version * define TC struct * walimis <wlm@student.dlut.edu.cn> * */ #ifndef __EP931200_H_ #define __EP931200_H_ /******************************************** * Timer Count definition ********************************************/ #define EP9312_TC_BASE1 (0x80810000) #define EP9312_TC_BASE2 (0x80810020) #define EP9312_TC_BASE3 (0x80810080) #define EP9312_TC_BASE4 (0x80810060) #define EP9312_TC_SIZE 0x10 /* Timer Count I/O register * */ #define TC_LOAD 0x0 #define TC_VALUE 0x4 #define TC_CTL 0x8 #define TC_CLEAR 0xC #define TC_VALUELOW 0x0 #define TC_VALUEHIGH 0x4 /* TC interrupt use "sys" interrupt * */ #define EP9312_ID_SYS (0x1 << 1) // System Peripheral #define TC_CTL_CLKSEL (0x1 << 3) // (TC) Control: CLKSEL bit #define TC_CTL_MODE (0x1 << 6) // (TC) Control: Mode bit #define TC_CTL_ENABLE (0x1 << 7) // (TC) Control: Enable bit struct ep9312_tc_io { /* I/O register * */ u32 load; /* Load Register */ u32 value; /* Value Register */ u32 ctl; /* Control Register */ u32 clear; /* Clear Register */ u32 mod_value; /* TC1 and TC2: 0xffff; TC3: 0xffffffff */ }; /******************************************** * UART definition ********************************************/ /* I/O register Offset * */ #define UART_DR 0x00 #define UART_RSR 0x04 /* Read */ #define UART_ECR 0x04 /* Write */ #define UART_CR_H 0x08 #define UART_CR_M 0x0C #define UART_CR_L 0x10 #define UART_CR 0x14 #define UART_FR 0x18 #define UART_IIR 0x1C /* Read */ #define UART_ICR 0x1C /* Write */ #define UART_ILPR 0x20 #define UART_DMACR 0x28 #define UART_TCR 0x80 #define UART_TISR 0x88 #define UART_TOCR 0x8C #define UART_TMR 0x84 #define UART_MCR 0x100 /* Modem Control Reg */ #define UART_MSR 0x104 /* Modem Status Reg */ #define UART_HDLCCR 0x20C /* HDLC Registers */ #define UART_HDLCAMV 0x210 /* HDLC Registers */ #define UART_HDLCAMSK 0x214 /* HDLC Registers */ #define UART_HDLCCRIB 0x218 /* HDLC Registers */ #define UART_HDLCSR 0x21C /* HDLC Registers */ /* default base address * */ #define EP9312_UART_BASE1 (0x808C0000) #define EP9312_UART_BASE2 (0x808D0000) #define EP9312_UART_BASE3 (0x808E0000) #define EP9312_UART_SIZE 0x10000 struct ep9312_uart_io { /* I/O register * */ u32 dr; u32 rsr; u32 ecr; u32 cr_h; u32 cr_m; u32 cr_l; u32 cr; u32 fr; u32 iir; u32 icr; u32 ilpr; u32 dmacr; u32 tcr; u32 tisr; u32 tocr; u32 tmr; u32 mcr; u32 msr; u32 sysflg; }; #endif /*__EP931200_H_ */ �����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/ns9750.h�������������������������������������������������������������0000644�0001750�0000144�00000015703�10541455476�016001� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* ns9750.h - definitions of "ns975000" machine for skyeye Copyright (C) 2004 Skyeye Develop Group for help please send mail to <skyeye-developer@lists.gro.clinux.org> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* * 05/29/2004 initial version * * walimis <wlm@student.dlut.edu.cn> * */ #ifndef __NS9750_H_ #define __NS9750_H_ /******************************************** * Advanced Interrupt Controller(AIC) ********************************************/ #define AT91RM92_AIC_BASE0 (0xfffff000) #define AT91RM92_AIC_SIZE 0x1000 #define AIC_SMR AT91RM92_AIC_BASE0+(0) // Source Mode Register #define AIC_SVR AT91RM92_AIC_BASE0+(128) // Source Vector Register #define AIC_IVR AT91RM92_AIC_BASE0+(256) // IRQ Vector Register #define AIC_FVR AT91RM92_AIC_BASE0+(260) // FIQ Vector Register #define AIC_ISR AT91RM92_AIC_BASE0+(264) // Interrupt Status Register #define AIC_IPR AT91RM92_AIC_BASE0+(268) // Interrupt Pending Register #define AIC_IMR AT91RM92_AIC_BASE0+(272) // Interrupt Mask Register #define AIC_CISR AT91RM92_AIC_BASE0+(276) // Core Interrupt Status Register #define AIC_IECR AT91RM92_AIC_BASE0+(288) // Interrupt Enable Command Register #define AIC_IDCR AT91RM92_AIC_BASE0+(292) // Interrupt Disable Command Register #define AIC_ICCR AT91RM92_AIC_BASE0+(296) // Interrupt Clear Command Register #define AIC_ISCR AT91RM92_AIC_BASE0+(300) // Interrupt Set Command Register #define AIC_EOICR AT91RM92_AIC_BASE0+(304) // End of Interrupt Command Register #define AIC_SPU AT91RM92_AIC_BASE0+(308) // Spurious Vector Register #define AIC_DCR AT91RM92_AIC_BASE0+(312) // Debug Control Register (Protect) #define AIC_FFER AT91RM92_AIC_BASE0+(320) // Fast Forcing Enable Register #define AIC_FFDR AT91RM92_AIC_BASE0+(324) // Fast Forcing Disable Register #define AIC_FFSR AT91RM92_AIC_BASE0+(328) // Fast Forcing Status Register /******************************************** * System Timer definition ********************************************/ #define AT91RM92_ST_BASE0 (0xfffffd00) #define AT91RM92_ST_SIZE 0x100 /* System I/O register * */ #define ST_CR 0x0 #define ST_PIMR 0x4 #define ST_WDMR 0x8 #define ST_RTMR 0xC #define ST_SR 0x10 #define ST_IER 0x14 #define ST_IDR 0x18 #define ST_IMR 0x1C #define ST_RTAR 0x20 #define ST_CRTR 0x24 /* ST interrupt use "sys" interrupt * */ #define AT91RM92_ID_SYS (0x1 << 1) // System Peripheral #define AT91RM92_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt #define AT91RM92_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow #define AT91RM92_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment #define AT91RM92_ST_ALMS (0x1 << 3) // (ST) Alarm Status struct ns9750_st_io { /* I/O register * */ u32 cr; /* control */ u32 pimr; /* Period Interval Mode */ u32 wdmr; /* Watchdog Mode Register */ u32 rtmr; /* Real-time Mode Register */ u32 sr; /* Status Register */ u32 ier; /* Interrupt Enable Register */ u32 idr; /* Interrupt Disable Register */ u32 imr; /* Interrupt Mask Register */ u32 rtar; /* Real-time Alarm Register */ u32 crtr; /* Current Real-time Register */ u16 piv_dc; /*Period Interval Value down count */ u16 wdv_dc; /*Watchdog Counter Value down count */ u16 rtpres_dc; /*Real-time Timer Prescaler Value down count */ }; /******************************************** * USART definition ********************************************/ /* I/O register Offset * */ #define US_CR 0x0 #define US_MR 0x4 #define US_IER 0x8 #define US_IDR 0xC #define US_IMR 0x10 #define US_CSR 0x14 #define US_RHR 0x18 #define US_THR 0x1C #define US_BRGR 0x20 #define US_RTOR 0x24 #define US_TTGR 0x28 #define US_FIDI 0x40 #define US_NER 0x44 #define US_IF 0x4C #define AT91RM92_US_RXRDY ( 0x1 << 0) // (USART) RXRDY Interrupt #define AT91RM92_US_TXRDY ( 0x1 << 1) // (USART) TXRDY Interrupt #define AT91RM92_US_RXBRK ( 0x1 << 2) // (USART) Break Received/End of Break #define AT91RM92_US_ENDRX ( 0x1 << 3) // (USART) End of Receive Transfer Interrupt #define AT91RM92_US_ENDTX ( 0x1 << 4) // (USART) End of Transmit Interrupt #define AT91RM92_US_OVRE ( 0x1 << 5) // (USART) Overrun Interrupt #define AT91RM92_US_FRAME ( 0x1 << 6) // (USART) Framing Error Interrupt #define AT91RM92_US_PARE ( 0x1 << 7) // (USART) Parity Error Interrupt #define AT91RM92_US_TIMEOUT ( 0x1 << 8) // (USART) Receiver Time-out #define AT91RM92_US_TXEMPTY ( 0x1 << 9) // (USART) TXEMPTY Interrupt #define AT91RM92_US_ITERATION ( 0x1 << 10) // (USART) Max number of Repetitions Reached #define AT91RM92_US_TXBUFE ( 0x1 << 11) // (USART) TXBUFE Interrupt #define AT91RM92_US_RXBUFF ( 0x1 << 12) // (USART) RXBUFF Interrupt #define AT91RM92_US_NACK ( 0x1 << 13) // (USART) Non Acknowledge #define AT91RM92_US_RIIC ( 0x1 << 16) // (USART) Ring INdicator Input Change Flag #define AT91RM92_US_DSRIC ( 0x1 << 17) // (USART) Data Set Ready Input Change Flag #define AT91RM92_US_DCDIC ( 0x1 << 18) // (USART) Data Carrier Flag #define AT91RM92_US_CTSIC ( 0x1 << 19) // (USART) Clear To Send Input Change Flag /* default base address for uart0 and uart1 * ns975000 use "USART" instead of "UART". we here use name "UART". * */ #define AT91RM92_UART_BASE0 (0xfffc0000) #define AT91RM92_UART_BASE1 (0xfffc4000) #define AT91RM92_UART_SIZE 0x4000 #define AT91RM92_ID_US0 ( 0x1 << 6) // USART 0 #define AT91RM92_ID_US1 ( 0x1 << 7) // USART 1 #define AT91RM92_ID_US2 ( 0x1 << 8) // USART 2 #define AT91RM92_ID_US3 ( 0x1 << 9) // USART 3 struct ns9750_uart_io { /* I/O register * */ u32 cr; /* control */ u32 mr; /* mode */ u32 ier; /* interrupt enable */ u32 idr; /* interrupt disable */ u32 imr; /* interrupt mask */ u32 csr; /* channel status */ u32 rhr; /* receive holding */ u32 thr; /* tramsmit holding */ u32 brgr; /* baud rate generator */ u32 rtor; /* rx time-out */ u32 ttgr; /* tx time-guard */ u32 fidi; u32 ner; u32 us_if; u32 sysflg; }; #endif /*__NS9750_H_ */ �������������������������������������������������������������skyeye-1.2.5_REL/arch/arm/mach/ep7212.h�������������������������������������������������������������0000644�0001750�0000144�00000004570�10541455476�015754� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������/* * linux/include/asm-arm/hardware/ep7212.h * * This file contains the hardware definitions of the EP7212 internal * registers. * * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_EP7212_H #define __ASM_HARDWARE_EP7212_H /* * define EP7212_BASE to be the base address of the region * you want to access. */ #define EP7212_PHYS_BASE (0x80000000) #ifndef __ASSEMBLY__ #define ep_readl(off) __raw_readl(EP7212_BASE + (off)) #define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off)) #endif /* * These registers are specific to the EP7212 only */ #define DAIR 0x2000 #define DAIR0 0x2040 #define DAIDR1 0x2080 #define DAIDR2 0x20c0 #define DAISR 0x2100 #define SYSCON3 0x2200 #define INTSR3 0x2240 #define INTMR3 0x2280 #define LEDFLSH 0x22c0 #define DAIR_DAIEN (1 << 16) #define DAIR_ECS (1 << 17) #define DAIR_LCTM (1 << 19) #define DAIR_LCRM (1 << 20) #define DAIR_RCTM (1 << 21) #define DAIR_RCRM (1 << 22) #define DAIR_LBM (1 << 23) #define DAIDR2_FIFOEN (1 << 15) #define DAIDR2_FIFOLEFT (0x0d << 16) #define DAIDR2_FIFORIGHT (0x11 << 16) #define DAISR_RCTS (1 << 0) #define DAISR_RCRS (1 << 1) #define DAISR_LCTS (1 << 2) #define DAISR_LCRS (1 << 3) #define DAISR_RCTU (1 << 4) #define DAISR_RCRO (1 << 5) #define DAISR_LCTU (1 << 6) #define DAISR_LCRO (1 << 7) #define DAISR_RCNF (1 << 8) #define DAISR_RCNE (1 << 9) #define DAISR_LCNF (1 << 10) #define DAISR_LCNE (1 << 11) #define DAISR_FIFO (1 << 12) #define SYSCON3_ADCCON (1 << 0) #define SYSCON3_DAISEL (1 << 3) #define SYSCON3_ADCCKNSEN (1 << 4) #define SYSCON3_FASTWAKE (1 << 8) #define SYSCON3_DAIEN (1 << 9) #endif /* __ASM_HARDWARE_EP7212_H */ ����������������������������������������������������������������������������������������������������������������������������������������skyeye-1.2.5_REL/aclocal.m4�������������������������������������������������������������������������0000644�0001750�0000144�00000076150�11023514463�014106� 0����������������������������������������������������������������������������������������������������ustar �ksh�����������������������������users������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������# generated automatically by aclocal 1.10 -*- Autoconf -*- # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, # 2005, 2006 Free Software Foundation, Inc. # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. m4_if(m4_PACKAGE_VERSION, [2.61],, [m4_fatal([this file was generated for autoconf 2.61. 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