pax_global_header00006660000000000000000000000064116704355230014520gustar00rootroot0000000000000052 comment=8052aabdd159bc9050e7dc264f33782c5acce05f .gitignore000066400000000000000000000001761167043552300130600ustar00rootroot00000000000000*.o *.P x86info AMD/fam10h.h AMD/fam11h.h AMD/fam12h.h AMD/fam14h.h AMD/fam15h.h AMD/k8.h generic_msr.h lsmsr x86info-1.*.tgz AMD/000077500000000000000000000000001167043552300114655ustar00rootroot00000000000000AMD/AMD.h000066400000000000000000000010451167043552300122370ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * AMD specific prototypes. */ #ifndef _AMD_H #define _AMD_H extern void decode_athlon_machine_check(int cpunum); extern void dump_athlon_MSR(struct cpudata *cpu); extern void dump_k6_MSR (struct cpudata *cpu); extern void decode_powernow (struct cpudata *cpu); extern void show_amd_bugs(struct cpudata *cpu); extern void dump_PSB(struct cpudata *cpu, unsigned int maxfid, unsigned int startvid); #define MSR_CLKCTL 0xc001001b #endif /* _AMD_H */ AMD/MSR-Athlon.c000066400000000000000000000010171167043552300135140ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * AMD-Athlon specific MSR information */ #include #include #include #include "../x86info.h" #include "AMD.h" void dump_athlon_MSR(struct cpudata *cpu) { if (!user_is_root) return; dumpmsr(cpu->number, 0x2A, 32); dumpmsr(cpu->number, 0xC0000080, 32); dumpmsr(cpu->number, 0xC0010010, 32); dumpmsr(cpu->number, 0xC0010015, 32); dumpmsr(cpu->number, MSR_CLKCTL, 32); printf("\n"); } AMD/MSR-K6.c000066400000000000000000000040311167043552300125460ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * AMD-K6 specific MSR information * See 21329h1.pdf for more details. */ #include #include #include #include "../x86info.h" #include "AMD.h" void dump_k6_MSR (struct cpudata *cpu) { unsigned long long val=0; if (!user_is_root) return; dumpmsr(cpu->number, 0xC0000082, 32); /* Original K6 or K6-2 (old core). */ if ((cpu->model < 8) || ((cpu->model == 8) && (cpu->stepping < 8))) { if (read_msr (cpu->number, 0xC0000082, &val) == 1) { printf("Write allocate enable limit: %dMbytes\n", (int) ((val & 0x7e) >>1) * 4); printf("Write allocate 15-16M bytes: %s\n", val & 1 ? "enabled" : "disabled"); } else { printf("Couldn't read WHCR register.\n"); } } /* K6-2 core (Stepping 8-F), K6-III or later. */ if ((cpu->model > 8) || ((cpu->model == 8) && (cpu->stepping >= 8))) { if (read_msr (cpu->number, 0xC0000082, &val) == 1) { if (!(val & (0x3ff << 22))) printf("Write allocate disabled\n"); else { printf("Write allocate enable limit: %dMbytes\n", (int) ((val >> 22) & 0x3ff) * 4); printf("Write allocate 15-16M bytes: %s\n", val & (1<<16) ? "enabled" : "disabled"); } } else { printf("Couldn't read WHCR register.\n"); } } /* Dump EWBE register on K6-2 & K6-3 */ if ((cpu->family == 5) && (cpu->model >= 8)) { if (read_msr (cpu->number, 0xC0000080, &val) == 1) { if (val & (1<<0)) printf("System call extension present.\n"); if (val & (1<<1)) printf("Data prefetch enabled.\n"); else printf("Data prefetch disabled.\n"); printf("EWBE mode: "); switch ((val & (1<<2|1<<3|1<<4))>>2) { case 0: printf("strong ordering (slowest performance)\n"); break; case 1: printf("speculative disable (close to best performance)\n"); break; case 2: printf("invalid\n"); break; case 3: printf("global disable (best performance)\n"); break; } } else { printf("Couldn't read EFER register.\n"); } } printf("\n"); } AMD/bugs.c000066400000000000000000000015111167043552300125670ustar00rootroot00000000000000/* * (C) 2002 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * AMD-specific errata information */ #include #include #include #include "../x86info.h" #include "AMD.h" static void show_k7_bugs(struct cpudata *cpu) { unsigned long long val; /* As per 27212 0.2 - Some newer athlons are more robust with CLK_CTL reprogrammed to 0x20000000 instead of 0x60000000 */ if (tuple(cpu) > 0x681) { if (read_msr (cpu->number, MSR_CLKCTL, &val) == 1) { if ((val & 0xfff00000) != 0x20000000) { printf("CLK_CTL is programmed to %08llx, instead of %08llx\n", val, ((val&~0xfff00000)|0x20000000)); } } } } void show_amd_bugs(struct cpudata *cpu) { switch (cpu->family) { /* Athlons. */ case 6: show_k7_bugs(cpu); break; default: break; } } AMD/dumppsb.c000066400000000000000000000056251167043552300133130ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * PSB decoding routines. */ #include #include #include #include #include #include #include #include "../x86info.h" #include "AMD.h" #include "powernow.h" #define START 0x000c0000L #define END 0x000ffff0L #define ROMSIZE (END-START)+1 struct psb_s { u8 signature[10]; u8 tableversion; u8 flags; u16 settlingtime; u8 reserved1; u8 numpst; }; struct pst_s { u32 cpuid; u8 fsbspeed; u8 maxfid; u8 startvid; u8 numpstates; }; void dump_PSB(struct cpudata *cpu, unsigned int maxfid, unsigned int startvid) { int fd, i, j; char *p; struct psb_s *psb; struct pst_s *pst; int numpstates; unsigned int fid, vid; fd=open("/dev/mem", O_RDONLY); if (fd == -1) { perror("/dev/mem"); return; } p = mmap(NULL, ROMSIZE, PROT_READ, MAP_SHARED, fd, START); if (p == (void *)-1) { perror("mmap() error"); if (close(fd)==-1) { perror("close"); exit(EXIT_FAILURE); } return; } for (i=0; itableversion); if (psb->tableversion != 0x12) { printf("Sorry, only v1.2 tables supported right now\n"); goto out; } printf("Flags: 0x%x ", (unsigned int) psb->flags); if ((psb->flags & 1)==0) { printf("(Mobile voltage regulator)\n"); } else { printf("(Desktop voltage regulator)\n"); } printf("Settling Time: %d microseconds.\n", (int)psb->settlingtime); printf("Has %d PST tables. (Only dumping ones relevant to this CPU).\n", (int)psb->numpst); p += sizeof (struct psb_s); for (i=0 ; inumpst; i++) { pst = (struct pst_s *) p; numpstates = pst->numpstates; if ((etuple(cpu) == pst->cpuid) && (maxfid==pst->maxfid) && (startvid==pst->startvid)) { printf(" PST:%d (@%p)\n", i, pst); printf(" cpuid: 0x%x\t", pst->cpuid); printf(" fsb: %d\t", (int)pst->fsbspeed); printf(" maxFID: 0x%x\t", (unsigned int)pst->maxfid); printf(" startvid: 0x%x\n", (unsigned int)pst->startvid); printf(" num of p states in this table: %d\n", numpstates); p = (char *) pst + sizeof (struct pst_s); for (j=0 ; jfsbspeed * fid_codes[fid]); vid = *p++; printf("VID: 0x%x (%0.3fV)\n", vid, mobile_vid_table[vid]); } printf("\n"); } else { p = (char *) pst + sizeof (struct pst_s); for (j=0 ; j # # Copyright (C) 2008, 2009 Advanced Micro Devices, Inc. # This file contains information from: # - "31116 Rev 3.48 - April 2010, BIOS and Kernel Developer's Guide (BKDG) # for AMD Family 10h Processors" # See scripts/createheader.py for the general format of this register # definitions. {LSMCAaddr=0x0000;load-store MCA address ADDR:48 :16 } # alias of MC3_ADDR # to be updated 24-31 bits 8:15 of syndrome {LSMCAstatus=0x0001;load-store MCE status ErrorCode:16 ErrorCodeExt:4 :25 UECC:1 CECC:1 SYND:8 :2 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } # alias of MC3_STATUS {TSC=0x0010;time-stamp counter TSC:64 } {APIC_BASE=0x001b;APIC base address :8 BSC:1 :2 ApicEn:1 ApicBar:36 :16 } {EBL_CR_POWERON=0x002a;cluster ID :16 ClusterID:2 :46 } {PATCH_LEVEL=0x008b;microcode patch level PATCH_LEVEL:32 :32 } {MTRRcap=0x00fe;MTRR capabilities MtrrCapVCnt:8 MtrrCapFix:1 :1 MtrrCapWc:1 :53 } {SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector SYSENTER_CS:16 :48 } {SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer SYSENTER_ESP:32 :32 } {SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer SYSENTER_EIP:32 :32 } {MCG_CAP=0x0179;global MC capabilities Count:8 MCG_CTL_P:1 :55 } {MCG_STAT=0x017a;global MC status RIPV:1 EIPV:1 MCIP:1 :61 } {MCG_CTL=0x017b;global MC control DCE:1 ICE:1 BUE:1 LSE:1 NBE:1 FRE:1 :58 } {DBG_CTL_MSR=0x01d9;debug control LBR:1 BTF:1 PB0:1 PB1:1 PB2:1 PB3:1 :58 } {BR_FROM=0x01db;last branch from IP LastBranchFromIP:64 } {BR_TO=0x01dc;last branch to IP LastBranchToIP:64 } {LastExceptionFromIP=0x01dd;last exception from IP LastIntFromIP:64 } {LastExceptionToIP=0x01de;last exception to IP LastIntToIP:64 } {MTRRphysBase0=0x0200;base of variable-size MTRR (0) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask0=0x0201;mask of variable-size MTRR (0) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase1=0x0202;base of variable-size MTRR (1) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask1=0x0203;mask of variable-size MTRR (1) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase2=0x0204;base of variable-size MTRR (2) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask2=0x0205;mask of variable-size MTRR (2) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase3=0x0206;base of variable-size MTRR (3) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask3=0x0207;mask of variable-size MTRR (3) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase4=0x0208;base of variable-size MTRR (4) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask4=0x0209;mask of variable-size MTRR (4) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase5=0x020a;base of variable-size MTRR (5) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask5=0x020b;mask of variable-size MTRR (5) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase6=0x020c;base of variable-size MTRR (6) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask6=0x020d;mask of variable-size MTRR (6) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase7=0x020e;base of variable-size MTRR (7) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask7=0x020f;mask of variable-size MTRR (7) :11 Valid:1 PhysMask:36 :16 } {MTRRfix64K_00000=0x0250;fixed range MTRR 0xxxxType:8 1xxxxType:8 2xxxxType:8 3xxxxType:8 4xxxxType:8 5xxxxType:8 6xxxxType:8 7xxxxType:8 } {MTRRfix16K_80000=0x0258;fixed range MTRR 80xxxType:8 84xxxType:8 88xxxType:8 8CxxxType:8 90xxxType:8 94xxxType:8 98xxxType:8 9CxxxType:8 } {MTRRfix16K_A0000=0x0259;fixed range MTRR A0xxxType:8 A4xxxType:8 A8xxxType:8 ACxxxType:8 B0xxxType:8 B4xxxType:8 B8xxxType:8 BCxxxType:8 } {MTRRfix4K_C0000=0x0268;fixed range MTRR C0xxxType:8 C1xxxType:8 C2xxxType:8 C3xxxType:8 C4xxxType:8 C5xxxType:8 C6xxxType:8 C7xxxType:8 } {MTRRfix4K_C8000=0x0269;fixed range MTRR C8xxxType:8 C9xxxType:8 CAxxxType:8 CBxxxType:8 CCxxxType:8 CDxxxType:8 CExxxType:8 CFxxxType:8 } {MTRRfix4K_D0000=0x026a;fixed range MTRR D0xxxType:8 D1xxxType:8 D2xxxType:8 D3xxxType:8 D4xxxType:8 D5xxxType:8 D6xxxType:8 D7xxxType:8 } {MTRRfix4K_D8000=0x026b;fixed range MTRR D8xxxType:8 D9xxxType:8 DAxxxType:8 DBxxxType:8 DCxxxType:8 DDxxxType:8 DExxxType:8 DFxxxType:8 } {MTRRfix4K_E0000=0x026c;fixed range MTRR E0xxxType:8 E1xxxType:8 E2xxxType:8 E3xxxType:8 E4xxxType:8 E5xxxType:8 E6xxxType:8 E7xxxType:8 } {MTRRfix4K_E8000=0x026d;fixed range MTRR E8xxxType:8 E9xxxType:8 EAxxxType:8 EBxxxType:8 ECxxxType:8 EDxxxType:8 EExxxType:8 EFxxxType:8 } {MTRRfix4K_F0000=0x026e;fixed range MTRR F0xxxType:8 F1xxxType:8 F2xxxType:8 F3xxxType:8 F4xxxType:8 F5xxxType:8 F6xxxType:8 F7xxxType:8 } {MTRRfix4K_F8000=0x026f;fixed range MTRR F8xxxType:8 F9xxxType:8 FAxxxType:8 FBxxxType:8 FCxxxType:8 FDxxxType:8 FExxxType:8 FFxxxType:8 } {PAT=0x0277;page attribute table PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 } {MTRRdefType=0x02ff;MTRR default memory type MemType:8 :2 MtrrDefTypeFixEn:1 MtrrDefTypeEn:1 :52 } {MC0_CTL=0x0400;data cache MC control ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC0_STATUS=0x0401;data cache MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 :8 Scrub:1 :4 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC0_ADDR=0x0402;data cache MC address ADDR:48 :16 } {MC0_MISC=0x0403;data cache MC miscellaneous :64 } {MC1_CTL=0x0404;instruction cache MC control ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC1_STATUS=0x0405;instruction cache MC status ErrorCode:16 ErrorCodeExt:4 :25 UECC:1 CECC:1 :10 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC1_ADDR=0x0406;instruction cache MC address ADDR:48 :16 } {MC1_MISC=0x0407;instruction cache MC miscellaneous :64 } {MC2_CTL=0x0408;bus unit MC control SRDE_HP:1 SRDE_TLB:1 SRDE_ALL:1 L2T_PAR:1 L2T_CECC:1 L2T_UECC:1 L2D_PAR:1 L2D_CECC:1 L2D_UECC:1 :1 VB_PAR:1 PDC_PAR:1 :52 } {MC2_STATUS=0x0409;bus unit MC status ErrorCode:16 ErrorCodeExt:4 :20 Scrub:1 :4 UECC:1 CECC:1 :10 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC2_ADDR=0x040a;bus unit MC address register ADDR:48 :16 } {MC2_MISC=0x040b;bus unit MC miscellaneous :64 } {MC3_CTL=0x040c;load store unit MC control SRDE_L:1 SRDE_S:1 :62 } {MC3_STATUS=0x040d;load store unit MC status ErrorCode:16 ErrorCodeExt:4 :25 UECC:1 CECC:1 :10 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC3_ADDR=0x040e;load store unit MC address ADDR:48 :16 } {MC3_MISC=0x040f;load store unit MC miscellaneous :64 } {MC4_CTL=0x0410;northbridge MC control CECCEn:1 UECCEn:1 CrcErr0En:1 CrcErr1En:1 CrcErr2En:1 SyncPkt0En:1 SyncPkt1En:1 SyncPkt2En:1 MstrAbrtEn:1 TgtAbrtEn:1 GartTblWkEn:1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 L3ArrayCorEn:1 L3ArrayUCEn:1 HtProtEn:1 HtDataEn:1 DramParEn:1 RtryHt0En:1 RtryHt1En:1 RtryHt2En:1 RtryHt3En:1 CrcErr3En:1 SyncPkt3En:1 McaUsPwDatErrEn:1 NbArrayParEn:1 TblWlkDatErrEn:1 :36 } {MC4_STATUS=0x0411;northbridge MC status ErrorCode:16 ErrorCodeExt:5 :3 Syndrome:8 ErrCpu:4 LDTLink0:1 LDTLink1:1 LDTLink2:1 LDTLink3:1 Scrub:1 SubLink:1 McaStatSubCache:2 :1 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Over:1 Val:1 } {MC4_ADDR=0x0412;northbridge MC address :1 ErrAddr:47 :16 } {MC4_MISC0=0x0413;northbridge MC misc (thresholding) (0 - DRAM) :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 IntType:2 CntEn:1 LvtOffset:4 :5 Locked:1 CntP:1 Valid:1 } {MC5_CTL=0x0414;fixed issue reorder buffer MC control CPUWDT:1 :63 } {MC5_STATUS=0x0415;fixed issue reorder buffer MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 :8 Scrub:1 :4 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC5_ADDR=0x0416;fixed issue reorder buffer MC address ADDR:48 :16 } {MC5_MISC=0x0417;fixed issue reorder buffer MC miscellaneous State:12 :52 } {EFER=0xc0000080;extended feature enable SYSCALL:1 :7 LME:1 :1 LMA:1 NXE:1 SVME:1 LMSLE:1 FFXSE:1 :49 } {STAR=0xc0000081;SYSCALL target address Target:32 SysCallSel:16 SysRetSel:16 } {STAR64=0xc0000082;long mode SYSCALL target address LSTAR:64 } {STARCOMPAT=0xc0000083;compat mode SYSCALL target address CSTAR:64 } {SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask MASK:32 :32 } {FS_BASE=0xc0000100;FS base FS_BASE:64 } {GS_BASE=0xc0000101;GS base GS_BASE:64 } {KernelGSbase=0xc0000102;kernel GS base KernelGSBase:64 } {TSC_AUX=0xc0000103;auxiliary time stamp counter data TscAux:32 :32 } {MC4_MISC1=0xc0000408;northbridge MC misc (thresholding) (1 - link) :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 IntType:2 CntEn:1 LvtOffset:4 :5 Locked:1 CntP:1 Valid:1 } {MC4_MISC2=0xc0000409;northbridge MC misc (thresholding) (2 - L3 cache) :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 IntType:2 CntEn:1 LvtOffset:4 :5 Locked:1 CntP:1 Valid:1 } {MC4_MISC3=0xc000040a;northbridge MC misc (thresholding) (3) :24 BlkPtr:8 :32 } {PERF_CTL0=0xc0010000;performance event select (0) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL1=0xc0010001;performance event select (1) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL2=0xc0010002;performance event select (2) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL3=0xc0010003;performance event select (3) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTR0=0xc0010004;performance event counter (0) CTR:48 :16 } {PERF_CTR1=0xc0010005;performance event counter (1) CTR:48 :16 } {PERF_CTR2=0xc0010006;performance event counter (2) CTR:48 :16 } {PERF_CTR3=0xc0010007;performance event counter (3) CTR:48 :16 } {SYS_CFG=0xc0010010;system configuration :8 SetDirtyEnE:1 SetDirtyEnS:1 SetDirtyEnO:1 :5 ChxToDirtyDis:1 SysUcLockEn:1 MtrrFixDramEn:1 MtrrFixDramModeEn:1 MtrrVarDramEn:1 MtrrTom2En:1 Tom2ForceMemTypeWB:1 :41 } {HWCR=0xc0010015;hardware configuration SmmLock:1 SlowFence:1 :1 TlbCacheDis:1 INVD_WBINVD:1 :3 IgnneEm:1 MonMwaitDis:1 MonMwaitUserEn:1 LimitCpuidStdMaxVal:1 HltXSpCycEn:1 SmiSpCycDis:1 RsmSpCycDis:1 SseDis:1 :1 Wrap32Dis:1 McStatusWrEn:1 :1 IoCfgGpFault:1 MisAlignSseDis:1 :1 ForceUsRdWrSzPrb:1 TscFreqSel:1 :39 } {IORR_BASE0=0xc0010016;base of variable I/O range (0) :3 WrMem:1 RdMem:1 :7 PhyBase:36 :16 } {IORR_MASK0=0xc0010017;mask of variable I/O range (0) :11 Valid:1 PhyMask:36 :16 } {IORR_BASE1=0xc0010018;base of variable I/O range (1) :3 WrMem:1 RdMem:1 :7 PhyBase:36 :16 } {IORR_MASK1=0xc0010019;mask of variable I/O range (1) :11 Valid:1 PhyMask:36 :16 } {TOP_MEM=0xc001001a;top of memory address :23 TOM:25 :16 } {TOM2=0xc001001d;second top of memory address :23 TOM2:25 :16 } {NB_CFG=0xc001001f;northbridge configuration :9 DisRefUseFreeBuf:1 DisXdsBypass:1 :20 DisCohLdtCfg:1 :4 DisDatMsk:1 :8 DisUsSysMgtReqToNcHt:1 EnableCf8ExtCfg:1 :3 DisOrderRdRsp:1 :3 InitApicIdCpuIdLo:1 :9 } {MCEredirection=0xc0010022;MCE redirection RedirVector:8 RedirVecEn:1 RedirSmiEn:1 :54 } {ProcessorNameString0=0xc0010030;processor name string (0) CpuNameString:64 } {ProcessorNameString1=0xc0010031;processor name string (1) CpuNameString:64 } {ProcessorNameString2=0xc0010032;processor name string (2) CpuNameString:64 } {ProcessorNameString3=0xc0010033;processor name string (3) CpuNameString:64 } {ProcessorNameString4=0xc0010034;processor name string (4) CpuNameString:64 } {ProcessorNameString5=0xc0010035;processor name string (5) CpuNameString:64 } {MC0_CTL_MASK=0xc0010044;data cache MC control mask ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC1_CTL_MASK=0xc0010045;instruction cache MC control mask ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC2_CTL_MASK=0xc0010046;bus unit MC control mask SRDE_HP:1 SRDE_TLB:1 SRDE_ALL:1 L2T_PAR:1 L2T_CECC:1 L2T_UECC:1 L2D_PAR:1 L2D_CECC:1 L2D_UECC:1 :1 VB_PAR:1 PDC_PAR:1 :52 } {MC3_CTL_MASK=0xc0010047;load store unit MC control mask SRDE_L:1 SRDE_S:1 :62 } {MC4_CTL_MASK=0xc0010048;northbridge MC control mask CECCEn:1 UECCEn:1 CrcErr0En:1 CrcErr1En:1 CrcErr2En:1 SyncPkt0En:1 SyncPkt1En:1 SyncPkt2En:1 MstrAbrtEn:1 TgtAbrtEn:1 GartTblWkEn:1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 L3ArrayCorEn:1 L3ArrayUCEn:1 HtProtEn:1 HtDataEn:1 DramParEn:1 RtryHt0En:1 RtryHt1En:1 RtryHt2En:1 RtryHt3En:1 CrcErr3En:1 SyncPkt3En:1 McaUsPwDatErrEn:1 NbArrayParEn:1 TblWlkDatErrEn:1 :36 } {MC5_CTL_MASK=0xc0010049;fixed issue reorder buffer MC control mask CPUWDT:1 :63 } {SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control :1 SmiEn_0:1 :1 SmiEn_1:1 :1 SmiEn_2:1 :1 SmiEn_3:1 :7 IoTrapEn:1 :48 } {IntPendingMessage=0xc0010055;interrupt pending and CMP-halt IOMsgAddr:16 IOMsgData:8 IntrPndMsgDis:1 IntrPndMsg:1 IORd:1 SmiOnCmpHalt:1 C1eOnCmpHalt:1 :35 } {SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle IoPortAddress:16 IoData:8 :1 IoCycleEn:1 IoRd:1 :37 } {MmioConfigBase=0xc0010058;MMIO configuration base address Enable:1 TrapAccess:1 SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 :14 MmiocCfgBaseAddr:28 :16 } {PstateCurrentLimit=0xc0010061;P-state current limit CurPstateLimit:3 :1 PstateMaxVal:3 :57 } {PstateControl=0xc0010062;P-state control PstateCmd:3 :61 } {PstateStatus=0xc0010063;P-state status CurPstate:3 :61 } {Pstate0=0xc0010064;P-state 0 CpuFid:6 CpuDid:3 CpuVid:7 :6 NbDid:1 :2 NbVid:7 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate1=0xc0010065;P-state 1 CpuFid:6 CpuDid:3 CpuVid:7 :6 NbDid:1 :2 NbVid:7 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate2=0xc0010066;P-state 2 CpuFid:6 CpuDid:3 CpuVid:7 :6 NbDid:1 :2 NbVid:7 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate3=0xc0010067;P-state 3 CpuFid:6 CpuDid:3 CpuVid:7 :6 NbDid:1 :2 NbVid:7 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate4=0xc0010068;P-state 4 CpuFid:6 CpuDid:3 CpuVid:7 :6 NbDid:1 :2 NbVid:7 IddValue:8 IddDiv:2 :21 PstateEn:1 } {COFVIDcontrol=0xc0010070;COFVID control CpuFid:6 CpuDid:3 CpuVid:7 PstateId:3 :3 NbDid:1 :2 NbVid:7 :32 } {COFVIDstatus=0xc0010071;COFVID status CurCpuFid:6 CurCpuDid:3 CurCpuVid:7 CurPstate:3 :3 CurNbDid:1 :2 CurNbVid:7 StartupPstate:3 MaxVid:7 MinVid:7 MaxCpuCof:6 :1 CurPstateLimit:3 MaxNbFid:5 } {CpuWdTmrCfg=0xc0010074;CPU watchdog timer CpuWdtEn:1 CpuWdtTimeBase:2 CpuWdtCountSel:4 :57 } {SMM_BASE=0xc0010111;SMM base address SMM_BASE:32 :32 } {SMMAddr=0xc0010112;SMM TSeg base address :17 TSegBase:31 :16 } {SMMMask=0xc0010113;SMM Tseg mask AValid:1 TValid:1 AClose:1 TClose:1 AMTypeIoWc:1 TMTypeIoWc:1 :2 AMTypeDram:3 :1 TMTypeDram:3 :2 TSegMask:31 :16 } {VM_CR=0xc0010114;virtual machine control dpd:1 r_init:1 dis_a20m:1 Lock:1 Svme_Disable:1 :59 } {IGNNE=0xc0010115;IGNNE IGNNE:1 :63 } # {SMM_CTL=0xc0010116;SMM control # smm_dismiss:1 # smm_enter:1 # smi_cyle:1 # smm_exit:1 # rsm_cycle:1 # :59 # } # write-only {VM_HSAVE_PA=0xc0010117;virtual machine host save physical address VM_HSAVE_PA:64 } # {SVMLock=0xc0010118;SVM lock key # SvmLockKey:64 # } # write-only {SMIstatus=0xc001011a;local SMI status IoTrapSts:4 :4 MceRedirSts:1 SmiOnCmpHaltSts:1 IntPendSmiSts:1 :5 SmiSrcLvtLcy:1 SmiSrcLvtExt:1 SmiSrcThrCntDram:1 SmiSrcThrCntHt:1 SmiSrcThrCntL3:1 :1 SmiSrcOnLineSpare:1 :41 } {OSVW_ID_Length=0xc0010140;OS visible work-around OSVW_ID_Length:16 :48 } {OsvwStatus=0xc0010141;OS visible work-around status bits OsvwStatusBits:64 } {CPUIDFeatures=0xc0011004;CPUID features FeaturesEdx:32 FeaturesEcx:32 } {CPUIDExtFeatures=0xc0011005;extended CPUID features ExtFeaturesEdx:32 ExtFeaturesEcx:32 } {NodeId=0xc001100c;Node ID NodeId:3 NodesPerProcessor:3 BiosScratch:6 :52 } {IC_CFG=0xc0011021;instruction cache configuration :9 DIS_SPEC_TLB_RLD:1 :4 DIS_IND:1 :39 } {DC_CFG=0xc0011022;data cache configuration :4 DIS_SPEC_TLB_RLD:1 :3 DIS_CLR_WBTOL2_SMC_HIT:1 :4 DIS_HW_PF:1 :20 REQ_CTR:2 :28 } {BU_CFG=0xc0011023;bus unit configuration :48 WbEnhWsbDis:1 :15 } {BU_CFG2=0xc001102A;bus unit configuration 2 :2 FrcWTMemTypToWPDis:1 :3 ThrottleNbInterface:2 :7 CILinesToNbDis:1 :13 Smash1GPages:1 :6 ThrottleNbInterface:2 :4 ProbeFilterSupEn:1 :7 RdMmExtCfgQwEn:1 :13 } {IbsFetchCtl=0xc0011030;IBS fetch control IbsFetchMaxCnt:16 IbsFetchCnt:16 IbsFetchLat:16 IbsFetchEn:1 IbsFetchVal:1 IbsFetchComp:1 IbsIcMiss:1 IbsPhyAddrValid:1 IbsL1TlbPgSz:2 IbsL1TlbMiss:1 IbsL2TlbMiss:1 IbsRandEn:1 :6 } {IbsFetchLinAd=0xc0011031;IBS fetch linear address IbsFetchLinAd:64 } {IbsFetchPhysAd=0xc0011032;IBS fetch physical address IbsFetchPhysAd:64 } {IbsOpCtl=0xc0011033;IBS execution control IbsOpMaxCnt:16 :1 IbsOpEn:1 IbsOpVal:1 IbsOpCntCtl:1 :12 IbsOpCurCnt:20 :12 } {IbsOpRip=0xc0011034;IBS Op logical address IbsOpRip:64 } {IbsOpData=0xc0011035;IBS Op data IbsCompToRetCtr:16 IbsTagToRetCtr:16 IbsOpBrnResync:1 IbsOpMispReturn:1 IbsOpReturn:1 IbsOpBrnTaken:1 IbsOpBrnMisp:1 IbsOpBrnRet:1 :26 } {IbsOpData2=0xc0011036;IBS Op data 2 NbIbsReqSrc:3 :1 NbIbsReqDstProc:1 NbIbsReqCacheHitSt:1 :58 } {IbsOpData3=0xc0011037;IBS Op data 3 IbsLdOp:1 IbsStOp:1 IbsDcL1tlbMiss:1 IbsDcL2tlbMiss:1 IbsDcL1tlbHit2M:1 IbsDcL1tlbHit1G:1 IbsDcL2tlbHit2M:1 IbsDcMiss:1 IbsDcMisAcc:1 IbsDcLdBnkCon:1 IbsDcStBnkCon:1 IbsDcStToLdFwd:1 IbsDcStToLdCan:1 IbsDcUcMemAcc:1 IbsDcWcMemAcc:1 IbsDcLockedOp:1 IbsDcMabHit:1 IbsDcLinAddrValid:1 IbsDcPhyAddrValid:1 IbsDcL2tlbHit1G:1 :12 IbsDcMissLat:16 :16 } {IbsDcLinAd=0xc0011038;IBS DC linear address IbsDcLinAd:64 } {IbsDcPhysAd=0xc0011039;IBS DC physical address IbsDcPhysAd:64 } {IbsControl=0xc001103a;IBS control LvtOffset:4 :4 LvtOffsetVal:1 :55 } ### Local Variables: ### ### mode:shell-script ### ### End: ### AMD/fam11h.regs000066400000000000000000000432241167043552300134310ustar00rootroot00000000000000# Author: Andreas Herrmann # # Copyright (C) 2009 Advanced Micro Devices, Inc. # This source file contains information based on: # - "41526 Rev 3.00 - July 07, 2008, AMD Family 11h Processor BKDG" # See scripts/createheader.py for the general format of this register # definitions. {LSMCAaddr=0x0000;load-store MCA address ADDR:48 :16 } # alias of MC3_ADDR {LSMCAstatus=0x0001;load-store MCA status ErrorCode:16 :29 UECC:1 CECC:1 :10 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } # alias of MC3_STATUS {TSC=0x0010;time-stamp counter TSC:64 } {APIC_BASE=0x001b;APIC base address :8 BSC:1 :2 ApicEn:1 ApicBar:36 :16 } {EBL_CR_POWERON=0x002a;cluster ID :16 ClusterID:2 :46 } {PATCH_LEVEL=0x008b;microcode patch level PATCH_LEVEL:32 :32 } {MTRRcap=0x00fe;MTRR capabilities MtrrCapVCnt:8 MtrrCapFix:1 :1 MtrrCapWc:1 :53 } {SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector SYSENTER_CS:16 :48 } {SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer SYSENTER_ESP:32 :32 } {SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer SYSENTER_EIP:32 :32 } {MCG_CAP=0x0179;global MC capabilities Count:8 MCG_CTL_P:1 :55 } {MCG_STAT=0x017a;global MC status RIPV:1 EIPV:1 MCIP:1 :61 } {MCG_CTL=0x017b;global MC control DCE:1 ICE:1 BUE:1 LSE:1 NBE:1 FRE:1 :58 } {DBG_CTL_MSR=0x01d9;debug control LBR:1 BTF:1 PB0:1 PB1:1 PB2:1 PB3:1 :58 } {BR_FROM=0x01db;last branch from IP LastBranchFromIP:64 } {BR_TO=0x01dc;last branch to IP LastBranchToIP:64 } {LastExceptionFromIP=0x01dd;last exception from IP LastIntFromIP:64 } {LastExceptionToIP=0x01de;last exception to IP LastIntToIP:64 } {MTRRphysBase0=0x0200;base of variable-size MTRR (0) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask0=0x0201;mask of variable-size MTRR (0) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase1=0x0202;base of variable-size MTRR (1) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask1=0x0203;mask of variable-size MTRR (1) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase2=0x0204;base of variable-size MTRR (2) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask2=0x0205;mask of variable-size MTRR (2) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase3=0x0206;base of variable-size MTRR (3) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask3=0x0207;mask of variable-size MTRR (3) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase4=0x0208;base of variable-size MTRR (4) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask4=0x0209;mask of variable-size MTRR (4) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase5=0x020a;base of variable-size MTRR (5) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask5=0x020b;mask of variable-size MTRR (5) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase6=0x020c;base of variable-size MTRR (6) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask6=0x020d;mask of variable-size MTRR (6) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase7=0x020e;base of variable-size MTRR (7) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask7=0x020f;mask of variable-size MTRR (7) :11 Valid:1 PhysMask:36 :16 } {MTRRfix64K_00000=0x0250;fixed range MTRR 0xxxxType:8 1xxxxType:8 2xxxxType:8 3xxxxType:8 4xxxxType:8 5xxxxType:8 6xxxxType:8 7xxxxType:8 } {MTRRfix16K_80000=0x0258;fixed range MTRR 80xxxType:8 84xxxType:8 88xxxType:8 8CxxxType:8 90xxxType:8 94xxxType:8 98xxxType:8 9CxxxType:8 } {MTRRfix16K_A0000=0x0259;fixed range MTRR A0xxxType:8 A4xxxType:8 A8xxxType:8 ACxxxType:8 B0xxxType:8 B4xxxType:8 B8xxxType:8 BCxxxType:8 } {MTRRfix4K_C0000=0x0268;fixed range MTRR C0xxxType:8 C1xxxType:8 C2xxxType:8 C3xxxType:8 C4xxxType:8 C5xxxType:8 C6xxxType:8 C7xxxType:8 } {MTRRfix4K_C8000=0x0269;fixed range MTRR C8xxxType:8 C9xxxType:8 CAxxxType:8 CBxxxType:8 CCxxxType:8 CDxxxType:8 CExxxType:8 CFxxxType:8 } {MTRRfix4K_D0000=0x026a;fixed range MTRR D0xxxType:8 D1xxxType:8 D2xxxType:8 D3xxxType:8 D4xxxType:8 D5xxxType:8 D6xxxType:8 D7xxxType:8 } {MTRRfix4K_D8000=0x026b;fixed range MTRR D8xxxType:8 D9xxxType:8 DAxxxType:8 DBxxxType:8 DCxxxType:8 DDxxxType:8 DExxxType:8 DFxxxType:8 } {MTRRfix4K_E0000=0x026c;fixed range MTRR E0xxxType:8 E1xxxType:8 E2xxxType:8 E3xxxType:8 E4xxxType:8 E5xxxType:8 E6xxxType:8 E7xxxType:8 } {MTRRfix4K_E8000=0x026d;fixed range MTRR E8xxxType:8 E9xxxType:8 EAxxxType:8 EBxxxType:8 ECxxxType:8 EDxxxType:8 EExxxType:8 EFxxxType:8 } {MTRRfix4K_F0000=0x026e;fixed range MTRR F0xxxType:8 F1xxxType:8 F2xxxType:8 F3xxxType:8 F4xxxType:8 F5xxxType:8 F6xxxType:8 F7xxxType:8 } {MTRRfix4K_F8000=0x026f;fixed range MTRR F8xxxType:8 F9xxxType:8 FAxxxType:8 FBxxxType:8 FCxxxType:8 FDxxxType:8 FExxxType:8 FFxxxType:8 } {PAT=0x0277;page attribute table PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 } {MTRRdefType=0x02ff;MTRR default memory type MemType:8 :2 MtrrDefTypeFixEn:1 MtrrDefTypeEn:1 :52 } {MC0_CTL=0x0400;data cache MC control ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC0_STATUS=0x0401;data cache MC status ErrorCode:16 ErrorCodeExt:4 :20 Scrub:1 :4 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC0_ADDR=0x0402;data cache MC address ADDR:48 :16 } {MC0_MISC=0x0403;data cache MC miscellaneous :64 } {MC1_CTL=0x0404;instruction cache MC control ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC1_STATUS=0x0405;instruction cache MC status ErrorCode:16 ErrorCodeExt:4 :25 UECC:1 CECC:1 :10 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC1_ADDR=0x0406;instruction cache MC address ADDR:48 :16 } {MC1_MISC=0x0407;instruction cache MC miscellaneous :64 } {MC2_CTL=0x0408;bus unit MC control S_RDE_HP:1 S_RDE_TLB:1 S_RDE_ALL:1 S_ECC1_TLB:1 S_ECC1_HP:1 S_ECCM_TLB:1 S_ECCM_HP:1 L2T_PAR_ICDC:1 L2T_PAR_TLB:1 L2_PAR_SNP:1 L2_PAR_CPB:1 L2_PAR_SCR:1 L2D_ECC1_TLB:1 L2D_ECC1_SNP:1 L2D_ECC1_CPB:1 L2D_ECCM_TLB:1 L2D_ECCM_SNP:1 L2D_ECCM_CPB:1 L2T_ECC1_SCR:1 L2T_ECCM_SCR:1 :44 } {MC2_STATUS=0x0409;bus unit MC status ErrorCode:16 ErrorCodeExt:4 :25 UECC:1 CECC:1 :10 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC2_ADDR=0x040a;bus unit MC address register ADDR:48 :16 } {MC2_MISC=0x040b;bus unit MC miscellaneous :64 } {MC3_CTL=0x040c;load store unit MC control S_RDE_L:1 S_RDE_S:1 :62 } {MC3_STATUS=0x040d;load store unit MC status ErrorCode:16 :29 UECC:1 CECC:1 :10 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } {MC3_ADDR=0x040e;load store unit MC address ADDR:48 :16 } {MC3_MISC=0x040f;load store unit MC miscellaneous :64 } {MC4_CTL=0x0410;northbridge MC control :2 CrcErr0En:1 :2 SyncPkt0En:1 :2 MstrAbrtEn:1 TgtAbrtEn:1 :1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 :2 HtProtEn:1 HtDataEn:1 :1 RtryHt0En:1 :5 McaUsPwDatErrEn:1 :1 TblWlkDatErrEn:1 :36 } {MC4_STATUS=0x0411;northbridge MC status ErrorCode:16 ErrorCodeExt:5 :11 ErrCpu0:1 ErrCpu1:1 :2 LDTLink:1 :4 SubLink:1 :15 PCC:1 AddrV:1 :1 En:1 UC:1 Over:1 Val:1 } {MC4_ADDR=0x0412;northbridge MC address NBaddr:64 } # 0x0413 reserved (was MC4_MISC0) {EFER=0xc0000080;extended feature enable SYSCALL:1 :7 LME:1 :1 LMA:1 NXE:1 SVME:1 LMSLE:1 FFXSE:1 :49 } {STAR=0xc0000081;SYSCALL target address Target:32 SysCallSel:16 SysRetSel:16 } {STAR64=0xc0000082;long mode SYSCALL target address LSTAR:64 } {STARCOMPAT=0xc0000083;compat mode SYSCALL target address CSTAR:64 } {SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask MASK:32 :32 } {FS_BASE=0xc0000100;FS base FS_BASE:64 } {GS_BASE=0xc0000101;GS base GS_BASE:64 } {KernelGSbase=0xc0000102;kernel GS base KernelGSBase:64 } {TSC_AUX=0xc0000103;auxiliary time stamp counter data TscAux:32 :32 } {PERF_CTL0=0xc0010000;performance event select (0) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 PC:1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :28 } {PERF_CTL1=0xc0010001;performance event select (1) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 PC:1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :28 } {PERF_CTL2=0xc0010002;performance event select (2) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 PC:1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :28 } {PERF_CTL3=0xc0010003;performance event select (3) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :28 } {PERF_CTR0=0xc0010004;performance event counter (0) CTR:48 :16 } {PERF_CTR1=0xc0010005;performance event counter (1) CTR:48 :16 } {PERF_CTR2=0xc0010006;performance event counter (2) CTR:48 :16 } {PERF_CTR3=0xc0010007;performance event counter (3) CTR:48 :16 } {SYS_CFG=0xc0010010;system configuration SysAckLimit:5 SysVicLimit:3 :1 SetDirtyEnS:1 SetDirtyEnO:1 :5 ChxToDirtyDis:1 SysUcLockEn:1 MtrrFixDramEn:1 MtrrFixDramModeEn:1 MtrrVarDramEn:1 MtrrTom2En:1 Tom2ForceMemTypeWB:1 :41 } {HWCR=0xc0010015;hardware configuration SmmLock:1 SlowFence:1 :1 TlbCacheDis:1 INVD_WBINVD:1 :1 FFDIS:1 DisLock:1 IgnneEm:1 :4 SmiSpCycDis:1 RsmSpCycDis:1 SseDis:1 :1 Wrap32Dis:1 McStatusWrEn:1 :1 IoCfgGpFault:1 :2 ForceUsRdWrSzPrb:1 TscFreqSel:1 :39 } {IORR_BASE0=0xc0010016;base of variable I/O range (0) :3 WrMem:1 RdMem:1 :7 PhyBase:36 :16 } {IORR_MASK0=0xc0010017;mask of variable I/O range (0) :11 Valid:1 PhyMask:36 :16 } {IORR_BASE1=0xc0010018;base of variable I/O range (1) :3 WrMem:1 RdMem:1 :7 PhyBase:36 :16 } {IORR_MASK1=0xc0010019;mask of variable I/O range (1) :11 Valid:1 PhyMask:36 :16 } {TOP_MEM=0xc001001a;top of memory address :23 TOM:17 :24 } {TOM2=0xc001001d;second top of memory address :23 TOM2:17 :24 } {NB_CFG=0xc001001f;northbridge configuration :42 EnaPStateSpyCyc:1 :2 DisUsSysMgtReqToNcHt:1 EnableCf8ExtCfg:1 :3 DisOrderRdRsp:1 :7 EnConvertToNonIsoc:1 :5 } {ProcessorNameString0=0xc0010030;processor name string (0) CpuNameString:64 } {ProcessorNameString1=0xc0010031;processor name string (1) CpuNameString:64 } {ProcessorNameString2=0xc0010032;processor name string (2) CpuNameString:64 } {ProcessorNameString3=0xc0010033;processor name string (3) CpuNameString:64 } {ProcessorNameString4=0xc0010034;processor name string (4) CpuNameString:64 } {ProcessorNameString5=0xc0010035;processor name string (5) CpuNameString:64 } {MC0_CTL_MASK=0xc0010044;data cache MC control mask ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC1_CTL_MASK=0xc0010045;instruction cache MC control mask ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC2_CTL_MASK=0xc0010046;bus unit MC control mask S_RDE_HP:1 S_RDE_TLB:1 S_RDE_ALL:1 S_ECC1_TLB:1 S_ECC1_HP:1 S_ECCM_TLB:1 S_ECCM_HP:1 L2T_PAR_ICDC:1 L2T_PAR_TLB:1 L2_PAR_SNP:1 L2_PAR_CPB:1 L2_PAR_SCR:1 L2D_ECC1_TLB:1 L2D_ECC1_SNP:1 L2D_ECC1_CPB:1 L2D_ECCM_TLB:1 L2D_ECCM_SNP:1 L2D_ECCM_CPB:1 L2T_ECC1_SCR:1 L2T_ECCM_SCR:1 :44 } {MC3_CTL_MASK=0xc0010047;load store unit MC control mask S_RDE_L:1 S_RDE_S:1 :62 } {MC4_CTL_MASK=0xc0010048;northbridge MC control mask :2 CrcErr0En:1 :2 SyncPkt0En:1 :2 MstrAbrtEn:1 TgtAbrtEn:1 :1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 :2 HtProtEn:1 HtDataEn:1 :1 RtryHt0En:1 :5 McaUsPwDatErrEn:1 :1 TblWlkDatErrEn:1 :36 } {SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control :1 SmiEn_0:1 :1 SmiEn_1:1 :1 SmiEn_2:1 :1 SmiEn_3:1 :7 IoTrapEn:1 :48 } {IntPendingMessage=0xc0010055;interrupt pending and CMP-halt IOMsgAddr:16 IOMsgData:8 IntrPndMsgDis:1 IntrPndMsg:1 IORd:1 SmiOnCmpHalt:1 C1eOnCmpHalt:1 :35 } {SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle IoPortAddress:16 IoData:8 :1 IoCycleEn:1 IoRd:1 :37 } {MmioConfigBase=0xc0010058;MMIO configuration base address Enable:1 :1 BusRange:4;0=1;1=2;2;4;3=8;4=16;5=32;6=64;7=128;8=256 :14 MmiocCfgBaseAddr:20 :24 } {BISTresults=0xc0010060;BIST results register ICFT:1 ICST:1 ICTLB2:1 BTA:1 BSA:1 ICD:1 PDA:1 BH:1 ICTLB1:1 ICLRU:1 BSR:1 DCD:1 DCECC:1 DCTLB1:1 DCT:1 DCTLB2:1 DCLRU:1 FPCR:1 FPRR:1 FPRQ:1 :2 ROBD:1 L2D:1 L2T:1 WDB:1 VDB:1 L2LRU:1 FF:1 PDC:1 :1 MC:1 :32 } {PstateCurrentLimit=0xc0010061;P-state current limit CurPstateLimit:3 :1 PstateMaxVal:3 :57 } {PstateControl=0xc0010062;P-state control PstateCmd:3 :61 } {PstateStatus=0xc0010063;P-state status CurPstate:3 :61 } {Pstate0=0xc0010064;P-state 0 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate1=0xc0010065;P-state 1 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate2=0xc0010066;P-state 2 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate3=0xc0010067;P-state 3 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate4=0xc0010068;P-state 4 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate5=0xc0010069;P-state 5 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate6=0xc001006a;P-state 6 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate7=0xc001006b;P-state 7 CpuFid:6 CpuDid:3 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {COFVIDcontrol=0xc0010070;COFVID control CpuFid:6 CpuDid:3 CpuVid:7 PstateId:3 :45 } {COFVIDstatus=0xc0010071;COFVID status CurCpuFid:6 CurCpuDid:3 CurCpuVid:7 CurPstate:3 :6 CurNbVid:7 StartupPstate:3 MaxVid:7 MinVid:7 MainPllOpFreqIdMax:6 :1 CurPstateLimit:3 :5 } {SMM_BASE=0xc0010111;SMM base address SMM_BASE:32 :32 } {SMMAddr=0xc0010112;SMM TSeg base address :17 TSegBase:23 :24 } {SMMMask=0xc0010113;SMM Tseg mask AValid:1 TValid:1 AClose:1 TClose:1 AMTypeIoWc:1 TMTypeIoWc:1 :2 AMTypeDram:3 :1 TMTypeDram:3 :2 TSegMask:23 :24 } {VM_CR=0xc0010114;virtual machine control dpd:1 r_init:1 dis_a20m:1 Lock:1 Svme_Disable:1 :59 } {IGNNE=0xc0010115;IGNNE IGNNE:1 :63 } # 0xc0010116 SMM_CTL, write-only {VM_HSAVE_PA=0xc0010117;virtual machine host save physical address VM_HSAVE_PA:64 } # 0xc0010118 SVM Lock key, write-only {OSVW_ID_Length=0xc0010140;OS visible work-around ID length OSVW_ID_Length:16 :48 } {OsvwStatus=0xc0010141;OS visible work-around status OsvwStatusBits:64 } {DC_CFG=0xc0011022;data cache configuration register :8 DIS_CLR_WBTOL2_SMC_HIT:1 :4 DIS_HW_PF:1 :1 DIS_PF_HW_FOR_SW:1 :48 } {BU_CFG=0xc0011023;bus unit configuration register :48 WbEnhWsbDis:1 :15 } ### Local Variables: ### ### mode:shell-script ### ### End: ### AMD/fam12h.regs000066400000000000000000000604141167043552300134320ustar00rootroot00000000000000# Author: Andreas Herrmann # # Copyright (C) 2008, 2009 Advanced Micro Devices, Inc. # This file contains information from: # - "41131 Rev 3.00 - June 2011, BIOS and Kernel Developer's Guide (BKDG) # for AMD Family 12h Processors" # See scripts/createheader.py for the general format of this register # definitions. {LSMCAaddr=0x0000;load-store MCA address ADDR:64 } # alias of MC3_ADDR {LSMCAstatus=0x0001;load-store MCE status ErrorCode:16 ErrorCodeExt:4 :4 SYND:8 :13 UECC:1 CECC:1 SYND:8 :2 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } # alias of MC3_STATUS {TSC=0x0010;time-stamp counter TSC:64 } {APIC_BASE=0x001b;APIC base address :8 BSC:1 :2 ApicEn:1 ApicBar:28 :24 } {EBL_CR_POWERON=0x002a;cluster ID :16 ClusterID:2 :46 } {PATCH_LEVEL=0x008b;microcode patch level PATCH_LEVEL:32 :32 } {MPERF=0x00e7;max performance frequency clock count MPERF:64 } {APERF=0x00e8;actual performance frequency clock count APERF:64 } {MTRRcap=0x00fe;MTRR capabilities MtrrCapVCnt:8 MtrrCapFix:1 :1 MtrrCapWc:1 :53 } {SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector SYSENTER_CS:16 :48 } {SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer SYSENTER_ESP:32 :32 } {SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer SYSENTER_EIP:32 :32 } {MCG_CAP=0x0179;global MC capabilities Count:8 MCG_CTL_P:1 :55 } {MCG_STAT=0x017a;global MC status RIPV:1 EIPV:1 MCIP:1 :61 } {MCG_CTL=0x017b;global MC control LS:1 IF:1 BU:1 FP:1 NB:1 FR:1 :58 } {DBG_CTL_MSR=0x01d9;debug control LBR:1 BTF:1 PB0:1 PB1:1 PB2:1 PB3:1 :58 } {BR_FROM=0x01db;last branch from IP LastBranchFromIP:64 } {BR_TO=0x01dc;last branch to IP LastBranchToIP:64 } {LastExceptionFromIP=0x01dd;last exception from IP LastIntFromIP:64 } {LastExceptionToIP=0x01de;last exception to IP LastIntToIP:64 } {MTRRphysBase0=0x0200;base of variable-size MTRR (0) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask0=0x0201;mask of variable-size MTRR (0) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase1=0x0202;base of variable-size MTRR (1) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask1=0x0203;mask of variable-size MTRR (1) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase2=0x0204;base of variable-size MTRR (2) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask2=0x0205;mask of variable-size MTRR (2) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase3=0x0206;base of variable-size MTRR (3) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask3=0x0207;mask of variable-size MTRR (3) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase4=0x0208;base of variable-size MTRR (4) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask4=0x0209;mask of variable-size MTRR (4) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase5=0x020a;base of variable-size MTRR (5) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask5=0x020b;mask of variable-size MTRR (5) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase6=0x020c;base of variable-size MTRR (6) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask6=0x020d;mask of variable-size MTRR (6) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase7=0x020e;base of variable-size MTRR (7) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:28 :24 } {MTRRphysMask7=0x020f;mask of variable-size MTRR (7) :11 Valid:1 PhysMask:28 :24 } {MTRRfix64K_00000=0x0250;fixed range MTRR 0xxxxMemType:3 0xxxxWrDram:1 0xxxxRdDram:1 :3 1xxxxMemType:3 1xxxxWrDram:1 1xxxxRdDram:1 :3 2xxxxMemType:3 2xxxxWrDram:1 2xxxxRdDram:1 :3 3xxxxMemType:3 3xxxxWrDram:1 3xxxxRdDram:1 :3 4xxxxMemType:3 4xxxxWrDram:1 4xxxxRdDram:1 :3 5xxxxMemType:3 5xxxxWrDram:1 5xxxxRdDram:1 :3 6xxxxMemType:3 6xxxxWrDram:1 6xxxxRdDram:1 :3 7xxxxMemType:3 7xxxxWrDram:1 7xxxxRdDram:1 :3 } {MTRRfix16K_80000=0x0258;fixed range MTRR 80xxxMemType:3 80xxxWrDram:1 80xxxRdDram:1 :3 84xxxMemType:3 84xxxWrDram:1 84xxxRdDram:1 :3 88xxxMemType:3 88xxxWrDram:1 88xxxRdDram:1 :3 8CxxxMemType:3 8CxxxWrDram:1 8CxxxRdDram:1 :3 90xxxMemType:3 90xxxWrDram:1 90xxxRdDram:1 :3 94xxxMemType:3 94xxxWrDram:1 94xxxRdDram:1 :3 98xxxMemType:3 98xxxWrDram:1 98xxxRdDram:1 :3 9CxxxMemType:3 9CxxxWrDram:1 9CxxxRdDram:1 :3 } {MTRRfix16K_A0000=0x0259;fixed range MTRR A0xxxMemType:3 A0xxxWrDram:1 A0xxxRdDram:1 :3 A4xxxMemType:3 A4xxxWrDram:1 A4xxxRdDram:1 :3 A8xxxMemType:3 A8xxxWrDram:1 A8xxxRdDram:1 :3 ACxxxMemType:3 ACxxxWrDram:1 ACxxxRdDram:1 :3 B0xxxMemType:3 B0xxxWrDram:1 B0xxxRdDram:1 :3 B4xxxMemType:3 B4xxxWrDram:1 B4xxxRdDram:1 :3 B8xxxMemType:3 B8xxxWrDram:1 B8xxxRdDram:1 :3 BCxxxMemType:3 BCxxxWrDram:1 BCxxxRdDram:1 :3 } {MTRRfix4K_C0000=0x0268;fixed range MTRR C0xxxMemType:3 C0xxxWrDram:1 C0xxxRdDram:1 :3 C1xxxMemType:3 C1xxxWrDram:1 C1xxxRdDram:1 :3 C2xxxMemType:3 C2xxxWrDram:1 C2xxxRdDram:1 :3 C3xxxMemType:3 C3xxxWrDram:1 C3xxxRdDram:1 :3 C4xxxMemType:3 C4xxxWrDram:1 C4xxxRdDram:1 :3 C5xxxMemType:3 C5xxxWrDram:1 C5xxxRdDram:1 :3 C6xxxMemType:3 C6xxxWrDram:1 C6xxxRdDram:1 :3 C7xxxMemType:3 C7xxxWrDram:1 C7xxxRdDram:1 :3 } {MTRRfix4K_C8000=0x0269;fixed range MTRR C8xxxMemType:3 C8xxxWrDram:1 C8xxxRdDram:1 :3 C9xxxMemType:3 C9xxxWrDram:1 C9xxxRdDram:1 :3 CAxxxMemType:3 CAxxxWrDram:1 CAxxxRdDram:1 :3 CBxxxMemType:3 CBxxxWrDram:1 CBxxxRdDram:1 :3 CCxxxMemType:3 CCxxxWrDram:1 CCxxxRdDram:1 :3 CDxxxMemType:3 CDxxxWrDram:1 CDxxxRdDram:1 :3 CExxxMemType:3 CExxxWrDram:1 CExxxRdDram:1 :3 CFxxxMemType:3 CFxxxWrDram:1 CFxxxRdDram:1 :3 } {MTRRfix4K_D0000=0x026a;fixed range MTRR D0xxxMemType:3 D0xxxWrDram:1 D0xxxRdDram:1 :3 D1xxxMemType:3 D1xxxWrDram:1 D1xxxRdDram:1 :3 D2xxxMemType:3 D2xxxWrDram:1 D2xxxRdDram:1 :3 D3xxxMemType:3 D3xxxWrDram:1 D3xxxRdDram:1 :3 D4xxxMemType:3 D4xxxWrDram:1 D4xxxRdDram:1 :3 D5xxxMemType:3 D5xxxWrDram:1 D5xxxRdDram:1 :3 D6xxxMemType:3 D6xxxWrDram:1 D6xxxRdDram:1 :3 D7xxxMemType:3 D7xxxWrDram:1 D7xxxRdDram:1 :3 } {MTRRfix4K_D8000=0x026b;fixed range MTRR D8xxxMemType:3 D8xxxWrDram:1 D8xxxRdDram:1 :3 D9xxxMemType:3 D9xxxWrDram:1 D9xxxRdDram:1 :3 DAxxxMemType:3 DAxxxWrDram:1 DAxxxRdDram:1 :3 DBxxxMemType:3 DBxxxWrDram:1 DBxxxRdDram:1 :3 DCxxxMemType:3 DCxxxWrDram:1 DCxxxRdDram:1 :3 DDxxxMemType:3 DDxxxWrDram:1 DDxxxRdDram:1 :3 DExxxMemType:3 DExxxWrDram:1 DExxxRdDram:1 :3 DFxxxMemType:3 DFxxxWrDram:1 DFxxxRdDram:1 :3 } {MTRRfix4K_E0000=0x026c;fixed range MTRR E0xxxMemType:3 E0xxxWrDram:1 E0xxxRdDram:1 :3 E1xxxMemType:3 E1xxxWrDram:1 E1xxxRdDram:1 :3 E2xxxMemType:3 E2xxxWrDram:1 E2xxxRdDram:1 :3 E3xxxMemType:3 E3xxxWrDram:1 E3xxxRdDram:1 :3 E4xxxMemType:3 E4xxxWrDram:1 E4xxxRdDram:1 :3 E5xxxMemType:3 E5xxxWrDram:1 E5xxxRdDram:1 :3 E6xxxMemType:3 E6xxxWrDram:1 E6xxxRdDram:1 :3 E7xxxMemType:3 E7xxxWrDram:1 E7xxxRdDram:1 :3 } {MTRRfix4K_E8000=0x026d;fixed range MTRR E8xxxMemType:3 E8xxxWrDram:1 E8xxxRdDram:1 :3 E9xxxMemType:3 E9xxxWrDram:1 E9xxxRdDram:1 :3 EAxxxMemType:3 EAxxxWrDram:1 EAxxxRdDram:1 :3 EBxxxMemType:3 EBxxxWrDram:1 EBxxxRdDram:1 :3 ECxxxMemType:3 ECxxxWrDram:1 ECxxxRdDram:1 :3 EDxxxMemType:3 EDxxxWrDram:1 EDxxxRdDram:1 :3 EExxxMemType:3 EExxxWrDram:1 EExxxRdDram:1 :3 EFxxxMemType:3 EFxxxWrDram:1 EFxxxRdDram:1 :3 } {MTRRfix4K_F0000=0x026e;fixed range MTRR F0xxxMemType:3 F0xxxWrDram:1 F0xxxRdDram:1 :3 F1xxxMemType:3 F1xxxWrDram:1 F1xxxRdDram:1 :3 F2xxxMemType:3 F2xxxWrDram:1 F2xxxRdDram:1 :3 F3xxxMemType:3 F3xxxWrDram:1 F3xxxRdDram:1 :3 F4xxxMemType:3 F4xxxWrDram:1 F4xxxRdDram:1 :3 F5xxxMemType:3 F5xxxWrDram:1 F5xxxRdDram:1 :3 F6xxxMemType:3 F6xxxWrDram:1 F6xxxRdDram:1 :3 F7xxxMemType:3 F7xxxWrDram:1 F7xxxRdDram:1 :3 } {MTRRfix4K_F8000=0x026f;fixed range MTRR F8xxxMemType:3 F8xxxWrDram:1 F8xxxRdDram:1 :3 F9xxxMemType:3 F9xxxWrDram:1 F9xxxRdDram:1 :3 FAxxxMemType:3 FAxxxWrDram:1 FAxxxRdDram:1 :3 FBxxxMemType:3 FBxxxWrDram:1 FBxxxRdDram:1 :3 FCxxxMemType:3 FCxxxWrDram:1 FCxxxRdDram:1 :3 FDxxxMemType:3 FDxxxWrDram:1 FDxxxRdDram:1 :3 FExxxMemType:3 FExxxWrDram:1 FExxxRdDram:1 :3 FFxxxMemType:3 FFxxxWrDram:1 FFxxxRdDram:1 :3 } {PAT=0x0277;page attribute table PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 } {MTRRdefType=0x02ff;MTRR default memory type MemType:8 :2 MtrrDefTypeFixEn:1 MtrrDefTypeEn:1 :52 } {MC0_CTL=0x0400;data cache MC control ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC0_STATUS=0x0401;data cache MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 :13 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC0_ADDR=0x0402;data cache MC address ADDR:64 } {MC0_MISC=0x0403;data cache MC miscellaneous :64 } {MC1_CTL=0x0404;instruction cache MC control ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC1_STATUS=0x0405;instruction cache MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 :13 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC1_ADDR=0x0406;instruction cache MC address ADDR:64 } {MC1_MISC=0x0407;instruction cache MC miscellaneous :64 } {MC2_CTL=0x0408;BU MC control SRDE_HP:1 SRDE_TLB:1 SRDE_ALL:1 L2T_PAR:1 L2T_CECC:1 L2T_UECC:1 L2D_PAR:1 L2D_CECC:1 L2D_UECC:1 :1 VB_PAR:1 PDC_PAR:1 :52 } {MC2_STATUS=0x0409;BU MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 :13 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC2_ADDR=0x040a;BU MC address register ADDR:64 } {MC2_MISC=0x040b;BU MC miscellaneous :64 } {MC3_CTL=0x040c;LS MC control SRDE_L:1 SRDE_S:1 :62 } {MC3_STATUS=0x040d;LS MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 :13 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC3_ADDR=0x040e;LS MC address ADDR:64 } {MC3_MISC=0x040f;LS MC miscellaneous :64 } {MC4_CTL=0x0410;NB MC control :5 SyncFloodEn:1 :2 MstrAbrtEn:1 TgtAbrtEn:1 :1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 :2 ProtEn:1 DataEn:1 :7 McaUsPwDatErrEn:1 :38 } {MC4_STATUS=0x0411;NB MC status ErrorCode:16 ErrorCodeExt:5 :11 ErrCpu0:1 ErrCpu1:1 ErrCpu2:1 ErrCpu3:1 BusErr:1 :20 PCC:1 AddrV:1 :1 En:1 UC:1 Over:1 Val:1 } {MC4_ADDR=0x0412;NB MC address McaNbAddrLow:32 McaNbAddrHigh:32 } {MC4_MISC0=0x0413;reserved (NB MC misc) :64 } {MC5_CTL=0x0414;FR MC control CPUWDT:1 :63 } {MC5_STATUS=0x0415;FR MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 :13 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC5_ADDR=0x0416;FR MC address ADDR:64 } {MC5_MISC=0x0417;FR MC miscellaneous State:12 :52 } {EFER=0xc0000080;extended feature enable SYSCALL:1 :7 LME:1 :1 LMA:1 NXE:1 SVME:1 LMSLE:1 FFXSE:1 :49 } {STAR=0xc0000081;SYSCALL target address Target:32 SysCallSel:16 SysRetSel:16 } {STAR64=0xc0000082;long mode SYSCALL target address LSTAR:64 } {STARCOMPAT=0xc0000083;compat mode SYSCALL target address CSTAR:64 } {SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask MASK:32 :32 } {FS_BASE=0xc0000100;FS base FS_BASE:64 } {GS_BASE=0xc0000101;GS base GS_BASE:64 } {KernelGSbase=0xc0000102;kernel GS base KernelGSBase:64 } {TSC_AUX=0xc0000103;auxiliary time stamp counter data TscAux:32 :32 } {PERF_CTL0=0xc0010000;performance event select (0) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL1=0xc0010001;performance event select (1) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL2=0xc0010002;performance event select (2) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL3=0xc0010003;performance event select (3) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTR0=0xc0010004;performance event counter (0) CTR:48 :16 } {PERF_CTR1=0xc0010005;performance event counter (1) CTR:48 :16 } {PERF_CTR2=0xc0010006;performance event counter (2) CTR:48 :16 } {PERF_CTR3=0xc0010007;performance event counter (3) CTR:48 :16 } {SYS_CFG=0xc0010010;system configuration :8 SetDirtyEnE:1 SetDirtyEnS:1 SetDirtyEnO:1 :5 ChxToDirtyDis:1 SysUcLockEn:1 MtrrFixDramEn:1 MtrrFixDramModeEn:1 MtrrVarDramEn:1 MtrrTom2En:1 Tom2ForceMemTypeWB:1 :41 } {HWCR=0xc0010015;hardware configuration SmmLock:1 SlowFence:1 :1 TlbCacheDis:1 INVD_WBINVD:1 :3 IgnneEm:1 MonMwaitDis:1 MonMwaitUserEn:1 :2 SmiSpCycDis:1 RsmSpCycDis:1 SseDis:1 :1 Wrap32Dis:1 McStatusWrEn:1 :1 IoCfgGpFault:1 MisAlignSseDis:1 :1 ForceUsRdWrSzPrb:1 TscFreqSel:1 CpbDis:1 EffFreqCntMwait:1 :37 } {IORR_BASE0=0xc0010016;base of variable I/O range (0) :3 WrMem:1 RdMem:1 :7 PhyBase:28 :24 } {IORR_MASK0=0xc0010017;mask of variable I/O range (0) :11 Valid:1 PhyMask:28 :24 } {IORR_BASE1=0xc0010018;base of variable I/O range (1) :3 WrMem:1 RdMem:1 :7 PhyBase:28 :24 } {IORR_MASK1=0xc0010019;mask of variable I/O range (1) :11 Valid:1 PhyMask:28 :24 } {TOP_MEM=0xc001001a;top of memory address :23 TOM:17 :24 } {TOM2=0xc001001d;second top of memory address :23 TOM2:17 :24 } {NB_CFG=0xc001001f;northbridge configuration :45 DisUsSysMgtReqToNcHt:1 EnableCf8ExtCfg:1 :11 EnConvertToNonIsoc:1 :5 } {MCEredirection=0xc0010022;MCE redirection RedirVector:8 RedirVecEn:1 RedirSmiEn:1 :54 } {ProcessorNameString0=0xc0010030;processor name string (0) CpuNameString:64 } {ProcessorNameString1=0xc0010031;processor name string (1) CpuNameString:64 } {ProcessorNameString2=0xc0010032;processor name string (2) CpuNameString:64 } {ProcessorNameString3=0xc0010033;processor name string (3) CpuNameString:64 } {ProcessorNameString4=0xc0010034;processor name string (4) CpuNameString:64 } {ProcessorNameString5=0xc0010035;processor name string (5) CpuNameString:64 } {MC0_CTL_MASK=0xc0010044;data cache MC control mask ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC1_CTL_MASK=0xc0010045;instruction cache MC control mask ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC2_CTL_MASK=0xc0010046;BU MC control mask SRDE_HP:1 SRDE_TLB:1 SRDE_ALL:1 L2T_PAR:1 L2T_CECC:1 L2T_UECC:1 L2D_PAR:1 L2D_CECC:1 L2D_UECC:1 :1 VB_PAR:1 PDC_PAR:1 :52 } {MC3_CTL_MASK=0xc0010047;LS MC control mask SRDE_L:1 SRDE_S:1 :62 } {MC4_CTL_MASK=0xc0010048;NB MC control mask :5 SyncFloodEn:1 :2 MstrAbrtEn:1 TgtAbrtEn:1 :1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 :2 ProtEn:1 DataEn:1 :7 McaUsPwDatErrEn:1 :38 } {MC5_CTL_MASK=0xc0010049;FR MC control mask CPUWDT:1 :63 } {SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control :1 SmiEn_0:1 :1 SmiEn_1:1 :1 SmiEn_2:1 :1 SmiEn_3:1 :7 IoTrapEn:1 :48 } {SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle IoPortAddress:16 IoData:8 :1 IoCycleEn:1 IoRd:1 :37 } {MmioConfigBase=0xc0010058;MMIO configuration base address Enable:1 :1 SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 :14 MmiocCfgBaseAddr:20 :24 } {BistResults=0xc0010060;BIST results BistResults:32 :32 } {PstateCurrentLimit=0xc0010061;P-state current limit CurPstateLimit:3 :1 PstateMaxVal:3 :57 } {PstateControl=0xc0010062;P-state control PstateCmd:3 :61 } {PstateStatus=0xc0010063;P-state status CurPstate:3 :61 } {Pstate0=0xc0010064;P-state 0 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate1=0xc0010065;P-state 1 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate2=0xc0010066;P-state 2 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate3=0xc0010067;P-state 3 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate4=0xc0010068;P-state 4 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate5=0xc0010069;P-state 5 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate6=0xc001006a;P-state 6 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate7=0xc001006b;P-state 7 CpuDid:4 CpuFid:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {COFVIDcontrol=0xc0010070;COFVID control CpuDid:4 CpuFid:5 CpuVid:7 PstateId:3 IgnorVidFidDid:1 :44 } {COFVIDstatus=0xc0010071;COFVID status CurCpuDid:4 CurCpuFid:5 CurCpuVid:7 CurPstate:3 :1 PstateInProgress:1 :4 CurNbVid:7 StartupPstate:3 MaxVid:7 MinVid:7 MainPllOpFreqIdMax:6 :1 CurPstateLimit:3 :5 } {CstateAddress=0xc0010073;C-state address CstateAddr:16 :48 } {CpuWdTmrCfg=0xc0010074;CPU watchdog timer CpuWdtEn:1 CpuWdtTimeBase:2 CpuWdtCountSel:4 :57 } {SMM_BASE=0xc0010111;SMM base address SMM_BASE:32 :32 } {SMMAddr=0xc0010112;SMM TSeg base address :17 TSegBase:23 :24 } {SMMMask=0xc0010113;SMM Tseg mask AValid:1 TValid:1 AClose:1 TClose:1 AMTypeIoWc:1 TMTypeIoWc:1 :2 AMTypeDram:3 :1 TMTypeDram:3 :2 TSegMask:23 :24 } {VM_CR=0xc0010114;virtual machine control dpd:1 r_init:1 dis_a20m:1 Lock:1 Svme_Disable:1 :59 } {IGNNE=0xc0010115;IGNNE IGNNE:1 :63 } # {SMM_CTL=0xc0010116;SMM control # smm_dismiss:1 # smm_enter:1 # smi_cyle:1 # smm_exit:1 # rsm_cycle:1 # :59 # } # write-only {VM_HSAVE_PA=0xc0010117;virtual machine host save physical address :12 VM_HSAVE_PA:28 :24 } # {SVMLock=0xc0010118;SVM lock key # SvmLockKey:64 # } # write-only # {SMMLock=0xc0010119;SMM lock key # SmmLockKey:64 # } # write-only {SMIstatus=0xc001011a;local SMI status IoTrapSts:4 :4 MceRedirSts:1 :7 SmiSrcLvtLcy:1 SmiSrcLvtExt:1 :46 } {OSVW_ID_Length=0xc0010140;OS visible work-around OSVW_ID_Length:16 :48 } {OsvwStatus=0xc0010141;OS visible work-around status bits OsvwStatusBits:64 } {CPUIDFeatures=0xc0011004;CPUID features FeaturesEdx:32 FeaturesEcx:32 } {CPUIDExtFeatures=0xc0011005;extended CPUID features ExtFeaturesEdx:32 ExtFeaturesEcx:32 } {LS_CFG=0xc0011020;load store configuration :28 DIS_SS:1 :35 } {IC_CFG=0xc0011021;instruction cache configuration :9 DIS_SPEC_TLB_RLD:1 :54 } {DC_CFG=0xc0011022;data cache configuration :4 DIS_SPEC_TLB_RLD:1 :3 DIS_CLR_WBTOL2_SMC_HIT:1 :4 DIS_HW_PF:1 :50 } {DE_CFG=0xc0011029;decode configuration :23 ClflushSerialize:1 :13 } {BU_CFG2=0xc001102A;bus unit configuration 2 :35 IcDisSpecTlbWr:1 :14 RdMmExtCfgDwDis:1 :5 L2ClkGatingEn:1 L2HystCnt:2 :5 } {IbsFetchCtl=0xc0011030;IBS fetch control IbsFetchMaxCnt:16 IbsFetchCnt:16 IbsFetchLat:16 IbsFetchEn:1 IbsFetchVal:1 IbsFetchComp:1 IbsIcMiss:1 IbsPhyAddrValid:1 IbsL1TlbPgSz:2 IbsL1TlbMiss:1 IbsL2TlbMiss:1 IbsRandEn:1 :6 } {IbsFetchLinAd=0xc0011031;IBS fetch linear address IbsFetchLinAd:64 } {IbsFetchPhysAd=0xc0011032;IBS fetch physical address IbsFetchPhysAd:64 } {IbsOpCtl=0xc0011033;IBS execution control IbsOpMaxCnt:16 :1 IbsOpEn:1 IbsOpVal:1 IbsOpCntCtl:1 IbsOpMaxCntExt:7 :5 IbsOpCurCnt:20 IbsOpCurCntExt:7 :5 } {IbsOpRip=0xc0011034;IBS Op logical address IbsOpRip:64 } {IbsOpData=0xc0011035;IBS Op data IbsCompToRetCtr:16 IbsTagToRetCtr:16 IbsOpBrnResync:1 IbsOpMispReturn:1 IbsOpReturn:1 IbsOpBrnTaken:1 IbsOpBrnMisp:1 IbsOpBrnRet:1 IbsRipInvalid:1 :25 } {IbsOpData2=0xc0011036;IBS Op data 2 NbIbsReqSrc:3 :61 } {IbsOpData3=0xc0011037;IBS Op data 3 IbsLdOp:1 IbsStOp:1 IbsDcL1tlbMiss:1 IbsDcL2tlbMiss:1 IbsDcL1tlbHit2M:1 IbsDcL1tlbHit1G:1 IbsDcL2tlbHit2M:1 IbsDcMiss:1 IbsDcMisAcc:1 IbsDcLdBnkCon:1 IbsDcStBnkCon:1 IbsDcStToLdFwd:1 IbsDcStToLdCan:1 IbsDcWcMemAcc:1 IbsDcUcMemAcc:1 IbsDcLockedOp:1 IbsDcMabHit:1 IbsDcLinAddrValid:1 IbsDcPhyAddrValid:1 IbsDcL2tlbHit1G:1 :12 IbsDcMissLat:16 :16 } {IbsDcLinAd=0xc0011038;IBS DC linear address IbsDcLinAd:64 } {IbsDcPhysAd=0xc0011039;IBS DC physical address IbsDcPhysAd:64 } {IbsControl=0xc001103a;IBS control LvtOffset:4 :4 LvtOffsetVal:1 :55 } {IbsBranchTargetAddress=0xc001103b;IBS branch target address IbsBrTarget:64 } ### Local Variables: ### ### mode:shell-script ### ### End: ### AMD/fam14h.regs000066400000000000000000000564041167043552300134400ustar00rootroot00000000000000# Author: Andreas Herrmann # # Copyright (C) 2011 Advanced Micro Devices, Inc. # This file contains information from: # - "43170 Rev 3.09 - May 02, 2011, BIOS and Kernel Developer's Guide (BKDG) # for AMD Family 14h Models 00h-0Fh Processors" # See scripts/createheader.py for the general format of this register # definitions. {LSMCAaddr=0x0000;load-store MCA address ADDR:48 :16 } # alias of MC0_ADDR {LSMCAstatus=0x0001;load-store MCE status ErrorCode:16 ErrorCodeExt:4 :37 PCC:1 AddrV:1 :1 En:1 UC:1 OVER:1 VAL:1 } # alias of MC0_STATUS {TSC=0x0010;time-stamp counter TSC:64 } {APIC_BASE=0x001b;APIC base address :8 BSC:1 :2 ApicEn:1 ApicBar:28 :24 } {EBL_CR_POWERON=0x002a;cluster ID :16 ClusterID:2 :46 } {PATCH_LEVEL=0x008b;microcode patch level PATCH_LEVEL:32 :32 } {MPERF=0x00e7;max performance frequency clock count MPERF:64 } {APERF=0x00e8;actual performance frequency clock count APERF:64 } {MTRRcap=0x00fe;MTRR capabilities MtrrCapVCnt:8 MtrrCapFix:1 :1 MtrrCapWc:1 :53 } {SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector SYSENTER_CS:16 :48 } {SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer SYSENTER_ESP:32 :32 } {SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer SYSENTER_EIP:32 :32 } {MCG_CAP=0x0179;global MC capabilities Count:8 MCG_CTL_P:1 :55 } {MCG_STAT=0x017a;global MC status RIPV:1 EIPV:1 MCIP:1 :61 } {MCG_CTL=0x017b;global MC control MC0En:1 MC1En:1 MC2En:1 MC3En:1 MC4En:1 MC5En:1 :58 } {DBG_CTL_MSR=0x01d9;debug control LBR:1 BTF:1 PB0:1 PB1:1 PB2:1 PB3:1 :58 } {BR_FROM=0x01db;last branch from IP LastBranchFromIP:64 } {BR_TO=0x01dc;last branch to IP LastBranchToIP:64 } {LastExceptionFromIP=0x01dd;last exception from IP LastIntFromIP:64 } {LastExceptionToIP=0x01de;last exception to IP LastIntToIP:64 } {MTRRphysBase0=0x0200;base of variable-size MTRR (0) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask0=0x0201;mask of variable-size MTRR (0) :11 Valid:1 PhysMask:24 :28 } {MTRRphysBase1=0x0202;base of variable-size MTRR (1) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask1=0x0203;mask of variable-size MTRR (1) :11 Valid:1 PhysMask:24 :28 } {MTRRphysBase2=0x0204;base of variable-size MTRR (2) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask2=0x0205;mask of variable-size MTRR (2) :11 Valid:1 PhysMask:24 :28 } {MTRRphysBase3=0x0206;base of variable-size MTRR (3) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask3=0x0207;mask of variable-size MTRR (3) :11 Valid:1 PhysMask:24 :28 } {MTRRphysBase4=0x0208;base of variable-size MTRR (4) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask4=0x0209;mask of variable-size MTRR (4) :11 Valid:1 PhysMask:24 :28 } {MTRRphysBase5=0x020a;base of variable-size MTRR (5) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask5=0x020b;mask of variable-size MTRR (5) :11 Valid:1 PhysMask:24 :28 } {MTRRphysBase6=0x020c;base of variable-size MTRR (6) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask6=0x020d;mask of variable-size MTRR (6) :11 Valid:1 PhysMask:24 :28 } {MTRRphysBase7=0x020e;base of variable-size MTRR (7) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:24 :28 } {MTRRphysMask7=0x020f;mask of variable-size MTRR (7) :11 Valid:1 PhysMask:24 :28 } {MTRRfix64K_00000=0x0250;fixed range MTRR 0xxxxMemType:3 0xxxxWrDram:1 0xxxxRdDram:1 :3 1xxxxMemType:3 1xxxxWrDram:1 1xxxxRdDram:1 :3 2xxxxMemType:3 2xxxxWrDram:1 2xxxxRdDram:1 :3 3xxxxMemType:3 3xxxxWrDram:1 3xxxxRdDram:1 :3 4xxxxMemType:3 4xxxxWrDram:1 4xxxxRdDram:1 :3 5xxxxMemType:3 5xxxxWrDram:1 5xxxxRdDram:1 :3 6xxxxMemType:3 6xxxxWrDram:1 6xxxxRdDram:1 :3 7xxxxMemType:3 7xxxxWrDram:1 7xxxxRdDram:1 :3 } {MTRRfix16K_80000=0x0258;fixed range MTRR 80xxxMemType:3 80xxxWrDram:1 80xxxRdDram:1 :3 84xxxMemType:3 84xxxWrDram:1 84xxxRdDram:1 :3 88xxxMemType:3 88xxxWrDram:1 88xxxRdDram:1 :3 8CxxxMemType:3 8CxxxWrDram:1 8CxxxRdDram:1 :3 90xxxMemType:3 90xxxWrDram:1 90xxxRdDram:1 :3 94xxxMemType:3 94xxxWrDram:1 94xxxRdDram:1 :3 98xxxMemType:3 98xxxWrDram:1 98xxxRdDram:1 :3 9CxxxMemType:3 9CxxxWrDram:1 9CxxxRdDram:1 :3 } {MTRRfix16K_A0000=0x0259;fixed range MTRR A0xxxMemType:3 A0xxxWrDram:1 A0xxxRdDram:1 :3 A4xxxMemType:3 A4xxxWrDram:1 A4xxxRdDram:1 :3 A8xxxMemType:3 A8xxxWrDram:1 A8xxxRdDram:1 :3 ACxxxMemType:3 ACxxxWrDram:1 ACxxxRdDram:1 :3 B0xxxMemType:3 B0xxxWrDram:1 B0xxxRdDram:1 :3 B4xxxMemType:3 B4xxxWrDram:1 B4xxxRdDram:1 :3 B8xxxMemType:3 B8xxxWrDram:1 B8xxxRdDram:1 :3 BCxxxMemType:3 BCxxxWrDram:1 BCxxxRdDram:1 :3 } {MTRRfix4K_C0000=0x0268;fixed range MTRR C0xxxMemType:3 C0xxxWrDram:1 C0xxxRdDram:1 :3 C1xxxMemType:3 C1xxxWrDram:1 C1xxxRdDram:1 :3 C2xxxMemType:3 C2xxxWrDram:1 C2xxxRdDram:1 :3 C3xxxMemType:3 C3xxxWrDram:1 C3xxxRdDram:1 :3 C4xxxMemType:3 C4xxxWrDram:1 C4xxxRdDram:1 :3 C5xxxMemType:3 C5xxxWrDram:1 C5xxxRdDram:1 :3 C6xxxMemType:3 C6xxxWrDram:1 C6xxxRdDram:1 :3 C7xxxMemType:3 C7xxxWrDram:1 C7xxxRdDram:1 :3 } {MTRRfix4K_C8000=0x0269;fixed range MTRR C8xxxMemType:3 C8xxxWrDram:1 C8xxxRdDram:1 :3 C9xxxMemType:3 C9xxxWrDram:1 C9xxxRdDram:1 :3 CAxxxMemType:3 CAxxxWrDram:1 CAxxxRdDram:1 :3 CBxxxMemType:3 CBxxxWrDram:1 CBxxxRdDram:1 :3 CCxxxMemType:3 CCxxxWrDram:1 CCxxxRdDram:1 :3 CDxxxMemType:3 CDxxxWrDram:1 CDxxxRdDram:1 :3 CExxxMemType:3 CExxxWrDram:1 CExxxRdDram:1 :3 CFxxxMemType:3 CFxxxWrDram:1 CFxxxRdDram:1 :3 } {MTRRfix4K_D0000=0x026a;fixed range MTRR D0xxxMemType:3 D0xxxWrDram:1 D0xxxRdDram:1 :3 D1xxxMemType:3 D1xxxWrDram:1 D1xxxRdDram:1 :3 D2xxxMemType:3 D2xxxWrDram:1 D2xxxRdDram:1 :3 D3xxxMemType:3 D3xxxWrDram:1 D3xxxRdDram:1 :3 D4xxxMemType:3 D4xxxWrDram:1 D4xxxRdDram:1 :3 D5xxxMemType:3 D5xxxWrDram:1 D5xxxRdDram:1 :3 D6xxxMemType:3 D6xxxWrDram:1 D6xxxRdDram:1 :3 D7xxxMemType:3 D7xxxWrDram:1 D7xxxRdDram:1 :3 } {MTRRfix4K_D8000=0x026b;fixed range MTRR D8xxxMemType:3 D8xxxWrDram:1 D8xxxRdDram:1 :3 D9xxxMemType:3 D9xxxWrDram:1 D9xxxRdDram:1 :3 DAxxxMemType:3 DAxxxWrDram:1 DAxxxRdDram:1 :3 DBxxxMemType:3 DBxxxWrDram:1 DBxxxRdDram:1 :3 DCxxxMemType:3 DCxxxWrDram:1 DCxxxRdDram:1 :3 DDxxxMemType:3 DDxxxWrDram:1 DDxxxRdDram:1 :3 DExxxMemType:3 DExxxWrDram:1 DExxxRdDram:1 :3 DFxxxMemType:3 DFxxxWrDram:1 DFxxxRdDram:1 :3 } {MTRRfix4K_E0000=0x026c;fixed range MTRR E0xxxMemType:3 E0xxxWrDram:1 E0xxxRdDram:1 :3 E1xxxMemType:3 E1xxxWrDram:1 E1xxxRdDram:1 :3 E2xxxMemType:3 E2xxxWrDram:1 E2xxxRdDram:1 :3 E3xxxMemType:3 E3xxxWrDram:1 E3xxxRdDram:1 :3 E4xxxMemType:3 E4xxxWrDram:1 E4xxxRdDram:1 :3 E5xxxMemType:3 E5xxxWrDram:1 E5xxxRdDram:1 :3 E6xxxMemType:3 E6xxxWrDram:1 E6xxxRdDram:1 :3 E7xxxMemType:3 E7xxxWrDram:1 E7xxxRdDram:1 :3 } {MTRRfix4K_E8000=0x026d;fixed range MTRR E8xxxMemType:3 E8xxxWrDram:1 E8xxxRdDram:1 :3 E9xxxMemType:3 E9xxxWrDram:1 E9xxxRdDram:1 :3 EAxxxMemType:3 EAxxxWrDram:1 EAxxxRdDram:1 :3 EBxxxMemType:3 EBxxxWrDram:1 EBxxxRdDram:1 :3 ECxxxMemType:3 ECxxxWrDram:1 ECxxxRdDram:1 :3 EDxxxMemType:3 EDxxxWrDram:1 EDxxxRdDram:1 :3 EExxxMemType:3 EExxxWrDram:1 EExxxRdDram:1 :3 EFxxxMemType:3 EFxxxWrDram:1 EFxxxRdDram:1 :3 } {MTRRfix4K_F0000=0x026e;fixed range MTRR F0xxxMemType:3 F0xxxWrDram:1 F0xxxRdDram:1 :3 F1xxxMemType:3 F1xxxWrDram:1 F1xxxRdDram:1 :3 F2xxxMemType:3 F2xxxWrDram:1 F2xxxRdDram:1 :3 F3xxxMemType:3 F3xxxWrDram:1 F3xxxRdDram:1 :3 F4xxxMemType:3 F4xxxWrDram:1 F4xxxRdDram:1 :3 F5xxxMemType:3 F5xxxWrDram:1 F5xxxRdDram:1 :3 F6xxxMemType:3 F6xxxWrDram:1 F6xxxRdDram:1 :3 F7xxxMemType:3 F7xxxWrDram:1 F7xxxRdDram:1 :3 } {MTRRfix4K_F8000=0x026f;fixed range MTRR F8xxxMemType:3 F8xxxWrDram:1 F8xxxRdDram:1 :3 F9xxxMemType:3 F9xxxWrDram:1 F9xxxRdDram:1 :3 FAxxxMemType:3 FAxxxWrDram:1 FAxxxRdDram:1 :3 FBxxxMemType:3 FBxxxWrDram:1 FBxxxRdDram:1 :3 FCxxxMemType:3 FCxxxWrDram:1 FCxxxRdDram:1 :3 FDxxxMemType:3 FDxxxWrDram:1 FDxxxRdDram:1 :3 FExxxMemType:3 FExxxWrDram:1 FExxxRdDram:1 :3 FFxxxMemType:3 FFxxxWrDram:1 FFxxxRdDram:1 :3 } {PAT=0x0277;page attribute table PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 } {MTRRdefType=0x02ff;MTRR default memory type MemType:8 :2 MtrrDefTypeFixEn:1 MtrrDefTypeEn:1 :52 } {MC0_CTL=0x0400;data cache MC control :2 DDP:1 DTP:1 :2 TLBP:1 :1 SRDEL:1 SRDES:1 SRDET:1 SRDE_ALL:1 :52 } {MC0_STATUS=0x0401;data cache MC status ErrorCode:16 ErrorCodeExt:4 :37 PCC:1 AddrV:1 :1 En:1 UC:1 OVER:1 VAL:1 } {MC0_ADDR=0x0402;data cache MC address ADDR:48 :16 } {MC0_MISC=0x0403;data cache MC miscellaneous :64 } {MC1_CTL=0x0404;instruction cache MC control :2 IDP:1 ITP:1 ISTP:1 :1 TLBP:1 :2 SRDE:1 :54 } {MC1_STATUS=0x0405;instruction cache MC status ErrorCode:16 ErrorCodeExt:4 :37 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC1_ADDR=0x0406;instruction cache MC address ADDR:48 :16 } {MC1_MISC=0x0407;instruction cache MC miscellaneous :64 } {MC2_CTL=0x0408;bus unit MC control :4 TagCor:1 TagUncor:1 DataParity:1 DataCor:1 DataUncor:1 :3 TagMultiHit:1 AttrParity:1 :50 } {MC2_STATUS=0x0409;bus unit MC status ErrorCode:16 ErrorCodeExt:5 :24 UECC:1 CECC:1 :10 PCC:1 AddrV:1 :1 En:1 UC:1 OVER:1 VAL:1 } {MC2_ADDR=0x040a;bus unit MC address register ADDR:36 :28 } {MC2_MISC=0x040b;bus unit MC miscellaneous :64 } {MC3_CTL=0x040c;reserved :64 } {MC3_STATUS=0x040d;reserved :64 } {MC3_ADDR=0x040e;reserved :64 } {MC3_MISC=0x040f;reserved :64 } {MC4_CTL=0x0410;northbridge MC control :5 SyncFloodEn:1 :2 MstrAbrtEn:1 TgtAbrtEn:1 :1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 :2 NbIntProtEn:1 CpPktDatEn:1 :7 UsPwDatErrEn:1 :38 } {MC4_STATUS=0x0411;northbridge MC status ErrorCode:16 ErrorCodeExt:5 :11 ErrCpu0:1 ErrCpu1:1 :2 BusErr:1 :20 PCC:1 AddrV:1 :1 En:1 UC:1 Over:1 Val:1 } {MC4_ADDR=0x0412;northbridge MC address McaNbAddrLow:32 McaNbAddrHigh:32 } {MC4_MISC0=0x0413;reserved (northbridge MC misc) :64 } {MC5_CTL=0x0414;reorder buffer MC control CPUWDT:1 :63 } {MC5_STATUS=0x0415;reorder buffer MC status ErrorCode:16 :41 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 OVER:1 VAL:1 } {MC5_ADDR=0x0416;reorder buffer MC address ADDR:48 :16 } {MC5_MISC=0x0417;reorder buffer MC miscellaneous FrCompl:8 :56 } {EFER=0xc0000080;extended feature enable SYSCALL:1 :7 LME:1 :1 LMA:1 NXE:1 SVME:1 LMSLE:1 FFXSE:1 :49 } {STAR=0xc0000081;SYSCALL target address Target:32 SysCallSel:16 SysRetSel:16 } {STAR64=0xc0000082;long mode SYSCALL target address LSTAR:64 } {STARCOMPAT=0xc0000083;compat mode SYSCALL target address CSTAR:64 } {SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask MASK:32 :32 } {FS_BASE=0xc0000100;FS base FS_BASE:64 } {GS_BASE=0xc0000101;GS base GS_BASE:64 } {KernelGSbase=0xc0000102;kernel GS base KernelGSBase:64 } {TSC_AUX=0xc0000103;auxiliary time stamp counter data TscAux:32 :32 } {PERF_CTL0=0xc0010000;performance event select (0) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL1=0xc0010001;performance event select (1) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL2=0xc0010002;performance event select (2) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTL3=0xc0010003;performance event select (3) EventSelect:8 UnitMask:8 User:1 OS:1 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 GuestOnly:1 HostOnly:1 :22 } {PERF_CTR0=0xc0010004;performance event counter (0) CTR:48 :16 } {PERF_CTR1=0xc0010005;performance event counter (1) CTR:48 :16 } {PERF_CTR2=0xc0010006;performance event counter (2) CTR:48 :16 } {PERF_CTR3=0xc0010007;performance event counter (3) CTR:48 :16 } {SYS_CFG=0xc0010010;system configuration :17 SysUcLockEn:1 MtrrFixDramEn:1 MtrrFixDramModeEn:1 MtrrVarDramEn:1 MtrrTom2En:1 Tom2ForceMemTypeWB:1 :41 } {HWCR=0xc0010015;hardware configuration SmmLock:1 :2 TlbCacheDis:1 INVD_WBINVD:1 :3 IgnneEm:1 MonMwaitDis:1 MonMwaitUserEn:1 :2 SmiSpCycDis:1 RsmSpCycDis:1 SseDis:1 :1 Wrap32Dis:1 McStatusWrEn:1 :1 IoCfgGpFault:1 MisAlignSseDis:1 :1 ForceUsRdWrSzPrb:1 TscFreqSel:1 :1 EffFreqCntMwait:1 :37 } {IORR_BASE0=0xc0010016;base of variable I/O range (0) :3 WrMem:1 RdMem:1 :7 PhyBase:24 :28 } {IORR_MASK0=0xc0010017;mask of variable I/O range (0) :11 Valid:1 PhyMask:24 :28 } {IORR_BASE1=0xc0010018;base of variable I/O range (1) :3 WrMem:1 RdMem:1 :7 PhyBase:24 :28 } {IORR_MASK1=0xc0010019;mask of variable I/O range (1) :11 Valid:1 PhyMask:24 :28 } {TOP_MEM=0xc001001a;top of memory address :23 TOM:13 :28 } {TOM2=0xc001001d;second top of memory address :23 TOM2:13 :28 } {NB_CFG=0xc001001f;northbridge configuration :45 DisUsSysMgtReqToNcHt:1 EnableCf8ExtCfg:1 :11 EnConvertToNonIsoc:1 :5 } {MCEredirection=0xc0010022;MCE redirection RedirVector:8 RedirVecEn:1 RedirSmiEn:1 :54 } {ProcessorNameString0=0xc0010030;processor name string (0) CpuNameString:64 } {ProcessorNameString1=0xc0010031;processor name string (1) CpuNameString:64 } {ProcessorNameString2=0xc0010032;processor name string (2) CpuNameString:64 } {ProcessorNameString3=0xc0010033;processor name string (3) CpuNameString:64 } {ProcessorNameString4=0xc0010034;processor name string (4) CpuNameString:64 } {ProcessorNameString5=0xc0010035;processor name string (5) CpuNameString:64 } {MC0_CTL_MASK=0xc0010044;data cache MC control mask :2 DDP:1 DTP:1 :2 TLBP:1 :1 SRDEL:1 SRDES:1 SRDET:1 SRDE_ALL:1 :52 } {MC1_CTL_MASK=0xc0010045;instruction cache MC control mask :2 IDP:1 ITP:1 ISTP:1 :1 TLBP:1 :2 SRDE:1 :54 } {MC2_CTL_MASK=0xc0010046;bus unit MC control mask :4 TagCor:1 TagUncor:1 DataParity:1 DataCor:1 DataUncor:1 :3 TagMultiHit:1 AttrParity:1 :50 } {MC3_CTL_MASK=0xc0010047;reserved :64 } {MC4_CTL_MASK=0xc0010048;northbridge MC control mask :5 SyncFloodEn:1 :2 MstrAbrtEn:1 TgtAbrtEn:1 :1 AtomicRMWEn:1 WDTRptEn:1 DevErrEn:1 :2 NbIntProtEn:1 CpPktDatEn:1 :7 UsPwDatErrEn:1 :38 } {MC5_CTL_MASK=0xc0010049;reorder buffer MC control mask CPUWDT:1 :63 } {SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control :1 SmiEn_0:1 :1 SmiEn_1:1 :1 SmiEn_2:1 :1 SmiEn_3:1 :7 IoTrapEn:1 :48 } {IntPendingMessage=0xc0010055;reserved :64 } {SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle IoPortAddress:16 IoData:8 :1 IoCycleEn:1 IoRd:1 :37 } {MmioConfigBase=0xc0010058;MMIO configuration base address Enable:1 :1 SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 :14 MmiocCfgBaseAddr:16 :28 } {BISTResults=0xc0010060;BIST Results BistResults:30 :34 } {PstateCurrentLimit=0xc0010061;P-state current limit CurPstateLimit:3 :1 PstateMaxVal:3 :57 } {PstateControl=0xc0010062;P-state control PstateCmd:3 :61 } {PstateStatus=0xc0010063;P-state status CurPstate:3 :61 } {Pstate0=0xc0010064;P-state 0 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate1=0xc0010065;P-state 1 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate2=0xc0010066;P-state 2 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate3=0xc0010067;P-state 3 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate4=0xc0010068;P-state 4 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate5=0xc0010069;P-state 5 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate6=0xc001006a;P-state 6 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate7=0xc001006b;P-state 7 CpuDidLSD:4 CpuDidMSD:5 CpuVid:7 :16 IddValue:8 IddDiv:2 :21 PstateEn:1 } {COFVIDstatus=0xc0010071;COFVID status CurCpuDidLSD:4 CurCpuDidMSD:5 CurCpuVid:7 CurPstate:3 :1 PstateInProgress:1 :4 CurNbVid:7 StartupPstate:3 MaxVid:7 MinVid:7 MainPllOpFreqIdMax:6 :1 CurPstateLimit:3 :5 } {CstateAddress=0xc0010073;C-state address CstateAddr:16 :48 } {CpuWdTmrCfg=0xc0010074;CPU watchdog timer CpuWdtEn:1 CpuWdtTimeBase:2 CpuWdtCountSel:4 :57 } {SMM_BASE=0xc0010111;SMM base address SMM_BASE:32 :32 } {SMMAddr=0xc0010112;SMM TSeg base address :17 TSegBase:19 :28 } {SMMMask=0xc0010113;SMM Tseg mask AValid:1 TValid:1 AClose:1 TClose:1 AMTypeIoWc:1 TMTypeIoWc:1 :2 AMTypeDram:3 :1 TMTypeDram:3 :2 TSegMask:19 :28 } {VM_CR=0xc0010114;virtual machine control dpd:1 r_init:1 dis_a20m:1 Lock:1 Svme_Disable:1 :59 } {IGNNE=0xc0010115;IGNNE IGNNE:1 :63 } # {SMM_CTL=0xc0010116;SMM control # smm_dismiss:1 # smm_enter:1 # smi_cyle:1 # smm_exit:1 # rsm_cycle:1 # :59 # } # write-only {VM_HSAVE_PA=0xc0010117;virtual machine host save physical address :12 VM_HSAVE_PA:24 :28 } # {SVMLock=0xc0010118;SVM lock key # SvmLockKey:64 # } # write-only {SMIstatus=0xc001011a;local SMI status IoTrapSts:4 :4 MceRedirSts:1 :7 SmiSrcLvtLcy:1 SmiSrcLvtExt:1 :46 } {OSVW_ID_Length=0xc0010140;OS visible work-around OSVW_ID_Length:16 :48 } {OsvwStatus=0xc0010141;OS visible work-around status bits OsvwStatusBits:64 } {CPUIDFeatures=0xc0011004;CPUID features FeaturesEdx:32 FeaturesEcx:32 } {CPUIDExtFeatures=0xc0011005;extended CPUID features ExtFeaturesEdx:32 ExtFeaturesEcx:32 } {LS_CFG=0xc0011020;load store configuration :28 DisStreamSt:1 :35 } {IC_CFG=0xc0011021;instruction cache configuration :9 DIS_SPEC_TLB_RLD:1 :54 } {DC_CFG=0xc0011022;data cache configuration :13 DIS_HW_PF:1 :50 } {IbsFetchCtl=0xc0011030;IBS fetch control IbsFetchMaxCnt:16 IbsFetchCnt:16 IbsFetchLat:16 IbsFetchEn:1 IbsFetchVal:1 IbsFetchComp:1 IbsIcMiss:1 IbsPhyAddrValid:1 IbsL1TlbPgSz:2 IbsL1TlbMiss:1 IbsL2TlbMiss:1 IbsRandEn:1 :6 } {IbsFetchLinAd=0xc0011031;IBS fetch linear address IbsFetchLinAd:64 } {IbsFetchPhysAd=0xc0011032;IBS fetch physical address IbsFetchPhysAd:36 :28 } {IbsOpCtl=0xc0011033;IBS execution control IbsOpMaxCnt:16 :1 IbsOpEn:1 IbsOpVal:1 IbsOpCntCtl:1 IbsOpMaxCntExt:7 :5 IbsOpCurCnt:20 IbsOpCurCntExt:7 :5 } {IbsOpRip=0xc0011034;IBS Op logical address IbsOpRip:64 } {IbsOpData=0xc0011035;IBS Op data IbsCompToRetCtr:16 IbsTagToRetCtr:16 IbsOpBrnResync:1 IbsOpMispReturn:1 IbsOpReturn:1 IbsOpBrnTaken:1 IbsOpBrnMisp:1 IbsOpBrnRet:1 IbsRipInvalid:1 :25 } {IbsOpData2=0xc0011036;IBS Op data 2 NbIbsReqSrc:3 :61 } {IbsOpData3=0xc0011037;IBS Op data 3 IbsLdOp:1 IbsStOp:1 IbsDcL1tlbMiss:1 IbsDcL2tlbMiss:1 IbsDcL1tlbHit2M:1 :1 IbsDcL2tlbHit2M:1 IbsDcMiss:1 IbsDcMisAcc:1 :2 IbsDcStToLdFwd:1 :1 IbsDcWcMemAcc:1 IbsDcUcMemAcc:1 IbsDcLockedOp:1 IbsDcMabHit:1 IbsDcLinAddrValid:1 IbsDcPhyAddrValid:1 :13 IbsDcMissLat:16 :16 } {IbsDcLinAd=0xc0011038;IBS DC linear address IbsDcLinAd:64 } {IbsDcPhysAd=0xc0011039;IBS DC physical address IbsDcPhysAd:36 :28 } {IbsControl=0xc001103a;IBS control LvtOffset:4 :4 LvtOffsetVal:1 :55 } {IbsBranchTargetAddress=0xc001103b;IBS branch target address IbsBrTarget:64 } ### Local Variables: ### ### mode:shell-script ### ### End: ### AMD/fam15h.regs000066400000000000000000000774111167043552300134420ustar00rootroot00000000000000# Author: Andreas Herrmann # # Copyright (C) 2011 Advanced Micro Devices, Inc. # # This file contains information from: # - "42301 Rev 3.02 - October 18, 2011, BIOS and Kernel Developer's # Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors" # See scripts/createheader.py for the general format of this register # definitions. {LSMCAaddr=0x0000;load-store MCA address ADDR:64 } # alias of MC0_ADDR {LSMCAstatus=0x0001;load-store MCE status ErrorCode:16 ErrorCodeExt:5 :15 Way:4 :3 Poison:1 Deferred:1 :12 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Overflow:1 Val:1 } # alias of MC0_STATUS {TSC=0x0010;time-stamp counter TSC:64 } {APIC_BASE=0x001b;APIC base address :8 BSC:1 :1 Apicx2En:1 ApicEn:1 ApicBar:28 :24 } {EBL_CR_POWERON=0x002a;cluster ID :16 ClusterID:2 :46 } {PATCH_LEVEL=0x008b;microcode patch level (sharedC) PATCH_LEVEL:32 :32 } {MPERF=0x00e7;max performance frequency clock count MPERF:64 } {APERF=0x00e8;actual performance frequency clock count APERF:64 } {MTRRcap=0x00fe;MTRR capabilities MtrrCapVCnt:8 MtrrCapFix:1 :1 MtrrCapWc:1 :53 } {SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector SYSENTER_CS:16 :48 } {SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer SYSENTER_ESP:32 :32 } {SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer SYSENTER_EIP:32 :32 } {MCG_CAP=0x0179;global MC capabilities Count:8 MCG_CTL_P:1 :55 } {MCG_STAT=0x017a;global MC status RIPV:1 EIPV:1 MCIP:1 :61 } {MCG_CTL=0x017b;global MC control LS:1 IF:1 CU:1 :1 NB:1 EX:1 FP:1 :57 } {DBG_CTL_MSR=0x01d9;debug control LBR:1 BTF:1 PB0:1 PB1:1 PB2:1 PB3:1 :58 } {BR_FROM=0x01db;last branch from IP LastBranchFromIP:64 } {BR_TO=0x01dc;last branch to IP LastBranchToIP:64 } {LastExceptionFromIP=0x01dd;last exception from IP LastIntFromIP:64 } {LastExceptionToIP=0x01de;last exception to IP LastIntToIP:64 } {MTRRphysBase0=0x0200;base of variable-size MTRR (0) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask0=0x0201;mask of variable-size MTRR (0) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase1=0x0202;base of variable-size MTRR (1) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask1=0x0203;mask of variable-size MTRR (1) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase2=0x0204;base of variable-size MTRR (2) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask2=0x0205;mask of variable-size MTRR (2) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase3=0x0206;base of variable-size MTRR (3) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask3=0x0207;mask of variable-size MTRR (3) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase4=0x0208;base of variable-size MTRR (4) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask4=0x0209;mask of variable-size MTRR (4) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase5=0x020a;base of variable-size MTRR (5) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask5=0x020b;mask of variable-size MTRR (5) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase6=0x020c;base of variable-size MTRR (6) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask6=0x020d;mask of variable-size MTRR (6) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase7=0x020e;base of variable-size MTRR (7) (sharedC) MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB :9 PhyBase:36 :16 } {MTRRphysMask7=0x020f;mask of variable-size MTRR (7) (sharedC) :11 Valid:1 PhysMask:36 :16 } {MTRRfix64K_00000=0x0250;fixed range MTRR (sharedC) 0xxxxMemType:3 0xxxxWrDram:1 0xxxxRdDram:1 :3 1xxxxMemType:3 1xxxxWrDram:1 1xxxxRdDram:1 :3 2xxxxMemType:3 2xxxxWrDram:1 2xxxxRdDram:1 :3 3xxxxMemType:3 3xxxxWrDram:1 3xxxxRdDram:1 :3 4xxxxMemType:3 4xxxxWrDram:1 4xxxxRdDram:1 :3 5xxxxMemType:3 5xxxxWrDram:1 5xxxxRdDram:1 :3 6xxxxMemType:3 6xxxxWrDram:1 6xxxxRdDram:1 :3 7xxxxMemType:3 7xxxxWrDram:1 7xxxxRdDram:1 :3 } {MTRRfix16K_80000=0x0258;fixed range MTRR (sharedC) 80xxxMemType:3 80xxxWrDram:1 80xxxRdDram:1 :3 84xxxMemType:3 84xxxWrDram:1 84xxxRdDram:1 :3 88xxxMemType:3 88xxxWrDram:1 88xxxRdDram:1 :3 8CxxxMemType:3 8CxxxWrDram:1 8CxxxRdDram:1 :3 90xxxMemType:3 90xxxWrDram:1 90xxxRdDram:1 :3 94xxxMemType:3 94xxxWrDram:1 94xxxRdDram:1 :3 98xxxMemType:3 98xxxWrDram:1 98xxxRdDram:1 :3 9CxxxMemType:3 9CxxxWrDram:1 9CxxxRdDram:1 :3 } {MTRRfix16K_A0000=0x0259;fixed range MTRR (sharedC) A0xxxMemType:3 A0xxxWrDram:1 A0xxxRdDram:1 :3 A4xxxMemType:3 A4xxxWrDram:1 A4xxxRdDram:1 :3 A8xxxMemType:3 A8xxxWrDram:1 A8xxxRdDram:1 :3 ACxxxMemType:3 ACxxxWrDram:1 ACxxxRdDram:1 :3 B0xxxMemType:3 B0xxxWrDram:1 B0xxxRdDram:1 :3 B4xxxMemType:3 B4xxxWrDram:1 B4xxxRdDram:1 :3 B8xxxMemType:3 B8xxxWrDram:1 B8xxxRdDram:1 :3 BCxxxMemType:3 BCxxxWrDram:1 BCxxxRdDram:1 :3 } {MTRRfix4K_C0000=0x0268;fixed range MTRR (sharedC) C0xxxMemType:3 C0xxxWrDram:1 C0xxxRdDram:1 :3 C1xxxMemType:3 C1xxxWrDram:1 C1xxxRdDram:1 :3 C2xxxMemType:3 C2xxxWrDram:1 C2xxxRdDram:1 :3 C3xxxMemType:3 C3xxxWrDram:1 C3xxxRdDram:1 :3 C4xxxMemType:3 C4xxxWrDram:1 C4xxxRdDram:1 :3 C5xxxMemType:3 C5xxxWrDram:1 C5xxxRdDram:1 :3 C6xxxMemType:3 C6xxxWrDram:1 C6xxxRdDram:1 :3 C7xxxMemType:3 C7xxxWrDram:1 C7xxxRdDram:1 :3 } {MTRRfix4K_C8000=0x0269;fixed range MTRR (sharedC) C8xxxMemType:3 C8xxxWrDram:1 C8xxxRdDram:1 :3 C9xxxMemType:3 C9xxxWrDram:1 C9xxxRdDram:1 :3 CAxxxMemType:3 CAxxxWrDram:1 CAxxxRdDram:1 :3 CBxxxMemType:3 CBxxxWrDram:1 CBxxxRdDram:1 :3 CCxxxMemType:3 CCxxxWrDram:1 CCxxxRdDram:1 :3 CDxxxMemType:3 CDxxxWrDram:1 CDxxxRdDram:1 :3 CExxxMemType:3 CExxxWrDram:1 CExxxRdDram:1 :3 CFxxxMemType:3 CFxxxWrDram:1 CFxxxRdDram:1 :3 } {MTRRfix4K_D0000=0x026a;fixed range MTRR (sharedC) D0xxxMemType:3 D0xxxWrDram:1 D0xxxRdDram:1 :3 D1xxxMemType:3 D1xxxWrDram:1 D1xxxRdDram:1 :3 D2xxxMemType:3 D2xxxWrDram:1 D2xxxRdDram:1 :3 D3xxxMemType:3 D3xxxWrDram:1 D3xxxRdDram:1 :3 D4xxxMemType:3 D4xxxWrDram:1 D4xxxRdDram:1 :3 D5xxxMemType:3 D5xxxWrDram:1 D5xxxRdDram:1 :3 D6xxxMemType:3 D6xxxWrDram:1 D6xxxRdDram:1 :3 D7xxxMemType:3 D7xxxWrDram:1 D7xxxRdDram:1 :3 } {MTRRfix4K_D8000=0x026b;fixed range MTRR (sharedC) D8xxxMemType:3 D8xxxWrDram:1 D8xxxRdDram:1 :3 D9xxxMemType:3 D9xxxWrDram:1 D9xxxRdDram:1 :3 DAxxxMemType:3 DAxxxWrDram:1 DAxxxRdDram:1 :3 DBxxxMemType:3 DBxxxWrDram:1 DBxxxRdDram:1 :3 DCxxxMemType:3 DCxxxWrDram:1 DCxxxRdDram:1 :3 DDxxxMemType:3 DDxxxWrDram:1 DDxxxRdDram:1 :3 DExxxMemType:3 DExxxWrDram:1 DExxxRdDram:1 :3 DFxxxMemType:3 DFxxxWrDram:1 DFxxxRdDram:1 :3 } {MTRRfix4K_E0000=0x026c;fixed range MTRR (sharedC) E0xxxMemType:3 E0xxxWrDram:1 E0xxxRdDram:1 :3 E1xxxMemType:3 E1xxxWrDram:1 E1xxxRdDram:1 :3 E2xxxMemType:3 E2xxxWrDram:1 E2xxxRdDram:1 :3 E3xxxMemType:3 E3xxxWrDram:1 E3xxxRdDram:1 :3 E4xxxMemType:3 E4xxxWrDram:1 E4xxxRdDram:1 :3 E5xxxMemType:3 E5xxxWrDram:1 E5xxxRdDram:1 :3 E6xxxMemType:3 E6xxxWrDram:1 E6xxxRdDram:1 :3 E7xxxMemType:3 E7xxxWrDram:1 E7xxxRdDram:1 :3 } {MTRRfix4K_E8000=0x026d;fixed range MTRR (sharedC) E8xxxMemType:3 E8xxxWrDram:1 E8xxxRdDram:1 :3 E9xxxMemType:3 E9xxxWrDram:1 E9xxxRdDram:1 :3 EAxxxMemType:3 EAxxxWrDram:1 EAxxxRdDram:1 :3 EBxxxMemType:3 EBxxxWrDram:1 EBxxxRdDram:1 :3 ECxxxMemType:3 ECxxxWrDram:1 ECxxxRdDram:1 :3 EDxxxMemType:3 EDxxxWrDram:1 EDxxxRdDram:1 :3 EExxxMemType:3 EExxxWrDram:1 EExxxRdDram:1 :3 EFxxxMemType:3 EFxxxWrDram:1 EFxxxRdDram:1 :3 } {MTRRfix4K_F0000=0x026e;fixed range MTRR (sharedC) F0xxxMemType:3 F0xxxWrDram:1 F0xxxRdDram:1 :3 F1xxxMemType:3 F1xxxWrDram:1 F1xxxRdDram:1 :3 F2xxxMemType:3 F2xxxWrDram:1 F2xxxRdDram:1 :3 F3xxxMemType:3 F3xxxWrDram:1 F3xxxRdDram:1 :3 F4xxxMemType:3 F4xxxWrDram:1 F4xxxRdDram:1 :3 F5xxxMemType:3 F5xxxWrDram:1 F5xxxRdDram:1 :3 F6xxxMemType:3 F6xxxWrDram:1 F6xxxRdDram:1 :3 F7xxxMemType:3 F7xxxWrDram:1 F7xxxRdDram:1 :3 } {MTRRfix4K_F8000=0x026f;fixed range MTRR (sharedC) F8xxxMemType:3 F8xxxWrDram:1 F8xxxRdDram:1 :3 F9xxxMemType:3 F9xxxWrDram:1 F9xxxRdDram:1 :3 FAxxxMemType:3 FAxxxWrDram:1 FAxxxRdDram:1 :3 FBxxxMemType:3 FBxxxWrDram:1 FBxxxRdDram:1 :3 FCxxxMemType:3 FCxxxWrDram:1 FCxxxRdDram:1 :3 FDxxxMemType:3 FDxxxWrDram:1 FDxxxRdDram:1 :3 FExxxMemType:3 FExxxWrDram:1 FExxxRdDram:1 :3 FFxxxMemType:3 FFxxxWrDram:1 FFxxxRdDram:1 :3 } {PAT=0x0277;page attribute table PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 } {MTRRdefType=0x02ff;MTRR default memory type (sharedC) MemType:8 :2 MtrrDefTypeFixEn:1 MtrrDefTypeEn:1 :52 } {MC0_CTL=0x0400;load store MC control TagP:1 TLBP:1 DatP:1 LQP:1 SQP:1 SCBP:1 LineFillPoison:1 SRDE:1 IntErrType2:1 IntErrType1:1 :54 } {MC0_STATUS=0x0401;load store MC status ErrorCode:16 ErrorCodeExt:5 :15 Way:4 :3 Poison:1 Deferred:1 :12 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Overflow:1 Val:1 } {MC0_ADDR=0x0402;load store MC address ADDR:64 } {MC0_MISC=0x0403;load store MC miscellaneous :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 :2 CntEn:1 :10 CntP:1 Valid:1 } {MC1_CTL=0x0404;instruction fetch MC control (sharedC) :2 IDP:1 IMTP:1 ISTP:1 L2TP:1 L1TP:1 LineFillPoison:1 :1 SRDE:1 :2 PFBP:1 PQP:1 :1 BSRP:1 DEPRP:1 DEUOPQP:1 DEIBP:1 DPDBE:1 DFIFOE:1 L2TLBM:1 L1TLBM:1 IVP:1 :40 } {MC1_STATUS=0x0405;instruction fetch MC status ErrorCode:16 ErrorCodeExt:5 :15 Way:4 :3 Poison:1 Deferred:1 :12 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Overflow:1 Val:1 } {MC1_ADDR=0x0406;instruction fetch MC address ADDR:64 } {MC1_MISC=0x0407;instruction fetch MC miscellaneous :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 :2 CntEn:1 :10 CntP:1 Valid:1 } {MC2_CTL=0x0408;combined unit MC control (sharedC) L2TagMultiHit:1 VbData:1 WcbData:1 WccData:1 WccAddr:1 PrqData:1 PrqAddr:1 FillData:1 PrbAddr:1 XabAddr:1 L2Prefetch:1 L2TlbData:1 L2Tag:1 RdData:1 L2TlbPoison:1 :49 } {MC2_STATUS=0x0409;combined unit MC status ErrorCode:16 ErrorCodeExt:5 :3 Syndrome:4 :8 Way:4 :3 Poison:1 Deferred:1 UECC:1 CECC:1 Syndrome:8 :2 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Overflow:1 Val:1 } {MC2_ADDR=0x040a;combined unit MC address register ADDR:64 } {MC2_MISC=0x040b;combined unit MC miscellaneous :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 :2 CntEn:1 :10 CntP:1 Valid:1 } {MC3_CTL=0x040c;reserved :64 } {MC3_STATUS=0x040d;reserved :64 } {MC3_ADDR=0x040e;reserved :64 } {MC3_MISC=0x040f;reserved :64 } {MC4_CTL=0x0410;northbridge MC control CECCEn:1 UECCEn:1 CrcErrEn:3 SyncPktEn:3 MstrAbrtEn:1 TgtAbrtEn:1 GartTblWkEn:1 AtomicRMWEn:1 WDTRptEn:1 :1 L3ArrayCorEn:1 L3ArrayUCEn:1 ProtEn:1 HtDataEn:1 DramParEn:1 RtryHtEn:4 CrcErrEn:1 SyncPktEn:1 McaUsPwDatErrEn:1 NbArrayParEn:1 TblWlkDatErrEn:1 :3 McaCpuDatErrEn:1 :32 } {MC4_STATUS=0x0411;northbridge MC status ErrorCode:16 ErrorCodeExt:5 :3 Syndrome:8 ErrCoreId:4 Link:4 Scrub:1 SubLink:1 McaStatSubCache:2 :1 UECC:1 CECC:1 Syndrome:8 :1 ErrCoreIdVal:1 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Overflow:1 Val:1 } {MC4_ADDR=0x0412;northbridge MC address :1 ErrAddr:47 :16 } {MC4_MISC0=0x0413;northbridge MC misc (DRAM Thresholding) (0) :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 IntType:2 CntEn:1 LvtOffset:4 :5 Locked:1 CntP:1 Valid:1 } {MC5_CTL=0x0414;execution unit MC control :1 PICWAK:1 PLDAG:1 PLDEX:1 IDF:1 RETDISP:1 MAP:1 EX0PRF:1 EX1PRF:1 AG0PRF:1 AG1PRF:1 FRF:1 DE:1 :51 } {MC5_STATUS=0x0415;execution unit MC status ErrorCode:16 ErrorCodeExt:5 :36 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Overflow:1 Val:1 } {MC5_ADDR=0x0416;execution unit MC address ADDR:64 } {MC5_MISC=0x0417;execution unit MC miscellaneous :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 :2 CntEn:1 :10 CntP:1 Valid:1 } {MC6_CTL=0x0418;floating point unit MC control (sharedC) PRF:1 FreeList:1 Sched:1 :1 RetireQ:1 SRF:1 :58 } {MC6_STATUS=0x0419;floating point unit MC status ErrorCode:16 ErrorCodeExt:5 :36 PCC:1 AddrV:1 MiscV:1 En:1 UC:1 Overflow:1 Val:1 } {MC6_ADDR=0x041a;floating point unit MC address :64 } {MC6_MISC=0x041b;floating point unit MC miscellaneous :64 } {EFER=0xc0000080;extended feature enable SYSCALL:1 :7 LME:1 :1 LMA:1 NXE:1 SVME:1 LMSLE:1 FFXSE:1 :49 } {STAR=0xc0000081;SYSCALL target address Target:32 SysCallSel:16 SysRetSel:16 } {STAR64=0xc0000082;long mode SYSCALL target address LSTAR:64 } {STARCOMPAT=0xc0000083;compat mode SYSCALL target address CSTAR:64 } {SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask MASK:32 :32 } {FS_BASE=0xc0000100;FS base FS_BASE:64 } {GS_BASE=0xc0000101;GS base GS_BASE:64 } {KernelGSbase=0xc0000102;kernel GS base KernelGSBase:64 } {TSC_AUX=0xc0000103;auxiliary time stamp counter data TscAux:32 :32 } {TscRateMsr=0xc0000104;time stamp counter ratio TscRateMsrFrac:32 TscRateMsrInt:32 } {LWP_CFG=0xc0000105;lightweight profile configuration :1 LwpVAL:1 LwpIRE:1 LwpBRE:1 LwpDME:1 LwpCNH:1 LwpRNH:1 :24 LwpInt:1 LwpCoreId:8 LwpVector:8 :16 } {LWP_CBADDR=0xc0000106;leightweight profile control block address :6 LwpCbAddr:58 } {MC4_MISC1=0xc0000408;northbridge MC misc (Link Thresholding) (1) :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 IntType:2 CntEn:1 LvtOffset:4 :5 Locked:1 CntP:1 Valid:1 } {MC4_MISC2=0xc0000409;northbridge MC misc (L3 Thresholding) (2) :24 BlkPtr:8 ErrCnt:12 :4 Ovrflw:1 IntType:2 CntEn:1 LvtOffset:4 :5 Locked:1 CntP:1 Valid:1 } {MC4_MISC3=0xc000040a;reserved :64 } {LEG_PERF_CTL0=0xc0010000;performance event select (0) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } # alias of PERF_CTL0 {LEG_PERF_CTL1=0xc0010001;performance event select (1) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } # alias of PERF_CTL1 {LEG_PERF_CTL2=0xc0010002;performance event select (2) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } # alias of PERF_CTL2 {LEG_PERF_CTL3=0xc0010003;performance event select (3) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } # alias of PERF_CTL3 {LEG_PERF_CTR0=0xc0010004;performance event counter (0) CTR:48 :16 } # alias of PERF_CTR0 {LEG_PERF_CTR1=0xc0010005;performance event counter (1) CTR:48 :16 } # alias of PERF_CTR1 {LEG_PERF_CTR2=0xc0010006;performance event counter (2) CTR:48 :16 } # alias of PERF_CTR2 {LEG_PERF_CTR3=0xc0010007;performance event counter (3) CTR:48 :16 } # alias of PERF_CTR3 {SYS_CFG=0xc0010010;system configuration (sharedC) :16 ChxToDirtyDis:1 :1 MtrrFixDramEn:1 MtrrFixDramModeEn:1 MtrrVarDramEn:1 MtrrTom2En:1 Tom2ForceMemTypeWB:1 :41 } {HWCR=0xc0010015;hardware configuration SmmLock:1 :2 TlbCacheDis:1 INVDWBINVD:1 :3 IgnneEm:1 MonMwaitDis:1 MonMwaitUserEn:1 :1 HltXSpCycEn:1 SmiSpCycDis:1 RsmSpCycDis:1 :2 Wrap32Dis:1 McStatusWrEn:1 :1 IoCfgGpFault:1 :2 ForceRdWrSzPrb:1 TscFreqSel:1 CpbDis:1 EffFreqCntMwait:1 :37 } {IORR_BASE0=0xc0010016;base of variable I/O range (0) (sharedC) :3 WrMem:1 RdMem:1 :7 PhyBase:36 :16 } {IORR_MASK0=0xc0010017;mask of variable I/O range (0) (sharedC) :11 Valid:1 PhyMask:36 :16 } {IORR_BASE1=0xc0010018;base of variable I/O range (1) (sharedC) :3 WrMem:1 RdMem:1 :7 PhyBase:36 :16 } {IORR_MASK1=0xc0010019;mask of variable I/O range (1) (sharedC) :11 Valid:1 PhyMask:36 :16 } {TOP_MEM=0xc001001a;top of memory address (sharedC) :23 TOM:25 :16 } {TOM2=0xc001001d;second top of memory address (sharedC) :23 TOM2:25 :16 } {NB_CFG=0xc001001f;northbridge configuration :9 DisRefUseFreeBuf:1 DisXdsBypass:1 :20 DisCohLdtCfg:1 :4 DisDatMsk:1 :8 DisUsSysMgtReqToNcHt:1 EnableCf8ExtCfg:1 :3 DisOrderRdRsp:1 :3 InitApicIdCpuIdLo:1 :9 } {MCEredirection=0xc0010022;MCE redirection RedirVector:8 RedirVecEn:1 RedirSmiEn:1 :54 } {ProcessorNameString0=0xc0010030;processor name string (0) (sharedNC) CpuNameString:64 } {ProcessorNameString1=0xc0010031;processor name string (1) (sharedNC) CpuNameString:64 } {ProcessorNameString2=0xc0010032;processor name string (2) (sharedNC) CpuNameString:64 } {ProcessorNameString3=0xc0010033;processor name string (3) (sharedNC) CpuNameString:64 } {ProcessorNameString4=0xc0010034;processor name string (4) (sharedNC) CpuNameString:64 } {ProcessorNameString5=0xc0010035;processor name string (5) (sharedNC) CpuNameString:64 } {HTC=0xc001003e;hardware thermal control HtcEn:1 :3 HtcAct:1 HtcActSts:1 PslApicHiEn:1 PslApicLoEn:1 :8 HtcTmpLmt:7 HtcSlewSel:1 HtcHystLmt:4 HtcPstateLimit:3 :33 } {MC0_CTL_MASK=0xc0010044;load store MC control mask TagP:1 TLBP:1 DatP:1 LQP:1 SQP:1 SCBP:1 LineFillPoison:1 SRDE:1 IntErrType2:1 :55 } {MC1_CTL_MASK=0xc0010045;instruction fetch MC control mask (sharedC) :2 IDP:1 IMTP:1 ISTP:1 L2TP:1 L1TP:1 LineFillPoison:1 :1 SRDE:1 :2 PFBP:1 PQP:1 :1 BSRP:1 DEPRP:1 DEUOPQP:1 DEIBP:1 DPDBE:1 DFIFOE:1 L2TLBM:1 L1TLBM:1 IVP:1 :40 } {MC2_CTL_MASK=0xc0010046;bus unit MC control mask (sharedC) L2TagMultiHit:1 VbData:1 WcbData:1 WccData:1 WccAddr:1 PrqData:1 PrqAddr:1 FillData:1 PrbAddr:1 XabAddr:1 L2Prefetch:1 L2TlbData:1 L2Tag:1 RdData:1 L2TlbPoison:1 :49 } {MC3_CTL_MASK=0xc0010047;reserved :64 } {MC4_CTL_MASK=0xc0010048;northbridge MC control mask CECCEn:1 UECCEn:1 CrcErrEn:3 SyncPktEn:3 MstrAbrtEn:1 TgtAbrtEn:1 GartTblWkEn:1 AtomicRMWEn:1 WDTRptEn:1 :1 L3ArrayCorEn:1 L3ArrayUCEn:1 ProtEn:1 HtDataEn:1 DramParEn:1 RtryHtEn:4 CrcErrEn:1 SyncPktEn:1 McaUsPwDatErrEn:1 NbArrayParEn:1 TblWlkDatErrEn:1 :3 McaCpuDatErrEn:1 :32 } {MC5_CTL_MASK=0xc0010049;execution unit MC control mask :1 PICWAK:1 PLDAG:1 PLDEX:1 IDF:1 RETDISP:1 MAP:1 EX0PRF:1 EX1PRF:1 AG0PRF:1 AG1PRF:1 FRF:1 DE:1 :51 } {MC6_CTL_MASK=0xc001004a;floating point unit MC control mask (sharedC) PRF:1 FreeList:1 Sched:1 :1 RetireQ:1 SRF:1 :58 } {SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0) (sharedNC) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1) (sharedNC) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2) (sharedNC) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3) (sharedNC) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control (sharedNC) :1 SmiEn_0:1 :1 SmiEn_1:1 :1 SmiEn_2:1 :1 SmiEn_3:1 :7 IoTrapEn:1 :48 } {IntPendingMessage=0xc0010055;interrupt pending (sharedNC) IOMsgAddr:16 IOMsgData:8 IntrPndMsgDis:1 IntrPndMsg:1 IORd:1 :2 BmStsClrOnHaltEn:1 :34 } {SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle IoPortAddress:16 IoData:8 :1 IoCycleEn:1 IoRd:1 :37 } {MmioConfigBase=0xc0010058;MMIO configuration base address Enable:1 :1 SegBusRange:4;0=1;1=2;2=4;3=8;4=16;5=32;6=64;7=128;8=256 :14 MmiocCfgBaseAddr:28 :16 } {BistResults=0xc0010060;BIST results :64 } {PstateCurrentLimit=0xc0010061;P-state current limit (sharedC) CurPstateLimit:3 :1 PstateMaxVal:3 :57 } {PstateControl=0xc0010062;P-state control PstateCmd:3 :61 } {PstateStatus=0xc0010063;P-state status (sharedC) CurPstate:3 :61 } {Pstate0=0xc0010064;P-state 0 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate1=0xc0010065;P-state 1 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate2=0xc0010066;P-state 2 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate3=0xc0010067;P-state 3 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate4=0xc0010068;P-state 4 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate5=0xc0010069;P-state 5 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate6=0xc001006a;P-state 6 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {Pstate7=0xc001006b;P-state 7 (sharedC) CpuFid:6 CpuDid:3 CpuVid:7 :6 NbPstate:1 :9 IddValue:8 IddDiv:2 :21 PstateEn:1 } {COFVIDcontrol=0xc0010070;COFVID control CpuFid:6 CpuDid:3 CpuVid:7 PstateId:3 :3 NbPstate:1 :1 NbVid:8 :32 } {COFVIDstatus=0xc0010071;COFVID status CurCpuFid:6 CurCpuDid:3 CurCpuVid:7 CurPstate:3 :4 NbPstateDis:1 :1 CurNbVid:7 StartupPstate:3 MaxVid:7 MinVid:7 MaxCpuCof:6 :1 CurPstateLimit:3 MaxNbCof:5 } {CstateAddress=0xc0010073;C-state address CstateAddr:16 :48 } {SMM_BASE=0xc0010111;SMM base address SMM_BASE:32 :32 } {SMMAddr=0xc0010112;SMM TSeg base address :17 TSegBase:31 :16 } {SMMMask=0xc0010113;SMM Tseg mask AValid:1 TValid:1 AClose:1 TClose:1 AMTypeIoWc:1 TMTypeIoWc:1 :2 AMTypeDram:3 :1 TMTypeDram:3 :2 TSegMask:31 :16 } {VM_CR=0xc0010114;virtual machine control dpd:1 InterceptInit:1 DisA20m:1 Lock:1 SvmeDisable:1 :59 } {IGNNE=0xc0010115;IGNNE IGNNE:1 :63 } {VM_HSAVE_PA=0xc0010117;virtual machine host save physical address :12 VM_HSAVE_PA:36 :16 } {SMIstatus=0xc001011a;local SMI status IoTrapSts:4 :4 MceRedirSts:1 :1 IntPendSmiSts:1 :5 SmiSrcLvtLcy:1 SmiSrcLvtExt:1 SmiSrcThrCntDram:1 SmiSrcThrCntHt:1 SmiSrcThrCntL3:1 :1 SmiSrcOnLineSpare:1 :41 } {OSVW_ID_Length=0xc0010140;OS visible work-around OSVW_ID_Length:16 :48 } {OsvwStatus=0xc0010141;OS visible work-around status bits OsvwStatusBits:64 } {PERF_CTL0=0xc0010200;performance event select (0) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } {PERF_CTR0=0xc0010201;performance event counter (0) CTR:48 :16 } {PERF_CTL1=0xc0010202;performance event select (1) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } {PERF_CTR1=0xc0010203;performance event counter (1) CTR:48 :16 } {PERF_CTL2=0xc0010204;performance event select (2) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } {PERF_CTR2=0xc0010205;performance event counter (2) CTR:48 :16 } {PERF_CTL3=0xc0010206;performance event select (3) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } {PERF_CTR3=0xc0010207;performance event counter (3) CTR:48 :16 } {PERF_CTL4=0xc0010208;performance event select (4) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } {PERF_CTR4=0xc0010209;performance event counter (4) CTR:48 :16 } {PERF_CTL5=0xc001020a;performance event select (5) EventSelect:8 UnitMask:8 OsUserMode:2 Edge:1 :1 Int:1 :1 En:1 Inv:1 CntMask:8 EventSelect:4 :4 HostGuestOnly:2 :22 } {PERF_CTR5=0xc001020b;performance event counter (5) CTR:48 :16 } {NB_PERF_CTL0=0xc0010240;northbridge performance event select (0) EventSelect:8 UnitMask:8 :4 Int:1 :1 En:1 :9 EventSelect:4 :28 } {NB_PERF_CTR0=0xc0010241;northbridge performance event counter (0) CTR:48 :16 } {NB_PERF_CTL1=0xc0010242;northbridge performance event select (1) EventSelect:8 UnitMask:8 :4 Int:1 :1 En:1 :9 EventSelect:4 :28 } {NB_PERF_CTR1=0xc0010243;northbridge performance event counter (1) CTR:48 :16 } {NB_PERF_CTL2=0xc0010244;northbridge performance event select (2) EventSelect:8 UnitMask:8 :4 Int:1 :1 En:1 :9 EventSelect:4 :28 } {NB_PERF_CTR2=0xc0010245;northbridge performance event counter (2) CTR:48 :16 } {NB_PERF_CTL3=0xc0010246;northbridge performance event select (3) EventSelect:8 UnitMask:8 :4 Int:1 :1 En:1 :9 EventSelect:4 :28 } {NB_PERF_CTR3=0xc0010247;northbridge performance event counter (3) CTR:48 :16 } {CPUIDPmFeatures=0xc0011003;thermal and power management CPUID features FeaturesEcx:32 :32 } {CPUIDFeatures=0xc0011004;CPUID features FeaturesEdx:32 FeaturesEcx:32 } {CPUIDExtFeatures=0xc0011005;extended CPUID features ExtFeaturesEdx:32 ExtFeaturesEcx:32 } {LS_CFG=0xc0011020;load store configuration :28 DIS_SS:1 :35 } {IC_CFG=0xc0011021;instruction cache configuration (sharedC) :9 DIS_SPEC_TLB_RLD:1 :54 } {DC_CFG=0xc0011022;data cache configuration :4 DIS_SPEC_TLB_RLD:1 :8 DIS_HW_PF:1 :50 } {CU_CFG=0xc0011023;combined unit configuration (sharedC) :10 DcacheAgressivePriority:1 :8 L2FirstLockedWay:4 L2WayLock:1 :40 } {FP_CFG=0xc0011028;floating point configuration (sharedC) :16 DiDtMode:1 :1 DiDtCfg0:5 :2 DiDtCfg2:2 DiDtCfg1:8 :29 } {DE_CFG=0xc0011029;decode configuration (sharedC) :10 ResyncPredSingleDispDis:1 :53 } {CU_CFG2=0xc001102A;combined unit configuration 2 (sharedC) :6 ThrottleNbInterface:2 :2 VicResyncChkEn:1 :25 ThrottleNbInterface:2 :4 ProbeFilterSupEn:1 :7 RdMmExtCfgQwEn:1 :13 } {CU_CFG3=0xc001102B;combined unit configuration 3 (sharedC) :42 PwcDisableWalkerSharing:1 :6 CombineCr0Cd:1 AsidIncrScaleFactor:1 AsidDecrScaleFactor:2 :11 } {EX_CFG=0xc001102C;execution unit configuration :64 } {IbsFetchCtl=0xc0011030;IBS fetch control IbsFetchMaxCnt:16 IbsFetchCnt:16 IbsFetchLat:16 IbsFetchEn:1 IbsFetchVal:1 IbsFetchComp:1 IbsIcMiss:1 IbsPhyAddrValid:1 IbsL1TlbPgSz:2 IbsL1TlbMiss:1 IbsL2TlbMiss:1 IbsRandEn:1 :6 } {IbsFetchLinAd=0xc0011031;IBS fetch linear address IbsFetchLinAd:64 } {IbsFetchPhysAd=0xc0011032;IBS fetch physical address IbsFetchPhysAd:64 } {IbsOpCtl=0xc0011033;IBS execution control IbsOpMaxCnt:16 :1 IbsOpEn:1 IbsOpVal:1 IbsOpCntCtl:1 IbsOpMaxCnt:7 :5 IbsOpCurCnt:27 :5 } {IbsOpRip=0xc0011034;IBS Op logical address IbsOpRip:64 } {IbsOpData=0xc0011035;IBS Op data IbsCompToRetCtr:16 IbsTagToRetCtr:16 IbsOpBrnResync:1 IbsOpMispReturn:1 IbsOpReturn:1 IbsOpBrnTaken:1 IbsOpBrnMisp:1 IbsOpBrnRet:1 IbsRipInvalid:1 :25 } {IbsOpData2=0xc0011036;IBS Op data 2 NbIbsReqSrc:3 :1 NbIbsReqDstNode:1 NbIbsReqCacheHitSt:1 :58 } {IbsOpData3=0xc0011037;IBS Op data 3 IbsLdOp:1 IbsStOp:1 IbsDcL1tlbMiss:1 IbsDcL2tlbMiss:1 IbsDcL1tlbHit2M:1 IbsDcL1tlbHit1G:1 IbsDcL2tlbHit2M:1 IbsDcMiss:1 IbsDcMisAcc:1 IbsDcLdBnkCon:1 :1 IbsDcStToLdFwd:1 IbsDcStToLdCan:1 IbsDcWcMemAcc:1 IbsDcUcMemAcc:1 IbsDcLockedOp:1 IbsDcMabHit:1 IbsDcLinAddrValid:1 IbsDcPhyAddrValid:1 IbsDcL2tlbHit1G:1 :12 IbsDcMissLat:16 :16 } {IbsDcLinAd=0xc0011038;IBS DC linear address IbsDcLinAd:64 } {IbsDcPhysAd=0xc0011039;IBS DC physical address IbsDcPhysAd:64 } {IbsControl=0xc001103a;IBS control LvtOffset:4 :4 LvtOffsetVal:1 :55 } {IbsBranchTargetAddress=0xc001103b;IBS branch target address IbsBrTarget:64 } ### Local Variables: ### ### mode:shell-script ### ### End: ### AMD/identify.c000066400000000000000000000442211167043552300134470ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Copyright (C) 2007 Advanced Micro Devices, Inc. * Andreas Herrmann * * Licensed under the terms of the GNU GPL License version 2. * * AMD-specific information */ #include #include #include #include #include "../x86info.h" #include "AMD.h" #include "revision.h" static char *amd_nameptr; #define add_to_cpuname(x) amd_nameptr += snprintf(amd_nameptr, sizeof(x), "%s", x) static void set_k8_name(struct k8_rev *r, struct cpudata *c) { unsigned int i, id, cont; char s[CPU_NAME_LEN]; const char *p; s[0] = 0; cont = 0; for (i = 0; (r != NULL) && (i < ARRAY_SIZE(k8_names)); i++) { p = NULL; id = 1<nameid & id) p = get_k8_name(id); if (p) { if (cont) strncat(s, "/", CPU_NAME_LEN-1); else cont = 1; strncat(s, p, CPU_NAME_LEN-1); } } if (r) snprintf(c->name, CPU_NAME_LEN, "%s (%s)", s, r->rev); else snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); } static void set_k8_revinfo(int id, struct cpudata *c) { int i; struct k8_rev *r; c->connector = 0; r = NULL; for (i = 0; i < ARRAY_SIZE(k8_revisions); i++) { if (k8_revisions[i].eax == id) { r = &k8_revisions[i]; break; } } set_k8_name(r, c); c->connector = r ? r->socketid : 0; } static void set_fam10h_name(struct fam10h_rev *r, struct cpudata *c) { if (!r) { snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); return; } snprintf(c->name, CPU_NAME_LEN, "Phenom/Athlon/Sempron/Turion (II)/Opteron (%s)", r->rev); } static void set_connector(struct cpudata *c) { unsigned int eax, ebx, ecx, edx; int pkg_id; if (family(c) == 0x11) { c->connector = CONN_SOCKET_S1G2; return; } cpuid(c->number, 0x80000001, &eax, &ebx, &ecx, &edx); pkg_id = (ebx >> 28) & 0xf; if ((family(c) == 0x10) || (family(c) == 0x11) || (family(c) == 0x15)) { switch (pkg_id) { case 0: c->connector = CONN_SOCKET_F_R2; break; case 1: c->connector = CONN_SOCKET_AM3; break; case 2: c->connector = CONN_SOCKET_S1G3; break; case 3: c->connector = CONN_SOCKET_G34; break; case 4: c->connector = CONN_SOCKET_ASB2; break; case 5: c->connector = CONN_SOCKET_C32; break; default: c->connector = 0; } } else if(family(c) == 0x12) { switch (pkg_id) { case 0: c->connector = CONN_SOCKET_FP1; break; case 1: c->connector = CONN_SOCKET_FS1; break; case 2: c->connector = CONN_SOCKET_FM1; break; default: c->connector = 0; } } else if (family(c) == 0x14) { switch (pkg_id) { case 0: c->connector = CONN_SOCKET_FT1; break; default: c->connector = 0; } } } static void set_fam10h_revinfo(int id, struct cpudata *c) { int i; struct fam10h_rev *r = NULL; for (i = 0; i < ARRAY_SIZE(fam10h_revisions); i++) { if (fam10h_revisions[i].eax == id) { r = &fam10h_revisions[i]; break; } } set_fam10h_name(r, c); set_connector(c); } static void set_fam11h_revinfo(int id, struct cpudata *c) { const char *p; p = get_fam11h_revision_name(id); if (p) snprintf(c->name, CPU_NAME_LEN, "AMD Turion X2 Ultra Dual-Core (%s)", p); else snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); set_connector(c); } static void set_fam12h_revinfo(int id, struct cpudata *c) { const char *p; p = get_fam12h_revision_name(id); if(p) snprintf(c->name, CPU_NAME_LEN, "AMD A/E2-Series Processor (%s)", p); else snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); set_connector(c); } static void set_fam14h_revinfo(int id, struct cpudata *c) { const char *p; p = get_fam14h_revision_name(id); if (p) snprintf(c->name, CPU_NAME_LEN, "AMD C/E/G-Series Processor (%s)", p); else snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); set_connector(c); } static void set_fam15h_revinfo(int id, struct cpudata *c) { const char *p; p = get_fam15h_revision_name(id); if (p) snprintf(c->name, CPU_NAME_LEN, "AMD FX Series Processor (%s)", p); else snprintf(c->name, CPU_NAME_LEN, "Unknown CPU"); set_connector(c); } static void do_assoc(unsigned long assoc) { switch (assoc & 0xff) { case 0x0: break; case 0x1: printf("Direct mapped. "); break; case 0xff: printf("Fully associative. "); break; default: printf("%lu-way associative. ", assoc); } } static void do_l2assoc(unsigned long assoc) { unsigned long a; a = 0; switch (assoc) { case 0x0: printf("Disabled. "); break; case 0x1: printf("Direct mapped. "); break; case 0xf: printf("Fully associative. "); break; case 0x2: a = 2; break; case 0x4: a = 4; break; case 0x6: a = 8; break; case 0x8: a = 16; break; case 0xa: a = 32; break; case 0xb: a = 48; break; case 0xc: a = 64; break; case 0xd: a = 96; break; case 0xe: a = 128; break; default: break; } if (a) printf("%lu-way associative. ", a); } void decode_AMD_cacheinfo(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; if ((cpu->eflags_edx & 1<<26) && cpu->maxei >= 0x80000019) { /* 1GB page TLB info */ cpuid(cpu->number, 0x80000019, &eax, &ebx, &ecx, &edx); printf("L1 Data TLB (1G): "); do_l2assoc(eax >> 28); printf("%u entries.\n", (eax >> 16) & 0xfff); printf("L1 Instruction TLB (1G): "); do_l2assoc((eax >> 12) & 0xf); printf("%u entries.\n", eax & 0xfff); } if (cpu->maxei >= 0x80000005) { /* TLB and cache info */ cpuid(cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx); printf("L1 Data TLB (2M/4M): "); do_assoc(eax >> 24); printf("%u entries.\n", (eax >> 16) & 0xff); printf("L1 Instruction TLB (2M/4M): "); do_assoc((eax >> 8) & 0xff); printf("%u entries.\n", eax & 0xff); printf("L1 Data TLB (4K): "); do_assoc(ebx >> 24); printf("%u entries.\n", (ebx >> 16) & 0xff); printf("L1 Instruction TLB (4K): "); do_assoc((ebx >> 8) & 0xff); printf("%u entries.\n", ebx & 0xff); printf("L1 Data cache:\n\t"); printf("Size: %uKb\t", ecx >> 24); do_assoc((ecx >> 16) & 0xff); printf("\n\t"); printf("lines per tag=%u\t", (ecx >> 8) & 0xff); printf("line size=%u bytes.\n", ecx & 0xff); printf("L1 Instruction cache:\n\t"); printf("Size: %uKb\t", edx >> 24); do_assoc((edx >> 16) & 0xff); printf("\n\t"); printf("lines per tag=%u\t", (edx >> 8) & 0xff); printf("line size=%u bytes.\n", edx & 0xff); } if ((cpu->eflags_edx & 1<<26) && cpu->maxei >= 0x80000019) { /* 1GB page TLB info */ cpuid(cpu->number, 0x80000019, &eax, &ebx, &ecx, &edx); printf("L2 Data TLB (1G): "); do_l2assoc(ebx >> 28); printf("%u entries.\n", (ebx >> 16) & 0xfff); printf("L2 Instruction TLB (1G): "); do_l2assoc((ebx >> 12) & 0xf); printf("%u entries.\n", ebx & 0xfff); } if (cpu->maxei >= 0x80000006) { /* K6-III (and later) on-chip L2 cache size */ cpuid(cpu->number, 0x80000006, &eax, &ebx, &ecx, &edx); printf("L2 Data TLB (2M/4M): "); do_l2assoc(eax >> 28); printf("%u entries.\n", (eax >> 16) & 0xfff); printf("L2 Instruction TLB (2M/4M): "); do_l2assoc((eax >> 12) & 0xf); printf("%u entries.\n", eax & 0xfff); printf("L2 Data TLB (4K): "); do_l2assoc(ebx >> 28); printf("%u entries.\n", (ebx >> 16) & 0xfff); printf("L2 Instruction TLB (4K): "); do_l2assoc((ebx >> 12) & 0xf); printf("%u entries.\n", ebx & 0xfff); printf("L2 cache:\n\t"); printf("Size: %uKb\t", ecx >> 16); do_l2assoc((ecx >> 12) & 0x0f); printf("\n\t"); printf("lines per tag=%u\t", (ecx >> 8) & 0x0f); printf("line size=%u bytes.\n", ecx & 0xff); if ((family(cpu) == 0x10) || (family(cpu) == 0x15)) { printf("L3 (shared) cache:\n\t"); if (!(edx >> 18)) printf("none/disabled\n"); else { /* shared L3 cache */ printf("Size: %uKb\t", (edx >> 18) * 512); do_l2assoc((edx >> 12) & 0x0f); printf("\n\t"); printf("lines per tag=%u\t", (edx >> 8) & 0x0f); printf("line size=%u bytes.\n", edx & 0xff); } } } printf("\n"); } /* * Returns size of L2 cache for Duron/Athlon descrimination * Assumes 0x80000006 is valid. */ static int getL2size(int cpunum) { unsigned int eax, ebx, ecx, edx; cpuid(cpunum, 0x80000006, &eax, &ebx, &ecx, &edx); return (ecx >> 16); } static int is_mobile(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; if (cpu->maxei >= 0x80000007) { cpuid(cpu->number, 0x80000007, &eax, &ebx, &ecx, &edx); if ((edx & (1<<1|1<<2)) == 0) return 0; else return 1; } else { return 0; } } static void determine_xp_mp(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; /* There are no mobile MPs. */ if (is_mobile(cpu)) { add_to_cpuname("XP"); return; } cpuid(cpu->number, 0x80000001, &eax, &ebx, &ecx, &edx); if ((edx & (1 << 19)) == 0) { add_to_cpuname("XP"); } else { add_to_cpuname("MP"); } } void Identify_AMD(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; amd_nameptr = cpu->name; if (cpu->cpuid_level < 1) return; cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx); if (cpu->family == 0xf) { cpu->emodel = (eax >> 16) & 0xf; cpu->efamily= (eax >> 20) & 0xff; } else { cpu->emodel = 0; cpu->efamily = 0; } if (family(cpu) >= 0xf) { switch family(cpu) { case 0xf: set_k8_revinfo(eax, cpu); break; case 0x10: set_fam10h_revinfo(eax, cpu); break; case 0x11: set_fam11h_revinfo(eax, cpu); break; case 0x12: set_fam12h_revinfo(eax, cpu); break; case 0x14: set_fam14h_revinfo(eax, cpu); break; case 0x15: set_fam15h_revinfo(eax, cpu); break; default: printf("Unknown CPU family: 0x%x\n", family(cpu)); break; } return; } switch (cpu->family) { case 4: cpu->connector = CONN_SOCKET_3; break; } switch (tuple(cpu) & 0xff0) { case 0x430: add_to_cpuname("Am486DX2-WT"); break; case 0x470: add_to_cpuname("Am486DX2-WB"); break; case 0x480: add_to_cpuname("Am486DX4-WT / Am5x86-WT"); break; case 0x490: add_to_cpuname("Am486DX4-WB / Am5x86-WB"); break; case 0x4a0: add_to_cpuname("Elan SC400"); break; case 0x4e0: add_to_cpuname("Am5x86-WT"); break; case 0x4f0: add_to_cpuname("Am5x86-WB"); break; case 0x500: add_to_cpuname("SSA5 (PR75/PR90/PR100)"); cpu->connector = CONN_SOCKET_5_7; break; case 0x510: add_to_cpuname("K5 (PR120/PR133)"); cpu->connector = CONN_SOCKET_5_7; break; case 0x520: add_to_cpuname("K5 (PR166)"); cpu->connector = CONN_SOCKET_5_7; break; case 0x530: add_to_cpuname("K5 (PR200)"); cpu->connector = CONN_SOCKET_5_7; break; case 0x560: // 166,200,233 MHz add_to_cpuname("K6 (0.30 um)"); cpu->connector = CONN_SOCKET_7; break; case 0x570: // 200,233,266,300 MHz add_to_cpuname("K6 (0.25 um)"); cpu->connector = CONN_SOCKET_7; break; case 0x580: add_to_cpuname("K6-2"); cpu->connector = CONN_SUPER_SOCKET_7; if (cpu->stepping >= 8) add_to_cpuname(" (CXT core)"); break; case 0x590: add_to_cpuname("K6-III"); cpu->connector = CONN_SUPER_SOCKET_7; break; case 0x5c0: add_to_cpuname("K6-2+ (0.18um)"); cpu->connector = CONN_SUPER_SOCKET_7; break; case 0x5d0: add_to_cpuname("K6-3+ (0.18um)"); cpu->connector = CONN_SUPER_SOCKET_7; break; case 0x600: cpu->connector = CONN_SLOT_A; add_to_cpuname("K7 ES"); break; case 0x610: cpu->connector = CONN_SLOT_A; add_to_cpuname("Athlon (0.25um)"); switch (cpu->stepping) { case 1: add_to_cpuname(" [C1]"); break; case 2: add_to_cpuname(" [C2]"); break; } break; case 0x620: cpu->connector = CONN_SLOT_A; add_to_cpuname("Athlon (0.18um)"); switch (cpu->stepping) { case 1: add_to_cpuname(" [A1]"); break; case 2: add_to_cpuname(" [A2]"); break; } break; case 0x630: cpu->connector = CONN_SOCKET_A; add_to_cpuname("Duron (spitfire)"); switch (cpu->stepping) { case 0: add_to_cpuname(" [A0]"); break; case 1: add_to_cpuname(" [A2]"); break; } break; case 0x640: cpu->connector = CONN_SOCKET_A; add_to_cpuname("Athlon (Thunderbird)"); switch (cpu->stepping) { case 0: add_to_cpuname(" [A1]"); break; case 1: add_to_cpuname(" [A2]"); break; case 2: add_to_cpuname(" [A4-A8]"); break; case 3: add_to_cpuname(" [A9]"); break; } break; case 0x660: cpu->connector = CONN_SOCKET_A; if (is_mobile(cpu)) { add_to_cpuname("Mobile Athlon 4"); goto out_660; } if (getL2size(cpu->number) < 256) { add_to_cpuname("Duron (Morgan)"); } else { add_to_cpuname("Athlon "); determine_xp_mp(cpu); /* Palomino * 0.18u L2=256KB * 266MHz FSB * 12%-20% faster than Athlon Thunderbird at same GHz * Power requirement reduced by 20% * Athlon XP 1500+ (Oct 2001) * Athlon XP 1600+ (Oct 2001) * Athlon XP 1700+ (Oct 2001) * Athlon XP 1800+ (Oct 2001) * Athlon XP 1900+ (Nov 2001) * Athlon XP 2000+ (Jan 2002) * Athlon XP 2100+ (Mar 2002) */ add_to_cpuname(" (Palomino)"); } out_660: switch (cpu->stepping) { case 0: add_to_cpuname(" [A0-A1]"); break; case 1: add_to_cpuname(" [A2]"); break; } break; case 0x670: cpu->connector = CONN_SOCKET_A; if (is_mobile(cpu)) add_to_cpuname("Mobile "); add_to_cpuname("Duron (Morgan core)"); switch (cpu->stepping) { case 0: add_to_cpuname(" [A0]"); break; case 1: add_to_cpuname(" [A1]"); break; } break; case 0x680: cpu->connector = CONN_SOCKET_A; if (is_mobile(cpu)) add_to_cpuname("Mobile "); if (getL2size(cpu->number) < 256) { add_to_cpuname("Duron "); } else { add_to_cpuname("Athlon "); determine_xp_mp(cpu); } /* * Thoroughbred * 0.13u L2=256KB * Thoroughbred 'A' = 266FSB * Thoroughbred 'B' = 266FSB * Thoroughbred 'B' = 333FSB * Throughbred B has an extra layer of copper interconnects * to reduce interference. * Athlon XP1600+ (A:June 2002 B:Mar 2003) * Athlon XP1700+ (A:June 2002 B:Dec 2002) * Athlon XP1800+ (A:June 2002 B:Dec 2002) * Athlon XP1900+ (A:June 2002 B:Dec 2002) * Athlon XP2000+ (A:June 2002 B:Aug 2002) * Athlon XP2100+ (A:June 2002 B:Dec 2002) * Athlon XP2200+ (A:June 2002 B:Aug 2002) * Athlon XP2400+ ( B:Aug 2002) * Athlon XP2600+ ( B:Aug 2002 B2: Nov 2002) * Athlon XP2700+ ( B2: Oct 2002) * Athlon XP2800+ ( B2: Oct 2002) */ add_to_cpuname(" (Thoroughbred)"); if (cpu->stepping == 0) add_to_cpuname("[A0]"); if (cpu->stepping == 1) add_to_cpuname("[B0]"); //fab_process = ".13 micron"; //transistors = 37600000; //die_size = "84 sq.mm"; break; case 0x6a0: cpu->connector = CONN_SOCKET_A; if (is_mobile(cpu)) add_to_cpuname("Mobile "); add_to_cpuname("Athlon "); determine_xp_mp(cpu); add_to_cpuname(" (Barton)"); //fab_process = ".13 micron copper"; //transistors = 54300000; //die_size = "101 sq. mm"; /* Barton * L2=512 * 333 FSB & 400 FSB * 10%-15% faster than Athlon XP (old) with same GHz * CPU core size 20% bigger than T-bred. * 333 FSB: * Athlon XP 2500+ (Feb 2003) * Athlon XP 2600+ (June 2003) * Athlon XP 2800+ (Feb 2003) * Athlon XP 3000+ (Feb 2003) * 400 FSB: * Athlon XP 3000+ (Apr 2003) * Athlon XP 3200+ (May 2003) * Athlon XP 3400+ (Q4 2003) * Athlon XP 3600+ (Q1 2004) * Athlon XP 3800+ (Q2 2004) */ break; /* * Applebred * 0.13u L2=64KB * 266FSB * Barton grade processor modules with 64KB cache * * Duron 1.4 (Aug 2003) * Duron 1.6 (Aug 2003) * Duron 1.8 (Q4 2003) */ /* * Socket 940 * Sledgehammer * 0.13u * L2=1mb * 400FSB * SOI (silicon on insulator) * Registered DIMM required * 25% faster than Athlon XP with same GHz * Athlon 64 FX51 (Sep 2003) * Athlon 64 FX53 (Nov 2003) * Athlon 64 FX55 (Q4 2003) */ /* * Socket 754 * Clawhammer * 0.13 * L2=1mb * 400FSB * No dual channel memory access * Registered DIMM not required * Athlon 64 3000+ (Oct 2003) * Athlon 64 3200+ (Sep 2003) * Athlon 64 3400+ (Oct 2003) * Athlon 64 3700+ (Q4 2003) */ /* * Socket 939 * San Diego * 90nm l2=1mb * 400FSB * Dual channel memory access * Registered DIMM not required * Athlon64 FX-57 (Q1 2004) */ /* * Socket 754 * Victoria * 90nm L2=1MB * 400FSB * No dual channel memory access * Registered DIMM not required * Athlon64 3x00+ (Q3 2004) */ default: add_to_cpuname("Unknown CPU"); break; } } static void show_patch_level(struct cpudata *cpu) { unsigned long long val = 0; if (!user_is_root) return; if (read_msr(cpu->number, 0x8b, &val) == 1) { if (val>0) printf("Microcode patch level: 0x%llx\n", val); printf("\n"); } } void display_AMD_info(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; if (show_msr) { if (cpu->family == 5) dump_k6_MSR(cpu); if (cpu->family == 6) dump_athlon_MSR(cpu); } if (show_machine_check) decode_athlon_machine_check(cpu->number); if (show_microcode && family(cpu) >= 0xf) show_patch_level(cpu); if (show_pm) decode_powernow(cpu); if (show_bugs) show_amd_bugs(cpu); if (cpu->cpuid_level >= 0x05) { cpuid (cpu->number, 0x05, &eax, &ebx, &ecx, NULL); printf("Monitor/Mwait: min/max line size %d/%d%s%s\n", (int) (eax & 0xffff), (int) (ebx & 0xffff), (ecx & 0x2) ? ", ecx bit 0 support" : "", (ecx & 0x1) ? ", enumeration extension" : ""); } if (cpu->maxei >= 0x8000000a) { cpuid (cpu->number, 0x8000000a, &eax, &ebx, NULL, &edx); printf("SVM: revision %d, %d ASIDs", (int) (eax & 0xff), (int) ebx); if (edx & 1) printf(", np"); if (edx & 2) printf(", lbrVirt"); if (edx & 4) printf(", SVMLock"); if (edx & 8) printf(", NRIPSave"); if (edx & 0x10) printf(", TscRateMsr"); if (edx & 0x20) printf(", VmcbClean"); if (edx & 0x40) printf(", FlushByAsid"); if (edx & 0x80) printf(", DecodeAssists"); if (edx & 0x400) printf(", PauseFilter"); if (edx & 0x1000) printf(", PauseFilterThreshold"); printf("\n"); } /* AMD Multicore characterisation */ if (cpu->maxei >= 0x80000008) { int n, p; cpuid (cpu->number, 0x80000008, &eax, NULL, &ecx, NULL); printf("Address Size: %d bits virtual, %d bits physical\n", (int) (eax >> 8) & 0xff, (int) eax & 0xff); p = (ecx >> 12) & 0xf; n = (ecx & 0xff) + 1; if (p) p = 1 << p; else p = n; if (p > 1) printf("The physical package has %d of %d " "possible cores implemented.\n", n, p); } } AMD/k8.regs000066400000000000000000000377141167043552300127050ustar00rootroot00000000000000# Author: Andreas Herrmann # # Copyright (C) 2008, 2009 Advanced Micro Devices, Inc. # This file contains information from: # - "26094 Rev 3.30 - February 2006, BIOS and Kernel Developer's Guide # for AMD Athlon 64 and AMD Opteron Processors" # # - "32559 Rev 3.08 - July 2007, BIOS and Kernel Developer's Guide # for AMD NPT Family 0Fh Processors" # # - "24593 Rev 3.14 - September 2007, AMD64 Technology - AMD64 # Architecture Programmer's Manual Volume 2: System Programming" # See scripts/createheader.py for the general format of this register # definitions. # Todos: # - distinguish between NPT and pre-NPT K8 registers {TSC=0x0010;time-stamp counter PCLKS:64 } {APIC_BASE=0x001b;APIC base address :8 BSP:1 :2 ApicEn:1 ApicBase:28 :24 } {EBL_CR_POWERON=0x002a;APIC cluster ID :16 ApicClusterID:2 :46 } {PATCH_LEVEL=0x008b;microcode patch level PATCH_LEVEL:32 :32 } {MTRRcap=0x00fe;MTRR capabilities MtrrCapVCnt:8 MtrrCapFix:1 :1 MtrrCapWc:1 :53 } {SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector SYSENTER_CS:16 :48 } {SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer SYSENTER_ESP:32 :32 } {SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer SYSENTER_EIP:32 :32 } {MCG_CAP=0x0179;global MC capabilities Count:8 MCG_CTL_P:1 :55 } {MCG_STATUS=0x017a;global MC status RIPV:1 EIPV:1 MCIP:1 :61 } {MCG_CTL=0x017b;global MC control DCE:1 ICE:1 BUE:1 LSE:1 NBE:1 :59 } {DebugCtl=0x01d9;debug control LBR:1 BTF:1 PB0:1 PB1:1 PB2:1 PB3:1 :58 } {LastBranchFromIP=0x01db;last branch from IP LastBranchFromIP:64 } {LastBranchToIP=0x01dc;last branch to IP LastBranchToIP:64 } {LastExceptionFromIP=0x01dd;last exception from IP LastExceptionFromIP:64 } {LastExceptionToIP=0x01de;last exception to IP LastExceptionToIP:64 } {MTRRphysBase0=0x0200;base of variable-size MTRR (0) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask0=0x0201;mask of variable-size MTRR (0) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase1=0x0202;base of variable-size MTRR (1) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask1=0x0203;mask of variable-size MTRR (1) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase2=0x0204;base of variable-size MTRR (2) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask2=0x0205;mask of variable-size MTRR (2) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase3=0x0206;base of variable-size MTRR (3) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask3=0x0207;mask of variable-size MTRR (3) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase4=0x0208;base of variable-size MTRR (4) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask4=0x0209;mask of variable-size MTRR (4) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase5=0x020a;base of variable-size MTRR (5) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask5=0x020b;mask of variable-size MTRR (5) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase6=0x020c;base of variable-size MTRR (6) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask6=0x020d;mask of variable-size MTRR (6) :11 Valid:1 PhysMask:28 :24 } {MTRRphysBase7=0x020e;base of variable-size MTRR (7) Type:8 :4 PhyBase:28 :24 } {MTRRphysMask7=0x020f;mask of variable-size MTRR (7) :11 Valid:1 PhysMask:28 :24 } {MTRRfix64K_00000=0x0250;fixed range MTRR 0xxxxType:8 1xxxxType:8 2xxxxType:8 3xxxxType:8 4xxxxType:8 5xxxxType:8 6xxxxType:8 7xxxxType:8 } {MTRRfix16K_80000=0x0258;fixed range MTRR 80xxxType:8 84xxxType:8 88xxxType:8 8CxxxType:8 90xxxType:8 94xxxType:8 98xxxType:8 9CxxxType:8 } {MTRRfix16K_A0000=0x0259;fixed range MTRR A0xxxType:8 A4xxxType:8 A8xxxType:8 ACxxxType:8 B0xxxType:8 B4xxxType:8 B8xxxType:8 BCxxxType:8 } {MTRRfix4K_C0000=0x0268;fixed range MTRR C0xxxType:8 C1xxxType:8 C2xxxType:8 C3xxxType:8 C4xxxType:8 C5xxxType:8 C6xxxType:8 C7xxxType:8 } {MTRRfix4K_C8000=0x0269;fixed range MTRR C8xxxType:8 C9xxxType:8 CAxxxType:8 CBxxxType:8 CCxxxType:8 CDxxxType:8 CExxxType:8 CFxxxType:8 } {MTRRfix4K_D0000=0x026a;fixed range MTRR D0xxxType:8 D1xxxType:8 D2xxxType:8 D3xxxType:8 D4xxxType:8 D5xxxType:8 D6xxxType:8 D7xxxType:8 } {MTRRfix4K_D8000=0x026b;fixed range MTRR D8xxxType:8 D9xxxType:8 DAxxxType:8 DBxxxType:8 DCxxxType:8 DDxxxType:8 DExxxType:8 DFxxxType:8 } {MTRRfix4K_E0000=0x026c;fixed range MTRR E0xxxType:8 E1xxxType:8 E2xxxType:8 E3xxxType:8 E4xxxType:8 E5xxxType:8 E6xxxType:8 E7xxxType:8 } {MTRRfix4K_E8000=0x026d;fixed range MTRR E8xxxType:8 E9xxxType:8 EAxxxType:8 EBxxxType:8 ECxxxType:8 EDxxxType:8 EExxxType:8 EFxxxType:8 } {MTRRfix4K_F0000=0x026e;fixed range MTRR F0xxxType:8 F1xxxType:8 F2xxxType:8 F3xxxType:8 F4xxxType:8 F5xxxType:8 F6xxxType:8 F7xxxType:8 } {MTRRfix4K_F8000=0x026f;fixed range MTRR F8xxxType:8 F9xxxType:8 FAxxxType:8 FBxxxType:8 FCxxxType:8 FDxxxType:8 FExxxType:8 FFxxxType:8 } {PAT=0x0277;page attribute table PA0:3 :5 PA1:3 :5 PA2:3 :5 PA3:3 :5 PA4:3 :5 PA5:3 :5 PA6:3 :5 PA7:3 :5 } {MTRRdefType=0x02ff;MTRR default memory type MtrrDefMemType:8 :2 MtrrDefTypeFixEn:1 MtrrDefTypeEn:1 :52 } {MC0_CTL=0x0400;data cache MC control ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC0_STATUS=0x0401;data cache MC status ERR_CODE:16 EXT_ERR_CODE:4 :20 SCRUB:1 :4 UECC:1 CECC:1 SYND:8 :2 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } {MC0_ADDR=0x0402;data cache MC address ADDR:48 :16 } {MC0_MISC=0x0403;data cache MC miscellaneous :64 } # K8 NPT only {MC1_CTL=0x0404;instruction cache MC control ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC1_STATUS=0x0405;instruction cache MC status ERR_CODE:16 EXT_ERR_CODE:4 :20 SCRUB:1 :4 UECC:1 CECC:1 SYND:8 :2 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } {MC1_ADDR=0x0406;instruction cache MC address ADDR:48 :16 } {MC1_MISC=0x0407;instruction cache MC miscellaneous :64 } # K8 NPT only {MC2_CTL=0x0408;bus unit MC control S_RDE_HP:1 S_RDE_TLB:1 S_RDE_ALL:1 S_ECC1_TLB:1 S_ECC1_HP:1 S_ECCM_TLB:1 S_ECCM_HP:1 L2T_PAR_ICDC:1 L2T_PAR_TLB:1 L2_PAR_SNP:1 L2_PAR_CPB:1 L2_PAR_SCR:1 L2D_ECC1_TLB:1 L2D_ECC1_SNP:1 L2D_ECC1_CPB:1 L2D_ECCM_TLB:1 L2D_ECCM_SNP:1 L2D_ECCM_CPB:1 L2T_ECC1_SCR:1 L2T_ECCM_SCR:1 :44 } {MC2_STATUS=0x0409;bus unit MC status ERR_CODE:16 EXT_ERR_CODE:4 :20 SCRUB:1 :4 UECC:1 CECC:1 SYND:8 :2 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } {MC2_ADDR=0x040a;bus unit MC address ADDR:48 :16 } {MC2_MISC=0x040b;bus unit MC miscellaneous :64 } # K8 NPT only {MC3_CTL=0x040c;load store unit MC control S_RDE_L:1 S_RDE_S:1 :62 } {MC3_STATUS=0x040d;load store unit MC status ERR_CODE:16 EXT_ERR_CODE:4 :20 SCRUB:1 :4 UECC:1 CECC:1 SYND:8 :2 PCC:1 ADDRV:1 MISCV:1 EN:1 UC:1 OVER:1 VAL:1 } {MC3_ADDR=0x040e;load store unit MC address ADDR:48 :16 } {MC3_MISC=0x040f;load store unit MC miscellaneous :64 } # K8 NPT only {MC4_CTL=0x0410;northbridge MC control CorrEccEn:1 UnCorrEccEn:1 CrcErr0En:1 CrcErr1En:1 CrcErr2En:1 SyncPkt0En:1 SyncPkt1En:1 SyncPkt2En:1 MstrAbrtEn:1 TgtAbrtEn:1 GartTblWkEn:1 AtomicRMWEn:1 WchDogTmrEn:1 :5 DramParEn:1;;K8 NPT :45 } {MC4_STATUS=0x0411;northbridge MC status ErrorCode:16 ErrorCodeExt:4 :4 Syndrome:8 ErrCpu0:1 ErrCpu1:1 :2 LDTLink:3 :1 ErrScrub:1 DramChannel:1;;K8 NPT :3 UnCorrECC:1 CorrECC:1 ECC_Synd:8 :2 PCC:1 ErrAddrVal:1 ErrMiscVal:1 ErrEn:1 ErrUnCorr:1 ErrOver:1 ErrValid:1 } {MC4_ADDR=0x0412;northbridge MC address :3 ADDR:37 :24 } {MC4_MISC=0x0413;DRAM errors threshold :32 ErrCount:12 :4 Ovrflw:1 IntType:2 CntEn:1 LvtOff:4 :5 Locked:1 CtrP:1 Val:1 } # K8 NPT only {EFER=0xc0000080;extended feature enable SYSCALL:1 :7 LME:1 :1 LMA:1 NXE:1 SVME:1;;K8 NPT LMSLE:1 FFXSR:1 :49 } {STAR=0xc0000081;SYSCALL target address Target:32 SysCallSel:16 SysRetSel:16 } {LSTAR=0xc0000082;long mode SYSCALL target address LSTAR:64 } {CSTAR=0xc0000083;compat mode SYSCALL target address CSTAR:64 } {SF_MASK=0xc0000084;SYSCALL flag mask MASK:32 :32 } {FSBase=0xc0000100;FS base FS_BASE:64 } {GSBase=0xc0000101;GS base GS_BASE:64 } {KernelGSbase=0xc0000102;kernel GS base KernelGSBase:64 } {PerfEvtSel0=0xc0010000;performance event-select (0) EVENT_MASK:8 UNIT_MASK:8 USR:1 OS:1 E:1 PC:1 INT:1 :1 EN:1 INV:1 CNT_MASK:8 :32 } {PerfEvtSel1=0xc0010001;performance event-select (1) EVENT_MASK:8 UNIT_MASK:8 USR:1 OS:1 E:1 PC:1 INT:1 :1 EN:1 INV:1 CNT_MASK:8 :32 } {PerfEvtSel2=0xc0010002;performance event-select (2) EVENT_MASK:8 UNIT_MASK:8 USR:1 OS:1 E:1 PC:1 INT:1 :1 EN:1 INV:1 CNT_MASK:8 :32 } {PerfEvtSel3=0xc0010003;performance event-select (3) EVENT_MASK:8 UNIT_MASK:8 USR:1 OS:1 E:1 PC:1 INT:1 :1 EN:1 INV:1 CNT_MASK:8 :32 } {PerfCtr0=0xc0010004;performance counter (0) CTR:48 :16 } {PerfCtr1=0xc0010005;performance counter (1) CTR:48 :16 } {PerfCtr2=0xc0010006;performance counter (2) CTR:48 :16 } {PerfCtr3=0xc0010007;performance counter (3) CTR:48 :16 } {SYSCFG=0xc0010010;system configuration SysAckLimit:5 SysVicLimit:3 SetDirtyEnE:1 SetDirtyEnS:1 SetDirtyEnO:1 ClVicBlkEn:1;;RevB and earlier :4 ChxToDirtyDis:1 SysUcLockEn:1 MtrrFixDramEn:1 MtrrFixDramModeEn:1 MtrrVarDramEn:1 MtrrTom2En:1 Tom2ForceMemTypeWB:1;;K8 NPT :41 } {HWCR=0xc0010015;hardware configuration SMMLOCK:1 SLOWFENCE:1 :1 TLBCACHEDIS:1 INVD_WBINVD:1 :1 FFDIS:1 DISLOCK:1 IGNNE_EM:1 :3 HLTXSPCYCEN:1 SMISPCYCDIS:1 RSMSPCYCDIS:1 SSEDIS:1 :1 WRAP32DIS:1 MCi_STATUS_WREN:1 :5 START_FID:6 :34 } {IORRBase0=0xc0010016;base of variable I/O range (0) :3 WrDram:1 RdDram:1 :7 Base:28 :24 } {IORRMask0=0xc0010017;mask of variable I/O range (0) :11 V:1 Mask:28 :24 } {IORRBase1=0xc0010018;base of variable I/O range (1) :3 WrDram:1 RdDram:1 :7 Base:28 :24 } {IORRMask1=0xc0010019;mask of variable I/O range (1) :11 V:1 Mask:28 :24 } {TOP_MEM=0xc001001a;top of memory address :23 TOM:17 :24 } {TOP_MEM2=0xc001001d;second top of memory address :23 TOM2:17 :24 } {MANID=0xc001001e;manufacturing identification number MinorRev:4 MajorRev:4 ReticleSite:2 :54 } {NB_CFG=0xc001001f;northbridge configuration :9 En/DisRefUseFreeBuf:1;;=RevD disable :21 DisCohLdtCfg:1 :4 DisDatMsk:1 :6 DisThmlPfMonSmiinterupts:1 :1 DisUsSysMgtRqToNLdt:1 :8 InitApicIdCpuIdLo:1 :9 } {ProcessorNameString0=0xc0010030;processor name string (0) CpuNameString:64 } {ProcessorNameString1=0xc0010031;processor name string (1) CpuNameString:64 } {ProcessorNameString2=0xc0010032;processor name string (2) CpuNameString:64 } {ProcessorNameString3=0xc0010033;processor name string (3) CpuNameString:64 } {ProcessorNameString4=0xc0010034;processor name string (4) CpuNameString:64 } {ProcessorNameString5=0xc0010035;processor name string (5) CpuNameString:64 } {HTC=0xc001003e;hardware thermal control HtcEn:1 HtcSbcEn:1 :2 HtcAct:1 HtcActSts:1 :58 } # K8 NPT only {ThermalControl=0xc001003f;thermal control StcSbcTmpHiEn:1 StcSbcTmpLoEn:1 StcApcTmpHiEn:1 StcApcTmpLoEn:1 StcHtcEn:1 :1 StcTmpHiSts:1 StcTmpLoSts:1 :8 StcTmpLmt:5 :3 StcHystLmt:4 :36 } # K8 NPT only {FIDVID_CTL=0xc0010041;FIDVID control NewFID:6 :2 NewVID:6 :2 IniFidVid:1 :15 StpGntTOCnt:20 :12 } # {FIDVID_STATUS=0xc0010042;FIDVID status # CurFID:6 # :2 # StartFID:6 # :2 # MaxFID:6 # :2 # MaxRampVID:5 # :2 # FidVidPending:1 # CurVID:5 # :3 # StartVID:5 # :3 # MaxVID:5 # :3 # MinVID:5 # :3 # } # K8 non-NPT {FIDVID_STATUS=0xc0010042;FIDVID status CurFID:6 :2 StartFID:6 :2 MaxFID:6 :2 MaxRampVID:6 :1 FidVidPending:1 CurVID:6 :2 StartVID:6 :2 MaxVID:6 :2 PstateStep:1 AltVidOffset:3 :1 IntPstateSup:1 :2 } # K8 NPT {MC0_CTL_MASK=0xc0010044;data cache MC control mask ECCI:1 ECCM:1 DECC:1 DMTP:1 DSTP:1 L1TP:1 L2TP:1 :57 } {MC1_CTL_MASK=0xc0010045;instruction cache MC control mask ECCI:1 ECCM:1 IDP:1 IMTP:1 ISTP:1 L1TP:1 L2TP:1 :2 RDDE:1 :54 } {MC2_CTL_MASK=0xc0010046;bus unit MC control mask S_RDE_HP:1 S_RDE_TLB:1 S_RDE_ALL:1 S_ECC1_TLB:1 S_ECC1_HP:1 S_ECCM_TLB:1 S_ECCM_HP:1 L2T_PAR_ICDC:1 L2T_PAR_TLB:1 L2_PAR_SNP:1 L2_PAR_CPB:1 L2_PAR_SCR:1 L2D_ECC1_TLB:1 L2D_ECC1_SNP:1 L2D_ECC1_CPB:1 L2D_ECCM_TLB:1 L2D_ECCM_SNP:1 L2D_ECCM_CPB:1 L2T_ECC1_SCR:1 L2T_ECCM_SCR:1 :44 } {MC3_CTL_MASK=0xc0010047;load store unit MC control mask S_RDE_L:1 S_RDE_S:1 :62 } {MC4_CTL_MASK=0xc0010048;northbridge MC control mask CorrEccEn:1 UnCorrEccEn:1 CrcErr0En:1 CrcErr1En:1 CrcErr2En:1 SyncPkt0En:1 SyncPkt1En:1 SyncPkt2En:1 MstrAbrtEn:1 TgtAbrtEn:1 GartTblWkEn:1 AtomicRMWEn:1 WchDogTmrEn:1 :5 DramParEn:1 :45 } {IOTRAP_ADDR0=0xc0010050;IO trap addr (0) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {IOTRAP_ADDR1=0xc0010051;IO trap addr (1) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {IOTRAP_ADDR2=0xc0010052;IO trap addr (2) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {IOTRAP_ADDR3=0xc0010053;IO trap addr (3) SmiAddr:32 SmiMask:24 :5 ConfigSmi:1 SmiOnWrEn:1 SmiOnRdEn:1 } {IOTRAP_CTL=0xc0010054;IO trap control SmiSts_0:1 SmiEn_0:1 SmiSts_1:1 SmiEn_1:1 SmiSts_2:1 SmiEn_2:1 SmiSts_3:1 SmiEn_3:1 :5 IoTrapCtlRsmSpcEn:1 IoTrapCtlSmiSpcEn:1 IoTrapEn:1 :48 } {IntPendingMessage=0xc0010055;interrupt pending message IOMsgAddr:16 IOMsgData:8 IntrPndMsgDis:1 IntrPndMsg:1 IORd:1 SmiOnCmpHalt:1;;K8 NPT C1eOnCmpHalt:1;;K8 NPT :35 } {SMM_BASE=0xc0010111;SMM base address SMM_BASE:32 :32 } {SMM_ADDR=0xc0010112;SMM TSeg base address :17 ADDR:23 :24 } {SMM_MASK=0xc0010113;SMM TSeg mask AValid:1 TValid:1 AClose:1 TClose:1 AMTypeIoWc:1 TMTypeIoWc:1 :2 AMTypeDram:3 :1 TMTypeDram:3 :2 MASK:23 :24 } {VM_CR=0xc0010114;security related controls dpd:1 r_init:1 dis_a20m:1 LOCK:1 SVME_DISABLE:1 :59 } # K8 NPT only {VM_HSAVE_PA=0xc0010117;VM host save physical address VM_HSAVE_PA:64 } # K8 NPT only ### Local Variables: ### ### mode:shell-script ### ### End: ### AMD/machine_check.c000066400000000000000000000103171167043552300143740ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Dump machine check registers. */ #include #include #include #include "../x86info.h" #include "AMD.h" #define MCG_CAP 0x0179 #define MCG_STATUS 0x17a #define MCG_CTL 0x17b #define MC_CTL 0x0400 #define MC_STATUS 0x0401 #define MC_ADDR 0x402 #define MC_MISC 0x403 void decode_athlon_machine_check(int cpunum) { unsigned long long val, val2; unsigned int banks, i, ctlp = 0; if (!user_is_root) return; if (read_msr(cpunum, MCG_CAP, &val) != 1) return; ctlp = val & (1<<8); if (ctlp == 0) printf("Erk, MCG_CTL not present! :%016llx:\n", val); banks = val & 0xf; printf("Number of reporting banks : %d\n\n", banks); if (read_msr(cpunum, MCG_STATUS, &val) == 1) { if (val != 0) { printf(" 31 23 15 7 \n"); printf("MCG_STATUS: "); dumpmsr_bin (cpunum, MCG_STATUS, 32); } } if ( ctlp && read_msr(cpunum, MCG_CTL, &val) == 1) { printf("MCG_CTL:\n"); printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis"); if ((val & (1<<0)) == 1) { if (read_msr(cpunum, MC_CTL, &val2) == 1) { printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis"); printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis"); printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis"); printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis"); printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis"); printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis"); } } printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis"); if (((val & (1<<1)) == 2) && (banks>1)) { if (read_msr(cpunum, MC_CTL+4, &val2) == 1) { printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis"); printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis"); printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis"); printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis"); printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis"); printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis"); printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis"); printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis"); printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis"); } } printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis"); if ((val & (1<<2)) == 4 && (banks>2)) { if (read_msr(cpunum, MC_CTL+8, &val2) == 1) { printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis"); printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis"); printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis"); printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis"); printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis"); printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis"); } } printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis"); if ((val & (1<<3)) == 8 && (banks>3)) { if (read_msr(cpunum, MC_CTL+12, &val2) == 1) { printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis"); } } } printf("\n"); printf(" 31 23 15 7 \n"); for (i=0; i #include #include #include #include "../x86info.h" #include "AMD.h" #include "powernow.h" double mobile_vid_table[32] = { 2.000, 1.950, 1.900, 1.850, 1.800, 1.750, 1.700, 1.650, 1.600, 1.550, 1.500, 1.450, 1.400, 1.350, 1.300, 0.000, 1.275, 1.250, 1.225, 1.200, 1.175, 1.150, 1.125, 1.100, 1.075, 1.050, 1.024, 1.000, 0.975, 0.950, 0.925, 0.000, }; double fid_codes[32] = { 11.0, 11.5, 12.0, 12.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10, 10.5, 3.0, 19.0, 4.0, 20.0, 13.0, 13.5, 14.0, 21.0, 15.0, 22.5, 16.0, 16.5, 17.0, 18.0, -1, -1, }; static void decode_fidvid(struct cpudata *cpu) { union msr_vidctl vidctl; union msr_fidvidstatus fidvidstatus; dumpmsr(cpu->number, MSR_FID_VID_CTL, 64); dumpmsr(cpu->number, MSR_FID_VID_STATUS, 64); printf("\n"); if (read_msr(cpu->number, MSR_FID_VID_CTL, &vidctl.val) != 1) { printf("Something went wrong reading MSR_FID_VID_CTL\n"); return; } printf("FID changes %s happen\n", vidctl.bits.FIDC ? "will" : "won't"); printf("VID changes %s happen\n", vidctl.bits.VIDC ? "will" : "won't"); if (vidctl.bits.VIDC) printf("Current VID multiplier code: %0.3f\n", mobile_vid_table[vidctl.bits.VID]); if (vidctl.bits.FIDC) printf("Current FSB multiplier code: %.1f\n", fid_codes[vidctl.bits.FID]); /* Now dump the status */ if (read_msr(cpu->number, MSR_FID_VID_STATUS, &fidvidstatus.val) != 1) { printf("Something went wrong reading MSR_FID_VID_STATUS\n"); return; } printf("Voltage ID codes: Maximum=%0.3fV Startup=%0.3fV Currently=%0.3fV\n", mobile_vid_table[fidvidstatus.bits.MVID], mobile_vid_table[fidvidstatus.bits.SVID], mobile_vid_table[fidvidstatus.bits.CVID]); printf("Frequency ID codes: Maximum=%.1fx Startup=%.1fx Currently=%.1fx\n", fid_codes[fidvidstatus.bits.MFID], fid_codes[fidvidstatus.bits.SFID], fid_codes[fidvidstatus.bits.CFID]); // printf("Voltage ID codes: Maximum=0x%x Startup=0x%x Currently=0x%x\n", // fidvidstatus.MVID, fidvidstatus.SVID, fidvidstatus.CVID); // printf("Frequency ID codes: Maximum=0x%x Startup=0x%x Currently=0x%x\n", // fidvidstatus.MFID, fidvidstatus.SFID, fidvidstatus.CFID); if (show_bios) { printf("Decoding BIOS PST tables (maxfid=%x, startvid=%x)\n", fidvidstatus.bits.MFID, fidvidstatus.bits.SVID); dump_PSB(cpu, fidvidstatus.bits.MFID, fidvidstatus.bits.SVID); } } static double k8_vid_table[32] = { 1.550, 1.525, 1.500, 1.475, 1.450, 1.425, 1.400, 1.375, 1.350, 1.325, 1.300, 1.275, 1.250, 1.225, 1.200, 1.175, 1.150, 1.125, 1.100, 1.075, 1.050, 1.025, 1.000, 0.975, 0.950, 0.925, 0.900, 0.875, 0.850, 0.825, 0.800, 0.000, }; static int k8_fid_codes[43] = { 4, -1, 5, -1, 6, -1, 7, -1, 8, -1, 9, -1, 10, -1, 11, -1, 12, -1, 13, -1, 14, -1, 15, -1, 16, -1, 17, -1, 18, -1, 19, -1, 20, -1, 21, -1, 22, -1, 23, -1, 24, -1, -25 }; static void k8_decode_fidvid(struct cpudata *cpu) { union k8_msr_fidvidstatus fidvidstatus; dumpmsr(cpu->number, MSR_FID_VID_CTL, 64); dumpmsr(cpu->number, MSR_FID_VID_STATUS, 64); printf("\n"); if (read_msr(cpu->number, MSR_FID_VID_STATUS, &fidvidstatus.val) != 1) { printf("Something went wrong reading MSR_FID_VID_STATUS\n"); return; } printf("Voltage ID codes: Maximum=%0.3fV Startup=%0.3fV Currently=%0.3fV\n", k8_vid_table[fidvidstatus.bits.maxvid], k8_vid_table[fidvidstatus.bits.svid], k8_vid_table[fidvidstatus.bits.cvid]); printf("Frequency ID codes: Maximum=%dx Startup=%dx Currently=%dx\n", k8_fid_codes[fidvidstatus.bits.mfid], k8_fid_codes[fidvidstatus.bits.sfid], k8_fid_codes[fidvidstatus.bits.cfid]); } static int get_did(int family, union msr_pstate pstate) { int t; if (family == 0x14) t = ((pstate.val >> 2) & 0x1f) + 4 + ((pstate.val & 0x3)); else if (family == 0x12) t = pstate.val & 0xf; else t = pstate.bits.did; return t; } static int get_main_pll_fid(void) { struct pci_filter filter_nb_misc = { -1, -1, -1, -1, 0x1022, 0x1703}; struct pci_access *pacc; struct pci_dev *z = NULL; u8 val; pacc = pci_alloc(); pci_init(pacc); pci_scan_bus(pacc); for (z=pacc->devices; z; z=z->next) { if (pci_filter_match(&filter_nb_misc, z)) break; } val = 0; if (z) { val = pci_read_byte(z, 0xd4); val &= 0x3f; } pci_cleanup(pacc); return val; } static int get_cof(int family, union msr_pstate pstate) { int t; int fid, did; did = get_did(family, pstate); t = 0x10; fid = pstate.bits.fid; if ((family == 0x10) || (family == 0x15)) goto out; if (family == 0x11) { t = 0x8; goto out; } if (family == 0x12) { int f, d; t = 0x10; fid = (pstate.val >> 4) & 0x1f; switch (did) { case 0: goto out; case 2: did = 1; goto out; case 4: did = 2; goto out; case 6: did = 3; goto out; case 8: did = 4; goto out; case 1: f = 2; d = 3; break; case 3: f = 1; d = 3; break; case 5: f = 1; d = 6; break; case 7: f = 1; d = 12; break; default: printf("Invalid divisor ID: %d\n", did); return 0; } return (100 * (fid + t) * f / d); } if (family == 0x14) { fid = get_main_pll_fid(); //from PCI return (((fid + 0x10) *100) * 4 / did); } out: return ((100 * (fid + t)) >> did); } static int get_num_boost_states(void) { struct pci_filter filter_nb_link = { -1, -1, -1, -1, 0x1022, 0}; int dev_ids[3] = {0x1204, 0x1604, 0x1704}; struct pci_access *pacc; struct pci_dev *z = NULL; u8 val; int i; pacc = pci_alloc(); pci_init(pacc); pci_scan_bus(pacc); for (i=0; idevices; z; z=z->next) { if (pci_filter_match(&filter_nb_link, z)) goto match; } } match: val = 0; if (z) { val = pci_read_byte(z, 0x15c); if (val & 3) printf("Boosting enabled\n"); else printf("Boosting disabled\n"); val = (val >> 2) & 7; printf("Number of boost states: %d\n", val); } pci_cleanup(pacc); return val; } static void decode_pstates(struct cpudata *cpu, int has_cpb) { int i, psmax, pscur, fam; union msr_pstate pstate; unsigned long long val; int boost_states = 0; fam = family(cpu); if (fam < 0x10) return; if (has_cpb) boost_states = get_num_boost_states(); if (read_msr(cpu->number, MSR_PSTATE_LIMIT, &val) != 1) { printf("Something went wrong reading MSR_PSTATE_CUR_LIMIT\n"); return; } psmax = (val >> 4) & 0x7; if (read_msr(cpu->number, MSR_PSTATE_STATUS, &val) != 1) { printf("Something went wrong reading MSR_PSTATE_STATUS\n"); return; } pscur = val & 0x7; pscur += boost_states; psmax += boost_states; for (i=0; i<=psmax; i++) { if (read_msr(cpu->number, MSR_PSTATE + i, &pstate.val) != 1) { printf("Something went wrong reading MSR_PSTATE_%d\n", i); return; } if (i < boost_states) { printf("Pstate-Pb%d: %dMHz (boost state)\n", i, get_cof(fam, pstate)); } else if (pstate.bits.en) { /* show information only if pstate is enabled */ printf("Pstate-P%d: %dMHz%s\n", i - boost_states, get_cof(fam, pstate), (i == pscur) ? " (current)" : ""); } } printf("\n"); } void decode_powernow(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; int can_scale_vid=0, can_scale_fid=0; int has_cpb = 0; if (cpu->maxei < 0x80000007) return; cpuid(cpu->number, 0x80000007, &eax, &ebx, &ecx, &edx); printf("PowerNOW! Technology information\n"); printf("Available features:"); if (edx & (1<<0)) printf("\n\tTemperature sensing diode present."); if (edx & (1<<1)) { printf("\n\tFrequency ID control"); can_scale_fid=1; } if (edx & (1<<2)) { printf("\n\tVoltage ID control"); can_scale_vid=1; } if (edx & (1<<3)) printf("\n\tThermal Trip"); if (edx & (1<<4)) printf("\n\tThermal Monitoring"); if (edx & (1<<5)) printf("\n\tSoftware Thermal Control"); if (edx & (1<<6)) printf("\n\t100MHz multiplier control"); if (edx & (1<<7)) { printf("\n\tHardware P-state control"); can_scale_fid = can_scale_vid = 1; } if (edx & (1<<8)) printf("\n\tinvariant TSC"); if (edx & (1<<9)) { printf("\n\tCore Performance Boost"); has_cpb = 1; } if (edx & (1<<10)) printf("\n\read-only Effective Frequency Interface"); if (!(edx & 0x1ff)) printf(" None"); cpuid(cpu->number, 6, &eax, &ebx, &ecx, &edx); if (ecx & 1) printf("\n\tEffective Frequency Interface"); printf("\n\n"); if (can_scale_fid==0 && can_scale_vid==0) return; if (!user_is_root) return; if (family(cpu) < 0xf) decode_fidvid(cpu); else if (family(cpu) == 0xf) k8_decode_fidvid(cpu); else if (family(cpu) >= 0x10) decode_pstates(cpu, has_cpb); } AMD/powernow.h000066400000000000000000000033371167043552300135240ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Powernow register definitions. */ #include #define MSR_FID_VID_CTL 0xc0010041 #define MSR_FID_VID_STATUS 0xc0010042 #define MSR_PSTATE_LIMIT 0xc0010061 #define MSR_PSTATE_STATUS 0xc0010063 #define MSR_PSTATE 0xc0010064 union msr_vidctl { struct { unsigned FID:5, // 4:0 reserved1:3, // 7:5 VID:5, // 12:8 reserved2:3, // 15:13 FIDC:1, // 16 VIDC:1, // 17 reserved3:2, // 19:18 FIDCHGRATIO:1, // 20 reserved4:11, // 31-21 SGTC:20, // 32:51 reserved5:12; // 63:52 } bits; unsigned long long val; }; union msr_fidvidstatus { struct { unsigned CFID:5, // 4:0 reserved1:3, // 7:5 SFID:5, // 12:8 reserved2:3, // 15:13 MFID:5, // 20:16 reserved3:11, // 31:21 CVID:5, // 36:32 reserved4:3, // 39:37 SVID:5, // 44:40 reserved5:3, // 47:45 MVID:5, // 52:48 reserved6:11; // 63:53 } bits; unsigned long long val; }; union k8_msr_fidvidstatus { struct { unsigned cfid:6; unsigned res1:2; unsigned sfid:6; unsigned res2:2; unsigned mfid:6; unsigned res3:2; unsigned mrampvid:5; unsigned res4:2; unsigned fvpending:1; unsigned cvid:5; unsigned res5:3; unsigned svid:5; unsigned res6:3; unsigned maxvid:5; unsigned res7:3; unsigned minvid:5; unsigned res8:3; } bits; unsigned long long val; }; union msr_pstate { struct { unsigned fid:6; unsigned did:3; unsigned vid:7; unsigned res1:6; unsigned nbdid:1; unsigned res2:2; unsigned nbvid:7; unsigned iddval:8; unsigned idddiv:2; unsigned res3:21; unsigned en:1; } bits; unsigned long long val; }; extern double mobile_vid_table[32]; extern double fid_codes[32]; AMD/revision.h000066400000000000000000000130571167043552300135020ustar00rootroot00000000000000#ifndef _amd_revision_h_ #define _amd_revision_h_ /* * Copyright (C) 2007 Advanced Micro Devices, Inc. * Andreas Herrmann * Your use of this code is subject to the terms and conditions of the * GNU general public license version 2. See "COPYING" or * http://www.gnu.org/licenses/gpl2.html */ #include "../x86info.h" /* name ids to concatenate cpu name */ #define _OPTERON 0x0001 #define _OPTERON_DC 0x0002 #define _ATHLON64 0x0004 #define _ATHLON64_X2 0x0008 #define _ATHLON64_FX 0x0010 #define _ATHLON64_FX_DC 0x0020 #define _ATHLON64_M 0x0040 #define _SEMPRON 0x0080 #define _SEMPRON_M 0x0100 #define _ATHLON_XPM 0x0200 #define _TURION 0x0400 #define _TURION_X2 0x0800 struct id_string { int id; const char *name; }; /* Note: For newer K8 NPT parts naming switched from "Athlon 64" to "Athlon" etc., but we stick to the old naming here. */ struct id_string k8_names[] = { {_OPTERON, "Opteron"}, {_OPTERON_DC, "Dual-Core Opteron"}, {_ATHLON64, "Athlon 64"}, {_ATHLON64_X2, "Athlon 64 X2 Dual-Core"}, {_ATHLON64_FX, "Athlon 64 FX"}, {_ATHLON64_FX_DC, "Athlon 64 FX Dual-Core"}, {_ATHLON64_M, "Mobile Athlon 64"}, {_SEMPRON, "Sempron"}, {_SEMPRON_M, "Mobile Sempron"}, {_ATHLON_XPM, "Mobile Athlon XP-M"}, {_TURION, "Turion"}, {_TURION_X2, "Turion 64 X2"}, }; get_name(k8, int, k8_names); struct k8_rev { int eax; int socketid; int nameid; const char* rev; }; struct k8_rev k8_revisions[] = { {0x00f00, CONN_SOCKET_754, _ATHLON64, "SH-A0"}, {0x00f01, CONN_SOCKET_754, _ATHLON64, "SH-A2"}, {0x00f10, CONN_SOCKET_940, _ATHLON64, "SH-A0"}, {0x00f11, CONN_SOCKET_940, _ATHLON64, "SH-A2"}, {0x00f40, CONN_SOCKET_754, _ATHLON64, "SH-B0"}, {0x00f50, CONN_SOCKET_940, _OPTERON, "SH-B0"}, {0x00f51, CONN_SOCKET_940, _OPTERON, "SH-B3"}, {0x00f48, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_ATHLON_XPM, "SH-C0"}, {0x00f58, CONN_SOCKET_940, _OPTERON|_ATHLON64_FX, "SH-C0"}, {0x00f4a, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_ATHLON_XPM, "SH-CG"}, {0x00f7a, CONN_SOCKET_939, _ATHLON64|_ATHLON64_FX, "SH-CG"}, {0x00f5a, CONN_SOCKET_940, _OPTERON|_ATHLON64_FX, "SH-CG"}, {0x00fe0, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_SEMPRON|_SEMPRON_M|_ATHLON_XPM, "DH-CG"}, {0x00fc0, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_SEMPRON|_SEMPRON_M|_ATHLON_XPM, "DH-CG"}, {0x00ff0, CONN_SOCKET_939, _ATHLON64|_SEMPRON, "DH-CG"}, {0x00f82, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_SEMPRON_M|_ATHLON_XPM, "CH-CG"}, {0x00fb2, CONN_SOCKET_939, _ATHLON64, "CH-CG"}, {0x10f40, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_ATHLON_XPM, "SH-D0"}, {0x10f70, CONN_SOCKET_939, _ATHLON64|_ATHLON64_FX, "SH-D0"}, {0x10f50, CONN_SOCKET_940, _OPTERON|_ATHLON64_FX, "SH-D0"}, {0x10ff0, CONN_SOCKET_939, _ATHLON64|_SEMPRON, "DH-D0"}, {0x10fc0, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_SEMPRON|_SEMPRON_M|_ATHLON_XPM, "DH-D0"}, {0x10f80, CONN_SOCKET_754, _ATHLON64|_ATHLON64_M|_SEMPRON_M|_ATHLON_XPM, "CH-D0"}, {0x10fb0, CONN_SOCKET_939, _ATHLON64, "CH-D0"}, {0x20f10, CONN_SOCKET_940, _OPTERON_DC, "JH-E1"}, {0x20fc0, CONN_SOCKET_754, _SEMPRON, "DH-E3"}, {0x20ff0, CONN_SOCKET_939, _ATHLON64|_SEMPRON, "DH-E3"}, {0x20f51, CONN_SOCKET_940, _OPTERON, "SH-E4"}, {0x20f71, CONN_SOCKET_939, _OPTERON|_ATHLON64|_ATHLON64_FX, "SH-E4"}, {0x20fb1, CONN_SOCKET_939, _ATHLON64_X2, "BH-E4"}, {0x20f42, CONN_SOCKET_754, _ATHLON64_M|_TURION, "SH-E5"}, {0x20fc2, CONN_SOCKET_754, _SEMPRON|_SEMPRON_M, "DH-E6"}, {0x20ff2, CONN_SOCKET_939, _ATHLON64|_SEMPRON, "DH-E6"}, {0x20f12, CONN_SOCKET_940, _OPTERON_DC, "JH-E6"}, {0x20f32, CONN_SOCKET_939, _OPTERON_DC|_ATHLON64_X2, "JH-E6"}, /* K8 NPT */ {0x40f12, CONN_SOCKET_F, _OPTERON_DC, "JH-F2"}, {0x40f13, CONN_SOCKET_F, _OPTERON_DC, "JH-F3"}, {0x40f32, CONN_SOCKET_AM2, _ATHLON64_X2|_ATHLON64_FX_DC|_OPTERON_DC, "JH-F2"}, {0x40f33, CONN_SOCKET_AM2, _ATHLON64_X2|_ATHLON64_FX_DC|_OPTERON_DC, "JH-F3"}, {0x40f82, CONN_SOCKET_S1G1, _TURION_X2, "BH-F2"}, {0x40fb2, CONN_SOCKET_AM2, _ATHLON64_X2, "BH-F2"}, {0x40fc2, CONN_SOCKET_S1G1,_ATHLON64|_SEMPRON|_SEMPRON_M, "DH-F2"}, {0x40ff2, CONN_SOCKET_AM2, _ATHLON64|_SEMPRON, "DH-F2"}, {0x50ff2, CONN_SOCKET_AM2, _ATHLON64|_SEMPRON, "DH-F2"}, {0x50ff3, CONN_SOCKET_AM2, _ATHLON64, "DH-F3"}, {0x60f81, CONN_SOCKET_S1G1,_ATHLON64_X2, "BH-G1"}, {0x60f82, CONN_SOCKET_S1G1,_ATHLON64_X2|_TURION_X2, "BH-G2"}, {0x60fb1, CONN_SOCKET_AM2,_ATHLON64_X2, "BH-G1"}, {0x60fb2, CONN_SOCKET_AM2,_ATHLON64_X2, "BH-G2"}, {0x60fc2, CONN_SOCKET_S1G1,_SEMPRON_M, "DH-G2"}, {0x60ff2, CONN_SOCKET_AM2,_SEMPRON|_ATHLON64, "DH-G2"}, {0x70fc2, CONN_SOCKET_S1G1,_SEMPRON_M, "DH-G2"}, {0x70ff1, CONN_SOCKET_AM2,_SEMPRON|_ATHLON64, "DH-G1"}, {0x70ff2, CONN_SOCKET_AM2,_SEMPRON, "DH-G2"}, {0xc0f13, CONN_SOCKET_F, _ATHLON64_FX, "JH-F3"}, }; struct fam10h_rev { int eax; const char* rev; }; struct fam10h_rev fam10h_revisions[] = { {0x0100f2a, "DR-BA"}, {0x0100f22, "DR-B2"}, {0x0100f23, "DR-B3"}, {0x0100f42, "RB-C2"}, {0x0100f43, "RB-C3"}, {0x0100f52, "BL-C2"}, {0x0100f53, "BL-C3"}, {0x0100f62, "DA-C2"}, {0x0100f63, "DA-C3"}, {0x0100f80, "HY-D0"}, {0x0100f81, "HY-D1"}, {0x0100f91, "HY-D1"}, {0x0100fa0, "PH-E0"}, }; struct id_string fam11h_revisions[] = { {0x0200f31, "LG-B1"}, }; get_name(fam11h_revision, int, fam11h_revisions); struct id_string fam12h_revisions[] = { {0x0300f10, "LN1-B0"}, }; get_name(fam12h_revision, int, fam12h_revisions); struct id_string fam14h_revisions[] = { {0x00500f10, "ON-B0"}, }; get_name(fam14h_revision, int, fam14h_revisions); struct id_string fam15h_revisions[] = { {0x00600f12, "OR-B2"}, }; get_name(fam15h_revision, int, fam15h_revisions); #endif /* _amd_revision_h_ */ COPYING000066400000000000000000000431031167043552300121200ustar00rootroot00000000000000 GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. 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If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. 9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. 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It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. , 1 April 1989 Ty Coon, President of Vice This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. Centaur/000077500000000000000000000000001167043552300124655ustar00rootroot00000000000000Centaur/MSR-C3.c000066400000000000000000000010331167043552300135320ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Centaur specific parts. */ #include #include "../x86info.h" #include "centaur.h" void dump_C3_MSR (struct cpudata *cpu) { if (!user_is_root) return; printf("FCR: "); dumpmsr (cpu->number, 0x1107, 32); printf("Power management: "); if (cpu->model==6 || cpu->model==7) { printf("Longhaul\n"); decode_longhaul(cpu); } if (cpu->model==8 || cpu->model==9) { printf("Powersaver\n"); decode_powersaver(cpu); } } Centaur/centaur.h000066400000000000000000000002761167043552300143040ustar00rootroot00000000000000#ifndef _CENTAUR_H #define _CENTAUR_H void dump_C3_MSR (struct cpudata *cpu); void decode_longhaul(struct cpudata *cpu); void decode_powersaver(struct cpudata *cpu); #endif /* _CENTAUR_H */ Centaur/identify.c000066400000000000000000000104441167043552300144470ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Centaur specific parts. */ #include #include "../x86info.h" #include "centaur.h" static char *centaur_nameptr; #define add_to_cpuname(x) centaur_nameptr += snprintf(centaur_nameptr, sizeof(x), "%s", x) void identify_centaur(struct cpudata *cpu) { centaur_nameptr = cpu->name; switch (tuple(cpu) & 0xff0) { case 0x540: add_to_cpuname("Winchip C6"); //transistors = 5400000; //fab_process = "0.35 micron CMOS"; //die_size = "88 sq.mm"; //introduction_date = "September 1997"; //pipeline_stages = 6; break; case 0x580: switch (cpu->stepping) { case 0 ... 6: add_to_cpuname("Winchip 2"); break; case 7 ... 9: add_to_cpuname("Winchip 2A"); break; case 0xA ... 0xF: add_to_cpuname("Winchip 2B"); break; } break; case 0x590: add_to_cpuname("Winchip 3"); break; /* Family 6 is when VIA bought out Cyrix & Centaur * This is the CyrixIII family. */ case 0x660: add_to_cpuname("VIA Cyrix 3 (Samuel) [C5A]"); //pipeline_stages = 12; //1.8-2.0V //CPGA //75mm //0.18 Al //500-733MHz //11.3 mil transistors //June 6 2000 break; case 0x670: switch (cpu->stepping) { case 0 ... 7: add_to_cpuname("VIA C3 (Samuel 2) [C5B]"); //pipeline_stages = 12; //1.6V //CPGA/EBGA //52mm //0.15u Al //650-800MHz //15.2 mil transistors //Mar 25 2001 break; case 8 ... 0xf: add_to_cpuname("VIA C3 (Ezra) [C5C]"); //pipeline_stages = 12; //1.35V //CPGA/EBGA //52mm //0.15u/0.13u hybrid Al //800-1000MHz //15.4 mil transistors //Sep 11 2001 break; } break; /* Ezra-T is much like Ezra but reworked to run in Pentium III Tualatin sockets. */ case 0x680: add_to_cpuname("VIA C3 (Ezra-T) [C5M/C5N]"); //pipeline_stages = 12; //CPGA/EBGA/uPGA2/uFCPGA //900-1200MHz //56mm //0.15/0.13u hybrid (Cu) //15.5 mil transistors //C5N=copper interconnectrs //2002 break; case 0x690: add_to_cpuname("VIA C3 (Nehemiah) [C5XL]"); //pipeline_stages = 16; //2 SSE units //first C3 to run FPU at full clock speed (previous ran at 50%) //1100-1300 //0.13 (Cu) //die_size = "78 sq. mm"; (C5X) //die_size = "54 sq. mm"; (C5XL) //January 22 2003 break; case 0x6A0: switch (cpu->stepping) { case 0: case 8 ... 0xF: add_to_cpuname("VIA C3 (Esther) [C7-M]"); break; case 1 ... 7: add_to_cpuname("VIA C3 (Ruth) [C7-M]"); break; } break; // C5P introduced the HW AES // C5YL // C5X // CZA default: add_to_cpuname("Unknown VIA CPU"); break; } } static void decode_centaur_cacheinfo(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; if (cpu->maxei >= 0x80000005) { /* TLB and cache info */ cpuid(cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx); printf("Cache info\n"); printf(" L1 Instruction cache: %dKB, %d-way associative, %d lines per tag, line size=%d bytes.\n", edx >> 24, (edx >> 16) & 0xff, (edx >> 8) & 0xff, edx & 0xff); printf(" L1 Data cache: %dKB %d-way associative, %d lines per tag, line size=%d bytes.\n", ecx >> 24, (ecx >> 16) & 0xff, (ecx >> 8) & 0xff, ecx & 0xff); if (cpu->maxei >= 0x80000006) { cpuid (cpu->number, 0x80000006, &eax, &ebx, &ecx, &edx); if ((cpu->family==6) && (cpu->model==7 || cpu->model==8)) /* Work around errata. */ printf(" L2 (on CPU) cache: %dKB %d-way associative, %d lines per tag, line size=%d bytes.\n", ecx >> 24, (ecx >> 16) & 0x0f, (ecx >> 8) & 0x0f, ecx & 0xff); else printf(" L2 (on CPU) cache: %dKB %d-way associative, %d lines per tag, line size=%d bytes.\n", ecx >> 16, (ecx >> 12) & 0x0f, (ecx >> 8) & 0x0f, ecx & 0xff); } printf("TLB info\n"); cpuid(cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx); printf(" Instruction TLB: %d-way associative. %d entries.\n", (ebx >> 8) & 0xff, ebx & 0xff); printf(" Data TLB: %d-way associative. %d entries.\n", ebx >> 24, (ebx >> 16) & 0xff); } /* check on-chip L2 cache size */ } void display_centaur_info(struct cpudata *cpu) { if (cpu->maxei == 0) return; decode_centaur_cacheinfo(cpu); if (cpu->family == 6 && show_cpuid) dump_C3_MSR(cpu); } Centaur/longhaul-v2.c000066400000000000000000000043571167043552300150000ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Longhaul v2 register definitions. */ #include #include "../x86info.h" union msr_longhaul { struct { unsigned RevisionID:4, // 3:0 RevisionKey:4, // 7:4 EnableSoftBusRatio:1, // 8 EnableSoftVID:1, // 9 EnableSoftBSEL:1, // 10 Reserved:3, // 11:13 SoftBusRatio4:1, // 14 VRMRev:1, // 15 SoftBusRatio:4, // 19:16 SoftVID:5, // 24:20 Reserved2:3, // 27:25 SoftBSEL:2, // 29:28 Reserved3:2, // 31:30 MaxMHzBR:4, // 35:32 MaximumVID:5, // 40:36 MaxMHzFSB:2, // 42:41 MaxMHzBR4:1, // 43 Reserved4:4, // 47:44 MinMHzBR:4, // 51:48 MinimumVID:5, // 56:52 MinMHzFSB:2, // 58:57 MinMHzBR4:1, // 59 Reserved5:4; // 63:60 } bits; unsigned long long val; }; void decode_longhaul2(struct cpudata *cpu) { union msr_longhaul longhaul; if (read_msr(cpu->number, 0x110A, &longhaul.val) == 1) { dumpmsr (cpu->number, 0x110A, 64); if (longhaul.bits.RevisionID & 1) printf("\tSoftVID support\n"); if (longhaul.bits.RevisionID & 2) printf("\tSoftBSEL support\n"); if (longhaul.bits.RevisionID == 0) printf("\tSoftware clock multiplier only: No Softvid\n"); if (longhaul.bits.EnableSoftBusRatio==1) printf("\tEnableSoftBusRatio=Enabled\n"); if (longhaul.bits.EnableSoftVID==1) printf("\tEnableSoftVID=Enabled\n"); if (longhaul.bits.EnableSoftBSEL==1) printf("\tEnableSoftBSEL=Enabled\n"); printf("\tSoftBusRatio4=%s\n", longhaul.bits.SoftBusRatio4 ? "1" : "0"); printf("\tSoftBusRatio="); binary (4, longhaul.bits.SoftBusRatio); if (longhaul.bits.RevisionID & 1) printf("\tVRM Rev=%s\n", longhaul.bits.VRMRev ? "Mobile VRM" : "VRM 8.5"); printf("\tMaxMHzBR4: %s\n", longhaul.bits.MaxMHzBR4 ? "1" : "0"); printf("\tMaxMHzBR: "); binary (4, longhaul.bits.MaxMHzBR); printf("\tMaximumVID: "); binary (5, longhaul.bits.MaximumVID); printf("\tMaxMHzFSB: "); binary (2, longhaul.bits.MaxMHzFSB); printf("\tMinMHzBR4: %s\n", longhaul.bits.MinMHzBR4 ? "1" : "0"); printf("\tMinMHzBR: "); binary (4, longhaul.bits.MinMHzBR); printf("\tMinimumVID: "); binary (4, longhaul.bits.MinimumVID); printf("\tMinMHzFSB: "); binary (2, longhaul.bits.MinMHzFSB); } } Centaur/longhaul.c000066400000000000000000000043751167043552300144530ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Longhaul register decoding. */ #include #include "../x86info.h" #include "centaur.h" union msr_longhaul { struct { unsigned RevisionID:4, // 3:0 RevisionKey:4, // 7:4 EnableSoftBusRatio:1, // 8 EnableSoftVID:1, // 9 EnableSoftBSEL:1, // 10 Reserved:3, // 11:13 SoftBusRatio4:1, // 14 VRMRev:1, // 15 SoftBusRatio:4, // 19:16 SoftVID:5, // 24:20 Reserved2:3, // 27:25 SoftBSEL:2, // 29:28 Reserved3:2, // 31:30 MaxMHzBR:4, // 35:32 MaximumVID:5, // 40:36 MaxMHzFSB:2, // 42:41 MaxMHzBR4:1, // 43 Reserved4:4, // 47:44 MinMHzBR:4, // 51:48 MinimumVID:5, // 56:52 MinMHzFSB:2, // 58:57 MinMHzBR4:1, // 59 Reserved5:4; // 63:60 } bits; unsigned long long val; }; void decode_longhaul(struct cpudata *cpu) { union msr_longhaul longhaul; if (read_msr(cpu->number, 0x110A, &longhaul.val) == 1) { dumpmsr (cpu->number, 0x110A, 64); if (longhaul.bits.RevisionID & 1) printf("\tSoftVID support\n"); if (longhaul.bits.RevisionID & 2) printf("\tSoftBSEL support\n"); if (longhaul.bits.RevisionID == 0) printf("\tSoftware clock multiplier only: No Softvid\n"); if (longhaul.bits.EnableSoftBusRatio==1) printf("\tEnableSoftBusRatio=Enabled\n"); if (longhaul.bits.EnableSoftVID==1) printf("\tEnableSoftVID=Enabled\n"); if (longhaul.bits.EnableSoftBSEL==1) printf("\tEnableSoftBSEL=Enabled\n"); printf("\tSoftBusRatio4=%s\n", longhaul.bits.SoftBusRatio4 ? "1" : "0"); printf("\tSoftBusRatio="); binary (4, longhaul.bits.SoftBusRatio); if (longhaul.bits.RevisionID & 1) printf("\tVRM Rev=%s\n", longhaul.bits.VRMRev ? "Mobile VRM" : "VRM 8.5"); printf("\tMaxMHzBR4: %s\n", longhaul.bits.MaxMHzBR4 ? "1" : "0"); printf("\tMaxMHzBR: "); binary (4, longhaul.bits.MaxMHzBR); printf("\tMaximumVID: "); binary (5, longhaul.bits.MaximumVID); printf("\tMaxMHzFSB: "); binary (2, longhaul.bits.MaxMHzFSB); printf("\tMinMHzBR4: %s\n", longhaul.bits.MinMHzBR4 ? "1" : "0"); printf("\tMinMHzBR: "); binary (4, longhaul.bits.MinMHzBR); printf("\tMinimumVID: "); binary (4, longhaul.bits.MinimumVID); printf("\tMinMHzFSB: "); binary (2, longhaul.bits.MinMHzFSB); } } Centaur/powersaver.c000066400000000000000000000040461167043552300150320ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Powersaver MSR decoding. */ #include #include #include #include "../x86info.h" #include "centaur.h" #include "powersaver.h" void decode_powersaver(struct cpudata *cpu) { union msr_powersaver ps; if (!user_is_root) return; dumpmsr(cpu->number, MSR_POWERSAVER, 64); printf("\n"); if (read_msr(cpu->number, MSR_POWERSAVER, &ps.val) != 1) { printf("Something went wrong reading MSR_POWERSAVER\n"); return; } printf(" RevisionID: %x : ", ps.bits.RevisionID); switch (ps.bits.RevisionID) { case 0x0: printf("Initial revision (Software clock multiplier only, no SoftVID)\n"); break; case 0x1: printf("SoftVID support\n"); break; default: printf("Unknown (0x%x).\n", ps.bits.RevisionID); break; } printf(" Software clock multiplier is "); if (ps.bits.EnableSoftBusRatio == 0) printf("disabled\n"); else { printf("enabled\n"); printf("\tMaxMHzBR4: %s\n", ps.bits.MaxMHzBR4 ? "1" : "0"); printf("\tMaxMHzBR: "); binary (4, ps.bits.MaxMHzBR); printf("\tMinMHzBR4: %s\n", ps.bits.MinMHzBR4 ? "1" : "0"); printf("\tMinMHzBR: "); binary (4, ps.bits.MinMHzBR); } /* these bits invalid if revision == 0*/ if (ps.bits.RevisionID != 0) { printf(" Software VID is "); if (ps.bits.EnableSoftVID == 0) printf("disabled\n"); else { printf("enabled\n"); printf("\tVRM Rev=%s\n", ps.bits.VRMRev ? "Mobile VRM" : "VRM 8.5"); printf("\tMinimumVID: "); binary (4, ps.bits.MinimumVID); printf("\tMaximumVID: "); binary (5, ps.bits.MaximumVID); } if (ps.bits.EnableSoftBusRatio==1) { printf("\tEnableSoftBusRatio=Enabled\n"); printf("\tMaxMHzFSB: "); binary (2, ps.bits.MaxMHzFSB); printf("\tMinMHzFSB: "); binary (2, ps.bits.MinMHzFSB); } //if (ps.bits.EnableSoftBSEL==1) // printf("\tEnableSoftBSEL=Enabled\n"); printf("\tSoftBusRatio4=%s\n", ps.bits.SoftBusRatio4 ? "1" : "0"); printf("\tSoftBusRatio="); binary (4, ps.bits.SoftBusRatio); } } Centaur/powersaver.h000066400000000000000000000014151167043552300150340ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Powersaver MSR definitions. */ #include #define MSR_POWERSAVER 0x110a union msr_powersaver { struct { unsigned RevisionID:4, // 3:0 RevisionKey:4, // 7:4 EnableSoftBusRatio:1, // 8 EnableSoftVID:1, // 9 Reserved:4, // 10:13 SoftBusRatio4:1, // 14 VRMRev:1, // 15 SoftBusRatio:4, // 16:19 SoftVID:5, // 20:24 Reserved2:7, // 25:31 MaxMHzBR:4, // 32:35 MaximumVID:5, // 36:40 MaxMHzFSB:2, // 41:42 MaxMHzBR4:1, // 43 Reserved3:4, // 44:47 MinMHzBR:4, // 48:51 MinimumVID:5, // 52:56 MinMHzFSB:2, // 57:58 MinMHzBR4:1, // 59 Reserved4:4; // 60:63 } bits; unsigned long long val; }; Cyrix/000077500000000000000000000000001167043552300121625ustar00rootroot00000000000000Cyrix/Cyrix.h000066400000000000000000000001251167043552300134270ustar00rootroot00000000000000#ifndef _CYRIX_H #define _CYRIX_H void decode_Cyrix_TLB (int); #endif /* _CYRIX_H */ Cyrix/identify.c000066400000000000000000000053011167043552300141400ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Cyrix specific information. */ #include #include "../x86info.h" #include "Cyrix.h" static char *cyrix_nameptr; #define add_to_cpuname(x) cyrix_nameptr += snprintf(cyrix_nameptr, sizeof(x), "%s", x) /* Decode TLB and cache info descriptors */ void decode_Cyrix_TLB (int x) { switch (x & 0xff) { case 0: break; case 0x70: printf("TLB: 32 entries 4-way associative 4KB pages\n"); break; case 0x80: printf("L1 Cache: 16KB 4-way associative 16 bytes/line\n"); break; } } /* Cyrix-specific information */ void Identify_Cyrix(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; cyrix_nameptr = cpu->name; switch (tuple(cpu) & 0xff0) { case 0x450: add_to_cpuname("MediaGX"); break; case 0x520: add_to_cpuname("6x86"); break; case 0x524: add_to_cpuname("GXm"); break; case 0x600: add_to_cpuname("6x86/MX"); break; case 0x620: add_to_cpuname("MII"); break; default: add_to_cpuname("Unknown CPU"); break; } /* Check for presence of extended info */ if (cpu->maxei < 0x80000000) return; if (cpu->maxei >= 0x80000001) { cpuid (cpu->number, 0x80000001, &eax, &ebx, &ecx, &edx); cpu->stepping = eax & 0xf; cpu->model = (eax >> 4) & 0xf; cpu->family = (eax >> 8) & 0xf; switch (cpu->family) { case 4: add_to_cpuname("MediaGX"); break; case 5: add_to_cpuname("6x86/GXm"); break; case 6: add_to_cpuname("6x86/MX"); break; } } } void display_Cyrix_info(struct cpudata *cpu) { unsigned int i, ntlb; unsigned int eax, ebx, ecx, edx; printf("TLB & L1 Cache info\n"); if (cpu->cpuid_level >= 2 && show_cacheinfo) { /* TLB and L1 Cache info */ ntlb = 255; for (i = 0; i < ntlb; i++) { cpuid (cpu->number, 2, &eax, &ebx, &ecx, &edx); ntlb = eax & 0xff; decode_Cyrix_TLB (eax >> 8); decode_Cyrix_TLB (eax >> 16); decode_Cyrix_TLB (eax >> 24); /* ebx and ecx are reserved */ if ((edx & 0x80000000) == 0) { decode_Cyrix_TLB (edx); decode_Cyrix_TLB (edx >> 8); decode_Cyrix_TLB (edx >> 16); decode_Cyrix_TLB (edx >> 24); } } } printf("TLB & L1 Cache info from extended info\n"); if (cpu->maxei >= 0x80000005 && show_cacheinfo) { /* TLB and L1 Cache info */ ntlb = 255; for (i = 0; i < ntlb; i++) { cpuid (cpu->number, 0x80000005, &eax, &ebx, &ecx, &edx); ntlb = eax & 0xff; decode_Cyrix_TLB (ebx >> 8); decode_Cyrix_TLB (ebx >> 16); decode_Cyrix_TLB (ebx >> 24); /* eax and edx are reserved */ if ((ecx & 0x80000000) == 0) { decode_Cyrix_TLB (ecx); decode_Cyrix_TLB (ecx >> 8); decode_Cyrix_TLB (ecx >> 16); decode_Cyrix_TLB (ecx >> 24); } } } } Intel/000077500000000000000000000000001167043552300121375ustar00rootroot00000000000000Intel/Intel.h000066400000000000000000000020311167043552300133570ustar00rootroot00000000000000#ifndef _INTEL_H #define _INTEL_H extern void decode_Intel_caches (struct cpudata *cpu, int output); extern void show_Intel_caches(struct cpudata *cpu); extern void decode_Intel_machine_check(int cpunum, int family); extern void dump_p4_MSRs(struct cpudata *cpu); extern void dump_p6_MSRs(struct cpudata *cpu); extern void dump_performance_MSRs(struct cpudata *cpu); extern void dump_thermal_MSRs(struct cpudata *cpu); extern void dump_IDA_MSRs(struct cpudata *cpu); extern void decode_microcode(struct cpudata *cpu); extern void Identify_Intel_family6pentium(struct cpudata *cpu); extern void Identify_Intel_family6core(struct cpudata *cpu); extern void Identify_Intel_family15(struct cpudata *cpu); #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_IA32_UCODE_REV 0x8b #define MSR_IA32_PERF_STATUS 0x198 #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_THERM_CONTROL 0x19a #define MSR_IA32_THERM_STATUS 0x19c #define MSR_PM_THERM2_CTL 0x19d #define MSR_IA32_MISC_ENABLE 0x1a0 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 #endif /* _INTEL_H */ Intel/MSR-IDA.c000066400000000000000000000024401167043552300133370ustar00rootroot00000000000000/* * (C) 2011 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * */ #include #include #include #include "../x86info.h" #include "Intel.h" void dump_IDA_MSRs(struct cpudata *cpu) { unsigned long long val = 0; unsigned int eax, ebx, ecx, edx; if (!user_is_root) return; if (cpu->cpuid_level < 6) return; cpuid(cpu->number, 6, &eax, &ebx, &ecx, &edx); printf("Dynamic Acceleration MSRs:\n"); printf(" Opportunistic performance operation "); if ((eax & (1 << 1)) == 1) printf("enabled by BIOS\n"); else printf("disabled by BIOS (or not supported)\n"); if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) != 1) return; if ((val & (1ULL << 38)) == 1) { printf(" IA32_MISC_ENABLES[38] is 1 (disabled opportunistic performance operation)\n"); return; } if (read_msr(cpu->number, MSR_IA32_PERF_CTL, &val) != 1) return; printf(" IA32_PERF_CTL: "); if ((val & (1ULL << 32)) == 1) { printf("IDA/Turbo DISENGAGE=1, "); } printf("EIST Transition target: 0x%x\n", (unsigned int) val & 0xff); if (ecx & (1 << 3)) { /* SETBH present ? */ if (read_msr(cpu->number, MSR_IA32_ENERGY_PERF_BIAS, &val) != 1) return; printf(" IA32_ENERGY_PERF_BIAS: "); printf("hint=%d\n", (unsigned int) val & 0xf); } } Intel/MSR-P4.c000066400000000000000000000044521167043552300132320ustar00rootroot00000000000000/* * (C) 2002 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel P4 specific MSR information * See 24547203.pdf for more details. */ #include #include #include #include "../x86info.h" #include "Intel.h" void dump_p4_MSRs (struct cpudata *cpu) { unsigned long long val = 0; if (!user_is_root) return; printf("Pentium 4 specific MSRs:\n"); if (read_msr (cpu->number, 0x17, &val) == 1) printf("IA32_PLATFORM_ID=%016llx\n", val); if (read_msr (cpu->number, 0x2a, &val) == 1) { printf("System bus in order queue depth="); if ((val & (1<<2))) printf("1"); else printf("12"); printf("\n"); } if (read_msr (cpu->number, 0x2c, &val) == 1) { printf("MSR_EBC_FREQUENCY_ID=%016llx\n", val); } if (read_msr (cpu->number, 0x8b, &val) == 1) { printf("IA32_BIOS_SIGN_ID=%016llx\n", val); } if (read_msr (cpu->number, 0x119, &val) == 1) { printf("Processor serial number is "); if ((val & (1<<21))) printf("dis"); else printf("en"); printf("abled\n"); } if (read_msr (cpu->number, 0x1a0, &val) == 1) { printf("Fast string enable is "); if (!(val & (1<<0))) printf("un"); printf("set\n"); printf("x87 FPU Fopcode compatability mode is "); if (!(val & (1<<2))) printf("un"); printf("set\n"); printf("Thermal monitor enable is "); if (!(val & (1<<3))) printf("un"); printf("set\n"); printf("Split lock disable is "); if (!(val & (1<<4))) printf("un"); printf("set\n"); printf("L3 cache disable is "); if (!(val & (1<<6))) printf("un"); printf("set\n"); printf("Performance monitoring is "); if (!(val & (1<<7))) printf("un"); printf("available\n"); printf("Suppress lock enable is "); if (!(val & (1<<8))) printf("un"); printf("set\n"); printf("Prefetch queue disable is "); if (!(val & (1<<9))) printf("un"); printf("set\n"); printf("FERR# Interrupt reporting enable is "); if (!(val & (1<<10))) printf("un"); printf("set\n"); printf("Branch trace storage unavailable is "); if (!(val & (1<<11))) printf("un"); printf("set\n"); printf("Precise Event Based Sampling Unavailable is "); if (!(val & (1<<12))) printf("un"); printf("set\n"); } /* if (read_msr (cpu->number, 0x410, &val) == 1) { } */ printf("\n"); } Intel/MSR-P6.c000066400000000000000000000012361167043552300132310ustar00rootroot00000000000000/* * (C) 2002 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel P6 specific MSR information * See 24547203.pdf for more details. */ #include #include #include #include "../x86info.h" #include "Intel.h" void dump_p6_MSRs (struct cpudata *cpu) { unsigned long long val = 0; if (!user_is_root) return; printf("P6 family MSRs:\n"); if (read_msr (cpu->number, 0x2a, &val) == 1) { printf("Low power mode is "); if ((val & (1<<26)) == 0) printf("dis"); else printf("en"); printf("abled\n"); } /* if (read_msr (cpu->number, 0x410, &val) == 1) { } */ printf("\n"); } Intel/MSR-performance.c000066400000000000000000000016061167043552300152460ustar00rootroot00000000000000/* * (C) 2011 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * */ #include #include #include #include "../x86info.h" #include "Intel.h" void dump_performance_MSRs(struct cpudata *cpu) { unsigned long long val = 0; if (!user_is_root) return; printf("Performance MSRs:\n"); if (read_msr(cpu->number, MSR_IA32_PERF_STATUS, &val) == 1) printf(" MSR_IA32_PERF_STATUS: 0x%llx\n", val); if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) == 1) { printf(" MSR_IA32_MISC_ENABLE: 0x%llx", val); printf(" [Enabled: "); if (val & (1<<3)) printf("TCC "); if (val & (1<<7)) printf("PerfMon "); if (val & (1<<10)) printf("FERR# "); if (val & (1<<11)) printf("noBTS "); if (val & (1<<12)) printf("noPEBS "); if (val & (1<<16)) printf("EnhancedSpeedStep "); printf("]\n"); } printf("\n"); } Intel/MSR-thermal.c000066400000000000000000000024001167043552300143720ustar00rootroot00000000000000/* * (C) 2011 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * */ #include #include #include #include "../x86info.h" #include "Intel.h" void dump_thermal_MSRs(struct cpudata *cpu) { unsigned long long val = 0; if (!user_is_root) return; if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) != 1) return; // tcc enabled ? if (!(val & (1<<3))) return; printf("Thermal MSRs:\n"); if (read_msr(cpu->number, MSR_PM_THERM2_CTL, &val) == 1) { /* THERM2_CTL */ printf(" MSR_PM_THERM2_CTL: 0x%llx [Thermal monitor: %d]\n", val, (val & (1<<16)) ? 2 : 1); } if (read_msr(cpu->number, MSR_IA32_THERM_CONTROL, &val) == 1) { printf(" MSR_IA32_THERM_CONTROL: 0x%llx ", val); if (val & (1<<4)) { printf("[Software-controlled clock: %f%% duty cycle]\n", ((val >> 1) & 7) / 8.); } else printf("[Software-controlled clock disabled (full speed)]\n"); } if (read_msr (cpu->number, MSR_IA32_THERM_STATUS, &val) == 1) { /* THERM_STATUS */ printf(" MSR_IA32_THERM_STATUS: 0x%llx", val); if (val & (1<<0|1<<1)) { printf(" ["); if (val & (1<<0)) printf("TooHot "); if (val & (1<<1)) printf("WasTooHot "); printf("]"); } printf("\n"); } printf("\n"); } Intel/cachesize.c000066400000000000000000000311571167043552300142500ustar00rootroot00000000000000/* * (C) 2001-2011 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel specific parts * * References: * http://www.intel.com/Assets/PDF/appnote/241618.pdf */ #include #include #include "../x86info.h" #include "Intel.h" #define MB(x) ((x) * 1024) struct _cache_table { unsigned char descriptor; int size; char *string; }; static struct _cache_table TRACE_cache_table[] = { { 0x70, 12, "Instruction trace cache: 12K uOps, 8-way associative." }, { 0x71, 16, "Instruction trace cache: 16K uOps, 8-way associative." }, { 0x72, 32, "Instruction trace cache: 32K uOps, 8-way associative." }, { 0x73, 64, "Instruction trace cache: 64K uOps, 8-way associative." }, { 0, 0, NULL } }; static struct _cache_table L1I_cache_table[] = { { 0x6, 8, "L1 Instruction cache: 8KB, 4-way associative. 32 byte line size." }, { 0x8, 16, "L1 Instruction cache: 16KB, 4-way associative. 32 byte line size." }, { 0x9, 32, "L1 Instruction cache: 32KB, 4-way associative. 64 byte line size." }, { 0x30, 32, "L1 Instruction cache: 32KB, 8-way associative. 64 byte line size." }, { 0, 0, NULL } }; static struct _cache_table L1D_cache_table[] = { { 0xa, 8, "L1 Data cache: 8KB, 2-way associative. 32 byte line size." }, { 0xc, 16, "L1 Data cache: 16KB, 4-way associative. 32 byte line size." }, { 0xd, 16, "L1 Data cache: 16KB, 4-way associative. 64 byte line size. ECC." }, { 0xe, 24, "L1 Data cache: 24KB, 6-way associative. 64 byte line size. ECC." }, { 0x2c, 32, "L1 Data cache: 32KB, 8-way associative. 64 byte line size." }, { 0x60, 16, "L1 Data cache: 16KB, sectored, 8-way associative. 64 byte line size." }, { 0x66 , 8, "L1 Data cache: 8KB, sectored, 4-way associative. 64 byte line size." }, { 0x67, 16, "L1 Data cache: 16KB, sectored, 4-way associative. 64 byte line size." }, { 0x68, 32, "L1 Data cache: 32KB, sectored, 4-way associative. 64 byte line size." }, { 0, 0, NULL } }; static struct _cache_table L2_cache_table[] = { { 0x21, 256, "L2 (MLC): 256KB, 8-way associative. 64 byte line size." }, { 0x39, 128, "L2 cache: 128KB, 4-way associative. Sectored. 64 byte line size." }, /* { 0x3a, 192, "L2 cache: 192KB, 6-way associative. Sectored. 64 byte line size." }, { 0x3b, 128, "L2 cache: 128KB, 2-way associative. Sectored. 64 byte line size." }, { 0x3c, 256, "L2 cache: 256KB, 4-way associative. Sectored. 64 byte line size." }, { 0x3d, 384, "L2 cache: 384KB, 6-way associative. Sectored. 64 byte line size." }, { 0x3e, 512, "L2 cache: 512KB, 4-way associative. Sectored. 64 byte line size." }, { 0x3f, 256, "L2 cache: 256KB, 2-way associative. Sectored. 64 byte line size." }, */ /* 3a->3f are no longer listed. */ { 0x41, 128, "L2 cache: 128KB, 4-way associative. 32 byte line size." }, { 0x42, 256, "L2 cache: 256KB, 4-way associative. 32 byte line size." }, { 0x43, 512, "L2 cache: 512KB, 4-way associative. 32 byte line size." }, { 0x44, MB(1), "L2 cache: 1MB, 4-way associative. 32 byte line size." }, { 0x45, MB(2), "L2 cache: 2MB, 4-way associative. 32 byte line size." }, { 0x48, MB(3), "L2 cache: 3MB, 12-way associative. 64 byte line size. Unified on-die." }, { 0x4e, MB(6), "L2 cache: 6MB, 24-way set associative, 64-byte line size." }, { 0x79, 128, "L2 cache: 128KB, sectored, 8-way associative. 64 byte line size." }, { 0x7a, 256, "L2 cache: 256KB, sectored, 8-way associative. 64 byte line size." }, { 0x7b, 512, "L2 cache: 512KB, sectored, 8-way associative. 64 byte line size." }, { 0x7c, MB(1), "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." }, { 0x7d, MB(2), "L2 cache: 2MB, 8-way associative. 64 byte line size." }, { 0x7f, 512, "L2 cache: 512KB, 2-way associative. 64 byte line size." }, { 0x80, 512, "L2 cache: 512KB, 8-way associative. 64 byte line size." }, { 0x82, 256, "L2 cache: 256KB, 8-way associative. 32 byte line size." }, { 0x83, 512, "L2 cache: 512KB, 8-way associative. 32 byte line size." }, { 0x84, MB(1), "L2 cache: 1MB, 8-way associative. 32 byte line size." }, { 0x85, MB(2), "L2 cache: 2MB, 8-way associative. 32 byte line size." }, { 0x86, 512, "L2 cache: 512KB, 4-way associative. 64 byte line size." }, { 0x87, MB(1), "L2 cache: 1MB, 8-way associative. 64 byte line size." }, { 0, 0, NULL } }; static struct _cache_table L2L3_cache_table[] = { { 0x46, MB(4), "L2 cache: 4MB, 4-way associative. 64 byte line size." }, { 0x47, MB(8), "L2 cache: 8MB, 8-way associative. 64 byte line size." }, { 0x48, MB(3), "L2 cache: 3MB, 12-way associative. 64 byte line size." }, { 0x49, MB(4), "L2 cache: 4MB, 16-way associative. 64 byte line size." }, { 0x4a, MB(6), "L2 cache: 6MB, 12-way associative. 64 byte line size." }, { 0x4b, MB(8), "L2 cache: 8MB, 16-way associative. 64 byte line size." }, { 0x4c, MB(12), "L2 cache: 12MB, 12-way associative. 64 byte line size." }, { 0x4d, MB(16), "L2 cache: 16MB, 16-way associative. 64 byte line size." }, { 0x78, MB(1), "L2 cache: 1MB, sectored, 8-way associative. 64 byte line size." }, { 0, 0, NULL } }; static struct _cache_table L3L2_cache_table[] = { { 0x46, MB(4), "L3 cache: 4MB, 4-way associative. 64 byte line size." }, { 0x47, MB(8), "L3 cache: 8MB, 8-way associative. 64 byte line size." }, { 0x49, MB(4), "L3 cache: 4MB, 16-way associative. 64 byte line size." }, { 0x4a, MB(6), "L3 cache: 6MB, 12-way associative. 64 byte line size." }, { 0x4b, MB(8), "L3 cache: 8MB, 16-way associative. 64 byte line size." }, { 0x4c, MB(12), "L3 cache: 12MB, 12-way associative. 64 byte line size." }, { 0x4d, MB(16), "L3 cache: 16MB, 16-way associative. 64 byte line size." }, { 0x78, MB(1), "L3 cache: 1MB, sectored, 8-way associative. 64 byte line size." }, { 0xd0, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." }, { 0xd1, MB(1), "L3 cache: 1MB, 4-way associative. 64 byte line size." }, { 0xd2, MB(2), "L3 cache: 2MB, 4-way associative. 64 byte line size." }, { 0xd6, MB(1), "L3 cache: 1MB, 8-way associative. 64 byte line size." }, { 0xd7, MB(2), "L3 cache: 2MB, 8-way associative. 64 byte line size." }, { 0xd8, MB(4), "L3 cache: 4MB, 8-way associative. 64 byte line size." }, { 0xdc, MB(2), "L3 cache: 2MB, 12-way associative. 64 byte line size." }, { 0xdd, MB(4), "L3 cache: 4MB, 12-way associative. 64 byte line size." }, { 0xe2, MB(2), "L3 cache: 2MB, 16-way associative. 64 byte line size." }, { 0xe3, MB(4), "L3 cache: 4MB, 16-way associative. 64 byte line size." }, { 0xe4, MB(8), "L3 cache: 8MB, 16-way associative. 64 byte line size." }, { 0xea, MB(12), "L3 cache: 12MB, 24-way associative. 64 byte line size." }, { 0xeb, MB(18), "L3 cache: 18MB, 24-way associative. 64 byte line size." }, { 0xec, MB(24), "L3 cache: 24MB, 24-way associative. 64 byte line size." }, { 0xde, MB(8), "L3 cache: 8MB, 12-way associative. 64 byte line size." }, { 0, 0, NULL } }; static struct _cache_table L3_cache_table[] = { { 0x22, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." }, { 0x23, MB(1), "L3 cache: 1MB, 8-way associative. 64 byte line size." }, { 0x25, MB(2), "L3 cache: 2MB, 8-way associative. 64 byte line size." }, { 0x29, MB(4), "L3 cache: 4MB, 8-way associative. 64 byte line size." }, { 0, 0, NULL } }; static struct _cache_table ITLB_cache_table[] = { { 0x1, 32, "Instruction TLB: 4KB pages, 4-way associative, 32 entries" }, { 0x2, 2, "Instruction TLB: 4MB pages, fully associative, 2 entries" }, { 0x50, 64, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries." }, { 0x51, 128, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries." }, { 0x52, 256, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 256 entries." }, { 0x55, 7, "Instruction TLB: 2MB or 4MB pages, fully associative, 7 entries" }, { 0xb0, 128, "Instruction TLB: 4K pages, 4-way associative, 128 entries." }, { 0xb1, 4, "Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative" }, { 0xb2, 64, "Instruction TLB: 4K pages, 4-way associative, 64 entries." }, { 0, 0, NULL } }; static struct _cache_table DTLB_cache_table[] = { { 0x3, 64, "Data TLB: 4KB pages, 4-way associative, 64 entries" }, { 0x4, 8, "Data TLB: 4MB pages, 4-way associative, 8 entries" }, { 0x5, 32, "Data TLB: 4MB pages, 4-way associative, 32 entries" }, { 0x56, 16, "L1 Data TLB: 4MB pages, 4-way set associative, 16 entries" }, { 0x57, 16, "L1 Data TLB: 4KB pages, 4-way set associative, 16 entries" }, { 0x5a, 32, "Data TLB: 4KB or 4MB pages, fully associative, 32 entries." }, { 0x5b, 64, "Data TLB: 4KB or 4MB pages, fully associative, 64 entries." }, { 0x5c, 128, "Data TLB: 4KB or 4MB pages, fully associative, 128 entries." }, { 0x5d, 256, "Data TLB: 4KB or 4MB pages, fully associative, 256 entries." }, { 0xb3, 128, "Data TLB: 4K pages, 4-way associative, 128 entries." }, { 0xb4, 256, "Data TLB: 4K pages, 4-way associative, 256 entries." }, { 0xca, 512, "Data TLB: 4K pages, 4-way associative, 512 entries." }, { 0, 0, NULL } }; static struct _cache_table prefetch_table[] = { {0xf0, 64, "64 byte prefetching."}, {0xf1, 64, "128 byte prefetching."}, }; static unsigned char found_unknown=0; static unsigned char unknown_array[256]; /* Decode Intel TLB and cache info descriptors */ //TODO : Errata workaround. http://www.sandpile.org/post/msgs/20002736.htm static void decode_Intel_cache(int des, struct cpudata *cpu, int output, struct _cache_table *table) { int k = 0; int found = 0; /* "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache". Skip this pointless entry.*/ if (des == 0x40) return; //TODO: Add description to link-list in cpu-> while ((table[k].descriptor != 0) && (found == 0)) { if (table[k].descriptor == des) { if (table == TRACE_cache_table) cpu->cachesize_trace += table[k].size; if (table == L1I_cache_table) cpu->cachesize_L1_I += table[k].size; if (table == L1D_cache_table) cpu->cachesize_L1_D += table[k].size; if (table == L2_cache_table) cpu->cachesize_L2 += table[k].size; if (table == L2L3_cache_table) cpu->cachesize_L2 += table[k].size; if (table == L3_cache_table) cpu->cachesize_L3 += table[k].size; if (table == L3L2_cache_table) cpu->cachesize_L3 += table[k].size; if (output) printf(" %s\n", table[k].string); found = 1; } k++; } if ((found == 0) && (unknown_array[des] == 0)) { unknown_array[des] = 1; found_unknown++; } } static void decode_cache(struct cpudata *cpu, struct _cache_table *table, int output) { unsigned int i, j, n; unsigned int regs[4]; /* Decode TLB and cache info */ cpuid(cpu->number, 2, ®s[0], ®s[1], ®s[2], ®s[3]); /* Number of times to iterate */ n = regs[0] & 0xff; for (i=0; inumber, 2, ®s[0], ®s[1], ®s[2], ®s[3]); /* If bit 31 is set, this is an unknown format */ for (j=0; j<3; j++) if (regs[j] & 0x80000000) regs[j] = 0; /* Byte 0 is level count, not a descriptor */ for (j=1; j<16; j++) { unsigned char val = regs[j / 4] >> (unsigned int)(8 * (j % 4)); if (val) decode_Intel_cache(val, cpu, output, table); } } } static void clean_unknowns(struct _cache_table *table) { int j=0; int des; while (table[j].descriptor != 0) { des = table[j++].descriptor; if (unknown_array[des] == 1) { unknown_array[des] = 0; found_unknown--; } } } void decode_Intel_caches(struct cpudata *cpu, int output) { unsigned int i = 0; unsigned char oldknown; if (cpu->cpuid_level < 2) return; memset(&unknown_array, 0, sizeof(unknown_array)); if (output) printf("Cache info\n"); decode_cache(cpu, TRACE_cache_table, output); decode_cache(cpu, L1I_cache_table, output); decode_cache(cpu, L1D_cache_table, output); oldknown = found_unknown; decode_cache(cpu, L2_cache_table, output); if (found_unknown > 0) { if (oldknown == found_unknown) decode_cache(cpu, L2L3_cache_table, output); else decode_cache(cpu, L3L2_cache_table, output); } decode_cache(cpu, L3_cache_table, output); if (output) printf("TLB info\n"); decode_cache(cpu, ITLB_cache_table, output); decode_cache(cpu, DTLB_cache_table, output); decode_cache(cpu, prefetch_table, output); if (found_unknown == 0) return; /* Remove any known entries */ clean_unknowns(TRACE_cache_table); clean_unknowns(L1I_cache_table); clean_unknowns(L1D_cache_table); clean_unknowns(L2_cache_table); clean_unknowns(L3_cache_table); clean_unknowns(L2L3_cache_table); clean_unknowns(ITLB_cache_table); clean_unknowns(DTLB_cache_table); clean_unknowns(prefetch_table); if (found_unknown == 0) return; if (output) printf("Found unknown cache descriptors: "); for (i=0; i<256; i++) { if (unknown_array[i] == 1) if (output) printf("%02x ", i); } if (output) printf("\n"); found_unknown = 0; } Intel/eblcr.c000066400000000000000000000023071167043552300133740ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Bus speed parsing. */ #include #include "../x86info.h" void interpret_eblcr(u32 lo) { const unsigned int buscode[2][4] = { { 6667, 13333, 10000, 0 }, { 10000, 13333, 10000, 0 } }; const unsigned int mult[32] = { 10, 6, 8, 0, 11, 7, 9, 0, 10, 14, 16, 12, 0, 15, 0, 13, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; int bus = (lo >> 18) & 3; int mul = (lo >> 22) & 15; int busclock, cpuclk; return; /* too many bugs right now.. fix for a future release */ if (!user_is_root || !show_eblcr) return; /* * FIXME: * 766MHz Celeron. 66MHz x 11.5 Being picked up as 133x5.0 * bus:1 mul:0 */ /* printf("bus:%x mul:%x\n", bus, mul);*/ /* The mobile pIII added bit 27. * This is zero on other intel and on the cyrix III */ if (lo & (1 >> 27)) mul += 16; busclock = buscode[1][bus]/100; if (busclock == 0 || mult[mul] == 0) printf("Unknown CPU/BUS multiplier (%d X %dMHz, %x).\n", mul, bus, lo); cpuclk = (buscode[1][bus] * mult[mul])/200; printf("Bus Speed (%dMHz) x Multiplier (%.1fx) = CPU speed %dMhz\n", busclock, (float) cpuclk/busclock, cpuclk); } Intel/identify-family15.c000066400000000000000000000171141167043552300155470ustar00rootroot00000000000000/* * (C) 2008 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel family 15 specific identification. */ #include #include #include "../x86info.h" #include "Intel.h" static char p4_423_datasheet[]="http://developer.intel.com/design/pentium4/datashts/24919805.pdf"; static char p4_478_datasheet[]="http://developer.intel.com/design/pentium4/datashts/24988703.pdf\n\thttp://developer.intel.com/design/pentium4/datashts/29864304.pdf"; static char p4_errata[]="http://developer.intel.com/design/pentium4/specupdt/249199.htm"; static char *intel_nameptr; #define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x) void Identify_Intel_family15(struct cpudata *cpu) { intel_nameptr = cpu->name; switch (model(cpu)) { case 0x0: /* Family 15 */ cpu->connector = CONN_SOCKET_423; cpu->datasheet_url = strdup(p4_423_datasheet); cpu->errata_url = strdup(p4_errata); add_to_cpuname("Pentium 4"); switch (cpu->stepping) { case 7: //SL4QD SL4SF = 1.3GHz //SL4SG SL4SC = 1.4GHz //SL4SH SL4TY = 1.5GHz add_to_cpuname(" [B2]"); break; case 0xA: //SL5FW SL5GC 1.3GHz //SL4WS SL4X2 SL59U SL5N7 1.4GHz //SL4WT SL4X3 SL59V SL5NB 1.5GHz //SL4WU SL4X4 SL5US SL5UW 1.6GHz //SL57W SL57V SL59X SL5N9 1.7GHz //SL4WV SL4X5 SL5UT SL5UV 1.8GHz add_to_cpuname(" [C1]"); break; } break; case 0x1: cpu->connector = CONN_SOCKET_423; add_to_cpuname("Pentium 4 (Willamette)"); cpu->datasheet_url = strdup(p4_423_datasheet); cpu->errata_url = strdup(p4_errata); switch (cpu->stepping) { case 1: //400FSB 256K L2 //SSpec MHz L3 //SL5G8 1.6 1M //SL5S4 1.6 1M //SL5FZ 1.4 512K //SL5RZ 1.4 512K //SL5G2 1.5 512K //SL5RW 1.5 512K add_to_cpuname(" [C0]"); break; case 2: //SL5TG SL5UE 1.4GHz //SL5SX SL5TJ SL5UF SL62Y SL5TN 1.5GHz //SL5VL SL5UL SL5VH SL5UJ 1.6GHz //SL5SY SL5TK SL5UG SL62Z 1.7GHz //SL5VM SL5VM SL5VJ SL5UK 1.8GHz //SL5VN SL5WH SL5VK SL5WG 1.9GHz //SL5SZ SL5TQ SL5TL 2GHz add_to_cpuname(" [D0]"); break; case 3: //SL6BC SL679 1.6GHz //SL6BD SL67A 1.7GHz //SL6BE SL78B 1.8GHz //SL6BF SL67C 1.9GHz add_to_cpuname(" [E0]"); break; } break; case 0x2: cpu->connector = CONN_SOCKET_478; cpu->datasheet_url = strdup(p4_478_datasheet); cpu->errata_url = strdup(p4_errata); switch (cpu->brand) { case 15: add_to_cpuname("Celeron (P4 core)"); break; case 7: default: add_to_cpuname("Pentium 4 (Northwood)"); break; } switch (cpu->stepping) { case 2: //512K L2 // L3 //SL6GZ 1.5 1M //SL6KB 1.5 1M //SL6H2 1.9 2M //SL6KC 1.9 2M //SL66Z 2.0 1M //SL6KD 2.0 1M add_to_cpuname(" [A0]"); break; case 4: //SL66B 1.6GHz //SL63X SL62P SL6BQ 1.8GHz //SL6BR SL5YR 2GHz //SL5YS SL6BS SL5ZU 2.2GHz //SL6B3 SL67Y 2.26GHz (533MHz FSB) //SL6BT SL65R SL67R 2.4GHz (400MHz FSB) //SL6B4 SL67Z 2.4GHz (533MHz FSB) //SL6B5 SL6B2 2.53GHz (533MHz FSB) add_to_cpuname(" [B0]"); break; case 5: /*[M0] */ //SL6Z3 2.4GHz (800FSB) //SL6Z5 2.8GHz (800FSB) /* P4 Extreme edition.*/ //SL7AA 3.2GHz (800FSB) 2MB L3 cache //SL7CH 3.4GHz (800FSB) 2MB L3 cache /* 400FSB B1 512K L2 */ //SL6YJ 2.0 1M L3 //SL6Z6 2.0 1M L3 //SL6Z2 2.5 1M L3 //SL6Z7 2.5 1M L3 //SL6YL 2.8 2M L3 //SL6Z8 2.8 2M L3 add_to_cpuname(" [M0]"); break; case 6: //400FSB 512K L2 //SL79V 3.0 4M L3 //SL79Z 2.7 2M L3 //SL7A5 2.2 2M L3 add_to_cpuname(" [C0]"); break; case 7: //SL6HL SL6K6 2.8GHz (533MHz FSB) //SL6LA SL6S6 1.8GHz //SL6GQ SL6S7 SL6E7 2GHz //SL6GR SL6SB SL6EB 2.2GHz //SL6DU SL6RY SL6EE 2.26GHz (533FSB) //SL6EF SL6DV SL6S9 SL6RZ SL6E9 2.4GHz (533FSB) //SL6SA 2.5GHz (400FSB) //SL6EG SL6S2 SL6DW 2.53GHz (533FSB) //SL6SB 2.6GHz (400FSB) //SL6S3 SL6SK 2.66GHz (533FSB) //SL6S4 SL6SL 2.8GHz (533FSB) //SL6S5 SL6K7 SL6SM SL6JJ 3.06GHz (533FSB) add_to_cpuname(" [C1]"); break; case 9: //SL6QL 1.8GHz //SL6QM SL6PK 2.0GHz //SL6QN SL6PL 2.2GHz //SL6QR SL6PB 2.26GHz (533FSB) //SL6QP SL6PM 2.4GHz //SL6QB SL6PC 2.4GHz (533FSB) //SL6WF SL6WR 2.4GHz (800FSB) //SL6QQ 2.5GHz //SL6Q9 SL6PD 2.53GHz (533FSB) //SL6QR 2.6GHz //SL6WH SL6WS 2.6GHz (800FSB) //SL6QA SL6PE 2.66GHz (533FSB) //SL6QB SL6PF 2.8GHz (533FSB) //SL6WJ SL6WT 2.8GHz (800FSB) //SL6WU SL6WK 3GHz (800FSB) //SL6QC SL6PG 3.06GHz (533FSB) //SL6WG SL6WE 3.2GHz (800FSB) //SL793 3.4GHz (800FSB) add_to_cpuname(" [D1]"); break; } break; case 0x3: switch (cpu->stepping) { case 3: /* sspec speed fsb l2 90nm SL7D7 2.26GHz 533 512K SL7FY 2.4GHz 800 1M SL7E8 2.4GHz 533 1M SL7E9 2.66GHz 533 1M SL7D8 2.8GHz 533 1M SL79K 2.8GHz 800 1M SL79L 3.0GHz 800 1M SL79M 3.2GHz 800 1M SL7B8 3.2GHz 800 1M SL7B9 3.4GHz 800 1M SL7AJ 3.4GHz 800 1M process = "0.09u"; 125 million transistors 112mm2 die size pipeline_stages=31 */ add_to_cpuname("Pentium 4 (Prescott) [C0]"); break; case 4: /* 1M L2 90nm sspec speed fsb SL7E2 2.8GHz 533 SL7E3 2.8GHz 800 SL7KA 2.8GHz 800 SL7K9 2.8GHz 533 SL7E4 3.0GHz 800 SL7KB 3.0GHz 800 SL7L4 3.0GHz 800 SL7L5 3.2GHz 800 SL7E5 3.2GHz 800 SL7KC 3.2GHz 800 SL7E6 3.4GHz 800 SL7KD 3.4GHz 800 SL7YP 2.4GHz 533 SL7YU 2.66GHz 533 SL7J4 2.8GHz 533 SL7J5 2.8GHz 800 SL7KH 2.8GHz 533 SL7KJ 2.8GHz 800 SL7YV 2.93GHz 533 SL7J6 3.0GHz 800 SL7KK 3.0GHz 800 SL7J7 3.2GHz 800 SL7KL 3.2GHz 800 SL7LA 3.2GHz 800 SL7J8 3.4GHz 800 SL7KM 3.4GHz 800 SL7L8 3.4GHz 800 SL7J9 3.6GHz 800 SL7KN 3.6GHz 800 SL7L9 3.6GHz 800 */ add_to_cpuname("Pentium 4 (Prescott) [D0]"); break; } break; case 0x4: add_to_cpuname("Pentium 4 "); switch (cpu->stepping) { case 1: /* 1M L2 90nm SL88F 2.4GHz 533 SL8B3 2.66GHz 533 SL88G 2.8GHz 533 SL88H 2.8GHz 800 SL7PL 2.8GHz 800 SL7PK 2.8GHz 533 SL7PM 3GHz 800 SL88J 3GHz 800 SL7PN 3.2GHz 800 SL88K 3.2GHz 800 SL88L 3.4GHz 800 SL7PP 3.4GHz 800 SL7PT 2.66GHz 533 SL82P 2.8GHz 800 SL7PR 2.8GHz 800 SL8HX 2.8GHz 800 SL85U 2.66GHz 533 SL8J8 2.66GHz 533 SL85V 2.93GHz 533 SL8J9 2.93GHz 533 SL87L 3.06GHz 533 SL8JA 3.06GHz 533 SL82X 3.0GHz 800 SL7PU 3.0GHz 800 SL8HZ 3.0GHz 800 SL7PW 3.2GHz 800 SL7PX 3.2GHz 800 SL82Z 3.2GHz 800 SL8J2 3.2GHz 800 SL7PY 3.4GHz 800 SL7PZ 3.4GHz 800 SL833 3.4GHz 800 SL7ZW 3.4GHz 800 SL8J5 3.4GHz 800 SL84X 3.6GHz 800 SL7Q2 3.6GHz 800 SL7NZ 3.6GHz 800 SL8J6 3.6GHz 800 SL82U 3.8GHz 800 SL84Y 3.8GHz 800 SL7P2 3.8GHz 800 SL8J7 3.8GHz 800 */ /* 8MB L3 [C-0] SL8EY 3.3GHz 667 SL8EW 3GHz 667 4MB L3 SL8ED 2.8GHz 667 */ add_to_cpuname("(Prescott) [E0]"); break; case 3: /* 2M L2 90nm SL7Z9 3.0GHz 800 SL7Z8 3.2GHz 800 SL8Z7 3.4GHz 800 SL7Z5 3.6GHz 800 SL7Z4 3.73GHz 800 SL7Z3 3.8GHz 800 */ add_to_cpuname("(Prescott) [N0]"); break; case 4: /* 1Mx2 L2 800MHz FSB SL88T 2.8GHz SL88S 3GHz SL88R 3.2GHz SL8FK 3.2GHz */ add_to_cpuname("Extreme Edition [A0]"); break; default: add_to_cpuname("D (Foster)"); break; } break; case 0x5: cpu->connector = CONN_SOCKET_603; // cpu->datasheet_url = strdup(p4_478_datasheet); // cpu->errata_url = strdup(p4_errata); add_to_cpuname("Pentium 4 Xeon (Foster)"); break; default: add_to_cpuname("Unknown CPU"); break; } } Intel/identify-family6-extended.c000066400000000000000000000221211167043552300172570ustar00rootroot00000000000000/* * (C) 2001,2008 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel family 6 specific decoding (Core family). * All the CPUs described in this file have cpu->emodel set to 1 */ #include #include #include "../x86info.h" #include "Intel.h" static char nehalem_info_url[] = "http://www.intel.com/design/corei7/documentation.htm"; static char *intel_nameptr; #define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x) void Identify_Intel_family6core(struct cpudata *cpu) { intel_nameptr = cpu->name; switch (model(cpu)) { case 7: switch (cpu->stepping) { case 6: // sSpec step CoreFreq Bus cache // SLAN3 C0 3.00 1333 12MB (2x6) QX9650 // SLANY C0 3.2 1600 12MB (2x6) QX9775 /* sSpec name package step HFM/LFM/SLFM FSB IDAT L2Cache SLAQG T9300 m-FCPGA C-0 2.5/1.2/0.8 800 2.7 6 SLAPV T9300 m-FCBGA C-0 2.5/1.2/0.8 800 2.7 6 SLAPU T8300 m-FCBGA C-0 2.4/1.2/0.8 800 2.6 3 SLAUU T8100 m-FCPGA C-0 2.1/1.2/0.8 800 2.3 3 SLAPT T8100 m-FCBGA C-0 2.1/1.2/0.8 800 2.3 3 SLAPT T8100 m-FCBGA C-0 2.1/1.2/0.8 800 2.3 3 SLAPA T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3 SLAPR T8300 m-FCBGA M-0 2.4/1.2/0.8 800 2.6 3 SLAP9 T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3 SLAPS T8100 m-FCBGA M-0 2.1/1.2/0.8 800 2.3 3 SLAVJ T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3 SLAXG T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3 SLAZD T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3 SLAYZ T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3 SLAZC T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3 SLAZB T9300 m-FCPGA C-0 2.5/1.2/0.8 800 2.7 6 SLAYY T9300 m-FCPGA C-0 2.5/1.2/0.8 800 2.7 6 SLAZA T9500 m-FCPGA C-0 2.6/1.2/0.8 800 2.8 6 SLAYX T9500 m-FCPGA C-0 2.6/1.2/0.8 800 2.8 6 SLAQJ X9000 m-FCPGA C-0 2.8/1.2/0.8 800 N/A 6 SLAZ3 X9000 m-FCPGA C-0 2.8/1.2/0.8 800 N/A 6 SLB47 T9600 m-FCPGA C-0 2.80/1.6/0.8 1066 2.93 6 SLB43 T9600 m-FCBGA C-0 2.80/1.6/0.8 1066 2.93 6 SLB46 T9400 m-FCPGA C-0 2.53/1.6/0.8 1066 2.66 6 SL3BX T9400 m-FCBGA C-0 2.53/1.6/0.8 1066 2.66 6 SLB4E P9500 m-FCPGA C-0 2.53/1.6/0.8 1066 2.66 6 SL3BW P9500 m-FCBGA C-0 2.53/1.6/0.8 1066 2.66 6 SLB3S P8600 m-FCPGA M-0 2.40/1.6/0.8 1066 2.53 3 SLB4N P8600 m-FCBGA M-0 2.40/1.6/0.8 1066 2.53 3 SLB3R P8400 m-FCPGA M-0 2.26/1.6/0.8 1066 2.40 3 SLB4M P8400 m-FCBGA M-0 2.26/1.6/0.8 1066 2.40 3 SLB3Q P8400 m-FCPGA M-0 2.26/1.6/0.8 1066 2.40 3 SL3BV P8600 m-FCBGA C-0 2.40/1.6/0.8 1066 2.53 3 SL3BU P8400 m-FCBGA C-0 2.26/1.6/0.8 1066 2.40 3 SLB48 X9100 m-FCPGA C-0 3.06/1.6/0.8 1066 N/A 6 SLAYS T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3 SLAYU T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3 SLAYP T8100 m-FCPGA M-0 2.1/1.2/0.8 800 2.3 3 SLAYQ T8300 m-FCPGA M-0 2.4/1.2/0.8 800 2.6 3 SLG8E P7350 m-FCBGA C-0 2.00/1.6/0.8 1066 N/A 3 SLB45 P7450 m-FCPGA C-0 2.13/1.6/0.8 1066 N/A 3 SLB44 P7350 m-FCPGA C-0 2.00/1.6/0.8 1066 N/A 3 SLB54 P7450 m-FCPGA M-0 2.13/1.6/0.8 1066 N/A 3 SLB53 P7350 m-FCPGA M-0 2.00/1.6/0.8 1066 N/A 3 SLB5J QX9300 m-FCPGA E-0 2.53/1.6/(n/a) 1066 2.8 45 12 SLB5G Q9100 m-FCPGA E-0 2.26/1.6/(n/a) 1066 2.53 45 12 SLB64 SP9400 m-FCBGA C-0 2.40/1.6/0.8 1066 2.53 25 6 SLB63 SP9300 m-FCBGA C-0 2.26/1.6/0.8 1066 2.40 25 6 SLB66 SL9400 m-FCBGA C-0 1.86/1.6/0.8 1066 2.13 17 6 SLB65 SL9300 m-FCBGA C-0 1.60/0.8/0.8 1066 1.86 17 6 SLB5V SU9400 m-FCBGA M-0 1.40/0.8/0.8 800 1.60 10 3 SLB5Q SU9300 m-FCBGA M-0 1.20/0.8/0.8 800 1.40 10 3 SLGAR SU3300 m-FCBGA M-0 1.20/0.8/(n/a) 800 N/A 5.5 3 (Celeron) SLGAS 723 m-FCBGA M-0 1.20/(n/a)/(n/a) 800 N/A 10 1 (Celeron) */ add_to_cpuname("Core 2 quad "); switch (cpu->MHz) { case 3000: add_to_cpuname("Core 2 quad (QX9650) "); break; case 3200: add_to_cpuname("Core 2 Extreme quad (QX9775) "); break; } add_to_cpuname("[C0] "); break; case 7: // sSpec step CoreFreq Bus cache // SLAWM C1 3.2 1600 12MB (2x6) QX9770 // SLAWQ C1 2.83 1600 12MB (2x6) Q9550 // SLAWR C1 2.66 1333 12MB (2x6) Q9450 // SLAWE M1 2.50 1333 6MB (2x3) Q9300 // SLB5M M1 2.33 1333 4MB (2x2) Q8200 add_to_cpuname("Core 2 quad "); switch (cpu->MHz) { case 3200: add_to_cpuname("(QX9770) [C1] "); break; case 2830: add_to_cpuname("(Q9550) [C1] "); break; case 2660: add_to_cpuname("(Q9450) [C1] "); break; case 2500: add_to_cpuname("(Q9300) [M1] "); break; case 2330: add_to_cpuname("(Q8200) [M1] "); break; } break; case 0xa: // sSpec step CoreFreq Bus cache // SLB8W E0 3.00 1333 12MB (2x6) Q9650 // SLB8V E0 2.83 1333 12MB (2x6) Q9550 // SLB6B R0 2.66 1333 6MB (2x3) Q9400 // SLB5W R0 2.5 1333 4MB (2x2) Q8300 add_to_cpuname("Core 2 quad "); switch (cpu->MHz) { case 3000: add_to_cpuname("(Q9650) [E0] "); break; case 2830: add_to_cpuname("(Q9550) [E0] "); break; case 2660: add_to_cpuname("(Q9400) [R0] "); break; case 2500: add_to_cpuname("(Q8300) [R0] "); break; } break; } break; case 0xa: add_to_cpuname("Core i7 "); //sSpec step CoreFreq/QuickpathGTs/DDR3 cache //SLBCJ C-0 3.2/6.40/1066 8MB //SLBCK C-0 2.93/4.80/1066 8MB //SLBCH C-0 2.66/4.80/1066 8MB break; case 0xc: add_to_cpuname("Atom "); switch (cpu->stepping) { case 1: /* * sSpec step TDP Name FSB EFMS HFM LFM Package MCU * QDTD B0 2.5 x 533 106C1 1.6GHz 800MHz FCBGA8 M01106C1109 * QDTB B0 2.5 x 533 106C1 1.6GHz 800MHz FCBGA8 M01106C1109 * QGFD1 B0 X X 533 106C1 1.33GHz ---- FCBGA437 M01106C1109 */ break; case 2: /* * sSpec step TDP Name FSB EFMS HFM LFM Package * * * SLB6Q C0 0.65W Z500 400 106C2 800GHz 600MHz FCBGA8 * SLB2C C0 2W Z510 400 106C2 1.1GHz 600MHz FCBGA8 * SLGMG C0 0.65W Z515 400 106C2 800MHz 600MHz FCBGA8 * SLB2H C0 2W Z520 533 106C2 1.33GHz 800MHz FCBGA8 * SLB6P C0 2W Z530 533 106C2 1.60GHz 800MHz FCBGA8 * QGZT C0 2.5W N270 533 106C2 1.60GHz 800MHz FCBGA8 * QKGY1 C0 8W 300 533 106C2 1.60GHz ------ FCBGA437 * QGZR2 C0 4W 230 533 106C2 1.60GHz ----- FCBGA437 * SLB2M C0 2.4W Z540 533 106C2 1.86GHz 800MHz FCBGA8 * SLGPT C0 2.4W Z550 533 106C2 2.0GHz 800MHz FCBGA8 */ switch (cpu->MHz) { case 800: add_to_cpuname("Z500/Z515 [SLB6Q/SLGMG][C0]"); break; case 1100: add_to_cpuname("Z510 [SLB2C][C0]"); break; case 1330: add_to_cpuname("Z520 [SLB2H][C0]"); break; case 1600: // could be a Z530,an N270,a QKGY1 or a QGZR2 break; case 1860: add_to_cpuname("Z540 [SLB2M][C0]"); break; case 2000: add_to_cpuname("Z550 [SLGPT][C0]"); break; } break; } break; case 0xe: add_to_cpuname("Core "); switch (cpu->stepping) { case 8: switch (cpu->MHz) { case 1000: // SL99W/SL8W7 533FSB add_to_cpuname("Duo U2400/Solo U1300 [C-0]"); break; case 1200: // SL8W6 533FSB add_to_cpuname("Solo U1400 [C-0]"); break; case 1500: // SL8VX 667FSB add_to_cpuname("Duo L2300 [C-0]"); break; case 1600: // SL9JE/SL9JV/SL8VR/SL8VV/SL8VY/SL8W3/SL8VW 667FSB add_to_cpuname("Solo T1300/Duo T2300(E)/Duo L2400"); break; case 1800: // SL92X/SL8VQ/SL8VU/SL92V/SL92X 667FSB add_to_cpuname("Solo T1400/Duo T2400 [C-0]"); break; case 2000: // SL8VP/SL8VT/SL92U/SL92W 667FSB add_to_cpuname("Solo T1500/Duo T2500 [C-0]"); break; case 2150: // SL8VN/SL8VS 667FSB add_to_cpuname("Duo T2600 [C-0]"); break; } break; case 0xc: switch (cpu->MHz) { case 1200: // SL99V 533FSB add_to_cpuname("Duo U2500 [D-0]"); break; case 1800: // SL9JU 667FSB add_to_cpuname("Duo L2500 [D-0]"); break; case 2300: // SL9JP/SL9K4 667FSB add_to_cpuname("Duo T2700 [D-0]"); break; } } break; case 0x17: add_to_cpuname("Core 2 Duo "); switch (cpu->stepping) { case 4: add_to_cpuname("(Penryn)"); break; case 6: add_to_cpuname("P8600"); break; } break; case 0x1a: /* * SLBCJ C-0 0x000106A4 3.20 / 6.40/ 1066 8MB * SLBCK C-0 0x000106A4 2.93 / 4.80/ 1066 8MB * SLBCH C-0 0x000106A4 2.66 / 4.80/ 1066 8MB */ add_to_cpuname("Core i7 (Nehalem) [bloomfield/gainestown]"); cpu->info_url = strdup(nehalem_info_url); switch (cpu->MHz) { case 3200: add_to_cpuname(" [C-0][SLBCJ]"); break; case 2930: add_to_cpuname(" [C-0][SLBCK]"); break; case 2660: add_to_cpuname(" [C-0][SLBCH]"); break; } break; case 0x1c: add_to_cpuname("Atom"); switch (cpu->stepping) { case 10: add_to_cpuname(" D510"); break; } break; case 0x1e: add_to_cpuname("Core i7 (Nehalem) [Lynnfield/Clarksfield/Jasper Forest]"); break; case 0x25: add_to_cpuname("Core i7 (Nehalem) [Clarkdale/Arrandale]"); break; case 0x2c: add_to_cpuname("Core i7 (Nehalem) [Gulftown/Westmere-EP]"); break; case 0x2d: add_to_cpuname("Core i7 (Sandybridge) [Romely-EP]"); break; case 0x2e: add_to_cpuname("Core i7 (Nehalem) [Beckton]"); break; case 0x2f: add_to_cpuname("Core i7 (Nehalem-EX) [Westmere] [Xeon E7]"); break; default: add_to_cpuname("Unknown model. "); } } Intel/identify-family6.c000066400000000000000000000334371167043552300154750ustar00rootroot00000000000000/* * (C) 2001,2008 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel family 6 specific decoding. (Pentium family) */ #include #include #include "../x86info.h" #include "Intel.h" static char pm_90nm_info_url[] = "http://www.intel.com/design/intarch/pentiumm/docs_pentiumm_90nm.htm"; static char *intel_nameptr; #define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x) void Identify_Intel_family6pentium(struct cpudata *cpu) { intel_nameptr = cpu->name; switch (model(cpu)) { case 0x0: add_to_cpuname("Pentium Pro A-Step"); cpu->connector = CONN_SOCKET_8; break; case 0x1: add_to_cpuname("Pentium Pro"); cpu->connector = CONN_SOCKET_8; switch (cpu->stepping) { case 1: add_to_cpuname(" [B0]"); switch (cpu->MHz) { case 133: //sSpec# Q0812, Q0815 break; case 150: //sSpec# Q0813, Q0816, SY002, SY011, SY014 break; } break; case 2: add_to_cpuname(" [C0]"); //sSpec# Q0822, Q0825, Q0826, SY010 break; case 6: add_to_cpuname(" [sA0]"); switch (cpu->MHz) { case 166: //sSpec# Q0864 break; case 180: //sSpec# SY012, Q0858, Q0860, Q0873, Q0910 break; case 200: //cache = 256 sSpec# SY013, Q0859, Q0874 //cache = 512 sSpec# Q0865 break; } break; case 7: add_to_cpuname(" [sA1]"); switch (cpu->MHz) { case 166: //sSpec# SY034, SY047, Q0918, Q0929, Q935 break; case 180: //sSpec# SY031, SY039, SU103, Q0871, Q0907 break; case 200: //cache = 256 sSpec# SY032, SY040, SL245, SL247, SU104, Q076, Q0872, Q0908, Q0909 //cache = 512 sSpec# SY048, Q0920, Q0924, Q932 , Q936 break; } break; case 9: add_to_cpuname(" [sB1]"); switch (cpu->MHz) { case 166: //sSpec# Q008, Q009, SL2FJ, SL22X break; case 180: //sSpec# SL22S, SL22U, SL23L, Q033, Q035 break; case 200: //cache = 256 sSpec# L22T, SL22V, SL23M,SL254,SL255,Q034,Q036 ,Q083 ,Q084 //cache = 512 sSpec# Q010, Q011, SL22Z //cache = 1MB sSpec# SL259, SL25A break; } break; } break; case 0x3: add_to_cpuname("Pentium II "); cpu->connector = CONN_SLOT_1; switch (cpu->stepping) { case 2: add_to_cpuname("Overdrive [tdB0]"); break; case 3: add_to_cpuname("(Klamath) [C0]"); switch (cpu->MHz) { case 233: //sSpec# SL264, SL268, SL28K break; case 266: //sSpec# SL265, SL269, SL28L break; case 300: //sSpec# SL28R, SL2MZ break; } break; case 4: add_to_cpuname("(Klamath) [C1]"); switch (cpu->MHz) { case 233: //sSpec# SL2HD, SL2HF, SL2QA break; case 266: //sSpec# SL2HC, SL2HE, SL2QB break; case 300: //sSpec# SL2HA, SL2QC break; } break; } break; case 0x4: //Does this exist? Its not in Intels spec update. cpu->connector = CONN_SLOT_1; add_to_cpuname("Pentium II (Deschutes?)"); break; case 0x5: cpu->connector = CONN_SLOT_1; switch (cpu->cachesize_L2) { case 0: add_to_cpuname("Celeron (Covington)"); break; case 256: add_to_cpuname("Mobile Pentium II (Dixon)"); break; case 512: switch (cpu->stepping) { case 0: add_to_cpuname("Pentium II [dA0]"); switch (cpu->MHz) { case 266: //sSpec# SL2K9 break; case 333: //sSpec# SL2KA, SL2QF break; } break; case 1: add_to_cpuname("Pentium II (Deschutes) [dA1]"); switch (cpu->MHz) { case 300: //66 bus sSpec# SL35V, SL2VY break; case 333: //66 bus sSpec# SL2QH, SL2S5, SL2ZP break; case 350: //100Bus - sSpec# SL2ZQ, SL2S6, SL2SF break; case 400: //100Bus - sSpec# Sl2S7, SL2SH break; } break; case 2: add_to_cpuname("Pentium II (Deschutes) [dB0]"); switch (cpu->MHz) { case 266: //66Bus sSpec# SL33D, SL2W7 break; case 300: //66Bus - SL2YK, SL2W8 break; case 333: //66Bus - SL2KE, SL2TV break; case 350: //100Bus - SL2WZ, SL2U3, SL2U4, SL356, SL37F, SL3FN break; case 400: //100Bus - SL2YM, SL37G, SL2U5, SL2U6, SL357, SL3EE, SL3F9 break; case 450: //100Bus - SL2WB, SL37H, SL2U7, SL358 break; } break; case 3: add_to_cpuname("Pentium II (Deschutes) [dB1]"); switch (cpu->MHz) { case 350: //100Bus - SL38M, SL36U, SL3J2 break; case 400: //100Bus - SL38N, SL38Z, SL3D5 break; } break; default: add_to_cpuname("Pentium II"); break; } } break; case 0x6: cpu->connector = CONN_SOCKET_370; if (cpu->cachesize_L2 == 128) { add_to_cpuname("Celeron (Mendocino)"); break; } switch (cpu->stepping) { case 0: add_to_cpuname("Celeron-A [mA0]"); break; case 5: add_to_cpuname("Celeron-A [mB0]"); break; case 0xA: add_to_cpuname("Mobile Pentium II [mdA0]"); break; default: add_to_cpuname("Celeron / Mobile Pentium II"); break; } break; case 0x7: cpu->connector = CONN_SLOT_1; switch (cpu->stepping) { case 2: // Core=500 FSB=100 // SL2XU SL3C9 (l2=512) // SL2XV SL3CA (l2=1MB) // SL2XW SL3CB (l2=2MB) add_to_cpuname("Pentium III (Katmai) [kB0]"); break; case 3: // Core=550 FSB=100 // SL3FK SL3D9 SL3AJ SL3Y4 SL3FR SL3LM (l2=512) // SL3DA SL3CE SL3TW SL3LN (l2=1mb) // SL3DB SL3CF SL3LP (l2=2mb) // // Core 500 FSB=100 // SL385 (l2=512) // SL386 (l2=1MB) // SL387 (l2=2MB) add_to_cpuname("Pentium III (Katmai) [kC0]"); break; default: add_to_cpuname("Pentium III/Pentium III Xeon"); break; } decode_serial_number(cpu); break; case 0x8: switch (cpu->brand) { case 2: add_to_cpuname("Pentium III/Pentium III-M (Coppermine)"); switch (cpu->stepping) { case 1: add_to_cpuname(" [cA2]"); break; case 3: add_to_cpuname(" [cB0]"); break; case 6: add_to_cpuname(" [cC0]"); break; case 0xA: add_to_cpuname(" [cD0]"); break; } break; case 3: add_to_cpuname("Pentium III Xeon"); switch (cpu->stepping) { case 1: // l2=256KB FSB=133 // Core=600 SL3BJ SL3BK SL3SS // Core=667 SL3BL SL3DC SL3ST // Core=733 SL3SF SL3SG SL3SU // Core=800 SL3V2 SL3V3 SL3VU add_to_cpuname(" [A2]"); break; case 3: // l2=256 FSB=133 // Core=600 SL3WM SL3WN // Core=667 SL3WP SL3WQ // Core=733 SL3WR SL3WS // Core=800 SL3WT SL3WU // Core=866 SL3WV SL3WW SL4PZ // Core=933 SL3WX SL3WY add_to_cpuname(" [B0]"); break; case 6: // l2=256 FSB=133 // Core=733 SL4H6 SL4H7 // Core=800 SL4H8 SL4H9 // Core=866 SL4HA SL4HB SL4U2 // Core=933 SL4HC SL4HD SL4R9 // Core=1000 SL4HE SL4HF add_to_cpuname(" [C0]"); break; } break; case 8: // cpu->connector = CONN_BGA2; - Could also be Micro-PGA2 add_to_cpuname("Mobile Pentium III"); break; default: cpu->connector = CONN_SOCKET_370_FCPGA; if (cpu->cachesize_L2 == 128) { add_to_cpuname("Celeron"); } else { add_to_cpuname("Pentium III"); } add_to_cpuname(" (Coppermine)"); switch (cpu->stepping) { case 1: add_to_cpuname(" [cA2]"); break; case 3: add_to_cpuname(" [cB0]"); break; case 6: add_to_cpuname(" [cC0]"); break; case 0xA: add_to_cpuname(" [cD0]"); break; } break; } decode_serial_number(cpu); break; case 0x9: // cpu->connector = add_to_cpuname("Pentium M (Banias)"); break; case 0xa: cpu->connector = CONN_SLOT_1; switch (cpu->brand) { case 0: add_to_cpuname("Pentium II (Deschutes)"); break; case 1: add_to_cpuname("Celeron"); break; case 2: add_to_cpuname("Pentium III"); decode_serial_number(cpu); break; case 3: // FSB=100 add_to_cpuname("Pentium III Xeon"); decode_serial_number(cpu); switch (cpu->stepping) { case 0: // Core=700 // L2=1MB SL3U4 SL3U5 SL4GD SL4GE // L2=2MB SL3WZ SL3X2 SL4GF SL4GG add_to_cpuname(" [A0]"); break; case 1: // Core=700 // L2=1MB SL49P SL49Q SL4RZ // L2=2MB SL49R SL49S SL4R3 add_to_cpuname(" [A1]"); break; case 4: // Core=700 // L2=1MB SL4XU SL5D4 SL4XV // L2=2MB SL4XW SL5D5 SL4XX // Core=900 // L2=2MB SL4XY SL4XZ SL5D3 add_to_cpuname(" [B0]"); break; } break; case 4: add_to_cpuname("Pentium III (Cascades)"); decode_serial_number(cpu); break; default: add_to_cpuname("Unknown CPU"); break; } break; case 0xb: switch (cpu->brand) { case 1: case 3: cpu->connector = CONN_SLOT_1; add_to_cpuname("Celeron (Tualatin) [tA1/cA2]"); break; case 6: cpu->connector = CONN_MICROFCBGA; add_to_cpuname("Pentium III-M"); decode_serial_number(cpu); break; default: cpu->connector = CONN_SLOT_1; switch (cpu->stepping) { case 1: add_to_cpuname("Pentium III (Tualatin) [tA1/cA2]"); break; case 4: add_to_cpuname("Pentium III [B-1]"); break; default: add_to_cpuname("Unknown CPU"); break; } decode_serial_number(cpu); break; } break; case 0xd: add_to_cpuname("Pentium M "); cpu->connector = CONN_MICROFCBGA; switch (cpu->stepping) { case 1: add_to_cpuname("(Dothan) [A-1]"); break; case 2: add_to_cpuname("(Dothan) [A-2]"); break; /* S-spec Processor Hi-Freq Low-Freq Number SL7EM 755 2.0GHz 600MHz SL7EL 755 2.0GHz 600MHz SL7EN 745 1.8GHz 600MHz SL7EQ 745 1.8GHz 600MHz SL7EP 735 1.7GHz 600MHz SL7ER 735 1.7GHz 600MHz SL7EG 725 1.6GHz 600MHz SL7F2 725 1.6GHz 600MHz SL7GL 715 1.5GHz 600MHz SL7GK 715 1.5GHz 600MHz SL7VC 738 1.4GHz 600MHz SL7F4 733 1.1GHz 600MHz SL7VD 733 1.1GHz 600MHz SL7V2 723 1.0GHz 600MHz */ case 6: add_to_cpuname("(Dothan) [B-1]"); break; /* FSB=533 2MB L2 90nm SL86G 730 1.6GHz 800MHz SL7SA 740 1.73GHz 800MHz SL7S9 750 1.86GHz 800MHz SL7SM 760 2.0GHz 800MHz SL7SL 770 2.13GHz 800MHz SL7VB 780 2.26GHz 800MHz SL86M 730 1.6GHz 800MHz SL7S8 740 1.73GHz 800MHz SL7SR 750 1.86GHz 800MHz Sl7SQ 760 2.0GHz 800MHz SL7SP 770 2.13GHz 800MHz SL7SN 780 2.26GHz 800MHz SL86B 740 1.73GHz 800MHz SL86A 750 1.86GHz 800MHz SL869 760 2.0GHz 800MHz SL868 770 2.13GHz 800MHz SL8QK 780 2.26GHz 800MHz FSB=400 SL8QF 778 1.6GHz 600MHz SL89X 758 1.5GHz 600MHz SL8A3 723 1.0GHz 600MHz SL8LM 733J 1.1GHz 600MHz SL8A2 733J 1.1GHz 600MHz SL89Z 753 1.2GHz 600MHz SL8LL 753 1.2GHz 600MHz SL8QG 778 1.6GHz 600MHz SL89M 758 1.5GHz 600MHz SL89R 723 1.0GHz 600MHz SL8LT 733J 1.1GHz 600MHz SL89Q 733J 1.1GHz 600MHz SL89P 753 1.2GHz 600MHz SL8LS 753 1.2GHz 600MHz SL89N 738 1.4GHz 600MHz SL89Y 738 1.4GHz 600MHz */ case 8: add_to_cpuname("(Dothan) [C-0]"); cpu->info_url = strdup(pm_90nm_info_url); break; } break; /* * ARGH. Intel made some Core CPUs without setting the efamily or emodel to 1. */ case 0xf: add_to_cpuname("Core 2 "); switch (cpu->stepping) { case 2: /* * 2M Level2 cache * SL9TB L2 E4300 1.8GHz/800Mhz * SLA3F L2 E4400 2GHz/800MHz * SL9TA L2 E6300 1.86GHz/1066MHz * SL9T9 L2 E6400 2.13GHz/1066MHz */ add_to_cpuname("Duo [L2]"); break; case 5: add_to_cpuname("Duo (Conroe XE)"); break; case 6: /* * 2MB L2 cache * - SL9SA B2 E6300 1.86GHz/1066MHz * - SL9S9 B2 E6400 2.13GHz/1066MHz * 4MB L2 cache * - SLA4U B2 E6320 1.86GHz/1066MHz * - SLA4T B2 E6420 2.13GHz/1066MHz * - SL9S8 B2 E6600 2.4GHz/1066MHz * - SL9ZL B2 E6600 2.4GHz/1066MHz * - SL9S7 B2 E6700 2.66GHz/1066MHz * - SL9ZF B2 E6700 2.66GHz/1066MHz * - SLAA5 G0 E6540 2.33GHz/1.333MHz * - SLA9X G0 E6550 2.33GHz/1.333MHz * - SLA9V G0 E6750 2.66GHz/1.333MHz * - SLA9U G0 E6850 3GHz/1.333MHz * - SL9S5 B2 X6800 2.93GHz/1066MHz */ add_to_cpuname("Duo "); switch (cpu->cachesize_L2) { case 2048: add_to_cpuname("[B2]"); if (cpu->MHz/100 == 1860) add_to_cpuname("[SL9SA] E6300"); if (cpu->MHz/100 == 2130) add_to_cpuname("[SL9S9] E6400"); break; case 4096: break; } break; case 7: /* * All quad-core. * SL9UK B3 8MB QX6800 2.93GHz/1066MHz * SL9UL B3 8MB QX6700 2.66GHz/1066MHz * SL9UM B3 8MB QX6600 2.4GHz/1066MHz * SLACP G0 8MB QX6800 2.93GHz/1066MHz */ add_to_cpuname("Quad (Kentsfield) "); switch (cpu->MHz) { case 2930: add_to_cpuname("[SL9UK/SLACP] [B3/G0] QX6800"); break; case 2660: add_to_cpuname("[SL9UL] [B3] QX6700"); break; case 2400: add_to_cpuname("[SL9UM] [B3] QX6600"); break; } break; case 0xa: /* sCode Procname (IDA/HFM) * SLA43 T7700 (2.6GHz/2.4GHz) * SLA3M T7700 (2.6GHz/2.4GHz) * SLA44 T7500 (2.4GHz/2.2GHz) * SLA3N T7500 (2.4GHz/2.2GHz) * SLA45 T7300 (2.4GHz/2.0GHz) * SLA3P T7300 (2.2GHz/2.0GHz) * SLA3R L7500 (1.8GHz/1.6GHz) * SLA3S L7300 (1.6GHz/1.4GHz) * SLA33 X7900 (2.8GHz) * SLA6Z X7800 (2.6GHz) */ add_to_cpuname(" [E1]"); break; case 0xb: /* * SLALT G0 2M E4700 2.6GHz/800MHz * * SLAFN G0 8M QX6850 3GHz/1333MHz * SLACQ G0 8M Q6700 2.66GHz/1066MHz * SLACR G0 8M Q6600 2.4GHz/1066MHz */ if (cpu->cachesize_L2 == 2048) { add_to_cpuname("Duo [G0]"); } else add_to_cpuname("Quad "); break; case 0xd: /* * SLA98 M0 2M E4400 2GHz/800MHz * SLA95 M0 2M E4500 2.2GHz/800MHz * SLA94 M0 2M E4600 2.4GHz/800MHz */ add_to_cpuname("Duo [M0]"); break; } break; default: add_to_cpuname("Unknown model. "); } } Intel/identify.c000066400000000000000000000056651167043552300141320ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel specific parts * * References: * http://developer.intel.com/ * http://microcodes.sourceforge.net/CPUID.htm */ #include #include #include "../x86info.h" #include "Intel.h" static char *intel_nameptr; #define add_to_cpuname(x) intel_nameptr += snprintf(intel_nameptr, sizeof(x), "%s", x) void Identify_Intel(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; intel_nameptr = cpu->name; cpuid(cpu->number, 0x00000001, &eax, &ebx, &ecx, &edx); cpu->emodel = (eax >> 16) & 0xf; cpu->efamily= (eax >> 20) & 0xff; cpu->type = (eax >> 12) & 0x3; cpu->brand = ebx & 0xf; cpu->apicid = ebx >> 24; cpu->nr_logical = (ebx >> 16) & 0xff; cpu->flags_ecx = ecx; // Used for identification of Core 2 cpu->flags_edx = edx; /* Figure out number of cores on this package. */ cpu->nr_cores = 1; if (cpu->cpuid_level >= 4) { cpuid4(cpu->number, 0, &eax, &ebx, &ecx, &edx); if (eax & 0x1f) cpu->nr_cores = ((eax >> 26) + 1); } decode_Intel_caches(cpu, 0); switch (cpu->family) { case 4: add_to_cpuname("i486 "); switch (cpu->model) { case 0: add_to_cpuname("DX-25/33"); break; case 1: add_to_cpuname("DX-50"); break; case 2: add_to_cpuname("SX"); break; case 3: add_to_cpuname("487/DX2"); break; case 4: add_to_cpuname("SL"); break; case 5: add_to_cpuname("SX2"); break; case 7: add_to_cpuname("write-back enhanced DX2"); break; case 8: add_to_cpuname("DX4"); cpu->connector = CONN_SOCKET_3; //transistors = 1600000; //fab_process = "0.6 micron CMOS"; //die_size = "345 sq. mm"; //introduction_date = "March 1994"; break; case 9: add_to_cpuname("write-back enhanced DX4"); cpu->connector = CONN_SOCKET_3; break; } break; case 5: add_to_cpuname("Pentium "); switch (cpu->model) { case 0: add_to_cpuname("A-step"); cpu->connector = CONN_SOCKET_4; break; case 1: add_to_cpuname("60/66"); cpu->connector = CONN_SOCKET_4; break; case 2: add_to_cpuname("75-200"); cpu->connector = CONN_SOCKET_5_7; break; case 3: add_to_cpuname("Overdrive"); cpu->connector = CONN_SOCKET_4; break; case 4: add_to_cpuname("MMX"); cpu->connector = CONN_SOCKET_7; //transistors = 4500000; //fab_process = "0.35 micron CMOS"; //die_size = "140 sq.mm"; //introduction_date = "June 1997"; break; case 7: add_to_cpuname("Mobile"); cpu->connector = CONN_SOCKET_7; break; case 8: add_to_cpuname("MMX Mobile"); cpu->connector = CONN_SOCKET_7; break; } break; case 0x6: if (cpu->emodel == 0) Identify_Intel_family6pentium(cpu); else Identify_Intel_family6core(cpu); intel_nameptr += strlen(cpu->name); // EWW break; case 0x7: add_to_cpuname("Itanium"); break; case 0xF: Identify_Intel_family15(cpu); intel_nameptr += strlen(cpu->name); // EWW break; } } Intel/info.c000066400000000000000000000062711167043552300132440ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel specific parts * * References: * http://developer.intel.com/ * http://microcodes.sourceforge.net/CPUID.htm */ #include #include #include "../x86info.h" #include "Intel.h" /* Decode Pentium III CPU serial number */ void decode_serial_number(struct cpudata *cpu) { char *p = cpu->serialno; unsigned int eax, ebx, ecx, edx; unsigned int signature; if (cpu->cpuid_level < 3) return; cpuid(cpu->number, 1, &eax, NULL, NULL, NULL); signature = eax; cpuid(cpu->number, 3, &eax, &ebx, &ecx, &edx); p += sprintf(p, "%04X", signature >> 16); p += sprintf(p, "-%04X", signature & 0xffff); p += sprintf(p, "-%04X", edx >> 16); p += sprintf(p, "-%04X", edx & 0xffff); p += sprintf(p, "-%04X", ecx >> 16); p += sprintf(p, "-%04X\n", ecx & 0xffff); printf("Processor serial: %s\n", cpu->serialno); } static void decode_brand(struct cpudata *cpu) { printf(")\tBrand: %u (", cpu->brand); switch (cpu->brand) { case 1: case 0xA: case 0x14: printf("Intel® Celeron® processor"); break; case 2: case 4: printf("Intel® Pentium® III processor"); break; case 3: if (tuple(cpu) == 0x6b1) printf("Intel® Celeron® processor"); else printf("Intel® Pentium® III Xeon processor"); break; case 6: printf("Mobile Intel® Pentium® III processor"); break; case 7: case 0xF: case 0x17: printf("Mobile Intel® Celeron® processor"); break; case 8: if (tuple(cpu) >= 0xf13) printf("Intel® genuine processor"); else printf("Intel® Pentium® 4 processor"); break; case 9: printf("Intel® Pentium® 4 processor"); break; case 0xb: if (tuple(cpu) <0xf13) printf("Intel® Xeon processor MP"); else printf("Intel® Xeon processor"); break; case 0xc: printf("Intel® Xeon processor"); break; case 0xe: if (tuple(cpu) <0xf13) printf("Intel® Xeon processor"); else printf("Mobile Intel® Pentium® 4 processor-M"); break; case 0x11: case 0x15: printf("Mobile Genuine Intel® processor"); break; case 0x12: printf("Intel® Celeron® M processor"); break; case 0x13: printf("Mobile Intel® Celeron® processor"); break; case 0x16: printf("Intel® Pentium® M processor"); break; default: printf("unknown"); break; } printf(")\n"); } void display_basic_Intel_info(struct cpudata *cpu) { if (cpu->type != 3) { printf("Type: %u (", cpu->type); switch (cpu->type) { case 0: printf("Original OEM"); break; case 1: printf("Overdrive"); break; case 2: printf("Dual-capable"); break; } printf(")\n"); } if (cpu->brand > 0) decode_brand(cpu); } void display_extended_Intel_info(struct cpudata *cpu) { if (show_msr) { if (cpu->family == 0xf) dump_p4_MSRs(cpu); dump_performance_MSRs(cpu); dump_thermal_MSRs(cpu); // dump_IDA_MSRs(cpu); } if (show_eblcr) { if (cpu->family == 6 && cpu->model >= 3) { unsigned long long eblcr; if (read_msr(cpu->number, 0x2A, &eblcr) == 1) interpret_eblcr(eblcr); } } /* FIXME: Bit test for MCA here!*/ if (show_machine_check) decode_Intel_machine_check(cpu->number, cpu->family); if (show_microcode) decode_microcode(cpu); } Intel/machine_check.c000066400000000000000000000104361167043552300150500ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Dump machine check registers. */ #include #include #include #include "../x86info.h" #include "Intel.h" #define MCG_CAP 0x0179 #define MCG_CTL_PBIT 8 #define MCG_EXT_PBIT 9 #define MCG_STATUS 0x17a #define MCG_CTL 0x17b #define MCG_EXT 0x180 #define MC_CTL 0x0400 #define MC_STATUS 0x0401 #define MC_ADDR 0x402 static int nr_msr_banks; static void decode_mcg_ctl(int cpunum) { unsigned long long val, val2; if (read_msr(cpunum, MCG_CTL, &val) == 1) { printf("MCG_CTL:\n"); printf(" Data cache check %sabled\n", val & (1<<0) ? "en" : "dis"); if ((val & (1<<0)) == 1) { if (read_msr(cpunum, MC_CTL, &val2) == 1) { printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis"); printf(" Data cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis"); printf(" Data cache main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis"); printf(" Data cache snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis"); printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis"); printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis"); } } printf(" Instruction cache check %sabled\n", val & (1<<1) ? "en" : "dis"); if (((val & (1<<1)) == 2) && (nr_msr_banks>1)) { if (read_msr(cpunum, MC_CTL+4, &val2) == 1) { printf(" ECC 1 bit error reporting %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" ECC multi bit error reporting %sabled\n", val2 & (1<<1) ? "en" : "dis"); printf(" Instruction cache data parity %sabled\n", val2 & (1<<2) ? "en" : "dis"); printf(" IC main tag parity %sabled\n", val2 & (1<<3) ? "en" : "dis"); printf(" IC snoop tag parity %sabled\n", val2 & (1<<4) ? "en" : "dis"); printf(" L1 TLB parity %sabled\n", val2 & (1<<5) ? "en" : "dis"); printf(" L2 TLB parity %sabled\n", val2 & (1<<6) ? "en" : "dis"); printf(" Predecode array parity %sabled\n", val2 & (1<<7) ? "en" : "dis"); printf(" Target selector parity %sabled\n", val2 & (1<<8) ? "en" : "dis"); printf(" Read data error %sabled\n", val2 & (1<<9) ? "en" : "dis"); } } printf(" Bus unit check %sabled\n", val & (1<<2) ? "en" : "dis"); if ((val & (1<<2)) == 4 && (nr_msr_banks>2)) { if (read_msr(cpunum, MC_CTL+8, &val2) == 1) { printf(" External L2 tag parity error %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" L2 partial tag parity error %sabled\n", val2 & (1<<1) ? "en" : "dis"); printf(" System ECC TLB reload error %sabled\n", val2 & (1<<2) ? "en" : "dis"); printf(" L2 ECC TLB reload error %sabled\n", val2 & (1<<3) ? "en" : "dis"); printf(" L2 ECC K7 deallocate %sabled\n", val2 & (1<<4) ? "en" : "dis"); printf(" L2 ECC probe deallocate %sabled\n", val2 & (1<<5) ? "en" : "dis"); printf(" System datareaderror reporting %sabled\n", val2 & (1<<6) ? "en" : "dis"); } } printf(" Load/Store unit check %sabled\n", val & (1<<3) ? "en" : "dis"); if ((val & (1<<3)) == 8 && (nr_msr_banks>3)) { if (read_msr(cpunum, MC_CTL+12, &val2) == 1) { printf(" Read data error enable (loads) %sabled\n", val2 & (1<<0) ? "en" : "dis"); printf(" Read data error enable (stores) %sabled\n", val2 & (1<<1) ? "en" : "dis"); } } } printf("\n"); } void decode_Intel_machine_check(int cpunum, int family) { unsigned long long val; int i, extcount = 0; if (!user_is_root) return; if (read_msr(cpunum, MCG_CAP, &val) != 1) return; nr_msr_banks = val & 0xff; printf("Machine check MSRs:\n"); printf("Number of reporting banks : %d\n", nr_msr_banks); if (family == 0xf) { if ((val & (1<> 16) & 0xff; printf("Number of extended MC registers : %d\n\n", extcount); } else printf("Erk, MCG_EXT not present! :%016llx:\n", val); } else if (val & (1< #include #include #include "../x86info.h" #include "Intel.h" void decode_microcode(struct cpudata *cpu) { unsigned long long val = 0; int ver; if (!user_is_root) return; if (cpu->family < 6) return; if (read_msr (cpu->number, MSR_IA32_UCODE_REV, &val) == 1) { ver = val >>32; if (ver>0) printf("Microcode version: 0x%016llx\n", val >>32); printf("\n"); } } Intel/topology.c000066400000000000000000000050711167043552300141620ustar00rootroot00000000000000/* * (C) 2008 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Intel multicore/multithread determination. */ #include #include #include #include "../x86info.h" #include "Intel.h" /** * fls - find last (most-significant) bit set * @x: the word to search * * This is defined the same way as ffs. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ static int fls(int x) { int r = 32; if (!x) return 0; if (!(x & 0xffff0000u)) { x <<= 16; r -= 16; } if (!(x & 0xff000000u)) { x <<= 8; r -= 8; } if (!(x & 0xf0000000u)) { x <<= 4; r -= 4; } if (!(x & 0xc0000000u)) { x <<= 2; r -= 2; } if (!(x & 0x80000000u)) { x <<= 1; r -= 1; } return r; } static int get_count_order(unsigned int count) { int order; order = fls(count) - 1; if (count & (count - 1)) order++; return order; } static int intel_num_cpu_cores(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; if (cpu->cpuid_level < 4) return 1; /* Intel has a non-standard dependency on %ecx for this CPUID level. */ cpuid_count(cpu->number, 4, 0, &eax, &ebx, &ecx, &edx); if (eax & 0x1f) return (eax >> 26) + 1; else return 1; } static int phys_pkg_id(int cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; } void get_intel_topology(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; unsigned int index_msb, core_bits; if (!(cpu->flags_edx & X86_FEATURE_HT)) return; /* if (cpu_has(cpu, X86_FEATURE_CMP_LEGACY)) goto out; if (cpu_has(cpu, X86_FEATURE_XTOPOLOGY)) return; */ cpuid(cpu->number, 1, &eax, &ebx, &ecx, &edx); cpu->num_siblings = (ebx & 0xff0000) >> 16; if (cpu->num_siblings == 1) { if (debug) printf("Hyper-Threading is disabled\n"); goto out; } if (cpu->num_siblings <= 1) goto out; index_msb = get_count_order(cpu->num_siblings); cpu->initial_apicid = (cpuid_ebx(cpu->number, 1) >> 24) & 0xFF; cpu->phys_proc_id = phys_pkg_id(cpu->initial_apicid, index_msb); cpu->x86_max_cores = intel_num_cpu_cores(cpu); cpu->num_siblings = cpu->num_siblings / cpu->x86_max_cores; index_msb = get_count_order(cpu->num_siblings); core_bits = get_count_order(cpu->x86_max_cores); cpu->cpu_core_id = phys_pkg_id(cpu->apicid, index_msb) & ((1 << core_bits) - 1); if (debug == 1) { if ((cpu->x86_max_cores * cpu->num_siblings) > 1) { printf("%s:\n", __func__); printf("\tSiblings: %d\n", cpu->num_siblings); printf("\tPhysical Processor ID: %d\n", cpu->phys_proc_id); printf("\tProcessor Core ID: %d\n", cpu->cpu_core_id); } } out: return; } Makefile000066400000000000000000000044471167043552300125350ustar00rootroot00000000000000VERSION=1.30 CFLAGS = -g -O2 -Werror -Wall -Wshadow -Wextra -Wmissing-declarations -Wdeclaration-after-statement -Wredundant-decls -DVERSION="$(VERSION)" LDFLAGS = -Wl,-z,relro,-z,now CC = gcc SHELL = /bin/sh all: x86info test lsmsr LSMSR_TMP_HEADERS=AMD/k8.h AMD/fam10h.h AMD/fam11h.h AMD/fam12h.h \ AMD/fam14h.h AMD/fam15h.h generic_msr.h %.h: %.regs scripts/createheader.py python scripts/createheader.py $< `basename $< .regs` >$@ LSMSR_SRC = \ lsmsr.c \ cpuid.c \ havecpuid.c LSMSR_OBJS = $(LSMSR_SRC:%.c=%.o) lsmsr.c: $(LSMSR_TMP_HEADERS) lsmsr.o: $(LSMSR_TMP_HEADERS) lsmsr: $(LSMSR_TMP_HEADERS) $(LSMSR_OBJS) $(CC) $(CFLAGS) $(LDFLAGS) -o lsmsr $(LSMSR_OBJS) X86INFO_SRC = \ AMD/identify.c \ AMD/machine_check.c \ AMD/MSR-Athlon.c \ AMD/MSR-K6.c \ AMD/powernow.c \ AMD/dumppsb.c \ AMD/bugs.c \ \ Cyrix/identify.c \ \ Intel/identify.c \ Intel/identify-family6.c \ Intel/identify-family6-extended.c \ Intel/identify-family15.c \ Intel/info.c \ Intel/machine_check.c \ Intel/cachesize.c \ Intel/eblcr.c \ Intel/MSR-P4.c \ Intel/MSR-P6.c \ Intel/MSR-performance.c \ Intel/MSR-thermal.c \ Intel/MSR-IDA.c \ Intel/microcode.c \ Intel/topology.c \ \ Centaur/identify.c \ Centaur/MSR-C3.c \ Centaur/longhaul.c \ Centaur/powersaver.c \ \ NatSemi/identify.c \ \ RiSE/identify.c \ \ SiS/identify.c \ \ x86info.c \ commandline.c \ havecpuid.c \ cpuid.c \ features.c \ identify.c \ rdmsr.c \ binary.c \ mptable.c \ get_model_name.c \ mtrr.c \ apic.c \ connector.c \ topology.c \ \ bench/benchmarks.c \ bench/MHz.c X86INFO_OBJS = $(X86INFO_SRC:%.c=%.o) x86info: $(X86INFO_OBJS) $(CC) $(CFLAGS) $(LDFLAGS) -o x86info $(X86INFO_OBJS) -lpci nodes: scripts/makenodes test: scripts/testnodes release: git repack -a -d git prune-packed git archive --format=tar --prefix=x86info-$(VERSION)/ HEAD | gzip -9 > x86info-$(VERSION).tgz clean: @find . -name "*.o" -exec rm {} \; @find . -name "*~" -exec rm {} \; @rm -f x86info x86info.exe @rm -f lsmsr $(LSMSR_TMP_HEADERS) @rm -f core.* splint: splint +posixlib -badflag -fileextensions -type -nullassign -boolops -showcolumn -sysunrecog -fullinitblock -onlytrans -unrecog -usedef -statictrans -compdestroy -predboolint -predboolothers -D__`uname -m`__ $(X86INFO_SRC) sparse: sparse $(X86INFO_SRC) cscope: cscope -Rb NatSemi/000077500000000000000000000000001167043552300124245ustar00rootroot00000000000000NatSemi/identify.c000066400000000000000000000010061167043552300144000ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * NatSemi specific parts. */ #include #include "../x86info.h" static char *NatSemi_nameptr; #define add_to_cpuname(x) NatSemi_nameptr += snprintf(NatSemi_nameptr, sizeof(x), "%s", x) void identify_natsemi(struct cpudata *cpu) { NatSemi_nameptr = cpu->name; switch (tuple(cpu) & 0xff0) { case 0x540: add_to_cpuname("Geode GX1"); break; default: add_to_cpuname("Unknown CPU"); break; } } README000066400000000000000000000026341167043552300117510ustar00rootroot00000000000000x86info http://www.codemonkey.org.uk/projects/x86info Dave Jones Somewhere in the mists of time, there was a program by Phil Karn (KA9Q) called cpuid, which identified CPU. It didn't get updated very often, and quickly got out of date. It also didn't do much more than just simple decoding. x86info was written to succeed Phils work. Initially, it borrowed some bits from his code, but the last remnants are now long gone. Additional functionality has been added, such as support for SMP, and building on non-Linux platforms. Features: - SMP support. - Recognition of all Intel/AMD/Centaur/Cyrix/VIA CPUs. - Parsing of model specific registers. - Approximation of current CPU MHz. Requirements: * On Linux, at least version 2.4 of glibc is required. * For usage of the MSR / SMP functions, x86info needs the x86 cpuid driver provided with the Linux kernel since 2.2.18 / 2.4.0, and the appropriate nodes in /dev To set up these devices, do the following.. mkdir /dev/cpu for i in 0 1 2 3 4 5 6 7 do mkdir /dev/cpu/$i ; cd /dev/cpu/$i mknod cpuid c 203 $i mknod msr c 202 $i done * If you are using the cpuid / msr drivers built as modules as opposed to built into the kernel, then you should ensure the following is in your /etc/modprobe.conf: alias char-major-202 msr alias char-major-203 cpuid Info on the command line switches can be found in the man page. RiSE/000077500000000000000000000000001167043552300116665ustar00rootroot00000000000000RiSE/identify.c000066400000000000000000000012541167043552300136470ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Rise specific parts. */ #include #include "../x86info.h" static char *rise_nameptr; #define add_to_cpuname(x) rise_nameptr += snprintf(rise_nameptr, sizeof(x), "%s", x) void identify_RiSE(struct cpudata *cpu) { rise_nameptr = cpu->name; switch (tuple(cpu) & 0xff0) { case 0x500: add_to_cpuname("iDragon (0.25um)"); break; case 0x520: add_to_cpuname("iDragon (0.18um)"); break; case 0x580: add_to_cpuname("iDragon II (0.25um)"); break; case 0x590: add_to_cpuname("iDragon II (0.18um)"); break; default: add_to_cpuname("Unknown CPU"); break; } } SiS/000077500000000000000000000000001167043552300115625ustar00rootroot00000000000000SiS/identify.c000066400000000000000000000007441167043552300135460ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Rise specific parts. */ #include #include "../x86info.h" static char *sis_nameptr; #define add_to_cpuname(x) sis_nameptr += snprintf(sis_nameptr, sizeof(x), "%s", x) void identify_sis(struct cpudata *cpu) { sis_nameptr = cpu->name; switch (tuple(cpu)) { case 0x505: add_to_cpuname("SiS55x"); break; default: add_to_cpuname("Unknown CPU"); break; } } TODO000066400000000000000000000022531167043552300115560ustar00rootroot00000000000000higher priority stuff --------------------- - handle error better in mptable. Propagate values up. - feature flag handling code could use more cleanup. - Would be nice to have something similar to the kernels CPU_HAS macros too. - Make intel cache sizing use cpuid(4) where present. - After identifying CPU we can associate more info with the CPU. - CPU codename - Introduction date - number of transistors - voltages (I/O, Core, Maximum) - number of pipelines - Be able to tell the user when we have failed to identify the chip, so they can send us information! - Add some additional tools, rename package to 'x86utils' ? - Report north bridge info (requires pci lib) medium priority stuff --------------------- - introduce hexdump option (-x) to dump register values in addition to decoding. - Some CPUs allow the name string to be changed. If this has happened we die horribly. We need to store the current name string, perform the cpuid reset sequence, and restore the name string on exit. - Fix benchmarking low priority stuff ------------------ - Identify Transmeta CPUs. - Dump cyrix ARR registers when we pass --mtrr - review code for extended natsemi support. apic.c000066400000000000000000000111041167043552300121410ustar00rootroot00000000000000/* * (C) 2011 Andre Nogueira * * Licensed under the terms of the GNU GPL License version 2. * * APIC register dumping. * TODO : decode the registers too. */ #include #include "apic.h" #include "x86info.h" static int fd; static int apic_msr_value(int cpu, int msr, unsigned long long *val) { if (read_msr(cpu, msr, val) == 1) return 1; else return 0; } static void dump_apic_base_msr(int cpu, int msr) { unsigned long long val; int ret; ret = apic_msr_value(cpu, msr, &val); if (ret) printf("0x%016llx\n", val); } static int apic_is_enable(int cpu, int msr) { unsigned long long val; int ret; ret = apic_msr_value(cpu, msr, &val); if (ret) ret = ((int)(val >> 11) & 0x1); return ret; } static unsigned int apic_physical_address(int cpu, int msr) { unsigned long long val; unsigned int apic_phys_addr; int ret; apic_phys_addr = 0; ret = apic_msr_value(cpu, msr, &val); if (ret) apic_phys_addr = ((val >> 12) << 12); return apic_phys_addr; } static unsigned int * mapping_apic_registers(unsigned long addr) { unsigned long offset; void *mapped; if ((fd = open("/dev/mem", O_RDONLY)) == -1) return NULL; offset = PAGE_OFFSET(addr); mapped = mmap(NULL, (APIC_REGISTER_SPACE + offset), PROT_READ, MAP_PRIVATE, fd, (unsigned long) addr - offset); if (mapped != MAP_FAILED) return (unsigned int *) (mapped + offset); else return NULL; } static void unmapping_apic_registers(void *mapped, unsigned int size) { if (munmap(mapped, size) == -1) return; if (close(fd) == -1) return; } static void dump_apic(unsigned int *apic_reg_buffer, unsigned int offset) { printf("0x%08x\n", apic_reg_buffer[ (offset * APIC_REGISTER_ALIGNED_SIZE) ]); } void dump_apics(struct cpudata *cpu) { unsigned int *apic_reg_buffer; unsigned int phys_addr; int i; /** * Verify if apic feature is supported **/ if (!(cpu->flags_edx & (X86_FEATURE_APIC))) return; /** * Verify if apic is enable **/ if (!(apic_is_enable(cpu->number, IA32_APIC_BASE_MSR))) return; phys_addr = apic_physical_address(cpu->number, IA32_APIC_BASE_MSR); /** * Mapping the apic registers **/ apic_reg_buffer = mapping_apic_registers(phys_addr); if (apic_reg_buffer == NULL) return; printf("APIC registers:\n"); printf("APIC MSR Base(0x%02x): : ", IA32_APIC_BASE_MSR); dump_apic_base_msr(cpu->number, IA32_APIC_BASE_MSR); printf("APIC Local ID : "); dump_apic(apic_reg_buffer, APIC_ID); printf("APIC Local Version : "); dump_apic(apic_reg_buffer, APIC_VER); printf("APIC Task Priority : "); dump_apic(apic_reg_buffer, APIC_TPR); printf("APIC Arbitration Priority : "); dump_apic(apic_reg_buffer, APIC_APR); printf("APIC Processor Priority : "); dump_apic(apic_reg_buffer, APIC_PPR); printf("APIC EOI : "); dump_apic(apic_reg_buffer, APIC_EOI); printf("APIC Remote Read : "); dump_apic(apic_reg_buffer, APIC_RRD); printf("APIC Logical Destination : "); dump_apic(apic_reg_buffer, APIC_LDR); printf("APIC Destination Format : "); dump_apic(apic_reg_buffer, APIC_DFR); printf("APIC Spurious Interrupt Vector : "); dump_apic(apic_reg_buffer, APIC_SIVR); for (i = 0 ; i < 8 ; i++) { printf("APIC In-Service (ISR%d) : ", i); dump_apic(apic_reg_buffer, APIC_ISR+i); } for (i = 0 ; i < 8 ; i++) { printf("APIC Trigger Mode (TMR%d) : ", i); dump_apic(apic_reg_buffer, APIC_TMR+i); } for (i = 0 ; i < 8 ; i++) { printf("APIC Interrupt Request (IRR0%d) : ", i); dump_apic(apic_reg_buffer, APIC_IRR+i); } printf("APIC Error Status : "); dump_apic(apic_reg_buffer, APIC_ESR); printf("APIC LVT CMCI : "); dump_apic(apic_reg_buffer, APIC_LVT); printf("APIC Interrupt Command (ICR0) : "); dump_apic(apic_reg_buffer, APIC_ICR0); printf("APIC Interrupt Command (ICR1) : "); dump_apic(apic_reg_buffer, APIC_ICR1); printf("APIC LVT Timer : "); dump_apic(apic_reg_buffer, APIC_LVTT); printf("APIC Thermal Sensor : "); dump_apic(apic_reg_buffer, APIC_LVTTS); printf("APIC LVT Performance Monitoring Counters: "); dump_apic(apic_reg_buffer, APIC_LVTPC); printf("APIC LVT LINT0 : "); dump_apic(apic_reg_buffer, APIC_LVT0); printf("APIC LVT LINT1 : "); dump_apic(apic_reg_buffer, APIC_LVT1); printf("APIC LVT Error : "); dump_apic(apic_reg_buffer, APIC_LVTER); printf("APIC Initial Count (for Timer) : "); dump_apic(apic_reg_buffer, APIC_TICR); printf("APIC Current Count (for Timer) : "); dump_apic(apic_reg_buffer, APIC_TCCR); printf("APIC Divide Configuration (for Timer) : "); dump_apic(apic_reg_buffer, APIC_TDCR); unmapping_apic_registers(apic_reg_buffer, APIC_REGISTER_SPACE); printf("\n"); } apic.h000066400000000000000000000014471167043552300121570ustar00rootroot00000000000000#ifndef _APIC_H #define _APIC_H #define IA32_APIC_BASE_MSR 0x1B #define APIC_REGISTER_SPACE 4096 #define APIC_REGISTER_ALIGNED_SIZE 4 #define PAGE_OFFSET(addr) ((unsigned long)(addr) & (getpagesize() - 1)) enum apic_register_offset { APIC_ID = 0x2, APIC_VER = 0x3, APIC_TPR = 0x8, APIC_APR = 0x9, APIC_PPR = 0xA, APIC_EOI = 0xB, APIC_RRD = 0xC, APIC_LDR = 0xD, APIC_DFR = 0xE, APIC_SIVR = 0xF, APIC_ISR = 0x10, APIC_TMR = 0x18, APIC_IRR = 0x20, APIC_ESR = 0x28, APIC_LVT = 0x2F, APIC_ICR0 = 0x30, APIC_ICR1 = 0x31, APIC_LVTT = 0x32, APIC_LVTTS = 0x33, APIC_LVTPC = 0x34, APIC_LVT0 = 0x35, APIC_LVT1 = 0x36, APIC_LVTER = 0x37, APIC_TICR = 0x38, APIC_TCCR = 0x39, APIC_TDCR = 0x3E, }; #include #include #endif /* _APIC_H */ bench/000077500000000000000000000000001167043552300121435ustar00rootroot00000000000000bench/MHz.c000066400000000000000000000031151167043552300130050ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. */ #include #include #include #include #include #include #include "../x86info.h" #include "bench.h" void display_MHz(struct cpudata *cpu) { if (cpu->MHz < 1000) printf("%uMHz", cpu->MHz); else { int a = (cpu->MHz / 1000); int b = ((cpu->MHz % 1000)/100); int c = (a*1000)+(b*100); printf("%u.%u%uGHz", a, b, (cpu->MHz - c)/10); } } static volatile int nosignal = 0; static void sighandler(int sig __attribute__((unused))) { nosignal = 1; } void estimate_MHz(struct cpudata *cpu) { unsigned long long int cycles[2]; /* gotta be 64 bit */ unsigned int eax, ebx, ecx, edx; unsigned long r; if (cpu->number != 0) { if (all_cpus == 0) { cpu->MHz = firstcpu->MHz; return; } } /* Make sure we have a TSC (and hence RDTSC) */ cpuid(cpu->number, 1, &eax, &ebx, &ecx, &edx); if ((edx & (1<<4)) == 0) { printf("No TSC, MHz calculation cannot be performed.\n"); cpu->MHz = 0; return; } if (signal(SIGALRM, sighandler) == SIG_ERR) { printf("Some kind of signal failure.\n"); return; } cycles[0] = rdtsc(); alarm(1); while (!nosignal) r = r * rand(); nosignal = 0; cycles[1] = rdtsc(); /* Check to see if rdtsc wrapped */ if (cycles[1] < cycles[0]) /* yes we did. */ cpu->MHz = ((-1ULL - cycles[0]) + cycles[1]) / 1000000; else cpu->MHz = (cycles[1] - cycles[0]) / 1000000; if ((cpu->MHz % 50) > 15) cpu->MHz = ((cpu->MHz / 50) * 50) + 50; else cpu->MHz = ((cpu->MHz / 50) * 50); } bench/bench.h000066400000000000000000000006361167043552300134000ustar00rootroot00000000000000static inline unsigned long long int rdtsc(void) { unsigned int low, high; __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)); return ((unsigned long long int)high << 32) | low; } #define NREPS 1000 #define TIME(x,y) \ { \ int i; \ unsigned long bstart, bend; \ bstart = rdtsc(); \ for (i=0; i #include #include #include #include "../x86info.h" #include "bench.h" #ifdef __linux__ #include #endif #include #include void show_benchmarks(struct cpudata *cpu __attribute__((unused))) { int tmp = 0; #ifdef __linux__ TIME(asm volatile("int $0x80" :"=a" (tmp) :"0" (__NR_getppid)), "int 0x80"); #endif TIME(asm volatile("cpuid": : :"ax", "dx", "cx", "bx"), "cpuid"); //TIME(asm volatile("addl $1,0(%esp)"), "addl"); //TIME(asm volatile("lock ; addl $1,0(%esp)"), "locked add"); TIME(asm volatile("bswap %0" : "=r" (tmp) : "0" (tmp)), "bswap"); } bench/syscall.c000066400000000000000000000006461167043552300137670ustar00rootroot00000000000000#include #include #include #include #include #include "../x86info.h" void time_int80h() { int i, ret; unsigned long start, end; if (show_bench != 1) return; start = rdtsc(); for (i = 0; i < 1000000; i++) { asm volatile("call 0xfffff000" :"=a" (ret) :"0" (__NR_getppid)); } end = rdtsc(); printf("%f cycles\n", (end - start) / 1000000.0); } binary.c000066400000000000000000000012501167043552300125120ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Binary output routines. */ #include #include "x86info.h" void binary(unsigned int n, unsigned long value) { unsigned int i; for (i = 0; i < n; i++, value<<=1) (void)putchar( (1<<(n-1) & value) ? '1' : '0' ); (void)putchar('\n'); } void binary32(unsigned long value) { int i; for (i = 0; i < 32; i++,value<<=1) { (void)putchar( (1<<31 & value) ? '1' : '0' ); if (i == 23 || i == 15 || i == 7) (void)putchar(' '); } (void)putchar('\n'); } void binary64(unsigned long long value) { binary32(value>>32); printf(" "); binary32(value); } commandline.c000066400000000000000000000067251167043552300135300ustar00rootroot00000000000000/* * (C) 2011 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. */ #include #include #include #include #include "x86info.h" unsigned int show_apic = 0; unsigned int show_bench = 0; unsigned int show_bios = 0; unsigned int show_machine_check = 0; unsigned int show_bugs = 0; unsigned int show_cacheinfo = 0; unsigned int show_connector = 0; unsigned int show_eblcr = 0; unsigned int show_msr = 0; unsigned int show_microcode = 0; unsigned int show_mtrr = 0; unsigned int show_pm = 0; unsigned int show_cpuid = 0; unsigned int show_urls = 0; unsigned int show_mptable = 0; unsigned int show_feature_flags = 0; unsigned int show_MHz = 0; unsigned int show_addr_sizes = 0; unsigned int all_cpus = 0; unsigned int debug = 0; unsigned int verbose = 0; unsigned int need_root = 0; static void usage(char *programname) { printf("Usage: %s []\n\ -a, --all\n\ --all-cpus\n\ --addr\n\ --apic\n\ --bench\n\ --bios\n\ --bugs\n\ -c, --cache\n\ --connector\n\ --debug\n\ -f, --flags\n\ -mce, --show-machine-check\n\ -mhz, --mhz\n\ --microcode\n\ -mp, --mptable\n\ -m, --msr\n\ --mult\n\ --mtrr\n\ --pm\n\ -r, --registers\n\ -u, --urls\n\ -v, --verbose\n\ \n", programname); exit (0); } void parse_command_line(int argc, char **argv) { char **argp, *arg; for (argp = argv+1; argp <= argv + argc && (arg = *argp); argp++) { if ((!strcmp(arg, "-a") || !strcmp(arg, "--all"))) { if (user_is_root) { show_apic = 1; show_bios = 1; show_msr = 1; show_microcode = 1; need_root = 1; show_mptable =1; show_mtrr = 1; show_machine_check = 1; show_eblcr =1; } show_addr_sizes = 1; show_bugs = 1; show_cacheinfo = 1; show_connector = 1; show_feature_flags = 1; show_MHz = 1; show_pm = 1; show_cpuid = 1; show_urls = 1; } if (!strcmp(arg, "--all-cpus")) all_cpus = 1; if (!strcmp(arg, "--addr")) show_addr_sizes = 1; if (!strcmp(arg, "--apic")) { need_root = 1; show_apic = 1; } if (!strcmp(arg, "--bench")) show_bench = 1; if (!strcmp(arg, "--bios")) { need_root = 1; show_bios = 1; } if (!strcmp(arg, "--bugs")) show_bugs = 1; if ((!strcmp(arg, "-c") || !strcmp(arg, "--cache"))) show_cacheinfo = 1; if (!strcmp(arg, "--connector")) show_connector = 1; if (!strcmp(arg, "--debug")) debug = 1; if ((!strcmp(arg, "-f") || !strcmp(arg, "--flags"))) show_feature_flags = 1; if ((!strcmp(arg, "-m") || !strcmp(arg, "--msr"))) { need_root = 1; show_msr = 1; } if (!strcmp(arg, "--microcode")) { need_root = 1; show_microcode = 1; } if ((!strcmp(arg, "-mhz") || !strcmp(arg, "--mhz"))) show_MHz = 1; if ((!strcmp(arg, "-mp") || !strcmp(arg, "--mptable"))) { need_root = 1; show_mptable = 1; } if (!strcmp(arg, "--mtrr")) { need_root = 1; show_mtrr = 1; } if (!strcmp(arg, "--mult")) { need_root = 1; show_eblcr = 1; } if (!strcmp(arg, "--pm")) show_pm = 1; if ((!strcmp(arg, "-r") || !strcmp(arg, "--raw-cpuid"))) show_cpuid = 1; if ((!strcmp(arg, "-mce") || !strcmp(arg, "--show-machine-check"))) { need_root = 1; show_machine_check = 1; } if ((!strcmp(arg, "-u") || !strcmp(arg, "--urls"))) show_urls = 1; if ((!strcmp(arg, "-v") || !strcmp(arg, "--verbose"))) verbose = 1; if ((!strcmp(arg, "?") || !strcmp(arg, "--help"))) usage(argv[0]); } } connector.c000066400000000000000000000050631167043552300132260ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Decode and print the name of the connector the CPU plugs into. */ #include #include "x86info.h" static struct { enum connector id; const char *name; } connector_strings[] = { /* generic sockets */ {CONN_SOCKET_3, "Socket 3 (PGA socket)"}, {CONN_SOCKET_4, "Socket 4 (273 pin PGA)"}, {CONN_SOCKET_5, "Socket 5 (296 pin PGA socket)"}, {CONN_SOCKET_7, "Socket 7 (321 pin PGA socket)"}, {CONN_SOCKET_370, "Socket 370 (370 Pin PGA)"}, {CONN_SOCKET_370_FCPGA, "Socket 370 (FC-PGA) or (PPGA)"}, /* AMD specific sockets */ {CONN_SOCKET_5_7, "Socket 5/7 (296 Pin PGA)"}, {CONN_SUPER_SOCKET_7, "Super Socket 7 (321 Pin PGA)"}, {CONN_SLOT_A, "Slot A (242 Contact Cartridge)"}, {CONN_SOCKET_A, "Socket A (462 Pin PGA)"}, {CONN_SOCKET_A_OR_SLOT_A, "Socket A or Slot A"}, {CONN_SOCKET_754, "Socket 754"}, {CONN_SOCKET_939, "Socket 939"}, {CONN_SOCKET_940, "Socket 940"}, {CONN_SOCKET_S1G1, "Socket S1g1"}, {CONN_SOCKET_S1G2, "Socket S1g2"}, {CONN_SOCKET_S1G3, "Socket S1g3/S1g4"}, {CONN_SOCKET_F, "Socket F (1207)"}, {CONN_SOCKET_AM2, "Socket AM2"}, {CONN_SOCKET_F_R2, "Socket Fr2 (1207)"}, {CONN_SOCKET_AM3, "Socket AM2r2/AM3"}, {CONN_SOCKET_G34, "Socket G34"}, {CONN_SOCKET_ASB2, "Socket ASB2"}, {CONN_SOCKET_C32, "Socket C32"}, {CONN_SOCKET_FP1, "Socket FP1"}, {CONN_SOCKET_FS1, "Socket FS1"}, {CONN_SOCKET_FM1, "Socket FM1"}, {CONN_SOCKET_FT1, "Socket FT1"}, /* Intel specific sockets */ {CONN_SOCKET_57B, "Socket 5/7 (320 Pin PGA)"}, {CONN_MOBILE_7, "Mobile Module (320 Lead TCP)"}, {CONN_SOCKET_8, "Socket 8 (387 pin Dual Cavity PGA)"}, {CONN_SLOT_1, "Slot 1 (242 Contact Cartridge)"}, {CONN_SLOT_2, "Slot 2 (SEC Cartridge)"}, {CONN_SOCKET_423, "Socket423 (PGA423 Socket)"}, {CONN_SOCKET_478, "Socket478 (PGA478 Socket)"}, {CONN_SOCKET_603, "Socket603 (PGA603 Socket)"}, {CONN_MMC, "Mobile Module Connector (BGA)"}, {CONN_MMC2, "Mobile Module Connector (MMC-2)"}, {CONN_MICROFCBGA, "Micro-FCBGA"}, {CONN_LGA775, "LGA775"}, /* Transmeta specific sockets */ {CONN_BGA474, "474 Pin BGA"}, /* natsemi specific (Geode) */ {CONN_BGA, "BGA"}, /* */ }; static const char * get_connector_name(enum connector id) { int i; for (i = 0; i < ARRAY_SIZE(connector_strings); i++) if (id == connector_strings[i].id) return connector_strings[i].name; return NULL; } void decode_connector(enum connector type) { const char *s; if (type == CONN_UNKNOWN) return; s = get_connector_name(type); if (!s) s = "unknown"; printf("Connector type: %s\n\n", s); } cpuid.c000066400000000000000000000132461167043552300123420ustar00rootroot00000000000000/* * (C) 2000, 2001 Dave Jones. * Fixes by Arjan van de Ven (arjanv@redhat.com) and * Philipp Rumpf (prumpf@mandrakesoft.com) * * Licensed under the terms of the GNU GPL License version 2. * * Routines for retrieving cpuid registers. */ #define _LARGEFILE64_SOURCE #include #include #include #include #include #include #include #include #define __USE_GNU #include #if defined(__FreeBSD__) # include # include #endif #include "x86info.h" /* * sched_* calls weren't stable until 2.3.4 * AFAIK, there's no macro to check for the .4, so we just * check for the next minor version up. (2.4) */ #ifdef __GLIBC__ #if __GLIBC__ < 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ < 4 #error Need at least glibc 2.4 #endif #endif /* returns zero on success */ static int native_cpuid(unsigned int cpunr, unsigned long long idx, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { cpu_set_t set, tmp_set; unsigned int a = 0, b = 0, c = 0, d = 0; int ret; if (eax != NULL) a = *eax; if (ebx != NULL) b = *ebx; if (ecx != NULL) c = *ecx; if (edx != NULL) d = *edx; ret = sched_getaffinity(getpid(), sizeof(set), &set); if (ret) return ret; /* man CPU_SET(3): To duplicate a CPU set, use memcpy(3) */ memcpy(&tmp_set, &set, sizeof(cpu_set_t)); CPU_ZERO(&set); CPU_SET(cpunr, &set); ret = sched_setaffinity(getpid(), sizeof(set), &set); if (ret) return ret; asm("cpuid" : "=a" (a), "=b" (b), "+c" (c), "=d" (d) : "0" ((unsigned int)idx)); if (eax!=NULL) *eax = a; if (ebx!=NULL) *ebx = b; if (ecx!=NULL) *ecx = c; if (edx!=NULL) *edx = d; /* Restore initial sched affinity */ ret = sched_setaffinity(getpid(), sizeof(tmp_set), &tmp_set); if (ret) return ret; return 0; } static const char *NATIVE_CPUID_FAILED_MSG = "WARNING: Native cpuid failed\n"; #if defined(__FreeBSD__) void cpuid(unsigned int CPU_number, unsigned long long idx, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { static int nodriver=0; char cpuname[20]; unsigned char buffer[16]; int fh; cpu_cpuid_args_t args; if (nodriver == 1) { if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx)) printf("%s", NATIVE_CPUID_FAILED_MSG); return; } args.level = idx; /* Ok, use the /dev/CPU interface in preference to the _up code. */ (void)snprintf(cpuname,18, "/dev/cpu%d", CPU_number); fh = open(cpuname, O_RDONLY); if (fh != -1) { if (ioctl(fh, CPU_CPUID, &args) != 0) { perror(cpuname); exit(EXIT_FAILURE); } if (eax!=0) *eax = args.data[0]; if (ebx!=0) *ebx = args.data[1]; if (ecx!=0) *ecx = args.data[2]; if (edx!=0) *edx = args.data[3]; if (close(fh) == -1) { perror("close"); exit(EXIT_FAILURE); } } else { /* Something went wrong, just do UP and hope for the best. */ nodriver = 1; if (nrCPUs != 1) perror(cpuname); if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx)) printf("%s", NATIVE_CPUID_FAILED_MSG); return; } } #else /* !__FreeBSD__ */ /* Kernel CPUID driver's minimum supported read size * (see linux/arch/i386/kernel/cpuid.c) */ #define CPUID_CHUNK_SIZE (16) void cpuid(unsigned int CPU_number, unsigned long long idx, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { static int nodriver=0; char cpuname[20]; unsigned char buffer[CPUID_CHUNK_SIZE]; unsigned int *ptr = (unsigned int *)buffer; int fh; if (eax != NULL) { *eax = (unsigned int) idx; if (*eax == 4) *ecx = idx >> 32; } if (nodriver == 1) { if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx)) printf("%s", NATIVE_CPUID_FAILED_MSG); return; } memset(cpuname, 0, sizeof(cpuname)); #ifdef __sun__ /* Solaris doesn't (yet) have per-CPU interface */ (void)snprintf(cpuname, sizeof(cpuname), "/dev/cpu/self/cpuid"); #else /* Ok, use the /dev/cpu interface in preference to the _up code. */ (void)snprintf(cpuname, sizeof(cpuname), "/dev/cpu/%d/cpuid", CPU_number); #endif fh = open(cpuname, O_RDONLY); if (fh != -1) { #ifndef S_SPLINT_S lseek64(fh, (off64_t)idx, SEEK_CUR); #endif if (read(fh, &buffer[0], CPUID_CHUNK_SIZE) == -1) { perror(cpuname); exit(EXIT_FAILURE); } if (eax!=0) *eax = *ptr; if (ebx!=0) *ebx = *(++ptr); if (ecx!=0) *ecx = *(++ptr); if (edx!=0) *edx = *(++ptr); if (close(fh) == -1) { perror("close"); exit(EXIT_FAILURE); } } else { /* Something went wrong, just do UP and hope for the best. */ nodriver = 1; if (native_cpuid(CPU_number, idx, eax,ebx,ecx,edx)) printf("%s", NATIVE_CPUID_FAILED_MSG); return; } } #endif /* __FreeBSD__ */ void cpuid4(unsigned int CPU_number, unsigned long long idx, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { cpuid(CPU_number, 4 | (idx << 32), eax, ebx, ecx, edx); } /* Some CPUID calls want 'count' to be placed in ecx */ void cpuid_count(unsigned int CPU_number, unsigned int op, int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { *ecx = count; cpuid(CPU_number, op, eax, ebx, ecx, edx); } unsigned int cpuid_ebx(unsigned int CPU_number, unsigned int op) { unsigned int eax, ebx, ecx, edx; cpuid(CPU_number, op, &eax, &ebx, &ecx, &edx); return ebx; } void dump_raw_cpuid(int cpunum, unsigned int begin, unsigned int end) { unsigned int i; unsigned int eax, ebx, ecx, edx; /* Dump all the CPUID results in raw hex */ for (i = begin; i <= end; i++) { cpuid(cpunum, i, &eax, &ebx, &ecx, &edx); printf("eax in: 0x%08x, eax = %08x ebx = %08x ecx = %08x edx = %08x\n", i, eax, ebx, ecx, edx); } printf("\n"); } features.c000066400000000000000000000334521167043552300130550ustar00rootroot00000000000000/* * (C) 2001-2010 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Feature flag decoding. */ #include #include #include #include "x86info.h" static void flag_decode(unsigned long reg, const char * reg_desc, const char *flags[], const char *flags_desc[]) { unsigned int i; for (i = 0; i < 32; i++) { if (reg & (1<number, 0x00000001, &eax, &ebx, &ecx, &edx); cpu->flags_ecx = ecx; cpu->flags_edx = edx; if (cpu->maxei >= 0x80000001) { cpuid(cpu->number, 0x80000001, &eax, &ebx, &ecx, &edx); cpu->eflags_ecx = ecx; cpu->eflags_edx = edx; } } void show_extra_intel_flags(struct cpudata *cpu) { unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; /* CPUID 0x00000006 EAX flags */ const char *intel_cpuid_06_eax_flags[] = { "dts", "ida", "arat", NULL, "pln", "ecmd", "ptm", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; const char *intel_cpuid_06_eax_flags_desc[] = { "Digital temperature sensor supported", // 0 "Intel Dynamic Acceleration Technology (Turbo Boost)", // 1 "Always Running APIC Timer", // 2 NULL, // 3 "Power limit notification controls", // 4 "Clock modulation duty cycle extension", // 5 "Package thermal management", // 6 NULL, // 7 NULL, // 8 NULL, // 9 NULL, // 10 NULL, // 11 NULL, // 12 NULL, // 13 NULL, // 14 NULL, // 15 NULL, // 16 NULL, // 17 NULL, // 18 NULL, // 19 NULL, // 20 NULL, // 21 NULL, // 22 NULL, // 23 NULL, // 24 NULL, // 25 NULL, // 26 NULL, // 27 NULL, // 28 NULL, // 29 NULL, // 30 NULL // 31 }; /* CPUID 0x80000007 EDX flags */ const char *intel_cpuid_80000007_edx_flags[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "nonstop_tsc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; const char *intel_cpuid_80000007_edx_flags_desc[] = { NULL, // 0 NULL, // 1 NULL, // 2 NULL, // 3 NULL, // 4 NULL, // 5 NULL, // 6 NULL, // 7 "Invariant/nonstop/constant TSC", // 8 NULL, // 9 NULL, // 10 NULL, // 11 NULL, // 12 NULL, // 13 NULL, // 14 NULL, // 15 NULL, // 16 NULL, // 17 NULL, // 18 NULL, // 19 NULL, // 20 NULL, // 21 NULL, // 22 NULL, // 23 NULL, // 24 NULL, // 25 NULL, // 26 NULL, // 27 NULL, // 28 NULL, // 29 NULL, // 30 NULL // 31 }; // Intel CPUID 0x06 if (cpu->cpuid_level >= 0x06) { cpuid(cpu->number, 0x06, &eax, &ebx, &ecx, &edx); flag_decode(eax, "6:eax", intel_cpuid_06_eax_flags, intel_cpuid_06_eax_flags_desc); } // Intel CPUID 0x80000007 if (cpu->maxei >= 0x80000007) { cpuid(cpu->number, 0x80000007, &eax, &ebx, &ecx, &edx); flag_decode(edx, "80000007:edx", intel_cpuid_80000007_edx_flags, intel_cpuid_80000007_edx_flags_desc); } } static void decode_feature_flags(struct cpudata *cpu) { unsigned int eax, ebx, ecx, edx; /* CPUID 0x00000001 EDX flags */ const char *generic_cap_flags[] = { "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov", "pat", "pse36", "psn", "clflsh", NULL, "ds", "acpi", "mmx", "fxsr", "sse", "sse2", "ss", "ht", "tm", NULL, "pbe" }; const char *generic_cap_flags_desc[] = { "Onboard FPU", // 0 "Virtual Mode Extensions", // 1 "Debugging Extensions", // 2 "Page Size Extensions", // 3 "Time Stamp Counter", // 4 "Model-Specific Registers", // 5 "Physical Address Extensions", // 6 "Machine Check Exception", // 7 "CMPXCHG8 instruction", // 8 "Onboard APIC", // 9 NULL, // 10 "SYSENTER/SYSEXIT instructions", // 11 "Memory Type Range Registers", // 12 "Page Global Enable", // 13 "Machine Check Architecture", // 14 "CMOV instruction", // 15 "Page Attribute Table", // 16 "36-bit PSEs", // 17 "Processor serial number", /* reserved on AMD */ // 18 "CLFLUSH instruction", // 19 NULL, // 20 "Debug Trace Store", /* reserved on AMD */ // 21 "ACPI via MSR", /* reserved on AMD */ // 22 "MMX support", // 23 "FXSAVE and FXRSTOR instructions", // 24 "SSE support", // 25 "SSE2 support", // 26 "CPU self snoop", /* reserved on AMD */ // 27 "Hyper-Threading", // 28 "Thermal Monitor", /* reserved on AMD */ // 29 NULL, // 30 "Pending Break Enable" /* reserved on AMD */ // 31 }; /* CPUID 0x00000001 ECX flags */ const char *intel_cap_generic_ecx_flags[] = { "sse3", "pclmuldq", "dtes64", "monitor", "ds-cpl", "vmx", "smx", "est", "tm2", "ssse3", "cid", NULL, "fma", "cx16", "xTPR", "pdcm", NULL, "pcid", "dca", "sse4_1", "sse4_2", "x2apic", "movbe", "popcnt", "tsc-deadline", "aes", "xsave", "osxsave", "avx", NULL, NULL, NULL }; const char *intel_cap_generic_ecx_flags_desc[] = { "Streaming SIMD Extensions 3", // 0 "PCLMULDQ Instruction", // 1 "64-Bit Debug Store", // 2 "MONITOR/MWAIT", // 3 "CPL Qualified Debug Store", // 4 "Virtual Machine Extensions", // 5 "Safer Mode Extensions", // 6 "Enhanced Intel SpeedStep Technology", // 7 "Thermal Monitor 2", // 8 "Supplemental Streaming SIMD Extensions 3", // 9 "L1 Context ID", // 10 NULL, // 11 "Fused Multiply Add", // 12 "CMPXCHG16B", // 13 "xTPR Update Control", // 14 "Perfmon and Debug Capability", // 15 NULL, // 16 "Process-context identifiers", // 17 "Direct Cache Access", // 18 "Streaming SIMD Extensions 4.1", // 19 "Streaming SIMD Extensions 4.2", // 20 "Extended xAPIC Support", // 21 "MOVBE Instruction", // 22 "POPCNT Instruction", // 23 "TSC Deadline support", // 24 "AES Instruction", // 25 "XSAVE/XSTOR States", // 26 "OS-Enabled Extended State Management", // 27 "AVX instruction extensions", // 28 NULL, // 29 NULL, // 30 NULL // 31 }; /* CPUID 0x80000001 EDX flags */ const char *intel_cap_extended_edx_flags[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "SYSCALL", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "xd", NULL, NULL, NULL, NULL, NULL, "pdpe1gb", "rdtscp", NULL, "em64t", NULL, NULL, }; const char *intel_cap_extended_edx_flags_desc[] = { NULL, // 0 NULL, // 1 NULL, // 2 NULL, // 3 NULL, // 4 NULL, // 5 NULL, // 6 NULL, // 7 NULL, // 8 NULL, // 9 NULL, // 10 "SYSCALL/SYSRET instructions", // 11 NULL, // 12 NULL, // 13 NULL, // 14 NULL, // 15 NULL, // 16 NULL, // 17 NULL, // 18 NULL, // 19 "Execution Disable Bit", // 20 NULL, // 21 NULL, // 22 NULL, // 23 NULL, // 24 NULL, // 25 "1-GByte pages", // 26 "RDTSCP and IA32_TSC_AUX", // 27 NULL, // 28 "Intel 64 Instruction Set Architecture", // 29 NULL, // 30 NULL // 31 }; /* CPUID 0x80000001 ECX flags */ const char *intel_cap_extended_ecx_flags[] = { "lahf_lm", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; const char *intel_cap_extended_ecx_flags_desc[] = { "LAHF/SAHF available in 64-bit mode", // 0 NULL, // 1 NULL, // 2 NULL, // 3 NULL, // 4 NULL, // 5 NULL, // 6 NULL, // 7 NULL, // 8 NULL, // 9 NULL, // 10 NULL, // 11 NULL, // 12 NULL, // 13 NULL, // 14 NULL, // 15 NULL, // 16 NULL, // 17 NULL, // 18 NULL, // 19 NULL, // 19 NULL, // 20 NULL, // 22 NULL, // 23 NULL, // 24 NULL, // 25 NULL, // 26 NULL, // 27 NULL, // 28 NULL, // 29 NULL, // 30 NULL // 31 }; const char *amd_cap_generic_ecx_flags[] = { "sse3", "pclmulqdq", NULL, "mwait", NULL, NULL, NULL, NULL, NULL, "ssse3", NULL, NULL, "fma", "cmpxchg16b", NULL, NULL, NULL, NULL, NULL, "sse4_1", "sse4_2", NULL, NULL, "popcnt", NULL, "aes", "xsave", "osxsave", "avx", "f16c", NULL, NULL }; const char *amd_cap_generic_ecx_flags_desc[] = { "Streaming SIMD Extensions 3", // 0 NULL, // 1 NULL, // 2 "MONITOR/MWAIT instructions", // 3 NULL, // 4 NULL, // 5 NULL, // 6 NULL, // 7 NULL, // 8 "Supplemental Streaming SIMD Extensions 3", // 9 NULL, // 10 NULL, // 11 NULL, // 12 "CMPXCHG16B instruction", // 13 NULL, // 14 NULL, // 15 NULL, // 16 NULL, // 17 NULL, // 18 "Streaming SIMD Extensions 4.1", // 19 NULL, // 20 NULL, // 22 "POPCNT instruction", // 23 NULL, // 24 NULL, // 25 NULL, // 26 NULL, // 27 NULL, // 28 NULL, // 29 NULL, // 30 NULL // 31 }; const char *amd_cap_extended_edx_flags[] = { "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov", "pat", "pse36", NULL, "mp", "nx", NULL, "mmxext", "mmx", "fxsr", "ffxsr", "page1gb", "rdtscp", NULL, "lm", "3dnowext", "3dnow" }; /* "mp" defined for CPUs prior to AMD family 0xf */ const char *amd_cap_extended_ecx_flags[] = { "lahf/sahf", "CmpLegacy", "svm", "ExtApicSpace", "LockMovCr0", "abm", "sse4a", "misalignsse", "3dnowPref", "osvw", "ibs", "xop", "skinit", "wdt", NULL, "lwp", "fma4", NULL, NULL, "NodeId", NULL, "tbm", "TopoExt", "PerfCtrExtCore", "PerfCtrExtNB", NULL, NULL, NULL, NULL, NULL, NULL, NULL }; const char *centaur_cap_extended_ecx_flags[] = { "sse3", NULL, NULL, NULL, NULL, NULL, NULL, "EPS", "tm2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "mmxext", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "3dnowext", "3dnow" }; const char *centaur_cap_extended_edx_flags[] = { NULL, NULL, "RNGp", "RNGe", NULL, NULL, "ACEp", "ACEe", "ACE2p", "ACE2e", "PHEp", "PHEe", "PMMp", "PMMe", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; const char *transmeta_cap_flags[] = { "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; printf("Feature flags:\n"); flag_decode(cpu->flags_edx, "1:edx", generic_cap_flags, generic_cap_flags_desc); /* Vendor specific extensions. */ switch (cpu->vendor) { case VENDOR_AMD: flag_decode(cpu->flags_ecx, "1:ecx", amd_cap_generic_ecx_flags, amd_cap_generic_ecx_flags_desc); printf("\n"); if (cpu->maxei < 0x80000001) break; printf("Extended feature flags:\n"); flag_decode(cpu->eflags_edx, "80000001:edx", amd_cap_extended_edx_flags, NULL); flag_decode(cpu->eflags_ecx, "80000001:ecx", amd_cap_extended_ecx_flags, NULL); printf("\n"); break; case VENDOR_CENTAUR: printf("\n"); printf("Extended feature flags:\n"); flag_decode(cpu->flags_ecx, "1:ecx", centaur_cap_extended_ecx_flags, NULL); cpuid(cpu->number, 0xc0000000, &eax, &ebx, &ecx, &edx); if (eax >=0xc0000001) { cpuid(cpu->number, 0xc0000001, &eax, &ebx, &ecx, &edx); cpu->flags_edx = edx; flag_decode(cpu->flags_edx, "1:edx", centaur_cap_extended_edx_flags, NULL); } break; case VENDOR_TRANSMETA: printf("\n"); printf("Extended feature flags:\n"); flag_decode(cpu->flags_ecx, "1:ecx", transmeta_cap_flags, NULL); break; case VENDOR_CYRIX: printf("\n"); break; case VENDOR_INTEL: flag_decode(cpu->flags_ecx, "1:ecx", intel_cap_generic_ecx_flags, intel_cap_generic_ecx_flags_desc); printf("\n"); if (cpu->maxei < 0x80000001) break; printf("Extended feature flags:\n"); flag_decode(cpu->eflags_edx, "80000001:edx", intel_cap_extended_edx_flags, intel_cap_extended_edx_flags_desc); flag_decode(cpu->eflags_ecx, "80000001:ecx", intel_cap_extended_ecx_flags, intel_cap_extended_ecx_flags_desc); show_extra_intel_flags(cpu); break; default: /* Unknown CPU manufacturer or no special handling needed */ break; } printf("\n"); } static sigjmp_buf out; static void sigill(__attribute__((__unused__))int sig) { siglongjmp(out, 1); } static void test_longnop(void) { int died; signal(SIGILL, sigill); died = sigsetjmp(out, 1); if (!died) asm volatile(".byte 0x0f,0x1f,0x00 /* nopl 0(%eax) */"); printf("Long NOPs supported: %s\n", died ? "no" : "yes"); } void display_feature_flags(struct cpudata *cpu) { decode_feature_flags(cpu); test_longnop(); printf("\n"); } generic_msr.regs000066400000000000000000000151121167043552300142430ustar00rootroot00000000000000# Author: Andreas Herrmann # # Copyright (C) 2008 Advanced Micro Devices, Inc. # This file contains information from: # "24593 Rev 3.14 - September 2007, AMD64 Technology - AMD64 # Architecture Programmer's Manual Volume 2: System Programming" # and # "The Intel Architecture Software Developer's Manual, Volume 3: # System Programing Guide (Order Number 243192)" # and # "The Intel 64 and IA-32 Architectures Software Developer's Manual: # System Programming Guide Part 1, (Order Number 253668), # System Programming Guide Part 2, (Order Number 253669)" # See scripts/createheader.py for the general format of this register # definitions. {TSC=0x0010;time-stamp counter TSC:64 } {APIC_BASE=0x001b;APIC base address :8 BSC:1 :2 ApicEn:1 ApicBar:36;;20 for 32-bit, 24 for Intel, 28 for AMD K8, 36 for AMD fam10h :16 } {EBL_CR_POWERON=0x002a;cluster ID :16 ClusterID:2 :46 } {MTRRcap=0x00fe;MTRR capabilities MtrrCapVCnt:8 MtrrCapFix:1 :1 MtrrCapWc:1 :53 } {MCG_CAP=0x0179;global MC capabilities Count:8 MCG_CTL_P:1 :55 } {MCG_STAT=0x017a;global MC status RIPV:1 EIPV:1 MCIP:1 :61 } {MCG_CTL=0x017b;global MC control val:64 } {DBG_CTL_MSR=0x01d9;debug control LBR:1 BTF:1 :62 } {LastBranchFromIP=0x01db;last branch from IP LastBranchFromIP:64;;32 bits on Intel } {LastBranchToIP=0x01dc;last branch to IP LastBranchToIP:64;;32 bits on Intel } {LastExceptionFromIP=0x01dd;last exception from IP LastExceptionFromIP:64;;32 bits on Intel } {LastExceptionToIP=0x01de;last exception to IP LastExceptionToIP:64;;32 bits on Intel } {MTRRphysBase0=0x0200;base of variable-size MTRR (0) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask0=0x0201;mask of variable-size MTRR (0) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase1=0x0202;base of variable-size MTRR (1) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask1=0x0203;mask of variable-size MTRR (1) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase2=0x0204;base of variable-size MTRR (2) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask2=0x0205;mask of variable-size MTRR (2) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase3=0x0206;base of variable-size MTRR (3) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask3=0x0207;mask of variable-size MTRR (3) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase4=0x0208;base of variable-size MTRR (4) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask4=0x0209;mask of variable-size MTRR (4) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase5=0x020a;base of variable-size MTRR (5) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask5=0x020b;mask of variable-size MTRR (5) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase6=0x020c;base of variable-size MTRR (6) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask6=0x020d;mask of variable-size MTRR (6) :11 Valid:1 PhysMask:36 :16 } {MTRRphysBase7=0x020e;base of variable-size MTRR (7) MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB :4 PhyBase:36 :16 } {MTRRphysMask7=0x020f;mask of variable-size MTRR (7) :11 Valid:1 PhysMask:36 :16 } {MTRRfix64K_00000=0x0250;fixed range MTRR 0xxxxType:8 1xxxxType:8 2xxxxType:8 3xxxxType:8 4xxxxType:8 5xxxxType:8 6xxxxType:8 7xxxxType:8 } {MTRRfix16K_80000=0x0258;fixed range MTRR 80xxxType:8 84xxxType:8 88xxxType:8 8CxxxType:8 90xxxType:8 94xxxType:8 98xxxType:8 9CxxxType:8 } {MTRRfix16K_A0000=0x0259;fixed range MTRR A0xxxType:8 A4xxxType:8 A8xxxType:8 ACxxxType:8 B0xxxType:8 B4xxxType:8 B8xxxType:8 BCxxxType:8 } {MTRRfix4K_C0000=0x0268;fixed range MTRR C0xxxType:8 C1xxxType:8 C2xxxType:8 C3xxxType:8 C4xxxType:8 C5xxxType:8 C6xxxType:8 C7xxxType:8 } {MTRRfix4K_C8000=0x0269;fixed range MTRR C8xxxType:8 C9xxxType:8 CAxxxType:8 CBxxxType:8 CCxxxType:8 CDxxxType:8 CExxxType:8 CFxxxType:8 } {MTRRfix4K_D0000=0x026a;fixed range MTRR D0xxxType:8 D1xxxType:8 D2xxxType:8 D3xxxType:8 D4xxxType:8 D5xxxType:8 D6xxxType:8 D7xxxType:8 } {MTRRfix4K_D8000=0x026b;fixed range MTRR D8xxxType:8 D9xxxType:8 DAxxxType:8 DBxxxType:8 DCxxxType:8 DDxxxType:8 DExxxType:8 DFxxxType:8 } {MTRRfix4K_E0000=0x026c;fixed range MTRR E0xxxType:8 E1xxxType:8 E2xxxType:8 E3xxxType:8 E4xxxType:8 E5xxxType:8 E6xxxType:8 E7xxxType:8 } {MTRRfix4K_E8000=0x026d;fixed range MTRR E8xxxType:8 E9xxxType:8 EAxxxType:8 EBxxxType:8 ECxxxType:8 EDxxxType:8 EExxxType:8 EFxxxType:8 } {MTRRfix4K_F0000=0x026e;fixed range MTRR F0xxxType:8 F1xxxType:8 F2xxxType:8 F3xxxType:8 F4xxxType:8 F5xxxType:8 F6xxxType:8 F7xxxType:8 } {MTRRfix4K_F8000=0x026f;fixed range MTRR F8xxxType:8 F9xxxType:8 FAxxxType:8 FBxxxType:8 FCxxxType:8 FDxxxType:8 FExxxType:8 FFxxxType:8 } {PAT=0x0277;page attribute table PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC- :5 } {MTRRdefType=0x02ff;MTRR default memory type MemType:8;;just 3 bits for older 32-bit CPUs :2 MtrrDefTypeFixEn:1 MtrrDefTypeEn:1 :52 } {EFER=0xc0000080;extended feature enable SYSCALL:1 :7 LME:1 :1 LMA:1 NXE:1 :52 } # just for newer CPUs, supporting 64-bit {STAR=0xc0000081;SYSCALL target address res:32;;target on AMD64 SysCallSel:16 SysRetSel:16 } # just for newer CPUs, supporting 64-bit {LSTAR=0xc0000082;long mode SYSCALL target address LSTAR:64 } # just for newer CPUs, supporting 64-bit {SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask MASK:32 :32 } {FS_BASE=0xc0000100;FS base FS_BASE:64 } {GS_BASE=0xc0000101;GS base GS_BASE:64 } {KernelGSbase=0xc0000102;kernel GS base KernelGSBase:64 } ### Local Variables: ### ### mode:shell-script ### ### End: ### get_model_name.c000066400000000000000000000141151167043552300141710ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Get CPU name string from cpuid. */ #include #include #include "x86info.h" void get_model_name(struct cpudata *cpu) { unsigned int i, j; unsigned int eax, ebx, ecx, edx; char namestring[49], *cp; if (cpu->maxei < 0x80000004) return; cp = namestring; for (j = 0x80000002; j <= 0x80000004; j++) { cpuid(cpu->number, j, &eax, &ebx, &ecx, &edx); if (eax == 0) return; for (i = 0; i < 4; i++) *cp++ = eax >> (8 * i); for (i = 0; i < 4; i++) *cp++ = ebx >> (8 * i); for (i = 0; i < 4; i++) *cp++ = ecx >> (8 * i); for (i = 0; i < 4; i++) *cp++ = edx >> (8 * i); } cp = namestring; while(*cp == ' ') cp++; /* Broken BIOS? Try to determine the model name ourselves. */ if (strstr(cp, "unknown") != NULL) { unsigned int vendor; cpuid(cpu->number, 0, NULL, &vendor, NULL, NULL); if (vendor == 0x68747541 && cpu->cpuid_level >= 1 && cpu->maxei >= 0x80000001) { /* AMD defined flags */ unsigned int bid, ebid; cpuid(cpu->number, 0x00000001, NULL, &bid, NULL, NULL); bid &= 0xff; cpuid(cpu->number, 0x80000001, NULL, &ebid, NULL, NULL); /* 8BitBrandId == 0, BrandId == non-zero */ if (bid == 0 && ebid != 0) { int BrandTableIndex = (ebid >> 6) & 0x3f; int NN = ebid & 0x3f; /* processor name string table */ int model_number = 0; const char *name = NULL; switch (BrandTableIndex) { case 0x00: name = "AMD Engineering Sample"; break; case 0x04: name = "AMD Athlon(tm) 64 Processor %d00+"; model_number = 'X'; break; case 0x05: name = "AMD Athlon(tm) 64 X2 Dual Core Processor %d00+"; model_number = 'X'; break; case 0x08: name = "Mobile AMD Athlon(tm) 64 Processor %d00+"; model_number = 'X'; break; case 0x09: name = "Mobile AMD Athlon(tm) 64 Processor %d00+"; model_number = 'X'; break; case 0x0A: name = "AMD Turion(tm) 64 Mobile Technology ML-%d"; model_number = 'X'; break; case 0x0B: name = "AMD Turion(tm) 64 Mobile Technology MT-%d"; model_number = 'X'; break; case 0x0C: name = "AMD Opteron(tm) Processor 1%d"; model_number = 'Y'; break; case 0x0D: name = "AMD Opteron(tm) Processor 1%d"; model_number = 'Y'; break; case 0x0E: name = "AMD Opteron(tm) Processor 1%d HE"; model_number = 'Y'; break; case 0x0F: name = "AMD Opteron(tm) Processor 1%d EE"; model_number = 'Y'; break; case 0x10: name = "AMD Opteron(tm) Processor 2%d"; model_number = 'Y'; break; case 0x11: name = "AMD Opteron(tm) Processor 2%d"; model_number = 'Y'; break; case 0x12: name = "AMD Opteron(tm) Processor 2%d HE"; model_number = 'Y'; break; case 0x13: name = "AMD Opteron(tm) Processor 2%d EE"; model_number = 'Y'; break; case 0x14: name = "AMD Opteron(tm) Processor 8%d"; model_number = 'Y'; break; case 0x15: name = "AMD Opteron(tm) Processor 8%d"; model_number = 'Y'; break; case 0x16: name = "AMD Opteron(tm) Processor 8%d HE"; model_number = 'Y'; break; case 0x17: name = "AMD Opteron(tm) Processor 8%d EE"; model_number = 'Y'; break; case 0x18: name = "AMD Athlon(tm) 64 Processor %d00+"; model_number = 'E'; break; case 0x1D: name = "Mobile Athlon(tm) XP-M Processor %d00+"; model_number = 'X'; break; case 0x1E: name = "Mobile Athlon(tm) XP-M Processor %d00+"; model_number = 'X'; break; case 0x20: name = "AMD Athlon(tm) XP Processor %d00+"; model_number = 'X'; break; case 0x21: name = "Mobile AMD Sempron(tm) Processor %d00+"; model_number = 'T'; break; case 0x22: name = "AMD Sempron(tm) Processor %d00+"; model_number = 'T'; break; case 0x23: name = "Mobile AMD Sempron(tm) Processor %d00+"; model_number = 'T'; break; case 0x24: name = "AMD Athlon(tm) 64 FX-%d Processor"; model_number = 'Z'; break; case 0x26: name = "AMD Sempron(tm) Processor %d00+"; model_number = 'T'; break; case 0x29: name = "Dual Core AMD Opteron(tm) Processor 1%d SE"; model_number = 'R'; break; case 0x2A: name = "Dual Core AMD Opteron(tm) Processor 2%d SE"; model_number = 'R'; break; case 0x2B: name = "Dual Core AMD Opteron(tm) Processor 8%d SE"; model_number = 'R'; break; case 0x2C: name = "Dual Core AMD Opteron(tm) Processor 1%d"; model_number = 'R'; break; case 0x2D: name = "Dual Core AMD Opteron(tm) Processor 1%d"; model_number = 'R'; break; case 0x2E: name = "Dual Core AMD Opteron(tm) Processor 1%d HE"; model_number = 'R'; break; case 0x2F: name = "Dual Core AMD Opteron(tm) Processor 1%d EE"; model_number = 'R'; break; case 0x30: name = "Dual Core AMD Opteron(tm) Processor 2%d"; model_number = 'R'; break; case 0x31: name = "Dual Core AMD Opteron(tm) Processor 2%d"; model_number = 'R'; break; case 0x32: name = "Dual Core AMD Opteron(tm) Processor 2%d HE"; model_number = 'R'; break; case 0x33: name = "Dual Core AMD Opteron(tm) Processor 2%d EE"; model_number = 'R'; break; case 0x34: name = "Dual Core AMD Opteron(tm) Processor 8%d"; model_number = 'R'; break; case 0x35: name = "Dual Core AMD Opteron(tm) Processor 8%d"; model_number = 'R'; break; case 0x36: name = "Dual Core AMD Opteron(tm) Processor 8%d HE"; model_number = 'R'; break; case 0x37: name = "Dual Core AMD Opteron(tm) Processor 8%d EE"; model_number = 'R'; break; case 0x38: name = "Dual Core AMD Opteron(tm) Processor 1%d"; model_number = 'R'; break; case 0x39: name = "Dual Core AMD Opteron(tm) Processor 2%d"; model_number = 'R'; break; case 0x3A: name = "Dual Core AMD Opteron(tm) Processor 8%d"; model_number = 'R'; break; default: name = "AMD Processor model unknown"; break; } /* model number calculation */ switch (model_number) { case 'X': model_number = 22 + NN; break; case 'Y': model_number = 38 + (2 * NN); break; case 'Z': model_number = 24 + NN; break; case 'T': model_number = 24 + NN; break; case 'R': model_number = 45 + (5 * NN); break; case 'E': model_number = 9 + NN; break; } cp = namestring; if (model_number) (void)snprintf(cp, sizeof(namestring), "%s %d", name, model_number); else strcpy(cp, name); } } } printf("Processor name string (BIOS programmed): %s\n", cp); } havecpuid.c000066400000000000000000000010321167043552300131740ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. */ #include #include "x86info.h" static int flag_is_changeable_p(unsigned long flag) { unsigned long f1, f2; __asm__ volatile("pushf\n\t" "pushf\n\t" "pop %0\n\t" "mov %0,%1\n\t" "xor %2,%0\n\t" "push %0\n\t" "popf\n\t" "pushf\n\t" "pop %0\n\t" "popf\n\t" : "=&r" (f1), "=&r" (f2) : "ir" (flag)); return ((f1^f2) & flag) != 0; } int HaveCPUID(void) { return flag_is_changeable_p(0x200000); } identify.c000066400000000000000000000051421167043552300130450ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. */ #include #include "x86info.h" void get_cpu_info_basics(struct cpudata *cpu) { unsigned int maxi, maxei, vendor, address_bits; unsigned int eax; cpuid(cpu->number, 0, &maxi, &vendor, NULL, NULL); maxi &= 0xffff; /* The high-order word is non-zero on some Cyrix CPUs */ cpu->cpuid_level = maxi; if (maxi < 1) return; /* Everything that supports cpuid supports these. */ cpuid(cpu->number, 1, &eax, NULL, NULL, NULL); cpu->stepping = eax & 0xf; cpu->model = (eax >> 4) & 0xf; cpu->family = (eax >> 8) & 0xf; cpuid(cpu->number, 0x80000000, &maxei, NULL, NULL, NULL); cpu->maxei = maxei; cpuid(cpu->number, 0xC0000000, &maxei, NULL, NULL, NULL); cpu->maxei2 = maxei; cpuid(cpu->number, 0x80000008,&address_bits, NULL, NULL, NULL); cpu->phyaddr_bits = address_bits & 0xFF; cpu->viraddr_bits = (address_bits >> 8) & 0xFF; switch (vendor) { case 0x756e6547: cpu->vendor = VENDOR_INTEL; break; case 0x68747541: cpu->vendor = VENDOR_AMD; break; case 0x69727943: cpu->vendor = VENDOR_CYRIX; break; case 0x746e6543: cpu->vendor = VENDOR_CENTAUR; break; case 0x646f6547: cpu->vendor = VENDOR_NATSEMI; break; case 0x52697365: case 0x65736952: cpu->vendor = VENDOR_RISE; break; case 0x20536953: cpu->vendor = VENDOR_SIS; break; default: printf("Unknown vendor (%x)\n", vendor); return; } } void identify(struct cpudata *cpu) { switch (cpu->vendor) { case VENDOR_INTEL: Identify_Intel(cpu); break; case VENDOR_AMD: Identify_AMD(cpu); break; case VENDOR_CYRIX: Identify_Cyrix(cpu); break; case VENDOR_CENTAUR: identify_centaur(cpu); break; case VENDOR_NATSEMI: identify_natsemi(cpu); break; case VENDOR_RISE: identify_RiSE(cpu); break; case VENDOR_SIS: identify_sis(cpu); break; case VENDOR_TRANSMETA: case VENDOR_UNKNOWN: break; } } void show_info(struct cpudata *cpu) { if ((cpu->efamily != 0) || (cpu->emodel != 0)) printf("Extended Family: %u Extended Model: %u ", cpu->efamily, cpu->emodel); printf("Family: %u Model: %u Stepping: %u\n", cpu->family, model(cpu), cpu->stepping); if (cpu->vendor == VENDOR_INTEL) display_basic_Intel_info(cpu); printf("CPU Model (x86info's best guess): %s\n", cpu->name); get_model_name(cpu); printf("\n"); switch (cpu->vendor) { case VENDOR_AMD: display_AMD_info(cpu); break; case VENDOR_CYRIX: display_Cyrix_info(cpu); break; case VENDOR_CENTAUR: display_centaur_info(cpu); break; case VENDOR_INTEL: display_extended_Intel_info(cpu); break; default: break; } } lsmsr.8000066400000000000000000000076071167043552300123270ustar00rootroot00000000000000.\" Copyright (C) 2008 Advanced Micro Devices, Inc. '\"! tbl | mmdoc '\"macro stdmacro .nr X .TH lsmsr 8 "July 2008" "x86utils" .SH NAME lsmsr \- show MSR information for x86 CPUs .SH SYNOPSIS .B lsmsr .RB [ \-hv ] .RB [ \-a .RB [ \-c .IR cpu_nr ] .RB [ \-f .IR family ] .RB [ \-l] .RB [ \-r .IR name|address ] .RB [\-V .IR verbosity] .IR [MSR] .SH DESCRIPTION .PP .B lsmsr is a tool to display information for machine specific registers of x86 CPUs. Following CPUs are supported: AMD family 0xf and family 0x10. For Intel and other AMD CPUs just a some common MSRs is supported. .SH OPTIONS .TP .B -a, --all Show information for all MSRs known to the tool for that CPU family. .TP .B -c cpu_nr, --cpu cpu_nr Select CPU (by number) for which MSR information should be displayed (default: 0). .TP .B -f fam, --family fam Specify CPU family. Normally CPU family is auto-detected. You can use this option to disable auto-detection, e.g. for debugging purposes. .TP .B -l, --list Show definition (address, field description) of selected MSR(s). .TP .B -r name|address, --register name|address Specify MSR (by name or address in hex) for which MSR information should be displayed. .TP .B -V num, --verbosity num Select verbosity of output format (between 0 and 4, default: 0) .TP .B -h, --help Print help message and exit. .TP .B -v, --version Display version info and exit. .SH Examples .IP "" 0 Show all MSRs beginning with 'MTRR' and force CPU family to 0x10 .IP "" 2 # lsmsr -l -f 0x10 MTRR MTRRcap : 0x000000fe MTRRphysBase0 : 0x00000200 MTRRphysMask0 : 0x00000201 MTRRphysBase1 : 0x00000202 MTRRphysMask1 : 0x00000203 MTRRphysBase2 : 0x00000204 MTRRphysMask2 : 0x00000205 MTRRphysBase3 : 0x00000206 MTRRphysMask3 : 0x00000207 MTRRphysBase4 : 0x00000208 MTRRphysMask4 : 0x00000209 MTRRphysBase5 : 0x0000020a MTRRphysMask5 : 0x0000020b MTRRphysBase6 : 0x0000020c MTRRphysMask6 : 0x0000020d MTRRphysBase7 : 0x0000020e MTRRphysMask7 : 0x0000020f MTRRfix64K_00000 : 0x00000250 MTRRfix16K_80000 : 0x00000258 MTRRfix16K_A0000 : 0x00000259 MTRRfix4K_C0000 : 0x00000268 MTRRfix4K_C8000 : 0x00000269 MTRRfix4K_D0000 : 0x0000026a MTRRfix4K_D8000 : 0x0000026b MTRRfix4K_E0000 : 0x0000026c MTRRfix4K_E8000 : 0x0000026d MTRRfix4K_F0000 : 0x0000026e MTRRfix4K_F8000 : 0x0000026f MTRRdefType : 0x000002ff .IP ""0 Show 'MTRRcap MSR in verbose one-line mode .IP "" 2 # lsmsr -r MTRRcap -V 1 MTRRcap = 0x0000000000000508 (MtrrCapVCnt=0x8, MtrrCapFix=0x1, MtrrCapWc=0x1) .IP "" 0 Show 'MTRRdefType' in verbose multi-line mode .IP "" 2 # lsmsr -r MTRRdefType -V 3 MTRRdefType = 0x0000000000000c00 MtrrDefMemType=0 MtrrDefTypeFixEn=0x1 MtrrDefTypeEn=0x1 .IP "" 0 Show definition of MSR 0x200 in verbose multi-line mode (including reserved fields) .IP "" 2 # lsmsr -r 0x200 -V 4 -l MTRRphysBase0: 0x00000200 0-7:Type 8-11:res 12-39:PhyBase 40-63:res .IP "" 0 List all known MSRs for family 0xf .IP "" 2 # lsmsr -f 0xf -l -a TSC : 0x00000010; time-stamp counter APIC_BASE : 0x0000001b; APIC base address ... MTRRphysBase0 : 0x00000200; base of variable MTRR (0) MTRRphysMask0 : 0x00000201; mask of variable MTRR (0) MTRRphysBase1 : 0x00000202; base of variable MTRR (1) MTRRphysMask1 : 0x00000203; mask of variable MTRR (1) ... MTRRfix4K_F0000 : 0x0000026e MTRRfix4K_F8000 : 0x0000026f PAT : 0x00000277; page attribute table MTRRdefType : 0x000002ff .SH Author .B lsmsr and this manual page was written by Andreas Herrmann . .PP Permission is granted to copy, distribute and/or modify this document under the terms of the GNU General Public License version 2. .SH REPORTING BUGS Please send bug reports to . lsmsr.c000066400000000000000000000215501167043552300123730ustar00rootroot00000000000000/* * Author: Andreas Herrmann * * Copyright (C) 2008 Advanced Micro Devices, Inc. * * Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2. * See file COPYING for details. */ #define _LARGEFILE64_SOURCE #include #include #include #include #include #include #include #include #include #include #ifndef _GNU_SOURCE #define _GNU_SOURCE #endif #include #include "msr.h" #include "x86info.h" #include "AMD/k8.h" #include "AMD/fam10h.h" #include "AMD/fam11h.h" #include "AMD/fam12h.h" #include "AMD/fam14h.h" #include "AMD/fam15h.h" #include "generic_msr.h" /* Todos: * - add (list and eventually write) support for write-only MSR * - add decoding support for bit fields * - proper check for MSR support * - add support for generic MSRs for non-Intel/AMD CPUs */ #define LSMSR_VERSION "0.816" struct { int fd; int show_all; int list; int verbosity; int cpu; enum vendor vendor; int family; int model; struct reg_spec *msr_table; const char *prog; const char *msr_name; const char *msr_search; uint32_t reg; } g = { .reg = -1, }; /* getopt_long stuff */ static struct option lopts[] = { {"all", no_argument, 0, 'a'}, /* show all MSRs */ {"cpu", required_argument, 0, 'c'}, /* CPU number */ {"family", required_argument, 0, 'f'}, /* CPU family */ {"list", no_argument, 0, 'l'}, /* list known MSRs */ {"register", required_argument, 0, 'r'}, /* register name or address */ {"help", no_argument, 0, 'h'}, /* help */ {"model", required_argument, 0, 'm'}, /* CPU model */ {"version", no_argument, 0, 'v'}, /* version info */ {"verbosity", required_argument, 0, 'V'}, /* verbosity */ {0, 0, 0, 0} }; #define OPTSTRING "ac:C:f:hlm:r:vV:" #define _USAGE "[OPTION] \n" #define _HELP \ " -a, --all show info for all known MSRs\n"\ " -c, --cpu specify CPU for which MSRs are shown (default 0)\n"\ " -f, --family set cpu family to be used\n"\ " -l, --list list info about MSR(s), its addresses and fields\n"\ " -r, --register select register by name or address\n"\ " -h, --help show help\n"\ " -m, --model set cpu model to be used\n"\ " -v, --version show version info\n"\ " -V, --verbosity set verbosity\n"\ " V=1 show all fields of the register\n"\ " V=2 dito and show reserved fields\n"\ " V=3 like V=1 but each field on separate line\n"\ " V=4 dito and show reserved fields\n"\ "\n"\ " Display model specific registers on AMD64 processors.\n"\ " If is given information for all MSRs for which matches the\n"\ " beginning of its name are displayed. Precedence of MSR selection is:\n"\ " \" -r \" overrules \"\" overrules \"-a\".\n"\ "\n" static void usage(void) { fprintf(stderr, "Usage: %s "_USAGE, g.prog); fprintf(stderr, "Try '%s --help' for more information\n", g.prog); exit(1); } static void help(void) { fprintf(stdout, "Usage: %s "_USAGE, g.prog); fprintf(stdout, "Help:\n"_HELP); } static void version(void) { fprintf(stdout, "%s version %s\n", g.prog, LSMSR_VERSION); } static int get_msr_val(unsigned int msr, unsigned long long *val) { off64_t off; int err; *val = 0; off = lseek64(g.fd, (off64_t) msr, SEEK_SET); if (off == (off_t) -1) { perror("invalid MSR"); return 1; } off = read(g.fd, val, 8); err = errno; if (off != 8) { fflush(stdout); fprintf(stderr, "could not read MSR 0x%8.8x (%s): %s\n", msr, get_reg_name(msr, g.msr_table), strerror(err)); return 0; } return 0; } static int open_dev(int cpu) { char s[20]; snprintf(s, sizeof(s), "/dev/cpu/%d/msr", cpu); g.fd = open(s, O_RDONLY); if (g.fd < 0) fprintf(stderr, "could not open device %s: %s\n", s, strerror(errno)); return g.fd; } #define PRINT_MSR(reg, val) \ do { \ print_reg(reg, val, g.list, g.show_all, g.verbosity); \ } while(0) static int _show_msr(struct reg_spec *reg) { unsigned long long val; if (!g.list) if (get_msr_val(reg->address, &val)) return 1; PRINT_MSR(reg, val); return 0; } static int show_matching(const char *name) { int i, t; int n = MSR_MAX_LEN; int ret = 0; t = strlen(name); if (t < n) n = t; g.show_all = 1; for (i = 0; g.msr_table[i].name; i++) { t = strlen(g.msr_table[i].name); if (n < t) t = n; if (t < n) continue; if (strncmp(name, g.msr_table[i].name, t) == 0) if (_show_msr(&(g.msr_table[i]))) { ret = 1; break; } } g.show_all = 0; return ret; } struct vendor_string { enum vendor id; const char *name; } vendor_names[] = { {VENDOR_UNKNOWN, "(unknown)"}, {VENDOR_AMD, "AMD"}, {VENDOR_CENTAUR, "Centaur"}, {VENDOR_CYRIX, "Cyrix"}, {VENDOR_INTEL, "Intel"}, {VENDOR_NATSEMI, "Natsemi"}, {VENDOR_RISE, "Rise"}, {VENDOR_TRANSMETA, "Transmeta"}, {VENDOR_SIS, "SIS"}, }; get_name(vendor, enum vendor, vendor_names); static void set_vendor(void) { unsigned int b; cpuid(g.cpu, 0, NULL, &b, NULL, NULL); switch (b) { case 0x68747541: g.vendor = VENDOR_AMD; break; case 0x756e6547: g.vendor = VENDOR_INTEL; break; case 0x69727943: g.vendor = VENDOR_CYRIX; break; case 0x746e6543: g.vendor = VENDOR_CENTAUR; break; case 0x646f6547: g.vendor = VENDOR_NATSEMI; break; case 0x52697365: case 0x65736952: g.vendor = VENDOR_RISE; break; case 0x20536953: g.vendor = VENDOR_SIS; break; default: g.vendor = VENDOR_UNKNOWN; break; } } static void set_family_model(void) { unsigned int a; cpuid(g.cpu, 0, &a, NULL, NULL, NULL); if (!g.family) { cpuid(g.cpu, 1, &a, NULL, NULL, NULL); g.family = (a >> 8) & 0xf; if (g.family == 0xf) g.family += (a >> 20) & 0xff; } if (!g.model) { cpuid(g.cpu, 1, &a, NULL, NULL, NULL); g.model = (a >> 4) & 0xf; if (g.model == 0xf) g.model |= (a >> 12) & 0xf0; } } static int set_msr_table(void) { int supported = 0; set_vendor(); set_family_model(); if (g.vendor == VENDOR_AMD) { supported = 1; switch (g.family) { case 0x0f: g.msr_table = k8_spec; break; case 0x10: g.msr_table = fam10h_spec; break; case 0x11: g.msr_table = fam11h_spec; break; case 0x12: g.msr_table = fam12h_spec; break; case 0x14: g.msr_table = fam14h_spec; break; case 0x15: g.msr_table = fam15h_spec; break; default: g.msr_table = generic_msr_spec; } } if (g.vendor == VENDOR_INTEL) { supported = 1; g.msr_table = generic_msr_spec; } if (!supported) { fprintf(stdout, "CPU not (yet) supported " "(vendor=\"%s\", family=%d, model=%d)\n", get_vendor_name(g.vendor), g.family, g.model); return 1; } return 0; } struct reg_spec unknown_msr = {0, "unknown", "(at your own risk)", NULL, NULL}; #define OPT_MAX 32 int main(int argc, char *argv[]) { char c; int i, li, ret; struct reg_spec *reg; ret = 1; if((g.prog = rindex(argv[0], '/'))) ++g.prog; else g.prog = argv[0]; if (!HaveCPUID()) { fprintf(stderr, "warning: no cpuid instruction available\n"); fprintf(stdout, "no MSR information available for this CPU\n"); return 0; } while((c = getopt_long(argc, argv, OPTSTRING, lopts, &li)) != -1) { switch (c) { case 'a': g.show_all = 1; break; case 'h': help(); return 0; case 'v': version(); return 0; case 'V': g.verbosity = strtol(optarg, NULL, 10); break; case 'c': g.cpu = strtol(optarg, NULL, 0); break; case 'm': g.model = strtol(optarg, NULL, 0); break; case 'f': g.family = strtol(optarg, NULL, 0); break; case 'l': g.list = 1; break; case 'r': if (isalpha(*optarg)) g.msr_name = optarg; else g.reg = (unsigned int) strtol(optarg, NULL, 16); break; default: usage(); } } if (argc < 2) { usage(); goto out; } if ((optind > -1) && argv[optind]) { if ((argc - optind) != 1) usage(); if (strlen(argv[optind]) >= OPT_MAX) { fprintf(stderr,"error: invalid command line\n"); goto out; } g.msr_search = argv[optind]; } if (set_msr_table()) goto out; if (g.msr_name) { g.reg = get_reg_addr(g.msr_name, g.msr_table); if (g.reg == (uint32_t) -1) { fflush(stdout); fprintf(stderr, "error: unknown register \"%s\"\n", g.msr_name); goto out; } } if (!g.list) if(open_dev(g.cpu) < 0) goto out; if (g.reg != (uint32_t) -1) { reg = get_reg_spec(g.reg, g.msr_table); if (!reg) { fflush(stdout); fprintf(stderr, "warning: unknown MSR %x\n", g.reg); g.verbosity = 0; unknown_msr.address = g.reg; reg = &unknown_msr; } if (_show_msr(reg)) goto out; } else if (g.msr_search) { if (show_matching(g.msr_search)) goto out; } else if (g.show_all) { for (i = 0; g.msr_table[i].name; i++) if (_show_msr(&(g.msr_table[i]))) goto out; } ret = 0; out: if (g.fd >=0) close(g.fd); return ret; } mptable.c000066400000000000000000000237751167043552300126720ustar00rootroot00000000000000/* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * hacked to make it work in userspace Linux by Ingo Molnar, same copyright * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include #include #include #include #include #include #include "mptable.h" #include "x86info.h" typedef unsigned long vm_offset_t; /* EBDA is @ 40:0e in real-mode terms */ #define EBDA_POINTER 0x040e /* location of EBDA pointer */ /* CMOS 'top of mem' is @ 40:13 in real-mode terms */ #define TOPOFMEM_POINTER 0x0413 /* BIOS: base memory size */ #define DEFAULT_TOPOFMEM 0xa0000 #define BIOS_BASE 0xf0000 #define BIOS_BASE2 0xe0000 #define BIOS_SIZE 0x10000 #define ONE_KBYTE 1024 #define GROPE_AREA1 0x80000 #define GROPE_AREA2 0x90000 #define GROPE_SIZE 0x10000 #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 #define MAXPNSTR 132 /* global data */ static int pfd; /* physical /dev/mem fd */ static int busses[16]; static int apics[16]; static int ncpu; static int nbus; static int napic; static int nintr; static int silent; typedef struct TABLE_ENTRY { u8 type; u8 length; char name[32]; } tableEntry; static tableEntry basetableEntryTypes[] = { { 0, 20, "Processor" }, { 1, 8, "Bus" }, { 2, 8, "I/O APIC" }, { 3, 8, "I/O INT" }, { 4, 8, "Local INT" } }; /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; u32 pap; u8 length; u8 spec_rev; u8 checksum; u8 mpfb1; u8 mpfb2; u8 mpfb3; u8 mpfb4; u8 mpfb5; } mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u16 base_table_length; u8 spec_rev; u8 checksum; u8 oem_id[8]; u8 product_id[12]; u32 oem_table_pointer; u16 oem_table_size; u16 entry_count; u32 apic_address; u16 extended_table_length; u8 extended_table_checksum; u8 reserved; } mpcth_t; typedef struct PROCENTRY { u8 type; u8 apicID; u8 apicVersion; u8 cpuFlags; u32 cpuSignature; u32 featureFlags; u32 reserved1; u32 reserved2; } ProcEntry; static void seekEntry(vm_offset_t addr) { if (lseek(pfd, (off_t)addr, SEEK_SET) < 0) { perror("/dev/mem seek"); exit(EXIT_FAILURE); } } static int readEntry(void* entry, int size) { if (read(pfd, entry, size) != size) { perror("readEntry"); return -1; } return 0; } static int readType(void) { unsigned char type; if (read(pfd, &type, sizeof(unsigned char)) != sizeof(unsigned char)) { perror("type read"); exit(EXIT_FAILURE); } if (lseek(pfd, -1, SEEK_CUR) < 0) { perror("type seek"); exit(EXIT_FAILURE); } return (int)type; } static void processorEntry(void) { ProcEntry entry; int t, family, model; /* read it into local memory */ if (readEntry(&entry, sizeof(entry)) < 0) { printf("Error reading processor entry\n"); exit(EXIT_FAILURE); } /* count it */ ++ncpu; if (!silent) { printf("#\t%2d", (int) entry.apicID); printf("\t 0x%2x", (unsigned int) entry.apicVersion); printf("\t %s, %s", (entry.cpuFlags & PROCENTRY_FLAG_BP) ? "BSP" : "AP", (entry.cpuFlags & PROCENTRY_FLAG_EN) ? "usable" : "unusable"); t = (int) entry.cpuSignature; family = (t >> 8) & 0xf; model = (t >> 4) & 0xf; if (family == 0xf) { family += (t >> 20) & 0xff; model += (t >> 12) & 0xf0; } printf("\t %d\t %d\t %d", family, model, t & 0xf); printf("\t 0x%04x\n", entry.featureFlags); } } static int MPConfigTableHeader(u32 pap) { vm_offset_t paddr; mpcth_t cth; int x; int totalSize; int count, c; if (pap == 0) { printf("MP Configuration Table Header MISSING!\n"); return SMP_NO; } /* convert physical address to virtual address */ paddr = (vm_offset_t)pap; /* read in cth structure */ seekEntry(paddr); if(readEntry(&cth, sizeof(cth))) { printf("error reading MP Config table header structure\n"); exit(EXIT_FAILURE); } totalSize = cth.base_table_length - sizeof(struct MPCTH); count = cth.entry_count; /* initialize tables */ for (x = 0; x < 16; ++x) busses[ x ] = apics[ x ] = 0xff; ncpu = 0; nbus = 0; napic = 0; nintr = 0; /* process all the CPUs */ if (!silent) printf("MP Table:\n#\tAPIC ID\tVersion\tState\t\tFamily\tModel\tStep\tFlags\n"); for (c = count; c; c--) { if (readType() == 0) processorEntry(); totalSize -= basetableEntryTypes[ 0 ].length; } if (!silent) printf("\n"); return SMP_YES; } /* * set PHYSICAL address of MP floating pointer structure */ #define NEXT(X) ((X) += 4) static int apic_probe(vm_offset_t* paddr) { unsigned int x; u16 segment; vm_offset_t target; unsigned int buffer[BIOS_SIZE]; const char MP_SIG[]="_MP_"; /* search Extended Bios Data Area, if present */ seekEntry((vm_offset_t)EBDA_POINTER); if (readEntry(&segment, 2)) { printf("error reading EBDA pointer\n"); exit(EXIT_FAILURE); } if (debug) printf("\nEBDA points to: %x\n", segment); if (segment) { /* search EBDA */ target = (vm_offset_t)segment << 4; seekEntry(target); if (debug) printf("EBDA segment ptr: %lx\n", target); if (readEntry(buffer, ONE_KBYTE)) { printf("error reading 1K from %p\n", (void *)target); exit(EXIT_FAILURE); } for (x = 0; x < ONE_KBYTE / 4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { *paddr = (x*4) + target; return 1; } } } /* read CMOS for real top of mem */ seekEntry((vm_offset_t)TOPOFMEM_POINTER); if (readEntry(&segment, 2)) { printf("error reading CMOS for real top of mem (%p)\n", (void *) TOPOFMEM_POINTER); exit(EXIT_FAILURE); } --segment; /* less ONE_KBYTE */ target = segment * 1024; seekEntry(target); if (readEntry(buffer, ONE_KBYTE)) { printf("error reading 1KB from %p\n", (void *)target); exit(EXIT_FAILURE); } for (x = 0; x < ONE_KBYTE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { *paddr = (x*4) + target; return 2; } } /* we don't necessarily believe CMOS, check base of the last 1K of 640K */ if (target != (DEFAULT_TOPOFMEM - 1024)) { target = (DEFAULT_TOPOFMEM - 1024); seekEntry(target); if (readEntry(buffer, ONE_KBYTE)) { printf("error reading DEFAULT_TOPOFMEM - 1024 from %p\n", (void *) target); exit(EXIT_FAILURE); } for (x = 0; x < ONE_KBYTE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { *paddr = (x*4) + target; return 3; } } } /* search the BIOS */ seekEntry(BIOS_BASE); if (readEntry(buffer, BIOS_SIZE)) { printf("error reading BIOS_BASE from %p\n", (void *)BIOS_BASE); exit(EXIT_FAILURE); } for (x = 0; x < BIOS_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { *paddr = (x*4) + BIOS_BASE; return 4; } } /* search the extended BIOS */ seekEntry(BIOS_BASE2); if (readEntry(buffer, BIOS_SIZE)) { printf("error reading BIOS_BASE2 from %p\n", (void *)BIOS_BASE2); exit(EXIT_FAILURE); } for (x = 0; x < BIOS_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { *paddr = (x*4) + BIOS_BASE2; return 4; } } /* search additional memory */ target = GROPE_AREA1; seekEntry(target); if (readEntry(buffer, GROPE_SIZE)) { printf("error reading GROPE_AREA1 from %p\n", (void *)target); exit(EXIT_FAILURE); } for (x = 0; x < GROPE_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { *paddr = (x*4) + GROPE_AREA1; return 5; } } target = GROPE_AREA2; seekEntry(target); if (readEntry(buffer, GROPE_SIZE)) { printf("error reading GROPE_AREA2 from %p\n", (void *)target); exit(EXIT_FAILURE); } for (x = 0; x < GROPE_SIZE/4; NEXT(x)) { if (!strncmp((char *)&buffer[x], MP_SIG, 4)) { *paddr = (x*4) + GROPE_AREA2; return 6; } } *paddr = (vm_offset_t)0; return 0; } int enumerate_cpus(void) { vm_offset_t paddr; mpfps_t mpfps; silent = 1; /* open physical memory for access to MP structures */ if ((pfd = open("/dev/mem", O_RDONLY)) < 0) { fprintf(stderr, "enumerate_cpus(): /dev/mem: %s\n", strerror(errno)); return -1; } /* probe for MP structures */ if (apic_probe(&paddr) <= 0) return 1; /* read in mpfps structure*/ seekEntry(paddr); if (readEntry(&mpfps, sizeof(mpfps_t))) { printf("error reading mpfpsfrom %p\n", (void *)paddr); exit(EXIT_FAILURE); } /* check whether an MP config table exists */ if (!mpfps.mpfb1) if (MPConfigTableHeader(mpfps.pap) == SMP_YES) return ncpu; return 1; } void display_mptable() { vm_offset_t paddr; mpfps_t mpfps; silent = 0; /* open physical memory for access to MP structures */ if ((pfd = open("/dev/mem", O_RDONLY)) < 0) { fprintf(stderr, "%s(): /dev/mem: %s\n", __func__, strerror(errno)); return; } /* probe for MP structures */ if (apic_probe(&paddr) <= 0) return; /* read in mpfps structure*/ seekEntry(paddr); if (readEntry(&mpfps, sizeof(mpfps_t))) { printf("error reading mpfps from %p\n", (void *)paddr); exit(EXIT_FAILURE); } /* parse an MP config table if it exists */ if (!mpfps.mpfb1) (void) MPConfigTableHeader(mpfps.pap); } mptable.h000066400000000000000000000001531167043552300126600ustar00rootroot00000000000000#ifndef _MPTABLE_H #define _MPTABLE_H #define SMP_NO 0 #define SMP_YES 1 void display_mptable(); #endif msr.h000066400000000000000000000051611167043552300120410ustar00rootroot00000000000000/* * Author: Andreas Herrmann * * Copyright (C) 2008 Advanced Micro Devices, Inc. * * Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2. * See file COPYING for details. */ #ifndef _msr_h #define _msr_h #define _RANGE(name, args...) \ unsigned char name##_range[] = { args } #define _NAMES(name, args...) \ const char *name##_spec[] = { args } #define _SPEC(addr, name, desc, prefix) \ {addr, #name, desc, prefix##name##_range, prefix##name##_spec} #define MSR_MAX_LEN 32 struct reg_spec { unsigned int address; const char *name; const char *desc; unsigned char *bits; const char **spec; }; static struct reg_spec *get_reg_spec(uint32_t msr, struct reg_spec *table) { int i; for (i = 0; table[i].name; i++) if (msr == table[i].address) return &(table[i]); return NULL; } static uint32_t get_reg_addr(const char *name, struct reg_spec *table) { int i; for (i = 0; table[i].name; i++) if (strcmp(name, table[i].name) == 0) return table[i].address; return -1; } static const char *get_reg_name(uint32_t reg, struct reg_spec *table) { struct reg_spec *d; const char *s = NULL; d = get_reg_spec(reg, table); if (d) s = d->name; return s; } static void print_reg_bits(struct reg_spec *reg, uint64_t val, uint8_t list, uint8_t verb) { unsigned char *r; const char **d; int i, j, k; int first, any; uint64_t t; const char *s; if (!reg || !reg->bits || !reg->spec) return; any = 0; first = 1; r = reg->bits; d = reg->spec; for (i = 0, j = 0; r[i]; i++, j = k + 1){ k = j + r[i] - 1; if (d[i] == 0) { if (verb == 2 || verb == 4) s = "res"; else /* hide reserved fields */ continue; } else s = d[i]; if (verb > 2) fprintf(stdout, "\n "); else fprintf(stdout, "%s", first ? " (" : ", "); if (list) printf("%d-%d:%s", j, k, s); else { if (r[i] == 64) t = val; else t = (val >> j) & ((1ULL<desc) fprintf(stdout, "%-*s: 0x%8.8x; %s", all ? 20 : 0, reg->name, reg->address, reg->desc); else fprintf(stdout, "%-*s: 0x%8.8x", all ? 20 : 0, reg->name, reg->address); } else fprintf(stdout, "%-*s = 0x%16.16llx", all ? 20 : 0, reg->name, (unsigned long long) val); if (verb) print_reg_bits(reg, val, list, verb); fprintf(stdout, "\n"); } #endif /* _msr_h */ mtrr.c000066400000000000000000000107331167043552300122200ustar00rootroot00000000000000/* * (C) 2002 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * MTRR register dumping. * TODO : decode the registers too. */ #include #include #include "x86info.h" #define IA32_MTRRCAP_SMRR 0x800 #define IA32_MTRRCAP_WC 0x400 #define IA32_MTRRCAP_FIX 0x100 #define IA32_MTRRCAP_VCNT 0xFF #define IA32_MTRR_DEFTYPE_E 0x800 #define IA32_MTRR_DEFTYPE_FE 0x400 #define IA32_MTRR_DEFTYPE_TYPE 0xFF #define IA32_PHYBASE_TYPE 0XFF #define IA32_PHYMASK_VALID 0X800 static unsigned int max_phy_addr = 0; static char * mtrr_types[MTRR_NUM_TYPES] = { "uncacheable", "write-combining", "?", "?", "write-through", "write-protect", "write-back", }; static void decode_address(unsigned long long val) { switch (max_phy_addr) { case 40: printf("0x%07x ", (unsigned int) ((val >> 12) & 0xFFFFFFF)); break; case 36: default: printf("0x%06x ", (unsigned int) ((val >> 12) & 0xFFFFFF)); break; } } static void set_max_phy_addr(struct cpudata *cpu) { unsigned int value; if (!max_phy_addr) { cpuid(cpu->number, 0x80000008,&value, NULL, NULL, NULL); max_phy_addr = (value & 0xFF); } } static int mtrr_value(int cpu, int msr, unsigned long long * val) { if (read_msr(cpu, msr, val) == 1) return 1; else return 0; } static void dump_mtrr(int cpu, int msr) { unsigned long long val=0; if (read_msr(cpu, msr, &val) == 1) printf("0x%016llx\n", val); } static void decode_mtrrcap(int cpu, int msr) { unsigned long long val; int ret; ret = mtrr_value(cpu,msr,&val); if (ret) { printf("0x%016llx ", val); printf("(smrr flag: 0x%01x, ",(unsigned int) (val & IA32_MTRRCAP_SMRR) >> 11 ); printf("wc flag: 0x%01x, ",(unsigned int) (val&IA32_MTRRCAP_WC) >> 10); printf("fix flag: 0x%01x, ",(unsigned int) (val&IA32_MTRRCAP_FIX) >> 8); printf("vcnt field: 0x%02x (%d))\n",(unsigned int) (val&IA32_MTRRCAP_VCNT) , (int) (val&IA32_MTRRCAP_VCNT)); } } static void decode_mtrr_deftype(int cpu, int msr) { unsigned long long val; int ret; ret = mtrr_value(cpu,msr,&val); if (ret) { printf("0x%016llx ", val); printf("(fixed-range flag: 0x%01x, ",(unsigned int) (val&IA32_MTRR_DEFTYPE_FE) >> 10); printf("mtrr flag: 0x%01x, ",(unsigned int) (val&IA32_MTRR_DEFTYPE_E) >> 11); printf("type field: 0x%02x (%s))\n", (unsigned int) (val&IA32_MTRR_DEFTYPE_TYPE) >> 8, mtrr_types[((val&IA32_MTRR_DEFTYPE_TYPE) >> 8)]); } } static void decode_mtrr_physbase(int cpu, int msr) { unsigned long long val; int ret; ret = mtrr_value(cpu,msr,&val); if (ret) { printf("0x%016llx ", val); printf("(physbase field:"); decode_address(val); printf("type field: 0x%02x (%s))\n",(unsigned int) (val&IA32_PHYBASE_TYPE), mtrr_types[((val&IA32_PHYBASE_TYPE))]); } } static void decode_mtrr_physmask(int cpu, int msr) { unsigned long long val; int ret; ret = mtrr_value(cpu,msr,&val); if (ret) { printf("0x%016llx ", val); printf("(physmask field:"); decode_address(val); printf("valid flag: %d)\n",(int) (val&IA32_PHYMASK_VALID)>>11); } } void dump_mtrrs(struct cpudata *cpu) { unsigned long long val = 0; unsigned int i; if (!(cpu->flags_edx & (X86_FEATURE_MTRR))) return; /* * If MTRR registers are not accessible like in some * virtualization systems then return */ if (!read_msr(cpu->number, 0xfe, &val)) return; printf("MTRR registers:\n"); printf("MTRRcap (0xfe): "); decode_mtrrcap(cpu->number, 0xfe); set_max_phy_addr(cpu); for (i = 0; i < 16; i+=2) { printf("MTRRphysBase%u (0x%x): ", i/2, (unsigned int) 0x200+i); decode_mtrr_physbase(cpu->number, 0x200+i); printf("MTRRphysMask%u (0x%x): ", i/2, (unsigned int) 0x201+i); decode_mtrr_physmask(cpu->number, 0x201+i); } printf("MTRRfix64K_00000 (0x250): "); dump_mtrr (cpu->number, 0x250); printf("MTRRfix16K_80000 (0x258): "); dump_mtrr (cpu->number, 0x258); printf("MTRRfix16K_A0000 (0x259): "); dump_mtrr (cpu->number, 0x259); printf("MTRRfix4K_C8000 (0x269): "); dump_mtrr (cpu->number, 0x269); printf("MTRRfix4K_D0000 0x26a: "); dump_mtrr (cpu->number, 0x26a); printf("MTRRfix4K_D8000 0x26b: "); dump_mtrr (cpu->number, 0x26b); printf("MTRRfix4K_E0000 0x26c: "); dump_mtrr (cpu->number, 0x26c); printf("MTRRfix4K_E8000 0x26d: "); dump_mtrr (cpu->number, 0x26d); printf("MTRRfix4K_F0000 0x26e: "); dump_mtrr (cpu->number, 0x26e); printf("MTRRfix4K_F8000 0x26f: "); dump_mtrr (cpu->number, 0x26f); printf("MTRRdefType (0x2ff): "); decode_mtrr_deftype(cpu->number, 0x2ff); printf("\n"); } rdmsr.c000066400000000000000000000050111167043552300123540ustar00rootroot00000000000000/* * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Contributions by Arjan van de Ven & Philipp Rumpf. * * Routines for reading MSRs. */ #define _LARGEFILE64_SOURCE #include #include #include #include #include #include #include "x86info.h" #if defined(__FreeBSD__) # include # include #endif #if defined(__FreeBSD__) int read_msr(int cpu, unsigned int idx, unsigned long long *val) { char cpuname[16]; unsigned char buffer[8]; unsigned long lo, hi; int fh; static int nodriver=0; cpu_msr_args_t args; if (nodriver==1) return 0; (void)snprintf(cpuname, sizeof(cpuname), "/dev/cpu%d", cpu); fh = open(cpuname, O_RDONLY); if (fh==-1) { perror(cpuname); nodriver=1; return 0; } args.msr = idx; if (ioctl(fh, CPU_RDMSR, &args) != 0) { if (close(fh) == -1) { perror("close"); exit(EXIT_FAILURE); } return 0; } *val = args.data; if (close(fh)==-1) { perror("close"); exit(EXIT_FAILURE); } return 1; } #else /* !__FreeBSD__ */ int read_msr(int cpu, unsigned int idx, unsigned long long *val) { char cpuname[16]; unsigned char buffer[8]; unsigned long long lo, hi; int fh; static int nodriver=0; unsigned int *ptr = (unsigned int *) buffer; if (nodriver==1) return 0; (void)snprintf(cpuname, sizeof(cpuname), "/dev/cpu/%d/msr", cpu); fh = open(cpuname, O_RDONLY); if (fh == -1) { perror(cpuname); nodriver=1; return 0; } if (lseek64(fh, (off64_t) idx, SEEK_CUR) == -1) { perror("lseek"); exit(EXIT_FAILURE); } if (fh != -1) { if (read(fh, &buffer[0], 8) != 8) { if (close(fh) == -1) { perror("close"); exit(EXIT_FAILURE); } return 0; } lo = *ptr; hi = *(++ptr); *val = (hi << 32) | lo; } if (close(fh) == -1) { perror("close"); exit(EXIT_FAILURE); } return 1; } #endif /* __FreeBSD__ */ void dumpmsr(int cpu, unsigned int msr, int size) { unsigned long long val=0; if (read_msr(cpu, msr, &val) == 1) { if (size == 32){ printf("MSR: 0x%08x=0x%08lx : ", msr, (unsigned long) val); binary32(val); } if (size == 64) { printf("MSR: 0x%08x=0x%016llx : ", msr, val); binary64(val); } return; } printf("Couldn't read MSR 0x%x\n", msr); } void dumpmsr_bin(int cpu, unsigned int msr, int size) { unsigned long long val=0; if (read_msr(cpu, msr, &val) == 1) { if (size == 32) binary32(val); if (size == 64) binary64(val); return; } printf("Couldn't read MSR 0x%x\n", msr); } results/000077500000000000000000000000001167043552300125655ustar00rootroot00000000000000results/AMD/000077500000000000000000000000001167043552300131665ustar00rootroot00000000000000results/AMD/athlon-model2.txt000066400000000000000000000122551167043552300164010ustar00rootroot00000000000000x86info v1.11. Dave Jones 2001, 2002 Feedback to . Found 1 CPU eax in: 0x00000000, eax = 00000001 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x00000001, eax = 00000621 ebx = 00000000 ecx = 00000000 edx = 0183fbff eax in: 0x80000000, eax = 80000006 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x80000001, eax = 00000721 ebx = 00000000 ecx = 00000000 edx = c1c3fbff eax in: 0x80000002, eax = 20444d41 ebx = 6c687441 ecx = 74286e6f edx = 5020296d eax in: 0x80000003, eax = 65636f72 ebx = 726f7373 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 0408ff08 ebx = ff18ff10 ecx = 40020140 edx = 40020140 eax in: 0x80000006, eax = 00000000 ebx = 41004100 ecx = 02002140 edx = 00000000 31 23 15 7 MSR: 0x0000002a=0x00000000 : 00000000 00000000 00000000 00000000 MSR: 0xc0000080=0x00000000 : 00000000 00000000 00000000 00000000 MSR: 0xc0010010=0x001e0604 : 00000000 00011110 00000110 00000100 MSR: 0xc0010015=0x0a701008 : 00001010 01110000 00010000 00001000 MSR: 0xc001001b=0x16820223 : 00010110 10000010 00000010 00100011 Number of reporting banks : 4 MCG_CTL: Data cache check enabled ECC 1 bit error reporting disabled ECC multi bit error reporting disabled Data cache data parity disabled Data cache main tag parity disabled Data cache snoop tag parity disabled L1 TLB parity disabled L2 TLB parity disabled Instruction cache check enabled ECC 1 bit error reporting enabled ECC multi bit error reporting enabled Instruction cache data parity enabled IC main tag parity enabled IC snoop tag parity enabled L1 TLB parity enabled L2 TLB parity enabled Predecode array parity enabled Target selector parity enabled Read data error enabled Bus unit check enabled External L2 tag parity error enabled L2 partial tag parity error enabled System ECC TLB reload error enabled L2 ECC TLB reload error enabled L2 ECC K7 deallocate enabled L2 ECC probe deallocate enabled System datareaderror reporting enabled Load/Store unit check enabled Read data error enable (loads) enabled Read data error enable (stores) enabled 31 23 15 7 Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 MC0STATUS: 00000000 00000000 00000000 00000000 MC0ADDR: 10001000 01100100 00000101 11110000 MC0MISC: 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 11111111 11111111 11111111 11111111 MC1STATUS: 00000000 00000000 00000000 00000000 MC1ADDR: 11000000 00011111 00110011 10100000 MC1MISC: 00000000 00000000 00000000 00000000 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 01111111 MC2STATUS: 00000000 00000000 00000000 00000000 MC2ADDR: 00111101 10100110 10100101 01000001 MC2MISC: 00111101 10100110 10100101 01000001 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000111 MC3STATUS: 00000000 00000000 00000000 00000000 MC3ADDR: 10111101 01101110 11010100 11101111 MC3MISC: 00000000 00000000 00000000 00000000 Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs MMX support FXSAVE and FXRESTORE instructions Extended feature flags: syscall mmxext 3dnowext 3dnow Instruction TLB: Fully associative. 16 entries. Data TLB: Fully associative. 24 entries. L1 Data cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L1 Instruction cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L2 (on CPU) cache: Size: 512Kb 2-way associative. lines per tag=1 line size=64 bytes. Family: 6 Model: 2 Stepping: 1 [Athlon (0.18um) [A1]] Processor name string: AMD Athlon(tm) Processor Connector type: Slot A (242 Contact Cartridge) MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000fc0000800 MTRRphysBase1 (0x202): 0x0000000030000000 MTRRphysMask1 (0x203): 0x0000000ff0000800 MTRRphysBase2 (0x204): 0x00000000ce000001 MTRRphysMask2 (0x205): 0x0000000ffe000800 MTRRphysBase3 (0x206): 0x00000000d0000001 MTRRphysMask3 (0x207): 0x0000000ff0000800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x1e1e1e1e1e1e1e1e MTRRfix16K_80000 (0x258): 0x1e1e1e1e1e1e1e1e MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x1010101010101010 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x1515151515151515 MTRRfix4K_E8000 0x26d: 0x1515151515151515 MTRRfix4K_F0000 0x26e: 0x1515151515151515 MTRRfix4K_F8000 0x26f: 0x1515151515151515 MTRRdefType (0x2ff): 0x0000000000000c00 800.04 MHz processor (estimate). results/AMD/athlon-xp1700.txt000066400000000000000000000131211167043552300161470ustar00rootroot00000000000000x86info v1.12. Dave Jones 2001, 2002 Feedback to . Found 1 CPU MP Table: # APIC ID Version State Family Model Step Flags # 0 0x11 BSP, usable 6 8 0 0xfbff -------------------------------------------------------------------------- eax in: 0x00000000, eax = 00000001 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x00000001, eax = 00000680 ebx = 00000000 ecx = 00000000 edx = 0383fbff eax in: 0x80000000, eax = 80000008 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x80000001, eax = 00000780 ebx = 00000000 ecx = 00000000 edx = c1c3fbff eax in: 0x80000002, eax = 20444d41 ebx = 6c687441 ecx = 74286e6f edx = 5820296d eax in: 0x80000003, eax = 37312050 ebx = 002b3030 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 0408ff08 ebx = ff20ff10 ecx = 40020140 edx = 40020140 eax in: 0x80000006, eax = 00000000 ebx = 41004100 ecx = 01008140 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000001 eax in: 0x80000008, eax = 00002022 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 8 Stepping: 0 CPU Model : Athlon XP (Thoroughbred)[A0] Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs MMX support FXSAVE and FXRESTORE instructions SSE support Extended feature flags: syscall mmxext 3dnowext 3dnow MSR: 0x0000002a=0x00000000 : 00000000 00000000 00000000 00000000 MSR: 0xc0000080=0x00000000 : 00000000 00000000 00000000 00000000 MSR: 0xc0010010=0x00140604 : 00000000 00010100 00000110 00000100 MSR: 0xc0010015=0x00031008 : 00000000 00000011 00010000 00001000 MSR: 0xc001001b=0x6003d223 : 01100000 00000011 11010010 00100011 Number of reporting banks : 4 MCG_CTL: Data cache check enabled ECC 1 bit error reporting enabled ECC multi bit error reporting enabled Data cache data parity enabled Data cache main tag parity enabled Data cache snoop tag parity enabled L1 TLB parity enabled L2 TLB parity enabled Instruction cache check enabled ECC 1 bit error reporting enabled ECC multi bit error reporting enabled Instruction cache data parity enabled IC main tag parity enabled IC snoop tag parity enabled L1 TLB parity enabled L2 TLB parity enabled Predecode array parity enabled Target selector parity enabled Read data error enabled Bus unit check enabled External L2 tag parity error enabled L2 partial tag parity error enabled System ECC TLB reload error enabled L2 ECC TLB reload error enabled L2 ECC K7 deallocate enabled L2 ECC probe deallocate enabled System datareaderror reporting enabled Load/Store unit check enabled Read data error enable (loads) enabled Read data error enable (stores) enabled 31 23 15 7 Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 01111111 MC0STATUS: 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 MC0MISC: 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 11111111 11111111 11111111 11111111 MC1STATUS: 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00001000 01100000 00000100 MC1MISC: 00000000 00000000 00000000 00000000 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000111 11111111 MC2STATUS: 00000000 00000000 00000000 00000000 MC2ADDR: 00100101 11101010 00001110 10001111 MC2MISC: 00100101 11101010 00001110 10001111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000111 MC3STATUS: 00000000 00000000 00000000 00000000 MC3ADDR: 11111111 11111111 01111111 11111111 MC3MISC: 00000000 00000000 00000000 00000000 Instruction TLB: Fully associative. 16 entries. Data TLB: Fully associative. 32 entries. L1 Data cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L1 Instruction cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L2 (on CPU) cache: Size: 256Kb 8-way associative. lines per tag=1 line size=64 bytes. PowerNOW! Technology information Available features: Temperature sensing diode present. Connector type: Socket A (462 Pin PGA) MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff8000800 MTRRphysBase1 (0x202): 0x00000000d0000001 MTRRphysMask1 (0x203): 0x0000000ff8000800 MTRRphysBase2 (0x204): 0x00000000d8000001 MTRRphysMask2 (0x205): 0x0000000ff8000800 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x00000000d0000001 MTRRphysMask5 (0x20b): 0x0000000ff8000800 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0505050505050505 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 1462.49 MHz processor (estimate). int 0x80: 273 cycles cpuid: 64 cycles locked add: 11 cycles results/AMD/k6.txt000066400000000000000000000030531167043552300142500ustar00rootroot00000000000000x86info v1.11. Dave Jones 2001, 2002 Feedback to . Found 1 CPU eax in: 0x00000000, eax = 00000001 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x00000001, eax = 00000562 ebx = 00000000 ecx = 00000000 edx = 008001bf eax in: 0x80000000, eax = 80000005 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000662 ebx = 00000000 ecx = 00000000 edx = 008005bf eax in: 0x80000002, eax = 2d444d41 ebx = 6d74364b ecx = 202f7720 edx = 746c756d eax in: 0x80000003, eax = 64656d69 ebx = 65206169 ecx = 6e657478 edx = 6e6f6973 eax in: 0x80000004, eax = 00000073 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 00000000 ebx = 02800140 ecx = 20020220 edx = 20020220 Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Machine Check Architecture CMPXCHG8 instruction MMX support Extended feature flags: 31 23 15 7 MSR: 0xc0000082=0x00000021 : 00000000 00000000 00000000 00100001 Write allocate enable limit: 64Mbytes Write allocate 15-16M bytes: enabled Instruction TLB: 1-way associative. 64 entries. Data TLB: 2-way associative. 128 entries. L1 Data cache: Size: 32Kb 2-way associative. lines per tag=2 line size=32 bytes. L1 Instruction cache: Size: 32Kb 2-way associative. lines per tag=2 line size=32 bytes. Family: 5 Model: 6 Stepping: 2 [K6 (0.30 um)] Processor name string: AMD-K6tm w/ multimedia extensions Connector type: Socket 7 (321 pin PGA socket) 233.87 MHz processor (estimate). results/AMD/mobile-athlon-xp.txt000066400000000000000000000151621167043552300171130ustar00rootroot00000000000000x86info v1.12. Dave Jones 2001, 2002 Feedback to . Found 1 CPU -------------------------------------------------------------------------- eax in: 0x00000000, eax = 00000001 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x00000001, eax = 00000680 ebx = 00000000 ecx = 00000000 edx = 0383fbff eax in: 0x80000000, eax = 80000008 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x80000001, eax = 00000780 ebx = 00000000 ecx = 00000000 edx = c1cbfbff eax in: 0x80000002, eax = 69626f4d ebx = 4120656c ecx = 4120444d edx = 6f6c6874 eax in: 0x80000003, eax = 6d74286e ebx = 50582029 ecx = 30363120 edx = 00002b30 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 0408ff08 ebx = ff20ff10 ecx = 40020140 edx = 40020140 eax in: 0x80000006, eax = 00000000 ebx = 41004100 ecx = 01008140 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000007 eax in: 0x80000008, eax = 00002022 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 8 Stepping: 0 CPU Model : Mobile Athlon XP (Thoroughbred)[A0] Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs MMX support FXSAVE and FXRESTORE instructions SSE support Extended feature flags: syscall mp mmxext 3dnowext 3dnow MSR: 0x0000002a=0x00000000 : 00000000 00000000 00000000 00000000 MSR: 0xc0000080=0x00000000 : 00000000 00000000 00000000 00000000 MSR: 0xc0010010=0x00160602 : 00000000 00010110 00000110 00000010 MSR: 0xc0010015=0x06031000 : 00000110 00000011 00010000 00000000 MSR: 0xc001001b=0x60071263 : 01100000 00000111 00010010 01100011 Number of reporting banks : 4 MCG_CTL: Data cache check enabled ECC 1 bit error reporting enabled ECC multi bit error reporting enabled Data cache data parity enabled Data cache main tag parity enabled Data cache snoop tag parity enabled L1 TLB parity enabled L2 TLB parity enabled Instruction cache check enabled ECC 1 bit error reporting enabled ECC multi bit error reporting enabled Instruction cache data parity enabled IC main tag parity enabled IC snoop tag parity enabled L1 TLB parity enabled L2 TLB parity enabled Predecode array parity enabled Target selector parity enabled Read data error enabled Bus unit check enabled External L2 tag parity error enabled L2 partial tag parity error enabled System ECC TLB reload error enabled L2 ECC TLB reload error enabled L2 ECC K7 deallocate enabled L2 ECC probe deallocate enabled System datareaderror reporting enabled Load/Store unit check enabled Read data error enable (loads) enabled Read data error enable (stores) enabled 31 23 15 7 Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 01111111 MC0STATUS: 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 MC0MISC: 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 11111111 11111111 11111111 11111111 MC1STATUS: 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 01000000 00000000 00000000 MC1MISC: 00000000 00000000 00000000 00000000 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000111 11111111 MC2STATUS: 00000000 00000000 00000000 00000000 MC2ADDR: 11111111 11111011 11110111 10001111 MC2MISC: 11111111 11111011 11110111 10001111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000111 MC3STATUS: 00000000 00000000 00000000 00000000 MC3ADDR: 11111111 11111111 11111111 11111111 MC3MISC: 00000000 00000000 00000000 00000000 Instruction TLB: Fully associative. 16 entries. Data TLB: Fully associative. 32 entries. L1 Data cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L1 Instruction cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L2 (on CPU) cache: Size: 256Kb 8-way associative. lines per tag=1 line size=64 bytes. PowerNOW! Technology information Available features: Temperature sensing diode present. Bus divisor control Voltage ID control MSR: 0xc0010041=0x0013090f : 00000000 00000000 00000000 00000000 00000000 00010011 00001001 00001111 MSR: 0xc0010042=0x90909000f060f : 00000000 00001001 00001001 00001001 00000000 00001111 00000110 00001111 FID changes will happen VID changes will happen Current VID multiplier code: 1.550 Current FSB multiplier code: 10.5 Voltage ID codes: Maximum=1.550V Startup=1.550V Currently=1.550V Frequency ID codes: Maximum=10.5x Startup=6.0x Currently=10.5x Decoding BIOS PST tables (maxfid=f, startvid=9) Found PSB header at 0x40158800 Table version: 0x12 Flags: 0x0 (Mobile voltage regulator) Settling Time: 100 microseconds. Has 31 PST tables. (Only dumping ones relevant to this CPU). PST:26 (@0x401589c2) cpuid: 0x780 fsb: 133 maxFID: 0xf startvid: 0x9 num of p states in this table: 5 FID: 0x12 (4.0x [532MHz]) VID: 0x13 (1.200V) FID: 0x4 (5.0x [665MHz]) VID: 0x13 (1.200V) FID: 0x6 (6.0x [798MHz]) VID: 0x13 (1.200V) FID: 0xa (8.0x [1064MHz]) VID: 0xd (1.350V) FID: 0xf (10.5x [1396MHz]) VID: 0x9 (1.550V) Connector type: Socket A (462 Pin PGA) MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff8000800 MTRRphysBase1 (0x202): 0x0000000008000006 MTRRphysMask1 (0x203): 0x0000000ffc000800 MTRRphysBase2 (0x204): 0x000000000c000006 MTRRphysMask2 (0x205): 0x0000000ffe000800 MTRRphysBase3 (0x206): 0x000000000e000006 MTRRphysMask3 (0x207): 0x0000000fff000800 MTRRphysBase4 (0x208): 0x00000000f6fe0001 MTRRphysMask4 (0x209): 0x0000000fffff0800 MTRRphysBase5 (0x20a): 0x00000000f6fc0001 MTRRphysMask5 (0x20b): 0x0000000ffffe0800 MTRRphysBase6 (0x20c): 0x00000000f6f80001 MTRRphysMask6 (0x20d): 0x0000000ffffc0800 MTRRphysBase7 (0x20e): 0x00000000f6f00001 MTRRphysMask7 (0x20f): 0x0000000ffff80800 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0005050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0500000000000000 MTRRfix4K_E0000 0x26c: 0x0505050506060606 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c00 1391.35 MHz processor (estimate). int 0x80: 267 cycles cpuid: 68 cycles addl: 11 cycles locked add: 10 cycles lea 1(%eax),%eax: 11 cycles results/Centaur/000077500000000000000000000000001167043552300141665ustar00rootroot00000000000000results/Centaur/C3-Ezra-T.txt000066400000000000000000000051131167043552300162740ustar00rootroot00000000000000x86info v1.11. Dave Jones 2001, 2002 Feedback to . Found 1 CPU eax in: 0x00000000, eax = 00000001 ebx = 746e6543 ecx = 736c7561 edx = 48727561 eax in: 0x00000001, eax = 00000689 ebx = 00000000 ecx = 00000000 edx = 00803135 eax in: 0x80000000, eax = 80000006 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000689 ebx = 00000000 ecx = 00000000 edx = 80803135 eax in: 0x80000002, eax = 20414956 ebx = 45203343 ecx = 0061727a edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 00000000 ebx = 08800880 ecx = 40040120 edx = 40040120 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 40040120 edx = 00000000 Family: 6 Model: 8 Stepping: 9 [VIA Ezra-T] Processor name string: VIA C3 Ezra Feature flags: fpu de tsc msr cx8 mtrr pge mmx Extended feature flags: 3dnow Instruction TLB: 8-way associative. 128 entries. Data TLB: 8-way associative. 128 entries. L1 Data cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L1 Instruction cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L2 (on CPU) cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. FCR: MSR: 0x00001107=0x867d90d7 : 10000110 01111101 10010000 11010111 Longhaul v3.0 present MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff0000800 MTRRphysBase1 (0x202): 0x0000000000f00000 MTRRphysMask1 (0x203): 0x0000000ffff00800 MTRRphysBase2 (0x204): 0x00000000da000001 MTRRphysMask2 (0x205): 0x0000000ffe000800 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0505050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0404040404040404 MTRRfix4K_F8000 0x26f: 0x0404040404040400 MTRRdefType (0x2ff): 0x0000000000000c00 433.35 MHz processor (estimate). results/Centaur/C3-Ezra.txt000066400000000000000000000061021167043552300160720ustar00rootroot00000000000000x86info v1.11. Dave Jones 2001, 2002 Feedback to . Found 1 CPU eax in: 0x00000000, eax = 00000001 ebx = 746e6543 ecx = 736c7561 edx = 48727561 eax in: 0x00000001, eax = 00000678 ebx = 00000000 ecx = 00000000 edx = 00803135 eax in: 0x80000000, eax = 80000006 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000678 ebx = 00000000 ecx = 00000000 edx = 80803135 eax in: 0x80000002, eax = 20414956 ebx = 61727a45 ecx = 00000000 edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 00000000 ebx = 08800880 ecx = 40040120 edx = 40040120 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 40040120 edx = 00000000 Family: 6 Model: 7 Stepping: 8 [VIA C3 "Ezra"] Processor name string: VIA Ezra Feature flags: Onboard FPU Debugging Extensions Time Stamp Counter Model-Specific Registers CMPXCHG8 instruction Memory Type Range Registers Page Global Enable MMX support Extended feature flags: 3dnow Instruction TLB: 8-way associative. 128 entries. Data TLB: 8-way associative. 128 entries. L1 Data cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L1 Instruction cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L2 cache size errata detected. Using workaround L2 (on CPU) cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. FCR: MSR: 0x00001107=0x963d9097 : 10010110 00111101 10010000 10010111 Longhaul v2.0 present MSR: 0x0000110a=0x24100ef000000f1 : 00000010 01000001 00000000 11101111 00000000 00000000 00000000 11110001 SoftVID support Revision key: 15 SoftBusRatio=0 VRM Rev=VRM 8.5 00000010 01000001 00000000 11101111 MaxMHzBR: 1111 MaximumVID: 01110 MaxMHzFSB: 00 MinMHzBR: 0001 MinimumVID: 0100 MinMHzFSB: 01 MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff0000800 MTRRphysBase1 (0x202): 0x0000000000f00000 MTRRphysMask1 (0x203): 0x0000000ffff00800 MTRRphysBase2 (0x204): 0x00000000da000001 MTRRphysMask2 (0x205): 0x0000000ffe000800 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0505050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0404040404040404 MTRRfix4K_F8000 0x26f: 0x0404040404040400 MTRRdefType (0x2ff): 0x0000000000000c00 866.71 MHz processor (estimate). results/Centaur/C3-Nehemiah-ES1.txt000066400000000000000000000065721167043552300173100ustar00rootroot00000000000000x86info v1.12. Dave Jones 2001-2003 Feedback to . Found 1 CPU -------------------------------------------------------------------------- eax in: 0x00000000, eax = 00000001 ebx = 746e6543 ecx = 736c7561 edx = 48727561 eax in: 0x00000001, eax = 00000691 ebx = 00000000 ecx = 00000000 edx = 0380b135 eax in: 0x80000000, eax = 80000009 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000691 ebx = 00000000 ecx = 00000000 edx = 1380b135 eax in: 0x80000002, eax = 20414956 ebx = 6568654e ecx = 6861696d edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 00000000 ebx = 08800880 ecx = 40040120 edx = 40040120 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 00410120 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000008, eax = 00002020 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000009, eax = 024a8000 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 9 Stepping: 1 CPU Model : VIA C3 (Nehemiah) [C5XL] Feature flags: Onboard FPU Debugging Extensions Time Stamp Counter Model-Specific Registers CMPXCHG8 instruction Memory Type Range Registers Page Global Enable CMOV instruction MMX support FXSAVE and FXRESTORE instructions SSE support Extended feature flags: Instruction TLB: 8-way associative. 128 entries. Data TLB: 8-way associative. 128 entries. L1 Data cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L1 Instruction cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L2 (on CPU) cache: Size: 65Kb 0-way associative. lines per tag=1 line size=32 bytes. FCR: MSR: 0x00001107=0x8c7c10d2 : 10001100 01111100 00010000 11010010 Power management: Powersaver v1.0 MSR: 0x0000110a=0x7ff000d000080f0 : 00000111 11111111 00000000 00001101 00000000 00000000 10000000 11110000 RevisionID: 0 : Unknown. Software clock multiplier is disabled MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff8000800 MTRRphysBase1 (0x202): 0x0000000007800000 MTRRphysMask1 (0x203): 0x0000000fff800800 MTRRphysBase2 (0x204): 0x00000000e0000001 MTRRphysMask2 (0x205): 0x0000000ffc000800 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 1002.29 MHz processor (estimate). int 0x80: 355 cycles cpuid: 100 cycles addl: 29 cycles locked add: 36 cycles lea 1(%eax),%eax: 29 cycles bswap: 31 cycles results/Centaur/C3-Nehemiah-ES2.txt000066400000000000000000000065011167043552300173010ustar00rootroot00000000000000x86info v1.12. Dave Jones 2001-2003 Feedback to . Found 1 CPU -------------------------------------------------------------------------- eax in: 0x00000000, eax = 00000001 ebx = 746e6543 ecx = 736c7561 edx = 48727561 eax in: 0x00000001, eax = 00000693 ebx = 00000000 ecx = 00000000 edx = 0380b13d eax in: 0x80000000, eax = 80000006 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000002, eax = 20414956 ebx = 6568654e ecx = 6861696d edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 00000000 ebx = 08800880 ecx = 40040120 edx = 40040120 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 00408120 edx = 00000000 eax in: 0xc0000000, eax = c0000001 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0xc0000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 0000001d Family: 6 Model: 9 Stepping: 3 CPU Model : VIA C3 (Nehemiah) [C5XL] Feature flags: Onboard FPU Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers CMPXCHG8 instruction Memory Type Range Registers Page Global Enable CMOV instruction MMX support FXSAVE and FXRESTORE instructions SSE support Extended feature flags: Instruction TLB: 8-way associative. 128 entries. Data TLB: 8-way associative. 128 entries. L1 Data cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L1 Instruction cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L2 (on CPU) cache: Size: 64Kb 8-way associative. lines per tag=1 line size=32 bytes. FCR: MSR: 0x00001107=0x8ebf10d6 : 10001110 10111111 00010000 11010110 Power management: Powersaver v1.0 MSR: 0x0000110a=0x7ff000d000080f0 : 00000111 11111111 00000000 00001101 00000000 00000000 10000000 11110000 RevisionID: 0 : Unknown. Software clock multiplier is disabled MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff8000800 MTRRphysBase1 (0x202): 0x0000000007800000 MTRRphysMask1 (0x203): 0x0000000fff800800 MTRRphysBase2 (0x204): 0x00000000e0000001 MTRRphysMask2 (0x205): 0x0000000ffc000800 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 1002.29 MHz processor (estimate). int 0x80: 355 cycles cpuid: 109 cycles addl: 29 cycles locked add: 36 cycles lea 1(%eax),%eax: 29 cycles bswap: 31 cycles results/Centaur/C7-Esther.txt000066400000000000000000000066671167043552300164470ustar00rootroot00000000000000x86info v1.18. Dave Jones 2001-2006 Feedback to . Found 1 CPU MP Table: # APIC ID Version State Family Model Step Flags # 0 0x11 BSP, usable 6 10 9 0xfbff -------------------------------------------------------------------------- eax in: 0x00000000, eax = 00000001 ebx = 746e6543 ecx = 736c7561 edx = 48727561 eax in: 0x00000001, eax = 000006a9 ebx = 00010800 ecx = 00000081 edx = 87c9bbff eax in: 0x80000000, eax = 80000006 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00100000 eax in: 0x80000002, eax = 20202020 ebx = 20202020 ecx = 20202020 edx = 20202020 eax in: 0x80000003, eax = 56202020 ebx = 45204149 ecx = 65687473 edx = 72702072 eax in: 0x80000004, eax = 7365636f ebx = 20726f73 ecx = 30303531 edx = 007a484d eax in: 0x80000005, eax = 00000000 ebx = 08800880 ecx = 40040140 edx = 40040140 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 0080a140 edx = 00000000 eax in: 0xc0000000, eax = c0000002 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0xc0000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00003fcc eax in: 0xc0000002, eax = 00000000 ebx = 08000810 ecx = 08100f13 edx = 42000000 Family: 6 Model: 10 Stepping: 9 CPU Model : VIA C3 (Esther) [C7-M] Processor name string: VIA Esther processor 1500MHz Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable CMOV instruction Page Attribute Table CLFLUSH instruction ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support Pending Break Enable Extended feature flags: Instruction TLB: 8-way associative. 128 entries. Data TLB: 8-way associative. 128 entries. L1 Data cache: Size: 64Kb 4-way associative. lines per tag=1 line size=64 bytes. L1 Instruction cache: Size: 64Kb 4-way associative. lines per tag=1 line size=64 bytes. L2 (on CPU) cache: Size: 128Kb 10-way associative. lines per tag=1 line size=64 bytes. FCR: MSR: 0x00001107=0x9f1f1ac6 : 10011111 00011111 00011010 11000110 Power management: MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000fc0000800 MTRRphysBase1 (0x202): 0x000000003c000000 MTRRphysMask1 (0x203): 0x0000000ffc000800 MTRRphysBase2 (0x204): 0x00000000d8000001 MTRRphysMask2 (0x205): 0x0000000ffc000800 MTRRphysBase3 (0x206): 0x000000003bf00000 MTRRphysMask3 (0x207): 0x0000000ffff00800 MTRRphysBase4 (0x208): 0x00000000a0000001 MTRRphysMask4 (0x209): 0x00000000fc000800 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0505050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0404040404040404 MTRRfix4K_F8000 0x26f: 0x0404040404040400 MTRRdefType (0x2ff): 0x0000000000000c00 800MHz processor (estimate). results/Centaur/cyrix3-samuel.txt000066400000000000000000000051061167043552300174360ustar00rootroot00000000000000x86info v1.11. Dave Jones 2001, 2002 Feedback to . Found 1 CPU eax in: 0x00000000, eax = 00000001 ebx = 746e6543 ecx = 736c7561 edx = 48727561 eax in: 0x00000001, eax = 00000660 ebx = c1704000 ecx = c1705f8c edx = 008031b5 eax in: 0x80000000, eax = 80000005 ebx = c1704000 ecx = c1705f8c edx = 00000010 eax in: 0x80000001, eax = 00000660 ebx = c1704000 ecx = c1705f8c edx = 808031b5 eax in: 0x80000002, eax = 20414956 ebx = 756d6153 ecx = 00006c65 edx = 0000004d eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 80000005 ebx = 08800880 ecx = 40040120 edx = 40040120 Family: 6 Model: 6 Stepping: 0 [VIA Cyrix III] Processor name string: VIA Samuel Feature flags: Onboard FPU Debugging Extensions Time Stamp Counter Model-Specific Registers Machine Check Architecture CMPXCHG8 instruction Memory Type Range Registers Page Global Enable MMX support Extended feature flags: 3dnow Instruction TLB: 8-way associative. 128 entries. Data TLB: 8-way associative. 128 entries. L1 Data cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. L1 Instruction cache: Size: 64Kb 4-way associative. lines per tag=1 line size=32 bytes. FCR: MSR: 0x00001107=0xd03b9282 : 11010000 00111011 10010010 10000010 Longhaul v1.0 present MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x00000000f8000800 MTRRphysBase1 (0x202): 0x00000000d4000001 MTRRphysMask1 (0x203): 0x00000000ff000800 MTRRphysBase2 (0x204): 0x0000000000000000 MTRRphysMask2 (0x205): 0x0000000000000000 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 400.91 MHz processor (estimate). results/Intel/000077500000000000000000000000001167043552300136405ustar00rootroot00000000000000results/Intel/core2-duo-E2180.txt000066400000000000000000000314471167043552300167060ustar00rootroot00000000000000x86info v1.24. Dave Jones 2001-2009 Feedback to . Found 2 CPUs MP Table: # APIC ID Version State Family Model Step Flags # 0 0x14 BSP, usable 6 15 13 0xbfebfbff # 1 0x14 AP, usable 6 15 13 0xbfebfbff -------------------------------------------------------------------------- CPU #1 EFamily: 0 EModel: 0 Family: 6 Model: 15 Stepping: 13 CPU Model: Core 2 Duo [M0] Processor name string: Intel(R) Pentium(R) Dual CPU E2180 @ 2.00GHz Type: 0 (Original OEM) Brand: 0 (Unsupported) Number of reporting banks : 6 Erk, MCG_CTL not present! :0000000000000806: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 01000010 10001000 00000000 00000000 MC0STATUS: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00110100 11100111 01010101 01000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000010 10101001 00000000 00000000 00000010 10101001 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00000000 00000010 10101001 00000000 00000000 00000010 10101001 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00100000 00000000 00000000 00000000 00000000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 00000010 00101000 00001000 00000100 00110000 Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001000 MC4STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010001 MC4ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 5 (0x414) MC5CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC5STATUS: 00010000 00000000 00000000 00010000 00000100 00000000 00001110 00001111 MC5ADDR: Couldn't read MSR 0x416 Microcode version: 0x00000000000000a3 Number of cores per physical package=2 Number of logical processors per socket=2 Number of logical processors per core=1 APIC ID: 0x0 Package: 0 Core: 0 SMT ID 0 eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 000006fd ebx = 00020800 ecx = 0000e39d edx = bfebfbff eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb43078 eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000004, eax = 04000121 ebx = 01c0003f ecx = 0000003f edx = 00000001 eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000220 eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000 eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000503 eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100000 eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 6e655020 edx = 6d756974 eax in: 0x80000003, eax = 20295228 ebx = 6c617544 ecx = 50432020 edx = 45202055 eax in: 0x80000004, eax = 30383132 ebx = 20402020 ecx = 30302e32 edx = 007a4847 eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 04004040 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000 Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L2 cache: 1MB, sectored, 8-way associative. 64 byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L1 Data TLB: 4KB pages, 4-way set associative, 16 entries L1 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Thermal Monitor Pending Break Enable Extended feature flags: sse3 [2] monitor ds-cpl est tm2 ssse3 cx16 xTPR [15] MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000f80000800 MTRRphysBase1 (0x202): 0x0000000080000006 MTRRphysMask1 (0x203): 0x0000000fc0000800 MTRRphysBase2 (0x204): 0x0000000000000000 MTRRphysMask2 (0x205): 0x0000000000000000 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0404040404040404 MTRRfix4K_E8000 0x26d: 0x0404040404040404 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c00 2.00GHz processor (estimate). -------------------------------------------------------------------------- CPU #2 EFamily: 0 EModel: 0 Family: 6 Model: 15 Stepping: 13 CPU Model: Core 2 Duo [M0] Processor name string: Intel(R) Pentium(R) Dual CPU E2180 @ 2.00GHz Type: 0 (Original OEM) Brand: 0 (Unsupported) Number of reporting banks : 6 Erk, MCG_CTL not present! :0000000000000806: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 01000010 10001000 00000000 00000000 MC0STATUS: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 01001110 10101011 11000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000010 10101001 00000000 00000000 00000010 10101001 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00000000 00000010 10101001 00000000 00000000 00000010 10101001 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00100000 00000000 00000000 00000000 00000000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 00000010 00101000 00001000 00000100 00110000 Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001000 MC4STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010001 MC4ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 5 (0x414) MC5CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC5STATUS: 00010000 00000000 00000000 00010000 00000000 00000000 00001110 00001111 MC5ADDR: Couldn't read MSR 0x416 Microcode version: 0x00000000000000a3 Number of cores per physical package=2 Number of logical processors per socket=2 Number of logical processors per core=1 APIC ID: 0x1 Package: 0 Core: 0 SMT ID 1 eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 000006fd ebx = 01020800 ecx = 0000e39d edx = bfebfbff eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb43078 eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000004, eax = 04000121 ebx = 01c0003f ecx = 0000003f edx = 00000001 eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000220 eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000 eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000503 eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100000 eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 6e655020 edx = 6d756974 eax in: 0x80000003, eax = 20295228 ebx = 6c617544 ecx = 50432020 edx = 45202055 eax in: 0x80000004, eax = 30383132 ebx = 20402020 ecx = 30302e32 edx = 007a4847 eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 04004040 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000 Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L2 cache: 1MB, sectored, 8-way associative. 64 byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L1 Data TLB: 4KB pages, 4-way set associative, 16 entries L1 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Thermal Monitor Pending Break Enable Extended feature flags: sse3 [2] monitor ds-cpl est tm2 ssse3 cx16 xTPR [15] MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000f80000800 MTRRphysBase1 (0x202): 0x0000000080000006 MTRRphysMask1 (0x203): 0x0000000fc0000800 MTRRphysBase2 (0x204): 0x0000000000000000 MTRRphysMask2 (0x205): 0x0000000000000000 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0404040404040404 MTRRfix4K_E8000 0x26d: 0x0404040404040404 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c00 4154502.40GHz processor (estimate). -------------------------------------------------------------------------- results/Intel/core2-duo-b2.txt000066400000000000000000000045431167043552300165070ustar00rootroot00000000000000x86info v1.20. Dave Jones 2001-2006 Feedback to . Found 2 CPUs -------------------------------------------------------------------------- CPU #1 /dev/cpu/0/cpuid: No such file or directory Family: 6 Model: 15 Stepping: 6 Type: 0 Brand: 0 CPU Model: Core 2 Duo [B2] Original OEM Feature flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe sse3 monitor ds-cpl vmx est tm2 ssse3 cx16 xTPR Extended feature flags: xd em64t lahf_lm Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L3 unified cache: 4MB, 16-way associative. 64 byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. The physical package supports 2 logical processors -------------------------------------------------------------------------- CPU #2 Family: 6 Model: 15 Stepping: 6 Type: 0 Brand: 0 CPU Model: Core 2 Duo [B2] Original OEM Feature flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe sse3 monitor ds-cpl vmx est tm2 ssse3 cx16 xTPR Extended feature flags: xd em64t lahf_lm Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L3 unified cache: 4MB, 16-way associative. 64 byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. The physical package supports 2 logical processors -------------------------------------------------------------------------- WARNING: Detected SMP, but unable to access cpuid driver. Used Uniprocessor CPU routines. Results inaccurate. results/Intel/core2-duo-e6400.txt000066400000000000000000000301601167043552300167340ustar00rootroot00000000000000x86info v1.18. Dave Jones 2001-2006 Feedback to . Found 2 CPUs MP Table: # APIC ID Version State Family Model Step Flags # 0 0x14 BSP, usable 6 15 6 0xbfebfbff -------------------------------------------------------------------------- CPU #1 Found unknown cache descriptors: 05 2c 30 56 57 7d b0 b1 b4 f0 eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 000006f6 ebx = 00020800 ecx = 0000e3bd edx = bfebfbff eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb4307d eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000020 eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000 eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100800 eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 726f4320 edx = 4d542865 eax in: 0x80000003, eax = 43203229 ebx = 20205550 ecx = 20202020 edx = 20202020 eax in: 0x80000004, eax = 30303436 ebx = 20402020 ecx = 33312e32 edx = 007a4847 eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 08006040 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 15 Stepping: 6 Type: 0 Brand: 0 CPU Model: Core 2 Duo E6400 [B2] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Thermal Monitor Pending Break Enable sse3 monitor ds-cpl vmx est tm2 cx16 xTPR Extended feature flags: SYSCALL xd em64t lahf_lm L1 Instruction cache: Size 32KB 8-way associative. line size=64 bytes. L1 Data cache: Size: 32KB 8-way associative. line size=64 bytes. L2 unified cache: Size: 2MB Sectored, 8-way associative. line size=64 bytes. Instruction TLB: 4K pages, 4-way associative, 128 entries. Found unknown cache descriptors: 05 2c 30 56 57 7d b0 b1 b4 f0 Processor serial: 0000-06F6-0000-0000-0000-0000 Number of reporting banks : 6 Erk, MCG_CTL not present! :0000000000000006: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 01111111 11111111 11111111 11111111 MC0STATUS: 00011111 11111111 11111111 11111111 11110000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 01111111 11111111 11111111 11111111 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00111111 11111111 11111111 11111111 11100000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 01111111 11111111 11111111 11111111 11111111 Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001111 MC4STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011111 MC4ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 5 (0x414) MC5CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC5STATUS: 00011111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 MC5ADDR: Couldn't read MSR 0x416 The physical package supports 2 logical processors Microcode version: 0x0000000000000044 Connector type: LGA775 MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000f80000800 MTRRphysBase1 (0x202): 0x000000007f000000 MTRRphysMask1 (0x203): 0x0000000fff000800 MTRRphysBase2 (0x204): 0x000000007e800000 MTRRphysMask2 (0x205): 0x0000000fff800800 MTRRphysBase3 (0x206): 0x000000007e700000 MTRRphysMask3 (0x207): 0x0000000ffff00800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 2.15GHz processor (estimate). -------------------------------------------------------------------------- CPU #2 Found unknown cache descriptors: 05 2c 30 56 57 7d b0 b1 b4 f0 eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 000006f6 ebx = 01020800 ecx = 0000e3bd edx = bfebfbff eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb4307d eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000004, eax = 04000121 ebx = 01c0003f ecx = 0000003f edx = 00000001 eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000020 eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000 eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100800 eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 726f4320 edx = 4d542865 eax in: 0x80000003, eax = 43203229 ebx = 20205550 ecx = 20202020 edx = 20202020 eax in: 0x80000004, eax = 30303436 ebx = 20402020 ecx = 33312e32 edx = 007a4847 eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 08006040 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 15 Stepping: 6 Type: 0 Brand: 0 CPU Model: Core 2 Duo E6400 [B2] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Thermal Monitor Pending Break Enable sse3 monitor ds-cpl vmx est tm2 cx16 xTPR Extended feature flags: SYSCALL xd em64t lahf_lm L1 Instruction cache: Size 32KB 8-way associative. line size=64 bytes. L1 Data cache: Size: 32KB 8-way associative. line size=64 bytes. L2 unified cache: Size: 2MB Sectored, 8-way associative. line size=64 bytes. Instruction TLB: 4K pages, 4-way associative, 128 entries. Found unknown cache descriptors: 05 2c 30 56 57 7d b0 b1 b4 f0 Processor serial: 0000-06F6-0000-0000-0000-0000 Number of reporting banks : 6 Erk, MCG_CTL not present! :0000000000000006: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 01111111 11111111 11111111 11111111 MC0STATUS: 00011111 11111111 11111111 11111111 11110000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 01111111 11111111 11111111 11111111 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00111111 11111111 11111111 11111111 11100000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 01111111 11111111 11111111 11111111 11111111 Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001111 MC4STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011111 MC4ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 5 (0x414) MC5CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC5STATUS: 00011111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 MC5ADDR: Couldn't read MSR 0x416 The physical package supports 2 logical processors Microcode version: 0x0000000000000044 Connector type: LGA775 MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000f80000800 MTRRphysBase1 (0x202): 0x000000007f000000 MTRRphysMask1 (0x203): 0x0000000fff000800 MTRRphysBase2 (0x204): 0x000000007e800000 MTRRphysMask2 (0x205): 0x0000000fff800800 MTRRphysBase3 (0x206): 0x000000007e700000 MTRRphysMask3 (0x207): 0x0000000ffff00800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 2.15GHz processor (estimate). -------------------------------------------------------------------------- results/Intel/core2-extreme-E6800.txt000066400000000000000000000270721167043552300175720ustar00rootroot00000000000000x86info v1.21. Dave Jones 2001-2007 Feedback to . Found 2 CPUs MP Table: # APIC ID Version State Family Model Step Flags # 0 0x14 BSP, usable 6 15 5 0xbfebfbff -------------------------------------------------------------------------- CPU #1 eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 000006f5 ebx = 00020800 ecx = 0000e3bd edx = bfebfbff eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb43049 eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000004, eax = 04000121 ebx = 01c0003f ecx = 0000003f edx = 00000001 eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000020 eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000 eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100800 eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 726f4320 edx = 4d542865 eax in: 0x80000003, eax = 43203229 ebx = 20205550 ecx = 20202020 edx = 45202020 eax in: 0x80000004, eax = 30303836 ebx = 20402020 ecx = 33392e32 edx = 007a4847 eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 10008040 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 15 Stepping: 5 Type: 0 Brand: 0 CPU Model: Core 2 Extreme E6800/X6800 [B1] Original OEM Feature flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe Extended feature flags: sse3 [2] monitor ds-cpl vmx est tm2 ssse3 cx16 xTPR [15] SYSCALL xd em64t lahf_lm Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L3 unified cache: 4MB, 16-way associative. 64 byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. Number of reporting banks : 6 Erk, MCG_CTL not present! :0000000000000006: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 01111111 11111111 11111111 11111111 MC0STATUS: 00011111 11111111 11111111 11111111 11110000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 01111111 11111111 11111111 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00111111 11111111 11111111 11111111 11100000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 01111111 11111111 11111111 11111111 11111111 Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001111 MC4STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011111 MC4ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 5 (0x414) MC5CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC5STATUS: 00011111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 MC5ADDR: Couldn't read MSR 0x416 The physical package supports 2 logical processors Microcode version: 0x0000000000000033 Connector type: LGA775 MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000f80000800 MTRRphysBase1 (0x202): 0x000000007ff00000 MTRRphysMask1 (0x203): 0x0000000ffff00800 MTRRphysBase2 (0x204): 0x0000000080000001 MTRRphysMask2 (0x205): 0x0000000ffc000800 MTRRphysBase3 (0x206): 0x0000000084000001 MTRRphysMask3 (0x207): 0x0000000ffc000800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 2.95GHz processor (estimate). -------------------------------------------------------------------------- CPU #2 eax in: 0x00000000, eax = 0000000a ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 000006f5 ebx = 01020800 ecx = 0000e3bd edx = bfebfbff eax in: 0x00000002, eax = 05b0b101 ebx = 005657f0 ecx = 00000000 edx = 2cb43049 eax in: 0x00000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000005, eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00000020 eax in: 0x00000006, eax = 00000001 ebx = 00000002 ecx = 00000001 edx = 00000000 eax in: 0x00000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000008, eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x00000009, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x0000000a, eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000000, eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100800 eax in: 0x80000002, eax = 65746e49 ebx = 2952286c ecx = 726f4320 edx = 4d542865 eax in: 0x80000003, eax = 43203229 ebx = 20205550 ecx = 20202020 edx = 45202020 eax in: 0x80000004, eax = 30303836 ebx = 20402020 ecx = 33392e32 edx = 007a4847 eax in: 0x80000005, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000006, eax = 00000000 ebx = 00000000 ecx = 10008040 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000008, eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 15 Stepping: 5 Type: 0 Brand: 0 CPU Model: Core 2 Extreme E6800/X6800 [B1] Original OEM Feature flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe Extended feature flags: sse3 [2] monitor ds-cpl vmx est tm2 ssse3 cx16 xTPR [15] SYSCALL xd em64t lahf_lm Cache info L1 Instruction cache: 32KB, 8-way associative. 64 byte line size. L1 Data cache: 32KB, 8-way associative. 64 byte line size. L3 unified cache: 4MB, 16-way associative. 64 byte line size. TLB info Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative Instruction TLB: 4K pages, 4-way associative, 128 entries. Data TLB: 4MB pages, 4-way associative, 32 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries L0 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. 64 byte prefetching. Number of reporting banks : 6 Erk, MCG_CTL not present! :0000000000000006: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 01111111 11111111 11111111 11111111 MC0STATUS: 00011111 11111111 11111111 11111111 11110000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00111111 11111111 11111111 11111111 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00000000 00000011 11111111 11111111 11111111 11111111 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00111111 11111111 11111111 11111111 11100000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 01111111 11111111 11111111 11111111 11111111 Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001111 MC4STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011111 MC4ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 5 (0x414) MC5CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC5STATUS: 00011111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 MC5ADDR: Couldn't read MSR 0x416 The physical package supports 2 logical processors Microcode version: 0x0000000000000033 Connector type: LGA775 MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000f80000800 MTRRphysBase1 (0x202): 0x000000007ff00000 MTRRphysMask1 (0x203): 0x0000000ffff00800 MTRRphysBase2 (0x204): 0x0000000080000001 MTRRphysMask2 (0x205): 0x0000000ffc000800 MTRRphysBase3 (0x206): 0x0000000084000001 MTRRphysMask3 (0x207): 0x0000000ffc000800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000000000000 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0000000000000000 MTRRfix4K_F0000 0x26e: 0x0000000000000000 MTRRfix4K_F8000 0x26f: 0x0000000000000000 MTRRdefType (0x2ff): 0x0000000000000c00 2.95GHz processor (estimate). -------------------------------------------------------------------------- results/Intel/pentium4-northwood-HT.txt000066400000000000000000000237501167043552300205070ustar00rootroot00000000000000x86info v1.12. Dave Jones 2001-2003 Feedback to . Found 2 CPUs MP Table: # APIC ID Version State Family Model Step Flags # 0 0x14 BSP, usable 15 2 7 0xbfebfbff # 1 0x14 AP, usable 15 2 7 0xbfebfbff -------------------------------------------------------------------------- CPU #1 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000f27 ebx = 00020809 ecx = 00000400 edx = bfebfbff eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040 eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 15 Model: 2 Stepping: 7 Type: 0 Brand: 9 CPU Model: Pentium 4 (Northwood) [C1] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Automatic clock Control Pending Break Enable Pentium 4 specific MSRs: IA32_PLATFORM_ID=0008000000000000 System bus in order queue depth=12 MSR_EBC_FREQUENCY_ID=0000000015010f00 IA32_BIOS_SIGN_ID=0000002400000000 Processor serial number is enabled Fast strings are enabled x87 FPU Fopcode compatability mode is disabled Thermal monitor is enabled Split lock is enabled Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries. Data TLB: 4KB or 4MB pages, fully associative, 64 entries. L1 Data cache: Size: 8KB Sectored, 4-way associative. line size=64 bytes. No level 2 cache or no level 3 cache if valid 2nd level cache. Instruction trace cache: Size: 12K uOps 8-way associative. L2 unified cache: Size: 512KB Sectored, 8-way associative. line size=64 bytes. Number of reporting banks : 4 Number of extended MC registers : 12 Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000011 10000000 00000000 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: Couldn't read MSR 0x40a Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01111110 MC3STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Number of logical processors supported within the physical package: 2 Microcode version: 0x0000000000000024 Connector type: Socket478 (PGA478 Socket) Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf http://developer.intel.com/design/pentium4/datashts/29864304.pdf Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff0000800 MTRRphysBase1 (0x202): 0x00000000f8000001 MTRRphysMask1 (0x203): 0x0000000ffc000800 MTRRphysBase2 (0x204): 0x00000000f2000001 MTRRphysMask2 (0x205): 0x0000000ffe000800 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0505050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0505050505050505 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c00 2.8Ghz processor (estimate). -------------------------------------------------------------------------- CPU #2 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000f27 ebx = 01020809 ecx = 00000400 edx = bfebfbff eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040 eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 15 Model: 2 Stepping: 7 Type: 0 Brand: 9 CPU Model: Pentium 4 (Northwood) [C1] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Automatic clock Control Pending Break Enable Pentium 4 specific MSRs: IA32_PLATFORM_ID=0008000000000000 System bus in order queue depth=12 MSR_EBC_FREQUENCY_ID=0000000015010f00 IA32_BIOS_SIGN_ID=0000002400000000 Processor serial number is enabled Fast strings are enabled x87 FPU Fopcode compatability mode is disabled Thermal monitor is enabled Split lock is enabled Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries. Data TLB: 4KB or 4MB pages, fully associative, 64 entries. L1 Data cache: Size: 8KB Sectored, 4-way associative. line size=64 bytes. No level 2 cache or no level 3 cache if valid 2nd level cache. Instruction trace cache: Size: 12K uOps 8-way associative. L2 unified cache: Size: 512KB Sectored, 8-way associative. line size=64 bytes. Number of reporting banks : 4 Number of extended MC registers : 12 Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000011 10000000 00000000 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: Couldn't read MSR 0x40a Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01111110 MC3STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Number of logical processors supported within the physical package: 2 Microcode version: 0x0000000000000024 Connector type: Socket478 (PGA478 Socket) Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf http://developer.intel.com/design/pentium4/datashts/29864304.pdf Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff0000800 MTRRphysBase1 (0x202): 0x00000000f8000001 MTRRphysMask1 (0x203): 0x0000000ffc000800 MTRRphysBase2 (0x204): 0x00000000f2000001 MTRRphysMask2 (0x205): 0x0000000ffe000800 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0505050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0505050505050505 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c00 2.8Ghz processor (estimate). -------------------------------------------------------------------------- results/Intel/pentium4-northwood.txt000066400000000000000000000220021167043552300201630ustar00rootroot00000000000000x86info v1.11. Dave Jones 2001, 2002 Feedback to . Found 2 CPUs MP Table: # APIC ID Version State Family Model Step Flags # 0 0x14 BSP, usable 15 2 7 0xbfebfbff # 1 0x14 AP, usable 15 2 7 0xbfebfbff CPU #1 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000f27 ebx = 00020809 ecx = 00000400 edx = bfebfbff eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040 eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 15 Model: 2 Stepping: 7 Type: 0 CPU Model: Pentium 4 Xeon (Northwood) [C1] Original OEM Processor name string: Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Automatic clock Control Pending Break Enable Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries. Data TLB: 4KB or 4MB pages, fully associative, 64 entries. L1 Data cache: Size: 8KB Sectored, 4-way associative. line size=64 bytes. No L3 cache Instruction trace cache: Size: 12K uOps 8-way associative. L2 unified cache: Size: 512KB Sectored, 8-way associative. line size=64 bytes. Number of reporting banks : 4 Number of extended MC registers : 12 Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000011 10000000 00000000 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: Couldn't read MSR 0x40a Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01111110 MC3STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Number of logical processors supported within the physical package: 2 Connector type: Socket478 (PGA478 Socket) Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf http://developer.intel.com/design/pentium4/datashts/29864304.pdf Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff0000800 MTRRphysBase1 (0x202): 0x00000000e0000001 MTRRphysMask1 (0x203): 0x0000000ffc000800 MTRRphysBase2 (0x204): 0x0000000000000000 MTRRphysMask2 (0x205): 0x0000000000000000 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0505050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0505050505050505 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c00 2784.34 MHz processor (estimate). CPU #2 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000f27 ebx = 01020809 ecx = 00000400 edx = bfebfbff eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040 eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 15 Model: 2 Stepping: 7 Type: 0 CPU Model: Pentium 4 Xeon (Northwood) [C1] Original OEM Processor name string: Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Page Attribute Table 36-bit PSEs CLFLUSH instruction Debug Trace Store ACPI via MSR MMX support FXSAVE and FXRESTORE instructions SSE support SSE2 support CPU self snoop Hyper-Threading Automatic clock Control Pending Break Enable Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries. Data TLB: 4KB or 4MB pages, fully associative, 64 entries. L1 Data cache: Size: 8KB Sectored, 4-way associative. line size=64 bytes. No L3 cache Instruction trace cache: Size: 12K uOps 8-way associative. L2 unified cache: Size: 512KB Sectored, 8-way associative. line size=64 bytes. Number of reporting banks : 4 Number of extended MC registers : 12 Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000011 10000000 00000000 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 2 (0x408) MC2CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: Couldn't read MSR 0x40a Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01111110 MC3STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC3ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Number of logical processors supported within the physical package: 2 Connector type: Socket478 (PGA478 Socket) Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf http://developer.intel.com/design/pentium4/datashts/29864304.pdf Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000006 MTRRphysMask0 (0x201): 0x0000000ff0000800 MTRRphysBase1 (0x202): 0x00000000e0000001 MTRRphysMask1 (0x203): 0x0000000ffc000800 MTRRphysBase2 (0x204): 0x0000000000000000 MTRRphysMask2 (0x205): 0x0000000000000000 MTRRphysBase3 (0x206): 0x0000000000000000 MTRRphysMask3 (0x207): 0x0000000000000000 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0505050505050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0505050505050505 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c00 2784.36 MHz processor (estimate). results/Intel/quad-ppro.txt000066400000000000000000000402601167043552300163130ustar00rootroot00000000000000x86info v1.12. Dave Jones 2001-2003 Feedback to . Found 4 CPUs MP Table: # APIC ID Version State Family Model Step Flags # 3 0x10 BSP, usable 6 1 9 0xfbff # 0 0x10 AP, usable 6 1 9 0xfbff # 1 0x10 AP, usable 6 1 9 0xfbff # 2 0x10 AP, usable 6 1 9 0xfbff -------------------------------------------------------------------------- CPU #1 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42 Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0 CPU Model: Pentium Pro [sB1] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Extended feature flags: Instruction TLB: 4KB pages, 4-way associative, 32 entries Instruction TLB: 4MB pages, fully associative, 2 entries Data TLB: 4KB pages, 4-way associative, 64 entries L2 unified cache: Size: 256KB 4-way associative. line size=32 bytes. L1 Data cache: Size: 8KB 2-way associative. line size=32 bytes. Data TLB: 4MB pages, 4-way associative, 8 entries L1 Instruction cache: Size: 8KB 4-way associative. line size=32 bytes. Number of reporting banks : 5 Erk, MCG_CTL not present! :0000000000000005: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 11000000 01110000 00000000 01000000 MC0STATUS: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00110100 00110000 11111111 00000000 00110100 00110000 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00110100 01000110 00000000 00000000 00110100 01000110 00000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00110100 01000110 11111111 00000000 00110100 01000110 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3ADDR: Couldn't read MSR 0x40e Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00001000 MC4STATUS: 00100010 00000000 00000000 00000000 00000000 00000000 00000000 00010001 MC4ADDR: 00000000 00110101 00100000 11111111 00000000 00110101 00100000 11111111 Microcode version: 0x00000000000000d2 Connector type: Socket 8 (387 pin Dual Cavity PGA) MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000000 MTRRphysMask0 (0x201): 0x0000000000000000 MTRRphysBase1 (0x202): 0x0000000020000000 MTRRphysMask1 (0x203): 0x0000000fe0000800 MTRRphysBase2 (0x204): 0x0000000040000000 MTRRphysMask2 (0x205): 0x0000000fc0000800 MTRRphysBase3 (0x206): 0x0000000080000000 MTRRphysMask3 (0x207): 0x0000000f80000800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000005050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c06 200MHz processor (estimate). -------------------------------------------------------------------------- CPU #2 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42 Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0 CPU Model: Pentium Pro [sB1] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Extended feature flags: Instruction TLB: 4KB pages, 4-way associative, 32 entries Instruction TLB: 4MB pages, fully associative, 2 entries Data TLB: 4KB pages, 4-way associative, 64 entries L2 unified cache: Size: 256KB 4-way associative. line size=32 bytes. L1 Data cache: Size: 8KB 2-way associative. line size=32 bytes. Data TLB: 4MB pages, 4-way associative, 8 entries L1 Instruction cache: Size: 8KB 4-way associative. line size=32 bytes. Number of reporting banks : 5 Erk, MCG_CTL not present! :0000000000000005: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 11000000 01000000 00000000 01000000 MC0STATUS: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00110100 00110000 11111111 00000000 00110100 00110000 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00110100 01000110 00000000 00000000 00110100 01000110 00000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00110100 01000110 11111111 00000000 00110100 01000110 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3ADDR: Couldn't read MSR 0x40e Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00001000 MC4STATUS: 00100010 00000000 00000000 00000000 00000000 00000000 00000000 00010001 MC4ADDR: 00000000 00110101 00100000 11111111 00000000 00110101 00100000 11111111 Microcode version: 0x00000000000000d2 Connector type: Socket 8 (387 pin Dual Cavity PGA) MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000000 MTRRphysMask0 (0x201): 0x0000000000000000 MTRRphysBase1 (0x202): 0x0000000020000000 MTRRphysMask1 (0x203): 0x0000000fe0000800 MTRRphysBase2 (0x204): 0x0000000040000000 MTRRphysMask2 (0x205): 0x0000000fc0000800 MTRRphysBase3 (0x206): 0x0000000080000000 MTRRphysMask3 (0x207): 0x0000000f80000800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000005050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c06 200MHz processor (estimate). -------------------------------------------------------------------------- CPU #3 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42 Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0 CPU Model: Pentium Pro [sB1] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Extended feature flags: Instruction TLB: 4KB pages, 4-way associative, 32 entries Instruction TLB: 4MB pages, fully associative, 2 entries Data TLB: 4KB pages, 4-way associative, 64 entries L2 unified cache: Size: 256KB 4-way associative. line size=32 bytes. L1 Data cache: Size: 8KB 2-way associative. line size=32 bytes. Data TLB: 4MB pages, 4-way associative, 8 entries L1 Instruction cache: Size: 8KB 4-way associative. line size=32 bytes. Number of reporting banks : 5 Erk, MCG_CTL not present! :0000000000000005: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 11000000 01010000 00000000 01000000 MC0STATUS: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00110100 00110000 11111111 00000000 00110100 00110000 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00110100 01000110 00000000 00000000 00110100 01000110 00000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00110100 01000110 11111111 00000000 00110100 01000110 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3ADDR: Couldn't read MSR 0x40e Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00001000 MC4STATUS: 00100010 00000000 00000000 00000000 00000000 00000000 00000000 00010001 MC4ADDR: 00000000 00110101 00100000 11111111 00000000 00110101 00100000 11111111 Microcode version: 0x00000000000000d2 Connector type: Socket 8 (387 pin Dual Cavity PGA) MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000000 MTRRphysMask0 (0x201): 0x0000000000000000 MTRRphysBase1 (0x202): 0x0000000020000000 MTRRphysMask1 (0x203): 0x0000000fe0000800 MTRRphysBase2 (0x204): 0x0000000040000000 MTRRphysMask2 (0x205): 0x0000000fc0000800 MTRRphysBase3 (0x206): 0x0000000080000000 MTRRphysMask3 (0x207): 0x0000000f80000800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000005050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c06 200MHz processor (estimate). -------------------------------------------------------------------------- CPU #4 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69 eax in: 0x00000001, eax = 00000619 ebx = 00000000 ecx = 00000000 edx = 0000fbff eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 06040a42 Family: 6 Model: 1 Stepping: 9 Type: 0 Brand: 0 CPU Model: Pentium Pro [sB1] Original OEM Feature flags: Onboard FPU Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter Model-Specific Registers Physical Address Extensions Machine Check Architecture CMPXCHG8 instruction Onboard APIC SYSENTER/SYSEXIT Memory Type Range Registers Page Global Enable Machine Check Architecture CMOV instruction Extended feature flags: Instruction TLB: 4KB pages, 4-way associative, 32 entries Instruction TLB: 4MB pages, fully associative, 2 entries Data TLB: 4KB pages, 4-way associative, 64 entries L2 unified cache: Size: 256KB 4-way associative. line size=32 bytes. L1 Data cache: Size: 8KB 2-way associative. line size=32 bytes. Data TLB: 4MB pages, 4-way associative, 8 entries L1 Instruction cache: Size: 8KB 4-way associative. line size=32 bytes. Number of reporting banks : 5 Erk, MCG_CTL not present! :0000000000000005: Bank: 0 (0x400) MC0CTL: 00000000 00000000 00000000 00000000 11000000 01100000 00000000 01000000 MC0STATUS: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC0ADDR: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Bank: 1 (0x404) MC1CTL: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 MC1STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC1ADDR: 00000000 00110100 00110000 11111111 00000000 00110100 00110000 11111111 Bank: 2 (0x408) MC2CTL: 00000000 00110100 01000110 00000000 00000000 00110100 01000110 00000000 MC2STATUS: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 MC2ADDR: 00000000 00110100 01000110 11111111 00000000 00110100 01000110 11111111 Bank: 3 (0x40c) MC3CTL: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3STATUS: 00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000001 MC3ADDR: Couldn't read MSR 0x40e Bank: 4 (0x410) MC4CTL: 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00001000 MC4STATUS: 00100010 00000000 00000000 00000000 00000000 00000000 00000000 00010001 MC4ADDR: 00000000 00110101 00100000 11111111 00000000 00110101 00100000 11111111 Microcode version: 0x00000000000000d2 Connector type: Socket 8 (387 pin Dual Cavity PGA) MTRR registers: MTRRcap (0xfe): 0x0000000000000508 MTRRphysBase0 (0x200): 0x0000000000000000 MTRRphysMask0 (0x201): 0x0000000000000000 MTRRphysBase1 (0x202): 0x0000000020000000 MTRRphysMask1 (0x203): 0x0000000fe0000800 MTRRphysBase2 (0x204): 0x0000000040000000 MTRRphysMask2 (0x205): 0x0000000fc0000800 MTRRphysBase3 (0x206): 0x0000000080000000 MTRRphysMask3 (0x207): 0x0000000f80000800 MTRRphysBase4 (0x208): 0x0000000000000000 MTRRphysMask4 (0x209): 0x0000000000000000 MTRRphysBase5 (0x20a): 0x0000000000000000 MTRRphysMask5 (0x20b): 0x0000000000000000 MTRRphysBase6 (0x20c): 0x0000000000000000 MTRRphysMask6 (0x20d): 0x0000000000000000 MTRRphysBase7 (0x20e): 0x0000000000000000 MTRRphysMask7 (0x20f): 0x0000000000000000 MTRRfix64K_00000 (0x250): 0x0606060606060606 MTRRfix16K_80000 (0x258): 0x0606060606060606 MTRRfix16K_A0000 (0x259): 0x0000000000000000 MTRRfix4K_C8000 (0x269): 0x0000000005050505 MTRRfix4K_D0000 0x26a: 0x0000000000000000 MTRRfix4K_D8000 0x26b: 0x0000000000000000 MTRRfix4K_E0000 0x26c: 0x0000000000000000 MTRRfix4K_E8000 0x26d: 0x0505050505050505 MTRRfix4K_F0000 0x26e: 0x0505050505050505 MTRRfix4K_F8000 0x26f: 0x0505050505050505 MTRRdefType (0x2ff): 0x0000000000000c06 200MHz processor (estimate). -------------------------------------------------------------------------- results/README.txt000066400000000000000000000001751167043552300142660ustar00rootroot00000000000000Add results of 'x86info -a -v' here. Note, the runs should be done as root, and with the MSR/CPUID modules loaded/built-in. scripts/000077500000000000000000000000001167043552300125535ustar00rootroot00000000000000scripts/createheader.py000066400000000000000000000061601167043552300155440ustar00rootroot00000000000000#!/usr/bin/python # Author: Andreas Herrmann # # Copyright (C) 2008 Advanced Micro Devices, Inc. # # Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2. # See file COPYING for details. # This script creates C header files from some register # description files. # # The general format for those register descriptions is # # {=
;[] # []:[;=|] # []:[;=|] # ... # []:[;=|] # } # # If no field name is provided the field is reserved and might # not be displayed with the msr viewing tool. The optional = # data is for bit field decoding but it's currently not yet supported. # Todos/Nice-to-have: # - comments in this script (?) # - create information for bit field decoding # - warn if names contain whitespace characters # - add include/insert statement to avoid dup definitions of common register # - allow annotations for registers (e.g. write-only) # - improve command line handling import re import sys import os progname=os.path.basename(sys.argv[0]) if len(sys.argv) < 3: print(progname + ": invalid number of argumenst") print("\nUSAGE:") print(progname + " ") print("\nEXAMPLE:") print(progname + " k8regs.txt k8 >k8.h") sys.exit(1) f=open(sys.argv[1]) family=sys.argv[2] print(\ "/*\n"\ " * Licensed under the terms of the GNU GENERAL PUBLIC LICENSE version 2.\n"\ " * See file COPYING for details.\n"\ " */\n") print("#ifndef " + family + "_h") print("#define " + family + "_h\n") if (re.search("/", sys.argv[1])): print("#include \"../msr.h\"\n") else: print("#include \"msr.h\"\n") struct=[] for line in f: if (re.search("^#",line)): continue if (re.search("^{",line)): start=1; end=0 tmp=line.split("{")[1] tmp=tmp.split("=") reg_name=tmp[0].strip() tmp=tmp[1].split(";") reg_addr=tmp[0].strip() if len(tmp) > 1: reg_desc=tmp[1].strip() else: reg_desc="" spec=[] if (re.search("^}",line)): end=1 str1="_RANGE(" + family + "_" + reg_name str2="_NAMES(" + family + "_" + reg_name for e in spec: if e[0]=="": str2 += ",0" else: str2 += ",\"" + e[0] +"\"" str1 += "," + e[1] str1 += ",0);" str2 += ");" print(str1) print(str2) str3 = "_SPEC(" + reg_addr + ", " + reg_name + ", " if reg_desc != "": str3 += "\"" + reg_desc + "\", " else: str3 += "NULL, " str3 += family + "_)" struct.append(str3) if (re.search(":", line)): tmp=line.split(";") field=tmp[0].split(":") fname=field[0].strip() fwidth=field[1].strip() spec.append([fname, fwidth]) print("\nstruct reg_spec " + family + "_spec [] = {") for i in struct: print("\t" + i + ",") print(" {0, NULL, NULL, NULL, NULL},") print("};\n") print("#endif /* " + family + "_h */") f.close() scripts/makenodes000077500000000000000000000012631167043552300144510ustar00rootroot00000000000000#!/bin/bash # Only root can run this script if [ "$(id -u)" != "0" ]; then echo "This script must be run as root" 1>&2 exit 1 fi let NRNODES=(`grep processor /proc/cpuinfo | wc -l`)-1 loadCpuid=0 loadMsr=0 if [ ! -d /dev/cpu ] ; then mkdir /dev/cpu fi for i in `seq 0 $NRNODES` do if [ ! -d /dev/cpu/$i ] ; then mkdir /dev/cpu/$i fi if [ ! -c /dev/cpu/$i/cpuid ] ; then (cd /dev/cpu/$i ; mknod cpuid c 203 $i) loadCpuid=1 fi if [ ! -c /dev/cpu/$i/msr ] ; then (cd /dev/cpu/$i ; mknod msr c 202 $i) loadMsr=1 fi done if test "$loadCpuid" -eq 1 ; then modprobe cpuid fi if test "$loadMsr" -eq 1 ; then modprobe msr fi echo "All cpuid & msr /dev nodes present." scripts/testnodes000077500000000000000000000007311167043552300145120ustar00rootroot00000000000000#!/bin/bash [ `uname -s` != "Linux" ] && exit 0 NRNODES=`grep processor /proc/cpuinfo | wc -l` need=0 for i in `seq 0 $(( $NRNODES - 1 ))` do if [ ! -c /dev/cpu/$i/cpuid ] ; then echo "*** No /dev/cpu/$i/cpuid found." need=1 fi if [ ! -c /dev/cpu/$i/msr ] ; then echo "*** No /dev/cpu/$i/msr found." need=1 fi done if test "$need" -eq 1 ; then echo "type \"make nodes\" as root to install device nodes" echo "You will also need msr driver installed" fi topology.c000066400000000000000000000046301167043552300131070ustar00rootroot00000000000000/* * (C) 2011 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. */ #include #include #include #include "x86info.h" static char * corenum(int num) { switch (num) { case 1: return ("single"); case 2: return ("dual"); case 3: return ("tri"); case 4: return ("quad"); case 6: return ("six"); case 8: return ("eight"); default: return ("?"); } } void get_topology(struct cpudata *cpu) { if (cpu->vendor == VENDOR_INTEL) get_intel_topology(cpu); } void display_topology(struct cpudata *head) { struct cpudata *cpu; unsigned int threads_per_socket; unsigned int i; char *sockets; int num_sockets = 0; /* For now, we only support topology parsing on Intel. */ if (head->vendor != VENDOR_INTEL) return; if (debug == 1) { cpu = head; printf("cpu->phys_proc_id: "); for (i = 0; i < nrCPUs; i++) { printf("%d, ", cpu->phys_proc_id); cpu = cpu->next; } printf("\n"); cpu = head; printf("cpu->x86_max_cores: "); for (i = 0; i < nrCPUs; i++) { printf("%d, ", cpu->x86_max_cores); cpu = cpu->next; } printf("\n"); cpu = head; printf("cpu->cpu_core_id: "); for (i = 0; i < nrCPUs; i++) { printf("%d, ", cpu->cpu_core_id); cpu = cpu->next; } printf("\n"); } sockets = malloc(nrCPUs); if (sockets == NULL) return; for (i = 0; i < nrCPUs; i++) sockets[i]=0; cpu = head; for (i = 0; i < nrCPUs; i++) { sockets[cpu->phys_proc_id]++; cpu = cpu->next; } for (i = 0; i < nrCPUs; i++) { if (debug == 1) printf("Socket %d: %d threads\n", i, sockets[i]); if (sockets[i] != 0) /* only count populated sockets */ num_sockets++; } /* Print a topology summary */ cpu = head; printf("Total processor threads: %d\n", sockets[0] * num_sockets); printf("This system has %d ", num_sockets); threads_per_socket = sockets[0]; if (cpu->flags_edx & X86_FEATURE_HT) if (cpu->num_siblings > 1) threads_per_socket = sockets[0]/2; if (nrCPUs == 1) { /* Handle the single CPU case */ printf("processor"); } else { char *p; p = corenum(threads_per_socket); if (strncmp("?", p, 1)) printf("%s-core processor", corenum(threads_per_socket)); else printf("%d-core processor", threads_per_socket); if (num_sockets > 1) printf("s"); } if (cpu->flags_edx & X86_FEATURE_HT && cpu->num_siblings > 1) printf(" with hyper-threading (%d threads per core)", cpu->num_siblings); free(sockets); } x86info.1000066400000000000000000000064751167043552300124630ustar00rootroot00000000000000.\" This -*- nroff -*- file has been generated from .\" DocBook SGML with docbook-to-man on Debian GNU/Linux. ...\" ...\" transcript compatibility for postscript use. ...\" ...\" synopsis: .P! ...\" .de P! \\&. .fl \" force out current output buffer \\!%PB \\!/showpage{}def ...\" the following is from Ken Flowers -- it prevents dictionary overflows \\!/tempdict 200 dict def tempdict begin .fl \" prolog .sy cat \\$1\" bring in postscript file ...\" the following line matches the tempdict above \\!end % tempdict % \\!PE \\!. .sp \\$2u \" move below the image .. .de pF .ie \\*(f1 .ds f1 \\n(.f .el .ie \\*(f2 .ds f2 \\n(.f .el .ie \\*(f3 .ds f3 \\n(.f .el .ie \\*(f4 .ds f4 \\n(.f .el .tm ? font overflow .ft \\$1 .. .de fP .ie !\\*(f4 \{\ . ft \\*(f4 . ds f4\" ' br \} .el .ie !\\*(f3 \{\ . ft \\*(f3 . ds f3\" ' br \} .el .ie !\\*(f2 \{\ . ft \\*(f2 . ds f2\" ' br \} .el .ie !\\*(f1 \{\ . ft \\*(f1 . ds f1\" ' br \} .el .tm ? font underflow .. .ds f1\" .ds f2\" .ds f3\" .ds f4\" '\" t .ta 8n 16n 24n 32n 40n 48n 56n 64n 72n .TH "x86info" "1" .SH "NAME" x86info \(em display x86 CPU diagnostics .SH "SYNOPSIS" .PP \fBx86info\fP [\fB-a\fP] [\fB-c\fP] [\fB-f\fP] [fB-F\fP] [\fB-m\fP] [\fB-mhz\fP] [\fB-r\fP] [\fB?\fP] [\fB--all\fP] [\fB--cache\fP] [\fB--flags\fP] [\fB--verbose\fP] [\fB--msr\fP] [\fB--mhz\fP] [\fB--registers\fP] [\fB--help\fP] .SH "DESCRIPTION" .PP This manual page documents \fBx86info\fP, a program which displays a range of information about the CPUs present in an x86 system. .PP In order to make full use of this program you need to have the CPU ID and MSR device drivers in your kernel with accessible device files /dev/cpu//cpuid and /dev/cpu//msr. .SH "OPTIONS" .PP This program follows the usual GNU command line syntax, with long options starting with two dashes (`-'). A summary of options is included below. .IP "\fB?\fP \fB--help\fP " 10 Show summary of options. .IP "\fB-a\fP \fB--all\fP " 10 Show all information. Equivalent to \fB-c\fP \fB-f\fP \fB-m\fP \fB-r\fP \fB-mhz\fP. .IP "\fB-c\fP \fB--cache\fP " 10 Show TLB, cache sizes and cache associativity. .IP "\fB-f\fP \fB--flags\fP " 10 Show CPU feature flags. .IP "\fB-m\fP \fB--msr\fP " 10 Dump model specific registers. This feature is currently only supported on a few different processors. Future versions will include parsing of bits in MSRs for all processors. .IP "\fB-mhz\fP \fB--mhz\fP " 10 Estimate current clock rate. .IP "\fB-mp\fP \fB--mptable\fP " 10 Dump MP table showing CPUs BIOS knows about. .IP "\fB-r\fP \fB--registers\fP " 10 Show register values from all possible cpuid calls. .IP "\fB-s\fP \fB--show-machine-check\fP " 10 Show machine check exception information. .IP "\fB-v\fP \fB--verbose\fP " 10 Show verbose descriptions. .SH "AUTHOR" .PP \fBx86info\fP was written by Dave Jones . .PP This manual page was written by Mark Brown for the \fBDebian GNU/Linux\fP system (but may be used by others). .PP Permission is granted to copy, distribute and/or modify this document under the terms of the GNU General Public License version 2. x86info.c000066400000000000000000000123531167043552300125350ustar00rootroot00000000000000/* * (C) 2001-2011 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. */ #include #include #include #include #include "x86info.h" #include "mptable.h" #include "Intel/Intel.h" unsigned int user_is_root = 0; unsigned int nrCPUs=1; static unsigned int nrSMPCPUs; struct cpudata *firstcpu; static void separator(void) { int j; for (j = 0; j < 74; j++) printf("-"); printf("\n"); } static void display_detailed_info(struct cpudata *cpu) { bind_cpu(cpu); /* FIXME: Eventually remove once 'gather' has all the per-cpu stuff */ show_info(cpu); if (show_cpuid) { dump_raw_cpuid(cpu->number, 0, cpu->cpuid_level); if (cpu->maxei >=0x80000000) dump_raw_cpuid(cpu->number, 0x80000000, cpu->maxei); if (cpu->maxei2 >=0xC0000000) dump_raw_cpuid(cpu->number, 0xC0000000, cpu->maxei2); } if (show_cacheinfo) { switch (cpu->vendor) { case VENDOR_INTEL: decode_Intel_caches(cpu, 1); break; case VENDOR_AMD: decode_AMD_cacheinfo(cpu); break; default: break; } } if (show_feature_flags) display_feature_flags(cpu); if (show_connector) decode_connector(cpu->connector); if (show_urls) { if (cpu->info_url != NULL) printf("Info URL: %s\n", cpu->info_url); if (cpu->datasheet_url != NULL) printf("Datasheet: %s\n", cpu->datasheet_url); if (cpu->errata_url != NULL) printf("Errata: %s\n", cpu->errata_url); } /* Info that requires root access (eg, reading MSRs etc) */ if (user_is_root) { if (show_mtrr) dump_mtrrs(cpu); if (show_apic) dump_apics(cpu); } if (show_addr_sizes) printf("Address sizes : %u bits physical, %u bits virtual\n", cpu->phyaddr_bits, cpu->viraddr_bits); if (show_MHz) { display_MHz(cpu); printf(" processor (estimate).\n\n"); } if (show_bench) show_benchmarks(cpu); } /* * check to see if all CPUs are the same. * returns 1 if all cpus are the same, 0 if something is different */ static int check_cpu_similarity() { struct cpudata *cpu; unsigned int i; /* force to display all cpus if the user requested it. */ if (all_cpus) return 0; if (nrCPUs == 1) return 1; cpu = firstcpu; for (i = 0; i < nrCPUs; i++) { cpu = cpu->next; if (!cpu) return 1; if (cpu->efamily != firstcpu->efamily) return 0; if (cpu->emodel != firstcpu->emodel) return 0; if (cpu->family != firstcpu->family) return 0; if (model(cpu) != model(firstcpu)) return 0; if (cpu->stepping != firstcpu->stepping) return 0; } return 1; } static struct cpudata *alloc_cpu() { struct cpudata *newcpu; newcpu = malloc (sizeof (struct cpudata)); if (!newcpu) { printf("Out of memory\n"); exit(EXIT_FAILURE); } memset(newcpu, 0, sizeof(struct cpudata)); return newcpu; } static void fill_in_cpu_info(struct cpudata *cpu) { bind_cpu(cpu); estimate_MHz(cpu); get_cpu_info_basics(cpu); /* get vendor,family,model,stepping */ get_feature_flags(cpu); identify(cpu); get_topology(cpu); } int main (int argc, char **argv) { struct cpudata *cpu=NULL, *tmp; unsigned int i; unsigned int display_one_cpu = 1; if (getuid() == 0) user_is_root = 1; parse_command_line(argc, argv); printf("x86info v" __stringify(VERSION) " Dave Jones 2001-2011\n"); printf("Feedback to .\n\n"); if ((HaveCPUID()) == 0) { printf("No CPUID instruction available.\n"); printf("No further information available for this CPU.\n"); exit(EXIT_SUCCESS); } if (need_root && !user_is_root) { printf("Need to be root to use specified options.\n"); exit(EXIT_FAILURE); } nrCPUs = sysconf(_SC_NPROCESSORS_ONLN); /* * can't have less than 1 CPU, or more than * 65535 (some arbitrary large number) */ if ((nrCPUs < 1) || (nrCPUs > 65535)) { printf("CPU count is bogus: defaulting to 1 CPU.\n"); nrCPUs = 1; } /* Allocate a cpu for boot cpu. */ cpu = firstcpu = alloc_cpu(); fill_in_cpu_info(cpu); /* Allocate structs for non-boot CPUs if present */ if (nrCPUs > 1) { for (i = 1; i < nrCPUs; i++) { cpu->next = alloc_cpu(); cpu = cpu->next; cpu->number = i; fill_in_cpu_info(cpu); } } display_one_cpu = check_cpu_similarity(); if (show_mptable && user_is_root) display_mptable(); /* Now we display the info we gathered */ cpu = firstcpu; if (display_one_cpu) { if (nrCPUs >= 2) printf("Found %d identical CPUs", nrCPUs); /* Check mptable if present. This way we get number of CPUs on SMP systems that have booted UP kernels. */ if (user_is_root) { nrSMPCPUs = enumerate_cpus(); if (nrSMPCPUs > nrCPUs) printf(" (but found %ud CPUs in MPTable!)", nrSMPCPUs); } if (nrCPUs >= 2) printf("\n"); display_detailed_info(cpu); } else { printf("Found %d CPUs.\n", nrCPUs); for (i = 0; i < nrCPUs; i++) { printf("CPU #%u:\n", i+1); display_detailed_info(cpu); if (nrCPUs > 1) separator(); cpu = cpu->next; } } display_topology(firstcpu); printf(" running at an estimated "); display_MHz(firstcpu); printf("\n"); /* Tear down the linked list. */ cpu = firstcpu; for (i = 0; i < nrCPUs; i++) { if (cpu->info_url) free(cpu->info_url); if (cpu->datasheet_url) free(cpu->datasheet_url); if (cpu->errata_url) free(cpu->errata_url); tmp = cpu->next; free(cpu); cpu = tmp; } exit(EXIT_SUCCESS); } x86info.h000066400000000000000000000144031167043552300125400ustar00rootroot00000000000000#ifndef _X86INFO_H #define _X86INFO_H typedef unsigned char u8; typedef unsigned short u16; typedef unsigned int u32; enum vendor { VENDOR_UNKNOWN = 0 , VENDOR_AMD, VENDOR_CENTAUR, VENDOR_CYRIX, VENDOR_INTEL, VENDOR_NATSEMI, VENDOR_RISE, VENDOR_TRANSMETA, VENDOR_SIS, }; enum connector { CONN_UNKNOWN = 0, CONN_SOCKET_3, CONN_SOCKET_4, CONN_SOCKET_5, CONN_SOCKET_7, CONN_SOCKET_370, CONN_SOCKET_370_FCPGA, CONN_SOCKET_5_7, CONN_SUPER_SOCKET_7, CONN_SLOT_A, CONN_SOCKET_A, CONN_SOCKET_A_SLOT_A, CONN_SOCKET_A_OR_SLOT_A, CONN_SOCKET_57B, CONN_MOBILE_7, CONN_SOCKET_8, CONN_SLOT_1, CONN_SLOT_2, CONN_SOCKET_423, CONN_MMC, CONN_MMC2, CONN_BGA474, CONN_BGA, CONN_SOCKET_754, CONN_SOCKET_478, CONN_SOCKET_603, CONN_MICROFCBGA, CONN_SOCKET_939, CONN_SOCKET_940, CONN_LGA775, CONN_SOCKET_F, CONN_SOCKET_AM2, CONN_SOCKET_S1G1, CONN_SOCKET_S1G2, CONN_SOCKET_S1G3, CONN_SOCKET_F_R2, CONN_SOCKET_AM3, CONN_SOCKET_G34, CONN_SOCKET_ASB2, CONN_SOCKET_C32, CONN_SOCKET_FP1, CONN_SOCKET_FS1, CONN_SOCKET_FM1, CONN_SOCKET_FT1, }; #define CPU_NAME_LEN 80 struct cpudata { struct cpudata *next; unsigned int number; enum vendor vendor; unsigned int efamily; unsigned int family; unsigned int model; unsigned int emodel; unsigned int stepping; unsigned int type; unsigned int cachesize_L1_I, cachesize_L1_D; unsigned int cachesize_L2; unsigned int cachesize_L3; unsigned int cachesize_trace; unsigned int phyaddr_bits; unsigned int viraddr_bits; unsigned int cpuid_level, maxei, maxei2; char name[CPU_NAME_LEN]; enum connector connector; unsigned int flags_ecx; unsigned int flags_edx; unsigned int eflags_ecx; unsigned int eflags_edx; unsigned int MHz; unsigned int nr_cores; unsigned int nr_logical; char *info_url; char *datasheet_url; char *errata_url; /* Intel specific bits */ unsigned int brand; unsigned int apicid; char serialno[30]; unsigned int phys_proc_id; unsigned int initial_apicid; unsigned int x86_max_cores; unsigned int cpu_core_id; unsigned int num_siblings; }; void cpuid_UP(unsigned int idx, unsigned long *eax, unsigned long *ebx, unsigned long *ecx, unsigned long *edx); void cpuid(unsigned int cpu, unsigned long long idx, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx); void cpuid4(unsigned int CPU_number, unsigned long long idx, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx); void cpuid_count(unsigned int CPU_number, unsigned int op, int count, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx); unsigned int cpuid_ebx(unsigned int CPU_number, unsigned int op); #define family(c) (c->family + c->efamily) #define model(c) ((c->emodel << 4) + c->model) #define tuple(c) ((c->family<<8)|(c->model<<4)|(c->stepping)) #define etuple(c) ((c->efamily<<8)|(c->model<<4)|(c->stepping)) #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof(x[0]))) #define get_name(title,type,table) \ static const char *get_##title##_name(type id) \ { \ int i; \ for (i = 0; i < ARRAY_SIZE(table); i++) \ if (id == table[i].id) \ return table[i].name; \ return NULL; \ } void Identify_AMD(struct cpudata *cpu); void Identify_Cyrix(struct cpudata *cpu); void identify_centaur(struct cpudata *cpu); void Identify_Intel(struct cpudata *cpu); void identify_RiSE(struct cpudata *cpu); void identify_natsemi(struct cpudata *cpu); void identify_sis(struct cpudata *cpu); void display_AMD_info(struct cpudata *cpu); void display_Cyrix_info(struct cpudata *cpu); void display_centaur_info(struct cpudata *cpu); void display_basic_Intel_info(struct cpudata *cpu); void display_extended_Intel_info(struct cpudata *cpu); void get_feature_flags(struct cpudata *cpu); void display_feature_flags(struct cpudata *cpu); void show_extra_intel_flags(struct cpudata *cpu); void parse_command_line(int argc, char **argv); void get_cpu_info_basics(struct cpudata *cpu); void identify(struct cpudata *cpu); void show_info(struct cpudata *cpu); int read_msr(int cpu, unsigned int idx, unsigned long long *val); void binary(unsigned int n, unsigned long value); void binary32(unsigned long value); void binary64(unsigned long long value); void dumpmsr(int cpunum, unsigned int msr, int size); void dumpmsr_bin(int cpunum, unsigned int msr, int size); void dump_raw_cpuid(int cpunum, unsigned int begin, unsigned int end); void dump_mtrrs(struct cpudata *cpu); void dump_apics(struct cpudata *cpu); void display_MHz(struct cpudata *cpu); void estimate_MHz(struct cpudata *cpu); int HaveCPUID(void); void interpret_eblcr(u32 lo); int enumerate_cpus(void); void get_model_name(struct cpudata *cpu); void decode_connector(enum connector type); void show_benchmarks(struct cpudata *cpu); void decode_serial_number(struct cpudata *cpu); void get_topology(struct cpudata *head); void display_topology(struct cpudata *head); void get_intel_topology(struct cpudata *cpu); void decode_AMD_cacheinfo(struct cpudata *cpu); extern unsigned int nrCPUs; extern struct cpudata *firstcpu; extern unsigned int user_is_root; extern unsigned int need_root; /* command line args */ extern unsigned int show_apic; extern unsigned int show_bench; extern unsigned int show_bios; extern unsigned int show_machine_check; extern unsigned int show_bugs; extern unsigned int show_cacheinfo; extern unsigned int show_connector; extern unsigned int show_eblcr; extern unsigned int show_msr; extern unsigned int show_microcode; extern unsigned int show_mtrr; extern unsigned int show_pm; extern unsigned int show_cpuid; extern unsigned int show_urls; extern unsigned int show_mptable; extern unsigned int show_feature_flags; extern unsigned int show_MHz; extern unsigned int show_addr_sizes; extern unsigned int all_cpus; extern unsigned int debug; extern unsigned int verbose; #define X86_FEATURE_HT (1<<28) #define X86_FEATURE_MTRR (1<<12) #define X86_FEATURE_APIC (1<<9) #define _GNU_SOURCE #define __USE_GNU #include #include #include static inline void bind_cpu(struct cpudata *cpu) { cpu_set_t set; if (sched_getaffinity(getpid(), sizeof(set), &set) == 0) { CPU_ZERO(&set); CPU_SET(cpu->number, &set); sched_setaffinity(getpid(), sizeof(set), &set); } } #define __stringify_1(x...) #x #define __stringify(x...) __stringify_1(x) #endif /* _X86INFO_H */