xresprobe-0.4.24ubuntu9/0000755000000000000000000000000010704625216012037 5ustar xresprobe-0.4.24ubuntu9/ddcprobe.sh0000755000000000000000000000357010677050343014167 0ustar #!/bin/sh # Copyright (C) 2004 Canonical Ltd. # Author: Daniel Stone # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License with # the Debian GNU/Linux distribution in file /usr/share/common-licenses/GPL-2; # if not, write to the Free Software Foundation, Inc., 59 Temple Place, # Suite 330, Boston, MA 02111-1307 USA # # On Debian systems, the complete text of the GNU General Public # License, version 2, can be found in /usr/share/common-licenses/GPL-2. BLACKLISTMODES="2288x1430" if [ -n "$1" ]; then DDCPROBE="$(cat $1)" else DDCPROBE="$(ddcprobe 2>/dev/null)" fi if [ "$?" = "1" ]; then exit 1 fi if (echo "$DDCPROBE" | egrep "(edidfail|ddcfail)" >/dev/null 2>&1); then exit 0 fi if (echo "$DDCPROBE" | egrep "^input: .*digital"); then SCREENTYPE="lcd" else # Not necessarily true, as lcds can be connected as analog too SCREENTYPE="crt" fi TIMINGS="$(echo "$DDCPROBE" | egrep '^[cd]*timing:' | \ sed -e 's/^[cd]*timing: \([^x]*\)x\([^ @$]*\).*$/\1x\2/;' | \ sort -nr | egrep -v "$BLACKLISTMODES")" TIMINGS="$(echo "$TIMINGS" | sort -rnu -tx -k1,1nr -k2,2nr)" MONITORNAME="$(echo "$DDCPROBE" | egrep '^monitorname:' | sed -e 's/^monitorname: //;')" MONITORRANGE="$(echo "$DDCPROBE" | egrep '^monitorrange:' | sed -e 's/^monitorrange: //;' -e 's/\,//;')" echo "res: $(echo $TIMINGS | xargs echo)" echo "displaytype: $SCREENTYPE" echo "name: $MONITORNAME" echo "freq: $MONITORRANGE" xresprobe-0.4.24ubuntu9/tests/0000755000000000000000000000000010415741443013201 5ustar xresprobe-0.4.24ubuntu9/tests/log-fglrx-1600x12000000644000000000000000000010464310214367723016116 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Ubuntu 4.3.0.dfsg.1-6ubuntu4 20040813041619 root@mcmurdo.warthogs.hbd.com) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.4.27-es i686 [ELF] Build Date: 13 August 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.7-1-386acpi (mjg59@tyrosine) (gcc version 3.3.4 (Debian 1:3.3.4-3)) #1 Wed Aug 11 16:30:30 BST 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Thu Aug 19 16:33:40 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Generic Monitor" (**) | |-->Device "ati Video Card" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "pc104" (**) XKB: model: "pc104" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Touchpad Mouse" (**) |-->Input Device "Generic Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: Probing config type using method 1 (II) PCI: Config type is 1 (II) PCI: stages = 0x03, oldVal1 = 0x00000000, mode1Res1 = 0x80000000 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,2570 card 1558,0500 rev 02 class 06,00,00 hdr 00 (II) PCI: 00:01:0: chip 8086,2571 card 0000,0000 rev 02 class 06,04,00 hdr 01 (II) PCI: 00:1d:0: chip 8086,24d2 card 1558,0500 rev 02 class 0c,03,00 hdr 80 (II) PCI: 00:1d:1: chip 8086,24d4 card 1558,0500 rev 02 class 0c,03,00 hdr 00 (II) PCI: 00:1d:2: chip 8086,24d7 card 1558,0500 rev 02 class 0c,03,00 hdr 00 (II) PCI: 00:1d:3: chip 8086,24de card 1558,0500 rev 02 class 0c,03,00 hdr 00 (II) PCI: 00:1d:7: chip 8086,24dd card 1558,0500 rev 02 class 0c,03,20 hdr 00 (II) PCI: 00:1e:0: chip 8086,244e card 0000,0000 rev c2 class 06,04,00 hdr 01 (II) PCI: 00:1f:0: chip 8086,24d0 card 0000,0000 rev 02 class 06,01,00 hdr 80 (II) PCI: 00:1f:1: chip 8086,24db card 1558,0500 rev 02 class 01,01,8a hdr 00 (II) PCI: 00:1f:3: chip 8086,24d3 card 1558,0500 rev 02 class 0c,05,00 hdr 00 (II) PCI: 00:1f:5: chip 8086,24d5 card 1558,0800 rev 02 class 04,01,00 hdr 00 (II) PCI: 00:1f:6: chip 8086,24d6 card 1558,0800 rev 02 class 07,03,00 hdr 00 (II) PCI: 01:00:0: chip 1002,4e50 card 1558,0500 rev 00 class 03,00,00 hdr 00 (II) PCI: 03:00:0: chip 1524,1410 card 4400,0000 rev 01 class 06,07,00 hdr 02 (II) PCI: 03:01:0: chip 104c,8026 card 1558,0500 rev 00 class 0c,00,10 hdr 00 (II) PCI: 03:03:0: chip 10ec,8169 card 1558,0500 rev 10 class 02,00,00 hdr 00 (II) PCI: 03:04:0: chip 8086,4220 card 8086,2701 rev 05 class 02,80,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (0,0,4), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-PCI bridge: (II) Bus 1: bridge is at (0:1:0), (0,1,1), BCTRL: 0x000c (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [1] -1 0 0x00003400 - 0x000034ff (0x100) IX[B] [2] -1 0 0x00003800 - 0x000038ff (0x100) IX[B] [3] -1 0 0x00003c00 - 0x00003cff (0x100) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0xe8100000 - 0xe81fffff (0x100000) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B] (II) PCI-to-PCI bridge: (II) Bus 3: bridge is at (0:30:0), (0,3,3), BCTRL: 0x0004 (VGA_EN is cleared) (II) Bus 3 I/O range: [0] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [1] -1 0 0x00004400 - 0x000044ff (0x100) IX[B] [2] -1 0 0x00004800 - 0x000048ff (0x100) IX[B] [3] -1 0 0x00004c00 - 0x00004cff (0x100) IX[B] (II) Bus 3 non-prefetchable memory range: [0] -1 0 0xe8200000 - 0xe82fffff (0x100000) MX[B] (II) PCI-to-ISA bridge: (II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set) (II) PCI-to-CardBus bridge: (II) Bus 4: bridge is at (3:0:0), (3,4,7), BCTRL: 0x0540 (VGA_EN is cleared) (II) Bus 4 I/O range: [0] -1 0 0x00004400 - 0x000044ff (0x100) IX[B] [1] -1 0 0x00004800 - 0x000048ff (0x100) IX[B] (--) PCI:*(1:0:0) ATI Technologies Inc unknown chipset (0x4e50) rev 0, Mem @ 0xf0000000/27, 0xe8100000/16, I/O @ 0x3000/8 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) PCI Memory resource overlap reduced 0xd0000000 from 0xd7ffffff to 0xcfffffff (II) Active PCI resource ranges: [0] -1 0 0xe8204000 - 0xe8204fff (0x1000) MX[B] [1] -1 0 0xe8205800 - 0xe82058ff (0x100) MX[B] [2] -1 0 0xe8200000 - 0xe8203fff (0x4000) MX[B] [3] -1 0 0xe8205000 - 0xe82057ff (0x800) MX[B] [4] -1 0 0xe8000800 - 0xe80008ff (0x100) MX[B] [5] -1 0 0xe8000c00 - 0xe8000dff (0x200) MX[B] [6] -1 0 0x40000000 - 0x400003ff (0x400) MX[B] [7] -1 0 0xe8000000 - 0xe80003ff (0x400) MX[B] [8] -1 0 0xd0000000 - 0xcfffffff (0x0) MX[B]O [9] -1 0 0xe8100000 - 0xe810ffff (0x10000) MX[B](B) [10] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B](B) [11] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [12] -1 0 0x00001c00 - 0x00001c7f (0x80) IX[B] [13] -1 0 0x00001800 - 0x000018ff (0x100) IX[B] [14] -1 0 0x00001c80 - 0x00001cbf (0x40) IX[B] [15] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [16] -1 0 0x00002040 - 0x0000205f (0x20) IX[B] [17] -1 0 0x00002060 - 0x0000206f (0x10) IX[B] [18] -1 0 0x00002020 - 0x0000203f (0x20) IX[B] [19] -1 0 0x00002000 - 0x0000201f (0x20) IX[B] [20] -1 0 0x00001ce0 - 0x00001cff (0x20) IX[B] [21] -1 0 0x00001cc0 - 0x00001cdf (0x20) IX[B] [22] -1 0 0x00003000 - 0x000030ff (0x100) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xe8204000 - 0xe8204fff (0x1000) MX[B] [1] -1 0 0xe8205800 - 0xe82058ff (0x100) MX[B] [2] -1 0 0xe8200000 - 0xe8203fff (0x4000) MX[B] [3] -1 0 0xe8205000 - 0xe82057ff (0x800) MX[B] [4] -1 0 0xe8000800 - 0xe80008ff (0x100) MX[B] [5] -1 0 0xe8000c00 - 0xe8000dff (0x200) MX[B] [6] -1 0 0x40000000 - 0x400003ff (0x400) MX[B] [7] -1 0 0xe8000000 - 0xe80003ff (0x400) MX[B] [8] -1 0 0xd0000000 - 0xcfffffff (0x0) MX[B]O [9] -1 0 0xe8100000 - 0xe810ffff (0x10000) MX[B](B) [10] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B](B) [11] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [12] -1 0 0x00001c00 - 0x00001c7f (0x80) IX[B] [13] -1 0 0x00001800 - 0x000018ff (0x100) IX[B] [14] -1 0 0x00001c80 - 0x00001cbf (0x40) IX[B] [15] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [16] -1 0 0x00002040 - 0x0000205f (0x20) IX[B] [17] -1 0 0x00002060 - 0x0000206f (0x10) IX[B] [18] -1 0 0x00002020 - 0x0000203f (0x20) IX[B] [19] -1 0 0x00002000 - 0x0000201f (0x20) IX[B] [20] -1 0 0x00001ce0 - 0x00001cff (0x20) IX[B] [21] -1 0 0x00001cc0 - 0x00001cdf (0x20) IX[B] [22] -1 0 0x00003000 - 0x000030ff (0x100) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xe8204000 - 0xe8204fff (0x1000) MX[B] [6] -1 0 0xe8205800 - 0xe82058ff (0x100) MX[B] [7] -1 0 0xe8200000 - 0xe8203fff (0x4000) MX[B] [8] -1 0 0xe8205000 - 0xe82057ff (0x800) MX[B] [9] -1 0 0xe8000800 - 0xe80008ff (0x100) MX[B] [10] -1 0 0xe8000c00 - 0xe8000dff (0x200) MX[B] [11] -1 0 0x40000000 - 0x400003ff (0x400) MX[B] [12] -1 0 0xe8000000 - 0xe80003ff (0x400) MX[B] [13] -1 0 0xd0000000 - 0xcfffffff (0x0) MX[B]O [14] -1 0 0xe8100000 - 0xe810ffff (0x10000) MX[B](B) [15] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B](B) [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [17] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [18] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [19] -1 0 0x00001c00 - 0x00001c7f (0x80) IX[B] [20] -1 0 0x00001800 - 0x000018ff (0x100) IX[B] [21] -1 0 0x00001c80 - 0x00001cbf (0x40) IX[B] [22] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [23] -1 0 0x00002040 - 0x0000205f (0x20) IX[B] [24] -1 0 0x00002060 - 0x0000206f (0x10) IX[B] [25] -1 0 0x00002020 - 0x0000203f (0x20) IX[B] [26] -1 0 0x00002000 - 0x0000201f (0x20) IX[B] [27] -1 0 0x00001ce0 - 0x00001cff (0x20) IX[B] [28] -1 0 0x00001cc0 - 0x00001cdf (0x20) IX[B] [29] -1 0 0x00003000 - 0x000030ff (0x100) IX[B](B) (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "extmod" (II) Reloading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "fglrx" (II) Loading /usr/X11R6/lib/modules/drivers/fglrx_drv.o (II) Module fglrx: vendor="Fire GL - ATI Research GmbH, Germany" compiled for 4.3.0.1, module version = 3.9.0 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "synaptics" (II) Loading /usr/X11R6/lib/modules/input/synaptics_drv.o (II) Module synaptics: vendor="The XFree86 Project" compiled for 4.2.0, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.3 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) FireGL8700/8800: Driver for chipset: ATI RV250 Id (R9000), ATI RV250 Ie (R9000), ATI RV250 If (R9000), ATI RV250 Ig (R9000), ATI RV250 Ld (M9), ATI RV250 Le (M9), ATI RV250 Lf (M9), ATI RV250 Lg (M9), ATI RV280 5960 (R9200 PRO), ATI RV280 Ya (R9200LE), ATI RV250SE Yd (R9200SE), ATI RV250 5C61 (M9+), ATI RV250 5C63 (M9+), ATI R200 QH (R8500), ATI R200 QL (R8500), ATI R200 QM (R9100), ATI R200 QT (R8500), ATI R200 QU (R9100), ATI R200 BB (R8500), ATI RV350 AP (R9600), ATI RV350SE AQ (R9600SE), ATI RV350 AR (R9600 PRO), ATI RV350 NP (M10), ATI R300 AD (R9500), ATI R300 AE (R9500), ATI R300 AF (R9500), ATI R300 AG (Fire GL Z1/X1), ATI R300 ND (R9700 PRO), ATI R300 NE (R9700/R9500 PRO), ATI R300 NF (R9600 TX), ATI R300 NG (Fire GL X1), ATI R350SE AH (R9800SE), ATI R350 AK (Fire GL unknown), ATI RV350 AT (Fire GL T2), ATI RV350 AU (Fire GL T2), ATI RV350 AV (Fire GL T2), ATI RV350 AW (Fire GL T2), ATI R350 NH (R9800), ATI R350LE NI (R9800LE), ATI R350 NJ (R9800), ATI R350 NK (Fire GL X2), ATI RV350 NT (WS/M10) (II) Primary Device is: PCI 01:00:0 (--) Assigning device section with no busID to primary device (--) Chipset ATI RV350 NP (M10) found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xe8204000 - 0xe8204fff (0x1000) MX[B] [6] -1 0 0xe8205800 - 0xe82058ff (0x100) MX[B] [7] -1 0 0xe8200000 - 0xe8203fff (0x4000) MX[B] [8] -1 0 0xe8205000 - 0xe82057ff (0x800) MX[B] [9] -1 0 0xe8000800 - 0xe80008ff (0x100) MX[B] [10] -1 0 0xe8000c00 - 0xe8000dff (0x200) MX[B] [11] -1 0 0x40000000 - 0x400003ff (0x400) MX[B] [12] -1 0 0xe8000000 - 0xe80003ff (0x400) MX[B] [13] -1 0 0xd0000000 - 0xcfffffff (0x0) MX[B]O [14] -1 0 0xe8100000 - 0xe810ffff (0x10000) MX[B](B) [15] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B](B) [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [17] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [18] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [19] -1 0 0x00001c00 - 0x00001c7f (0x80) IX[B] [20] -1 0 0x00001800 - 0x000018ff (0x100) IX[B] [21] -1 0 0x00001c80 - 0x00001cbf (0x40) IX[B] [22] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [23] -1 0 0x00002040 - 0x0000205f (0x20) IX[B] [24] -1 0 0x00002060 - 0x0000206f (0x10) IX[B] [25] -1 0 0x00002020 - 0x0000203f (0x20) IX[B] [26] -1 0 0x00002000 - 0x0000201f (0x20) IX[B] [27] -1 0 0x00001ce0 - 0x00001cff (0x20) IX[B] [28] -1 0 0x00001cc0 - 0x00001cdf (0x20) IX[B] [29] -1 0 0x00003000 - 0x000030ff (0x100) IX[B](B) (II) fglrx(0): pEnt->device->identifier=0x81f93e8 (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xe8204000 - 0xe8204fff (0x1000) MX[B] [6] -1 0 0xe8205800 - 0xe82058ff (0x100) MX[B] [7] -1 0 0xe8200000 - 0xe8203fff (0x4000) MX[B] [8] -1 0 0xe8205000 - 0xe82057ff (0x800) MX[B] [9] -1 0 0xe8000800 - 0xe80008ff (0x100) MX[B] [10] -1 0 0xe8000c00 - 0xe8000dff (0x200) MX[B] [11] -1 0 0x40000000 - 0x400003ff (0x400) MX[B] [12] -1 0 0xe8000000 - 0xe80003ff (0x400) MX[B] [13] -1 0 0xd0000000 - 0xcfffffff (0x0) MX[B]O [14] -1 0 0xe8100000 - 0xe810ffff (0x10000) MX[B](B) [15] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B](B) [16] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [17] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [18] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [19] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [20] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [21] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [22] -1 0 0x00001c00 - 0x00001c7f (0x80) IX[B] [23] -1 0 0x00001800 - 0x000018ff (0x100) IX[B] [24] -1 0 0x00001c80 - 0x00001cbf (0x40) IX[B] [25] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [26] -1 0 0x00002040 - 0x0000205f (0x20) IX[B] [27] -1 0 0x00002060 - 0x0000206f (0x10) IX[B] [28] -1 0 0x00002020 - 0x0000203f (0x20) IX[B] [29] -1 0 0x00002000 - 0x0000201f (0x20) IX[B] [30] -1 0 0x00001ce0 - 0x00001cff (0x20) IX[B] [31] -1 0 0x00001cc0 - 0x00001cdf (0x20) IX[B] [32] -1 0 0x00003000 - 0x000030ff (0x100) IX[B](B) [33] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [34] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) fglrx(0): === [R200PreInit] === begin, [s] (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) fglrx(0): PCI bus 1 card 0 func 0 (**) fglrx(0): Depth 24, (--) framebuffer bpp 32 (II) fglrx(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) (==) fglrx(0): Default visual is TrueColor (**) fglrx(0): Option "OpenGLOverlay" "off" (**) fglrx(0): Option "VideoOverlay" "on" (**) fglrx(0): Option "UseInternalAGPGART" "no" (==) fglrx(0): Qbs disabled (==) fglrx(0): RGB weight 888 (II) fglrx(0): Using 8 bits per RGB (8 bit DAC) (==) fglrx(0): Gamma Correction for I is 0x06419064 (==) fglrx(0): Gamma Correction for II is 0x06419064 (==) fglrx(0): Buffer Tiling is ON (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) fglrx(0): initializing int10 (II) fglrx(0): Primary V_BIOS segment is: 0xc000 (--) fglrx(0): Chipset: "ATI RV350 NP (M10)" (Chipset = 0x4e50) (--) fglrx(0): (PciSubVendor = 0x1558, PciSubDevice = 0x0500) (--) fglrx(0): board vendor info: third party grafics adapter - NOT original ATI (--) fglrx(0): Linear framebuffer (phys) at 0xf0000000 (--) fglrx(0): MMIO registers at 0xe8100000 (--) fglrx(0): ChipExtRevID = 0x00 (--) fglrx(0): ChipIntRevID = 0x0C (--) fglrx(0): VideoRAM: 131072 kByte (64-bit SDR SDRAM) (WW) fglrx(0): board is an unknown third party board, chipset is supported (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.2.0 ABI class: XFree86 Video Driver, version 0.6 (II) fglrx(0): I2C bus "DDC" initialized. (II) fglrx(0): Connector Layout from BIOS -------- (II) fglrx(0): Connector1: DDCType-3, DACType-0, TMDSType--1, ConnectorType-2 (II) fglrx(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) fglrx(0): I2C device "DDC:ddc2" removed. (II) fglrx(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) fglrx(0): I2C device "DDC:ddc2" removed. (II) fglrx(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) fglrx(0): I2C device "DDC:ddc2" removed. (II) fglrx(0): DDC detected on DDCType 3 with Monitor Type 0 (II) fglrx(0): Primary head: Monitor -- LVDS Connector -- None DAC Type -- Unknown TMDS Type -- NONE DDC Type -- NONE (II) fglrx(0): Secondary head: Monitor -- NONE Connector -- VGA DAC Type -- Primary TMDS Type -- NONE DDC Type -- VGA_DDC (II) fglrx(0): (II) fglrx(0): DesktopSetup 0x0000 (II) fglrx(0): Panel ID string: LG 1600x1200 (II) fglrx(0): Panel Size from BIOS: 1600x1200 (==) fglrx(0): PseudoColor visuals disabled (==) fglrx(0): Overlay disabled (**) fglrx(0): Overlay disabled (II) fglrx(0): PLL parameters: rf=2700 rd=6 min=20000 max=35000; xclk=23600 (==) fglrx(0): Using gamma correction (1.0, 1.0, 1.0) (==) fglrx(0): Center Mode is disabled (==) fglrx(0): TMDS coherent mode is enabled (II) fglrx(0): Valid mode using on-chip RMX: 1600x1200 (II) fglrx(0): Valid mode using on-chip RMX: 800x600 (II) fglrx(0): Total 2 valid mode(s) found. (--) fglrx(0): Virtual size is 1600x1200 (pitch 1600) (**) fglrx(0): *Mode "1600x1200": 162.0 MHz (scaled from 0.0 MHz), 75.0 kHz, 60.1 Hz (II) fglrx(0): Modeline "1600x1200" 162.00 1600 1656 1848 2160 1200 1202 1205 1248 (**) fglrx(0): *Mode "800x600": 162.0 MHz (scaled from 0.0 MHz), 75.0 kHz, 60.1 Hz (II) fglrx(0): Modeline "800x600" 162.00 800 1656 1848 2160 600 1202 1205 1248 (**) fglrx(0): Display dimensions: (307, 230) mm (**) fglrx(0): DPI set to (132, 132) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (==) fglrx(0): NoAccel = NO (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (==) fglrx(0): HPV inactive (==) fglrx(0): FSAA enabled: NO (==) fglrx(0): FSAA Gamma enabled (==) fglrx(0): FSAA Multisample Position is fix (==) fglrx(0): NoDRI = NO (II) Loading sub module "fglrxdrm" (II) LoadModule: "fglrxdrm" (II) Loading /usr/X11R6/lib/modules/linux/libfglrxdrm.a (II) Module fglrxdrm: vendor="Fire GL - ATI Research GmbH, Germany" compiled for 4.3.0.1, module version = 3.9.0 ABI class: XFree86 Server Extension, version 0.2 (II) fglrx(0): Depth moves disabled by default (==) fglrx(0): Capabilities: 0x00000000 (==) fglrx(0): cpuFlags: 0x8000001d (==) fglrx(0): cpuSpeedMHz: 0x00000af0 (==) fglrx(0): OpenGL ClientDriverName: "fglrx_dri.so" (**) fglrx(0): using built in AGPGART module: no (==) fglrx(0): UseFastTLS=0 (==) fglrx(0): BlockSignalsOnLock=1 (==) fglrx(0): EnablePrivateBackZ = NO (II) fglrx(0): using CAIL version [ATI LIB=CAIL.LIB,IA32,2.0024] (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0xe8100000 - 0xe810ffff (0x10000) MX[B] [1] 0 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B] [2] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [3] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [4] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [5] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [6] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [7] -1 0 0xe8204000 - 0xe8204fff (0x1000) MX[B] [8] -1 0 0xe8205800 - 0xe82058ff (0x100) MX[B] [9] -1 0 0xe8200000 - 0xe8203fff (0x4000) MX[B] [10] -1 0 0xe8205000 - 0xe82057ff (0x800) MX[B] [11] -1 0 0xe8000800 - 0xe80008ff (0x100) MX[B] [12] -1 0 0xe8000c00 - 0xe8000dff (0x200) MX[B] [13] -1 0 0x40000000 - 0x400003ff (0x400) MX[B] [14] -1 0 0xe8000000 - 0xe80003ff (0x400) MX[B] [15] -1 0 0xd0000000 - 0xcfffffff (0x0) MX[B]O [16] -1 0 0xe8100000 - 0xe810ffff (0x10000) MX[B](B) [17] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B](B) [18] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [19] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [20] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [21] 0 0 0x00003000 - 0x000030ff (0x100) IX[B] [22] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [23] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [24] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [25] -1 0 0x00001c00 - 0x00001c7f (0x80) IX[B] [26] -1 0 0x00001800 - 0x000018ff (0x100) IX[B] [27] -1 0 0x00001c80 - 0x00001cbf (0x40) IX[B] [28] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [29] -1 0 0x00002040 - 0x0000205f (0x20) IX[B] [30] -1 0 0x00002060 - 0x0000206f (0x10) IX[B] [31] -1 0 0x00002020 - 0x0000203f (0x20) IX[B] [32] -1 0 0x00002000 - 0x0000201f (0x20) IX[B] [33] -1 0 0x00001ce0 - 0x00001cff (0x20) IX[B] [34] -1 0 0x00001cc0 - 0x00001cdf (0x20) IX[B] [35] -1 0 0x00003000 - 0x000030ff (0x100) IX[B](B) [36] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [37] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) fglrx(0): UMM area: 0xf0953000 (size=0x076ad000) (II) fglrx(0): driver needs XFree86 version: 4.3.x (II) fglrx(0): detected XFree86 version: 4.3.0 (II) Loading extension ATIFGLRXDRI (II) fglrx(0): doing DRIScreenInit drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: Open failed drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: Open failed [drm] failed to load kernel module "fglrx" (II) fglrx(0): [drm] drmOpen failed (EE) fglrx(0): DRIScreenInit failed! (WW) fglrx(0): *********************************************** (WW) fglrx(0): * DRI initialization failed! * (WW) fglrx(0): * (maybe driver kernel module missing or bad) * (WW) fglrx(0): * 2D acceleraton available (MMIO) * (WW) fglrx(0): * no 3D acceleration available * (WW) fglrx(0): ********************************************* * (II) fglrx(0): FBADPhys: 0xf0000000 FBMappedSize: 0x08000000 (==) fglrx(0): Write-combining range (0xf0000000,0x8000000) (II) fglrx(0): FBMM initialized for area (0,0)-(1600,8191) (II) fglrx(0): FBMM auto alloc for area (0,0)-(1600,1200) (front color buffer - assumption) (==) fglrx(0): Backing store disabled (==) fglrx(0): Silken mouse enabled (II) fglrx(0): Using hardware cursor (scanline 1200) (II) fglrx(0): Largest offscreen area available: 1600 x 6988 (**) Option "dpms" (**) fglrx(0): DPMS enabled (II) fglrx(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles Solid Horizontal and Vertical Lines Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 32 256x256 slots 16 512x512 slots (II) fglrx(0): Acceleration enabled (II) fglrx(0): Direct rendering disabled (II) Loading extension FGLRXEXTENSION (II) Loading extension ATITVOUT (==) RandR enabled (II) Setting vga for screen 0. (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (II) Synaptics touchpad driver version 0.13.5 (--) Touchpad Mouse auto-dev sets device to /dev/input/event1 (**) Option "Device" "/dev/input/event1" (**) Option "LeftEdge" "1700" (**) Option "RightEdge" "5300" (**) Option "TopEdge" "1700" (**) Option "BottomEdge" "4200" (**) Option "FingerLow" "25" (**) Option "FingerHigh" "30" (**) Option "MaxTapTime" "180" (**) Option "MaxTapMove" "220" (**) Option "VertScrollDelta" "100" (--) Touchpad Mouse synaptics touchpad found (**) Option "CorePointer" (**) Touchpad Mouse: Core Pointer (**) Option "Protocol" "ImPS/2" (**) Generic Mouse: Protocol: "ImPS/2" (**) Option "SendCoreEvents" "true" (**) Generic Mouse: always reports core events (**) Option "Device" "/dev/input/mice" (**) Generic Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Generic Mouse: ZAxisMapping: buttons 4 and 5 (**) Generic Mouse: Buttons: 5 (II) XINPUT: Adding extended input device "Generic Mouse" (type: MOUSE) (II) XINPUT: Adding extended input device "Touchpad Mouse" (type: MOUSE) Synaptics DeviceInit called SynapticsCtrl called. Synaptics DeviceOn called (--) Touchpad Mouse synaptics touchpad found (II) Generic Mouse: ps2EnableDataReporting: succeeded Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 SynapticsCtrl called. SynapticsCtrl called. GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 SetGrabKeysState - disabled GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 GetModeLine - scrn: 0 clock: 162000 GetModeLine - hdsp: 1600 hbeg: 1656 hend: 1848 httl: 2160 vdsp: 1200 vbeg: 1202 vend: 1205 vttl: 1248 flags: -2147483648 SetGrabKeysState - enabled xresprobe-0.4.24ubuntu9/tests/log-r128-1024x768-dave0000644000000000000000000007672710214367723016362 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Ubuntu 4.3.0.dfsg.1-6ubuntu7 20040820130619 root@false) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.6.7-power4 ppc [ELF] Build Date: 20 August 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.7-powerpc (buildd@ross) (gcc version 3.3.4 (Debian 1:3.3.4-5ubuntu1)) #1 Thu Aug 12 00:13:19 UTC 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Wed Aug 25 11:15:50 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Generic Laptop LCD" (**) | |-->Device "ATI Technologies, Inc. Rage Mobility M3 AGP 2x" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "macintosh" (**) XKB: model: "macintosh" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (II) Open APM successful (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:0b:0: chip 106b,0027 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 00:10:0: chip 1002,4c46 card 1002,4c46 rev 02 class 03,00,00 hdr 00 (II) PCI: 01:0b:0: chip 106b,0028 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 01:17:0: chip 106b,0025 card 0000,0000 rev 00 class ff,00,00 hdr 00 (II) PCI: 01:18:0: chip 106b,0026 card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:19:0: chip 106b,0026 card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 02:0b:0: chip 106b,0029 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 02:0e:0: chip 106b,0030 card 106b,0030 rev 00 class 0c,00,10 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:11:0), (0,0,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 1: bridge is at (1:11:0), (1,1,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 2: bridge is at (2:11:0), (2,2,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 2 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (--) PCI:*(0:16:0) ATI Technologies Inc Rage Mobility M3 AGP 2x rev 2, Mem @ 0x94000000/26, 0x90000000/14, I/O @ 0x0400/8 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) Active PCI resource ranges: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [2] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [3] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [4] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [5] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [6] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [2] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [3] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [4] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [5] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [6] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) All system resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [4] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [5] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [6] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [7] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [8] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [9] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [10] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "ati" (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.o (II) Module ati: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) ATI: ATI driver (version 6.5.5) for chipset: ati (II) R128: Driver for ATI Rage 128 chipsets: ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), ATI Rage 128 Pro GL PA (AGP?), ATI Rage 128 Pro GL PB (AGP?), ATI Rage 128 Pro GL PC (AGP?), ATI Rage 128 Pro GL PD (PCI), ATI Rage 128 Pro GL PE (AGP?), ATI Rage 128 Pro GL PF (AGP), ATI Rage 128 Pro VR PG (AGP?), ATI Rage 128 Pro VR PH (AGP?), ATI Rage 128 Pro VR PI (AGP?), ATI Rage 128 Pro VR PJ (AGP?), ATI Rage 128 Pro VR PK (AGP?), ATI Rage 128 Pro VR PL (AGP?), ATI Rage 128 Pro VR PM (AGP?), ATI Rage 128 Pro VR PN (AGP?), ATI Rage 128 Pro VR PO (AGP?), ATI Rage 128 Pro VR PP (PCI), ATI Rage 128 Pro VR PQ (AGP?), ATI Rage 128 Pro VR PR (PCI), ATI Rage 128 Pro VR PS (AGP?), ATI Rage 128 Pro VR PT (AGP?), ATI Rage 128 Pro VR PU (AGP?), ATI Rage 128 Pro VR PV (AGP?), ATI Rage 128 Pro VR PW (AGP?), ATI Rage 128 Pro VR PX (AGP?), ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (AGP?), ATI Rage 128 4X SF (AGP?), ATI Rage 128 4X SG (AGP?), ATI Rage 128 4X SH (AGP?), ATI Rage 128 4X SK (AGP?), ATI Rage 128 4X SL (AGP?), ATI Rage 128 4X SM (AGP), ATI Rage 128 4X SN (AGP?), ATI Rage 128 Pro ULTRA TF (AGP), ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), ATI Rage 128 Pro ULTRA TU (AGP?) (II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), ATI Radeon Mobility M7 LW (AGP), ATI Mobility FireGL 7800 M7 LX (AGP), ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon IGP330M/340M/350M (U2) 4337, ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), ATI Radeon Mobility 9000 (M9) Lf (AGP), ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9100 IGP (A5) 5834, ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9200PRO 5960 (AGP), ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), ATI Radeon 9200SE 5964 (AGP), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9700 NF (AGP), ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI FireGL RV360 AV (AGP), ATI Radeon Mobility 9600 (M10) NP (AGP), ATI Radeon Mobility 9600 (M10) NQ (AGP), ATI Radeon Mobility 9600 (M11) NR (AGP), ATI Radeon Mobility 9600 (M10) NS (AGP), ATI FireGL Mobility T2 (M10) NT (AGP), ATI FireGL Mobility T2 (M11) NV (AGP), ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP) (II) Primary Device is: PCI 00:10:0 (II) ATI: Candidate "Device" section "ATI Technologies, Inc. Rage Mobility M3 AGP 2x". (--) Chipset ATI Rage 128 Mobility M3 LF (AGP) found (II) Loading sub module "r128" (II) LoadModule: "r128" (II) Loading /usr/X11R6/lib/modules/drivers/r128_drv.o (II) Module r128: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 4.0.1 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [4] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [5] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [6] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [7] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [8] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [9] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [10] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) resource ranges after probing: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [4] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [5] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [6] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [7] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [8] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [9] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [10] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [13] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) [14] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [15] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) R128(0): PCI bus 0 card 16 func 0 (**) R128(0): Depth 24, (--) framebuffer bpp 32 (II) R128(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) (==) R128(0): Default visual is TrueColor (**) R128(0): Option "UseFBDev" "true" (==) R128(0): RGB weight 888 (II) R128(0): Using 8 bits per RGB (8 bit DAC) (**) R128(0): Using framebuffer device (II) Loading sub module "fbdevhw" (II) LoadModule: "fbdevhw" (II) Loading /usr/X11R6/lib/modules/linux/libfbdevhw.a (II) Module fbdevhw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.0.2 ABI class: XFree86 Video Driver, version 0.6 (--) R128(0): Chipset: "ATI Rage 128 Mobility M3 LF (AGP)" (ChipID = 0x4c46) (--) R128(0): Linear framebuffer at 0x94000000 (--) R128(0): MMIO registers at 0x90000000 (II) R128(0): Option "Display" ignored (framebuffer device determines display type) (--) R128(0): VideoRAM: 8192 kByte (128-bit SDR SGRAM 1:1) (WW) R128(0): Video BIOS not detected in PCI space! (WW) R128(0): Attempting to read Video BIOS from legacy ISA space! (WW) R128(0): Video BIOS not found! (WW) R128(0): Can't determine panel dimensions, and none specified. Disabling programming of FP registers. (II) R128(0): PLL parameters: rf=2950 rd=59 min=12500 max=25000; xclk=10500 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (==) R128(0): Using gamma correction (1.0, 1.0, 1.0) (II) R128(0): Generic Laptop LCD: Using hsync range of 28.00-49.00 kHz (II) R128(0): Generic Laptop LCD: Using vrefresh range of 43.00-72.00 Hz (II) R128(0): Clock range: 12.50 to 250.00 MHz (II) R128(0): Not using default mode "640x350" (vrefresh out of range) (II) R128(0): Not using default mode "320x175" (vrefresh out of range) (II) R128(0): Not using default mode "640x400" (vrefresh out of range) (II) R128(0): Not using default mode "320x200" (vrefresh out of range) (II) R128(0): Not using default mode "720x400" (vrefresh out of range) (II) R128(0): Not using default mode "360x200" (vrefresh out of range) (II) R128(0): Not using default mode "640x480" (vrefresh out of range) (II) R128(0): Not using default mode "320x240" (vrefresh out of range) (II) R128(0): Not using default mode "640x480" (vrefresh out of range) (II) R128(0): Not using default mode "320x240" (vrefresh out of range) (II) R128(0): Not using default mode "640x480" (vrefresh out of range) (II) R128(0): Not using default mode "320x240" (vrefresh out of range) (II) R128(0): Not using default mode "800x600" (vrefresh out of range) (II) R128(0): Not using default mode "400x300" (vrefresh out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "400x300" (hsync out of range) (II) R128(0): Not using default mode "1024x768" (vrefresh out of range) (II) R128(0): Not using default mode "512x384" (vrefresh out of range) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "512x384" (hsync out of range) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "512x384" (hsync out of range) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "512x384" (hsync out of range) (II) R128(0): Not using default mode "1152x864" (hsync out of range) (II) R128(0): Not using default mode "576x432" (hsync out of range) (II) R128(0): Not using default mode "1280x960" (hsync out of range) (II) R128(0): Not using default mode "640x480" (hsync out of range) (II) R128(0): Not using default mode "1280x960" (hsync out of range) (II) R128(0): Not using default mode "640x480" (hsync out of range) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (hsync out of range) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (hsync out of range) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) R128(0): Not using default mode "896x672" (hsync out of range) (II) R128(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) R128(0): Not using default mode "896x672" (hsync out of range) (II) R128(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) R128(0): Not using default mode "928x696" (hsync out of range) (II) R128(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) R128(0): Not using default mode "928x696" (hsync out of range) (II) R128(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) R128(0): Not using default mode "960x720" (hsync out of range) (II) R128(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) R128(0): Not using default mode "960x720" (hsync out of range) (II) R128(0): Not using default mode "832x624" (hsync out of range) (II) R128(0): Not using default mode "416x312" (hsync out of range) (II) R128(0): Not using default mode "1400x1050" (hsync out of range) (II) R128(0): Not using default mode "700x525" (hsync out of range) (II) R128(0): Not using default mode "1400x1050" (hsync out of range) (II) R128(0): Not using default mode "700x525" (hsync out of range) (II) R128(0): Not using default mode "1600x1024" (hsync out of range) (II) R128(0): Not using default mode "800x512" (hsync out of range) (II) R128(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) R128(0): Not using default mode "960x720" (hsync out of range) (II) R128(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "1152x768" (width too large for virtual size) (--) R128(0): Virtual size is 1024x768 (pitch 1024) (**) R128(0): *Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz (II) R128(0): Modeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (**) R128(0): *Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) R128(0): Modeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (**) R128(0): *Default mode "640x480": 25.2 MHz, 31.5 kHz, 60.0 Hz (II) R128(0): Modeline "640x480" 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (**) R128(0): Default mode "800x600": 40.0 MHz, 37.9 kHz, 60.3 Hz (II) R128(0): Modeline "800x600" 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (**) R128(0): Default mode "800x600": 36.0 MHz, 35.2 kHz, 56.2 Hz (II) R128(0): Modeline "800x600" 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (**) R128(0): Default mode "576x384": 32.5 MHz, 44.2 kHz, 54.8 Hz (D) (II) R128(0): Modeline "576x384" 32.50 576 589 657 736 384 385 388 403 doublescan +hsync +vsync (**) R128(0): Default mode "512x384": 32.5 MHz, 48.4 kHz, 60.0 Hz (D) (II) R128(0): Modeline "512x384" 32.50 512 524 592 672 384 385 388 403 doublescan -hsync -vsync (**) R128(0): Default mode "400x300": 25.0 MHz, 48.1 kHz, 72.2 Hz (D) (II) R128(0): Modeline "400x300" 25.00 400 428 488 520 300 318 321 333 doublescan +hsync +vsync (**) R128(0): Default mode "400x300": 20.0 MHz, 37.9 kHz, 60.3 Hz (D) (II) R128(0): Modeline "400x300" 20.00 400 420 484 528 300 300 302 314 doublescan +hsync +vsync (**) R128(0): Default mode "400x300": 18.0 MHz, 35.2 kHz, 56.3 Hz (D) (II) R128(0): Modeline "400x300" 18.00 400 412 448 512 300 300 301 312 doublescan +hsync +vsync (**) R128(0): Default mode "320x240": 12.6 MHz, 31.5 kHz, 60.1 Hz (D) (II) R128(0): Modeline "320x240" 12.60 320 328 376 400 240 245 246 262 doublescan -hsync -vsync (==) R128(0): DPI set to (75, 75) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "shadowfb" (II) LoadModule: "shadowfb" (II) Loading /usr/X11R6/lib/modules/libshadowfb.a (II) Module shadowfb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) R128(0): Page flipping disabled (!!) R128(0): For information on using the multimedia capabilities of this adapter, please see http://gatos.sf.net. (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0x90000000 - 0x90003fff (0x4000) MS[B] [1] 0 0 0x94000000 - 0x97ffffff (0x4000000) MS[B] [2] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [4] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [5] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [6] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [7] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [8] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [9] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [10] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) [11] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) [12] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) [13] 0 0 0x00000400 - 0x000004ff (0x100) IS[B] [14] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [15] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [16] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) [17] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [18] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (WW) R128(0): Static buffer allocation failed -- need at least 9216 kB video memory (II) R128(0): Memory manager initialized to (0,0) (1024,2048) (II) R128(0): Reserved area from (0,768) to (1024,770) (II) R128(0): Largest offscreen area available: 1024 x 1278 (II) R128(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Indirect CPU to Screen color expansion Solid Lines Dashed Lines Scanline Image Writes Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 10 256x256 slots (II) R128(0): Acceleration enabled (==) R128(0): Backing store disabled (==) R128(0): Silken mouse enabled (II) R128(0): Using hardware cursor (scanline 3080) (II) R128(0): Largest offscreen area available: 1024 x 1276 (**) Option "dpms" (**) R128(0): DPMS enabled (II) R128(0): Direct rendering disabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (**) Option "Emulate3Buttons" "true" (**) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Configured Mouse: ZAxisMapping: buttons 4 and 5 (**) Configured Mouse: Buttons: 5 (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) Server_Terminate keybinding not found (II) Configured Mouse: ps2EnableDataReporting: succeeded Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded GetModeLine - scrn: 0 clock: 65000 GetModeLine - hdsp: 1024 hbeg: 1048 hend: 1184 httl: 1344 vdsp: 768 vbeg: 771 vend: 777 vttl: 806 flags: 10 (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded xresprobe-0.4.24ubuntu9/tests/log-mach64-1024x7680000644000000000000000000020073710214367723016021 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Ubuntu 4.3.0.dfsg.1-5ubuntu1 20040629130816 root@rockhopper.warthogs.hbd.com) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.4.26-es i686 [ELF] Build Date: 29 June 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.7 (daniels@catsby) (gcc version 3.3.4 (Debian 1:3.3.4-3)) #1 Sun Jul 25 14:54:18 EDT 2004 T Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Mon Jul 26 20:18:03 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Generic Monitor" (**) | |-->Device "ATI Mach64 AGP" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "pc104" (**) XKB: model: "pc104" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Synaptics Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: Probing config type using method 1 (II) PCI: Config type is 1 (II) PCI: stages = 0x03, oldVal1 = 0x00000000, mode1Res1 = 0x80000000 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,7190 card 0000,0000 rev 03 class 06,00,00 hdr 00 (II) PCI: 00:01:0: chip 8086,7191 card 0000,0000 rev 03 class 06,04,00 hdr 01 (II) PCI: 00:07:0: chip 8086,7110 card 0000,0000 rev 02 class 06,80,00 hdr 80 (II) PCI: 00:07:1: chip 8086,7111 card 0000,0000 rev 01 class 01,01,80 hdr 00 (II) PCI: 00:07:2: chip 8086,7112 card 0000,0000 rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:07:3: chip 8086,7113 card 0000,0000 rev 03 class 06,80,00 hdr 00 (II) PCI: 00:0a:0: chip 104c,ac51 card 4000,0000 rev 00 class 06,07,00 hdr 82 (II) PCI: 00:0a:1: chip 104c,ac51 card 4800,0000 rev 00 class 06,07,00 hdr 82 (II) PCI: 00:0b:0: chip 10b7,6055 card 10b7,6256 rev 10 class 02,00,00 hdr 80 (II) PCI: 00:0b:1: chip 10b7,1007 card 10b7,6158 rev 10 class 07,80,00 hdr 00 (II) PCI: 00:0d:0: chip 125d,1998 card 103c,0010 rev 00 class 04,01,00 hdr 00 (II) PCI: 01:00:0: chip 1002,4c4d card 103c,0010 rev 64 class 03,00,00 hdr 00 (II) PCI: 02:00:0: chip 14e4,4320 card 1799,7010 rev 03 class 02,80,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (0,0,6), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-PCI bridge: (II) Bus 1: bridge is at (0:1:0), (0,1,1), BCTRL: 0x008c (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00009000 - 0x000090ff (0x100) IX[B] [1] -1 0 0x00009400 - 0x000094ff (0x100) IX[B] [2] -1 0 0x00009800 - 0x000098ff (0x100) IX[B] [3] -1 0 0x00009c00 - 0x00009cff (0x100) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0xf4100000 - 0xf5ffffff (0x1f00000) MX[B] (II) PCI-to-CardBus bridge: (II) Bus 2: bridge is at (0:10:0), (0,2,5), BCTRL: 0x0500 (VGA_EN is cleared) (II) Bus 2 I/O range: [0] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [1] -1 0 0x00004400 - 0x000044ff (0x100) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0x10800000 - 0x10bfffff (0x400000) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0x10400000 - 0x107fffff (0x400000) MX[B] (II) PCI-to-CardBus bridge: (II) Bus 6: bridge is at (0:10:1), (0,6,9), BCTRL: 0x05c0 (VGA_EN is cleared) (II) Bus 6 I/O range: [0] -1 0 0x00004800 - 0x000048ff (0x100) IX[B] [1] -1 0 0x00004c00 - 0x00004cff (0x100) IX[B] (II) Bus 6 non-prefetchable memory range: [0] -1 0 0x11000000 - 0x113fffff (0x400000) MX[B] (II) Bus 6 prefetchable memory range: [0] -1 0 0x10c00000 - 0x10ffffff (0x400000) MX[B] (--) PCI:*(1:0:0) ATI Technologies Inc Rage Mobility P/M AGP 2x rev 100, Mem @ 0xf5000000/24, 0xf4100000/12, I/O @ 0x9000/8 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) PCI Memory resource overlap reduced 0xf8000000 from 0xfbffffff to 0xf7ffffff (II) Active PCI resource ranges: [0] -1 0 0x10800000 - 0x10801fff (0x2000) MX[B] [1] -1 0 0xf4000000 - 0xf4001fff (0x2000) MX[B] [2] -1 0 0xf4002800 - 0xf400287f (0x80) MX[B] [3] -1 0 0xf4002c00 - 0xf4002cff (0x100) MX[B] [4] -1 0 0xf4002000 - 0xf400207f (0x80) MX[B] [5] -1 0 0xf4002400 - 0xf400247f (0x80) MX[B] [6] -1 0 0xf8000000 - 0xf7ffffff (0x0) MX[B]O [7] -1 0 0xf4100000 - 0xf4100fff (0x1000) MX[B](B) [8] -1 0 0xf5000000 - 0xf5ffffff (0x1000000) MX[B](B) [9] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [10] -1 0 0x00001000 - 0x000010ff (0x100) IX[B] [11] -1 0 0x00001800 - 0x0000187f (0x80) IX[B] [12] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [13] -1 0 0x000018a0 - 0x000018af (0x10) IX[B] [14] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0x10800000 - 0x10801fff (0x2000) MX[B] [1] -1 0 0xf4000000 - 0xf4001fff (0x2000) MX[B] [2] -1 0 0xf4002800 - 0xf400287f (0x80) MX[B] [3] -1 0 0xf4002c00 - 0xf4002cff (0x100) MX[B] [4] -1 0 0xf4002000 - 0xf400207f (0x80) MX[B] [5] -1 0 0xf4002400 - 0xf400247f (0x80) MX[B] [6] -1 0 0xf8000000 - 0xf7ffffff (0x0) MX[B]O [7] -1 0 0xf4100000 - 0xf4100fff (0x1000) MX[B](B) [8] -1 0 0xf5000000 - 0xf5ffffff (0x1000000) MX[B](B) [9] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [10] -1 0 0x00001000 - 0x000010ff (0x100) IX[B] [11] -1 0 0x00001800 - 0x0000187f (0x80) IX[B] [12] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [13] -1 0 0x000018a0 - 0x000018af (0x10) IX[B] [14] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x107fffff (0x10700000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x107fffff (0x10700000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x10800000 - 0x10801fff (0x2000) MX[B] [6] -1 0 0xf4000000 - 0xf4001fff (0x2000) MX[B] [7] -1 0 0xf4002800 - 0xf400287f (0x80) MX[B] [8] -1 0 0xf4002c00 - 0xf4002cff (0x100) MX[B] [9] -1 0 0xf4002000 - 0xf400207f (0x80) MX[B] [10] -1 0 0xf4002400 - 0xf400247f (0x80) MX[B] [11] -1 0 0xf8000000 - 0xf7ffffff (0x0) MX[B]O [12] -1 0 0xf4100000 - 0xf4100fff (0x1000) MX[B](B) [13] -1 0 0xf5000000 - 0xf5ffffff (0x1000000) MX[B](B) [14] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [15] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [16] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [17] -1 0 0x00001000 - 0x000010ff (0x100) IX[B] [18] -1 0 0x00001800 - 0x0000187f (0x80) IX[B] [19] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [20] -1 0 0x000018a0 - 0x000018af (0x10) IX[B] [21] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "ati" (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.o (II) Module ati: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "synaptics" (II) Loading /usr/X11R6/lib/modules/input/synaptics_drv.o (II) Module synaptics: vendor="The XFree86 Project" compiled for 4.2.0, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.3 (II) ATI: ATI driver (version 6.5.5) for chipsets: ati, ativga (II) R128: Driver for ATI Rage 128 chipsets: ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), ATI Rage 128 Pro GL PA (AGP?), ATI Rage 128 Pro GL PB (AGP?), ATI Rage 128 Pro GL PC (AGP?), ATI Rage 128 Pro GL PD (PCI), ATI Rage 128 Pro GL PE (AGP?), ATI Rage 128 Pro GL PF (AGP), ATI Rage 128 Pro VR PG (AGP?), ATI Rage 128 Pro VR PH (AGP?), ATI Rage 128 Pro VR PI (AGP?), ATI Rage 128 Pro VR PJ (AGP?), ATI Rage 128 Pro VR PK (AGP?), ATI Rage 128 Pro VR PL (AGP?), ATI Rage 128 Pro VR PM (AGP?), ATI Rage 128 Pro VR PN (AGP?), ATI Rage 128 Pro VR PO (AGP?), ATI Rage 128 Pro VR PP (PCI), ATI Rage 128 Pro VR PQ (AGP?), ATI Rage 128 Pro VR PR (PCI), ATI Rage 128 Pro VR PS (AGP?), ATI Rage 128 Pro VR PT (AGP?), ATI Rage 128 Pro VR PU (AGP?), ATI Rage 128 Pro VR PV (AGP?), ATI Rage 128 Pro VR PW (AGP?), ATI Rage 128 Pro VR PX (AGP?), ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (AGP?), ATI Rage 128 4X SF (AGP?), ATI Rage 128 4X SG (AGP?), ATI Rage 128 4X SH (AGP?), ATI Rage 128 4X SK (AGP?), ATI Rage 128 4X SL (AGP?), ATI Rage 128 4X SM (AGP), ATI Rage 128 4X SN (AGP?), ATI Rage 128 Pro ULTRA TF (AGP), ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), ATI Rage 128 Pro ULTRA TU (AGP?) (II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), ATI Radeon Mobility M7 LW (AGP), ATI Mobility FireGL 7800 M7 LX (AGP), ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon IGP330M/340M/350M (U2) 4337, ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), ATI Radeon Mobility 9000 (M9) Lf (AGP), ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9100 IGP (A5) 5834, ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9200PRO 5960 (AGP), ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), ATI Radeon 9200SE 5964 (AGP), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9700 NF (AGP), ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI FireGL RV360 AV (AGP), ATI Radeon Mobility 9600 (M10) NP (AGP), ATI Radeon Mobility 9600 (M10) NQ (AGP), ATI Radeon Mobility 9600 (M11) NR (AGP), ATI Radeon Mobility 9600 (M10) NS (AGP), ATI FireGL Mobility T2 (M10) NT (AGP), ATI FireGL Mobility T2 (M11) NV (AGP), ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP) (II) Primary Device is: PCI 01:00:0 (II) ATI: Candidate "Device" section "ATI Mach64 AGP". (II) ATI: Shared PCI/AGP Mach64 in slot 1:0:0 detected. (II) ATI: Shared PCI/AGP Mach64 in slot 1:0:0 assigned to active "Device" section "ATI Mach64 AGP". (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x107fffff (0x10700000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x10800000 - 0x10801fff (0x2000) MX[B] [6] -1 0 0xf4000000 - 0xf4001fff (0x2000) MX[B] [7] -1 0 0xf4002800 - 0xf400287f (0x80) MX[B] [8] -1 0 0xf4002c00 - 0xf4002cff (0x100) MX[B] [9] -1 0 0xf4002000 - 0xf400207f (0x80) MX[B] [10] -1 0 0xf4002400 - 0xf400247f (0x80) MX[B] [11] -1 0 0xf8000000 - 0xf7ffffff (0x0) MX[B]O [12] -1 0 0xf4100000 - 0xf4100fff (0x1000) MX[B](B) [13] -1 0 0xf5000000 - 0xf5ffffff (0x1000000) MX[B](B) [14] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [15] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [16] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [17] -1 0 0x00001000 - 0x000010ff (0x100) IX[B] [18] -1 0 0x00001800 - 0x0000187f (0x80) IX[B] [19] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [20] -1 0 0x000018a0 - 0x000018af (0x10) IX[B] [21] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) (II) Loading sub module "atimisc" (II) LoadModule: "atimisc" (II) Loading /usr/X11R6/lib/modules/drivers/atimisc_drv.o (II) Module atimisc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x107fffff (0x10700000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x10800000 - 0x10801fff (0x2000) MX[B] [6] -1 0 0xf4000000 - 0xf4001fff (0x2000) MX[B] [7] -1 0 0xf4002800 - 0xf400287f (0x80) MX[B] [8] -1 0 0xf4002c00 - 0xf4002cff (0x100) MX[B] [9] -1 0 0xf4002000 - 0xf400207f (0x80) MX[B] [10] -1 0 0xf4002400 - 0xf400247f (0x80) MX[B] [11] -1 0 0xf8000000 - 0xf7ffffff (0x0) MX[B]O [12] -1 0 0xf4100000 - 0xf4100fff (0x1000) MX[B](B) [13] -1 0 0xf5000000 - 0xf5ffffff (0x1000000) MX[B](B) [14] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [15] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [16] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [17] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [18] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [19] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [20] -1 0 0x00001000 - 0x000010ff (0x100) IX[B] [21] -1 0 0x00001800 - 0x0000187f (0x80) IX[B] [22] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [23] -1 0 0x000018a0 - 0x000018af (0x10) IX[B] [24] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) [25] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [26] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (==) ATI(0): Chipset: "ati". (**) ATI(0): Depth 24, (--) framebuffer bpp 32 (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) ATI(0): Primary V_BIOS segment is: 0xc000 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Reloading /usr/X11R6/lib/modules/libvbe.a (II) ATI(0): VESA BIOS detected (II) ATI(0): VESA VBE Version 2.0 (II) ATI(0): VESA VBE Total Mem: 8128 kB (II) ATI(0): VESA VBE OEM: ATI MACH64 (II) ATI(0): VESA VBE OEM Software Rev: 1.0 (II) ATI(0): VESA VBE OEM Vendor: ATI Technologies Inc. (II) ATI(0): VESA VBE OEM Product: MACH64RM (II) ATI(0): VESA VBE OEM Product Rev: 01.00 (II) ATI(0): VESA VBE DDC supported (II) ATI(0): VESA VBE DDC Level none (II) ATI(0): VESA VBE DDC transfer in appr. 2 sec. (II) ATI(0): VESA VBE DDC read failed (II) ATI(0): BIOS Data: BIOSSize=0xC800, ROMTable=0x010C. (II) ATI(0): BIOS Data: ClockTable=0x0A16, FrequencyTable=0x09F0. (II) ATI(0): BIOS Data: LCDTable=0x0178, LCDPanelInfo=0xBFE8. (II) ATI(0): BIOS Data: VideoTable=0x0000, HardwareTable=0x0156. (II) ATI(0): BIOS Data: I2CType=0x0F, Tuner=0x00, Decoder=0x00, Audio=0x0F. (--) ATI(0): ATI 3D Rage Mobility graphics controller detected. (--) ATI(0): Chip type 4C4D "LM", version 4, foundry TSMC, class 0, revision 0x01. (--) ATI(0): AGP bus interface detected; block I/O base is 0x9000. (--) ATI(0): ATI Mach64 adapter detected. (!!) ATI(0): For information on using the multimedia capabilities of this adapter, please see http://gatos.sf.net. (--) ATI(0): Internal RAMDAC (subtype 1) detected. (==) ATI(0): RGB weight 888 (==) ATI(0): Default visual is TrueColor (==) ATI(0): Using gamma correction (1.0, 1.0, 1.0) (II) ATI(0): Using Mach64 accelerator CRTC. (--) ATI(0): 1024x768 panel (ID 24) detected. (--) ATI(0): Panel model Hitachi TX38D85VC1CAA. (--) ATI(0): Panel clock is 65.146 MHz. (II) ATI(0): Using digital flat panel interface. (II) ATI(0): Storing hardware cursor image at 0xF57FFC00. (II) ATI(0): Using 8 MB linear aperture at 0xF5000000. (!!) ATI(0): Virtual resolutions will be limited to 8191 kB due to linear aperture size and/or placement of hardware cursor image area. (II) ATI(0): Using Block 0 MMIO aperture at 0xF4100400. (II) ATI(0): Using Block 1 MMIO aperture at 0xF4100000. (==) ATI(0): Write-combining range (0xf5000000,0x800000) (II) ATI(0): MMIO write caching enabled. (--) ATI(0): 8192 kB of SDRAM (1:1) detected (using 8191 kB). (WW) ATI(0): Cannot shadow an accelerated frame buffer. (II) ATI(0): Engine XCLK 124.453 MHz; Refresh rate code 12. (--) ATI(0): Internal programmable clock generator detected. (--) ATI(0): Reference clock 29.500 MHz. (WW) ATI(0): Extraneous XF86Config HorizSync specification(s) ignored. (WW) ATI(0): Extraneous XF86Config VertRefresh specification(s) ignored. (II) ATI(0): Maximum clock: 230.00 MHz (II) ATI(0): Not using default mode "1152x864" (exceeds panel dimensions) (II) ATI(0): Not using default mode "576x432" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x960" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x480" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x960" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x480" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) ATI(0): Not using default mode "896x672" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) ATI(0): Not using default mode "896x672" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) ATI(0): Not using default mode "928x696" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) ATI(0): Not using default mode "928x696" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) ATI(0): Not using default mode "960x720" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) ATI(0): Not using default mode "960x720" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1152x768" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1400x1050" (exceeds panel dimensions) (II) ATI(0): Not using default mode "700x525" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1400x1050" (exceeds panel dimensions) (II) ATI(0): Not using default mode "700x525" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) ATI(0): Not using default mode "960x720" (exceeds panel dimensions) (II) ATI(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) ATI(0): Not using default mode "1024x768" (exceeds panel dimensions) (II) ATI(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) ATI(0): Not using default mode "1024x768" (exceeds panel dimensions) (II) ATI(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) ATI(0): Not using default mode "1024x768" (exceeds panel dimensions) (--) ATI(0): Virtual size is 1024x768 (pitch 1024) (**) ATI(0): *Default mode "1024x768": 94.5 MHz, 68.7 kHz, 85.0 Hz (II) ATI(0): Modeline "1024x768" 94.50 1024 1072 1168 1376 768 769 772 808 +hsync +vsync (**) ATI(0): Default mode "1024x768": 78.8 MHz, 60.1 kHz, 75.1 Hz (II) ATI(0): Modeline "1024x768" 78.80 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (**) ATI(0): Default mode "1024x768": 75.0 MHz, 56.5 kHz, 70.1 Hz (II) ATI(0): Modeline "1024x768" 75.00 1024 1048 1184 1328 768 771 777 806 -hsync -vsync (**) ATI(0): Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz (II) ATI(0): Modeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (**) ATI(0): Default mode "1024x768": 44.9 MHz, 35.5 kHz, 87.1 Hz (I) (II) ATI(0): Modeline "1024x768" 44.90 1024 1032 1208 1264 768 768 776 817 interlace +hsync +vsync (**) ATI(0): Built-in mode "Native panel mode": 65.1 MHz, 62.6 kHz, 81.4 Hz (II) ATI(0): Modeline "Native panel mode" 65.15 1024 1024 1032 1040 768 768 769 770 (**) ATI(0): Default mode "832x624": 57.3 MHz, 49.7 kHz, 74.6 Hz (II) ATI(0): Modeline "832x624" 57.28 832 864 928 1152 624 625 628 667 -hsync -vsync (**) ATI(0): Default mode "800x600": 56.3 MHz, 53.7 kHz, 85.1 Hz (II) ATI(0): Modeline "800x600" 56.30 800 832 896 1048 600 601 604 631 +hsync +vsync (**) ATI(0): Default mode "800x600": 49.5 MHz, 46.9 kHz, 75.0 Hz (II) ATI(0): Modeline "800x600" 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (**) ATI(0): Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) ATI(0): Modeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (**) ATI(0): Default mode "800x600": 40.0 MHz, 37.9 kHz, 60.3 Hz (II) ATI(0): Modeline "800x600" 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (**) ATI(0): Default mode "800x600": 36.0 MHz, 35.2 kHz, 56.2 Hz (II) ATI(0): Modeline "800x600" 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (**) ATI(0): Default mode "640x480": 36.0 MHz, 43.3 kHz, 85.0 Hz (II) ATI(0): Modeline "640x480" 36.00 640 696 752 832 480 481 484 509 -hsync -vsync (**) ATI(0): Default mode "640x480": 31.5 MHz, 37.5 kHz, 75.0 Hz (II) ATI(0): Modeline "640x480" 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (**) ATI(0): Default mode "640x480": 31.5 MHz, 37.9 kHz, 72.8 Hz (II) ATI(0): Modeline "640x480" 31.50 640 664 704 832 480 489 491 520 -hsync -vsync (**) ATI(0): Default mode "640x480": 25.2 MHz, 31.5 kHz, 60.0 Hz (II) ATI(0): Modeline "640x480" 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (**) ATI(0): Default mode "720x400": 35.5 MHz, 37.9 kHz, 85.0 Hz (II) ATI(0): Modeline "720x400" 35.50 720 756 828 936 400 401 404 446 -hsync +vsync (**) ATI(0): Default mode "640x400": 31.5 MHz, 37.9 kHz, 85.1 Hz (II) ATI(0): Modeline "640x400" 31.50 640 672 736 832 400 401 404 445 -hsync +vsync (**) ATI(0): Default mode "640x350": 31.5 MHz, 37.9 kHz, 85.1 Hz (II) ATI(0): Modeline "640x350" 31.50 640 672 736 832 350 382 385 445 +hsync -vsync (**) ATI(0): Default mode "576x384": 32.5 MHz, 44.2 kHz, 54.8 Hz (D) (II) ATI(0): Modeline "576x384" 32.50 576 589 657 736 384 385 388 403 doublescan +hsync +vsync (**) ATI(0): Default mode "512x384": 47.2 MHz, 68.7 kHz, 85.0 Hz (D) (II) ATI(0): Modeline "512x384" 47.25 512 536 584 688 384 384 386 404 doublescan +hsync +vsync (**) ATI(0): Default mode "512x384": 39.4 MHz, 60.1 kHz, 75.1 Hz (D) (II) ATI(0): Modeline "512x384" 39.40 512 520 568 656 384 384 386 400 doublescan +hsync +vsync (**) ATI(0): Default mode "512x384": 37.5 MHz, 56.5 kHz, 70.1 Hz (D) (II) ATI(0): Modeline "512x384" 37.50 512 524 592 664 384 385 388 403 doublescan -hsync -vsync (**) ATI(0): Default mode "512x384": 32.5 MHz, 48.4 kHz, 60.0 Hz (D) (II) ATI(0): Modeline "512x384" 32.50 512 524 592 672 384 385 388 403 doublescan -hsync -vsync (**) ATI(0): Default mode "512x384": 22.4 MHz, 35.5 kHz, 87.1 Hz (D) (II) ATI(0): Modeline "512x384" 22.45 512 516 604 632 384 384 388 409 interlace doublescan +hsync +vsync (**) ATI(0): Default mode "416x312": 28.6 MHz, 49.7 kHz, 74.7 Hz (D) (II) ATI(0): Modeline "416x312" 28.64 416 432 464 576 312 312 314 333 doublescan -hsync -vsync (**) ATI(0): Default mode "400x300": 28.1 MHz, 53.7 kHz, 85.3 Hz (D) (II) ATI(0): Modeline "400x300" 28.15 400 416 448 524 300 300 302 315 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 24.8 MHz, 46.9 kHz, 75.1 Hz (D) (II) ATI(0): Modeline "400x300" 24.75 400 408 448 528 300 300 302 312 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 25.0 MHz, 48.1 kHz, 72.2 Hz (D) (II) ATI(0): Modeline "400x300" 25.00 400 428 488 520 300 318 321 333 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 20.0 MHz, 37.9 kHz, 60.3 Hz (D) (II) ATI(0): Modeline "400x300" 20.00 400 420 484 528 300 300 302 314 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 18.0 MHz, 35.2 kHz, 56.3 Hz (D) (II) ATI(0): Modeline "400x300" 18.00 400 412 448 512 300 300 301 312 doublescan +hsync +vsync (**) ATI(0): Default mode "320x240": 18.0 MHz, 43.3 kHz, 85.2 Hz (D) (II) ATI(0): Modeline "320x240" 18.00 320 348 376 416 240 240 242 254 doublescan -hsync -vsync (**) ATI(0): Default mode "320x240": 15.8 MHz, 37.5 kHz, 75.0 Hz (D) (II) ATI(0): Modeline "320x240" 15.75 320 328 360 420 240 240 242 250 doublescan -hsync -vsync (**) ATI(0): Default mode "320x240": 15.8 MHz, 37.9 kHz, 72.8 Hz (D) (II) ATI(0): Modeline "320x240" 15.75 320 332 352 416 240 244 245 260 doublescan -hsync -vsync (**) ATI(0): Default mode "320x240": 12.6 MHz, 31.5 kHz, 60.1 Hz (D) (II) ATI(0): Modeline "320x240" 12.60 320 328 376 400 240 245 246 262 doublescan -hsync -vsync (**) ATI(0): Default mode "360x200": 17.8 MHz, 37.9 kHz, 85.0 Hz (D) (II) ATI(0): Modeline "360x200" 17.75 360 378 414 468 200 200 202 223 doublescan -hsync +vsync (**) ATI(0): Default mode "320x200": 15.8 MHz, 37.9 kHz, 85.3 Hz (D) (II) ATI(0): Modeline "320x200" 15.75 320 336 368 416 200 200 202 222 doublescan -hsync +vsync (**) ATI(0): Default mode "320x175": 15.8 MHz, 37.9 kHz, 85.3 Hz (D) (II) ATI(0): Modeline "320x175" 15.75 320 336 368 416 175 191 192 222 doublescan +hsync -vsync (==) ATI(0): DPI set to (75, 75) (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.2.0 ABI class: XFree86 Video Driver, version 0.6 (II) ATI(0): I2C bus "Mach64" initialized. (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0xf4100000 - 0xf4100fff (0x1000) MS[B] [1] 0 0 0xf5000000 - 0xf5ffffff (0x1000000) MS[B] [2] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [3] -1 0 0x00100000 - 0x107fffff (0x10700000) MX[B]E(B) [4] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [5] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [6] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [7] -1 0 0x10800000 - 0x10801fff (0x2000) MX[B] [8] -1 0 0xf4000000 - 0xf4001fff (0x2000) MX[B] [9] -1 0 0xf4002800 - 0xf400287f (0x80) MX[B] [10] -1 0 0xf4002c00 - 0xf4002cff (0x100) MX[B] [11] -1 0 0xf4002000 - 0xf400207f (0x80) MX[B] [12] -1 0 0xf4002400 - 0xf400247f (0x80) MX[B] [13] -1 0 0xf8000000 - 0xf7ffffff (0x0) MX[B]O [14] -1 0 0xf4100000 - 0xf4100fff (0x1000) MX[B](B) [15] -1 0 0xf5000000 - 0xf5ffffff (0x1000000) MX[B](B) [16] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) [17] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) [18] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) [19] 0 0 0x00009000 - 0x000090ff (0x100) IS[B] [20] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [21] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [22] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [23] -1 0 0x00001000 - 0x000010ff (0x100) IX[B] [24] -1 0 0x00001800 - 0x0000187f (0x80) IX[B] [25] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [26] -1 0 0x000018a0 - 0x000018af (0x10) IX[B] [27] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) [28] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [29] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (==) ATI(0): Write-combining range (0xf5000000,0x800000) (II) ATI(0): Largest offscreen areas (with overlaps): (II) ATI(0): 1024 x 1279 rectangle at 0,768 (II) ATI(0): 768 x 1280 rectangle at 0,768 (II) ATI(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Indirect CPU to Screen color expansion Solid Lines Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 10 256x256 slots (==) ATI(0): Backing store disabled (==) ATI(0): Silken mouse enabled (**) Option "dpms" (**) ATI(0): DPMS enabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (II) Synaptics touchpad driver version 0.13.3 (--) Synaptics Mouse auto-dev sets device to /dev/input/event1 (**) Option "Device" "/dev/input/event1" (**) Option "SHMConfig" "on" (**) Option "LeftEdge" "1700" (**) Option "RightEdge" "5300" (**) Option "TopEdge" "1700" (**) Option "BottomEdge" "4200" (**) Option "FingerLow" "25" (**) Option "FingerHigh" "30" (**) Option "MaxTapTime" "180" (**) Option "MaxTapMove" "220" (**) Option "VertScrollDelta" "100" (--) Synaptics Mouse synaptics touchpad found (**) Option "CorePointer" (**) Synaptics Mouse: Core Pointer (II) XINPUT: Adding extended input device "Synaptics Mouse" (type: MOUSE) Synaptics DeviceInit called SynapticsCtrl called. Synaptics DeviceOn called (--) Synaptics Mouse synaptics touchpad found Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! SynapticsCtrl called. SynapticsCtrl called. GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 GetModeLine - scrn: 0 clock: 65146 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1176 httl: 1344 vdsp: 768 vbeg: 769 vend: 775 vttl: 806 flags: 5 xresprobe-0.4.24ubuntu9/tests/log-r128-1024x7680000644000000000000000000007672710214367723015445 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Ubuntu 4.3.0.dfsg.1-6ubuntu7 20040820130619 root@false) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.6.7-power4 ppc [ELF] Build Date: 20 August 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.7-powerpc (buildd@ross) (gcc version 3.3.4 (Debian 1:3.3.4-5ubuntu1)) #1 Thu Aug 12 00:13:19 UTC 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Wed Aug 25 11:15:50 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Generic Laptop LCD" (**) | |-->Device "ATI Technologies, Inc. Rage Mobility M3 AGP 2x" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "macintosh" (**) XKB: model: "macintosh" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (II) Open APM successful (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:0b:0: chip 106b,0027 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 00:10:0: chip 1002,4c46 card 1002,4c46 rev 02 class 03,00,00 hdr 00 (II) PCI: 01:0b:0: chip 106b,0028 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 01:17:0: chip 106b,0025 card 0000,0000 rev 00 class ff,00,00 hdr 00 (II) PCI: 01:18:0: chip 106b,0026 card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:19:0: chip 106b,0026 card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 02:0b:0: chip 106b,0029 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 02:0e:0: chip 106b,0030 card 106b,0030 rev 00 class 0c,00,10 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:11:0), (0,0,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 1: bridge is at (1:11:0), (1,1,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 2: bridge is at (2:11:0), (2,2,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 2 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (--) PCI:*(0:16:0) ATI Technologies Inc Rage Mobility M3 AGP 2x rev 2, Mem @ 0x94000000/26, 0x90000000/14, I/O @ 0x0400/8 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) Active PCI resource ranges: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [2] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [3] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [4] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [5] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [6] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [2] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [3] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [4] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [5] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [6] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) All system resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [4] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [5] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [6] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [7] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [8] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [9] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [10] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "ati" (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.o (II) Module ati: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) ATI: ATI driver (version 6.5.5) for chipset: ati (II) R128: Driver for ATI Rage 128 chipsets: ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), ATI Rage 128 Pro GL PA (AGP?), ATI Rage 128 Pro GL PB (AGP?), ATI Rage 128 Pro GL PC (AGP?), ATI Rage 128 Pro GL PD (PCI), ATI Rage 128 Pro GL PE (AGP?), ATI Rage 128 Pro GL PF (AGP), ATI Rage 128 Pro VR PG (AGP?), ATI Rage 128 Pro VR PH (AGP?), ATI Rage 128 Pro VR PI (AGP?), ATI Rage 128 Pro VR PJ (AGP?), ATI Rage 128 Pro VR PK (AGP?), ATI Rage 128 Pro VR PL (AGP?), ATI Rage 128 Pro VR PM (AGP?), ATI Rage 128 Pro VR PN (AGP?), ATI Rage 128 Pro VR PO (AGP?), ATI Rage 128 Pro VR PP (PCI), ATI Rage 128 Pro VR PQ (AGP?), ATI Rage 128 Pro VR PR (PCI), ATI Rage 128 Pro VR PS (AGP?), ATI Rage 128 Pro VR PT (AGP?), ATI Rage 128 Pro VR PU (AGP?), ATI Rage 128 Pro VR PV (AGP?), ATI Rage 128 Pro VR PW (AGP?), ATI Rage 128 Pro VR PX (AGP?), ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (AGP?), ATI Rage 128 4X SF (AGP?), ATI Rage 128 4X SG (AGP?), ATI Rage 128 4X SH (AGP?), ATI Rage 128 4X SK (AGP?), ATI Rage 128 4X SL (AGP?), ATI Rage 128 4X SM (AGP), ATI Rage 128 4X SN (AGP?), ATI Rage 128 Pro ULTRA TF (AGP), ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), ATI Rage 128 Pro ULTRA TU (AGP?) (II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), ATI Radeon Mobility M7 LW (AGP), ATI Mobility FireGL 7800 M7 LX (AGP), ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon IGP330M/340M/350M (U2) 4337, ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), ATI Radeon Mobility 9000 (M9) Lf (AGP), ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9100 IGP (A5) 5834, ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9200PRO 5960 (AGP), ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), ATI Radeon 9200SE 5964 (AGP), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9700 NF (AGP), ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI FireGL RV360 AV (AGP), ATI Radeon Mobility 9600 (M10) NP (AGP), ATI Radeon Mobility 9600 (M10) NQ (AGP), ATI Radeon Mobility 9600 (M11) NR (AGP), ATI Radeon Mobility 9600 (M10) NS (AGP), ATI FireGL Mobility T2 (M10) NT (AGP), ATI FireGL Mobility T2 (M11) NV (AGP), ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP) (II) Primary Device is: PCI 00:10:0 (II) ATI: Candidate "Device" section "ATI Technologies, Inc. Rage Mobility M3 AGP 2x". (--) Chipset ATI Rage 128 Mobility M3 LF (AGP) found (II) Loading sub module "r128" (II) LoadModule: "r128" (II) Loading /usr/X11R6/lib/modules/drivers/r128_drv.o (II) Module r128: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 4.0.1 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [4] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [5] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [6] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [7] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [8] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [9] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [10] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) resource ranges after probing: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [4] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [5] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [6] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [7] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [8] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [9] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [10] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [13] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) [14] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [15] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) R128(0): PCI bus 0 card 16 func 0 (**) R128(0): Depth 24, (--) framebuffer bpp 32 (II) R128(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) (==) R128(0): Default visual is TrueColor (**) R128(0): Option "UseFBDev" "true" (==) R128(0): RGB weight 888 (II) R128(0): Using 8 bits per RGB (8 bit DAC) (**) R128(0): Using framebuffer device (II) Loading sub module "fbdevhw" (II) LoadModule: "fbdevhw" (II) Loading /usr/X11R6/lib/modules/linux/libfbdevhw.a (II) Module fbdevhw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.0.2 ABI class: XFree86 Video Driver, version 0.6 (--) R128(0): Chipset: "ATI Rage 128 Mobility M3 LF (AGP)" (ChipID = 0x4c46) (--) R128(0): Linear framebuffer at 0x94000000 (--) R128(0): MMIO registers at 0x90000000 (II) R128(0): Option "Display" ignored (framebuffer device determines display type) (--) R128(0): VideoRAM: 8192 kByte (128-bit SDR SGRAM 1:1) (WW) R128(0): Video BIOS not detected in PCI space! (WW) R128(0): Attempting to read Video BIOS from legacy ISA space! (WW) R128(0): Video BIOS not found! (WW) R128(0): Can't determine panel dimensions, and none specified. Disabling programming of FP registers. (II) R128(0): PLL parameters: rf=2950 rd=59 min=12500 max=25000; xclk=10500 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (==) R128(0): Using gamma correction (1.0, 1.0, 1.0) (II) R128(0): Generic Laptop LCD: Using hsync range of 28.00-49.00 kHz (II) R128(0): Generic Laptop LCD: Using vrefresh range of 43.00-72.00 Hz (II) R128(0): Clock range: 12.50 to 250.00 MHz (II) R128(0): Not using default mode "640x350" (vrefresh out of range) (II) R128(0): Not using default mode "320x175" (vrefresh out of range) (II) R128(0): Not using default mode "640x400" (vrefresh out of range) (II) R128(0): Not using default mode "320x200" (vrefresh out of range) (II) R128(0): Not using default mode "720x400" (vrefresh out of range) (II) R128(0): Not using default mode "360x200" (vrefresh out of range) (II) R128(0): Not using default mode "640x480" (vrefresh out of range) (II) R128(0): Not using default mode "320x240" (vrefresh out of range) (II) R128(0): Not using default mode "640x480" (vrefresh out of range) (II) R128(0): Not using default mode "320x240" (vrefresh out of range) (II) R128(0): Not using default mode "640x480" (vrefresh out of range) (II) R128(0): Not using default mode "320x240" (vrefresh out of range) (II) R128(0): Not using default mode "800x600" (vrefresh out of range) (II) R128(0): Not using default mode "400x300" (vrefresh out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "400x300" (hsync out of range) (II) R128(0): Not using default mode "1024x768" (vrefresh out of range) (II) R128(0): Not using default mode "512x384" (vrefresh out of range) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "512x384" (hsync out of range) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "512x384" (hsync out of range) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "512x384" (hsync out of range) (II) R128(0): Not using default mode "1152x864" (hsync out of range) (II) R128(0): Not using default mode "576x432" (hsync out of range) (II) R128(0): Not using default mode "1280x960" (hsync out of range) (II) R128(0): Not using default mode "640x480" (hsync out of range) (II) R128(0): Not using default mode "1280x960" (hsync out of range) (II) R128(0): Not using default mode "640x480" (hsync out of range) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (hsync out of range) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (hsync out of range) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1600x1200" (hsync out of range) (II) R128(0): Not using default mode "800x600" (hsync out of range) (II) R128(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) R128(0): Not using default mode "896x672" (hsync out of range) (II) R128(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) R128(0): Not using default mode "896x672" (hsync out of range) (II) R128(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) R128(0): Not using default mode "928x696" (hsync out of range) (II) R128(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) R128(0): Not using default mode "928x696" (hsync out of range) (II) R128(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) R128(0): Not using default mode "960x720" (hsync out of range) (II) R128(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) R128(0): Not using default mode "960x720" (hsync out of range) (II) R128(0): Not using default mode "832x624" (hsync out of range) (II) R128(0): Not using default mode "416x312" (hsync out of range) (II) R128(0): Not using default mode "1400x1050" (hsync out of range) (II) R128(0): Not using default mode "700x525" (hsync out of range) (II) R128(0): Not using default mode "1400x1050" (hsync out of range) (II) R128(0): Not using default mode "700x525" (hsync out of range) (II) R128(0): Not using default mode "1600x1024" (hsync out of range) (II) R128(0): Not using default mode "800x512" (hsync out of range) (II) R128(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) R128(0): Not using default mode "960x720" (hsync out of range) (II) R128(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "1152x768" (width too large for virtual size) (--) R128(0): Virtual size is 1024x768 (pitch 1024) (**) R128(0): *Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz (II) R128(0): Modeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (**) R128(0): *Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) R128(0): Modeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (**) R128(0): *Default mode "640x480": 25.2 MHz, 31.5 kHz, 60.0 Hz (II) R128(0): Modeline "640x480" 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (**) R128(0): Default mode "800x600": 40.0 MHz, 37.9 kHz, 60.3 Hz (II) R128(0): Modeline "800x600" 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (**) R128(0): Default mode "800x600": 36.0 MHz, 35.2 kHz, 56.2 Hz (II) R128(0): Modeline "800x600" 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (**) R128(0): Default mode "576x384": 32.5 MHz, 44.2 kHz, 54.8 Hz (D) (II) R128(0): Modeline "576x384" 32.50 576 589 657 736 384 385 388 403 doublescan +hsync +vsync (**) R128(0): Default mode "512x384": 32.5 MHz, 48.4 kHz, 60.0 Hz (D) (II) R128(0): Modeline "512x384" 32.50 512 524 592 672 384 385 388 403 doublescan -hsync -vsync (**) R128(0): Default mode "400x300": 25.0 MHz, 48.1 kHz, 72.2 Hz (D) (II) R128(0): Modeline "400x300" 25.00 400 428 488 520 300 318 321 333 doublescan +hsync +vsync (**) R128(0): Default mode "400x300": 20.0 MHz, 37.9 kHz, 60.3 Hz (D) (II) R128(0): Modeline "400x300" 20.00 400 420 484 528 300 300 302 314 doublescan +hsync +vsync (**) R128(0): Default mode "400x300": 18.0 MHz, 35.2 kHz, 56.3 Hz (D) (II) R128(0): Modeline "400x300" 18.00 400 412 448 512 300 300 301 312 doublescan +hsync +vsync (**) R128(0): Default mode "320x240": 12.6 MHz, 31.5 kHz, 60.1 Hz (D) (II) R128(0): Modeline "320x240" 12.60 320 328 376 400 240 245 246 262 doublescan -hsync -vsync (==) R128(0): DPI set to (75, 75) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "shadowfb" (II) LoadModule: "shadowfb" (II) Loading /usr/X11R6/lib/modules/libshadowfb.a (II) Module shadowfb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) R128(0): Page flipping disabled (!!) R128(0): For information on using the multimedia capabilities of this adapter, please see http://gatos.sf.net. (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0x90000000 - 0x90003fff (0x4000) MS[B] [1] 0 0 0x94000000 - 0x97ffffff (0x4000000) MS[B] [2] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [4] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [5] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [6] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [7] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [8] -1 0 0x90000000 - 0x90003fff (0x4000) MX[B](B) [9] -1 0 0x94000000 - 0x97ffffff (0x4000000) MX[B](B) [10] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) [11] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) [12] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) [13] 0 0 0x00000400 - 0x000004ff (0x100) IS[B] [14] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [15] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [16] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) [17] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [18] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (WW) R128(0): Static buffer allocation failed -- need at least 9216 kB video memory (II) R128(0): Memory manager initialized to (0,0) (1024,2048) (II) R128(0): Reserved area from (0,768) to (1024,770) (II) R128(0): Largest offscreen area available: 1024 x 1278 (II) R128(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Indirect CPU to Screen color expansion Solid Lines Dashed Lines Scanline Image Writes Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 10 256x256 slots (II) R128(0): Acceleration enabled (==) R128(0): Backing store disabled (==) R128(0): Silken mouse enabled (II) R128(0): Using hardware cursor (scanline 3080) (II) R128(0): Largest offscreen area available: 1024 x 1276 (**) Option "dpms" (**) R128(0): DPMS enabled (II) R128(0): Direct rendering disabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (**) Option "Emulate3Buttons" "true" (**) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Configured Mouse: ZAxisMapping: buttons 4 and 5 (**) Configured Mouse: Buttons: 5 (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) Server_Terminate keybinding not found (II) Configured Mouse: ps2EnableDataReporting: succeeded Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded GetModeLine - scrn: 0 clock: 65000 GetModeLine - hdsp: 1024 hbeg: 1048 hend: 1184 httl: 1344 vdsp: 768 vbeg: 771 vend: 777 vttl: 806 flags: 10 (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Open APM successful (II) Configured Mouse: ps2EnableDataReporting: succeeded xresprobe-0.4.24ubuntu9/tests/ddcprobe-1280x8540000644000000000000000000000050610214367723015732 0ustar oem: ATI Radeon Lf memory: 0kb edid: 1 3 id: 209c eisa: APP209c serial: 01010101 manufacture: 5 2002 input: digital signal. screensize: 32 22 gamma: 2.200000 dpms: non-RGB, no active off, suspend, no standby timing0: 115510000 1280 256 854 12 16 112 1 3 321x 214 monitorid: LTN152W3 monitorid: LTN152W3 monitorname: Color LCD xresprobe-0.4.24ubuntu9/tests/log-i855-1024x7680000644000000000000000000020520110214367723015420 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Ubuntu 4.3.0.dfsg.1-6ubuntu4 20040811120910 root@macaroni.warthogs.hbd.com) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.4.27-es i686 [ELF] Build Date: 11 August 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.7 (thom@virelais) (gcc version 3.3.4 (Debian 1:3.3.4-5ubuntu1)) #1 Wed Aug 11 12:45:39 BST 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Thu Aug 19 09:03:56 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Generic Monitor" (**) | |-->Device "Generic Video Card" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "pc104" (**) XKB: model: "pc104" (**) Option "XkbLayout" "gb" (**) XKB: layout: "gb" (**) Option "XkbOptions" "ctrl:nocaps" (**) XKB: options: "ctrl:nocaps" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: Probing config type using method 1 (II) PCI: Config type is 1 (II) PCI: stages = 0x03, oldVal1 = 0x8002007c, mode1Res1 = 0x80000000 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,3580 card 1014,055c rev 02 class 06,00,00 hdr 80 (II) PCI: 00:00:1: chip 8086,3584 card 1014,055d rev 02 class 08,80,00 hdr 00 (II) PCI: 00:00:3: chip 8086,3585 card 1014,055e rev 02 class 08,80,00 hdr 80 (II) PCI: 00:02:0: chip 8086,3582 card 1014,0557 rev 02 class 03,00,00 hdr 80 (II) PCI: 00:02:1: chip 8086,3582 card 1014,0557 rev 02 class 03,80,00 hdr 80 (II) PCI: 00:1d:0: chip 8086,24c2 card 1014,052d rev 01 class 0c,03,00 hdr 80 (II) PCI: 00:1d:1: chip 8086,24c4 card 1014,052d rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:1d:2: chip 8086,24c7 card 1014,052d rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:1d:7: chip 8086,24cd card 1014,052e rev 01 class 0c,03,20 hdr 00 (II) PCI: 00:1e:0: chip 8086,2448 card 0000,0000 rev 81 class 06,04,00 hdr 01 (II) PCI: 00:1f:0: chip 8086,24cc card 0000,0000 rev 01 class 06,01,00 hdr 80 (II) PCI: 00:1f:1: chip 8086,24ca card 1014,052d rev 01 class 01,01,8a hdr 00 (II) PCI: 00:1f:3: chip 8086,24c3 card 1014,052d rev 01 class 0c,05,00 hdr 00 (II) PCI: 00:1f:5: chip 8086,24c5 card 1014,0558 rev 01 class 04,01,00 hdr 00 (II) PCI: 00:1f:6: chip 8086,24c6 card 1014,055a rev 01 class 07,03,00 hdr 00 (II) PCI: 02:00:0: chip 1180,0476 card 4000,0000 rev 8d class 06,07,00 hdr 82 (II) PCI: 02:00:1: chip 1180,0822 card 1014,0556 rev 13 class 08,05,00 hdr 80 (II) PCI: 02:01:0: chip 8086,1077 card 1014,055b rev 00 class 02,00,00 hdr 00 (II) PCI: 02:02:0: chip 8086,1043 card 8086,2551 rev 04 class 02,80,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (0,0,3), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-PCI bridge: (II) Bus 2: bridge is at (0:30:0), (0,2,5), BCTRL: 0x0004 (VGA_EN is cleared) (II) Bus 2 I/O range: [0] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [1] -1 0 0x00003400 - 0x000034ff (0x100) IX[B] [2] -1 0 0x00003800 - 0x000038ff (0x100) IX[B] [3] -1 0 0x00003c00 - 0x00003cff (0x100) IX[B] [4] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [5] -1 0 0x00004400 - 0x000044ff (0x100) IX[B] [6] -1 0 0x00004800 - 0x000048ff (0x100) IX[B] [7] -1 0 0x00004c00 - 0x00004cff (0x100) IX[B] [8] -1 0 0x00005000 - 0x000050ff (0x100) IX[B] [9] -1 0 0x00005400 - 0x000054ff (0x100) IX[B] [10] -1 0 0x00005800 - 0x000058ff (0x100) IX[B] [11] -1 0 0x00005c00 - 0x00005cff (0x100) IX[B] [12] -1 0 0x00006000 - 0x000060ff (0x100) IX[B] [13] -1 0 0x00006400 - 0x000064ff (0x100) IX[B] [14] -1 0 0x00006800 - 0x000068ff (0x100) IX[B] [15] -1 0 0x00006c00 - 0x00006cff (0x100) IX[B] [16] -1 0 0x00007000 - 0x000070ff (0x100) IX[B] [17] -1 0 0x00007400 - 0x000074ff (0x100) IX[B] [18] -1 0 0x00007800 - 0x000078ff (0x100) IX[B] [19] -1 0 0x00007c00 - 0x00007cff (0x100) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0xd0200000 - 0xdfffffff (0xfe00000) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0xf0000000 - 0xf7ffffff (0x8000000) MX[B] (II) PCI-to-ISA bridge: (II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set) (II) PCI-to-CardBus bridge: (II) Bus 3: bridge is at (2:0:0), (2,3,6), BCTRL: 0x0580 (VGA_EN is cleared) (II) Bus 3 I/O range: [0] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [1] -1 0 0x00004400 - 0x000044ff (0x100) IX[B] (--) PCI:*(0:2:0) Intel Corp. 82852/855GM Integrated Graphics Device rev 2, Mem @ 0xe0000000/27, 0xd0000000/19, I/O @ 0x1800/3 (--) PCI: (0:2:1) Intel Corp. 82852/855GM Integrated Graphics Device rev 2, Mem @ 0xe8000000/27, 0xd0080000/19 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) Active PCI resource ranges: [0] -1 0 0xd0220000 - 0xd0220fff (0x1000) MX[B] [1] -1 0 0xd0200000 - 0xd021ffff (0x20000) MX[B] [2] -1 0 0xd0221000 - 0xd02210ff (0x100) MX[B] [3] -1 0 0xd0100800 - 0xd01008ff (0x100) MX[B] [4] -1 0 0xd0100c00 - 0xd0100dff (0x200) MX[B] [5] -1 0 0x20000000 - 0x200003ff (0x400) MX[B] [6] -1 0 0xd0100000 - 0xd01003ff (0x400) MX[B] [7] -1 0 0xd0080000 - 0xd00fffff (0x80000) MX[B](B) [8] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [9] -1 0 0xd0000000 - 0xd007ffff (0x80000) MX[B](B) [10] -1 0 0xe0000000 - 0xe7ffffff (0x8000000) MX[B](B) [11] -1 0 0x00007000 - 0x0000703f (0x40) IX[B] [12] -1 0 0x00002000 - 0x0000207f (0x80) IX[B] [13] -1 0 0x00002400 - 0x000024ff (0x100) IX[B] [14] -1 0 0x000018c0 - 0x000018ff (0x40) IX[B] [15] -1 0 0x00001c00 - 0x00001cff (0x100) IX[B] [16] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [17] -1 0 0x00001810 - 0x0000181f (0x10) IX[B] [18] -1 0 0x00001860 - 0x0000187f (0x20) IX[B] [19] -1 0 0x00001840 - 0x0000185f (0x20) IX[B] [20] -1 0 0x00001820 - 0x0000183f (0x20) IX[B] [21] -1 0 0x00001800 - 0x00001807 (0x8) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xd0220000 - 0xd0220fff (0x1000) MX[B] [1] -1 0 0xd0200000 - 0xd021ffff (0x20000) MX[B] [2] -1 0 0xd0221000 - 0xd02210ff (0x100) MX[B] [3] -1 0 0xd0100800 - 0xd01008ff (0x100) MX[B] [4] -1 0 0xd0100c00 - 0xd0100dff (0x200) MX[B] [5] -1 0 0x20000000 - 0x200003ff (0x400) MX[B] [6] -1 0 0xd0100000 - 0xd01003ff (0x400) MX[B] [7] -1 0 0xd0080000 - 0xd00fffff (0x80000) MX[B](B) [8] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [9] -1 0 0xd0000000 - 0xd007ffff (0x80000) MX[B](B) [10] -1 0 0xe0000000 - 0xe7ffffff (0x8000000) MX[B](B) [11] -1 0 0x00007000 - 0x0000703f (0x40) IX[B] [12] -1 0 0x00002000 - 0x0000207f (0x80) IX[B] [13] -1 0 0x00002400 - 0x000024ff (0x100) IX[B] [14] -1 0 0x000018c0 - 0x000018ff (0x40) IX[B] [15] -1 0 0x00001c00 - 0x00001cff (0x100) IX[B] [16] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [17] -1 0 0x00001810 - 0x0000181f (0x10) IX[B] [18] -1 0 0x00001860 - 0x0000187f (0x20) IX[B] [19] -1 0 0x00001840 - 0x0000185f (0x20) IX[B] [20] -1 0 0x00001820 - 0x0000183f (0x20) IX[B] [21] -1 0 0x00001800 - 0x00001807 (0x8) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x1fffffff (0x1ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x1fffffff (0x1ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xd0220000 - 0xd0220fff (0x1000) MX[B] [6] -1 0 0xd0200000 - 0xd021ffff (0x20000) MX[B] [7] -1 0 0xd0221000 - 0xd02210ff (0x100) MX[B] [8] -1 0 0xd0100800 - 0xd01008ff (0x100) MX[B] [9] -1 0 0xd0100c00 - 0xd0100dff (0x200) MX[B] [10] -1 0 0x20000000 - 0x200003ff (0x400) MX[B] [11] -1 0 0xd0100000 - 0xd01003ff (0x400) MX[B] [12] -1 0 0xd0080000 - 0xd00fffff (0x80000) MX[B](B) [13] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [14] -1 0 0xd0000000 - 0xd007ffff (0x80000) MX[B](B) [15] -1 0 0xe0000000 - 0xe7ffffff (0x8000000) MX[B](B) [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [17] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [18] -1 0 0x00007000 - 0x0000703f (0x40) IX[B] [19] -1 0 0x00002000 - 0x0000207f (0x80) IX[B] [20] -1 0 0x00002400 - 0x000024ff (0x100) IX[B] [21] -1 0 0x000018c0 - 0x000018ff (0x40) IX[B] [22] -1 0 0x00001c00 - 0x00001cff (0x100) IX[B] [23] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [24] -1 0 0x00001810 - 0x0000181f (0x10) IX[B] [25] -1 0 0x00001860 - 0x0000187f (0x20) IX[B] [26] -1 0 0x00001840 - 0x0000185f (0x20) IX[B] [27] -1 0 0x00001820 - 0x0000183f (0x20) IX[B] [28] -1 0 0x00001800 - 0x00001807 (0x8) IX[B](B) (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "i810" (II) Loading /usr/X11R6/lib/modules/drivers/i810_drv.o (II) Module i810: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.3.0 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) I810: Driver for Intel Integrated Graphics Chipsets: i810, i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G (II) Primary Device is: PCI 00:02:0 (--) Chipset 852GM/855GM found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x1fffffff (0x1ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xd0220000 - 0xd0220fff (0x1000) MX[B] [6] -1 0 0xd0200000 - 0xd021ffff (0x20000) MX[B] [7] -1 0 0xd0221000 - 0xd02210ff (0x100) MX[B] [8] -1 0 0xd0100800 - 0xd01008ff (0x100) MX[B] [9] -1 0 0xd0100c00 - 0xd0100dff (0x200) MX[B] [10] -1 0 0x20000000 - 0x200003ff (0x400) MX[B] [11] -1 0 0xd0100000 - 0xd01003ff (0x400) MX[B] [12] -1 0 0xd0080000 - 0xd00fffff (0x80000) MX[B](B) [13] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [14] -1 0 0xd0000000 - 0xd007ffff (0x80000) MX[B](B) [15] -1 0 0xe0000000 - 0xe7ffffff (0x8000000) MX[B](B) [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [17] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [18] -1 0 0x00007000 - 0x0000703f (0x40) IX[B] [19] -1 0 0x00002000 - 0x0000207f (0x80) IX[B] [20] -1 0 0x00002400 - 0x000024ff (0x100) IX[B] [21] -1 0 0x000018c0 - 0x000018ff (0x40) IX[B] [22] -1 0 0x00001c00 - 0x00001cff (0x100) IX[B] [23] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [24] -1 0 0x00001810 - 0x0000181f (0x10) IX[B] [25] -1 0 0x00001860 - 0x0000187f (0x20) IX[B] [26] -1 0 0x00001840 - 0x0000185f (0x20) IX[B] [27] -1 0 0x00001820 - 0x0000183f (0x20) IX[B] [28] -1 0 0x00001800 - 0x00001807 (0x8) IX[B](B) (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x1fffffff (0x1ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xd0220000 - 0xd0220fff (0x1000) MX[B] [6] -1 0 0xd0200000 - 0xd021ffff (0x20000) MX[B] [7] -1 0 0xd0221000 - 0xd02210ff (0x100) MX[B] [8] -1 0 0xd0100800 - 0xd01008ff (0x100) MX[B] [9] -1 0 0xd0100c00 - 0xd0100dff (0x200) MX[B] [10] -1 0 0x20000000 - 0x200003ff (0x400) MX[B] [11] -1 0 0xd0100000 - 0xd01003ff (0x400) MX[B] [12] -1 0 0xd0080000 - 0xd00fffff (0x80000) MX[B](B) [13] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [14] -1 0 0xd0000000 - 0xd007ffff (0x80000) MX[B](B) [15] -1 0 0xe0000000 - 0xe7ffffff (0x8000000) MX[B](B) [16] 1 0 0x000a0000 - 0x000affff (0x10000) MS[B] [17] 1 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [18] 1 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [19] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [20] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [21] -1 0 0x00007000 - 0x0000703f (0x40) IX[B] [22] -1 0 0x00002000 - 0x0000207f (0x80) IX[B] [23] -1 0 0x00002400 - 0x000024ff (0x100) IX[B] [24] -1 0 0x000018c0 - 0x000018ff (0x40) IX[B] [25] -1 0 0x00001c00 - 0x00001cff (0x100) IX[B] [26] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [27] -1 0 0x00001810 - 0x0000181f (0x10) IX[B] [28] -1 0 0x00001860 - 0x0000187f (0x20) IX[B] [29] -1 0 0x00001840 - 0x0000185f (0x20) IX[B] [30] -1 0 0x00001820 - 0x0000183f (0x20) IX[B] [31] -1 0 0x00001800 - 0x00001807 (0x8) IX[B](B) [32] 1 0 0x000003b0 - 0x000003bb (0xc) IS[B] [33] 1 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Reloading /usr/X11R6/lib/modules/libvbe.a (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (**) I810(0): Depth 24, (--) framebuffer bpp 32 (==) I810(0): RGB weight 888 (==) I810(0): Default visual is TrueColor (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) I810(0): initializing int10 (WW) I810(0): Bad V_BIOS checksum (II) I810(0): Primary V_BIOS segment is: 0xc000 (II) I810(0): VESA BIOS detected (II) I810(0): VESA VBE Version 3.0 (II) I810(0): VESA VBE Total Mem: 8000 kB (II) I810(0): VESA VBE OEM: Intel(r)852GM/852GME/855GM/855GME Graphics Chip Accelerated VGA BIOS (II) I810(0): VESA VBE OEM Software Rev: 1.0 (II) I810(0): VESA VBE OEM Vendor: Intel Corporation (II) I810(0): VESA VBE OEM Product: Intel(r)852GM/852GME/855GM/855GME Graphics Controller (II) I810(0): VESA VBE OEM Product Rev: Hardware Version 0.0 (II) I810(0): Integrated Graphics Chipset: Intel(R) 855GME (--) I810(0): Chipset: "852GM/855GM" (--) I810(0): Linear framebuffer at 0xE0000000 (--) I810(0): IO registers at addr 0xD0000000 (II) I810(0): detected 8060 kB stolen memory. (II) I810(0): I830CheckAvailableMemory: 440316 kB available (II) I810(0): Will attempt to tell the BIOS that there is 12288 kB VideoRAM (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) I810(0): initializing int10 (WW) I810(0): Bad V_BIOS checksum (II) I810(0): Primary V_BIOS segment is: 0xc000 (II) I810(0): VESA BIOS detected (II) I810(0): VESA VBE Version 3.0 (II) I810(0): VESA VBE Total Mem: 12288 kB (II) I810(0): VESA VBE OEM: Intel(r)852GM/852GME/855GM/855GME Graphics Chip Accelerated VGA BIOS (II) I810(0): VESA VBE OEM Software Rev: 1.0 (II) I810(0): VESA VBE OEM Vendor: Intel Corporation (II) I810(0): VESA VBE OEM Product: Intel(r)852GM/852GME/855GM/855GME Graphics Controller (II) I810(0): VESA VBE OEM Product Rev: Hardware Version 0.0 (II) I810(0): BIOS now sees 12288 kB VideoRAM (--) I810(0): Pre-allocated VideoRAM: 8060 kByte (==) I810(0): VideoRAM: 32768 kByte (==) I810(0): video overlay key set to 0x101fe (**) I810(0): page flipping disabled (--) I810(0): Maximum frambuffer space: 32616 kByte (==) I810(0): Using gamma correction (1.0, 1.0, 1.0) (II) I810(0): 2 display pipes available. (==) I810(0): Display Info: enabled. (II) I810(0): Broken BIOSes cause the system to hang here. If you encounter this problem please add Option "DisplayInfo" "FALSE" to the Device section of your XF86Config file. (II) I810(0): Display Info: CRT: attached: FALSE, present: TRUE, size: (720,400) (II) I810(0): Display Info: TV: attached: FALSE, present: FALSE, size: (0,2057) (II) I810(0): Display Info: DFP (digital flat panel): attached: FALSE, present: FALSE, size: (0,2057) (II) I810(0): Display Info: LFP (local flat panel): attached: TRUE, present: TRUE, size: (1024,768) (II) I810(0): Display Info: TV2 (second TV): attached: FALSE, present: FALSE, size: (0,2057) (II) I810(0): Display Info: DFP2 (second digital flat panel): attached: FALSE, present: FALSE, size: (0,2057) (II) I810(0): Size of device LFP (local flat panel) is 1024 x 768 (II) I810(0): No active displays on Pipe A. (II) I810(0): Currently active displays on Pipe B: (II) I810(0): LFP (local flat panel) (II) I810(0): Lowest common panel size for pipe B is 1024 x 768 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) I810(0): VESA VBE DDC supported (II) I810(0): VESA VBE DDC Level none (II) I810(0): VESA VBE DDC transfer in appr. 0 sec. (II) I810(0): VESA VBE DDC read failed (--) I810(0): A non-CRT device is attached to pipe B. No refresh rate overrides will be attempted. (II) I810(0): Will use BIOS call 0x5f05 to set refresh rates for CRTs. (II) I810(0): Will use BIOS call 0x5f64 to enable displays. (--) I810(0): Maximum space available for video modes: 12288 kByte Mode: 30 (640x480) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 640 XResolution: 640 YResolution: 480 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 37 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 640 BnkNumberOfImagePages: 37 LinNumberOfImagePages: 37 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 32 (800x600) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 800 XResolution: 800 YResolution: 600 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 26 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 800 BnkNumberOfImagePages: 26 LinNumberOfImagePages: 26 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 34 (1024x768) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 1024 XResolution: 1024 YResolution: 768 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 15 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 1024 BnkNumberOfImagePages: 15 LinNumberOfImagePages: 15 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 38 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 3a (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 3c (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 41 (640x480) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 1280 XResolution: 640 YResolution: 480 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 20 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 1280 BnkNumberOfImagePages: 20 LinNumberOfImagePages: 20 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 43 (800x600) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 1600 XResolution: 800 YResolution: 600 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 11 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 1600 BnkNumberOfImagePages: 11 LinNumberOfImagePages: 11 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 45 (1024x768) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 2048 XResolution: 1024 YResolution: 768 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 7 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 2048 BnkNumberOfImagePages: 7 LinNumberOfImagePages: 7 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 49 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 4b (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 4d (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 *Mode: 50 (640x480) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 2560 XResolution: 640 YResolution: 480 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 9 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 2560 BnkNumberOfImagePages: 9 LinNumberOfImagePages: 9 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 *Mode: 52 (800x600) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 3200 XResolution: 800 YResolution: 600 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 5 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 3200 BnkNumberOfImagePages: 5 LinNumberOfImagePages: 5 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 *Mode: 54 (1024x768) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0007102 BytesPerScanline: 4096 XResolution: 1024 YResolution: 768 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 3 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe0000000 LinBytesPerScanLine: 4096 BnkNumberOfImagePages: 3 LinNumberOfImagePages: 3 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 Mode: 58 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 5a (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 5c (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 60 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 61 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 62 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 63 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 64 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 65 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 66 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 67 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 68 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 69 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 6a (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 6b (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 6c (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 6d (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 6e (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 6f (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 70 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 71 (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 7c (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 7d (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 7e (0x0) ModeAttributes: 0x0 WinAAttributes: 0x0 WinBAttributes: 0x0 WinGranularity: 0 WinSize: 0 WinASegment: 0x0 WinBSegment: 0x0 WinFuncPtr: 0x0 BytesPerScanline: 0 XResolution: 0 YResolution: 0 XCharSize: 0 YCharSize: 0 NumberOfPlanes: 0 BitsPerPixel: 0 NumberOfBanks: 0 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 (II) I810(0): Generic Monitor: Using hsync range of 30.00-57.00 kHz (II) I810(0): Generic Monitor: Using vrefresh range of 43.00-72.00 Hz (--) I810(0): Virtual size is 1024x768 (pitch 1024) (**) I810(0): *Built-in mode "1024x768" (**) I810(0): *Built-in mode "800x600" (**) I810(0): *Built-in mode "640x480" (==) I810(0): DPI set to (75, 75) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (==) I810(0): VBE Restore workaround: enabled. (II) Loading sub module "shadow" (II) LoadModule: "shadow" (II) Loading /usr/X11R6/lib/modules/libshadow.a (II) Module shadow: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (==) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 1 0 0xd0000000 - 0xd007ffff (0x80000) MS[B] [1] 1 0 0xe0000000 - 0xe7ffffff (0x8000000) MS[B] [2] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [3] -1 0 0x00100000 - 0x1fffffff (0x1ff00000) MX[B]E(B) [4] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [5] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [6] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [7] -1 0 0xd0220000 - 0xd0220fff (0x1000) MX[B] [8] -1 0 0xd0200000 - 0xd021ffff (0x20000) MX[B] [9] -1 0 0xd0221000 - 0xd02210ff (0x100) MX[B] [10] -1 0 0xd0100800 - 0xd01008ff (0x100) MX[B] [11] -1 0 0xd0100c00 - 0xd0100dff (0x200) MX[B] [12] -1 0 0x20000000 - 0x200003ff (0x400) MX[B] [13] -1 0 0xd0100000 - 0xd01003ff (0x400) MX[B] [14] -1 0 0xd0080000 - 0xd00fffff (0x80000) MX[B](B) [15] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [16] -1 0 0xd0000000 - 0xd007ffff (0x80000) MX[B](B) [17] -1 0 0xe0000000 - 0xe7ffffff (0x8000000) MX[B](B) [18] 1 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprD) [19] 1 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD) [20] 1 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprD) [21] 1 0 0x00001800 - 0x00001807 (0x8) IS[B] [22] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [23] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [24] -1 0 0x00007000 - 0x0000703f (0x40) IX[B] [25] -1 0 0x00002000 - 0x0000207f (0x80) IX[B] [26] -1 0 0x00002400 - 0x000024ff (0x100) IX[B] [27] -1 0 0x000018c0 - 0x000018ff (0x40) IX[B] [28] -1 0 0x00001c00 - 0x00001cff (0x100) IX[B] [29] -1 0 0x00001880 - 0x0000189f (0x20) IX[B] [30] -1 0 0x00001810 - 0x0000181f (0x10) IX[B] [31] -1 0 0x00001860 - 0x0000187f (0x20) IX[B] [32] -1 0 0x00001840 - 0x0000185f (0x20) IX[B] [33] -1 0 0x00001820 - 0x0000183f (0x20) IX[B] [34] -1 0 0x00001800 - 0x00001807 (0x8) IX[B](B) [35] 1 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [36] 1 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) I810(0): initializing int10 (WW) I810(0): Bad V_BIOS checksum (II) I810(0): Primary V_BIOS segment is: 0xc000 (II) I810(0): VESA BIOS detected (II) I810(0): VESA VBE Version 3.0 (II) I810(0): VESA VBE Total Mem: 8000 kB (II) I810(0): VESA VBE OEM: Intel(r)852GM/852GME/855GM/855GME Graphics Chip Accelerated VGA BIOS (II) I810(0): VESA VBE OEM Software Rev: 1.0 (II) I810(0): VESA VBE OEM Vendor: Intel Corporation (II) I810(0): VESA VBE OEM Product: Intel(r)852GM/852GME/855GM/855GME Graphics Controller (II) I810(0): VESA VBE OEM Product Rev: Hardware Version 0.0 (==) I810(0): Default visual is TrueColor (II) I810(0): Allocated 128 kB for the ring buffer at 0x0 (II) I810(0): Allocating at least 512 scanlines for pixmap cache (II) I810(0): Initial framebuffer allocation size: 5120 kByte (II) I810(0): Allocated 4 kB for HW cursor at 0x7fff000 (0x1bc71001) (II) I810(0): Allocated 4 kB for Overlay registers at 0x7ffe000 (0x1bc6a001). (II) I810(0): Allocated 64 kB for the scratch buffer at 0x7fee000 drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: Open failed drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: open result is -1, (Unknown error 999) drmOpenDevice: Open failed drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 6, (OK) drmGetBusid returned '' (II) I810(0): [drm] loaded kernel module for "i830" driver (II) I810(0): [drm] created "i830" driver at busid "PCI:0:2:0" (II) I810(0): [drm] added 8192 byte SAREA at 0xe022f000 (II) I810(0): [drm] mapped SAREA 0xe022f000 to 0x4027f000 (II) I810(0): [drm] framebuffer handle = 0xe0020000 (II) I810(0): [drm] added 1 reserved context for kernel (II) I810(0): Allocated 3072 kB for the back buffer at 0x7800000. (II) I810(0): Allocated 3072 kB for the depth buffer at 0x7400000. (II) I810(0): Allocated 32 kB for the logical context at 0x73f8000. (II) I810(0): Allocated 1024 kB for the DMA buffers at 0x72f8000. (II) I810(0): Allocated 19968 kB for textures at 0xfec80000 (II) I810(0): Updated framebuffer allocation size from 5120 to 5400 kByte (II) I810(0): Updated pixmap cache from 512 scanlines to 582 scanlines (II) I810(0): 0x86140fc: Memory at offset 0x00020000, size 5400 kBytes (II) I810(0): 0x861411c: Memory at offset 0x07fff000, size 4 kBytes (II) I810(0): 0x8614140: Memory at offset 0x00000000, size 128 kBytes (II) I810(0): 0x8614170: Memory at offset 0x07fee000, size 64 kBytes (II) I810(0): 0x8614190: Memory at offset 0x07ffe000, size 4 kBytes (II) I810(0): 0x86141b0: Memory at offset 0x07800000, size 3072 kBytes (II) I810(0): 0x86141d0: Memory at offset 0x07400000, size 3072 kBytes (II) I810(0): 0x8614230: Memory at offset 0x073f8000, size 32 kBytes (II) I810(0): 0x8614210: Memory at offset 0x072f8000, size 1024 kBytes (II) I810(0): 0x86141f0: Memory at offset 0x00566000, size 19968 kBytes (II) I810(0): Activating tiled memory for the back buffer. (II) I810(0): Activating tiled memory for the depth buffer. (II) I810(0): [drm] Registers = 0xd0000000 (II) I810(0): [drm] Back Buffer = 0xe7800000 (II) I810(0): [drm] Depth Buffer = 0xe7400000 (II) I810(0): [drm] DMA Buffers = 0xe72f8000 (II) I810(0): [drm] ring buffer = 0xe0000000 (II) I810(0): [drm] textures = 0xe0566000 (II) I810(0): [drm] added 256 4096 byte DMA buffers (II) I810(0): [drm] dma control initialized, using IRQ -1007 (II) I810(0): [dri] visual configs initialized (==) I810(0): Write-combining range (0xe0000000,0x8000000) (II) I810(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000 (II) I810(0): xf86BindGARTMemory: bind key 7 at 0x007df000 (pgoffset 2015) (II) I810(0): xf86BindGARTMemory: bind key 0 at 0x07fff000 (pgoffset 32767) (II) I810(0): xf86BindGARTMemory: bind key 2 at 0x07fee000 (pgoffset 32750) (II) I810(0): xf86BindGARTMemory: bind key 1 at 0x07ffe000 (pgoffset 32766) (II) I810(0): xf86BindGARTMemory: bind key 3 at 0x07800000 (pgoffset 30720) (II) I810(0): xf86BindGARTMemory: bind key 4 at 0x07400000 (pgoffset 29696) (II) I810(0): xf86BindGARTMemory: bind key 5 at 0x073f8000 (pgoffset 29688) (II) I810(0): xf86BindGARTMemory: bind key 6 at 0x072f8000 (pgoffset 29432) (II) I810(0): Display plane A is disabled. (II) I810(0): Display plane B is enabled. (II) I810(0): PIPEACONF is 0x80000000 (II) I810(0): PIPEBCONF is 0x80000000 (II) I810(0): Mode bandwidth is 47 Mpixel/s (II) I810(0): maxBandwidth is 1440 Mbyte/s, pipe bandwidths are 252 Mbyte/s, 0 Mbyte/s (II) I810(0): LFP compensation mode: 0x6 (II) I810(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Indirect CPU to Screen color expansion Solid Horizontal and Vertical Lines Offscreen Pixmaps Setting up tile and stipple cache: 16 128x128 slots 4 256x256 slots (==) I810(0): Backing store disabled (==) I810(0): Silken mouse enabled (II) I810(0): Initializing HW Cursor (**) Option "dpms" (**) I810(0): DPMS enabled (II) I810(0): X context handle = 0x00000001 (II) I810(0): [drm] installed DRM signal handler (II) I810(0): [DRI] installation complete (II) I810(0): direct rendering: Enabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (**) Option "Emulate3Buttons" "true" (**) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (==) Configured Mouse: Buttons: 3 (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) Configured Mouse: ps2EnableDataReporting: succeeded Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! GetModeLine - scrn: 0 clock: 0 GetModeLine - hdsp: 1024 hbeg: 0 hend: 0 httl: 0 vdsp: 768 vbeg: 0 vend: 0 vttl: 0 flags: 0 GetModeLine - scrn: 0 clock: 0 GetModeLine - hdsp: 1024 hbeg: 0 hend: 0 httl: 0 vdsp: 768 vbeg: 0 vend: 0 vttl: 0 flags: 0 GetModeLine - scrn: 0 clock: 0 GetModeLine - hdsp: 1024 hbeg: 0 hend: 0 httl: 0 vdsp: 768 vbeg: 0 vend: 0 vttl: 0 flags: 0 GetModeLine - scrn: 0 clock: 0 GetModeLine - hdsp: 1024 hbeg: 0 hend: 0 httl: 0 vdsp: 768 vbeg: 0 vend: 0 vttl: 0 flags: 0 GetModeLine - scrn: 0 clock: 0 GetModeLine - hdsp: 1024 hbeg: 0 hend: 0 httl: 0 vdsp: 768 vbeg: 0 vend: 0 vttl: 0 flags: 0 GetModeLine - scrn: 0 clock: 0 GetModeLine - hdsp: 1024 hbeg: 0 hend: 0 httl: 0 vdsp: 768 vbeg: 0 vend: 0 vttl: 0 flags: 0 GetModeLine - scrn: 0 clock: 0 GetModeLine - hdsp: 1024 hbeg: 0 hend: 0 httl: 0 vdsp: 768 vbeg: 0 vend: 0 vttl: 0 flags: 0 xresprobe-0.4.24ubuntu9/tests/log-r128-1400x10500000644000000000000000000012526710214367723015476 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Ubuntu 4.3.0.dfsg.1-6ubuntu25 20041018053958 root@macaroni.warthogs.hbd.com) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.6.8.1 i686 [ELF] Build Date: 18 October 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.8.1-3-686 (buildd@macaroni) (gcc version 3.3.4 (Debian 1:3.3.4-9ubuntu5)) #1 Wed Nov 3 00:20:12 GMT 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Wed Nov 3 10:19:23 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Écran générique" (**) | |-->Device "ATI Technologies, Inc. Rage Mobility M4 (AGP)" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "pc105" (**) XKB: model: "pc105" (**) Option "XkbLayout" "fr" (**) XKB: layout: "fr" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (**) |-->Input Device "Synaptics Touchpad" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (WW) `fonts.dir' not found (or not valid) in "/var/lib/defoma/x-ttcidfont-conf.d/dirs/CID". Entry deleted from font path. (Run 'mkfontdir' on "/var/lib/defoma/x-ttcidfont-conf.d/dirs/CID"). (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi,/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: Probing config type using method 1 (II) PCI: Config type is 1 (II) PCI: stages = 0x03, oldVal1 = 0x00000000, mode1Res1 = 0x80000000 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,1130 card 0000,0000 rev 02 class 06,00,00 hdr 00 (II) PCI: 00:01:0: chip 8086,1131 card 0000,0000 rev 02 class 06,04,00 hdr 01 (II) PCI: 00:1e:0: chip 8086,2448 card 0000,0000 rev 02 class 06,04,00 hdr 01 (II) PCI: 00:1f:0: chip 8086,244c card 0000,0000 rev 02 class 06,01,00 hdr 80 (II) PCI: 00:1f:1: chip 8086,244a card 8086,4541 rev 02 class 01,01,80 hdr 00 (II) PCI: 00:1f:2: chip 8086,2442 card 8086,4541 rev 02 class 0c,03,00 hdr 00 (II) PCI: 01:00:0: chip 1002,4d46 card 1028,00a3 rev 00 class 03,00,00 hdr 00 (II) PCI: 02:03:0: chip 125d,1998 card 1028,00a3 rev 10 class 04,01,00 hdr 00 (II) PCI: 02:06:0: chip 10b7,6055 card 10b7,6456 rev 10 class 02,00,00 hdr 80 (II) PCI: 02:06:1: chip 10b7,1007 card 10b7,615b rev 10 class 07,80,00 hdr 00 (II) PCI: 02:0f:0: chip 104c,ac42 card 4000,0000 rev 00 class 06,07,00 hdr 82 (II) PCI: 02:0f:1: chip 104c,ac42 card 4800,0000 rev 00 class 06,07,00 hdr 82 (II) PCI: 02:0f:2: chip 104c,8027 card 1028,00a3 rev 00 class 0c,00,10 hdr 80 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (0,0,7), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-PCI bridge: (II) Bus 1: bridge is at (0:1:0), (0,1,1), BCTRL: 0x000c (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x0000c000 - 0x0000c0ff (0x100) IX[B] [1] -1 0 0x0000c400 - 0x0000c4ff (0x100) IX[B] [2] -1 0 0x0000c800 - 0x0000c8ff (0x100) IX[B] [3] -1 0 0x0000cc00 - 0x0000ccff (0x100) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0xfc000000 - 0xfdffffff (0x2000000) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0xe8000000 - 0xebffffff (0x4000000) MX[B] (II) PCI-to-PCI bridge: (II) Bus 2: bridge is at (0:30:0), (0,2,16), BCTRL: 0x0006 (VGA_EN is cleared) (II) Bus 2 I/O range: [0] -1 0 0x0000e000 - 0x0000e0ff (0x100) IX[B] [1] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [2] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [3] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] [4] -1 0 0x0000f000 - 0x0000f0ff (0x100) IX[B] [5] -1 0 0x0000f400 - 0x0000f4ff (0x100) IX[B] [6] -1 0 0x0000f800 - 0x0000f8ff (0x100) IX[B] [7] -1 0 0x0000fc00 - 0x0000fcff (0x100) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0xf4000000 - 0xfbffffff (0x8000000) MX[B] (II) PCI-to-ISA bridge: (II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set) (II) PCI-to-CardBus bridge: (II) Bus 3: bridge is at (2:15:0), (2,3,6), BCTRL: 0x05c0 (VGA_EN is cleared) (II) PCI-to-CardBus bridge: (II) Bus 7: bridge is at (2:15:1), (2,7,10), BCTRL: 0x05c0 (VGA_EN is cleared) (--) PCI:*(1:0:0) ATI Technologies Inc Rage Mobility M4 AGP rev 0, Mem @ 0xe8000000/26, 0xfcffc000/14, I/O @ 0xcc00/8 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) PCI Memory resource overlap reduced 0xe4000000 from 0xe7ffffff to 0xe3ffffff (II) Active PCI resource ranges: [0] -1 0 0xf8ff8000 - 0xf8ffbfff (0x4000) MX[B] [1] -1 0 0xf8ffc800 - 0xf8ffcfff (0x800) MX[B] [2] -1 0 0xf8ffd000 - 0xf8ffd07f (0x80) MX[B] [3] -1 0 0xf8ffd400 - 0xf8ffd4ff (0x100) MX[B] [4] -1 0 0xf8ffd800 - 0xf8ffd87f (0x80) MX[B] [5] -1 0 0xf8ffdc00 - 0xf8ffdc7f (0x80) MX[B] [6] -1 0 0xf8ffe000 - 0xf8ffffff (0x2000) MX[B] [7] -1 0 0xe4000000 - 0xe3ffffff (0x0) MX[B]O [8] -1 0 0xfcffc000 - 0xfcffffff (0x4000) MX[B](B) [9] -1 0 0xe8000000 - 0xebffffff (0x4000000) MX[B](B) [10] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [11] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [12] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] [13] -1 0 0x0000dce0 - 0x0000dcff (0x20) IX[B] [14] -1 0 0x0000bfa0 - 0x0000bfaf (0x10) IX[B] [15] -1 0 0x0000cc00 - 0x0000ccff (0x100) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xf8ff8000 - 0xf8ffbfff (0x4000) MX[B] [1] -1 0 0xf8ffc800 - 0xf8ffcfff (0x800) MX[B] [2] -1 0 0xf8ffd000 - 0xf8ffd07f (0x80) MX[B] [3] -1 0 0xf8ffd400 - 0xf8ffd4ff (0x100) MX[B] [4] -1 0 0xf8ffd800 - 0xf8ffd87f (0x80) MX[B] [5] -1 0 0xf8ffdc00 - 0xf8ffdc7f (0x80) MX[B] [6] -1 0 0xf8ffe000 - 0xf8ffffff (0x2000) MX[B] [7] -1 0 0xe4000000 - 0xe3ffffff (0x0) MX[B]O [8] -1 0 0xfcffc000 - 0xfcffffff (0x4000) MX[B](B) [9] -1 0 0xe8000000 - 0xebffffff (0x4000000) MX[B](B) [10] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [11] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [12] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] [13] -1 0 0x0000dce0 - 0x0000dcff (0x20) IX[B] [14] -1 0 0x0000bfa0 - 0x0000bfaf (0x10) IX[B] [15] -1 0 0x0000cc00 - 0x0000ccff (0x100) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xf8ff8000 - 0xf8ffbfff (0x4000) MX[B] [6] -1 0 0xf8ffc800 - 0xf8ffcfff (0x800) MX[B] [7] -1 0 0xf8ffd000 - 0xf8ffd07f (0x80) MX[B] [8] -1 0 0xf8ffd400 - 0xf8ffd4ff (0x100) MX[B] [9] -1 0 0xf8ffd800 - 0xf8ffd87f (0x80) MX[B] [10] -1 0 0xf8ffdc00 - 0xf8ffdc7f (0x80) MX[B] [11] -1 0 0xf8ffe000 - 0xf8ffffff (0x2000) MX[B] [12] -1 0 0xe4000000 - 0xe3ffffff (0x0) MX[B]O [13] -1 0 0xfcffc000 - 0xfcffffff (0x4000) MX[B](B) [14] -1 0 0xe8000000 - 0xebffffff (0x4000000) MX[B](B) [15] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [16] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [17] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [18] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [19] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] [20] -1 0 0x0000dce0 - 0x0000dcff (0x20) IX[B] [21] -1 0 0x0000bfa0 - 0x0000bfaf (0x10) IX[B] [22] -1 0 0x0000cc00 - 0x0000ccff (0x100) IX[B](B) (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "v4l" (II) Loading /usr/X11R6/lib/modules/drivers/linux/v4l_drv.o (II) Module v4l: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.0.1 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "xtt" (II) Loading /usr/X11R6/lib/modules/fonts/libxtt.a (II) Module xtt: vendor="X-TrueType Server Project & After X-TT Project" compiled for 4.3.0.1, module version = 1.4.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font xtt (II) LoadModule: "ati" (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.o (II) Module ati: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) LoadModule: "synaptics" (II) Loading /usr/X11R6/lib/modules/input/synaptics_drv.o (II) Module synaptics: vendor="The XFree86 Project" compiled for 4.2.0, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.3 (II) v4l driver for Video4Linux (II) ATI: ATI driver (version 6.5.5) for chipsets: ati, ativga (II) R128: Driver for ATI Rage 128 chipsets: ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), ATI Rage 128 Pro GL PA (AGP?), ATI Rage 128 Pro GL PB (AGP?), ATI Rage 128 Pro GL PC (AGP?), ATI Rage 128 Pro GL PD (PCI), ATI Rage 128 Pro GL PE (AGP?), ATI Rage 128 Pro GL PF (AGP), ATI Rage 128 Pro VR PG (AGP?), ATI Rage 128 Pro VR PH (AGP?), ATI Rage 128 Pro VR PI (AGP?), ATI Rage 128 Pro VR PJ (AGP?), ATI Rage 128 Pro VR PK (AGP?), ATI Rage 128 Pro VR PL (AGP?), ATI Rage 128 Pro VR PM (AGP?), ATI Rage 128 Pro VR PN (AGP?), ATI Rage 128 Pro VR PO (AGP?), ATI Rage 128 Pro VR PP (PCI), ATI Rage 128 Pro VR PQ (AGP?), ATI Rage 128 Pro VR PR (PCI), ATI Rage 128 Pro VR PS (AGP?), ATI Rage 128 Pro VR PT (AGP?), ATI Rage 128 Pro VR PU (AGP?), ATI Rage 128 Pro VR PV (AGP?), ATI Rage 128 Pro VR PW (AGP?), ATI Rage 128 Pro VR PX (AGP?), ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (AGP?), ATI Rage 128 4X SF (AGP?), ATI Rage 128 4X SG (AGP?), ATI Rage 128 4X SH (AGP?), ATI Rage 128 4X SK (AGP?), ATI Rage 128 4X SL (AGP?), ATI Rage 128 4X SM (AGP), ATI Rage 128 4X SN (AGP?), ATI Rage 128 Pro ULTRA TF (AGP), ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), ATI Rage 128 Pro ULTRA TU (AGP?) (II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), ATI Radeon Mobility M7 LW (AGP), ATI Mobility FireGL 7800 M7 LX (AGP), ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon IGP330M/340M/350M (U2) 4337, ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), ATI Radeon Mobility 9000 (M9) Lf (AGP), ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9100 IGP (A5) 5834, ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9200PRO 5960 (AGP), ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), ATI Radeon 9200SE 5964 (AGP), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9700 NF (AGP), ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI FireGL RV360 AV (AGP), ATI Radeon Mobility 9600 (M10) NP (AGP), ATI Radeon Mobility 9600 (M10) NQ (AGP), ATI Radeon Mobility 9600 (M11) NR (AGP), ATI Radeon Mobility 9600 (M10) NS (AGP), ATI FireGL Mobility T2 (M10) NT (AGP), ATI FireGL Mobility T2 (M11) NV (AGP), ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP) (II) Primary Device is: PCI 01:00:0 (II) ATI: Candidate "Device" section "ATI Technologies, Inc. Rage Mobility M4 (AGP)". (--) Chipset ATI Rage 128 Mobility M4 MF (AGP) found (II) Loading sub module "r128" (II) LoadModule: "r128" (II) Loading /usr/X11R6/lib/modules/drivers/r128_drv.o (II) Module r128: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 4.0.1 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xf8ff8000 - 0xf8ffbfff (0x4000) MX[B] [6] -1 0 0xf8ffc800 - 0xf8ffcfff (0x800) MX[B] [7] -1 0 0xf8ffd000 - 0xf8ffd07f (0x80) MX[B] [8] -1 0 0xf8ffd400 - 0xf8ffd4ff (0x100) MX[B] [9] -1 0 0xf8ffd800 - 0xf8ffd87f (0x80) MX[B] [10] -1 0 0xf8ffdc00 - 0xf8ffdc7f (0x80) MX[B] [11] -1 0 0xf8ffe000 - 0xf8ffffff (0x2000) MX[B] [12] -1 0 0xe4000000 - 0xe3ffffff (0x0) MX[B]O [13] -1 0 0xfcffc000 - 0xfcffffff (0x4000) MX[B](B) [14] -1 0 0xe8000000 - 0xebffffff (0x4000000) MX[B](B) [15] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [16] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [17] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [18] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [19] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] [20] -1 0 0x0000dce0 - 0x0000dcff (0x20) IX[B] [21] -1 0 0x0000bfa0 - 0x0000bfaf (0x10) IX[B] [22] -1 0 0x0000cc00 - 0x0000ccff (0x100) IX[B](B) (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xf8ff8000 - 0xf8ffbfff (0x4000) MX[B] [6] -1 0 0xf8ffc800 - 0xf8ffcfff (0x800) MX[B] [7] -1 0 0xf8ffd000 - 0xf8ffd07f (0x80) MX[B] [8] -1 0 0xf8ffd400 - 0xf8ffd4ff (0x100) MX[B] [9] -1 0 0xf8ffd800 - 0xf8ffd87f (0x80) MX[B] [10] -1 0 0xf8ffdc00 - 0xf8ffdc7f (0x80) MX[B] [11] -1 0 0xf8ffe000 - 0xf8ffffff (0x2000) MX[B] [12] -1 0 0xe4000000 - 0xe3ffffff (0x0) MX[B]O [13] -1 0 0xfcffc000 - 0xfcffffff (0x4000) MX[B](B) [14] -1 0 0xe8000000 - 0xebffffff (0x4000000) MX[B](B) [15] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [16] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [17] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [18] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [19] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [20] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [21] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [22] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] [23] -1 0 0x0000dce0 - 0x0000dcff (0x20) IX[B] [24] -1 0 0x0000bfa0 - 0x0000bfaf (0x10) IX[B] [25] -1 0 0x0000cc00 - 0x0000ccff (0x100) IX[B](B) [26] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [27] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) R128(0): PCI bus 1 card 0 func 0 (**) R128(0): Depth 16, (--) framebuffer bpp 16 (II) R128(0): Pixel depth = 16 bits stored in 2 bytes (16 bpp pixmaps) (==) R128(0): Default visual is TrueColor (==) R128(0): RGB weight 565 (II) R128(0): Using 6 bits per RGB (8 bit DAC) (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) R128(0): initializing int10 (II) R128(0): Primary V_BIOS segment is: 0xc000 (--) R128(0): Chipset: "ATI Rage 128 Mobility M4 MF (AGP)" (ChipID = 0x4d46) (--) R128(0): Linear framebuffer at 0xe8000000 (--) R128(0): MMIO registers at 0xfcffc000 (--) R128(0): VideoRAM: 16384 kByte (128-bit SDR SGRAM 1:1) (**) R128(0): Using flat panel for display (II) R128(0): Panel size: 1400x1050 (II) R128(0): Panel ID: Samsung LTN150P2-L01 (II) R128(0): Panel Type: Color, Single, TFT (II) R128(0): Panel Interface: LVDS (II) R128(0): PLL parameters: rf=2700 rd=12 min=12000 max=27000; xclk=10500 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Reloading /usr/X11R6/lib/modules/libvbe.a (II) R128(0): VESA BIOS detected (II) R128(0): VESA VBE Version 2.0 (II) R128(0): VESA VBE Total Mem: 16384 kB (II) R128(0): VESA VBE OEM: ATI MOBILE M4 (II) R128(0): VESA VBE OEM Software Rev: 1.0 (II) R128(0): VESA VBE OEM Vendor: ATI Technologies Inc. (II) R128(0): VESA VBE OEM Product: M4 (II) R128(0): VESA VBE OEM Product Rev: 01.00 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) R128(0): VESA VBE DDC supported (II) R128(0): VESA VBE DDC Level none (II) R128(0): VESA VBE DDC transfer in appr. 2 sec. (II) R128(0): VESA VBE DDC read failed (==) R128(0): Using gamma correction (1.0, 1.0, 1.0) (II) R128(0): Écran générique: Using hsync range of 30.00-67.00 kHz (II) R128(0): Écran générique: Using vrefresh range of 50.00-75.00 Hz (II) R128(0): Clock range: 12.00 to 270.00 MHz (II) R128(0): Not using default mode "640x350" (vrefresh out of range) (II) R128(0): Not using default mode "320x175" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "640x400" (vrefresh out of range) (II) R128(0): Not using default mode "320x200" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "720x400" (no mode of this name) (II) R128(0): Not using default mode "360x200" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "640x480" (vrefresh out of range) (II) R128(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "800x600" (vrefresh out of range) (II) R128(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1024x768" (hsync out of range) (II) R128(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1152x864" (no mode of this name) (II) R128(0): Not using default mode "576x432" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1280x960" (no mode of this name) (II) R128(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1280x960" (no mode of this name) (II) R128(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "640x512" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1280x1024" (hsync out of range) (II) R128(0): Not using default mode "640x512" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1600x1200" (no mode of this name) (II) R128(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1600x1200" (no mode of this name) (II) R128(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1600x1200" (no mode of this name) (II) R128(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1600x1200" (no mode of this name) (II) R128(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1600x1200" (no mode of this name) (II) R128(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1792x1344" (no mode of this name) (II) R128(0): Not using default mode "896x672" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1792x1344" (no mode of this name) (II) R128(0): Not using default mode "896x672" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1856x1392" (no mode of this name) (II) R128(0): Not using default mode "928x696" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1856x1392" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "928x696" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1920x1440" (no mode of this name) (II) R128(0): Not using default mode "960x720" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1920x1440" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "960x720" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "832x624" (no mode of this name) (II) R128(0): Not using default mode "416x312" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1152x768" (no mode of this name) (II) R128(0): Not using default mode "576x384" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1152x864" (no mode of this name) (II) R128(0): Not using default mode "576x432" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "700x525" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1400x1050" (hsync out of range) (II) R128(0): Not using default mode "700x525" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1400x1050" (hsync out of range) (II) R128(0): Not using default mode "700x525" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1400x1050" (hsync out of range) (II) R128(0): Not using default mode "700x525" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1600x1024" (no mode of this name) (II) R128(0): Not using default mode "800x512" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1920x1200" (no mode of this name) (II) R128(0): Not using default mode "960x600" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1920x1440" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "960x720" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "2048x1536" (no mode of this name) (II) R128(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "2048x1536" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "2048x1536" (bad mode clock/interlace/doublescan) (II) R128(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) R128(0): Modifying mode according to VBIOS: 1400x1050 [pclk 122.0 MHz] for FP to: 1400x1050 [pclk 108.0 MHz] (II) R128(0): Not using mode "1280x960" (no mode of this name) (II) R128(0): Not using mode "1152x864" (no mode of this name) (II) R128(0): Modifying mode according to VBIOS: 1024x768 [pclk 78.8 MHz] for FP to: 1024x768 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 800x600 [pclk 49.5 MHz] for FP to: 800x600 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 640x480 [pclk 31.5 MHz] for FP to: 640x480 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 1280x1024 [pclk 108.0 MHz] for FP to: 1280x1024 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 1024x768 [pclk 75.0 MHz] for FP to: 1024x768 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 1024x768 [pclk 65.0 MHz] for FP to: 1024x768 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 800x600 [pclk 50.0 MHz] for FP to: 800x600 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 800x600 [pclk 40.0 MHz] for FP to: 800x600 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 800x600 [pclk 36.0 MHz] for FP to: 800x600 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 640x480 [pclk 31.5 MHz] for FP to: 640x480 [pclk 108.0 MHz] (II) R128(0): Modifying mode according to VBIOS: 640x480 [pclk 25.2 MHz] for FP to: 640x480 [pclk 108.0 MHz] (--) R128(0): Virtual size is 1400x1050 (pitch 1408) (**) R128(0): *Default mode "1400x1050": 108.0 MHz (scaled from 122.0 MHz), 64.9 kHz, 60.0 Hz (II) R128(0): Modeline "1400x1050" 108.00 1400 1448 1462 1696 1050 1050 1053 1066 +hsync +vsync (**) R128(0): *Default mode "1024x768": 108.0 MHz (scaled from 78.8 MHz), 60.1 kHz, 75.1 Hz (II) R128(0): Modeline "1024x768" 108.00 1024 1072 1086 1320 768 769 772 784 +hsync +vsync (**) R128(0): *Default mode "800x600": 108.0 MHz (scaled from 49.5 MHz), 46.9 kHz, 75.0 Hz (II) R128(0): Modeline "800x600" 108.00 800 848 862 1096 600 600 603 616 +hsync +vsync (**) R128(0): *Default mode "640x480": 108.0 MHz (scaled from 31.5 MHz), 37.5 kHz, 75.0 Hz (II) R128(0): Modeline "640x480" 108.00 640 688 702 936 480 480 483 496 -hsync -vsync (**) R128(0): Default mode "1280x1024": 108.0 MHz, 64.0 kHz, 60.0 Hz (II) R128(0): Modeline "1280x1024" 108.00 1280 1328 1342 1576 1024 1025 1028 1045 +hsync +vsync (**) R128(0): Default mode "1024x768": 108.0 MHz (scaled from 75.0 MHz), 56.5 kHz, 70.1 Hz (II) R128(0): Modeline "1024x768" 108.00 1024 1072 1086 1320 768 769 772 784 -hsync -vsync (**) R128(0): Default mode "1024x768": 108.0 MHz (scaled from 65.0 MHz), 48.4 kHz, 60.0 Hz (II) R128(0): Modeline "1024x768" 108.00 1024 1072 1086 1320 768 769 772 784 -hsync -vsync (**) R128(0): Default mode "800x600": 108.0 MHz (scaled from 50.0 MHz), 48.1 kHz, 72.2 Hz (II) R128(0): Modeline "800x600" 108.00 800 848 862 1096 600 600 603 616 +hsync +vsync (**) R128(0): Default mode "800x600": 108.0 MHz (scaled from 40.0 MHz), 37.9 kHz, 60.3 Hz (II) R128(0): Modeline "800x600" 108.00 800 848 862 1096 600 600 603 616 +hsync +vsync (**) R128(0): Default mode "800x600": 108.0 MHz (scaled from 36.0 MHz), 35.2 kHz, 56.2 Hz (II) R128(0): Modeline "800x600" 108.00 800 848 862 1096 600 600 603 616 +hsync +vsync (**) R128(0): Default mode "640x480": 108.0 MHz (scaled from 31.5 MHz), 37.9 kHz, 72.8 Hz (II) R128(0): Modeline "640x480" 108.00 640 688 702 936 480 480 483 496 -hsync -vsync (**) R128(0): Default mode "640x480": 108.0 MHz (scaled from 25.2 MHz), 31.5 kHz, 60.0 Hz (II) R128(0): Modeline "640x480" 108.00 640 688 702 936 480 480 483 496 -hsync -vsync (==) R128(0): DPI set to (75, 75) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "shadowfb" (II) LoadModule: "shadowfb" (II) Loading /usr/X11R6/lib/modules/libshadowfb.a (II) Module shadowfb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) R128(0): Page flipping disabled (!!) R128(0): For information on using the multimedia capabilities of this adapter, please see http://gatos.sf.net. (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0xfcffc000 - 0xfcffffff (0x4000) MS[B] [1] 0 0 0xe8000000 - 0xebffffff (0x4000000) MS[B] [2] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [3] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [4] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [5] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [6] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [7] -1 0 0xf8ff8000 - 0xf8ffbfff (0x4000) MX[B] [8] -1 0 0xf8ffc800 - 0xf8ffcfff (0x800) MX[B] [9] -1 0 0xf8ffd000 - 0xf8ffd07f (0x80) MX[B] [10] -1 0 0xf8ffd400 - 0xf8ffd4ff (0x100) MX[B] [11] -1 0 0xf8ffd800 - 0xf8ffd87f (0x80) MX[B] [12] -1 0 0xf8ffdc00 - 0xf8ffdc7f (0x80) MX[B] [13] -1 0 0xf8ffe000 - 0xf8ffffff (0x2000) MX[B] [14] -1 0 0xe4000000 - 0xe3ffffff (0x0) MX[B]O [15] -1 0 0xfcffc000 - 0xfcffffff (0x4000) MX[B](B) [16] -1 0 0xe8000000 - 0xebffffff (0x4000000) MX[B](B) [17] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) [18] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) [19] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) [20] 0 0 0x0000cc00 - 0x0000ccff (0x100) IS[B] [21] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [22] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [23] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [24] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [25] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] [26] -1 0 0x0000dce0 - 0x0000dcff (0x20) IX[B] [27] -1 0 0x0000bfa0 - 0x0000bfaf (0x10) IX[B] [28] -1 0 0x0000cc00 - 0x0000ccff (0x100) IX[B](B) [29] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [30] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (==) R128(0): Write-combining range (0xe8000000,0x1000000) drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 5, (OK) drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 5, (OK) drmOpenDevice: minor is 0 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 5, (OK) drmGetBusid returned '' (II) R128(0): [drm] created "r128" driver at busid "PCI:1:0:0" (II) R128(0): [drm] added 8192 byte SAREA at 0xd8b1a000 (II) R128(0): [drm] mapped SAREA 0xd8b1a000 to 0x411ec000 (II) R128(0): [drm] framebuffer handle = 0xe8000000 (II) R128(0): [drm] added 1 reserved context for kernel (II) R128(0): [agp] Mode 0x1f000201 [AGP 0x8086/0x1130; Card 0x1002/0x4d46] (II) R128(0): [agp] 8192 kB allocated with handle 0x00000001 (II) R128(0): [agp] ring handle = 0xe4000000 (II) R128(0): [agp] Ring mapped at 0x411ee000 (II) R128(0): [agp] ring read ptr handle = 0xe4101000 (II) R128(0): [agp] Ring read ptr mapped at 0x412ef000 (II) R128(0): [agp] vertex/indirect buffers handle = 0xe4102000 (II) R128(0): [agp] Vertex/indirect buffers mapped at 0x412f0000 (II) R128(0): [agp] AGP texture map handle = 0xe4302000 (II) R128(0): [agp] AGP Texture map mapped at 0x414f0000 (II) R128(0): [drm] register handle = 0xfcffc000 (II) R128(0): [dri] Visual configs initialized (II) R128(0): CCE in BM mode (II) R128(0): Using 8 MB AGP aperture (II) R128(0): Using 1 MB for the ring buffer (II) R128(0): Using 2 MB for vertex/indirect buffers (II) R128(0): Using 5 MB for AGP textures (II) R128(0): Memory manager initialized to (0,0) (1408,4235) (II) R128(0): Reserved area from (0,1050) to (1408,1052) (II) R128(0): Largest offscreen area available: 1408 x 3183 (II) R128(0): Reserved back buffer from (0,1052) to (1400,2102) (II) R128(0): Reserved depth buffer from (0,2102) to (1400,3153) (II) R128(0): Reserved depth span from (0,3152) offset 0x877000 (II) R128(0): Reserved 4736 kb for textures at offset 0xb5f900 (II) R128(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Indirect CPU to Screen color expansion Solid Lines Dashed Lines Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 14 256x256 slots (II) R128(0): Acceleration enabled (==) R128(0): Backing store disabled (==) R128(0): Silken mouse enabled (II) R128(0): Using hardware cursor (scanline 6306) (II) R128(0): Largest offscreen area available: 1408 x 1080 (**) Option "dpms" (**) R128(0): DPMS enabled (II) R128(0): X context handle = 0x00000001 (II) R128(0): [drm] installed DRM signal handler (II) R128(0): [DRI] installation complete (II) R128(0): [drm] Added 128 16384 byte vertex/indirect buffers (II) R128(0): [drm] Mapped 128 vertex/indirect buffers (II) R128(0): [drm] dma control initialized, using IRQ 11 (II) R128(0): Direct rendering enabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (**) Option "Emulate3Buttons" "true" (**) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Configured Mouse: ZAxisMapping: buttons 4 and 5 (**) Configured Mouse: Buttons: 5 (II) Synaptics touchpad driver version 0.13.6 (--) Synaptics Touchpad auto-dev sets device to /dev/input/event1 (**) Option "Device" "/dev/input/event1" (--) Synaptics Touchpad synaptics touchpad found (**) Option "SendCoreEvents" "true" (**) Synaptics Touchpad: always reports core events (II) XINPUT: Adding extended input device "Synaptics Touchpad" (type: MOUSE) (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) Synaptics DeviceInit called SynapticsCtrl called. (II) Configured Mouse: ps2EnableDataReporting: succeeded Synaptics DeviceOn called (--) Synaptics Touchpad synaptics touchpad found Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! Synaptics DeviceOff called Synaptics DeviceOn called (--) Synaptics Touchpad synaptics touchpad found (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Configured Mouse: ps2EnableDataReporting: succeeded xresprobe-0.4.24ubuntu9/tests/log-radeon-derived-1024x7680000644000000000000000000005247510242533543017627 0ustar This is a pre-release version of the The X.Org Foundation X11. Portions of this release are based on XFree86 4.4RC2 and selected files from XFree86 4.4RC3. It is not supported in any way. Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/. Select the "xorg" product for bugs you find in this release. Before reporting bugs in pre-release versions please check the latest version in the The X.Org Foundation "monolithic tree" CVS repository hosted at http://www.freedesktop.org/Software/xorg/.99 Release Date: 12 August 2004 X Protocol Version 11, Revision 0, Release 6.7.99.2 Build Operating System: Linux 2.6.8 ppc [ELF] Current Operating System: Linux localhost 2.6.8 #1 Sat Aug 14 13:49:21 CEST 2004 ppc Build Date: 14 August 2004 Before reporting problems, check http://wiki.X.Org to make sure that you have the latest version. Module Loader present Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/Xorg.0.log", Time: Sat Aug 14 20:14:21 2004 (==) Using config file: "/etc/X11/XF86Config" (==) ServerLayout "Simple Layout" (**) |-->Screen "Screen1" (0) (**) | |-->Monitor "Monitor1" (**) | |-->Device "Card1" (**) |-->Input Device "Mouse1" (**) |-->Input Device "Keyboard1" (**) Option "AutoRepeat" "250 30" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "macintosh" (**) XKB: model: "macintosh" (**) Option "XkbLayout" "de_ibook" (**) XKB: layout: "de_ibook" (==) Keyboard: CustomKeycode disabled (WW) The directory "/usr/X11R6/lib/X11/fonts/PEX/" does not exist. Entry deleted from font path. (WW) The directory "/usr/X11R6/lib/X11/fonts/latin2/" does not exist. Entry deleted from font path. (WW) The directory "/usr/X11R6/lib/X11/fonts/sharefont" does not exist. Entry deleted from font path. (**) FontPath set to "/usr/X11R6/lib/X11/fonts/75dpi/:unscaled,/usr/X11R6/lib/X11/fonts/100dpi/:unscaled,/usr/X11R6/lib/X11/fonts/CID/,/usr/X11R6/lib/X11/fonts/Speedo/,/usr/X11R6/lib/X11/fonts/Type1/,/usr/X11R6/lib/X11/fonts/cyrillic/,/usr/X11R6/lib/X11/fonts/encodings/,/usr/X11R6/lib/X11/fonts/freefont/,/usr/X11R6/lib/X11/fonts/local/,/usr/X11R6/lib/X11/fonts/misc/,/usr/X11R6/lib/X11/fonts/TrueType,/usr/share/ghostscript/fonts/" (**) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (II) Open APM successful (II) Module ABI versions: X.Org ANSI C Emulation: 0.2 X.Org Video Driver: 0.7 X.Org XInput driver : 0.4 X.Org Server Extension : 0.2 X.Org Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (--) using VT number 7 (WW) xf86OpenConsole: Could not save ownership of VT (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:0b:0: chip 106b,0027 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 00:10:0: chip 1002,4c57 card 1002,4c57 rev 00 class 03,00,00 hdr 00 (II) PCI: 01:0b:0: chip 106b,0028 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 01:17:0: chip 106b,0025 card 0000,0000 rev 00 class ff,00,00 hdr 00 (II) PCI: 01:18:0: chip 106b,0026 card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:19:0: chip 106b,0026 card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 02:0b:0: chip 106b,0029 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:11:0), (0,0,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x00ffffff (0x1000000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 1: bridge is at (1:11:0), (1,1,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00000000 - 0x00ffffff (0x1000000) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 2: bridge is at (2:11:0), (2,2,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 2 I/O range: [0] -1 0 0x00000000 - 0x00ffffff (0x1000000) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (--) PCI:*(0:16:0) ATI Technologies Inc Radeon Mobility M7 LW [Radeon Mobility 7500] rev 0, Mem @ 0x98000000/27, 0x90000000/16, I/O @ 0x0400/8, BIOS @ 0xf1000000/17 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x00ffffff (0x1000000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x00ffffff - 0x00ffffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) Active PCI resource ranges: [0] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [1] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [2] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [3] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [4] -1 0 0x90000000 - 0x9000ffff (0x10000) MX[B](B) [5] -1 0 0x98000000 - 0x9fffffff (0x8000000) MX[B](B) [6] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [1] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [2] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [3] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [4] -1 0 0x90000000 - 0x9000ffff (0x10000) MX[B](B) [5] -1 0 0x98000000 - 0x9fffffff (0x8000000) MX[B](B) [6] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x00ffffff - 0x00ffffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) All system resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [3] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [4] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [5] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [6] -1 0 0x90000000 - 0x9000ffff (0x10000) MX[B](B) [7] -1 0 0x98000000 - 0x9fffffff (0x8000000) MX[B](B) [8] -1 0 0x00ffffff - 0x00ffffff (0x1) IX[B] [9] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [10] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.2 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.so (II) Module freetype: vendor="X.Org Foundation & the After X-TT Project" compiled for 6.7.99.2, module version = 2.1.0 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Module GLcore: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading extension GLX (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "ati" (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.o (II) Module ati: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 6.5.6 Module class: X.Org Video Driver ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.0.0 Module class: X.Org XInput Driver ABI class: X.Org XInput driver, version 0.4 (II) ATI: ATI driver (version 6.5.6) for chipset: ati (II) R128: Driver for ATI Rage 128 chipsets: ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), ATI Rage 128 Pro GL PA (PCI/AGP), ATI Rage 128 Pro GL PB (PCI/AGP), ATI Rage 128 Pro GL PC (PCI/AGP), ATI Rage 128 Pro GL PD (PCI), ATI Rage 128 Pro GL PE (PCI/AGP), ATI Rage 128 Pro GL PF (AGP), ATI Rage 128 Pro VR PG (PCI/AGP), ATI Rage 128 Pro VR PH (PCI/AGP), ATI Rage 128 Pro VR PI (PCI/AGP), ATI Rage 128 Pro VR PJ (PCI/AGP), ATI Rage 128 Pro VR PK (PCI/AGP), ATI Rage 128 Pro VR PL (PCI/AGP), ATI Rage 128 Pro VR PM (PCI/AGP), ATI Rage 128 Pro VR PN (PCI/AGP), ATI Rage 128 Pro VR PO (PCI/AGP), ATI Rage 128 Pro VR PP (PCI), ATI Rage 128 Pro VR PQ (PCI/AGP), ATI Rage 128 Pro VR PR (PCI), ATI Rage 128 Pro VR PS (PCI/AGP), ATI Rage 128 Pro VR PT (PCI/AGP), ATI Rage 128 Pro VR PU (PCI/AGP), ATI Rage 128 Pro VR PV (PCI/AGP), ATI Rage 128 Pro VR PW (PCI/AGP), ATI Rage 128 Pro VR PX (PCI/AGP), ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (PCI/AGP), ATI Rage 128 4X SF (PCI/AGP), ATI Rage 128 4X SG (PCI/AGP), ATI Rage 128 4X SH (PCI/AGP), ATI Rage 128 4X SK (PCI/AGP), ATI Rage 128 4X SL (PCI/AGP), ATI Rage 128 4X SM (AGP), ATI Rage 128 4X SN (PCI/AGP), ATI Rage 128 Pro ULTRA TF (AGP), ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), ATI Rage 128 Pro ULTRA TU (AGP?) (II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), ATI Radeon Mobility M7 LW (AGP), ATI Mobility FireGL 7800 M7 LX (AGP), ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon IGP330M/340M/350M (U2) 4337, ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), ATI Radeon Mobility 9000 (M9) Lf (AGP), ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9100 IGP (A5) 5834, ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835, ATI Radeon 9200PRO 5960 (AGP), ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), ATI Radeon 9200SE 5964 (AGP), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9700 NF (AGP), ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI FireGL RV360 AV (AGP), ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP), ATI Radeon Mobility 9600 (M10) NQ (AGP), ATI Radeon Mobility 9600 (M11) NR (AGP), ATI Radeon Mobility 9600 (M10) NS (AGP), ATI FireGL Mobility T2 (M10) NT (AGP), ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP), ATI Radeon X600 (RV380) 3E50 (PCIE), ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireGL M24 GL 3154 (PCIE), ATI Radeon X300 (RV370) 5B60 (PCIE), ATI Radeon X600 (RV370) 5B62 (PCIE), ATI FireGL V3100 (RV370) 5B64 (PCIE), ATI FireGL D1100 (RV370) 5B65 (PCIE), ATI Radeon Mobility M300 (M22) 5460 (PCIE), ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R420) JH (AGP), ATI Radeon X800PRO (R420) JI (AGP), ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP), ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP), ATI Radeon Mobility 9800 (M18) JN (AGP), ATI Radeon X800XT (R420) JP (AGP), ATI Radeon X800 (R423) UH (PCIE), ATI Radeon X800PRO (R423) UI (PCIE), ATI Radeon X800LE (R423) UJ (PCIE), ATI Radeon X800SE (R423) UK (PCIE), ATI FireGL V7200 (R423) UQ (PCIE), ATI FireGL V5100 (R423) UR (PCIE), ATI FireGL V7100 (R423) UT (PCIE), ATI Radeon X800XT (R423) 5D57 (PCIE) (II) Primary Device is: PCI 00:10:0 (II) ATI: Candidate "Device" section "Card1". (--) Assigning device section with no busID to primary device (--) Chipset ATI Radeon Mobility M7 LW (AGP) found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [3] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [4] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [5] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [6] -1 0 0x90000000 - 0x9000ffff (0x10000) MX[B](B) [7] -1 0 0x98000000 - 0x9fffffff (0x8000000) MX[B](B) [8] -1 0 0x00ffffff - 0x00ffffff (0x1) IX[B] [9] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [10] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) Loading sub module "radeon" (II) LoadModule: "radeon" (II) Loading /usr/X11R6/lib/modules/drivers/radeon_drv.o (II) Module radeon: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 4.0.1 Module class: X.Org Video Driver ABI class: X.Org Video Driver, version 0.7 (II) resource ranges after probing: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x80080000 - 0x80080fff (0x1000) MX[B] [3] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [4] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [5] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [6] -1 0 0x90000000 - 0x9000ffff (0x10000) MX[B](B) [7] -1 0 0x98000000 - 0x9fffffff (0x8000000) MX[B](B) [8] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [9] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [10] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [11] -1 0 0x00ffffff - 0x00ffffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [13] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) [14] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [15] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) RADEON(0): MMIO registers at 0x90000000 (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 0.1.0 ABI class: X.Org Video Driver, version 0.7 (II) RADEON(0): vgaHWGetIOBase: hwp->IOBase is 0x03b0, hwp->PIOOffset is 0x0000 (II) RADEON(0): PCI bus 0 card 16 func 0 (**) RADEON(0): Depth 24, (--) framebuffer bpp 32 (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) (==) RADEON(0): Default visual is TrueColor (==) RADEON(0): RGB weight 888 (II) RADEON(0): Using 8 bits per RGB (8 bit DAC) (--) RADEON(0): Chipset: "ATI Radeon Mobility M7 LW (AGP)" (ChipID = 0x4c57) (--) RADEON(0): Linear framebuffer at 0x98000000 (--) RADEON(0): BIOS at 0xf1000000 (--) RADEON(0): VideoRAM: 32768 kByte (64 bit DDR SDRAM) (II) RADEON(0): AGP card detected (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="X.Org Foundation" compiled for 6.7.99.2, module version = 1.2.0 ABI class: X.Org Video Driver, version 0.7 (II) RADEON(0): I2C bus "DDC" initialized. (WW) RADEON(0): Video BIOS not detected in PCI space! (WW) RADEON(0): Attempting to read Video BIOS from legacy ISA space! (WW) RADEON(0): Unrecognized BIOS signature, BIOS data will not be used (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): DDC Type: 2, Detected Type: 2 (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): DDC Type: 3, Detected Type: 0 (II) RADEON(0): EDID data from the display on port 1 ---------------------- (II) RADEON(0): Manufacturer: APP Model: 9c1a Serial#: 0 (II) RADEON(0): Year: 2001 Week: 31 (II) RADEON(0): EDID Version: 1.3 (II) RADEON(0): Digital Display Input (II) RADEON(0): Max H-Image Size [cm]: horiz.: 29 vert.: 21 (II) RADEON(0): Gamma: 2.20 (II) RADEON(0): No DPMS capabilities specified; RGB/Color Display (II) RADEON(0): redX: 0.580 redY: 0.339 greenX: 0.327 greenY: 0.533 (II) RADEON(0): blueX: 0.157 blueY: 0.143 whiteX: 0.320 whiteY: 0.330 (II) RADEON(0): Supported VESA Video Modes: (II) RADEON(0): 1024x768 at 60Hz (II) RADEON(0): Manufacturer's mask: 0 (II) RADEON(0): Supported additional Video Mode: (II) RADEON(0): clock: 65.0 MHz Image Size: 285 x 214 mm (II) RADEON(0): h_active: 1024 h_sync: 1048 h_sync_end 1184 h_blank_end 1344 h_border: 0 (II) RADEON(0): v_active: 768 v_sync: 771 v_sync_end 777 v_blanking: 806 v_border: 0 (II) RADEON(0): LTN141XF (II) RADEON(0): LTN141XF (II) RADEON(0): Monitor name: Color LCD (II) RADEON(0): (II) RADEON(0): Primary: Monitor -- LVDS Connector -- DVI-D DAC Type -- TVDAC/ExtDAC TMDS Type -- Internal DDC Type -- DVI_DDC (II) RADEON(0): Secondary: Monitor -- NONE Connector -- VGA DAC Type -- Primary TMDS Type -- External DDC Type -- VGA_DDC (WW) RADEON(0): Video BIOS not detected, using default clock settings! (II) RADEON(0): PLL parameters: rf=2700 rd=12 min=12500 max=35000; xclk=10300 (WW) RADEON(0): Panel size 1024x768 is derived, this may not be correct. If not, use PanelSize option to overwrite this setting (WW) RADEON(0): No valid timing info from BIOS. xresprobe-0.4.24ubuntu9/tests/incomplete-savage.log0000644000000000000000000000013110214367723017304 0ustar # found from good old Google (--) SAVAGE(0): 1024x768 TFT LCD panel detected and active xresprobe-0.4.24ubuntu9/tests/incomplete-radeon.log0000644000000000000000000000035010214367723017311 0ustar # from Keybuk (II) RADEON(0): Displays Detected: Monitor1--Type 2, Monitor2--Type 0 (II) RADEON(0): (II) RADEON(0): Primary Display == Type 2 (II) RADEON(0): Panel ID string: 1024x768 (II) RADEON(0): Panel Size from BIOS: 1024x768 xresprobe-0.4.24ubuntu9/tests/log-radeon-1280x8540000644000000000000000000007116110214367723016204 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Debian 4.3.0.dfsg.1-6 20040709050738 branden@redwald.deadbeast.net) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.4.25-powerpc-smp ppc [ELF] Build Date: 09 July 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.7-powerpc (jens@yorick) (gcc version 3.3.4 (Debian 1:3.3.4-5)) #1 Tue Jul 27 19:01:34 CEST 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Thu Aug 19 12:20:35 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "PowerBook Panel" (**) | |-->Device "PowerBook Internal Video" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "macintosh" (**) XKB: model: "macintosh" (**) Option "XkbLayout" "gb" (**) XKB: layout: "gb" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/75dpi,/usr/lib/X11/fonts/100dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:0b:0: chip 106b,0034 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 00:10:0: chip 1002,4e50 card 1002,4e50 rev 00 class 03,00,00 hdr 00 (II) PCI: 01:0b:0: chip 106b,0035 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 01:12:0: chip 14e4,4320 card 106b,004e rev 03 class 02,80,00 hdr 00 (II) PCI: 01:13:0: chip 104c,ac56 card 1000,0000 rev 00 class 06,07,00 hdr 02 (II) PCI: 01:17:0: chip 106b,003e card 0000,0000 rev 00 class ff,00,00 hdr 00 (II) PCI: 01:18:0: chip 106b,003f card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:19:0: chip 106b,003f card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:1a:0: chip 106b,003f card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:1b:0: chip 1033,0035 card 1033,0035 rev 43 class 0c,03,10 hdr 80 (II) PCI: 01:1b:1: chip 1033,0035 card 1033,0035 rev 43 class 0c,03,10 hdr 00 (II) PCI: 01:1b:2: chip 1033,00e0 card 1033,00e0 rev 04 class 0c,03,20 hdr 00 (II) PCI: 06:0b:0: chip 106b,0036 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 06:0d:0: chip 106b,003b card 0000,0000 rev 00 class ff,00,00 hdr 00 (II) PCI: 06:0e:0: chip 106b,0031 card 106b,5811 rev 81 class 0c,00,10 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:11:0), (0,0,6), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 1: bridge is at (1:11:0), (1,1,6), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-CardBus bridge: (II) Bus 2: bridge is at (1:19:0), (1,2,5), BCTRL: 0x05c0 (VGA_EN is cleared) (II) Bus 2 I/O range: [0] -1 0 0x00001000 - 0x000010ff (0x100) IX[B] [1] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0xf3200000 - 0xf33fffff (0x200000) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0x90000000 - 0x9fffffff (0x10000000) MX[B] (II) Host-to-PCI bridge: (II) Bus 6: bridge is at (6:11:0), (6,6,6), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 6 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 6 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 6 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (--) PCI:*(0:16:0) ATI Technologies Inc unknown chipset (0x4e50) rev 0, Mem @ 0xb8000000/27, 0xb0000000/16, I/O @ 0x0400/8, BIOS @ 0xf1000000/17 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) Active PCI resource ranges: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [2] -1 0 0xa0000000 - 0xa00000ff (0x100) MX[B] [3] -1 0 0xa0001000 - 0xa0001fff (0x1000) MX[B] [4] -1 0 0xa0002000 - 0xa0002fff (0x1000) MX[B] [5] -1 0 0xa0003000 - 0xa0003fff (0x1000) MX[B] [6] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [7] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [8] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [9] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [10] -1 0 0xb0000000 - 0xb000ffff (0x10000) MX[B](B) [11] -1 0 0xb8000000 - 0xbfffffff (0x8000000) MX[B](B) [12] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) Inactive PCI resource ranges: [0] -1 0 0xa0006000 - 0xa0007fff (0x2000) MX[B] (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [2] -1 0 0xa0000000 - 0xa00000ff (0x100) MX[B] [3] -1 0 0xa0001000 - 0xa0001fff (0x1000) MX[B] [4] -1 0 0xa0002000 - 0xa0002fff (0x1000) MX[B] [5] -1 0 0xa0003000 - 0xa0003fff (0x1000) MX[B] [6] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [7] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [8] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [9] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [10] -1 0 0xb0000000 - 0xb000ffff (0x10000) MX[B](B) [11] -1 0 0xb8000000 - 0xbfffffff (0x8000000) MX[B](B) [12] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) Inactive PCI resource ranges after removing overlaps: [0] -1 0 0xa0006000 - 0xa0007fff (0x2000) MX[B] (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) All system resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [4] -1 0 0xa0000000 - 0xa00000ff (0x100) MX[B] [5] -1 0 0xa0001000 - 0xa0001fff (0x1000) MX[B] [6] -1 0 0xa0002000 - 0xa0002fff (0x1000) MX[B] [7] -1 0 0xa0003000 - 0xa0003fff (0x1000) MX[B] [8] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [9] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [10] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [11] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [12] -1 0 0xb0000000 - 0xb000ffff (0x10000) MX[B](B) [13] -1 0 0xb8000000 - 0xbfffffff (0x8000000) MX[B](B) [14] -1 0 0xa0006000 - 0xa0007fff (0x2000) MX[B] [15] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [16] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [17] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension GLX (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "ati" (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.o (II) Module ati: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) ATI: ATI driver (version 6.5.5) for chipset: ati (II) R128: Driver for ATI Rage 128 chipsets: ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), ATI Rage 128 Pro GL PA (AGP?), ATI Rage 128 Pro GL PB (AGP?), ATI Rage 128 Pro GL PC (AGP?), ATI Rage 128 Pro GL PD (PCI), ATI Rage 128 Pro GL PE (AGP?), ATI Rage 128 Pro GL PF (AGP), ATI Rage 128 Pro VR PG (AGP?), ATI Rage 128 Pro VR PH (AGP?), ATI Rage 128 Pro VR PI (AGP?), ATI Rage 128 Pro VR PJ (AGP?), ATI Rage 128 Pro VR PK (AGP?), ATI Rage 128 Pro VR PL (AGP?), ATI Rage 128 Pro VR PM (AGP?), ATI Rage 128 Pro VR PN (AGP?), ATI Rage 128 Pro VR PO (AGP?), ATI Rage 128 Pro VR PP (PCI), ATI Rage 128 Pro VR PQ (AGP?), ATI Rage 128 Pro VR PR (PCI), ATI Rage 128 Pro VR PS (AGP?), ATI Rage 128 Pro VR PT (AGP?), ATI Rage 128 Pro VR PU (AGP?), ATI Rage 128 Pro VR PV (AGP?), ATI Rage 128 Pro VR PW (AGP?), ATI Rage 128 Pro VR PX (AGP?), ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (AGP?), ATI Rage 128 4X SF (AGP?), ATI Rage 128 4X SG (AGP?), ATI Rage 128 4X SH (AGP?), ATI Rage 128 4X SK (AGP?), ATI Rage 128 4X SL (AGP?), ATI Rage 128 4X SM (AGP), ATI Rage 128 4X SN (AGP?), ATI Rage 128 Pro ULTRA TF (AGP), ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), ATI Rage 128 Pro ULTRA TU (AGP?) (II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), ATI Radeon Mobility M7 LW (AGP), ATI Mobility FireGL 7800 M7 LX (AGP), ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon IGP330M/340M/350M (U2) 4337, ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), ATI Radeon Mobility 9000 (M9) Lf (AGP), ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9100 IGP (A5) 5834, ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9200PRO 5960 (AGP), ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), ATI Radeon 9200SE 5964 (AGP), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9700 NF (AGP), ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI FireGL RV360 AV (AGP), ATI Radeon Mobility 9600 (M10) NP (AGP), ATI Radeon Mobility 9600 (M10) NQ (AGP), ATI Radeon Mobility 9600 (M11) NR (AGP), ATI Radeon Mobility 9600 (M10) NS (AGP), ATI FireGL Mobility T2 (M10) NT (AGP), ATI FireGL Mobility T2 (M11) NV (AGP), ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP) (II) Primary Device is: PCI 00:10:0 (II) ATI: Candidate "Device" section "PowerBook Internal Video". (--) Assigning device section with no busID to primary device (--) Chipset ATI Radeon Mobility 9600 (M10) NP (AGP) found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [4] -1 0 0xa0000000 - 0xa00000ff (0x100) MX[B] [5] -1 0 0xa0001000 - 0xa0001fff (0x1000) MX[B] [6] -1 0 0xa0002000 - 0xa0002fff (0x1000) MX[B] [7] -1 0 0xa0003000 - 0xa0003fff (0x1000) MX[B] [8] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [9] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [10] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [11] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [12] -1 0 0xb0000000 - 0xb000ffff (0x10000) MX[B](B) [13] -1 0 0xb8000000 - 0xbfffffff (0x8000000) MX[B](B) [14] -1 0 0xa0006000 - 0xa0007fff (0x2000) MX[B] [15] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [16] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [17] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) (II) Loading sub module "radeon" (II) LoadModule: "radeon" (II) Loading /usr/X11R6/lib/modules/drivers/radeon_drv.o (II) Module radeon: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 4.0.1 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) resource ranges after probing: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [3] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [4] -1 0 0xa0000000 - 0xa00000ff (0x100) MX[B] [5] -1 0 0xa0001000 - 0xa0001fff (0x1000) MX[B] [6] -1 0 0xa0002000 - 0xa0002fff (0x1000) MX[B] [7] -1 0 0xa0003000 - 0xa0003fff (0x1000) MX[B] [8] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [9] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [10] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [11] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [12] -1 0 0xb0000000 - 0xb000ffff (0x10000) MX[B](B) [13] -1 0 0xb8000000 - 0xbfffffff (0x8000000) MX[B](B) [14] -1 0 0xa0006000 - 0xa0007fff (0x2000) MX[B] [15] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [16] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [17] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [18] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [19] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [20] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) [21] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [22] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) RADEON(0): MMIO registers at 0xb0000000 (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) RADEON(0): vgaHWGetIOBase: hwp->IOBase is 0x03b0, hwp->PIOOffset is 0x0000 (II) RADEON(0): PCI bus 0 card 16 func 0 (**) RADEON(0): Depth 24, (--) framebuffer bpp 32 (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) (==) RADEON(0): Default visual is TrueColor (==) RADEON(0): RGB weight 888 (II) RADEON(0): Using 8 bits per RGB (8 bit DAC) (--) RADEON(0): Chipset: "ATI Radeon Mobility 9600 (M10) NP (AGP)" (ChipID = 0x4e50) (--) RADEON(0): Linear framebuffer at 0xb8000000 (--) RADEON(0): BIOS at 0xf1000000 (--) RADEON(0): VideoRAM: 65536 kByte (128 bit DDR SDRAM) (II) RADEON(0): AGP card detected (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.2.0 ABI class: XFree86 Video Driver, version 0.6 (II) RADEON(0): I2C bus "DDC" initialized. (WW) RADEON(0): Video BIOS not detected in PCI space! (WW) RADEON(0): Attempting to read Video BIOS from legacy ISA space! (WW) RADEON(0): Video BIOS not found! (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): DDC Type: 2, Detected Type: 2 (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) RADEON(0): I2C device "DDC:ddc2" removed. (II) RADEON(0): DDC Type: 3, Detected Type: 0 (II) RADEON(0): DDC Type: 4, Detected Type: 0 (II) RADEON(0): Displays Detected: Monitor1--Type 2, Monitor2--Type 0 (II) RADEON(0): Monitor1 EDID data --------------------------- (II) RADEON(0): Manufacturer: APP Model: 9c20 Serial#: 16843009 (II) RADEON(0): Year: 2002 Week: 5 (II) RADEON(0): EDID Version: 1.3 (II) RADEON(0): Digital Display Input (II) RADEON(0): Max H-Image Size [cm]: horiz.: 32 vert.: 22 (II) RADEON(0): Gamma: 2.20 (II) RADEON(0): No DPMS capabilities specified; RGB/Color Display (II) RADEON(0): First detailed timing is preferred mode (II) RADEON(0): redX: 0.600 redY: 0.350 greenX: 0.310 greenY: 0.550 (II) RADEON(0): blueX: 0.150 blueY: 0.115 whiteX: 0.320 whiteY: 0.330 (II) RADEON(0): Manufacturer's mask: 0 (II) RADEON(0): Supported additional Video Mode: (II) RADEON(0): clock: 79.8 MHz Image Size: 321 x 214 mm (II) RADEON(0): h_active: 1280 h_sync: 1296 h_sync_end 1408 h_blank_end 1536 h_border: 0 (II) RADEON(0): v_active: 854 v_sync: 855 v_sync_end 858 v_blanking: 866 v_border: 0 (II) RADEON(0): LTN152W3 (II) RADEON(0): LTN152W3 (II) RADEON(0): Monitor name: Color LCD (II) RADEON(0): End of Monitor1 EDID data -------------------- (II) RADEON(0): (II) RADEON(0): Primary Display == Type 2 (WW) RADEON(0): No valid info for SCLK/MCLK for display bandwidth calculation. (==) RADEON(0): Using gamma correction (1.0, 1.0, 1.0) (II) RADEON(0): Validating modes on Primary head --------- (II) RADEON(0): Panel size found from DDC: 1280x854 (II) RADEON(0): Valid Mode from Detailed timing table: 1280x854 (II) RADEON(0): Total of 1 mode(s) found. (II) RADEON(0): Total number of valid DDC mode(s) found: 1 (II) RADEON(0): No valid mode specified, force to native mdoe (II) RADEON(0): Total number of valid FP mode(s) found: 1 (--) RADEON(0): Virtual size is 1280x854 (pitch 1280) (**) RADEON(0): *Mode "1280x854": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "1280x854" 79.81 1280 1296 1408 1536 854 855 858 866 (**) RADEON(0): Default mode "640x350": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "640x350" 79.81 640 1296 1408 1536 350 855 858 866 (**) RADEON(0): Default mode "640x400": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "640x400" 79.81 640 1296 1408 1536 400 855 858 866 (**) RADEON(0): Default mode "720x400": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "720x400" 79.81 720 1296 1408 1536 400 855 858 866 (**) RADEON(0): Default mode "640x480": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "640x480" 79.81 640 1296 1408 1536 480 855 858 866 (**) RADEON(0): Default mode "800x600": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "800x600" 79.81 800 1296 1408 1536 600 855 858 866 (**) RADEON(0): Default mode "1024x768": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "1024x768" 79.81 1024 1296 1408 1536 768 855 858 866 (**) RADEON(0): Default mode "832x624": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "832x624" 79.81 832 1296 1408 1536 624 855 858 866 (**) RADEON(0): Default mode "1152x768": 79.8 MHz (scaled from 0.0 MHz), 52.0 kHz, 60.0 Hz (II) RADEON(0): Modeline "1152x768" 79.81 1152 1296 1408 1536 768 855 858 866 (--) RADEON(0): Display dimensions: (320, 220) mm (--) RADEON(0): DPI set to (101, 98) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) RADEON(0): AGP Fast Write disabled by default (II) RADEON(0): Depth moves disabled by default (II) Loading sub module "shadowfb" (II) LoadModule: "shadowfb" (II) Loading /usr/X11R6/lib/modules/libshadowfb.a (II) Module shadowfb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) RADEON(0): Page flipping disabled (!!) RADEON(0): For information on using the multimedia capabilities of this adapter, please see http://gatos.sf.net. (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0xb0000000 - 0xb000ffff (0x10000) MX[B] [1] 0 0 0xb8000000 - 0xbfffffff (0x8000000) MX[B] [2] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [4] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [5] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [6] -1 0 0xa0000000 - 0xa00000ff (0x100) MX[B] [7] -1 0 0xa0001000 - 0xa0001fff (0x1000) MX[B] [8] -1 0 0xa0002000 - 0xa0002fff (0x1000) MX[B] [9] -1 0 0xa0003000 - 0xa0003fff (0x1000) MX[B] [10] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [11] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [12] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [13] -1 0 0xf1000000 - 0xf101ffff (0x20000) MX[B](B) [14] -1 0 0xb0000000 - 0xb000ffff (0x10000) MX[B](B) [15] -1 0 0xb8000000 - 0xbfffffff (0x8000000) MX[B](B) [16] -1 0 0xa0006000 - 0xa0007fff (0x2000) MX[B] [17] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) [18] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) [19] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) [20] 0 0 0x00000400 - 0x000004ff (0x100) IX[B] [21] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [22] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [23] -1 0 0x00000400 - 0x000004ff (0x100) IX[B](B) [24] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [25] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (WW) RADEON(0): Direct rendering not yet supported on Radeon 9500/9700 and newer cards (II) RADEON(0): Memory manager initialized to (0,0) (1280,8191) (II) RADEON(0): Reserved area from (0,854) to (1280,856) (II) RADEON(0): Largest offscreen area available: 1280 x 7335 (II) RADEON(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Indirect CPU to Screen color expansion Solid Lines Scanline Image Writes Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 32 256x256 slots 16 512x512 slots (II) RADEON(0): Acceleration enabled (==) RADEON(0): Backing store disabled (==) RADEON(0): Silken mouse enabled (II) RADEON(0): Using hardware cursor (scanline 856) (II) RADEON(0): Largest offscreen area available: 1280 x 7331 (**) Option "dpms" (**) RADEON(0): DPMS enabled (II) RADEON(0): Direct rendering disabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (**) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Configured Mouse: ZAxisMapping: buttons 4 and 5 (**) Configured Mouse: Buttons: 5 (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) Server_Terminate keybinding not found (II) Configured Mouse: ps2EnableDataReporting: succeeded Could not init font path element unix/:7100, removing from list! Could not init font path element /usr/lib/X11/fonts/Speedo, removing from list! (II) 3rd Button detected: disabling emulate3Button xresprobe-0.4.24ubuntu9/tests/ddc-monitor-1600x12000000644000000000000000000000277510214367723016437 0ustar vbe: VESA 3.0 detected. oem: NVidia vendor: NVidia Corporation product: Riva TNT Chip Rev B1 memory: 16384kb mode: 640x400x256 mode: 640x480x256 mode: 800x600x16 mode: 800x600x256 mode: 1024x768x16 mode: 1024x768x256 mode: 1280x1024x16 mode: 1280x1024x256 mode: 80x60 (text) mode: 132x25 (text) mode: 132x43 (text) mode: 132x50 (text) mode: 132x60 (text) mode: 320x200x64k mode: 320x200x16m mode: 640x480x64k mode: 640x480x16m mode: 800x600x64k mode: 800x600x16m mode: 1024x768x64k mode: 1024x768x16m mode: 1280x1024x64k edid: 1 2 id: 04b0 eisa: SNY04b0 serial: 005c3bd8 manufacture: 2 2001 input: separate sync, composite sync, sync on green, analog signal. screensize: 40 30 gamma: 2.500000 dpms: RGB, active off, suspend, standby timing: 720x400@70 Hz (VGA 640x400, IBM) timing: 720x400@88 Hz (XGA2) timing: 640x480@60 Hz (VGA) timing: 640x480@67 Hz (Mac II, Apple) timing: 640x480@72 Hz (VESA) timing: 640x480@75 Hz (VESA) timing: 800x600@56 Hz (VESA) timing: 800x600@60 Hz (VESA) timing: 800x600@72 Hz (VESA) timing: 800x600@75 Hz (VESA) timing: 832x624@75 Hz (Mac II) timing: 1024x768@87 Hz Interlaced (8514A) timing: 1024x768@60 Hz (VESA) timing: 1024x768@70 Hz (VESA) timing: 1024x768@75 Hz (VESA) timing: 1280x1024@75 (VESA) ctiming: 640x480@85 ctiming: 800x600@85 ctiming: 1024x768@85 ctiming: 1152x864@85 ctiming: 1280x960@75 ctiming: 1280x1024@85 ctiming: 1600x1200@85 ctiming: 2048x1536@60 timing0: 157500000 256 1472 0 1072 64 160 3 1 388x 291 monitorrange: 30-109, 48-160 monitorname: CPD-E500E monitorserial: 6044632 xresprobe-0.4.24ubuntu9/tests/log-mach64-1024x768-fabio0000644000000000000000000011500410214367723017067 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Debian 4.3.0.dfsg.1-6 20040707142024 fabbione@fabbione.net) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.4.23 i686 [ELF] Build Date: 07 July 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.7-1-686 (dilinger@toaster.hq.voxel.net) (gcc version 3.3.4 (Debian 1:3.3.4-2)) #1 Thu Jul 8 05:36:53 EDT 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Thu Aug 19 09:33:52 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Generic Monitor" (**) | |-->Device "Generic Video Card" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "pc104" (**) XKB: model: "pc104" (**) Option "XkbLayout" "dk" (**) XKB: layout: "dk" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (**) |-->Input Device "Generic Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: Probing config type using method 1 (II) PCI: Config type is 1 (II) PCI: stages = 0x03, oldVal1 = 0x8000213c, mode1Res1 = 0x80000000 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,7190 card 0e11,b110 rev 03 class 06,00,00 hdr 00 (II) PCI: 00:01:0: chip 8086,7191 card 0000,0000 rev 03 class 06,04,00 hdr 01 (II) PCI: 00:04:0: chip 104c,ac1b card 4400,0000 rev 03 class 06,07,00 hdr 82 (II) PCI: 00:04:1: chip 104c,ac1b card 4c00,0000 rev 03 class 06,07,00 hdr 82 (II) PCI: 00:07:0: chip 8086,7110 card 0000,0000 rev 02 class 06,80,00 hdr 80 (II) PCI: 00:07:1: chip 8086,7111 card 0000,0000 rev 01 class 01,01,80 hdr 00 (II) PCI: 00:07:2: chip 8086,7112 card 0000,0000 rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:07:3: chip 8086,7113 card 0000,0000 rev 03 class 06,80,00 hdr 00 (II) PCI: 00:08:0: chip 125d,1978 card 0e11,b112 rev 10 class 04,01,00 hdr 00 (II) PCI: 00:09:0: chip 8086,1229 card 8086,2203 rev 09 class 02,00,00 hdr 80 (II) PCI: 00:09:1: chip 11c1,0445 card 8086,2203 rev 00 class 07,00,00 hdr 80 (II) PCI: 01:00:0: chip 1002,4c4d card 0e11,b111 rev 64 class 03,00,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (0,0,6), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-PCI bridge: (II) Bus 1: bridge is at (0:1:0), (0,1,1), BCTRL: 0x008c (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00002000 - 0x000020ff (0x100) IX[B] [1] -1 0 0x00002400 - 0x000024ff (0x100) IX[B] [2] -1 0 0x00002800 - 0x000028ff (0x100) IX[B] [3] -1 0 0x00002c00 - 0x00002cff (0x100) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x40000000 - 0x410fffff (0x1100000) MX[B] (II) PCI-to-CardBus bridge: (II) Bus 2: bridge is at (0:4:0), (0,2,5), BCTRL: 0x05c0 (VGA_EN is cleared) (II) Bus 2 I/O range: [0] -1 0 0x00004400 - 0x000044ff (0x100) IX[B] [1] -1 0 0x00004800 - 0x000048ff (0x100) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0x24400000 - 0x247fffff (0x400000) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0x24000000 - 0x243fffff (0x400000) MX[B] (II) PCI-to-CardBus bridge: (II) Bus 6: bridge is at (0:4:1), (0,6,9), BCTRL: 0x05c0 (VGA_EN is cleared) (II) Bus 6 I/O range: [0] -1 0 0x00004c00 - 0x00004cff (0x100) IX[B] [1] -1 0 0x00005400 - 0x000054ff (0x100) IX[B] (II) Bus 6 non-prefetchable memory range: [0] -1 0 0x24c00000 - 0x24ffffff (0x400000) MX[B] (II) Bus 6 prefetchable memory range: [0] -1 0 0x24800000 - 0x24bfffff (0x400000) MX[B] (--) PCI:*(1:0:0) ATI Technologies Inc Rage Mobility P/M AGP 2x rev 100, Mem @ 0x40000000/24, 0x41000000/12, I/O @ 0x2000/8 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) PCI Memory resource overlap reduced 0x50000000 from 0x53ffffff to 0x4fffffff (II) Active PCI resource ranges: [0] -1 0 0x41300000 - 0x41300fff (0x1000) MX[B] [1] -1 0 0x41200000 - 0x4121ffff (0x20000) MX[B] [2] -1 0 0x41280000 - 0x41280fff (0x1000) MX[B] [3] -1 0 0x50000000 - 0x4fffffff (0x0) MX[B]O [4] -1 0 0x41000000 - 0x41000fff (0x1000) MX[B](B) [5] -1 0 0x40000000 - 0x40ffffff (0x1000000) MX[B](B) [6] -1 0 0x00003430 - 0x00003437 (0x8) IX[B] [7] -1 0 0x00003440 - 0x0000347f (0x40) IX[B] [8] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [9] -1 0 0x00003400 - 0x0000341f (0x20) IX[B] [10] -1 0 0x00003420 - 0x0000342f (0x10) IX[B] [11] -1 0 0x00002000 - 0x000020ff (0x100) IX[B](B) (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0x41300000 - 0x41300fff (0x1000) MX[B] [1] -1 0 0x41200000 - 0x4121ffff (0x20000) MX[B] [2] -1 0 0x41280000 - 0x41280fff (0x1000) MX[B] [3] -1 0 0x50000000 - 0x4fffffff (0x0) MX[B]O [4] -1 0 0x41000000 - 0x41000fff (0x1000) MX[B](B) [5] -1 0 0x40000000 - 0x40ffffff (0x1000000) MX[B](B) [6] -1 0 0x00003430 - 0x00003437 (0x8) IX[B] [7] -1 0 0x00003440 - 0x0000347f (0x40) IX[B] [8] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [9] -1 0 0x00003400 - 0x0000341f (0x20) IX[B] [10] -1 0 0x00003420 - 0x0000342f (0x10) IX[B] [11] -1 0 0x00002000 - 0x000020ff (0x100) IX[B](B) (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x41300000 - 0x41300fff (0x1000) MX[B] [6] -1 0 0x41200000 - 0x4121ffff (0x20000) MX[B] [7] -1 0 0x41280000 - 0x41280fff (0x1000) MX[B] [8] -1 0 0x50000000 - 0x4fffffff (0x0) MX[B]O [9] -1 0 0x41000000 - 0x41000fff (0x1000) MX[B](B) [10] -1 0 0x40000000 - 0x40ffffff (0x1000000) MX[B](B) [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [13] -1 0 0x00003430 - 0x00003437 (0x8) IX[B] [14] -1 0 0x00003440 - 0x0000347f (0x40) IX[B] [15] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [16] -1 0 0x00003400 - 0x0000341f (0x20) IX[B] [17] -1 0 0x00003420 - 0x0000342f (0x10) IX[B] [18] -1 0 0x00002000 - 0x000020ff (0x100) IX[B](B) (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "ati" (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.o (II) Module ati: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) ATI: ATI driver (version 6.5.5) for chipsets: ati, ativga (II) R128: Driver for ATI Rage 128 chipsets: ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), ATI Rage 128 Pro GL PA (AGP?), ATI Rage 128 Pro GL PB (AGP?), ATI Rage 128 Pro GL PC (AGP?), ATI Rage 128 Pro GL PD (PCI), ATI Rage 128 Pro GL PE (AGP?), ATI Rage 128 Pro GL PF (AGP), ATI Rage 128 Pro VR PG (AGP?), ATI Rage 128 Pro VR PH (AGP?), ATI Rage 128 Pro VR PI (AGP?), ATI Rage 128 Pro VR PJ (AGP?), ATI Rage 128 Pro VR PK (AGP?), ATI Rage 128 Pro VR PL (AGP?), ATI Rage 128 Pro VR PM (AGP?), ATI Rage 128 Pro VR PN (AGP?), ATI Rage 128 Pro VR PO (AGP?), ATI Rage 128 Pro VR PP (PCI), ATI Rage 128 Pro VR PQ (AGP?), ATI Rage 128 Pro VR PR (PCI), ATI Rage 128 Pro VR PS (AGP?), ATI Rage 128 Pro VR PT (AGP?), ATI Rage 128 Pro VR PU (AGP?), ATI Rage 128 Pro VR PV (AGP?), ATI Rage 128 Pro VR PW (AGP?), ATI Rage 128 Pro VR PX (AGP?), ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (AGP?), ATI Rage 128 4X SF (AGP?), ATI Rage 128 4X SG (AGP?), ATI Rage 128 4X SH (AGP?), ATI Rage 128 4X SK (AGP?), ATI Rage 128 4X SL (AGP?), ATI Rage 128 4X SM (AGP), ATI Rage 128 4X SN (AGP?), ATI Rage 128 Pro ULTRA TF (AGP), ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), ATI Rage 128 Pro ULTRA TU (AGP?) (II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), ATI Radeon Mobility M7 LW (AGP), ATI Mobility FireGL 7800 M7 LX (AGP), ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon IGP330M/340M/350M (U2) 4337, ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), ATI Radeon Mobility 9000 (M9) Lf (AGP), ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9100 IGP (A5) 5834, ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9200PRO 5960 (AGP), ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), ATI Radeon 9200SE 5964 (AGP), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9700 NF (AGP), ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI FireGL RV360 AV (AGP), ATI Radeon Mobility 9600 (M10) NP (AGP), ATI Radeon Mobility 9600 (M10) NQ (AGP), ATI Radeon Mobility 9600 (M11) NR (AGP), ATI Radeon Mobility 9600 (M10) NS (AGP), ATI FireGL Mobility T2 (M10) NT (AGP), ATI FireGL Mobility T2 (M11) NV (AGP), ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP) (II) Primary Device is: PCI 01:00:0 (II) ATI: Candidate "Device" section "Generic Video Card". (II) ATI: Shared PCI/AGP Mach64 in slot 1:0:0 detected. (II) ATI: Shared PCI/AGP Mach64 in slot 1:0:0 assigned to active "Device" section "Generic Video Card". (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x41300000 - 0x41300fff (0x1000) MX[B] [6] -1 0 0x41200000 - 0x4121ffff (0x20000) MX[B] [7] -1 0 0x41280000 - 0x41280fff (0x1000) MX[B] [8] -1 0 0x50000000 - 0x4fffffff (0x0) MX[B]O [9] -1 0 0x41000000 - 0x41000fff (0x1000) MX[B](B) [10] -1 0 0x40000000 - 0x40ffffff (0x1000000) MX[B](B) [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [13] -1 0 0x00003430 - 0x00003437 (0x8) IX[B] [14] -1 0 0x00003440 - 0x0000347f (0x40) IX[B] [15] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [16] -1 0 0x00003400 - 0x0000341f (0x20) IX[B] [17] -1 0 0x00003420 - 0x0000342f (0x10) IX[B] [18] -1 0 0x00002000 - 0x000020ff (0x100) IX[B](B) (II) Loading sub module "atimisc" (II) LoadModule: "atimisc" (II) Loading /usr/X11R6/lib/modules/drivers/atimisc_drv.o (II) Module atimisc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 6.5.5 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x41300000 - 0x41300fff (0x1000) MX[B] [6] -1 0 0x41200000 - 0x4121ffff (0x20000) MX[B] [7] -1 0 0x41280000 - 0x41280fff (0x1000) MX[B] [8] -1 0 0x50000000 - 0x4fffffff (0x0) MX[B]O [9] -1 0 0x41000000 - 0x41000fff (0x1000) MX[B](B) [10] -1 0 0x40000000 - 0x40ffffff (0x1000000) MX[B](B) [11] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [12] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [13] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [14] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [15] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [16] -1 0 0x00003430 - 0x00003437 (0x8) IX[B] [17] -1 0 0x00003440 - 0x0000347f (0x40) IX[B] [18] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [19] -1 0 0x00003400 - 0x0000341f (0x20) IX[B] [20] -1 0 0x00003420 - 0x0000342f (0x10) IX[B] [21] -1 0 0x00002000 - 0x000020ff (0x100) IX[B](B) [22] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [23] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (==) ATI(0): Chipset: "ati". (**) ATI(0): Depth 24, (--) framebuffer bpp 32 (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) ATI(0): Primary V_BIOS segment is: 0xc000 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Reloading /usr/X11R6/lib/modules/libvbe.a (II) ATI(0): VESA BIOS detected (II) ATI(0): VESA VBE Version 2.0 (II) ATI(0): VESA VBE Total Mem: 8128 kB (II) ATI(0): VESA VBE OEM: ATI MACH64 (II) ATI(0): VESA VBE OEM Software Rev: 1.0 (II) ATI(0): VESA VBE OEM Vendor: ATI Technologies Inc. (II) ATI(0): VESA VBE OEM Product: MACH64RM (II) ATI(0): VESA VBE OEM Product Rev: 01.00 (II) ATI(0): VESA VBE DDC supported (II) ATI(0): VESA VBE DDC Level none (II) ATI(0): VESA VBE DDC transfer in appr. 2 sec. (II) ATI(0): VESA VBE DDC read failed (II) ATI(0): BIOS Data: BIOSSize=0x10000, ROMTable=0x010C. (II) ATI(0): BIOS Data: ClockTable=0x0A8C, FrequencyTable=0x0A66. (II) ATI(0): BIOS Data: LCDTable=0x0180, LCDPanelInfo=0xEA7E. (II) ATI(0): BIOS Data: VideoTable=0x0000, HardwareTable=0x015C. (II) ATI(0): BIOS Data: I2CType=0x0F, Tuner=0x00, Decoder=0x00, Audio=0x0F. (--) ATI(0): ATI 3D Rage Mobility graphics controller detected. (--) ATI(0): Chip type 4C4D "LM", version 4, foundry TSMC, class 0, revision 0x01. (--) ATI(0): AGP bus interface detected; block I/O base is 0x2000. (--) ATI(0): ATI Mach64 adapter detected. (!!) ATI(0): For information on using the multimedia capabilities of this adapter, please see http://gatos.sf.net. (--) ATI(0): Internal RAMDAC (subtype 1) detected. (==) ATI(0): RGB weight 888 (==) ATI(0): Default visual is TrueColor (==) ATI(0): Using gamma correction (1.0, 1.0, 1.0) (II) ATI(0): Using Mach64 accelerator CRTC. (--) ATI(0): 1024x768 panel (ID 10) detected. (--) ATI(0): Panel model Hitachi TX36D81VC1CAB. (--) ATI(0): Panel clock is 65.146 MHz. (II) ATI(0): Using digital flat panel interface. (II) ATI(0): Storing hardware cursor image at 0x407FFC00. (II) ATI(0): Using 8 MB linear aperture at 0x40000000. (!!) ATI(0): Virtual resolutions will be limited to 8191 kB due to linear aperture size and/or placement of hardware cursor image area. (II) ATI(0): Using Block 0 MMIO aperture at 0x41000400. (II) ATI(0): Using Block 1 MMIO aperture at 0x41000000. (==) ATI(0): Write-combining range (0x40000000,0x800000) (II) ATI(0): MMIO write caching enabled. (--) ATI(0): 8192 kB of SDRAM (1:1) detected (using 8191 kB). (WW) ATI(0): Cannot shadow an accelerated frame buffer. (II) ATI(0): Engine XCLK 124.453 MHz; Refresh rate code 12. (--) ATI(0): Internal programmable clock generator detected. (--) ATI(0): Reference clock 29.500 MHz. (WW) ATI(0): Extraneous XF86Config HorizSync specification(s) ignored. (WW) ATI(0): Extraneous XF86Config VertRefresh specification(s) ignored. (II) ATI(0): Maximum clock: 230.00 MHz (II) ATI(0): Not using default mode "1152x864" (exceeds panel dimensions) (II) ATI(0): Not using default mode "576x432" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x960" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x480" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x960" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x480" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1280x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "640x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1200" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x600" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) ATI(0): Not using default mode "896x672" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) ATI(0): Not using default mode "896x672" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) ATI(0): Not using default mode "928x696" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) ATI(0): Not using default mode "928x696" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) ATI(0): Not using default mode "960x720" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) ATI(0): Not using default mode "960x720" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1152x768" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1400x1050" (exceeds panel dimensions) (II) ATI(0): Not using default mode "700x525" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1400x1050" (exceeds panel dimensions) (II) ATI(0): Not using default mode "700x525" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1600x1024" (exceeds panel dimensions) (II) ATI(0): Not using default mode "800x512" (exceeds panel dimensions) (II) ATI(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) ATI(0): Not using default mode "960x720" (exceeds panel dimensions) (II) ATI(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) ATI(0): Not using default mode "1024x768" (exceeds panel dimensions) (II) ATI(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) ATI(0): Not using default mode "1024x768" (exceeds panel dimensions) (II) ATI(0): Not using default mode "2048x1536" (insufficient memory for mode) (II) ATI(0): Not using default mode "1024x768" (exceeds panel dimensions) (--) ATI(0): Virtual size is 1024x768 (pitch 1024) (**) ATI(0): *Default mode "1024x768": 94.5 MHz, 68.7 kHz, 85.0 Hz (II) ATI(0): Modeline "1024x768" 94.50 1024 1072 1168 1376 768 769 772 808 +hsync +vsync (**) ATI(0): Default mode "1024x768": 78.8 MHz, 60.1 kHz, 75.1 Hz (II) ATI(0): Modeline "1024x768" 78.80 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (**) ATI(0): Default mode "1024x768": 75.0 MHz, 56.5 kHz, 70.1 Hz (II) ATI(0): Modeline "1024x768" 75.00 1024 1048 1184 1328 768 771 777 806 -hsync -vsync (**) ATI(0): Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz (II) ATI(0): Modeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (**) ATI(0): Default mode "1024x768": 44.9 MHz, 35.5 kHz, 87.1 Hz (I) (II) ATI(0): Modeline "1024x768" 44.90 1024 1032 1208 1264 768 768 776 817 interlace +hsync +vsync (**) ATI(0): Built-in mode "Native panel mode": 65.1 MHz, 62.6 kHz, 81.4 Hz (II) ATI(0): Modeline "Native panel mode" 65.15 1024 1024 1032 1040 768 768 769 770 (**) ATI(0): Default mode "832x624": 57.3 MHz, 49.7 kHz, 74.6 Hz (II) ATI(0): Modeline "832x624" 57.28 832 864 928 1152 624 625 628 667 -hsync -vsync (**) ATI(0): Default mode "800x600": 56.3 MHz, 53.7 kHz, 85.1 Hz (II) ATI(0): Modeline "800x600" 56.30 800 832 896 1048 600 601 604 631 +hsync +vsync (**) ATI(0): Default mode "800x600": 49.5 MHz, 46.9 kHz, 75.0 Hz (II) ATI(0): Modeline "800x600" 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (**) ATI(0): Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) ATI(0): Modeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (**) ATI(0): Default mode "800x600": 40.0 MHz, 37.9 kHz, 60.3 Hz (II) ATI(0): Modeline "800x600" 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (**) ATI(0): Default mode "800x600": 36.0 MHz, 35.2 kHz, 56.2 Hz (II) ATI(0): Modeline "800x600" 36.00 800 824 896 1024 600 601 603 625 +hsync +vsync (**) ATI(0): Default mode "640x480": 36.0 MHz, 43.3 kHz, 85.0 Hz (II) ATI(0): Modeline "640x480" 36.00 640 696 752 832 480 481 484 509 -hsync -vsync (**) ATI(0): Default mode "640x480": 31.5 MHz, 37.5 kHz, 75.0 Hz (II) ATI(0): Modeline "640x480" 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (**) ATI(0): Default mode "640x480": 31.5 MHz, 37.9 kHz, 72.8 Hz (II) ATI(0): Modeline "640x480" 31.50 640 664 704 832 480 489 491 520 -hsync -vsync (**) ATI(0): Default mode "640x480": 25.2 MHz, 31.5 kHz, 60.0 Hz (II) ATI(0): Modeline "640x480" 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (**) ATI(0): Default mode "720x400": 35.5 MHz, 37.9 kHz, 85.0 Hz (II) ATI(0): Modeline "720x400" 35.50 720 756 828 936 400 401 404 446 -hsync +vsync (**) ATI(0): Default mode "640x400": 31.5 MHz, 37.9 kHz, 85.1 Hz (II) ATI(0): Modeline "640x400" 31.50 640 672 736 832 400 401 404 445 -hsync +vsync (**) ATI(0): Default mode "640x350": 31.5 MHz, 37.9 kHz, 85.1 Hz (II) ATI(0): Modeline "640x350" 31.50 640 672 736 832 350 382 385 445 +hsync -vsync (**) ATI(0): Default mode "576x384": 32.5 MHz, 44.2 kHz, 54.8 Hz (D) (II) ATI(0): Modeline "576x384" 32.50 576 589 657 736 384 385 388 403 doublescan +hsync +vsync (**) ATI(0): Default mode "512x384": 47.2 MHz, 68.7 kHz, 85.0 Hz (D) (II) ATI(0): Modeline "512x384" 47.25 512 536 584 688 384 384 386 404 doublescan +hsync +vsync (**) ATI(0): Default mode "512x384": 39.4 MHz, 60.1 kHz, 75.1 Hz (D) (II) ATI(0): Modeline "512x384" 39.40 512 520 568 656 384 384 386 400 doublescan +hsync +vsync (**) ATI(0): Default mode "512x384": 37.5 MHz, 56.5 kHz, 70.1 Hz (D) (II) ATI(0): Modeline "512x384" 37.50 512 524 592 664 384 385 388 403 doublescan -hsync -vsync (**) ATI(0): Default mode "512x384": 32.5 MHz, 48.4 kHz, 60.0 Hz (D) (II) ATI(0): Modeline "512x384" 32.50 512 524 592 672 384 385 388 403 doublescan -hsync -vsync (**) ATI(0): Default mode "512x384": 22.4 MHz, 35.5 kHz, 87.1 Hz (D) (II) ATI(0): Modeline "512x384" 22.45 512 516 604 632 384 384 388 409 interlace doublescan +hsync +vsync (**) ATI(0): Default mode "416x312": 28.6 MHz, 49.7 kHz, 74.7 Hz (D) (II) ATI(0): Modeline "416x312" 28.64 416 432 464 576 312 312 314 333 doublescan -hsync -vsync (**) ATI(0): Default mode "400x300": 28.1 MHz, 53.7 kHz, 85.3 Hz (D) (II) ATI(0): Modeline "400x300" 28.15 400 416 448 524 300 300 302 315 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 24.8 MHz, 46.9 kHz, 75.1 Hz (D) (II) ATI(0): Modeline "400x300" 24.75 400 408 448 528 300 300 302 312 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 25.0 MHz, 48.1 kHz, 72.2 Hz (D) (II) ATI(0): Modeline "400x300" 25.00 400 428 488 520 300 318 321 333 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 20.0 MHz, 37.9 kHz, 60.3 Hz (D) (II) ATI(0): Modeline "400x300" 20.00 400 420 484 528 300 300 302 314 doublescan +hsync +vsync (**) ATI(0): Default mode "400x300": 18.0 MHz, 35.2 kHz, 56.3 Hz (D) (II) ATI(0): Modeline "400x300" 18.00 400 412 448 512 300 300 301 312 doublescan +hsync +vsync (**) ATI(0): Default mode "320x240": 18.0 MHz, 43.3 kHz, 85.2 Hz (D) (II) ATI(0): Modeline "320x240" 18.00 320 348 376 416 240 240 242 254 doublescan -hsync -vsync (**) ATI(0): Default mode "320x240": 15.8 MHz, 37.5 kHz, 75.0 Hz (D) (II) ATI(0): Modeline "320x240" 15.75 320 328 360 420 240 240 242 250 doublescan -hsync -vsync (**) ATI(0): Default mode "320x240": 15.8 MHz, 37.9 kHz, 72.8 Hz (D) (II) ATI(0): Modeline "320x240" 15.75 320 332 352 416 240 244 245 260 doublescan -hsync -vsync (**) ATI(0): Default mode "320x240": 12.6 MHz, 31.5 kHz, 60.1 Hz (D) (II) ATI(0): Modeline "320x240" 12.60 320 328 376 400 240 245 246 262 doublescan -hsync -vsync (**) ATI(0): Default mode "360x200": 17.8 MHz, 37.9 kHz, 85.0 Hz (D) (II) ATI(0): Modeline "360x200" 17.75 360 378 414 468 200 200 202 223 doublescan -hsync +vsync (**) ATI(0): Default mode "320x200": 15.8 MHz, 37.9 kHz, 85.3 Hz (D) (II) ATI(0): Modeline "320x200" 15.75 320 336 368 416 200 200 202 222 doublescan -hsync +vsync (**) ATI(0): Default mode "320x175": 15.8 MHz, 37.9 kHz, 85.3 Hz (D) (II) ATI(0): Modeline "320x175" 15.75 320 336 368 416 175 191 192 222 doublescan +hsync -vsync (==) ATI(0): DPI set to (75, 75) (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.2.0 ABI class: XFree86 Video Driver, version 0.6 (II) ATI(0): I2C bus "Mach64" initialized. (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0x41000000 - 0x41000fff (0x1000) MS[B] [1] 0 0 0x40000000 - 0x40ffffff (0x1000000) MS[B] [2] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [3] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [4] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [5] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [6] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [7] -1 0 0x41300000 - 0x41300fff (0x1000) MX[B] [8] -1 0 0x41200000 - 0x4121ffff (0x20000) MX[B] [9] -1 0 0x41280000 - 0x41280fff (0x1000) MX[B] [10] -1 0 0x50000000 - 0x4fffffff (0x0) MX[B]O [11] -1 0 0x41000000 - 0x41000fff (0x1000) MX[B](B) [12] -1 0 0x40000000 - 0x40ffffff (0x1000000) MX[B](B) [13] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) [14] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) [15] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) [16] 0 0 0x00002000 - 0x000020ff (0x100) IS[B] [17] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [18] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [19] -1 0 0x00003430 - 0x00003437 (0x8) IX[B] [20] -1 0 0x00003440 - 0x0000347f (0x40) IX[B] [21] -1 0 0x00003000 - 0x000030ff (0x100) IX[B] [22] -1 0 0x00003400 - 0x0000341f (0x20) IX[B] [23] -1 0 0x00003420 - 0x0000342f (0x10) IX[B] [24] -1 0 0x00002000 - 0x000020ff (0x100) IX[B](B) [25] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [26] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (==) ATI(0): Write-combining range (0x40000000,0x800000) (II) ATI(0): Largest offscreen areas (with overlaps): (II) ATI(0): 1024 x 1279 rectangle at 0,768 (II) ATI(0): 768 x 1280 rectangle at 0,768 (II) ATI(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Indirect CPU to Screen color expansion Solid Lines Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 10 256x256 slots (==) ATI(0): Backing store disabled (==) ATI(0): Silken mouse enabled (**) Option "dpms" (**) ATI(0): DPMS enabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (**) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Configured Mouse: ZAxisMapping: buttons 4 and 5 (**) Configured Mouse: Buttons: 5 (**) Option "Protocol" "ImPS/2" (**) Generic Mouse: Protocol: "ImPS/2" (**) Option "SendCoreEvents" "true" (**) Generic Mouse: always reports core events (**) Option "Device" "/dev/input/mice" (**) Generic Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Generic Mouse: ZAxisMapping: buttons 4 and 5 (**) Generic Mouse: Buttons: 5 (II) XINPUT: Adding extended input device "Generic Mouse" (type: MOUSE) (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) Configured Mouse: ps2EnableDataReporting: succeeded (II) Generic Mouse: ps2EnableDataReporting: succeeded Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! SetClientVersion: 0 8 SetClientVersion: 0 8 SetGrabKeysState - disabled SetGrabKeysState - enabled SetClientVersion: 0 8 SetGrabKeysState - disabled (II) 3rd Button detected: disabling emulate3Button (II) 3rd Button detected: disabling emulate3Button SetGrabKeysState - enabled SetClientVersion: 0 8 SetGrabKeysState - disabled SetGrabKeysState - enabled SetClientVersion: 0 8 SetGrabKeysState - disabled SetGrabKeysState - enabled SetClientVersion: 0 8 SetGrabKeysState - disabled SetGrabKeysState - enabled xresprobe-0.4.24ubuntu9/tests/ddcprobe-1024x768-dave0000644000000000000000000000050510214367723016646 0ustar oem: ATY Rage128 memory: 8192kb edid: 1 3 id: 199c eisa: APP199c serial: 00000000 manufacture: 0 2001 input: digital signal. screensize: 24 18 gamma: 2.600000 dpms: non-RGB, no active off, suspend, no standby timing0: 256250000 1024 320 768 38 24 136 3 6 245x 184 monitorid: LP121X1 monitorid: LP121X1 monitorname: COLOR LCD xresprobe-0.4.24ubuntu9/tests/log-i810-no24bpp0000644000000000000000000012175010220410053015634 0ustar This is a pre-release version of the The X.Org Foundation X11. It is not supported in any way. Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/. Select the "xorg" product for bugs you find in this release. Before reporting bugs in pre-release versions please check the latest version in the The X.Org Foundation "monolithic tree" CVS repository hosted at http://www.freedesktop.org/Software/xorg/ X Window System Version 6.8.1.902 (6.8.2 RC 2) (Ubuntu 6.8.1-1ubuntu16 20050209180945 root@rockhopper.warthogs.hbd.com) Release Date: 12 January 2005 X Protocol Version 11, Revision 0, Release 6.8.1.902 Build Operating System: Linux 2.6.8.1 i686 [ELF] Current Operating System: Linux ubuntu 2.6.10-3-386 #1 Tue Feb 15 21:18:07 UTC 2005 i686 Build Date: 09 February 2005 Before reporting problems, check http://wiki.X.Org to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.10-3-386 (buildd@mcmurdo) (gcc version 3.3.5 (Debian 1:3.3.5-8ubuntu2)) #1 Tue Feb 15 21:18:07 UTC 2005 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/Xorg.0.log", Time: Thu Feb 17 10:10:48 2005 (==) Using config file: "/etc/X11/xorg.conf" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "DELL 1703FP" (**) | |-->Device "Intel Corporation 82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xorg" (**) XKB: rules: "xorg" (**) Option "XkbModel" "pc104" (**) XKB: model: "pc104" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (WW) `fonts.dir' not found (or not valid) in "/var/lib/defoma/x-ttcidfont-conf.d/dirs/CID". Entry deleted from font path. (Run 'mkfontdir' on "/var/lib/defoma/x-ttcidfont-conf.d/dirs/CID"). (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi,/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: X.Org ANSI C Emulation: 0.2 X.Org Video Driver: 0.7 X.Org XInput driver : 0.4 X.Org Server Extension : 0.2 X.Org Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (++) using VT number 7 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,2560 card 1028,0126 rev 01 class 06,00,00 hdr 00 (II) PCI: 00:02:0: chip 8086,2562 card 1028,0126 rev 01 class 03,00,00 hdr 00 (II) PCI: 00:1d:0: chip 8086,24c2 card 1028,0126 rev 01 class 0c,03,00 hdr 80 (II) PCI: 00:1d:1: chip 8086,24c4 card 1028,0126 rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:1d:2: chip 8086,24c7 card 1028,0126 rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:1d:7: chip 8086,24cd card 1028,0126 rev 01 class 0c,03,20 hdr 00 (II) PCI: 00:1e:0: chip 8086,244e card 0000,0000 rev 81 class 06,04,00 hdr 01 (II) PCI: 00:1f:0: chip 8086,24c0 card 0000,0000 rev 01 class 06,01,00 hdr 80 (II) PCI: 00:1f:1: chip 8086,24cb card 1028,0126 rev 01 class 01,01,8a hdr 00 (II) PCI: 00:1f:3: chip 8086,24c3 card 1028,0126 rev 01 class 0c,05,00 hdr 00 (II) PCI: 00:1f:5: chip 8086,24c5 card 1028,0126 rev 01 class 04,01,00 hdr 00 (II) PCI: 01:0c:0: chip 8086,100e card 1028,002e rev 02 class 02,00,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (0,0,1), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-PCI bridge: (II) Bus 1: bridge is at (0:30:0), (0,1,1), BCTRL: 0x0006 (VGA_EN is cleared) (II) Bus 1 I/O range: [0] -1 0 0x0000e000 - 0x0000e0ff (0x100) IX[B] [1] -1 0 0x0000e400 - 0x0000e4ff (0x100) IX[B] [2] -1 0 0x0000e800 - 0x0000e8ff (0x100) IX[B] [3] -1 0 0x0000ec00 - 0x0000ecff (0x100) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0xff800000 - 0xff9fffff (0x200000) MX[B] (II) PCI-to-ISA bridge: (II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set) (--) PCI:*(0:2:0) Intel Corp. 82845G/GL [Brookdale-G] Chipset Integrated Graphics Device rev 1, Mem @ 0xe8000000/27, 0xff680000/19 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) PCI Memory resource overlap reduced 0xf0000000 from 0xf7ffffff to 0xefffffff (II) Active PCI resource ranges: [0] -1 0 0xff8e0000 - 0xff8fffff (0x20000) MX[B] [1] -1 0 0xffa00000 - 0xffa000ff (0x100) MX[B] [2] -1 0 0xffa00400 - 0xffa005ff (0x200) MX[B] [3] -1 0 0x3ff00000 - 0x3ff003ff (0x400) MX[B] [4] -1 0 0xffa00800 - 0xffa00bff (0x400) MX[B] [5] -1 0 0xf0000000 - 0xefffffff (0x0) MX[B]O [6] -1 0 0xff680000 - 0xff6fffff (0x80000) MX[B](B) [7] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [8] -1 0 0x0000ecc0 - 0x0000ecff (0x40) IX[B] [9] -1 0 0x0000dc40 - 0x0000dc7f (0x40) IX[B] [10] -1 0 0x0000d800 - 0x0000d8ff (0x100) IX[B] [11] -1 0 0x0000dc80 - 0x0000dc9f (0x20) IX[B] [12] -1 0 0x0000ffa0 - 0x0000ffaf (0x10) IX[B] [13] -1 0 0x0000ff40 - 0x0000ff5f (0x20) IX[B] [14] -1 0 0x0000ff60 - 0x0000ff7f (0x20) IX[B] [15] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xff8e0000 - 0xff8fffff (0x20000) MX[B] [1] -1 0 0xffa00000 - 0xffa000ff (0x100) MX[B] [2] -1 0 0xffa00400 - 0xffa005ff (0x200) MX[B] [3] -1 0 0x3ff00000 - 0x3ff003ff (0x400) MX[B] [4] -1 0 0xffa00800 - 0xffa00bff (0x400) MX[B] [5] -1 0 0xf0000000 - 0xefffffff (0x0) MX[B]O [6] -1 0 0xff680000 - 0xff6fffff (0x80000) MX[B](B) [7] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [8] -1 0 0x0000ecc0 - 0x0000ecff (0x40) IX[B] [9] -1 0 0x0000dc40 - 0x0000dc7f (0x40) IX[B] [10] -1 0 0x0000d800 - 0x0000d8ff (0x100) IX[B] [11] -1 0 0x0000dc80 - 0x0000dc9f (0x20) IX[B] [12] -1 0 0x0000ffa0 - 0x0000ffaf (0x10) IX[B] [13] -1 0 0x0000ff40 - 0x0000ff5f (0x20) IX[B] [14] -1 0 0x0000ff60 - 0x0000ff7f (0x20) IX[B] [15] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fefffff (0x3fe00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fefffff (0x3fe00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xff8e0000 - 0xff8fffff (0x20000) MX[B] [6] -1 0 0xffa00000 - 0xffa000ff (0x100) MX[B] [7] -1 0 0xffa00400 - 0xffa005ff (0x200) MX[B] [8] -1 0 0x3ff00000 - 0x3ff003ff (0x400) MX[B] [9] -1 0 0xffa00800 - 0xffa00bff (0x400) MX[B] [10] -1 0 0xf0000000 - 0xefffffff (0x0) MX[B]O [11] -1 0 0xff680000 - 0xff6fffff (0x80000) MX[B](B) [12] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [13] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [14] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [15] -1 0 0x0000ecc0 - 0x0000ecff (0x40) IX[B] [16] -1 0 0x0000dc40 - 0x0000dc7f (0x40) IX[B] [17] -1 0 0x0000d800 - 0x0000d8ff (0x100) IX[B] [18] -1 0 0x0000dc80 - 0x0000dc9f (0x20) IX[B] [19] -1 0 0x0000ffa0 - 0x0000ffaf (0x10) IX[B] [20] -1 0 0x0000ff40 - 0x0000ff5f (0x20) IX[B] [21] -1 0 0x0000ff60 - 0x0000ff7f (0x20) IX[B] [22] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="X.Org Foundation & the After X-TT Project" compiled for 6.8.1.902, module version = 2.1.0 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found (II) Module GLcore: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.13.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.2 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.1.0 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "i810" (II) Loading /usr/X11R6/lib/modules/drivers/i810_drv.o (II) Module i810: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.3.0 Module class: X.Org Video Driver ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "keyboard" (II) Loading /usr/X11R6/lib/modules/input/keyboard_drv.o (II) Module keyboard: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 Module class: X.Org XInput Driver ABI class: X.Org XInput driver, version 0.4 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 1.0.0 Module class: X.Org XInput Driver ABI class: X.Org XInput driver, version 0.4 (II) I810: Driver for Intel Integrated Graphics Chipsets: i810, i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G, 915GM (II) Primary Device is: PCI 00:02:0 (--) Chipset 845G found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fefffff (0x3fe00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xff8e0000 - 0xff8fffff (0x20000) MX[B] [6] -1 0 0xffa00000 - 0xffa000ff (0x100) MX[B] [7] -1 0 0xffa00400 - 0xffa005ff (0x200) MX[B] [8] -1 0 0x3ff00000 - 0x3ff003ff (0x400) MX[B] [9] -1 0 0xffa00800 - 0xffa00bff (0x400) MX[B] [10] -1 0 0xf0000000 - 0xefffffff (0x0) MX[B]O [11] -1 0 0xff680000 - 0xff6fffff (0x80000) MX[B](B) [12] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [13] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [14] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [15] -1 0 0x0000ecc0 - 0x0000ecff (0x40) IX[B] [16] -1 0 0x0000dc40 - 0x0000dc7f (0x40) IX[B] [17] -1 0 0x0000d800 - 0x0000d8ff (0x100) IX[B] [18] -1 0 0x0000dc80 - 0x0000dc9f (0x20) IX[B] [19] -1 0 0x0000ffa0 - 0x0000ffaf (0x10) IX[B] [20] -1 0 0x0000ff40 - 0x0000ff5f (0x20) IX[B] [21] -1 0 0x0000ff60 - 0x0000ff7f (0x20) IX[B] [22] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fefffff (0x3fe00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xff8e0000 - 0xff8fffff (0x20000) MX[B] [6] -1 0 0xffa00000 - 0xffa000ff (0x100) MX[B] [7] -1 0 0xffa00400 - 0xffa005ff (0x200) MX[B] [8] -1 0 0x3ff00000 - 0x3ff003ff (0x400) MX[B] [9] -1 0 0xffa00800 - 0xffa00bff (0x400) MX[B] [10] -1 0 0xf0000000 - 0xefffffff (0x0) MX[B]O [11] -1 0 0xff680000 - 0xff6fffff (0x80000) MX[B](B) [12] -1 0 0xe8000000 - 0xefffffff (0x8000000) MX[B](B) [13] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [14] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [15] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [17] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [18] -1 0 0x0000ecc0 - 0x0000ecff (0x40) IX[B] [19] -1 0 0x0000dc40 - 0x0000dc7f (0x40) IX[B] [20] -1 0 0x0000d800 - 0x0000d8ff (0x100) IX[B] [21] -1 0 0x0000dc80 - 0x0000dc9f (0x20) IX[B] [22] -1 0 0x0000ffa0 - 0x0000ffaf (0x10) IX[B] [23] -1 0 0x0000ff40 - 0x0000ff5f (0x20) IX[B] [24] -1 0 0x0000ff60 - 0x0000ff7f (0x20) IX[B] [25] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] [26] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [27] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Reloading /usr/X11R6/lib/modules/libvbe.a (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="X.Org Foundation" compiled for 6.8.1.902, module version = 0.1.0 ABI class: X.Org Video Driver, version 0.7 (**) I810(0): Depth 24, (--) framebuffer bpp 32 (==) I810(0): RGB weight 888 (==) I810(0): Default visual is TrueColor (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) I810(0): initializing int10 (WW) I810(0): Bad V_BIOS checksum (II) I810(0): Primary V_BIOS segment is: 0xc000 (II) I810(0): VESA BIOS detected (II) I810(0): VESA VBE Version 3.0 (II) I810(0): VESA VBE Total Mem: 832 kB (II) I810(0): VESA VBE OEM: Brookdale-G Graphics Chip Accelerated VGA BIOS (II) I810(0): VESA VBE OEM Software Rev: 1.0 (II) I810(0): VESA VBE OEM Vendor: Intel Corporation (II) I810(0): VESA VBE OEM Product: Brookdale-G Graphics Controller (II) I810(0): VESA VBE OEM Product Rev: Hardware Version 0.0 (II) I810(0): Integrated Graphics Chipset: Intel(R) 845G (--) I810(0): Chipset: "845G" (--) I810(0): Linear framebuffer at 0xE8000000 (--) I810(0): IO registers at addr 0xFF680000 (II) I810(0): 1 display pipe available. (II) I810(0): detected 892 kB stolen memory. (II) I810(0): I830CheckAvailableMemory: 835580 kB available (II) I810(0): Will attempt to tell the BIOS that there is 12288 kB VideoRAM (WW) I810(0): Extended BIOS function 0x5f11 not supported. (II) I810(0): Before: SWF1 is 0x00000001 (II) I810(0): After: SWF1 is 0x00000008 (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) I810(0): initializing int10 (WW) I810(0): Bad V_BIOS checksum (II) I810(0): Primary V_BIOS segment is: 0xc000 (II) I810(0): VESA BIOS detected (II) I810(0): VESA VBE Version 3.0 (II) I810(0): VESA VBE Total Mem: 832 kB (II) I810(0): VESA VBE OEM: Brookdale-G Graphics Chip Accelerated VGA BIOS (II) I810(0): VESA VBE OEM Software Rev: 1.0 (II) I810(0): VESA VBE OEM Vendor: Intel Corporation (II) I810(0): VESA VBE OEM Product: Brookdale-G Graphics Controller (II) I810(0): VESA VBE OEM Product Rev: Hardware Version 0.0 (II) I810(0): BIOS now sees 832 kB VideoRAM (--) I810(0): Pre-allocated VideoRAM: 892 kByte (==) I810(0): VideoRAM: 32768 kByte (==) I810(0): video overlay key set to 0x101fe (**) I810(0): page flipping disabled (==) I810(0): Using gamma correction (1.0, 1.0, 1.0) (II) I810(0): BIOS Build: 2833 (==) I810(0): Device Presence: disabled. (==) I810(0): Display Info: enabled. (II) I810(0): Broken BIOSes cause the system to hang here. If you encounter this problem please add Option "DisplayInfo" "FALSE" to the Device section of your XF86Config file. (II) I810(0): Display Info: CRT: attached: FALSE, present: FALSE, size: (0,0) (II) I810(0): Display Info: TV: attached: FALSE, present: FALSE, size: (0,0) (II) I810(0): Display Info: DFP (digital flat panel): attached: FALSE, present: FALSE, size: (0,0) (II) I810(0): Display Info: LFP (local flat panel): attached: FALSE, present: FALSE, size: (0,0) (II) I810(0): Display Info: CRT2 (second CRT): attached: FALSE, present: FALSE, size: (0,0) (II) I810(0): Display Info: TV2 (second TV): attached: FALSE, present: FALSE, size: (0,0) (II) I810(0): Currently active displays on Pipe A: (II) I810(0): CRT (==) I810(0): Display is using Pipe A (--) I810(0): Maximum frambuffer space: 32600 kByte (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) I810(0): VESA VBE DDC supported (II) I810(0): VESA VBE DDC Level 2 (II) I810(0): VESA VBE DDC transfer in appr. 1 sec. (II) I810(0): VESA VBE DDC read successfully (II) I810(0): Manufacturer: DEL Model: 3010 Serial#: 1095645490 (II) I810(0): Year: 2004 Week: 41 (II) I810(0): EDID Version: 1.3 (II) I810(0): Analog Display Input, Input Voltage Level: 0.700/0.300 V (II) I810(0): Sync: Separate Composite SyncOnGreen (II) I810(0): Max H-Image Size [cm]: horiz.: 34 vert.: 27 (II) I810(0): Gamma: 2.20 (II) I810(0): DPMS capabilities: StandBy Suspend Off; RGB/Color Display (II) I810(0): Default color space is primary color space (II) I810(0): First detailed timing is preferred mode (II) I810(0): redX: 0.634 redY: 0.354 greenX: 0.304 greenY: 0.581 (II) I810(0): blueX: 0.143 blueY: 0.102 whiteX: 0.310 whiteY: 0.330 (II) I810(0): Supported VESA Video Modes: (II) I810(0): 720x400@70Hz (II) I810(0): 640x480@60Hz (II) I810(0): 640x480@75Hz (II) I810(0): 800x600@60Hz (II) I810(0): 800x600@75Hz (II) I810(0): 1024x768@60Hz (II) I810(0): 1024x768@75Hz (II) I810(0): 1280x1024@75Hz (II) I810(0): Manufacturer's mask: 0 (II) I810(0): Supported Future Video Modes: (II) I810(0): #0: hsize: 1152 vsize 864 refresh: 75 vid: 20337 (II) I810(0): #1: hsize: 1280 vsize 1024 refresh: 60 vid: 32897 (II) I810(0): Supported additional Video Mode: (II) I810(0): clock: 108.0 MHz Image Size: 338 x 270 mm (II) I810(0): h_active: 1280 h_sync: 1328 h_sync_end 1440 h_blank_end 1688 h_border: 0 (II) I810(0): v_active: 1024 v_sync: 1025 v_sync_end 1028 v_blanking: 1066 v_border: 0 (II) I810(0): Serial No: 4Y2794A6AN92 (II) I810(0): Monitor name: DELL 1703FP (II) I810(0): Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 80 kHz, PixClock max 140 MHz (II) I810(0): Will use BIOS call 0x5f05 to set refresh rates for CRTs. (--) I810(0): Maximum space available for video modes: 832 kByte Mode: 20 (132x25) ModeAttributes: 0xf WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 528 XResolution: 132 YResolution: 25 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 4 NumberOfBanks: 1 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 21 (132x43) ModeAttributes: 0xf WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 528 XResolution: 132 YResolution: 43 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 4 NumberOfBanks: 1 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 22 (132x50) ModeAttributes: 0xf WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 528 XResolution: 132 YResolution: 50 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 4 NumberOfBanks: 1 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 23 (132x60) ModeAttributes: 0xf WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 528 XResolution: 132 YResolution: 60 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 4 NumberOfBanks: 1 MemoryModel: 0 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0x0 LinBytesPerScanLine: 0 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 0 Mode: 30 (640x480) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 640 XResolution: 640 YResolution: 480 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 1 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 640 BnkNumberOfImagePages: 1 LinNumberOfImagePages: 1 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 32 (800x600) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 800 XResolution: 800 YResolution: 600 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 800 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 34 (1024x768) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 1024 XResolution: 1024 YResolution: 768 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 1024 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 38 (1280x1024) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 1280 XResolution: 1280 YResolution: 1024 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 1280 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 3a (1600x1200) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 1600 XResolution: 1600 YResolution: 1200 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 1600 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 3c (1920x1440) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 1920 XResolution: 1920 YResolution: 1440 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 8 NumberOfBanks: 1 MemoryModel: 4 BankSize: 0 NumberOfImages: 0 RedMaskSize: 0 RedFieldPosition: 0 GreenMaskSize: 0 GreenFieldPosition: 0 BlueMaskSize: 0 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 1920 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 0 LinRedFieldPosition: 0 LinGreenMaskSize: 0 LinGreenFieldPosition: 0 LinBlueMaskSize: 0 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 41 (640x480) ModeAttributes: 0x9b WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 1280 XResolution: 640 YResolution: 480 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 1280 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 43 (800x600) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 1600 XResolution: 800 YResolution: 600 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 1600 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 45 (1024x768) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 2048 XResolution: 1024 YResolution: 768 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 2048 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 49 (1280x1024) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 2560 XResolution: 1280 YResolution: 1024 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 2560 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 4b (1600x1200) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 3200 XResolution: 1600 YResolution: 1200 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 3200 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 4d (1920x1440) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 3840 XResolution: 1920 YResolution: 1440 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 16 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 5 RedFieldPosition: 11 GreenMaskSize: 6 GreenFieldPosition: 5 BlueMaskSize: 5 BlueFieldPosition: 0 RsvdMaskSize: 0 RsvdFieldPosition: 0 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 3840 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 5 LinRedFieldPosition: 11 LinGreenMaskSize: 6 LinGreenFieldPosition: 5 LinBlueMaskSize: 5 LinBlueFieldPosition: 0 LinRsvdMaskSize: 0 LinRsvdFieldPosition: 0 MaxPixelClock: 230000000 Mode: 50 (640x480) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 2560 XResolution: 640 YResolution: 480 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 2560 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 Mode: 52 (800x600) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 3200 XResolution: 800 YResolution: 600 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 3200 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 Mode: 54 (1024x768) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 4096 XResolution: 1024 YResolution: 768 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 4096 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 Mode: 58 (1280x1024) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 5120 XResolution: 1280 YResolution: 1024 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 5120 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 Mode: 5a (1600x1200) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 6400 XResolution: 1600 YResolution: 1200 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 6400 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 Mode: 5c (1920x1440) ModeAttributes: 0x9a WinAAttributes: 0x7 WinBAttributes: 0x0 WinGranularity: 64 WinSize: 64 WinASegment: 0xa000 WinBSegment: 0x0 WinFuncPtr: 0xc0005aef BytesPerScanline: 7680 XResolution: 1920 YResolution: 1440 XCharSize: 8 YCharSize: 16 NumberOfPlanes: 1 BitsPerPixel: 32 NumberOfBanks: 1 MemoryModel: 6 BankSize: 0 NumberOfImages: 0 RedMaskSize: 8 RedFieldPosition: 16 GreenMaskSize: 8 GreenFieldPosition: 8 BlueMaskSize: 8 BlueFieldPosition: 0 RsvdMaskSize: 8 RsvdFieldPosition: 24 DirectColorModeInfo: 0 PhysBasePtr: 0xe8000000 LinBytesPerScanLine: 7680 BnkNumberOfImagePages: 0 LinNumberOfImagePages: 0 LinRedMaskSize: 8 LinRedFieldPosition: 16 LinGreenMaskSize: 8 LinGreenFieldPosition: 8 LinBlueMaskSize: 8 LinBlueFieldPosition: 0 LinRsvdMaskSize: 8 LinRsvdFieldPosition: 24 MaxPixelClock: 230000000 (EE) I810(0): No Video BIOS modes for chosen depth. (II) UnloadModule: "i810" (II) UnloadModule: "ddc" (II) UnloadModule: "int10" (II) UnloadModule: "int10" (II) UnloadModule: "vgahw" (II) Unloading /usr/X11R6/lib/modules/libvgahw.a (II) UnloadModule: "vbe" (II) UnloadModule: "int10" (EE) Screen(s) found, but none have a usable configuration. Fatal server error: no screens found Please consult the The X.Org Foundation support at http://wiki.X.Org for help. Please also check the log file at "/var/log/Xorg.0.log" for additional information. xresprobe-0.4.24ubuntu9/tests/log-nv-1024x7680000644000000000000000000011004510214367723015352 0ustar This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs). XFree86 Version 4.3.0.1 (Ubuntu 4.3.0.dfsg.1-6ubuntu4 20040811120604 root@false) Release Date: 15 August 2003 X Protocol Version 11, Revision 0, Release 6.6 Build Operating System: Linux 2.6.7-power4 ppc [ELF] Build Date: 11 August 2004 Before reporting problems, check http://www.XFree86.Org/ to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.8.1 (root@debian) (gcc version 3.3.4 (Debian 1:3.3.4-5ubuntu1)) #1 Wed Aug 18 09:47:29 BST 2004 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Thu Aug 19 09:43:04 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Color LCD" (**) | |-->Device "Standardgrafikkarte" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "macintosh" (**) XKB: model: "macintosh" (**) Option "XkbLayout" "de" (**) XKB: layout: "de" (**) Option "XkbOptions" "ctrl:nocaps" (**) XKB: options: "ctrl:nocaps" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (--) using VT number 7 (II) Open APM successful (II) Module ABI versions: XFree86 ANSI C Emulation: 0.2 XFree86 Video Driver: 0.6 XFree86 XInput driver : 0.4 XFree86 Server Extension : 0.2 XFree86 Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:0b:0: chip 106b,0034 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 00:10:0: chip 10de,0329 card 10de,0010 rev a1 class 03,00,00 hdr 00 (II) PCI: 01:0b:0: chip 106b,0035 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 01:12:0: chip 14e4,4320 card 106b,004e rev 03 class 02,80,00 hdr 00 (II) PCI: 01:17:0: chip 106b,003e card 0000,0000 rev 00 class ff,00,00 hdr 00 (II) PCI: 01:18:0: chip 106b,003f card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:19:0: chip 106b,003f card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:1a:0: chip 106b,003f card 0000,0000 rev 00 class 0c,03,10 hdr 00 (II) PCI: 01:1b:0: chip 1033,0035 card 1033,0035 rev 43 class 0c,03,10 hdr 80 (II) PCI: 01:1b:1: chip 1033,0035 card 1033,0035 rev 43 class 0c,03,10 hdr 00 (II) PCI: 01:1b:2: chip 1033,00e0 card 1033,00e0 rev 04 class 0c,03,20 hdr 00 (II) PCI: 02:0b:0: chip 106b,0036 card 0000,0000 rev 00 class 06,00,00 hdr 00 (II) PCI: 02:0d:0: chip 106b,003b card 0000,0000 rev 00 class ff,00,00 hdr 00 (II) PCI: 02:0e:0: chip 106b,0031 card 106b,5811 rev 81 class 0c,00,10 hdr 00 (II) PCI: 02:0f:0: chip 106b,0032 card 0000,0000 rev 80 class 02,00,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:11:0), (0,0,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 1: bridge is at (1:11:0), (1,1,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Host-to-PCI bridge: (II) Bus 2: bridge is at (2:11:0), (2,2,2), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 2 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 2 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 2 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (--) PCI:*(0:16:0) nVidia Corporation GeForce FX 5200 (Mac) rev 161, Mem @ 0x91000000/24, 0xa0000000/27, BIOS @ 0x90000000/17 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) Active PCI resource ranges: [0] -1 0 0xf5200000 - 0xf53fffff (0x200000) MX[B] [1] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [2] -1 0 0x80080000 - 0x800800ff (0x100) MX[B] [3] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [4] -1 0 0x80082000 - 0x80082fff (0x1000) MX[B] [5] -1 0 0x80083000 - 0x80083fff (0x1000) MX[B] [6] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [7] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [8] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [9] -1 0 0x90000000 - 0x9001ffff (0x20000) MX[B](B) [10] -1 0 0xa0000000 - 0xa7ffffff (0x8000000) MX[B](B) [11] -1 0 0x91000000 - 0x91ffffff (0x1000000) MX[B](B) (II) Inactive PCI resource ranges: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0x80084000 - 0x80085fff (0x2000) MX[B] (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xf5200000 - 0xf53fffff (0x200000) MX[B] [1] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [2] -1 0 0x80080000 - 0x800800ff (0x100) MX[B] [3] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [4] -1 0 0x80082000 - 0x80082fff (0x1000) MX[B] [5] -1 0 0x80083000 - 0x80083fff (0x1000) MX[B] [6] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [7] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [8] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [9] -1 0 0x90000000 - 0x9001ffff (0x20000) MX[B](B) [10] -1 0 0xa0000000 - 0xa7ffffff (0x8000000) MX[B](B) [11] -1 0 0x91000000 - 0x91ffffff (0x1000000) MX[B](B) (II) Inactive PCI resource ranges after removing overlaps: [0] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [1] -1 0 0x80084000 - 0x80085fff (0x2000) MX[B] (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) All system resource ranges: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5200000 - 0xf53fffff (0x200000) MX[B] [3] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [4] -1 0 0x80080000 - 0x800800ff (0x100) MX[B] [5] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [6] -1 0 0x80082000 - 0x80082fff (0x1000) MX[B] [7] -1 0 0x80083000 - 0x80083fff (0x1000) MX[B] [8] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [9] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [10] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [11] -1 0 0x90000000 - 0x9001ffff (0x20000) MX[B](B) [12] -1 0 0xa0000000 - 0xa7ffffff (0x8000000) MX[B](B) [13] -1 0 0x91000000 - 0x91ffffff (0x1000000) MX[B](B) [14] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [15] -1 0 0x80084000 - 0x80085fff (0x2000) MX[B] [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [17] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_vertex.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 2.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.2 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "nv" (II) Loading /usr/X11R6/lib/modules/drivers/nv_drv.o (II) Module nv: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.1 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.6 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.4 (II) NV: driver for NVIDIA chipsets: RIVA 128, RIVA TNT, RIVA TNT2, Unknown TNT2, Vanta, RIVA TNT2 Ultra, RIVA TNT2 Model 64, Aladdin TNT2, GeForce 256, GeForce DDR, Quadro, GeForce2 MX/MX 400, GeForce2 MX 100/200, GeForce2 Go, Quadro2 MXR/EX/Go, GeForce2 Integrated GPU, GeForce2 GTS, GeForce2 Ti, GeForce2 Ultra, Quadro2 Pro, GeForce4 MX 460, GeForce4 MX 440, GeForce4 MX 420, GeForce4 MX 440-SE, GeForce4 440 Go, GeForce4 420 Go, GeForce4 420 Go 32M, GeForce4 460 Go, GeForce4 440 Go 64M, GeForce4 410 Go 16M, Quadro4 500 GoGL, Quadro4 550 XGL, Quadro4 NVS, GeForce4 MX 440 with AGP8X, GeForce4 MX 440SE with AGP8X, GeForce4 MX 420 with AGP8X, GeForce4 448 Go, GeForce4 488 Go, Quadro4 580 XGL, Quadro4 280 NVS, Quadro4 380 XGL, GeForce4 MX Integrated GPU, GeForce3, GeForce3 Ti 200, GeForce3 Ti 500, Quadro DCC, GeForce4 Ti 4600, GeForce4 Ti 4400, 0x0252, GeForce4 Ti 4200, Quadro4 900 XGL, Quadro4 750 XGL, Quadro4 700 XGL, GeForce4 Ti 4800, GeForce4 Ti 4200 with AGP8X, GeForce4 Ti 4800 SE, GeForce4 4200 Go, Quadro4 700 GoGL, Quadro4 980 XGL, Quadro4 780 XGL, GeForce FX 5800 Ultra, GeForce FX 5800, Quadro FX 2000, Quadro FX 1000, GeForce FX 5600 Ultra, GeForce FX 5600, 0x0313, GeForce FX 5600SE, 0x0316, 0x0317, GeForce FX Go5600, GeForce FX Go5650, Quadro FX Go700, 0x031D, 0x031E, 0x031F, GeForce FX 5200 Ultra, GeForce FX 5200, 0x0323, GeForce FX Go5200, GeForce FX Go5250, 0x0323, 0x0328, 0x0329, 0x032A, Quadro FX 500, 0x032C, GeForce FX Go5100, 0x032F, GeForce FX 5900 Ultra, GeForce FX 5900, Quadro FX 3000 (II) Primary Device is: PCI 00:10:0 (--) Chipset 0x0329 found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5200000 - 0xf53fffff (0x200000) MX[B] [3] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [4] -1 0 0x80080000 - 0x800800ff (0x100) MX[B] [5] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [6] -1 0 0x80082000 - 0x80082fff (0x1000) MX[B] [7] -1 0 0x80083000 - 0x80083fff (0x1000) MX[B] [8] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [9] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [10] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [11] -1 0 0x90000000 - 0x9001ffff (0x20000) MX[B](B) [12] -1 0 0xa0000000 - 0xa7ffffff (0x8000000) MX[B](B) [13] -1 0 0x91000000 - 0x91ffffff (0x1000000) MX[B](B) [14] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [15] -1 0 0x80084000 - 0x80085fff (0x2000) MX[B] [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [17] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] (II) resource ranges after probing: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [2] -1 0 0xf5200000 - 0xf53fffff (0x200000) MX[B] [3] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [4] -1 0 0x80080000 - 0x800800ff (0x100) MX[B] [5] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [6] -1 0 0x80082000 - 0x80082fff (0x1000) MX[B] [7] -1 0 0x80083000 - 0x80083fff (0x1000) MX[B] [8] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [9] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [10] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [11] -1 0 0x90000000 - 0x9001ffff (0x20000) MX[B](B) [12] -1 0 0xa0000000 - 0xa7ffffff (0x8000000) MX[B](B) [13] -1 0 0x91000000 - 0x91ffffff (0x1000000) MX[B](B) [14] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [15] -1 0 0x80084000 - 0x80085fff (0x2000) MX[B] [16] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [17] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [18] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [19] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [20] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [21] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [22] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/libint10.a (--) NV(0): Chipset: "0x0329" (**) NV(0): Depth 24, (--) framebuffer bpp 32 (==) NV(0): RGB weight 888 (==) NV(0): Default visual is TrueColor (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (==) NV(0): Using HW cursor (--) NV(0): Linear framebuffer at 0xA0000000 (--) NV(0): MMIO registers at 0x91000000 (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.2.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) NV(0): I2C bus "DDC" initialized. (II) NV(0): Probing for analog device on output A... (--) NV(0): ...can't find one (II) NV(0): Probing for analog device on output B... (--) NV(0): ...can't find one (II) NV(0): Probing for EDID on I2C bus A... (II) NV(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) NV(0): I2C device "DDC:ddc2" removed. (II) NV(0): ... none found (II) NV(0): Probing for EDID on I2C bus B... (II) NV(0): I2C device "DDC:ddc2" registered at address 0xA0. (II) NV(0): I2C device "DDC:ddc2" removed. (II) NV(0): ... none found (--) NV(0): CRTC 1 is currently programmed for DFP (II) NV(0): Using DFP on CRTC 1 (--) NV(0): VideoRAM: 65536 kBytes (==) NV(0): Using gamma correction (1.0, 1.0, 1.0) (II) NV(0): Color LCD: Using hsync range of 35.00-60.00 kHz (II) NV(0): Color LCD: Using vrefresh range of 60.00-75.00 Hz (II) NV(0): Clock range: 12.00 to 350.00 MHz (II) NV(0): Not using default mode "640x350" (vrefresh out of range) (II) NV(0): Not using default mode "320x175" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "640x400" (vrefresh out of range) (II) NV(0): Not using default mode "320x200" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "720x400" (vrefresh out of range) (II) NV(0): Not using default mode "360x200" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "640x480" (hsync out of range) (II) NV(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "640x480" (vrefresh out of range) (II) NV(0): Not using default mode "320x240" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "800x600" (vrefresh out of range) (II) NV(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "800x600" (vrefresh out of range) (II) NV(0): Not using default mode "400x300" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1024x768" (hsync out of range) (II) NV(0): Not using default mode "512x384" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1152x864" (hsync out of range) (II) NV(0): Not using default mode "576x432" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1280x960" (hsync out of range) (II) NV(0): Not using default mode "640x480" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1280x1024" (hsync out of range) (II) NV(0): Not using default mode "640x512" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1280x1024" (hsync out of range) (II) NV(0): Not using default mode "640x512" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1280x1024" (hsync out of range) (II) NV(0): Not using default mode "640x512" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1600x1200" (hsync out of range) (II) NV(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1600x1200" (hsync out of range) (II) NV(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1600x1200" (hsync out of range) (II) NV(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1600x1200" (hsync out of range) (II) NV(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1600x1200" (hsync out of range) (II) NV(0): Not using default mode "800x600" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1792x1344" (hsync out of range) (II) NV(0): Not using default mode "896x672" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1792x1344" (hsync out of range) (II) NV(0): Not using default mode "896x672" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1856x1392" (hsync out of range) (II) NV(0): Not using default mode "928x696" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1856x1392" (hsync out of range) (II) NV(0): Not using default mode "928x696" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1920x1440" (hsync out of range) (II) NV(0): Not using default mode "960x720" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1920x1440" (hsync out of range) (II) NV(0): Not using default mode "960x720" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "416x312" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1152x768" (vrefresh out of range) (II) NV(0): Not using default mode "576x384" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1400x1050" (hsync out of range) (II) NV(0): Not using default mode "700x525" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1400x1050" (hsync out of range) (II) NV(0): Not using default mode "700x525" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1600x1024" (hsync out of range) (II) NV(0): Not using default mode "800x512" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1920x1440" (hsync out of range) (II) NV(0): Not using default mode "960x720" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "2048x1536" (hsync out of range) (II) NV(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "2048x1536" (hsync out of range) (II) NV(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "2048x1536" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) NV(0): Not using default mode "1280x960" (width too large for virtual size) (--) NV(0): Virtual size is 1024x768 (pitch 1024) (**) NV(0): *Default mode "1024x768": 78.8 MHz, 60.1 kHz, 75.1 Hz (II) NV(0): Modeline "1024x768" 78.80 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (**) NV(0): *Default mode "800x600": 49.5 MHz, 46.9 kHz, 75.0 Hz (II) NV(0): Modeline "800x600" 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (**) NV(0): *Default mode "640x480": 31.5 MHz, 37.5 kHz, 75.0 Hz (II) NV(0): Modeline "640x480" 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (**) NV(0): Default mode "1024x768": 75.0 MHz, 56.5 kHz, 70.1 Hz (II) NV(0): Modeline "1024x768" 75.00 1024 1048 1184 1328 768 771 777 806 -hsync -vsync (**) NV(0): Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz (II) NV(0): Modeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (**) NV(0): Default mode "832x624": 57.3 MHz, 49.7 kHz, 74.6 Hz (II) NV(0): Modeline "832x624" 57.28 832 864 928 1152 624 625 628 667 -hsync -vsync (**) NV(0): Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) NV(0): Modeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (**) NV(0): Default mode "800x600": 40.0 MHz, 37.9 kHz, 60.3 Hz (II) NV(0): Modeline "800x600" 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (**) NV(0): Default mode "640x480": 31.5 MHz, 37.9 kHz, 72.8 Hz (II) NV(0): Modeline "640x480" 31.50 640 664 704 832 480 489 491 520 -hsync -vsync (++) NV(0): DPI set to (100, 100) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.2 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 1.1.0 ABI class: XFree86 Video Driver, version 0.6 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.3.0.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.6 (--) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0xa0000000 - 0xa7ffffff (0x8000000) MX[B] [1] 0 0 0x91000000 - 0x91ffffff (0x1000000) MX[B] [2] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [3] -1 0 0x00000000 - 0x00000000 (0x1) MX[B] [4] -1 0 0xf5200000 - 0xf53fffff (0x200000) MX[B] [5] -1 0 0xf5004000 - 0xf5007fff (0x4000) MX[B] [6] -1 0 0x80080000 - 0x800800ff (0x100) MX[B] [7] -1 0 0x80081000 - 0x80081fff (0x1000) MX[B] [8] -1 0 0x80082000 - 0x80082fff (0x1000) MX[B] [9] -1 0 0x80083000 - 0x80083fff (0x1000) MX[B] [10] -1 0 0xf3001000 - 0xf3001fff (0x1000) MX[B] [11] -1 0 0xf3000000 - 0xf3000fff (0x1000) MX[B] [12] -1 0 0x80000000 - 0x8007ffff (0x80000) MX[B] [13] -1 0 0x90000000 - 0x9001ffff (0x20000) MX[B](B) [14] -1 0 0xa0000000 - 0xa7ffffff (0x8000000) MX[B](B) [15] -1 0 0x91000000 - 0x91ffffff (0x1000000) MX[B](B) [16] -1 0 0xf5000000 - 0xf5000fff (0x1000) MX[B] [17] -1 0 0x80084000 - 0x80085fff (0x2000) MX[B] [18] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprD) [19] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD) [20] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprD) [21] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [22] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [23] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [24] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (II) NV(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles Solid Lines Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 32 256x256 slots 16 512x512 slots (==) NV(0): Backing store disabled (==) NV(0): Silken mouse enabled (**) Option "dpms" (**) NV(0): DPMS enabled (==) RandR enabled (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (**) Option "Emulate3Buttons" "true" (**) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Configured Mouse: ZAxisMapping: buttons 4 and 5 (**) Configured Mouse: Buttons: 5 (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) Server_Terminate keybinding not found (II) Configured Mouse: ps2EnableDataReporting: succeeded Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - disabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - enabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - disabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - enabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - disabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - enabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - disabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - enabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - disabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - enabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - disabled GetModeLine - scrn: 0 clock: 78800 GetModeLine - hdsp: 1024 hbeg: 1040 hend: 1136 httl: 1312 vdsp: 768 vbeg: 769 vend: 772 vttl: 800 flags: 5 SetGrabKeysState - enabled xresprobe-0.4.24ubuntu9/tests/log-chips-800x6000000644000000000000000000004032610242533543015737 0ustar XFree86 Version 4.1.0 / X Window System (protocol Version 11, revision 0, vendor release 6510) Release Date: 2 June 2001 If the server is older than 6-12 months, or if your card is newer than the above date, look for a newer version before reporting problems. (See http://www.XFree86.Org/FAQ) Build Operating System: Linux 2.2.19 i686 [ELF] Module Loader present (==) Log file: "/var/log/XFree86.0.log", Time: Fri Jun 15 22:52:56 2001 (==) Using config file: "/etc/X11/XF86Config-4" Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) ServerLayout "XFree86 Configured" (**) |-->Screen "Screen0" (0) (**) | |-->Monitor "Monitor0" (**) | |-->Device "C&T 65555" (**) |-->Input Device "Mouse0" (**) |-->Input Device "Keyboard0" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "pc105" (**) XKB: model: "pc105" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (==) Keyboard: CustomKeycode disabled (WW) The directory "/usr/X11R6/lib/X11/fonts/local/" does not exist. Entry deleted from font path. (**) FontPath set to "/usr/X11R6/lib/X11/fonts/misc/,/usr/X11R6/lib/X11/fonts/75dpi/:unscaled,/usr/X11R6/lib/X11/fonts/100dpi/:unscaled,/usr/X11R6/lib/X11/fonts/Type1/,/usr/X11R6/lib/X11/fonts/Speedo/,/usr/X11R6/lib/X11/fonts/75dpi/,/usr/X11R6/lib/X11/fonts/100dpi/" (**) RgbPath set to "/usr/X11R6/lib/X11/rgb" (**) ModulePath set to "/usr/X11R6/lib/modules" (--) using VT number 7 (II) Open APM successful (II) Module ABI versions: XFree86 ANSI C Emulation: 0.1 XFree86 Video Driver: 0.4 XFree86 XInput driver : 0.2 XFree86 Server Extension : 0.1 XFree86 Font Renderer : 0.2 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.2 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.1.0, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.4 (II) PCI: Probing config type using method 1 (II) PCI: Config type is 1 (II) PCI: stages = 0x03, oldVal1 = 0x00000000, mode1Res1 = 0x80000000 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,7192 card 1179,0001 rev 02 class 06,00,00 hdr 00 (II) PCI: 00:02:0: chip 1179,060f card 1400,0000 rev 05 class 06,07,00 hdr 82 (II) PCI: 00:02:1: chip 1179,060f card 1c00,0000 rev 05 class 06,07,00 hdr 82 (II) PCI: 00:04:0: chip 102c,00e5 card 1179,0001 rev c6 class 03,00,00 hdr 00 (II) PCI: 00:07:0: chip 8086,7110 card 0000,0000 rev 02 class 06,80,00 hdr 80 (II) PCI: 00:07:1: chip 8086,7111 card 0000,0000 rev 01 class 01,01,80 hdr 00 (II) PCI: 00:07:2: chip 8086,7112 card 0000,0000 rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:07:3: chip 8086,7113 card 0000,0000 rev 02 class 06,80,00 hdr 00 (II) PCI: 00:0a:0: chip 1179,0701 card 1179,0001 rev 23 class 07,80,00 hdr 00 (II) PCI: End of PCI scan (II) LoadModule: "scanpci" (II) Loading /usr/X11R6/lib/modules/libscanpci.a (II) Module scanpci: vendor="The XFree86 Project" compiled for 4.1.0, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.4 (II) UnloadModule: "scanpci" (II) Unloading /usr/X11R6/lib/modules/libscanpci.a (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (-1,0,0), BCTRL: 0x08 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (--) PCI:*(0:4:0) C&T 65555 rev 198, Mem @ 0xfe000000/24 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) Active PCI resource ranges: [0] -1 0 0xe0000000 - 0xefffffff (0x10000000) MX[B] [1] -1 0 0xfe000000 - 0xfeffffff (0x1000000) MX[B](B) [2] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] [3] -1 0 0x0000ffe0 - 0x0000ffff (0x20) IX[B] [4] -1 0 0x00001000 - 0x0000100f (0x10) IX[B] (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0xe0000000 - 0xefffffff (0x10000000) MX[B] [1] -1 0 0xfe000000 - 0xfeffffff (0x1000000) MX[B](B) [2] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] [3] -1 0 0x0000ffe0 - 0x0000ffff (0x20) IX[B] [4] -1 0 0x00001000 - 0x0000100f (0x10) IX[B] (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xe0000000 - 0xefffffff (0x10000000) MX[B] [6] -1 0 0xfe000000 - 0xfeffffff (0x1000000) MX[B](B) [7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [8] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [9] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] [10] -1 0 0x0000ffe0 - 0x0000ffff (0x20) IX[B] [11] -1 0 0x00001000 - 0x0000100f (0x10) IX[B] (II) LoadModule: "chips" (II) Loading /usr/X11R6/lib/modules/drivers/chips_drv.o (II) Module chips: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.4 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.2 (II) CHIPS: Driver for Chips and Technologies chipsets: ct65520, ct65525, ct65530, ct65535, ct65540, ct65545, ct65546, ct65548, ct65550, ct65554, ct65555, ct68554, ct69000, ct69030, ct64200, ct64300 (II) Primary Device is: PCI 00:04:0 (--) Assigning device section with no busID to primary device (--) Chipset ct65555 found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xe0000000 - 0xefffffff (0x10000000) MX[B] [6] -1 0 0xfe000000 - 0xfeffffff (0x1000000) MX[B](B) [7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [8] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [9] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] [10] -1 0 0x0000ffe0 - 0x0000ffff (0x20) IX[B] [11] -1 0 0x00001000 - 0x0000100f (0x10) IX[B] (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0xe0000000 - 0xefffffff (0x10000000) MX[B] [6] -1 0 0xfe000000 - 0xfeffffff (0x1000000) MX[B](B) [7] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [8] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [9] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [10] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [11] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [12] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] [13] -1 0 0x0000ffe0 - 0x0000ffff (0x20) IX[B] [14] -1 0 0x00001000 - 0x0000100f (0x10) IX[B] [15] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [16] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.1.0, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.4 (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.4 (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.4 (II) CHIPS(0): initializing int10 (II) CHIPS(0): Primary V_BIOS segment is: 0xc000 (II) CHIPS(0): VESA BIOS detected (II) CHIPS(0): VESA VBE Version 2.0 (II) CHIPS(0): VESA VBE Total Mem: 2048 kB (II) CHIPS(0): VESA VBE OEM: CHIPS 6x555 Super VGA (II) CHIPS(0): VESA VBE OEM Software Rev: 1.0 (II) CHIPS(0): VESA VBE OEM Vendor: Chips & Technologies, Inc. (II) CHIPS(0): VESA VBE OEM Product: 6x555 Display Controller (II) CHIPS(0): VESA VBE OEM Product Rev: 2 (**) CHIPS(0): Depth 24, (--) framebuffer bpp 24 (==) CHIPS(0): RGB weight 888 (==) CHIPS(0): Default visual is TrueColor (==) CHIPS(0): Using gamma correction (1.0, 1.0, 1.0) (**) CHIPS(0): Option "STN" (**) CHIPS(0): Option "NoStretch" (**) CHIPS(0): Option "LcdCenter" (==) CHIPS(0): Using HW cursor (**) CHIPS(0): Enabling linear addressing (--) CHIPS(0): base address is set at 0xFE000000. (**) CHIPS(0): Using MMIO (--) CHIPS(0): VideoRAM: 2048 kByte (--) CHIPS(0): DD-STN probed (--) CHIPS(0): LCD (--) CHIPS(0): Display Size: x=800; y=600 (--) CHIPS(0): Frame Buffer used (--) CHIPS(0): Using embedded Frame Buffer, size 96000 bytes (--) CHIPS(0): Frame accelerator enabled (--) CHIPS(0): PCI Bus (--) CHIPS(0): Internal DAC disabled (--) CHIPS(0): Using programmable clocks (--) CHIPS(0): Dot clock 0: 25.172 MHz (--) CHIPS(0): Dot clock 1: 28.325 MHz (--) CHIPS(0): Dot clock 2: 40.090 MHz FPclk CRTclk (--) CHIPS(0): Probed memory clock of 50.113 MHz (==) CHIPS(0): Min pixel clock is 11.000 MHz (**) CHIPS(0): User max pixel clock of 110.000 MHz overrides 35.079 MHz limit (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.4 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) CHIPS(0): VESA VBE DDC supported (II) CHIPS(0): VESA VBE DDC Level 2 (II) CHIPS(0): VESA VBE DDC transfer in appr. 1 sec. (II) CHIPS(0): VESA VBE DDC read successfully (II) CHIPS(0): Manufacturer: TOS Model: 5081 Serial#: 0 (II) CHIPS(0): Year: 1995 Week: 20 (II) CHIPS(0): EDID Version: 1.0 (II) CHIPS(0): Digital Display Input (II) CHIPS(0): Max H-Image Size [cm]: horiz.: 23 vert.: 17 (II) CHIPS(0): Gamma: 1.00 (II) CHIPS(0): No DPMS capabilities specified; RGB/Color Display (II) CHIPS(0): redX: 0.000 redY: 0.000 greenX: 0.000 greenY: 0.000 (II) CHIPS(0): blueX: 0.000 blueY: 0.000 whiteX: 0.000 whiteY: 0.000 (II) CHIPS(0): Supported VESA Video Modes: (II) CHIPS(0): 640x480@60Hz (II) CHIPS(0): 800x600@60Hz (II) CHIPS(0): Manufacturer's mask: 0 (II) CHIPS(0): Monitor0: Using hsync range of 10.00-100.00 kHz (WW) CHIPS(0): Monitor0: using default vrefresh range of 43-72Hz (II) CHIPS(0): Clock range: 11.00 to 110.00 MHz (II) CHIPS(0): Not using default mode "640x350" (vrefresh out of range) (II) CHIPS(0): Not using default mode "640x400" (vrefresh out of range) (II) CHIPS(0): Not using default mode "720x400" (vrefresh out of range) (II) CHIPS(0): Not using default mode "640x480" (vrefresh out of range) (II) CHIPS(0): Not using default mode "640x480" (vrefresh out of range) (II) CHIPS(0): Not using default mode "640x480" (vrefresh out of range) (II) CHIPS(0): Not using default mode "800x600" (vrefresh out of range) (II) CHIPS(0): Not using default mode "800x600" (vrefresh out of range) (II) CHIPS(0): Not using default mode "1024x768" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1024x768" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1024x768" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1024x768" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1024x768" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1152x864" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1280x960" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1280x960" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1280x1024" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1280x1024" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1280x1024" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1600x1200" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1600x1200" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1600x1200" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1600x1200" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1600x1200" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1792x1344" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1856x1392" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1920x1440" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1400x1050" (insufficient memory for mode) (II) CHIPS(0): Not using default mode "1400x1050" (insufficient memory for mode) (--) CHIPS(0): Virtual size is 800x600 (pitch 800) (**) CHIPS(0): Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) CHIPS(0): Modeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (--) CHIPS(0): Display dimensions: (23, 17) cm (--) CHIPS(0): DPI set to (88, 89) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.1 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.1.0, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.4 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.1.0, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.4 (==) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0xfe000000 - 0xfeffffff (0x1000000) MS[B] [1] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [2] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [3] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [4] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [5] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [6] -1 0 0xe0000000 - 0xefffffff (0x10000000) MX[B] [7] -1 0 0xfe000000 - 0xfeffffff (0x1000000) MX[B](B) [8] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprD) [9] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD) [10] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprD) [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [13] -1 0 0x0000ff80 - 0x0000ff9f (0x20) IX[B] [14] -1 0 0x0000ffe0 - 0x0000ffff (0x20) IX[B] [15] -1 0 0x00001000 - 0x0000100f (0x10) IX[B] [16] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [17] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] xresprobe-0.4.24ubuntu9/tests/ddc-monitor-1600x1200-custom0000644000000000000000000000166510214367723017744 0ustar timing: 720x400@70 Hz (VGA 640x400, IBM) timing: 720x400@88 Hz (XGA2) timing: 640x480@60 Hz (VGA) timing: 640x480@67 Hz (Mac II, Apple) timing: 640x480@72 Hz (VESA) timing: 640x480@75 Hz (VESA) timing: 800x600@56 Hz (VESA) timing: 800x600@60 Hz (VESA) timing: 800x600@72 Hz (VESA) timing: 800x600@75 Hz (VESA) timing: 832x624@75 Hz (Mac II) timing: 1024x768@87 Hz Interlaced (8514A) timing: 1024x768@60 Hz (VESA) timing: 1024x768@70 Hz (VESA) timing: 1024x768@75 Hz (VESA) timing: 1280x1024@75 (VESA) ctiming: 2288x1430@123 ctiming: 2288x1430@123 ctiming: 2288x1430@123 ctiming: 2288x1430@123 ctiming: 2288x1430@123 ctiming: 2288x1430@123 ctiming: 2288x1430@123 ctiming: 2288x1430@123 timing0: 655350000 4095 4095 4095 4095 1023 1023 63 63 4095x 4095 timing1: 655350000 4095 4095 4095 4095 1023 1023 63 63 4095x 4095 timing2: 655350000 4095 4095 4095 4095 1023 1023 63 63 4095x 4095 timing3: 655350000 4095 4095 4095 4095 1023 1023 63 63 4095x 4095 xresprobe-0.4.24ubuntu9/tests/log-neomagic-1024x7680000644000000000000000000007751010214367723016522 0ustar Native res 1024x768 This is a pre-release version of XFree86, and is not supported in any way. Bugs may be reported to XFree86@XFree86.Org and patches submitted to fixes@XFree86.Org. Before reporting bugs in pre-release versions, please check the latest version in the XFree86 CVS repository (http://www.XFree86.Org/cvs) XFree86 Version 4.2.1.1 (Debian 4.2.1-12.1 20031003005825 james@nocrew.org) / X Window System (protocol Version 11, revision 0, vendor release 6600) Release Date: 18 October 2002 If the server is older than 6-12 months, or if your card is newer than the above date, look for a newer version before reporting problems. (See http://www.XFree86.Org/) Build Operating System: Linux 2.4.21-rc1-ac1-cryptoloop i686 [ELF] Module Loader present Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/XFree86.0.log", Time: Mon Aug 16 18:16:34 2004 (==) Using config file: "/etc/X11/XF86Config-4" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "PS2Mouse" (**) | |-->Device "Neomagic" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xfree86" (**) XKB: rules: "xfree86" (**) Option "XkbModel" "pc104" (**) XKB: model: "pc104" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (**) |-->Input Device "Generic Mouse" (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Spe edo,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (++) using VT number 7 (II) Open APM successful (II) Module ABI versions: XFree86 ANSI C Emulation: 0.1 XFree86 Video Driver: 0.5 XFree86 XInput driver : 0.3 XFree86 Server Extension : 0.1 XFree86 Font Renderer : 0.3 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.3 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.5 (II) PCI: Probing config type using method 1 (II) PCI: Config type is 1 (II) PCI: stages = 0x03, oldVal1 = 0x80003ac0, mode1Res1 = 0x80000000 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,7190 card 0000,0000 rev 03 class 06,00,00 hdr 00 (II) PCI: 00:01:0: chip 8086,7191 card 0000,0000 rev 03 class 06,04,00 hdr 01 (II) PCI: 00:02:0: chip 104c,ac1d card 4000,0000 rev 00 class 06,07,00 hdr 82 (II) PCI: 00:02:1: chip 104c,ac1d card 4800,0000 rev 00 class 06,07,00 hdr 82 (II) PCI: 00:06:0: chip 1013,6001 card 1014,1010 rev 01 class 04,01,00 hdr 00 (II) PCI: 00:07:0: chip 8086,7110 card 0000,0000 rev 02 class 06,80,00 hdr 80 (II) PCI: 00:07:1: chip 8086,7111 card 0000,0000 rev 01 class 01,01,80 hdr 00 (II) PCI: 00:07:2: chip 8086,7112 card 0000,0000 rev 01 class 0c,03,00 hdr 00 (II) PCI: 00:07:3: chip 8086,7113 card 0000,0000 rev 02 class 06,80,00 hdr 00 (II) PCI: 01:00:0: chip 10c8,0005 card 1014,00dd rev 12 class 03,00,00 hdr 00 (II) PCI: End of PCI scan (II) LoadModule: "scanpci" (II) Loading /usr/X11R6/lib/modules/libscanpci.a (II) Module scanpci: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.5 (II) UnloadModule: "scanpci" (II) Unloading /usr/X11R6/lib/modules/libscanpci.a (II) Host-to-PCI bridge: (II) PCI-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (-1,0,0), BCTRL: 0x08 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 1: bridge is at (0:1:0), (0,1,1), BCTRL: 0x88 (VGA_EN is set) (II) Bus 1 I/O range: [0] -1 0 0x0000d000 - 0x0000dfff (0x1000) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x70000000 - 0xdfffffff (0x70000000) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0xe0000000 - 0xf7ffffff (0x18000000) MX[B] (--) PCI:*(1:0:0) Neomagic NM2200 rev 18, Mem @ 0xe0000000/24, 0x70000000/22, 0x 70400000/20 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) Active PCI resource ranges: [0] -1 0 0x50000000 - 0x500fffff (0x100000) MX[B] [1] -1 0 0x50100000 - 0x50100fff (0x1000) MX[B] [2] -1 0 0x40000000 - 0x43ffffff (0x4000000) MX[B] [3] -1 0 0x70400000 - 0x704fffff (0x100000) MX[B](B) [4] -1 0 0x70000000 - 0x703fffff (0x400000) MX[B](B) [5] -1 0 0xe0000000 - 0xe0ffffff (0x1000000) MX[B](B) [6] -1 0 0x00008400 - 0x0000841f (0x20) IX[B] [7] -1 0 0x0000fcf0 - 0x0000fcff (0x10) IX[B] (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0x50000000 - 0x500fffff (0x100000) MX[B] [1] -1 0 0x50100000 - 0x50100fff (0x1000) MX[B] [2] -1 0 0x40000000 - 0x43ffffff (0x4000000) MX[B] [3] -1 0 0x70400000 - 0x704fffff (0x100000) MX[B](B) [4] -1 0 0x70000000 - 0x703fffff (0x400000) MX[B](B) [5] -1 0 0xe0000000 - 0xe0ffffff (0x1000000) MX[B](B) [6] -1 0 0x00008400 - 0x0000841f (0x20) IX[B] [7] -1 0 0x0000fcf0 - 0x0000fcff (0x10) IX[B] (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x50000000 - 0x500fffff (0x100000) MX[B] [6] -1 0 0x50100000 - 0x50100fff (0x1000) MX[B] [7] -1 0 0x40000000 - 0x43ffffff (0x4000000) MX[B] [8] -1 0 0x70400000 - 0x704fffff (0x100000) MX[B](B) [9] -1 0 0x70000000 - 0x703fffff (0x400000) MX[B](B) [10] -1 0 0xe0000000 - 0xe0ffffff (0x1000000) MX[B](B) [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [13] -1 0 0x00008400 - 0x0000841f (0x20) IX[B] [14] -1 0 0x0000fcf0 - 0x0000fcff (0x10) IX[B] (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:debug_xform.o": No symbols found (II) Module GLcore: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.1 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.1 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.5 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.1 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.1 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.1 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.1.10 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.3 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Server Extension, version 0.1 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.5 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.13.0 Module class: XFree86 Server Extension ABI class: XFree86 Server Extension, version 0.1 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols foun d (II) Module speedo: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.3 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.1 Module class: XFree86 Font Renderer ABI class: XFree86 Font Renderer, version 0.3 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.5 (II) LoadModule: "neomagic" (II) Loading /usr/X11R6/lib/modules/drivers/neomagic_drv.o (II) Module neomagic: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 Module class: XFree86 Video Driver ABI class: XFree86 Video Driver, version 0.5 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.3 (II) NEOMAGIC: Driver for Neomagic chipsets: neo2070, neo2090, neo2093, neo2097, neo2160, neo2200, neo2230, neo2360, neo2380 (II) Primary Device is: PCI 01:00:0 (--) Assigning device section with no busID to primary device (--) Chipset neo2200 found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x50000000 - 0x500fffff (0x100000) MX[B] [6] -1 0 0x50100000 - 0x50100fff (0x1000) MX[B] [7] -1 0 0x40000000 - 0x43ffffff (0x4000000) MX[B] [8] -1 0 0x70400000 - 0x704fffff (0x100000) MX[B](B) [9] -1 0 0x70000000 - 0x703fffff (0x400000) MX[B](B) [10] -1 0 0xe0000000 - 0xe0ffffff (0x1000000) MX[B](B) [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [13] -1 0 0x00008400 - 0x0000841f (0x20) IX[B] [14] -1 0 0x0000fcf0 - 0x0000fcff (0x10) IX[B] (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x50000000 - 0x500fffff (0x100000) MX[B] [6] -1 0 0x50100000 - 0x50100fff (0x1000) MX[B] [7] -1 0 0x40000000 - 0x43ffffff (0x4000000) MX[B] [8] -1 0 0x70400000 - 0x704fffff (0x100000) MX[B](B) [9] -1 0 0x70000000 - 0x703fffff (0x400000) MX[B](B) [10] -1 0 0xe0000000 - 0xe0ffffff (0x1000000) MX[B](B) [11] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [12] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [13] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [14] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [15] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [16] -1 0 0x00008400 - 0x0000841f (0x20) IX[B] [17] -1 0 0x0000fcf0 - 0x0000fcff (0x10) IX[B] [18] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [19] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.5 (II) NEOMAGIC(0): Chipset is a MagicMedia 256AV (NM2200) (II) NEOMAGIC(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x000 0 (--) NEOMAGIC(0): Panel is a 1024x768 color TFT display (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Reloading /usr/X11R6/lib/modules/libvbe.a (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) NEOMAGIC(0): initializing int10 (II) NEOMAGIC(0): Primary V_BIOS segment is: 0xc000 (II) NEOMAGIC(0): VESA BIOS detected (II) NEOMAGIC(0): VESA VBE Version 2.0 (II) NEOMAGIC(0): VESA VBE Total Mem: 2496 kB (II) NEOMAGIC(0): VESA VBE OEM: MagicMedia 256AV 48K (II) NEOMAGIC(0): VESA VBE OEM Software Rev: 1.15 (II) NEOMAGIC(0): VESA VBE OEM Vendor: NeoMagic (II) NEOMAGIC(0): VESA VBE OEM Product: MagicMedia 256AV (II) NEOMAGIC(0): VESA VBE OEM Product Rev: 01.0 (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) NEOMAGIC(0): VESA VBE DDC supported (II) NEOMAGIC(0): VESA VBE DDC Level none (II) NEOMAGIC(0): VESA VBE DDC transfer in appr. 0 sec. (II) NEOMAGIC(0): VESA VBE DDC read failed (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.2.0 ABI class: XFree86 Video Driver, version 0.5 (II) NEOMAGIC(0): I2C bus "I2C bus" initialized. (II) NEOMAGIC(0): I2C device "I2C bus:ddc2" registered. (II) NEOMAGIC(0): I2C device "I2C bus:ddc2" removed. (--) NEOMAGIC(0): No DDC signal (**) NEOMAGIC(0): Depth 16, (--) framebuffer bpp 16 (==) NEOMAGIC(0): RGB weight 565 (==) NEOMAGIC(0): Default visual is TrueColor (==) NEOMAGIC(0): Using gamma correction (1.0, 1.0, 1.0) (--) NEOMAGIC(0): Internal LCD only display mode (==) NEOMAGIC(0): using linear mode (**) NEOMAGIC(0): using PCI Burst mode (**) NEOMAGIC(0): Option StrangeLockups set: disabling some acceleration (--) NEOMAGIC(0): FB base address is set at 0xE0000000. (--) NEOMAGIC(0): MMIO base address is set at 0x70000000. (--) NEOMAGIC(0): MMIO base address2 is set at 0x70400000. (--) NEOMAGIC(0): VideoRAM: 2560 kByte (--) NEOMAGIC(0): Max Clock: 110000 kHz (II) NEOMAGIC(0): PS2Mouse: Using hsync range of 28.00-49.00 kHz (II) NEOMAGIC(0): PS2Mouse: Using vrefresh range of 43.00-72.00 Hz (II) NEOMAGIC(0): Clock range: 11.00 to 110.00 MHz (II) NEOMAGIC(0): Removing mode (640x350) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "640x350" (unknown reason) (II) NEOMAGIC(0): Removing mode (320x175) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "320x175" (unknown reason) (II) NEOMAGIC(0): Removing mode (640x400) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "640x400" (unknown reason) (II) NEOMAGIC(0): Removing mode (320x200) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "320x200" (unknown reason) (II) NEOMAGIC(0): Removing mode (720x400) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "720x400" (unknown reason) (II) NEOMAGIC(0): Removing mode (360x200) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "360x200" (unknown reason) (II) NEOMAGIC(0): Not using default mode "640x480" (vrefresh out of range) (II) NEOMAGIC(0): Not using default mode "320x240" (vrefresh out of range) (II) NEOMAGIC(0): Not using default mode "640x480" (vrefresh out of range) (II) NEOMAGIC(0): Not using default mode "320x240" (vrefresh out of range) (II) NEOMAGIC(0): Not using default mode "640x480" (vrefresh out of range) (II) NEOMAGIC(0): Not using default mode "320x240" (vrefresh out of range) (II) NEOMAGIC(0): Removing mode (400x300) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "400x300" (unknown reason) (II) NEOMAGIC(0): Removing mode (400x300) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "400x300" (unknown reason) (II) NEOMAGIC(0): Removing mode (400x300) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "400x300" (unknown reason) (II) NEOMAGIC(0): Not using default mode "800x600" (vrefresh out of range) (II) NEOMAGIC(0): Removing mode (400x300) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "400x300" (unknown reason) (II) NEOMAGIC(0): Not using default mode "800x600" (hsync out of range) (II) NEOMAGIC(0): Removing mode (400x300) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "400x300" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1024x768" (bad mode clock/interlace/do ublescan) (II) NEOMAGIC(0): Not using default mode "512x384" (bad mode clock/interlace/dou blescan) (II) NEOMAGIC(0): Removing mode (512x384) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "512x384" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1024x768" (hsync out of range) (II) NEOMAGIC(0): Removing mode (512x384) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "512x384" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1024x768" (hsync out of range) (II) NEOMAGIC(0): Removing mode (512x384) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "512x384" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1024x768" (hsync out of range) (II) NEOMAGIC(0): Removing mode (512x384) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "512x384" (unknown reason) (II) NEOMAGIC(0): Removing mode (1152x864) larger than the LCD panel (1024x768) (II) NEOMAGIC(0): Not using default mode "1152x864" (unknown reason) (II) NEOMAGIC(0): Removing mode (576x432) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "576x432" (unknown reason) (II) NEOMAGIC(0): Removing mode (1280x960) larger than the LCD panel (1024x768) (II) NEOMAGIC(0): Not using default mode "1280x960" (unknown reason) (II) NEOMAGIC(0): Not using default mode "640x480" (hsync out of range) (II) NEOMAGIC(0): Not using default mode "1280x960" (bad mode clock/interlace/do ublescan) (II) NEOMAGIC(0): Not using default mode "640x480" (hsync out of range) (II) NEOMAGIC(0): Removing mode (1280x1024) larger than the LCD panel (1024x768) (II) NEOMAGIC(0): Not using default mode "1280x1024" (unknown reason) (II) NEOMAGIC(0): Removing mode (640x512) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "640x512" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1280x1024" (bad mode clock/interlace/d oublescan) (II) NEOMAGIC(0): Removing mode (640x512) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "640x512" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1280x1024" (bad mode clock/interlace/d oublescan) (II) NEOMAGIC(0): Removing mode (640x512) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "640x512" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1600x1200" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "800x600" (hsync out of range) (II) NEOMAGIC(0): Not using default mode "1600x1200" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "800x600" (hsync out of range) (II) NEOMAGIC(0): Not using default mode "1600x1200" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "800x600" (hsync out of range) (II) NEOMAGIC(0): Not using default mode "1600x1200" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "800x600" (hsync out of range) (II) NEOMAGIC(0): Not using default mode "1600x1200" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "800x600" (bad mode clock/interlace/dou blescan) (II) NEOMAGIC(0): Not using default mode "1792x1344" (insufficient memory for mo de) (II) NEOMAGIC(0): Removing mode (896x672) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "896x672" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1792x1344" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "896x672" (bad mode clock/interlace/dou blescan) (II) NEOMAGIC(0): Not using default mode "1856x1392" (insufficient memory for mo de) (II) NEOMAGIC(0): Removing mode (928x696) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "928x696" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1856x1392" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "928x696" (bad mode clock/interlace/dou blescan) (II) NEOMAGIC(0): Not using default mode "1920x1440" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "960x720" (bad mode clock/interlace/dou blescan) (II) NEOMAGIC(0): Not using default mode "1920x1440" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "960x720" (bad mode clock/interlace/dou blescan) (II) NEOMAGIC(0): Removing mode (832x624) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "832x624" (unknown reason) (II) NEOMAGIC(0): Removing mode (416x312) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "416x312" (unknown reason) (II) NEOMAGIC(0): Removing mode (1152x768) larger than the LCD panel (1024x768) (II) NEOMAGIC(0): Not using default mode "1152x768" (unknown reason) (II) NEOMAGIC(0): Removing mode (576x384) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "576x384" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1400x1050" (insufficient memory for mo de) (II) NEOMAGIC(0): Removing mode (700x525) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "700x525" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1400x1050" (insufficient memory for mo de) (II) NEOMAGIC(0): Removing mode (700x525) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "700x525" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1600x1024" (insufficient memory for mo de) (II) NEOMAGIC(0): Removing mode (800x512) that won't display properly on LCD (II) NEOMAGIC(0): Not using default mode "800x512" (unknown reason) (II) NEOMAGIC(0): Not using default mode "1920x1440" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "960x720" (bad mode clock/interlace/dou blescan) (II) NEOMAGIC(0): Not using default mode "2048x1536" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "1024x768" (bad mode clock/interlace/do ublescan) (II) NEOMAGIC(0): Not using default mode "2048x1536" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "1024x768" (bad mode clock/interlace/do ublescan) (II) NEOMAGIC(0): Not using default mode "2048x1536" (insufficient memory for mo de) (II) NEOMAGIC(0): Not using default mode "1024x768" (bad mode clock/interlace/do ublescan) (II) NEOMAGIC(0): Not using mode "1280x960" (no mode of this name) (II) NEOMAGIC(0): Not using mode "1152x864" (no mode of this name) (--) NEOMAGIC(0): Virtual size is 1024x768 (pitch 1024) (**) NEOMAGIC(0): Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz (II) NEOMAGIC(0): Modeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (**) NEOMAGIC(0): Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) NEOMAGIC(0): Modeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (**) NEOMAGIC(0): Default mode "640x480": 25.2 MHz, 31.5 kHz, 60.0 Hz (II) NEOMAGIC(0): Modeline "640x480" 25.20 640 656 752 800 480 490 492 525 - hsync -vsync (++) NEOMAGIC(0): DPI set to (100, 100) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a (II) Module fb: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 ANSI C Emulation, version 0.1 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 1.0.0 ABI class: XFree86 Video Driver, version 0.5 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="The XFree86 Project" compiled for 4.2.1.1, module version = 0.1.0 ABI class: XFree86 Video Driver, version 0.5 (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0x70400000 - 0x704fffff (0x100000) MX[B] [1] 0 0 0x70000000 - 0x703fffff (0x400000) MX[B] [2] 0 0 0xe0000000 - 0xe0ffffff (0x1000000) MX[B] [3] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [4] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [5] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [6] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [7] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [8] -1 0 0x50000000 - 0x500fffff (0x100000) MX[B] [9] -1 0 0x50100000 - 0x50100fff (0x1000) MX[B] [10] -1 0 0x40000000 - 0x43ffffff (0x4000000) MX[B] [11] -1 0 0x70400000 - 0x704fffff (0x100000) MX[B](B) [12] -1 0 0x70000000 - 0x703fffff (0x400000) MX[B](B) [13] -1 0 0xe0000000 - 0xe0ffffff (0x1000000) MX[B](B) [14] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [15] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [16] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [17] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [18] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [19] -1 0 0x00008400 - 0x0000841f (0x20) IX[B] [20] -1 0 0x0000fcf0 - 0x0000fcff (0x10) IX[B] [21] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [22] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (==) NEOMAGIC(0): Write-combining range (0xe0000000,0x400000) (II) NEOMAGIC(0): Stretching disabled (II) NEOMAGIC(0): Using linear framebuffer at: 0xE0000000 (--) NEOMAGIC(0): 1048576 bytes off-screen memory available (II) NEOMAGIC(0): Using H/W Cursor. (II) NEOMAGIC(0): Using 256 scanlines of offscreen memory (II) NEOMAGIC(0): Using XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles Solid Horizontal and Vertical Lines Offscreen Pixmaps Setting up tile and stipple cache: 16 128x128 slots (II) NEOMAGIC(0): Acceleration Initialized (==) NEOMAGIC(0): Backing store disabled (==) NEOMAGIC(0): Silken mouse enabled (**) Option "dpms" (**) NEOMAGIC(0): DPMS enabled (II) Setting vga for screen 0. (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Keyboard "Generic Keyboard" handled by legacy driver (**) Option "Protocol" "PS/2" (**) Configured Mouse: Protocol: "PS/2" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/psaux" (==) Configured Mouse: Buttons: 3 (**) Option "Protocol" "ImPS/2" (**) Generic Mouse: Protocol: "ImPS/2" (**) Generic Mouse: always reports core events (**) Option "Device" "/dev/input/mice" (EE) xf86OpenSerial: Cannot open device /dev/input/mice No such device. (EE) Generic Mouse: cannot open input device (EE) PreInit failed for input device "Generic Mouse" (II) UnloadModule: "mouse" (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) PM Event received: System Suspend Request (II) PM Event received: Power Status Change (II) PM Event received: Normal Resume System (II) NEOMAGIC(0): Stretching disabled -- Nathan Parslow parslow@optusnet.com.au xresprobe-0.4.24ubuntu9/tests/log-smi-1024x7680000644000000000000000000010511010214367723015514 0ustar This is a pre-release version of the The X.Org Foundation X11. It is not supported in any way. Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/. Select the "xorg" product for bugs you find in this release. Before reporting bugs in pre-release versions please check the latest version in the The X.Org Foundation "monolithic tree" CVS repository hosted at http://www.freedesktop.org/Software/xorg/ X Window System Version 6.8.1.99 (Ubuntu 6.8.1-1ubuntu11 20050119010805 root@) Release Date: 2 October 2004 + 6.8.x branch CVS X Protocol Version 11, Revision 0, Release 6.8.1.99 Build Operating System: Linux 2.6.8.1 i686 [ELF] Current Operating System: Linux wildebeest 2.6.10-2-686 #1 Thu Jan 27 13:39:43 UTC 2005 i686 Build Date: 19 January 2005 Before reporting problems, check http://wiki.X.Org to make sure that you have the latest version. Module Loader present OS Kernel: Linux version 2.6.10-2-686 (buildd@terranova) (gcc version 3.3.5 (Debian 1:3.3.5-6ubuntu1)) #1 Thu Jan 27 13:39:43 UTC 2005 Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/Xorg.0.log", Time: Sun Jan 30 18:34:44 2005 (==) Using config file: "/etc/X11/xorg.conf" (==) ServerLayout "Default Layout" (**) |-->Screen "Default Screen" (0) (**) | |-->Monitor "Generic Monitor" (**) | |-->Device "Silicon Motion, Inc. SM720 Lynx3DM" (**) |-->Input Device "Generic Keyboard" (**) Option "XkbRules" "xorg" (**) XKB: rules: "xorg" (**) Option "XkbModel" "pc105" (**) XKB: model: "pc105" (**) Option "XkbLayout" "us" (**) XKB: layout: "us" (**) Option "XkbOptions" "compose:menu" (**) XKB: options: "compose:menu" (==) Keyboard: CustomKeycode disabled (**) |-->Input Device "Configured Mouse" (**) |-->Input Device "Synaptics Touchpad" (WW) The directory "/usr/lib/X11/fonts/cyrillic" does not exist. Entry deleted from font path. (WW) The directory "/usr/lib/X11/fonts/CID" does not exist. Entry deleted from font path. (WW) `fonts.dir' not found (or not valid) in "/var/lib/defoma/x-ttcidfont-conf.d/dirs/CID". Entry deleted from font path. (Run 'mkfontdir' on "/var/lib/defoma/x-ttcidfont-conf.d/dirs/CID"). (**) FontPath set to "unix/:7100,/usr/lib/X11/fonts/misc,/usr/lib/X11/fonts/100dpi/:unscaled,/usr/lib/X11/fonts/75dpi/:unscaled,/usr/lib/X11/fonts/Type1,/usr/lib/X11/fonts/Speedo,/usr/lib/X11/fonts/100dpi,/usr/lib/X11/fonts/75dpi,/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType" (==) RgbPath set to "/usr/X11R6/lib/X11/rgb" (==) ModulePath set to "/usr/X11R6/lib/modules" (WW) Open APM failed (/dev/apm_bios) (No such file or directory) (II) Module ABI versions: X.Org ANSI C Emulation: 0.2 X.Org Video Driver: 0.7 X.Org XInput driver : 0.4 X.Org Server Extension : 0.2 X.Org Font Renderer : 0.4 (II) Loader running on linux (II) LoadModule: "bitmap" (II) Loading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Module bitmap: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font Bitmap (II) LoadModule: "pcidata" (II) Loading /usr/X11R6/lib/modules/libpcidata.a (II) Module pcidata: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (++) using VT number 7 (II) PCI: PCI scan (all values are in hex) (II) PCI: 00:00:0: chip 8086,7194 card 0000,0000 rev 01 class 06,00,00 hdr 80 (II) PCI: 00:00:1: chip 8086,7195 card 1043,1063 rev 00 class 04,01,00 hdr 00 (II) PCI: 00:02:0: chip 126f,0720 card 1043,1332 rev b1 class 03,00,00 hdr 00 (II) PCI: 00:07:0: chip 8086,7198 card 0000,0000 rev 01 class 06,01,00 hdr 80 (II) PCI: 00:07:1: chip 8086,7199 card 0000,0000 rev 00 class 01,01,80 hdr 00 (II) PCI: 00:07:2: chip 8086,719a card 0000,0000 rev 00 class 0c,03,00 hdr 00 (II) PCI: 00:07:3: chip 8086,719b card 0000,0000 rev 00 class 06,80,00 hdr 00 (II) PCI: 00:09:0: chip 134d,7890 card 134d,0001 rev 01 class 07,80,00 hdr 00 (II) PCI: 00:0a:0: chip 1180,0476 card 4000,0000 rev 80 class 06,07,00 hdr 82 (II) PCI: 00:0a:1: chip 1180,0476 card 4800,0000 rev 80 class 06,07,00 hdr 82 (II) PCI: 05:00:0: chip 1260,3890 card 10b8,a835 rev 01 class 02,80,00 hdr 00 (II) PCI: End of PCI scan (II) Host-to-PCI bridge: (II) Bus 0: bridge is at (0:0:0), (0,0,5), BCTRL: 0x0008 (VGA_EN is set) (II) Bus 0 I/O range: [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) Bus 0 non-prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) Bus 0 prefetchable memory range: [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] (II) PCI-to-ISA bridge: (II) Bus -1: bridge is at (0:7:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set) (II) PCI-to-CardBus bridge: (II) Bus 1: bridge is at (0:10:0), (0,1,4), BCTRL: 0x0580 (VGA_EN is cleared) (II) Bus 1 I/O range: [0] -1 0 0x00004000 - 0x000040ff (0x100) IX[B] [1] -1 0 0x00004400 - 0x000044ff (0x100) IX[B] (II) Bus 1 non-prefetchable memory range: [0] -1 0 0x10800000 - 0x10bfffff (0x400000) MX[B] (II) Bus 1 prefetchable memory range: [0] -1 0 0x10400000 - 0x107fffff (0x400000) MX[B] (II) PCI-to-CardBus bridge: (II) Bus 5: bridge is at (0:10:1), (0,5,8), BCTRL: 0x0500 (VGA_EN is cleared) (II) Bus 5 I/O range: [0] -1 0 0x00004800 - 0x000048ff (0x100) IX[B] [1] -1 0 0x00004c00 - 0x00004cff (0x100) IX[B] (II) Bus 5 non-prefetchable memory range: [0] -1 0 0x11000000 - 0x113fffff (0x400000) MX[B] (II) Bus 5 prefetchable memory range: [0] -1 0 0x10c00000 - 0x10ffffff (0x400000) MX[B] (--) PCI:*(0:2:0) Silicon Motion, Inc. SM720 Lynx3DM rev 177, Mem @ 0xf8000000/26 (II) Addressable bus resource ranges are [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] (II) OS-reported resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) Active PCI resource ranges: [0] -1 0 0x11000000 - 0x11001fff (0x2000) MX[B] [1] -1 0 0xf8000000 - 0xfbffffff (0x4000000) MX[B](B) [2] -1 0 0x00002000 - 0x0000203f (0x40) IX[B] [3] -1 0 0x00001c00 - 0x00001c1f (0x20) IX[B] [4] -1 0 0x00001800 - 0x0000180f (0x10) IX[B] [5] -1 0 0x00001000 - 0x0000103f (0x40) IX[B] [6] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] (II) Active PCI resource ranges after removing overlaps: [0] -1 0 0x11000000 - 0x11001fff (0x2000) MX[B] [1] -1 0 0xf8000000 - 0xfbffffff (0x4000000) MX[B](B) [2] -1 0 0x00002000 - 0x0000203f (0x40) IX[B] [3] -1 0 0x00001c00 - 0x00001c1f (0x20) IX[B] [4] -1 0 0x00001800 - 0x0000180f (0x10) IX[B] [5] -1 0 0x00001000 - 0x0000103f (0x40) IX[B] [6] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] (II) OS-reported resource ranges after removing overlaps with PCI: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x10ffffff (0x10f00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [6] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] (II) All system resource ranges: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x10ffffff (0x10f00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x11000000 - 0x11001fff (0x2000) MX[B] [6] -1 0 0xf8000000 - 0xfbffffff (0x4000000) MX[B](B) [7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [8] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [9] -1 0 0x00002000 - 0x0000203f (0x40) IX[B] [10] -1 0 0x00001c00 - 0x00001c1f (0x20) IX[B] [11] -1 0 0x00001800 - 0x0000180f (0x10) IX[B] [12] -1 0 0x00001000 - 0x0000103f (0x40) IX[B] [13] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] (II) LoadModule: "GLcore" (II) Loading /usr/X11R6/lib/modules/extensions/libGLcore.a Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_clip.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_norm.o": No symbols found Skipping "/usr/X11R6/lib/modules/extensions/libGLcore.a:m_debug_xform.o": No symbols found (II) Module GLcore: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) LoadModule: "bitmap" (II) Reloading /usr/X11R6/lib/modules/fonts/libbitmap.a (II) Loading font Bitmap (II) LoadModule: "dbe" (II) Loading /usr/X11R6/lib/modules/extensions/libdbe.a (II) Module dbe: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension DOUBLE-BUFFER (II) LoadModule: "ddc" (II) Loading /usr/X11R6/lib/modules/libddc.a (II) Module ddc: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "dri" (II) Loading /usr/X11R6/lib/modules/extensions/libdri.a (II) Module dri: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading sub module "drm" (II) LoadModule: "drm" (II) Loading /usr/X11R6/lib/modules/linux/libdrm.a (II) Module drm: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading extension XFree86-DRI (II) LoadModule: "extmod" (II) Loading /usr/X11R6/lib/modules/extensions/libextmod.a (II) Module extmod: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension SHAPE (II) Loading extension MIT-SUNDRY-NONSTANDARD (II) Loading extension BIG-REQUESTS (II) Loading extension SYNC (II) Loading extension MIT-SCREEN-SAVER (II) Loading extension XC-MISC (II) Loading extension XFree86-VidModeExtension (II) Loading extension XFree86-Misc (II) Loading extension XFree86-DGA (II) Loading extension DPMS (II) Loading extension FontCache (II) Loading extension TOG-CUP (II) Loading extension Extended-Visual-Information (II) Loading extension XVideo (II) Loading extension XVideo-MotionCompensation (II) Loading extension X-Resource (II) LoadModule: "freetype" (II) Loading /usr/X11R6/lib/modules/fonts/libfreetype.a (II) Module freetype: vendor="X.Org Foundation & the After X-TT Project" compiled for 6.8.1.99, module version = 2.1.0 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font FreeType (II) LoadModule: "glx" (II) Loading /usr/X11R6/lib/modules/extensions/libglx.a (II) Module glx: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org Server Extension, version 0.2 (II) Loading sub module "GLcore" (II) LoadModule: "GLcore" (II) Reloading /usr/X11R6/lib/modules/extensions/libGLcore.a (II) Loading extension GLX (II) LoadModule: "int10" (II) Loading /usr/X11R6/lib/modules/linux/libint10.a (II) Module int10: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "record" (II) Loading /usr/X11R6/lib/modules/extensions/librecord.a (II) Module record: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.13.0 Module class: X.Org Server Extension ABI class: X.Org Server Extension, version 0.2 (II) Loading extension RECORD (II) LoadModule: "speedo" (II) Loading /usr/X11R6/lib/modules/fonts/libspeedo.a Skipping "/usr/X11R6/lib/modules/fonts/libspeedo.a:spencode.o": No symbols found (II) Module speedo: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.1 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font Speedo (II) LoadModule: "type1" (II) Loading /usr/X11R6/lib/modules/fonts/libtype1.a (II) Module type1: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.2 Module class: X.Org Font Renderer ABI class: X.Org Font Renderer, version 0.4 (II) Loading font Type1 (II) Loading font CID (II) LoadModule: "v4l" (II) Loading /usr/X11R6/lib/modules/drivers/linux/v4l_drv.o (II) Module v4l: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 0.0.1 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "vbe" (II) Loading /usr/X11R6/lib/modules/libvbe.a (II) Module vbe: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.1.0 ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "siliconmotion" (II) Loading /usr/X11R6/lib/modules/drivers/siliconmotion_drv.o (II) Module siliconmotion: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.3.1 Module class: X.Org Video Driver ABI class: X.Org Video Driver, version 0.7 (II) LoadModule: "keyboard" (II) Loading /usr/X11R6/lib/modules/input/keyboard_drv.o (II) Module keyboard: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 Module class: X.Org XInput Driver ABI class: X.Org XInput driver, version 0.4 (II) LoadModule: "mouse" (II) Loading /usr/X11R6/lib/modules/input/mouse_drv.o (II) Module mouse: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 Module class: X.Org XInput Driver ABI class: X.Org XInput driver, version 0.4 (II) LoadModule: "synaptics" (II) Loading /usr/X11R6/lib/modules/input/synaptics_drv.o (II) Module synaptics: vendor="The XFree86 Project" compiled for 4.2.0, module version = 1.0.0 Module class: XFree86 XInput Driver ABI class: XFree86 XInput driver, version 0.3 (II) v4l driver for Video4Linux (II) Silicon Motion: driver (version 1.3.1) for Silicon Motion Lynx chipsets: Lynx, LynxE, Lynx3D, LynxEM, LynxEM+, Lynx3DM, Cougar3DR (II) Primary Device is: PCI 00:02:0 (--) Chipset Lynx3DM found (II) resource ranges after xf86ClaimFixedResources() call: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x10ffffff (0x10f00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x11000000 - 0x11001fff (0x2000) MX[B] [6] -1 0 0xf8000000 - 0xfbffffff (0x4000000) MX[B](B) [7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [8] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [9] -1 0 0x00002000 - 0x0000203f (0x40) IX[B] [10] -1 0 0x00001c00 - 0x00001c1f (0x20) IX[B] [11] -1 0 0x00001800 - 0x0000180f (0x10) IX[B] [12] -1 0 0x00001000 - 0x0000103f (0x40) IX[B] [13] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] (II) resource ranges after probing: [0] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [1] -1 0 0x00100000 - 0x10ffffff (0x10f00000) MX[B]E(B) [2] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [3] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [4] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [5] -1 0 0x11000000 - 0x11001fff (0x2000) MX[B] [6] -1 0 0xf8000000 - 0xfbffffff (0x4000000) MX[B](B) [7] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [8] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [9] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [10] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [11] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [12] -1 0 0x00002000 - 0x0000203f (0x40) IX[B] [13] -1 0 0x00001c00 - 0x00001c1f (0x20) IX[B] [14] -1 0 0x00001800 - 0x0000180f (0x10) IX[B] [15] -1 0 0x00001000 - 0x0000103f (0x40) IX[B] [16] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [17] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [18] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Setting vga for screen 0. (II) Loading sub module "vgahw" (II) LoadModule: "vgahw" (II) Loading /usr/X11R6/lib/modules/libvgahw.a (II) Module vgahw: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 0.1.0 ABI class: X.Org Video Driver, version 0.7 (**) Silicon MotionDepth 16, (--) framebuffer bpp 16 (==) Silicon MotionRGB weight 565 (==) Silicon MotionDefault visual is TrueColor (==) Silicon MotionUsing Hardware Cursor (II) Loading sub module "int10" (II) LoadModule: "int10" (II) Reloading /usr/X11R6/lib/modules/linux/libint10.a (II) Silicon MotionPrimary V_BIOS segment is: 0xc000 (II) Loading sub module "vbe" (II) LoadModule: "vbe" (II) Reloading /usr/X11R6/lib/modules/libvbe.a (II) Silicon MotionVESA BIOS detected (II) Silicon MotionVESA VBE Version 2.0 (II) Silicon MotionVESA VBE Total Mem: 8192 kB (II) Silicon MotionVESA VBE OEM: Silicon Motion SM720 VGA BIOS (II) Silicon MotionVESA VBE OEM Software Rev: 2.0 (II) Silicon MotionVESA VBE OEM Vendor: SM720 (II) Silicon MotionVESA VBE OEM Product: SM720 (II) Silicon MotionVESA VBE OEM Product Rev: SM720 (--) Silicon MotionChipset: "Lynx3DM" (II) Silicon MotionCursor Offset: FFFFFC00 Reserved: FFFFF800 (II) Silicon MotionTFT Panel Size = 1024x768 (II) Silicon MotionvgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000 (II) Loading sub module "i2c" (II) LoadModule: "i2c" (II) Loading /usr/X11R6/lib/modules/libi2c.a (II) Module i2c: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.2.0 ABI class: X.Org Video Driver, version 0.7 (II) Silicon MotionI2C bus "I2C bus" initialized. (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Loading sub module "ddc" (II) LoadModule: "ddc" (II) Reloading /usr/X11R6/lib/modules/libddc.a (II) Silicon MotionVESA VBE DDC supported (II) Silicon MotionVESA VBE DDC Level none (II) Silicon MotionVESA VBE DDC transfer in appr. 0 sec. (II) Silicon MotionVESA VBE DDC read successfully (==) Silicon MotionUsing gamma correction (1.0, 1.0, 1.0) (--) Silicon Motionvideoram: 8192kB (--) Silicon MotionDetected current MCLK value of 100.227 MHz (II) Silicon MotionGeneric Monitor: Using hsync range of 28.00-49.00 kHz (II) Silicon MotionGeneric Monitor: Using vrefresh range of 60.00-72.00 Hz (II) Silicon MotionClock range: 20.00 to 135.00 MHz (II) Silicon MotionMode: 640x350 16-bpp, 85.079948Hz (II) Silicon MotionNot using default mode "640x350" (vrefresh out of range) (II) Silicon MotionNot using default mode "320x175" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 640x400 16-bpp, 85.079948Hz (II) Silicon MotionNot using default mode "640x400" (vrefresh out of range) (II) Silicon MotionNot using default mode "320x200" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 720x400 16-bpp, 85.038902Hz (II) Silicon MotionNot using default mode "720x400" (vrefresh out of range) (II) Silicon MotionNot using default mode "360x200" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 640x480 16-bpp, 60.000000Hz (II) Silicon MotionNot using default mode "320x240" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 640x480 16-bpp, 72.808800Hz (II) Silicon MotionNot using default mode "640x480" (vrefresh out of range) (II) Silicon MotionNot using default mode "320x240" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 640x480 16-bpp, 75.000000Hz (II) Silicon MotionNot using default mode "640x480" (vrefresh out of range) (II) Silicon MotionNot using default mode "320x240" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 640x480 16-bpp, 85.008308Hz (II) Silicon MotionNot using default mode "640x480" (vrefresh out of range) (II) Silicon MotionNot using default mode "320x240" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 800x600 16-bpp, 56.250000Hz (II) Silicon MotionNot using default mode "800x600" (vrefresh out of range) (II) Silicon MotionNot using default mode "400x300" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 800x600 16-bpp, 60.316540Hz (II) Silicon MotionNot using default mode "400x300" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 800x600 16-bpp, 72.187569Hz (II) Silicon MotionNot using default mode "400x300" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 800x600 16-bpp, 75.000000Hz (II) Silicon MotionNot using default mode "800x600" (vrefresh out of range) (II) Silicon MotionNot using default mode "400x300" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 800x600 16-bpp, 85.136887Hz (II) Silicon MotionNot using default mode "800x600" (hsync out of range) (II) Silicon MotionNot using default mode "400x300" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "512x384" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1024x768 16-bpp, 60.003841Hz (II) Silicon MotionNot using default mode "512x384" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1024x768 16-bpp, 70.069359Hz (II) Silicon MotionNot using default mode "1024x768" (hsync out of range) (II) Silicon MotionNot using default mode "512x384" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1024x768 16-bpp, 75.076218Hz (II) Silicon MotionNot using default mode "1024x768" (hsync out of range) (II) Silicon MotionNot using default mode "512x384" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1024x768 16-bpp, 84.996689Hz (II) Silicon MotionNot using default mode "1024x768" (hsync out of range) (II) Silicon MotionNot using default mode "512x384" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1152x864 16-bpp, 75.000000Hz (II) Silicon MotionNot using default mode "1152x864" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "576x432" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1280x960 16-bpp, 60.000000Hz (II) Silicon MotionNot using default mode "1280x960" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "640x480" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1280x960" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "640x480" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1280x1024 16-bpp, 60.019741Hz (II) Silicon MotionNot using default mode "1280x1024" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "640x512" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1280x1024 16-bpp, 75.024673Hz (II) Silicon MotionNot using default mode "1280x1024" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "640x512" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1280x1024" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "640x512" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1600x1200" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "800x600" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1600x1200" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "800x600" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1600x1200" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "800x600" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1600x1200" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "800x600" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1600x1200" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "800x600" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1792x1344" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "896x672" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1792x1344" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "896x672" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1856x1392" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "928x696" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1856x1392" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "928x696" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1920x1440" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "960x720" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1920x1440" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "960x720" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 832x624 16-bpp, 74.551270Hz (II) Silicon MotionNot using default mode "832x624" (hsync out of range) (II) Silicon MotionNot using default mode "416x312" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1152x768 16-bpp, 54.781902Hz (II) Silicon MotionNot using default mode "1152x768" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "576x384" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1152x864 16-bpp, 85.057350Hz (II) Silicon MotionNot using default mode "1152x864" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "576x432" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1400x1050 16-bpp, 59.975616Hz (II) Silicon MotionNot using default mode "1400x1050" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "700x525" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1400x1050" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "700x525" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1400x1050" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "700x525" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1400x1050" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "700x525" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1440x900 16-bpp, 60.174088Hz (II) Silicon MotionNot using default mode "1440x900" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "720x450" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1600x1024 16-bpp, 59.998093Hz (II) Silicon MotionNot using default mode "1600x1024" (exceeds panel dimensions) (II) Silicon MotionNot using default mode "800x512" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1920x1200" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "960x600" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1920x1440" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "960x720" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "2048x1536" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "2048x1536" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "2048x1536" (bad mode clock/interlace/doublescan) (II) Silicon MotionNot using default mode "1024x768" (bad mode clock/interlace/doublescan) (II) Silicon MotionMode: 1024x768 16-bpp, 60.003841Hz (II) Silicon MotionMode: 800x600 16-bpp, 72.187569Hz (II) Silicon MotionMode: 640x480 16-bpp, 60.000000Hz (II) Silicon MotionMode: 800x600 16-bpp, 60.316540Hz (--) Silicon MotionVirtual size is 1024x768 (pitch 1024) (**) Silicon Motion*Default mode "1024x768": 65.0 MHz, 48.4 kHz, 60.0 Hz (II) Silicon MotionModeline "1024x768" 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (**) Silicon Motion*Default mode "800x600": 50.0 MHz, 48.1 kHz, 72.2 Hz (II) Silicon MotionModeline "800x600" 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (**) Silicon Motion*Default mode "640x480": 25.2 MHz, 31.5 kHz, 60.0 Hz (II) Silicon MotionModeline "640x480" 25.20 640 656 752 800 480 490 492 525 -hsync -vsync (**) Silicon Motion Default mode "800x600": 40.0 MHz, 37.9 kHz, 60.3 Hz (II) Silicon MotionModeline "800x600" 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (==) Silicon MotionDPI set to (75, 75) (II) Loading sub module "fb" (II) LoadModule: "fb" (II) Loading /usr/X11R6/lib/modules/libfb.a Skipping "/usr/X11R6/lib/modules/libfb.a:fbmmx.o": No symbols found (II) Module fb: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.0.0 ABI class: X.Org ANSI C Emulation, version 0.2 (II) Loading sub module "xaa" (II) LoadModule: "xaa" (II) Loading /usr/X11R6/lib/modules/libxaa.a (II) Module xaa: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 1.2.0 ABI class: X.Org Video Driver, version 0.7 (II) Loading sub module "ramdac" (II) LoadModule: "ramdac" (II) Loading /usr/X11R6/lib/modules/libramdac.a (II) Module ramdac: vendor="X.Org Foundation" compiled for 6.8.1.99, module version = 0.1.0 ABI class: X.Org Video Driver, version 0.7 (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] 0 0 0xf8000000 - 0xfbffffff (0x4000000) MX[B] [1] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) [2] -1 0 0x00100000 - 0x10ffffff (0x10f00000) MX[B]E(B) [3] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [4] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [5] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [6] -1 0 0x11000000 - 0x11001fff (0x2000) MX[B] [7] -1 0 0xf8000000 - 0xfbffffff (0x4000000) MX[B](B) [8] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] [9] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] [10] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] [11] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [12] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] [13] -1 0 0x00002000 - 0x0000203f (0x40) IX[B] [14] -1 0 0x00001c00 - 0x00001c1f (0x20) IX[B] [15] -1 0 0x00001800 - 0x0000180f (0x10) IX[B] [16] -1 0 0x00001000 - 0x0000103f (0x40) IX[B] [17] -1 0 0x00001400 - 0x000014ff (0x100) IX[B] [18] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] [19] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] (II) Silicon MotionSplitting WC range: base: 0xf8200000, size: 0x800000 (II) Silicon MotionSplitting WC range: base: 0xf8400000, size: 0x600000 (==) Silicon MotionWrite-combining range (0xf8800000,0x200000) (==) Silicon MotionWrite-combining range (0xf8400000,0x600000) (==) Silicon MotionWrite-combining range (0xf8200000,0x800000) (II) Silicon MotionCursor Offset: 007FFC00 Reserved: 007FF800 (II) Silicon MotionTFT Panel Size = 1024x768 (II) Silicon MotionvgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000 (II) Silicon MotionPrimary V_BIOS segment is: 0xc000 (II) Silicon MotionCurrent mode 0x03. (II) Silicon MotionSetting mode 0x62 (II) Silicon MotionFrameBuffer Box: 0,0 - 1024,4095 (II) Silicon MotionUsing XFree86 Acceleration Architecture (XAA) Screen to screen bit blits Solid filled rectangles 8x8 mono pattern filled rectangles 8x8 color pattern filled rectangles CPU to Screen color expansion Solid Horizontal and Vertical Lines Offscreen Pixmaps Setting up tile and stipple cache: 32 128x128 slots 18 256x256 slots 6 512x512 slots 32 8x8 color pattern slots (**) Option "dpms" (**) Silicon MotionDPMS enabled (II) Silicon MotionI2C device "I2C bus:SAA 7111A" registered at address 0x48. (II) Silicon MotionI2C device "I2C bus:SAA 7111A" removed. (==) RandR enabled (II) Setting vga for screen 0. (II) Initializing built-in extension MIT-SHM (II) Initializing built-in extension XInputExtension (II) Initializing built-in extension XTEST (II) Initializing built-in extension XKEYBOARD (II) Initializing built-in extension LBX (II) Initializing built-in extension XC-APPGROUP (II) Initializing built-in extension SECURITY (II) Initializing built-in extension XINERAMA (II) Initializing built-in extension XFIXES (II) Initializing built-in extension XFree86-Bigfont (II) Initializing built-in extension RENDER (II) Initializing built-in extension RANDR (II) Initializing built-in extension COMPOSITE (II) Initializing built-in extension DAMAGE (II) Initializing built-in extension XEVIE (**) Generic Keyboard: Core Keyboard (**) Option "Protocol" "standard" (**) Generic Keyboard: Protocol: standard (**) Option "AutoRepeat" "500 30" (**) Option "XkbRules" "xorg" (**) Generic Keyboard: XkbRules: "xorg" (**) Option "XkbModel" "pc105" (**) Generic Keyboard: XkbModel: "pc105" (**) Option "XkbLayout" "us" (**) Generic Keyboard: XkbLayout: "us" (**) Option "XkbOptions" "compose:menu" (**) Generic Keyboard: XkbOptions: "compose:menu" (**) Option "CustomKeycodes" "off" (**) Generic Keyboard: CustomKeycodes disabled (**) Option "Protocol" "ImPS/2" (**) Configured Mouse: Device: "/dev/input/mice" (**) Configured Mouse: Protocol: "ImPS/2" (**) Option "CorePointer" (**) Configured Mouse: Core Pointer (**) Option "Device" "/dev/input/mice" (==) Configured Mouse: Emulate3Buttons, Emulate3Timeout: 50 (**) Option "ZAxisMapping" "4 5" (**) Configured Mouse: ZAxisMapping: buttons 4 and 5 (**) Configured Mouse: Buttons: 5 (II) Synaptics touchpad driver version 0.13.6 Synaptics Touchpad no synaptics event device found (checked 7 nodes) (**) Option "Device" "/dev/psaux" Query no Synaptics: 6003C8 (EE) Synaptics Touchpad no synaptics touchpad detected and no repeater device (EE) Synaptics Touchpad Unable to query/initialize Synaptics hardware. (EE) PreInit failed for input device "Synaptics Touchpad" (II) UnloadModule: "synaptics" (II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE) (II) XINPUT: Adding extended input device "Generic Keyboard" (type: KEYBOARD) (II) Configured Mouse: ps2EnableDataReporting: succeeded Warning: font renderer for ".pcf" already registered at priority 0 Warning: font renderer for ".pcf.Z" already registered at priority 0 Warning: font renderer for ".pcf.gz" already registered at priority 0 Warning: font renderer for ".snf" already registered at priority 0 Warning: font renderer for ".snf.Z" already registered at priority 0 Warning: font renderer for ".snf.gz" already registered at priority 0 Warning: font renderer for ".bdf" already registered at priority 0 Warning: font renderer for ".bdf.Z" already registered at priority 0 Warning: font renderer for ".bdf.gz" already registered at priority 0 Warning: font renderer for ".pmf" already registered at priority 0 Could not init font path element unix/:7100, removing from list! SetGrabKeysState - disabled SetGrabKeysState - enabled (II) 3rd Button detected: disabling emulate3Button SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled SetGrabKeysState - disabled SetGrabKeysState - enabled xresprobe-0.4.24ubuntu9/Makefile0000644000000000000000000000107710220413313013466 0ustar DATADIR := /usr/share/xresprobe SBINDIR := /usr/sbin all: $(MAKE) -C ddcprobe clean: $(MAKE) -C ddcprobe clean install: $(MAKE) -C ddcprobe install DESTDIR="$(DESTDIR)" mkdir -p $(DESTDIR)$(DATADIR)/ mkdir -p $(DESTDIR)$(SBINDIR)/ install -m755 xresprobe $(DESTDIR)$(SBINDIR)/ install -m755 xprobe.sh $(DESTDIR)$(DATADIR)/ install -m755 ddcprobe.sh $(DESTDIR)$(DATADIR)/ install -m755 lcdsize.sh $(DESTDIR)$(DATADIR)/ install -m755 bitdepth.sh $(DESTDIR)$(DATADIR)/ install -m755 rigprobe.sh $(DESTDIR)$(DATADIR)/ install -m644 xorg.conf $(DESTDIR)$(DATADIR)/ xresprobe-0.4.24ubuntu9/lcdsize.sh0000755000000000000000000001162510703166737014047 0ustar #!/bin/sh # usage: lcdsize.sh driver logfile [stdout] # Copyright (C) 2004 Canonical Ltd. # Author: Daniel Stone # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License with # the Debian GNU/Linux distribution in file /usr/share/common-licenses/GPL; # if not, write to the Free Software Foundation, Inc., 59 Temple Place, # Suite 330, Boston, MA 02111-1307 USA # # On Debian systems, the complete text of the GNU General Public # License, version 2, can be found in /usr/share/common-licenses/GPL-2. getres () { RESLINE="$(egrep "$EGREPLINE" "$LOGFILE" | head -1)" RES="$(echo "$RESLINE" | sed -e "$SEDLINE")" } DRIVER="$1" LOGFILE="$2" # stdout is, for now, unused STDOUT="$3" if [ -z "$DRIVER" -o -z "$LOGFILE" ]; then echo "Driver name and logfile must be specified on the command line." exit 1 fi # EGREPLINE must pull out only one line, which contains the res, from egrep. # SEDLINE must print the resolution from that line. if [ "$DRIVER" = "ati" -o "$DRIVER" = "atimisc" -o "$DRIVER" = "r128" -o \ "$DRIVER" = "radeon" ]; then EGREPLINE="\(--\) ATI\(.*\): .* panel \(ID .*\) detected." SEDLINE="s/(--) ATI([^)]*): \([^ ]*\) panel (ID [^)]*) detected./\1/;" getres if [ -z "$RES" ]; then EGREPLINE="\(II\) RADEON\(.*\): Panel [Ss]ize .*from .*: .*" SEDLINE="s/(II) RADEON([^)]*): Panel [Ss]ize .*from [^:]*: \(.*\)/\1/;" getres fi if [ -z "$RES" ]; then EGREPLINE="\(WW\) RADEON\(.*\): Panel size .*x.* is derived, this may not be correct." SEDLINE="s/(WW) RADEON([^)]*): Panel size \([^x]*\)x\([^ ]*\) is derived, this may not be correct./\1x\2/;" getres fi if [ -z "$RES" ]; then EGREPLINE="\(II\) R128\(.*\): Panel size: .*x.*" SEDLINE="s/(II) R128([^)]*): Panel size: \(.*\)/\1/;" getres fi elif [ "$DRIVER" = "i810" ]; then EGREPLINE="\(II\) I810\(.*\): Size of device LFP \(local flat panel\) is .* x .*" SEDLINE="s/(II) I810([^)]*): Size of device LFP (local flat panel) is \([^ ]*\) x \([^ ]*\)/\1x\2/;" getres elif [ "$DRIVER" = "intel" ]; then EGREPLINE="\(II\) intel\(.*\): Output LVDS using initial mode .*x.*" SEDLINE="s/(II) intel([^)]*): Output LVDS using initial mode \([^ ]*\)x\([^ ]*\)/\1x\2/;" getres elif [ "$DRIVER" = "savage" ]; then EGREPLINE="\(--\) SAVAGE\(.*\): .*.* .* LCD panel detected.*" SEDLINE="s/(--) SAVAGE([^)]*): \([^x]*\)x\([^x]*\) [^ ]* LCD panel detected.*$/\1x\2/;" getres # don't even ask. ubuntu #15231. RES="$(echo "$RES" | sed -e 's/1408x1050/1400x1050/;')" elif [ "$DRIVER" = "neomagic" ]; then EGREPLINE="\(--\) NEOMAGIC\(.*\): Panel is a .*x.* .* .* display" SEDLINE="s/(--) NEOMAGIC(.*): Panel is a \([^x]*\)x\([^ ]*\) [^ ]* .* display/\1x\2/;" getres elif [ "$DRIVER" = "nv" ]; then # the nv driver would ideally tell us this # ... and it does, when backported EGREPLINE="\(--\) NV\(.*\): Panel size is .* x .*" SEDLINE="s/(--) NV([^)]*): Panel size is \([^ ]*\) x \(.*\)/\1x\2/;" getres if [ -z "$RES" ]; then EGREPLINE="\(--\) NV\(.*\): Virtual size is .*x.* \(pitch .*\)" SEDLINE="s/(--) NV([^)]*): Virtual size is \([^x]*\)x\([^ ]*\) (pitch .*)/\1x\2/;" getres fi elif [ "$DRIVER" = "siliconmotion" ]; then EGREPLINE="\(II\) Silicon MotionDetected panel size via BIOS: .* x .*" SEDLINE="s/(II) Silicon MotionDetected panel size via BIOS: \([^ ]*\) x \([^ ]*\)/\1x\2/;" getres if [ -z "$RES" ]; then EGREPLINE="\(II\) Silicon Motion.* Panel Size = .*x.*" SEDLINE="s/(II) Silicon Motion[^ ]* Panel Size = \([^x]*\)x\([^ ]*\)/\1x\2/;" getres fi elif [ "$DRIVER" = "trident" ]; then EGREPLINE="\(--\) TRIDENT\(.*\): .* Panel .*x.* found" SEDLINE="s/(--) TRIDENT([^)]*): [^ ]* Panel \([^x]*\)x\([^ ]*\) found/\1x\2/;" getres elif [ "$DRIVER" = "via" ]; then EGREPLINE="\(II\) VIA\(.*\): ViaPanelGetIndex: index: .* (.*x.*)" SEDLINE="s/(II) VIA([^)]*): ViaPanelGetIndex: index: [^ ]* (\([^x]*\)x\([^)]*\))/\1x\2/;" getres if [ -z "$RES" ]; then EGREPLINE="\(II\) VIA\(.*\): Selected Panel Size is .*x.*" SEDLINE="s/(II) VIA([^)]*): Selected Panel Size is \([^x]*\)x\([^ ]*\)/\1x\2/;" getres fi elif [ "$DRIVER" = "chips" ]; then EGREPLINE="\(--\) CHIPS\(.*\): Display Size: x=.*; y=.*" SEDLINE="s/(--) CHIPS([^)]*): Display Size: x=\([^;]*\); y=\([^ ]*\)/\1x\2/;" getres elif [ "$DRIVER" = "vesa" ]; then EGREPLINE="\(--\) VESA\(.*\): Virtual size is .*x.*" SEDLINE="s/(--) VESA([^)]*): Virtual size is \([^x]*\)x\([^ ]*\).*/\1x\2/;" getres else exit 1 fi echo "$RES" xresprobe-0.4.24ubuntu9/bitdepth.sh0000755000000000000000000000317210242533543014202 0ustar #!/bin/sh # usage: bitdepth.sh driver logfile [stdout] # Copyright (C) 2005 Canonical Ltd. # Author: Daniel Stone # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License with # the Debian GNU/Linux distribution in file /usr/share/common-licenses/GPL; # if not, write to the Free Software Foundation, Inc., 59 Temple Place, # Suite 330, Boston, MA 02111-1307 USA # # On Debian systems, the complete text of the GNU General Public # License, version 2, can be found in /usr/share/common-licenses/GPL-2. DRIVER="$1" LOGFILE="$2" # stdout is, for now, unused STDOUT="$3" if [ -z "$DRIVER" -o -z "$LOGFILE" ]; then echo "Driver name and logfile must be specified on the command line." exit 1 fi if [ "$DRIVER" = "i810" ]; then if egrep -q "\(EE\) I810\(.*\): No Video BIOS modes for chosen depth." \ "$LOGFILE"; then # broken bios! word. if we don't have any 24bpp modes, just hope like # hell that 16bpp will work; some vendors ship bioses without 24bpp modes # in their vesa mode table. but sometimes this means we need to go to 32. FORCEDEPTH=16 fi else exit 1 fi if [ -n "$FORCEDEPTH" ]; then echo $FORCEDEPTH fi xresprobe-0.4.24ubuntu9/xorg.conf0000644000000000000000000000303310677032267013673 0ustar # bare-bones XFree86 config to start the server in probe-only mode Section "Files" FontPath "/usr/share/X11/fonts/misc" RgbPath "/etc/X11/rgb.txt" EndSection Section "ServerFlags" Option "AllowMouseOpenFail" EndSection Section "Module" Load "bitmap" Load "dbe" Load "ddc" Load "extmod" Load "freetype" Load "int10" Load "record" Load "vbe" EndSection Section "InputDevice" Identifier "Generic Keyboard" Driver "keyboard" Option "CoreKeyboard" Option "XkbRules" "xorg" Option "XkbModel" "pc104" Option "XkbLayout" "us" EndSection Section "InputDevice" Identifier "Generic Mouse" Driver "mouse" Option "CorePointer" Option "Device" "/dev/input/mice" Option "Protocol" "ImPS/2" EndSection Section "Device" Identifier "Generic Device" Driver "::DRIVER::" EndSection Section "Monitor" Identifier "Generic Monitor" Option "DPMS" EndSection Section "Screen" Identifier "Default Screen" Device "Generic Device" Monitor "Generic Monitor" DefaultDepth 24 SubSection "Display" Depth 1 Modes "1024x768" EndSubSection SubSection "Display" Depth 4 Modes "1024x768" EndSubSection SubSection "Display" Depth 8 Modes "1024x768" EndSubSection SubSection "Display" Depth 15 Modes "1024x768" EndSubSection SubSection "Display" Depth 16 Modes "1024x768" EndSubSection SubSection "Display" Depth 24 Modes "1024x768" EndSubSection EndSection Section "ServerLayout" Identifier "Default Layout" Screen "Default Screen" InputDevice "Generic Keyboard" InputDevice "Generic Mouse" EndSection xresprobe-0.4.24ubuntu9/ddcprobe/0000755000000000000000000000000011261766110013617 5ustar xresprobe-0.4.24ubuntu9/ddcprobe/bioscall.c0000644000000000000000000002147310214367723015566 0ustar #if defined (__i386__) #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "bioscall.h" #ident "$Id: bioscall.c,v 1.7 2003/02/11 14:47:38 notting Exp $" #define DFLAG 0x0400 #define IFLAG 0x0200 #define TFLAG 0x0100 #define SFLAG 0x0080 #define ZFLAG 0x0040 #define AFLAG 0x0010 #define PFLAG 0x0004 #define CFLAG 0x0001 /* Dump some of the interesting parts of a register struct to stdout. */ void dump_regs(struct vm86_regs *regs) { printf("ax = 0x%04lx\n", regs->eax & 0xffff); printf("bx = 0x%04lx\n", regs->ebx & 0xffff); printf("cx = 0x%04lx\n", regs->ecx & 0xffff); printf("dx = 0x%04lx\n", regs->edx & 0xffff); printf("cs = 0x%04x\n", regs->cs & 0xffff); printf("ip = 0x%08lx\n", regs->eip & 0xffffffff); printf("ss = 0x%04x\n", regs->ss & 0xffff); printf("sp = 0x%08lx\n", regs->esp & 0xffffffff); printf("%04x:%08lx = (%ld)\n", regs->cs & 0xffff, regs->eip, regs->cs * 16 + regs->eip); } /* Call vm86, but do I/O that gets trapped. We could skip vm86() altogether, but then I'm not trying to emulate an entire CPU here. Luckily, none of the I/O instructions (or push/pop) affect the flags, so we can leave them alone and just deal with performing the I/O operation that caused a return to 32-bit mode. */ void do_vm86(struct vm86_struct *vm, char *memory, unsigned stop_eip) { int ret; unsigned start_cs, start_eip; unsigned char *ip = NULL; /* Save the starting instruction address. */ start_cs = vm->regs.cs; start_eip = vm->regs.eip; /* We'll need to pass I/O through. PCI devices have higher addresses than we can get access to with ioperm(). */ if(iopl(3) != 0) { return; } /* Do it. */ ret = syscall(SYS_vm86old, vm); while((vm->regs.cs * 16 + vm->regs.eip) != (start_cs * 16 + stop_eip)) { ip = &memory[vm->regs.cs * 16 + vm->regs.eip]; #ifdef DEBUG2 printf("Unexpected return:\n"); dump_regs(&vm->regs); printf("Offending instructions: %02x %02x %02x %02x\n", ip[0], ip[1], ip[2], ip[3]); #endif switch(ip[0]) { case 0xe4: { /* in al, literal */ vm->regs.eax &= 0xffffff00; vm->regs.eax |= inb(ip[1]); vm->regs.eip += 2; break; } case 0xe6: { /* out al, literal */ outb(vm->regs.eax & 0xff, ip[1]); vm->regs.eip += 2; break; } case 0xec: { /* in al, dx */ vm->regs.eax &= 0xffffff00; vm->regs.eax |= inb(vm->regs.edx & 0xffff); vm->regs.eip++; break; } case 0xed: { /* in ax, dx */ vm->regs.eax &= 0xffff0000; vm->regs.eax |= inw(vm->regs.edx & 0xffff); vm->regs.eip++; break; } case 0xee: { /* out al, dx */ outb(vm->regs.eax & 0xff, vm->regs.edx & 0xffff); vm->regs.eip++; break; } case 0xef: { /* out ax, dx */ outw(vm->regs.eax & 0xffff, vm->regs.edx & 0xffff); vm->regs.eip++; break; } case 0x6c: { /* insb */ unsigned char *result = (unsigned char*) &memory[vm->regs.es*16 + vm->regs.edi]; *result = inb(vm->regs.edx & 0xffff); if(vm->regs.eflags & DFLAG) { vm->regs.edi -= 1; } else { vm->regs.edi += 1; } if(ip[-1] == 0xf3) { /* rep'ped */ vm->regs.ecx--; vm->regs.eip--; } else { vm->regs.eip++; } break; } case 0x6d: { /* insw */ u_int16_t *result = (u_int16_t*) &memory[vm->regs.es*16 + vm->regs.edi]; *result = inw(vm->regs.edx & 0xffff); if(vm->regs.eflags & DFLAG) { vm->regs.edi -= 2; } else { vm->regs.edi += 2; } if(ip[-1] == 0xf3) { /* rep'ped */ vm->regs.ecx--; vm->regs.eip--; } else { vm->regs.eip++; } break; } case 0x6e: { /* outsb */ unsigned char *result = (unsigned char*) &memory[vm->regs.es*16 + vm->regs.edi]; outb(*result, vm->regs.edx & 0xffff); if(vm->regs.eflags & DFLAG) { vm->regs.edi -= 1; } else { vm->regs.edi += 1; } if(ip[-1] == 0xf3) { /* rep'ped */ vm->regs.ecx--; vm->regs.eip--; } else { vm->regs.eip++; } break; } case 0x6f: { /* outsw */ u_int16_t *result = (u_int16_t*) &memory[vm->regs.es*16 + vm->regs.edi]; outw(*result, vm->regs.edx & 0xffff); if(vm->regs.eflags & DFLAG) { vm->regs.edi -= 2; } else { vm->regs.edi += 2; } if(ip[-1] == 0xf3) { /* rep'ped */ vm->regs.ecx--; vm->regs.eip--; } else { vm->regs.eip++; } break; } case 0xfa: { /* cli */ vm->regs.eflags &= ~(IFLAG); vm->regs.eip++; break; } case 0xfb: { /* sti */ vm->regs.eflags |= ~(IFLAG); vm->regs.eip++; break; } case 0x9c: { /* pushf */ vm->regs.esp -= 2; *(u_int16_t*) &memory[vm->regs.ss * 16 + vm->regs.esp] = vm->regs.eflags & 0xffff; vm->regs.eip++; break; } case 0x9d: { /* popf */ vm->regs.esp += 2; vm->regs.eflags &= 0xffff0000; vm->regs.eflags |= *(u_int16_t*) &memory[vm->regs.ss * 16 + vm->regs.esp]; vm->regs.eip++; break; } case 0xf0: { /* lock prefix */ /* ignore it */ vm->regs.eip++; break; } case 0x66: { /* 32-bit extension prefix. Valid, even in v86 mode. Weird. */ vm->regs.eip++; ip++; switch(ip[0]) { case 0xed: { /* in eax, dx */ vm->regs.eax = inl(vm->regs.edx & 0xffff); vm->regs.eip++; break; } case 0xef: { /* out eax, dx */ outl(vm->regs.eax, vm->regs.edx & 0xffff); vm->regs.eip++; break; } default: { fprintf(stderr, "unhandled " "32-bit opcode\n"); exit(1); } } break; } case 0x55: { /* push bp */ vm->regs.esp -= 2; *(u_int16_t*) &memory[vm->regs.ss * 16 + vm->regs.esp] = vm->regs.ebp & 0xffff; vm->regs.eip++; break; } case 0x5d: { /* pop bp */ vm->regs.ebp &= 0xffff0000; vm->regs.ebp |= *(u_int16_t*) &memory[vm->regs.ss*16 + vm->regs.esp]; vm->regs.esp += 2; vm->regs.eip++; break; } case 0x59: { /* pop cx -- Banshee */ vm->regs.ecx &= 0xffff0000; vm->regs.ecx |= *(u_int16_t*) &memory[vm->regs.ss*16 + vm->regs.esp]; vm->regs.esp += 2; vm->regs.eip++; } case 0xc3: { /* ret near, just pop ip */ vm->regs.eip &= 0xffff0000; vm->regs.eip |= *(u_int16_t*) &memory[vm->regs.ss*16 + vm->regs.esp]; vm->regs.esp += 2; break; } case 0xcb: { /* ret far, pop both ip and cs */ vm->regs.eip &= 0xffff0000; vm->regs.eip |= *(u_int16_t*) &memory[vm->regs.ss*16 + vm->regs.esp]; vm->regs.esp += 2; vm->regs.cs = *(u_int16_t*) &memory[vm->regs.ss*16 + vm->regs.esp]; vm->regs.esp += 2; break; } default: { fprintf(stderr, "Unexpected stop!\n"); dump_regs(&vm->regs); printf("Offending instructions: %02x %02x %02x %02x\n", ip[0], ip[1], ip[2], ip[3]); exit(1); } } ip = &memory[vm->regs.cs * 16 + vm->regs.eip]; #ifdef DEBUG printf("Resuming execution:\n"); dump_regs(&vm->regs); printf("Offending instructions: %02x %02x %02x %02x\n", ip[0], ip[1], ip[2], ip[3]); #endif ret = syscall(SYS_vm86old, vm); } #ifdef DEBUG printf("Reached stopping point, returning.\n"); #endif return; } /* Get a snapshot of the first megabyte of memory for use with vm86. */ unsigned char *vm86_ram_alloc() { unsigned char *memory; int fd; /* Grab address 0 for this process. mmap() 1 megabyte + 64k HMA */ memory = mmap(0, 0x110000, PROT_READ | PROT_EXEC | PROT_WRITE, MAP_PRIVATE | MAP_FIXED | MAP_ANON, -1, 0x00000); if(memory == MAP_FAILED) { perror("error mmap()ing memory for the BIOS"); return MAP_FAILED; } /* Copy the low megabyte to our mmap()'ed buffer. */ fd = open("/dev/mem", O_RDONLY); if(fd == -1) { perror("reading kernel memory"); return MAP_FAILED; } // read(fd, memory, 0x110000); lseek(fd, 0, SEEK_SET); read(fd, &memory[0], 0x10000); lseek(fd, 0xa0000, SEEK_SET); read(fd, &memory[0xa0000], 0x50000); close(fd); return memory; } void vm86_ram_free(unsigned char *ram) { munmap(ram, 0x110000); } void bioscall(unsigned char int_no, struct vm86_regs *regs, unsigned char *mem) { unsigned char call[] = {0xcd, int_no, 0xcd, 0x09}; struct vm86_struct vm; memset(&vm, 0, sizeof(vm)); memcpy(&vm.regs, regs, sizeof(vm.regs)); vm.regs.cs = BIOSCALL_START_SEG; vm.regs.eip = BIOSCALL_START_OFS; vm.regs.ss = BIOSCALL_START_SEG; vm.regs.esp = 0xfff0 - BIOSCALL_START_OFS; vm.regs.eflags = VM_MASK | IOPL_MASK; memcpy(&mem[BIOSCALL_START_SEG * 16 + BIOSCALL_START_OFS], call, sizeof(call)); do_vm86(&vm, mem, BIOSCALL_START_OFS + sizeof(call)); memcpy(regs, &vm.regs, sizeof(vm.regs)); } #endif /* __i386__ */ xresprobe-0.4.24ubuntu9/ddcprobe/minifind.c0000644000000000000000000000370210214367723015566 0ustar /* minifind.c -- simple find library * * Copyright (c) 2002 Terra Soft Solutions, Inc. * Written by Dan Burcaw * * This software may be freely redistributed under the terms of the GNU * library public license. * * You should have received a copy of the GNU Library Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * */ #include "minifind.h" // insert a node at head of linked-list void insert_node(struct pathNode *n, char *path) { struct pathNode *new = (struct pathNode *) malloc(sizeof(struct pathNode)); new->path = path; new->next = n->next; n->next = new; } // return input strip less last character char *stripLastChar(char *in) { char *out = malloc(sizeof(char)*strlen(in)); snprintf(out, strlen(in) - 1, "%s", in); return out; } // do the work char *minifind(char *dir, char *search, struct findNode *list) { char *d = NULL; int n; struct dirent **namelist; struct stat buf; if (dir[strlen(dir)-1] == '/') dir = stripLastChar(dir); // check is there is an exact filematch to dir // when search is not specified if (search == NULL) { if (lstat(dir, &buf) == 0) insert_node(list->result, dir); return 0; } n = scandir(dir, &namelist, 0, alphasort); if (n >= 0) { while (n--) { d = malloc(sizeof(char) * (strlen(dir) \ + strlen(namelist[n]->d_name)+1)); sprintf(d, "%s/%s", dir, namelist[n]->d_name); if (strstr(namelist[n]->d_name, search)) insert_node(list->result, d); if ((lstat(d, &buf) == 0) && S_ISDIR(buf.st_mode)) { if (strcmp(namelist[n]->d_name, ".") && strcmp(namelist[n]->d_name, "..")) d = minifind(d, search, list); } free(namelist[n]); } free(namelist); return d; } return 0; } xresprobe-0.4.24ubuntu9/ddcprobe/ddcxinfo.c0000644000000000000000000000406510214367723015572 0ustar #include #include #include #include "common.h" #ident "$Id: ddcxinfo.c,v 1.8 2003/02/11 14:47:38 notting Exp $" int main(int argc, char **argv) { int i, j; unsigned char hmin = -1, hmax = -1, vmin = -1, vmax = -1; if(argc < 2) { char *p = argv[0]; if(strchr(p, '/')) { p = strchr(p, '/'); p++; } fprintf(stderr,"syntax: %s [-hsync] [-vsync] [-modelines]\n",p); exit(1); } for(i = 1; i < argc; i++) { if((strcmp(argv[i], "-hsync") == 0) || (strcmp(argv[i], "-vsync") == 0)) { get_edid_ranges(&hmin, &hmax, &vmin, &vmax); if(!hmin && !hmax && !vmin && !vmax) { struct modeline* modelines; modelines = get_edid_modelines(); for(j = 0; modelines && (modelines[j].refresh != 0); j++) { if(hmin == 0) hmin = modelines[j].hfreq; /* guess */ if(modelines[j].hfreq) hmin = (hmin < modelines[j].hfreq) ? hmin : modelines[j].hfreq; if(modelines[j].hfreq) hmax = (hmax > modelines[j].hfreq) ? hmax : modelines[j].hfreq; if(vmin == 0) vmin = modelines[j].vfreq; if(modelines[j].vfreq) vmin = (vmin < modelines[j].vfreq) ? vmin : modelines[j].vfreq; if(modelines[j].vfreq) vmax = (vmax > modelines[j].vfreq) ? vmax : modelines[j].vfreq; } } } if(strcmp(argv[i], "-hsync") == 0) { printf("%d-%d\n", hmin, hmax); } if(strcmp(argv[i], "-vsync") == 0) { printf("%d-%d\n", vmin, vmax); } if(strcmp(argv[i], "-modelines") == 0) { struct modeline* modelines; modelines = get_edid_modelines(); for(j=0; modelines && (modelines[j].refresh != 0); j++){ if(modelines[j].modeline) { printf("# %dx%d, %1.1f%sHz; hfreq=%f, vfreq=%f\n%s\n", modelines[j].width, modelines[j].height, modelines[j].refresh, modelines[j].interlaced?"i":"", modelines[j].hfreq, modelines[j].vfreq, modelines[j].modeline); } } if(modelines) { free(modelines); } else { return 1; } } } return 0; } xresprobe-0.4.24ubuntu9/ddcprobe/vbe.c0000644000000000000000000002274410410136571014545 0ustar #if defined (__i386__) || defined (__amd64__) #include #include #include #include #include #include #include #include #include #include #include "common.h" #include "include/lrmi.h" #include "vbe.h" #ident "$Id: vbe.c,v 1.10 2003/02/11 14:47:38 notting Exp $" /* Return information about a particular video mode. */ struct vbe_mode_info *vbe_get_mode_info(u_int16_t mode) { struct LRMI_regs regs; char *mem; struct vbe_mode_info *ret = NULL; /* Initialize LRMI. */ if(LRMI_init() == 0) { return NULL; } /* Allocate a chunk of memory. */ mem = LRMI_alloc_real(sizeof(struct vbe_mode_info)); if(mem == NULL) { return NULL; } memset(mem, 0, sizeof(struct vbe_mode_info)); memset(®s, 0, sizeof(regs)); regs.eax = 0x4f01; regs.ecx = mode; regs.es = (u_int32_t)(mem - LRMI_base_addr()) >> 4; regs.edi = (u_int32_t)(mem - LRMI_base_addr()) & 0x0f; /* Do it. */ iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { LRMI_free_real(mem); return NULL; } /* Check for successful return. */ if((regs.eax & 0xffff) != 0x004f) { LRMI_free_real(mem); return NULL; } /* Get memory for return. */ ret = malloc(sizeof(struct vbe_mode_info)); if(ret == NULL) { LRMI_free_real(mem); return NULL; } /* Copy the buffer for return. */ memcpy(ret, mem, sizeof(struct vbe_mode_info)); /* Clean up and return. */ LRMI_free_real(mem); return ret; } /* Get VBE info. */ struct vbe_parent_info *vbe_get_vbe_info() { struct LRMI_regs regs; unsigned char *mem; struct vbe_parent_info *ret = NULL; int i; /* Initialize LRMI. */ if(LRMI_init() == 0) { return NULL; } /* Allocate a chunk of memory. */ mem = LRMI_alloc_real(sizeof(struct vbe_mode_info)); if(mem == NULL) { return NULL; } memset(mem, 0, sizeof(struct vbe_mode_info)); /* Set up registers for the interrupt call. */ memset(®s, 0, sizeof(regs)); regs.eax = 0x4f00; regs.es = (u_int32_t)(mem - LRMI_base_addr()) >> 4; regs.edi = (u_int32_t)(mem - LRMI_base_addr()) & 0x0f; memcpy(mem, "VBE2", 4); /* Do it. */ iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { LRMI_free_real(mem); return NULL; } /* Check for successful return code. */ if((regs.eax & 0xffff) != 0x004f) { LRMI_free_real(mem); return NULL; } /* Get memory to return the information. */ ret = malloc(sizeof(struct vbe_parent_info)); if(ret == NULL) { LRMI_free_real(mem); return NULL; } memcpy(&ret->vbe, mem, sizeof(struct vbe_info)); /* Set up pointers to usable memory. */ ret->mode_list_list = (u_int16_t*) (LRMI_base_addr() + (ret->vbe.mode_list_addr.seg << 4) + (ret->vbe.mode_list_addr.ofs)); ret->oem_name_string = (char*) (LRMI_base_addr() + (ret->vbe.oem_name_addr.seg << 4) + (ret->vbe.oem_name_addr.ofs)); /* Snip, snip. */ mem = strdup(ret->oem_name_string); /* leak */ while(((i = strlen(mem)) > 0) && isspace(mem[i - 1])) { mem[i - 1] = '\0'; } ret->oem_name_string = mem; /* Set up pointers for VESA 2.0+ strings. */ if(ret->vbe.version[1] >= 2) { /* Vendor name. */ ret->vendor_name_string = (char*) (LRMI_base_addr() + (ret->vbe.vendor_name_addr.seg << 4) + (ret->vbe.vendor_name_addr.ofs)); mem = strdup(ret->vendor_name_string); /* leak */ while(((i = strlen(mem)) > 0) && isspace(mem[i - 1])) { mem[i - 1] = '\0'; } ret->vendor_name_string = mem; /* Product name. */ ret->product_name_string = (char*) (LRMI_base_addr() + (ret->vbe.product_name_addr.seg << 4) + (ret->vbe.product_name_addr.ofs)); mem = strdup(ret->product_name_string); /* leak */ while(((i = strlen(mem)) > 0) && isspace(mem[i - 1])) { mem[i - 1] = '\0'; } ret->product_name_string = mem; /* Product revision. */ ret->product_revision_string = (char*) (LRMI_base_addr() + (ret->vbe.product_revision_addr.seg << 4) + (ret->vbe.product_revision_addr.ofs)); mem = strdup(ret->product_revision_string); /* leak */ while(((i = strlen(mem)) > 0) && isspace(mem[i - 1])) { mem[i - 1] = '\0'; } ret->product_revision_string = mem; } /* Cleanup. */ LRMI_free_real(mem); return ret; } /* Check if EDID queries are suorted. */ int get_edid_supported() { struct LRMI_regs regs; int ret = 0; /* Initialize LRMI. */ if(LRMI_init() == 0) { return 0; } memset(®s, 0, sizeof(regs)); regs.eax = 0x4f15; /* VBE DDC service */ regs.ebx = 0x0000; /* SERVICE_REPORT_DDC */ regs.es = 0x3000; regs.edi = 0x3000; /* Do it. */ iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { return 0; } /* Check for successful return. */ if((regs.eax & 0xff) == 0x4f) { /* Supported. */ ret = 1; } else { /* Not supported. */ ret = 0; } /* Clean up and return. */ return ret; } /* Get EDID info. */ struct edid1_info *get_edid_info() { struct LRMI_regs regs; unsigned char *mem; struct edid1_info *ret = NULL; u_int16_t man; /* Initialize LRMI. */ if(LRMI_init() == 0) { return NULL; } /* Allocate a chunk of memory. */ mem = LRMI_alloc_real(sizeof(struct edid1_info)); if(mem == NULL) { return NULL; } memset(mem, 0, sizeof(struct edid1_info)); memset(®s, 0, sizeof(regs)); regs.eax = 0x4f15; regs.ebx = 0x0001; regs.es = (u_int32_t)(mem) >> 4; regs.edi = (u_int32_t)(mem) & 0x0f; /* Do it. */ iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { LRMI_free_real(mem); return NULL; } #if 0 /* Check for successful return. */ if((regs.eax & 0xffff) != 0x004f) { LRMI_free_real(mem); return NULL; } #elseif /* Check for successful return. */ if((regs.eax & 0xff) != 0x4f) { LRMI_free_real(mem); return NULL; } #endif /* Get memory for return. */ ret = malloc(sizeof(struct edid1_info)); if(ret == NULL) { LRMI_free_real(mem); return NULL; } /* Copy the buffer for return. */ memcpy(ret, mem, sizeof(struct edid1_info)); memcpy(&man, &ret->manufacturer_name, 2); man = ntohs(man); memcpy(&ret->manufacturer_name, &man, 2); LRMI_free_real(mem); return ret; } /* Figure out what the current video mode is. */ int32_t vbe_get_mode() { struct LRMI_regs regs; int32_t ret = -1; /* Initialize LRMI. */ if(LRMI_init() == 0) { return -1; } memset(®s, 0, sizeof(regs)); regs.eax = 0x4f03; /* Do it. */ iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { return -1; } /* Save the returned value. */ if((regs.eax & 0xffff) == 0x004f) { ret = regs.ebx & 0xffff; } else { ret = -1; } /* Clean up and return. */ return ret; } /* Set the video mode. */ void vbe_set_mode(u_int16_t mode) { struct LRMI_regs regs; /* Initialize LRMI. */ if(LRMI_init() == 0) { return; } memset(®s, 0, sizeof(regs)); regs.eax = 0x4f02; regs.ebx = mode; /* Do it. */ iopl(3); ioperm(0, 0x400, 1); LRMI_int(0x10, ®s); /* Return. */ return; } const void *vbe_save_svga_state() { struct LRMI_regs regs; unsigned char *mem; u_int16_t block_size; void *data; /* Initialize LRMI. */ if(LRMI_init() == 0) { return NULL; } memset(®s, 0, sizeof(regs)); regs.eax = 0x4f04; regs.ecx = 0xffff; regs.edx = 0; iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { return NULL; } if((regs.eax & 0xff) != 0x4f) { fprintf(stderr, "Get SuperVGA Video State not supported.\n"); return NULL; } if((regs.eax & 0xffff) != 0x004f) { fprintf(stderr, "Get SuperVGA Video State Info failed.\n"); return NULL; } block_size = 64 * (regs.ebx & 0xffff); /* Allocate a chunk of memory. */ mem = LRMI_alloc_real(block_size); if(mem == NULL) { return NULL; } memset(mem, 0, sizeof(block_size)); memset(®s, 0, sizeof(regs)); regs.eax = 0x4f04; regs.ecx = 0x000f; regs.edx = 0x0001; regs.es = (u_int32_t)(mem) >> 4; regs.ebx = (u_int32_t)(mem) & 0x0f; memset(mem, 0, block_size); iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { LRMI_free_real(mem); return NULL; } if((regs.eax & 0xffff) != 0x004f) { fprintf(stderr, "Get SuperVGA Video State Save failed.\n"); return NULL; } data = malloc(block_size); if(data == NULL) { LRMI_free_real(mem); return NULL; } /* Clean up and return. */ memcpy(data, mem, block_size); LRMI_free_real(mem); return data; } void vbe_restore_svga_state(const void *state) { struct LRMI_regs regs; unsigned char *mem; u_int16_t block_size; /* Initialize LRMI. */ if(LRMI_init() == 0) { return; } memset(®s, 0, sizeof(regs)); regs.eax = 0x4f04; regs.ecx = 0x000f; regs.edx = 0; /* Find out how much memory we need. */ iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { return; } if((regs.eax & 0xff) != 0x4f) { fprintf(stderr, "Get SuperVGA Video State not supported.\n"); return; } if((regs.eax & 0xffff) != 0x004f) { fprintf(stderr, "Get SuperVGA Video State Info failed.\n"); return; } block_size = 64 * (regs.ebx & 0xffff); /* Allocate a chunk of memory. */ mem = LRMI_alloc_real(block_size); if(mem == NULL) { return; } memset(mem, 0, sizeof(block_size)); memset(®s, 0, sizeof(regs)); regs.eax = 0x4f04; regs.ecx = 0x000f; regs.edx = 0x0002; regs.es = 0x2000; regs.ebx = 0x0000; memcpy(mem, state, block_size); iopl(3); ioperm(0, 0x400, 1); if(LRMI_int(0x10, ®s) == 0) { LRMI_free_real(mem); return; } if((regs.eax & 0xffff) != 0x004f) { fprintf(stderr, "Get SuperVGA Video State Restore failed.\n"); return; } } #endif /* __i386__ */ xresprobe-0.4.24ubuntu9/ddcprobe/of.c0000644000000000000000000000721310410136571014367 0ustar #ifdef __powerpc__ #include #include #include #include #include #include #include #include #include #include #include #include #include "common.h" #include "minifind.h" /* misnomer */ struct vbe_parent_info *vbe_get_vbe_info() { struct vbe_parent_info *ret = NULL; struct fb_fix_screeninfo fix; unsigned char *mem; int rc = 0; int fd, i; if (!rc && !(fd = open("/dev/fb0", O_RDONLY))) { rc = 1; fprintf(stderr, "Unable to open /dev/fb0. Exiting.\n"); } if ((!rc) && (ioctl(fd, FBIOGET_FSCREENINFO, &fix))) { rc = 1; fprintf(stderr, "Framebuffer ioctl failed. Exiting.\n"); } close(fd); if (!rc) { // Note: if OFfb, vram info is unreliable! if (strcmp(fix.id, "OFfb")) { ret = malloc(sizeof(struct vbe_parent_info)); mem = strdup(fix.id); while(((i = strlen(mem)) > 0) && isspace(mem[i - 1])) { mem[i - 1] = '\0'; } ret->oem_name_string = mem; ret->product_name_string = NULL; ret->vendor_name_string = NULL; ret->product_revision_string = NULL; ret->vbe.memory_size = fix.smem_len/1024; } } return ret; } int get_edid_supported() { int ret = 0; struct findNode *list; struct pathNode *n; list = (struct findNode *) malloc(sizeof(struct findNode)); list->result = (struct pathNode *) malloc(sizeof(struct pathNode)); list->result->path = NULL; list->result->next = list->result; minifind("/proc/device-tree", "EDID", list); /* Supported */ for (n = list->result->next; n != list->result; n = n->next) ret = 1; /* If there is no EDID in /proc/device-tree provided by the OF, maybe * some fbdev driver (like radeonfb) provides the info in /sys */ if (ret == 0) { minifind("/sys", "edid1", list); for (n = list->result->next; n != list->result; n = n->next) ret = 1; } /* Clean up and return. */ return ret; } /* Get EDID info. */ struct edid1_info *get_edid_info() { unsigned char *mem; struct edid1_info *ret = NULL; struct pathNode *n; struct findNode *list; u_int16_t man; unsigned char edid[0x80]; FILE* edid_file = NULL; char *path = NULL; list = (struct findNode *) malloc(sizeof(struct findNode)); list->result = (struct pathNode *) malloc(sizeof(struct pathNode)); list->result->path = NULL; list->result->next = list->result; minifind("/proc/device-tree", "EDID", list); for (n = list->result->next; n != list->result; n = n->next) { path = n->path; break; } /* If there is no EDID in /proc/device-tree provided by the OF, maybe * some fbdev driver (like radeonfb) provides the info in /sys */ if (!path) { minifind("/sys", "edid1", list); for (n = list->result->next; n != list->result; n = n->next) { path = n->path; break; } } if (path) edid_file = fopen(path, "rb" ); if (!edid_file) return NULL; if (fread(edid, sizeof(unsigned char), 0x80, edid_file) != 0x80) return NULL; fclose(edid_file); mem = malloc(sizeof(struct edid1_info)); if(mem == NULL) { return NULL; } memcpy(mem, edid, 0x80); /* Get memory for return. */ ret = malloc(sizeof(struct edid1_info)); if(ret == NULL) { free(mem); return NULL; } /* Copy the buffer for return. */ memcpy(ret, mem, sizeof(struct edid1_info)); memcpy(&man, &ret->manufacturer_name, 2); man = ntohs(man); memcpy(&ret->manufacturer_name, &man, 2); free(mem); return ret; } #endif /* __powerpc__ */ xresprobe-0.4.24ubuntu9/ddcprobe/Makefile0000644000000000000000000000317410410136571015261 0ustar ARCH := $(patsubst i%86,i386,$(shell uname -m)) ARCH := $(patsubst sparc%,sparc,$(ARCH)) ARCH := $(patsubst ppc%,ppc,$(ARCH)) CC = gcc CFLAGS = -W -Wall -g -O2 #-DDEBUG TARGETS = ddcprobe ddcxinfo DDC_OBJS = vesamode.o common.o DDC_LIBS = ifeq ($(findstring $(ARCH),i386), $(ARCH)) TARGETS += svgamodes modetest libvbe.a DDC_OBJS += x86-common.o lrmi.o vbe.o else ifeq ($(findstring $(ARCH),x86_64), $(ARCH)) DDC_OBJS += x86-common.o vbe.o thunk.o x86emu/libx86emu.a else ifeq ($(ARCH),ppc) DDC_OBJS += of.o minifind.o else DDC_OBJS += stub.o endif endif endif ifeq (.depend,$(wildcard .depend)) TARGET=all else TARGET=depend all endif everything: $(TARGET) all: $(TARGETS) install: $(TARGETS) mkdir -p $(DESTDIR)/usr/sbin cp -a ddcprobe $(DESTDIR)/usr/sbin/ddcprobe # i386 and ppc targets ddcprobe: $(DDC_OBJS) ddcprobe.o $(CC) $(CFLAGS) -o ddcprobe $(DDC_OBJS) ddcprobe.o $(DDC_LIBS) ddcxinfo: $(DDC_OBJS) ddcxinfo.o $(CC) $(CFLAGS) -o ddcxinfo $(DDC_OBJS) ddcxinfo.o $(DDC_LIBS) x86emu/libx86emu.a: make -C x86emu libx86emu.a # i386 targets svgamodes: x86-common.o lrmi.o vesamode.o vbe.o svgamodes.o modetest: x86-common.o lrmi.o vesamode.o vbe.o modetest.o libvbe.a: x86-common.o lrmi.o vesamode.o vbe.o $(AR) cru $@ $^ install-lib: $(prefix)/include/vbe.h $(prefix)/lib/libvbe.a $(prefix)/include/vbe.h: install -m 644 vbe.h $(prefix)/include/vbe.h $(prefix)/lib/libvbe.a: install -m 644 libvbe.a $(prefix)/lib/libvbe.a clean: $(RM) $(TARGETS) *.o .depend core make -C x86emu clean depend: $(CPP) -M $(CFLAGS) *.c > .depend ifeq (.depend,$(wildcard .depend)) include .depend endif xresprobe-0.4.24ubuntu9/ddcprobe/vesamode.h0000644000000000000000000000116710214367723015604 0ustar #ifndef vesamode_h #define vesamode_h #include #ident "$Id: vesamode.h,v 1.1 1999/08/24 01:08:47 nalin Exp $" typedef enum { hsync_neg = 0, hsync_pos } hsync_t; typedef enum { vsync_neg = 0, vsync_pos } vsync_t; struct vesa_mode_t { u_int16_t number; u_int16_t x, y; u_int32_t colors; const char *text; const char *modeline; }; struct vesa_timing_t { u_int16_t x, y; float refresh; float dotclock; u_int16_t timings[8]; hsync_t hsync; vsync_t vsync; float hfreq; float vfreq; }; extern struct vesa_mode_t known_vesa_modes[]; extern struct vesa_timing_t known_vesa_timings[]; #endif /* vesamode_h */ xresprobe-0.4.24ubuntu9/ddcprobe/lrmi.h0000644000000000000000000000320110214367723014733 0ustar /* Linux Real Mode Interface - A library of DPMI-like functions for Linux. Copyright (C) 1998 by Josh Vanderhoof You are free to distribute and modify this file, as long as you do not remove this copyright notice and clearly label modified versions as being modified. This software has NO WARRANTY. Use it at your own risk. */ #ifndef LRMI_H #define LRMI_H struct LRMI_regs { unsigned int edi; unsigned int esi; unsigned int ebp; unsigned int reserved; unsigned int ebx; unsigned int edx; unsigned int ecx; unsigned int eax; unsigned short int flags; unsigned short int es; unsigned short int ds; unsigned short int fs; unsigned short int gs; unsigned short int ip; unsigned short int cs; unsigned short int sp; unsigned short int ss; }; #ifndef LRMI_PREFIX #define LRMI_PREFIX LRMI_ #endif #define LRMI_CONCAT2(a, b) a ## b #define LRMI_CONCAT(a, b) LRMI_CONCAT2(a, b) #define LRMI_MAKENAME(a) LRMI_CONCAT(LRMI_PREFIX, a) /* Initialize returns 1 if sucessful, 0 for failure */ #define LRMI_init LRMI_MAKENAME(init) int LRMI_init(void); /* Simulate a 16 bit far call returns 1 if sucessful, 0 for failure */ #define LRMI_call LRMI_MAKENAME(call) int LRMI_call(struct LRMI_regs *r); /* Simulate a 16 bit interrupt returns 1 if sucessful, 0 for failure */ #define LRMI_int LRMI_MAKENAME(int) int LRMI_int(int interrupt, struct LRMI_regs *r); /* Allocate real mode memory The returned block is paragraph (16 byte) aligned */ #define LRMI_alloc_real LRMI_MAKENAME(alloc_real) void * LRMI_alloc_real(int size); /* Free real mode memory */ #define LRMI_free_real LRMI_MAKENAME(free_real) void LRMI_free_real(void *m); #endif xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/0000755000000000000000000000000010415741443014755 5ustar xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/makefile.linux0000644000000000000000000000375510410136571017620 0ustar ############################################################################# # # Realmode X86 Emulator Library # # Copyright (C) 1996-1999 SciTech Software, Inc. # # ======================================================================== # # Permission to use, copy, modify, distribute, and sell this software and # its documentation for any purpose is hereby granted without fee, # provided that the above copyright notice appear in all copies and that # both that copyright notice and this permission notice appear in # supporting documentation, and that the name of the authors not be used # in advertising or publicity pertaining to distribution of the software # without specific, written prior permission. The authors makes no # representations about the suitability of this software for any purpose. # It is provided "as is" without express or implied warranty. # # THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, # INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO # EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR # CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF # USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR # OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR # PERFORMANCE OF THIS SOFTWARE. # # ======================================================================== # # Descripton: Linux specific makefile for the x86emu library. # ############################################################################# TARGETLIB = libx86emu.a OBJS=\ debug.o \ decode.o \ fpu.o \ ops.o \ ops2.o \ prim_ops.o \ sys.o all: $(TARGETLIB) $(TARGETLIB): $(OBJS) ar rv $(TARGETLIB) $(OBJS) INCS = -I. -Ix86emu -I../../include -I../x86emu_include CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -DDEBUG .c.o: gcc -g -O -Wall -c $(CFLAGS) $(INCS) $*.c .cpp.o: gcc -c $(CFLAGS) $(INCS) $*.cpp distclean: clean clean: rm -f *.a *.o install: xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/debug.c0000644000000000000000000002716510410136571016215 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: This file contains the code to handle debugging of the * emulator. * ****************************************************************************/ #include "x86emu/x86emui.h" #ifdef IN_MODULE #include "xf86_ansic.h" #else #include #include #endif /*----------------------------- Implementation ----------------------------*/ #ifdef DEBUG static void print_encoded_bytes (u16 s, u16 o); static void print_decoded_instruction (void); static int parse_line (char *s, int *ps, int *n); /* should look something like debug's output. */ void X86EMU_trace_regs (void) { return; if (DEBUG_TRACE()) { x86emu_dump_regs(); } if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { printf("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); print_decoded_instruction(); } printf("%04x:%04x \n",M.x86.saved_cs, M.x86.saved_ip); print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); print_decoded_instruction(); } void X86EMU_trace_xregs (void) { if (DEBUG_TRACE()) { x86emu_dump_xregs(); } } void x86emu_just_disassemble (void) { /* * This routine called if the flag DEBUG_DISASSEMBLE is set kind * of a hack! */ printf("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); print_decoded_instruction(); } static void disassemble_forward (u16 seg, u16 off, int n) { X86EMU_sysEnv tregs; int i; u8 op1; /* * hack, hack, hack. What we do is use the exact machinery set up * for execution, except that now there is an additional state * flag associated with the "execution", and we are using a copy * of the register struct. All the major opcodes, once fully * decoded, have the following two steps: TRACE_REGS(r,m); * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to * the preprocessor. The TRACE_REGS macro expands to: * * if (debug&DEBUG_DISASSEMBLE) * {just_disassemble(); goto EndOfInstruction;} * if (debug&DEBUG_TRACE) trace_regs(r,m); * * ...... and at the last line of the routine. * * EndOfInstruction: end_instr(); * * Up to the point where TRACE_REG is expanded, NO modifications * are done to any register EXCEPT the IP register, for fetch and * decoding purposes. * * This was done for an entirely different reason, but makes a * nice way to get the system to help debug codes. */ tregs = M; tregs.x86.R_IP = off; tregs.x86.R_CS = seg; /* reset the decoding buffers */ tregs.x86.enc_str_pos = 0; tregs.x86.enc_pos = 0; /* turn on the "disassemble only, no execute" flag */ tregs.x86.debug |= DEBUG_DISASSEMBLE_F; /* DUMP NEXT n instructions to screen in straight_line fashion */ /* * This looks like the regular instruction fetch stream, except * that when this occurs, each fetched opcode, upon seeing the * DEBUG_DISASSEMBLE flag set, exits immediately after decoding * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! * Note the use of a copy of the register structure... */ for (i=0; i 256) return; seg = fetch_data_word_abs(0,iv*4); off = fetch_data_word_abs(0,iv*4+2); printf("%04x:%04x ", seg, off); } void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) { u32 start = off & 0xfffffff0; u32 end = (off+16) & 0xfffffff0; u32 i; u32 current; current = start; while (end <= off + amt) { printf("%04x:%04x ", seg, start); for (i=start; i< off; i++) printf(" "); for ( ; i< end; i++) printf("%02x ", fetch_data_byte_abs(seg,i)); printf("\n"); start = end; end = start + 16; } } void x86emu_single_step (void) { char s[1024]; int ps[10]; int ntok; int cmd; int done; int segment; int offset; static int breakpoint; static int noDecode = 1; char *p; if (DEBUG_BREAK()) { if (M.x86.saved_ip != breakpoint) { return; } else { M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; M.x86.debug |= DEBUG_TRACE_F; M.x86.debug &= ~DEBUG_BREAK_F; print_decoded_instruction (); X86EMU_trace_regs(); } } done=0; offset = M.x86.saved_ip; while (!done) { printf("-"); p = fgets(s, 1023, stdin); cmd = parse_line(s, ps, &ntok); switch(cmd) { case 'u': disassemble_forward(M.x86.saved_cs,(u16)offset,10); break; case 'd': if (ntok == 2) { segment = M.x86.saved_cs; offset = ps[1]; X86EMU_dump_memory(segment,(u16)offset,16); offset += 16; } else if (ntok == 3) { segment = ps[1]; offset = ps[2]; X86EMU_dump_memory(segment,(u16)offset,16); offset += 16; } else { segment = M.x86.saved_cs; X86EMU_dump_memory(segment,(u16)offset,16); offset += 16; } break; case 'c': M.x86.debug ^= DEBUG_TRACECALL_F; break; case 's': M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; break; case 'r': X86EMU_trace_regs(); break; case 'x': X86EMU_trace_xregs(); break; case 'g': if (ntok == 2) { breakpoint = ps[1]; if (noDecode) { M.x86.debug |= DEBUG_DECODE_NOPRINT_F; } else { M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; } M.x86.debug &= ~DEBUG_TRACE_F; M.x86.debug |= DEBUG_BREAK_F; done = 1; } break; case 'q': exit(1); case 'P': noDecode = (noDecode)?0:1; printf("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); break; case 't': case 0: done = 1; break; } } } int X86EMU_trace_on(void) { return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; } int X86EMU_trace_off(void) { return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); } static int parse_line (char *s, int *ps, int *n) { int cmd; *n = 0; while(*s == ' ' || *s == '\t') s++; ps[*n] = *s; switch (*s) { case '\n': *n += 1; return 0; default: cmd = *s; *n += 1; } while (1) { while (*s != ' ' && *s != '\t' && *s != '\n') s++; if (*s == '\n') return cmd; while(*s == ' ' || *s == '\t') s++; sscanf(s,"%x",&ps[*n]); *n += 1; } } #endif /* DEBUG */ void x86emu_dump_regs (void) { printf("\tAX=%04x ", M.x86.R_AX ); printf("BX=%04x ", M.x86.R_BX ); printf("CX=%04x ", M.x86.R_CX ); printf("DX=%04x ", M.x86.R_DX ); printf("SP=%04x ", M.x86.R_SP ); printf("BP=%04x ", M.x86.R_BP ); printf("SI=%04x ", M.x86.R_SI ); printf("DI=%04x\n", M.x86.R_DI ); printf("\tDS=%04x ", M.x86.R_DS ); printf("ES=%04x ", M.x86.R_ES ); printf("SS=%04x ", M.x86.R_SS ); printf("CS=%04x ", M.x86.R_CS ); printf("IP=%04x ", M.x86.R_IP ); if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ else printf("NV "); if (ACCESS_FLAG(F_DF)) printf("DN "); else printf("UP "); if (ACCESS_FLAG(F_IF)) printf("EI "); else printf("DI "); if (ACCESS_FLAG(F_SF)) printf("NG "); else printf("PL "); if (ACCESS_FLAG(F_ZF)) printf("ZR "); else printf("NZ "); if (ACCESS_FLAG(F_AF)) printf("AC "); else printf("NA "); if (ACCESS_FLAG(F_PF)) printf("PE "); else printf("PO "); if (ACCESS_FLAG(F_CF)) printf("CY "); else printf("NC "); printf("\n"); } void x86emu_dump_xregs (void) { printf("\tEAX=%08x ", M.x86.R_EAX ); printf("EBX=%08x ", M.x86.R_EBX ); printf("ECX=%08x ", M.x86.R_ECX ); printf("EDX=%08x \n", M.x86.R_EDX ); printf("\tESP=%08x ", M.x86.R_ESP ); printf("EBP=%08x ", M.x86.R_EBP ); printf("ESI=%08x ", M.x86.R_ESI ); printf("EDI=%08x\n", M.x86.R_EDI ); printf("\tDS=%04x ", M.x86.R_DS ); printf("ES=%04x ", M.x86.R_ES ); printf("SS=%04x ", M.x86.R_SS ); printf("CS=%04x ", M.x86.R_CS ); printf("EIP=%08x\n\t", M.x86.R_EIP ); if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ else printf("NV "); if (ACCESS_FLAG(F_DF)) printf("DN "); else printf("UP "); if (ACCESS_FLAG(F_IF)) printf("EI "); else printf("DI "); if (ACCESS_FLAG(F_SF)) printf("NG "); else printf("PL "); if (ACCESS_FLAG(F_ZF)) printf("ZR "); else printf("NZ "); if (ACCESS_FLAG(F_AF)) printf("AC "); else printf("NA "); if (ACCESS_FLAG(F_PF)) printf("PE "); else printf("PO "); if (ACCESS_FLAG(F_CF)) printf("CY "); else printf("NC "); printf("\n"); } xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/decode.c0000644000000000000000000007037710410136571016355 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: This file includes subroutines which are related to * instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ #include "x86emu/x86emui.h" /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** REMARKS: Handles any pending asychronous interrupts. ****************************************************************************/ static void x86emu_intr_handle(void) { u8 intno; if (M.x86.intr & INTR_SYNCH) { intno = M.x86.intno; if (_X86EMU_intrTab[intno]) { (*_X86EMU_intrTab[intno])(intno); } else { push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); push_word(M.x86.R_CS); M.x86.R_CS = mem_access_word(intno * 4 + 2); push_word(M.x86.R_IP); M.x86.R_IP = mem_access_word(intno * 4); M.x86.intr = 0; } } } /**************************************************************************** PARAMETERS: intrnum - Interrupt number to raise REMARKS: Raise the specified interrupt to be handled before the execution of the next instruction. ****************************************************************************/ void x86emu_intr_raise( u8 intrnum) { M.x86.intno = intrnum; M.x86.intr |= INTR_SYNCH; } /**************************************************************************** REMARKS: Main execution loop for the emulator. We return from here when the system halts, which is normally caused by a stack fault when we return from the original real mode call. ****************************************************************************/ void X86EMU_exec(void) { u8 op1; M.x86.intr = 0; DB(x86emu_end_instr();) for (;;) { DB( if (CHECK_IP_FETCH()) x86emu_check_ip_access();) /* If debugging, save the IP and CS values. */ SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); INC_DECODED_INST_LEN(1); if (M.x86.intr) { if (M.x86.intr & INTR_HALTED) { DB( X86EMU_trace_regs();) return; } if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || !ACCESS_FLAG(F_IF)) { x86emu_intr_handle(); } } if ((M.x86.R_CS == 0) && (M.x86.R_IP == 0)) { DB( X86EMU_trace_regs();) return; } op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); /*X86EMU_trace_regs();*/ (*x86emu_optab[op1])(op1); } } /**************************************************************************** REMARKS: Halts the system by setting the halted system flag. ****************************************************************************/ void X86EMU_halt_sys(void) { M.x86.intr |= INTR_HALTED; } /**************************************************************************** PARAMETERS: mod - Mod value from decoded byte regh - Reg h value from decoded byte regl - Reg l value from decoded byte REMARKS: Raise the specified interrupt to be handled before the execution of the next instruction. NOTE: Do not inline this function, as (*sys_rdb) is already inline! ****************************************************************************/ void fetch_decode_modrm( int *mod, int *regh, int *regl) { int fetched; DB( if (CHECK_IP_FETCH()) x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); *mod = (fetched >> 6) & 0x03; *regh = (fetched >> 3) & 0x07; *regl = (fetched >> 0) & 0x07; } /**************************************************************************** RETURNS: Immediate byte value read from instruction queue REMARKS: This function returns the immediate byte from the instruction queue, and moves the instruction pointer to the next value. NOTE: Do not inline this function, as (*sys_rdb) is already inline! ****************************************************************************/ u8 fetch_byte_imm(void) { u8 fetched; DB( if (CHECK_IP_FETCH()) x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); return fetched; } /**************************************************************************** RETURNS: Immediate word value read from instruction queue REMARKS: This function returns the immediate byte from the instruction queue, and moves the instruction pointer to the next value. NOTE: Do not inline this function, as (*sys_rdw) is already inline! ****************************************************************************/ u16 fetch_word_imm(void) { u16 fetched; DB( if (CHECK_IP_FETCH()) x86emu_check_ip_access();) fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 2; INC_DECODED_INST_LEN(2); return fetched; } /**************************************************************************** RETURNS: Immediate lone value read from instruction queue REMARKS: This function returns the immediate byte from the instruction queue, and moves the instruction pointer to the next value. NOTE: Do not inline this function, as (*sys_rdw) is already inline! ****************************************************************************/ u32 fetch_long_imm(void) { u32 fetched; DB( if (CHECK_IP_FETCH()) x86emu_check_ip_access();) fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 4; INC_DECODED_INST_LEN(4); return fetched; } /**************************************************************************** RETURNS: Value of the default data segment REMARKS: Inline function that returns the default data segment for the current instruction. On the x86 processor, the default segment is not always DS if there is no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to addresses relative to SS (ie: on the stack). So, at the minimum, all decodings of addressing modes would have to set/clear a bit describing whether the access is relative to DS or SS. That is the function of the cpu-state-varible M.x86.mode. There are several potential states: repe prefix seen (handled elsewhere) repne prefix seen (ditto) cs segment override ds segment override es segment override fs segment override gs segment override ss segment override ds/ss select (in absense of override) Each of the above 7 items are handled with a bit in the mode field. ****************************************************************************/ _INLINE u32 get_data_segment(void) { #define GET_SEGMENT(segment) switch (M.x86.mode & SYSMODE_SEGMASK) { case 0: /* default case: use ds register */ case SYSMODE_SEGOVR_DS: case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: return M.x86.R_DS; case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ return M.x86.R_SS; case SYSMODE_SEGOVR_CS: case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: return M.x86.R_CS; case SYSMODE_SEGOVR_ES: case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: return M.x86.R_ES; case SYSMODE_SEGOVR_FS: case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: return M.x86.R_FS; case SYSMODE_SEGOVR_GS: case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: return M.x86.R_GS; case SYSMODE_SEGOVR_SS: case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: return M.x86.R_SS; default: #ifdef DEBUG printk("error: should not happen: multiple overrides.\n"); #endif HALT_SYS(); return 0; } } /**************************************************************************** PARAMETERS: offset - Offset to load data from RETURNS: Byte value read from the absolute memory location. NOTE: Do not inline this function as (*sys_rdX) is already inline! ****************************************************************************/ u8 fetch_data_byte( uint offset) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdb)((get_data_segment() << 4) + offset); } /**************************************************************************** PARAMETERS: offset - Offset to load data from RETURNS: Word value read from the absolute memory location. NOTE: Do not inline this function as (*sys_rdX) is already inline! ****************************************************************************/ u16 fetch_data_word( uint offset) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdw)((get_data_segment() << 4) + offset); } /**************************************************************************** PARAMETERS: offset - Offset to load data from RETURNS: Long value read from the absolute memory location. NOTE: Do not inline this function as (*sys_rdX) is already inline! ****************************************************************************/ u32 fetch_data_long( uint offset) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdl)((get_data_segment() << 4) + offset); } /**************************************************************************** PARAMETERS: segment - Segment to load data from offset - Offset to load data from RETURNS: Byte value read from the absolute memory location. NOTE: Do not inline this function as (*sys_rdX) is already inline! ****************************************************************************/ u8 fetch_data_byte_abs( uint segment, uint offset) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif return (*sys_rdb)(((u32)segment << 4) + offset); } /**************************************************************************** PARAMETERS: segment - Segment to load data from offset - Offset to load data from RETURNS: Word value read from the absolute memory location. NOTE: Do not inline this function as (*sys_rdX) is already inline! ****************************************************************************/ u16 fetch_data_word_abs( uint segment, uint offset) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif return (*sys_rdw)(((u32)segment << 4) + offset); } /**************************************************************************** PARAMETERS: segment - Segment to load data from offset - Offset to load data from RETURNS: Long value read from the absolute memory location. NOTE: Do not inline this function as (*sys_rdX) is already inline! ****************************************************************************/ u32 fetch_data_long_abs( uint segment, uint offset) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif return (*sys_rdl)(((u32)segment << 4) + offset); } /**************************************************************************** PARAMETERS: offset - Offset to store data at val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is the current 'default' segment, which may have been overridden. NOTE: Do not inline this function as (*sys_wrX) is already inline! ****************************************************************************/ void store_data_byte( uint offset, u8 val) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrb)((get_data_segment() << 4) + offset, val); } /**************************************************************************** PARAMETERS: offset - Offset to store data at val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is the current 'default' segment, which may have been overridden. NOTE: Do not inline this function as (*sys_wrX) is already inline! ****************************************************************************/ void store_data_word( uint offset, u16 val) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrw)((get_data_segment() << 4) + offset, val); } /**************************************************************************** PARAMETERS: offset - Offset to store data at val - Value to store REMARKS: Writes a long value to an segmented memory location. The segment used is the current 'default' segment, which may have been overridden. NOTE: Do not inline this function as (*sys_wrX) is already inline! ****************************************************************************/ void store_data_long( uint offset, u32 val) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrl)((get_data_segment() << 4) + offset, val); } /**************************************************************************** PARAMETERS: segment - Segment to store data at offset - Offset to store data at val - Value to store REMARKS: Writes a byte value to an absolute memory location. NOTE: Do not inline this function as (*sys_wrX) is already inline! ****************************************************************************/ void store_data_byte_abs( uint segment, uint offset, u8 val) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif (*sys_wrb)(((u32)segment << 4) + offset, val); } /**************************************************************************** PARAMETERS: segment - Segment to store data at offset - Offset to store data at val - Value to store REMARKS: Writes a word value to an absolute memory location. NOTE: Do not inline this function as (*sys_wrX) is already inline! ****************************************************************************/ void store_data_word_abs( uint segment, uint offset, u16 val) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif (*sys_wrw)(((u32)segment << 4) + offset, val); } /**************************************************************************** PARAMETERS: segment - Segment to store data at offset - Offset to store data at val - Value to store REMARKS: Writes a long value to an absolute memory location. NOTE: Do not inline this function as (*sys_wrX) is already inline! ****************************************************************************/ void store_data_long_abs( uint segment, uint offset, u32 val) { #ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif (*sys_wrl)(((u32)segment << 4) + offset, val); } /**************************************************************************** PARAMETERS: reg - Register to decode RETURNS: Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the modrm byte, for byte operands. Also enables the decoding of instructions. ****************************************************************************/ u8* decode_rm_byte_register( int reg) { switch (reg) { case 0: DECODE_PRINTF("AL"); return &M.x86.R_AL; case 1: DECODE_PRINTF("CL"); return &M.x86.R_CL; case 2: DECODE_PRINTF("DL"); return &M.x86.R_DL; case 3: DECODE_PRINTF("BL"); return &M.x86.R_BL; case 4: DECODE_PRINTF("AH"); return &M.x86.R_AH; case 5: DECODE_PRINTF("CH"); return &M.x86.R_CH; case 6: DECODE_PRINTF("DH"); return &M.x86.R_DH; case 7: DECODE_PRINTF("BH"); return &M.x86.R_BH; } HALT_SYS(); return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** PARAMETERS: reg - Register to decode RETURNS: Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the modrm byte, for word operands. Also enables the decoding of instructions. ****************************************************************************/ u16* decode_rm_word_register( int reg) { switch (reg) { case 0: DECODE_PRINTF("AX"); return &M.x86.R_AX; case 1: DECODE_PRINTF("CX"); return &M.x86.R_CX; case 2: DECODE_PRINTF("DX"); return &M.x86.R_DX; case 3: DECODE_PRINTF("BX"); return &M.x86.R_BX; case 4: DECODE_PRINTF("SP"); return &M.x86.R_SP; case 5: DECODE_PRINTF("BP"); return &M.x86.R_BP; case 6: DECODE_PRINTF("SI"); return &M.x86.R_SI; case 7: DECODE_PRINTF("DI"); return &M.x86.R_DI; } HALT_SYS(); return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** PARAMETERS: reg - Register to decode RETURNS: Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the modrm byte, for dword operands. Also enables the decoding of instructions. ****************************************************************************/ u32* decode_rm_long_register( int reg) { switch (reg) { case 0: DECODE_PRINTF("EAX"); return &M.x86.R_EAX; case 1: DECODE_PRINTF("ECX"); return &M.x86.R_ECX; case 2: DECODE_PRINTF("EDX"); return &M.x86.R_EDX; case 3: DECODE_PRINTF("EBX"); return &M.x86.R_EBX; case 4: DECODE_PRINTF("ESP"); return &M.x86.R_ESP; case 5: DECODE_PRINTF("EBP"); return &M.x86.R_EBP; case 6: DECODE_PRINTF("ESI"); return &M.x86.R_ESI; case 7: DECODE_PRINTF("EDI"); return &M.x86.R_EDI; } HALT_SYS(); return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** PARAMETERS: reg - Register to decode RETURNS: Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the modrm byte, for word operands, modified from above for the weirdo special case of segreg operands. Also enables the decoding of instructions. ****************************************************************************/ u16* decode_rm_seg_register( int reg) { switch (reg) { case 0: DECODE_PRINTF("ES"); return &M.x86.R_ES; case 1: DECODE_PRINTF("CS"); return &M.x86.R_CS; case 2: DECODE_PRINTF("SS"); return &M.x86.R_SS; case 3: DECODE_PRINTF("DS"); return &M.x86.R_DS; case 4: DECODE_PRINTF("FS"); return &M.x86.R_FS; case 5: DECODE_PRINTF("GS"); return &M.x86.R_GS; case 6: case 7: DECODE_PRINTF("ILLEGAL SEGREG"); break; } printf("reg %d\n", reg); //DECODE_PRINTF("CS"); //return &M.x86.R_CS; /*HALT_SYS();*/ return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /* * * return offset from the SIB Byte */ u32 decode_sib_address(int sib, int mod) { u32 base = 0, i = 0, scale = 1; switch(sib & 0x07) { case 0: DECODE_PRINTF("[EAX]"); base = M.x86.R_EAX; break; case 1: DECODE_PRINTF("[ECX]"); base = M.x86.R_ECX; break; case 2: DECODE_PRINTF("[EDX]"); base = M.x86.R_EDX; break; case 3: DECODE_PRINTF("[EBX]"); base = M.x86.R_EBX; break; case 4: DECODE_PRINTF("[ESP]"); base = M.x86.R_ESP; M.x86.mode |= SYSMODE_SEG_DS_SS; break; case 5: if (mod == 0) { base = fetch_long_imm(); DECODE_PRINTF2("%08x", base); } else { DECODE_PRINTF("[EBP]"); base = M.x86.R_ESP; M.x86.mode |= SYSMODE_SEG_DS_SS; } break; case 6: DECODE_PRINTF("[ESI]"); base = M.x86.R_ESI; break; case 7: DECODE_PRINTF("[EDI]"); base = M.x86.R_EDI; break; } switch ((sib >> 3) & 0x07) { case 0: DECODE_PRINTF("[EAX"); i = M.x86.R_EAX; break; case 1: DECODE_PRINTF("[ECX"); i = M.x86.R_ECX; break; case 2: DECODE_PRINTF("[EDX"); i = M.x86.R_EDX; break; case 3: DECODE_PRINTF("[EBX"); i = M.x86.R_EBX; break; case 4: i = 0; break; case 5: DECODE_PRINTF("[EBP"); i = M.x86.R_EBP; break; case 6: DECODE_PRINTF("[ESI"); i = M.x86.R_ESI; break; case 7: DECODE_PRINTF("[EDI"); i = M.x86.R_EDI; break; } scale = 1 << ((sib >> 6) & 0x03); if (((sib >> 3) & 0x07) != 4) { if (scale == 1) { DECODE_PRINTF("]"); } else { DECODE_PRINTF2("*%d]", scale); } } return base + (i * scale); } /**************************************************************************** PARAMETERS: rm - RM value to decode RETURNS: Offset in memory for the address decoding REMARKS: Return the offset given by mod=00 addressing. Also enables the decoding of instructions. NOTE: The code which specifies the corresponding segment (ds vs ss) below in the case of [BP+..]. The assumption here is that at the point that this subroutine is called, the bit corresponding to SYSMODE_SEG_DS_SS will be zero. After every instruction except the segment override instructions, this bit (as well as any bits indicating segment overrides) will be clear. So if a SS access is needed, set this bit. Otherwise, DS access occurs (unless any of the segment override bits are set). ****************************************************************************/ u32 decode_rm00_address( int rm) { u32 offset; int sib; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { switch (rm) { case 0: DECODE_PRINTF("[EAX]"); return M.x86.R_EAX; case 1: DECODE_PRINTF("[ECX]"); return M.x86.R_ECX; case 2: DECODE_PRINTF("[EDX]"); return M.x86.R_EDX; case 3: DECODE_PRINTF("[EBX]"); return M.x86.R_EBX; case 4: sib = fetch_byte_imm(); return decode_sib_address(sib, 0); case 5: offset = fetch_long_imm(); DECODE_PRINTF2("[%08x]", offset); return offset; case 6: DECODE_PRINTF("[ESI]"); return M.x86.R_ESI; case 7: DECODE_PRINTF("[EDI]"); return M.x86.R_EDI; } HALT_SYS(); } else { switch (rm) { case 0: DECODE_PRINTF("[BX+SI]"); return M.x86.R_BX + M.x86.R_SI; case 1: DECODE_PRINTF("[BX+DI]"); return M.x86.R_BX + M.x86.R_DI; case 2: DECODE_PRINTF("[BP+SI]"); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + M.x86.R_SI; case 3: DECODE_PRINTF("[BP+DI]"); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + M.x86.R_DI; case 4: DECODE_PRINTF("[SI]"); return M.x86.R_SI; case 5: DECODE_PRINTF("[DI]"); return M.x86.R_DI; case 6: offset = fetch_word_imm(); DECODE_PRINTF2("[%04x]", offset); return offset; case 7: DECODE_PRINTF("[BX]"); return M.x86.R_BX; } HALT_SYS(); } return 0; } /**************************************************************************** PARAMETERS: rm - RM value to decode RETURNS: Offset in memory for the address decoding REMARKS: Return the offset given by mod=01 addressing. Also enables the decoding of instructions. ****************************************************************************/ u32 decode_rm01_address( int rm) { int displacement = 0; int sib; /* Fetch disp8 if no SIB byte */ if (!((M.x86.mode & SYSMODE_PREFIX_ADDR) && (rm == 4))) displacement = (s8)fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) { switch (rm) { case 0: DECODE_PRINTF2("%d[EAX]", displacement); return M.x86.R_EAX + displacement; case 1: DECODE_PRINTF2("%d[ECX]", displacement); return M.x86.R_ECX + displacement; case 2: DECODE_PRINTF2("%d[EDX]", displacement); return M.x86.R_EDX + displacement; case 3: DECODE_PRINTF2("%d[EBX]", displacement); return M.x86.R_EBX + displacement; case 4: sib = fetch_byte_imm(); displacement = (s8)fetch_byte_imm(); DECODE_PRINTF2("%d", displacement); return decode_sib_address(sib, 1) + displacement; case 5: DECODE_PRINTF2("%d[EBP]", displacement); return M.x86.R_EBP + displacement; case 6: DECODE_PRINTF2("%d[ESI]", displacement); return M.x86.R_ESI + displacement; case 7: DECODE_PRINTF2("%d[EDI]", displacement); return M.x86.R_EDI + displacement; } HALT_SYS(); } else { switch (rm) { case 0: DECODE_PRINTF2("%d[BX+SI]", displacement); return M.x86.R_BX + M.x86.R_SI + displacement; case 1: DECODE_PRINTF2("%d[BX+DI]", displacement); return M.x86.R_BX + M.x86.R_DI + displacement; case 2: DECODE_PRINTF2("%d[BP+SI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + M.x86.R_SI + displacement; case 3: DECODE_PRINTF2("%d[BP+DI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + M.x86.R_DI + displacement; case 4: DECODE_PRINTF2("%d[SI]", displacement); return M.x86.R_SI + displacement; case 5: DECODE_PRINTF2("%d[DI]", displacement); return M.x86.R_DI + displacement; case 6: DECODE_PRINTF2("%d[BP]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + displacement; case 7: DECODE_PRINTF2("%d[BX]", displacement); return M.x86.R_BX + displacement; } HALT_SYS(); } return 0; /* SHOULD NOT HAPPEN */ } /**************************************************************************** PARAMETERS: rm - RM value to decode RETURNS: Offset in memory for the address decoding REMARKS: Return the offset given by mod=10 addressing. Also enables the decoding of instructions. ****************************************************************************/ u32 decode_rm10_address( int rm) { u32 displacement = 0; int sib; /* Fetch disp16 if 16-bit addr mode */ if (!(M.x86.mode & SYSMODE_PREFIX_ADDR)) displacement = (u16)fetch_word_imm(); else { /* Fetch disp32 if no SIB byte */ if (rm != 4) displacement = (u32)fetch_long_imm(); } if (M.x86.mode & SYSMODE_PREFIX_ADDR) { switch (rm) { case 0: DECODE_PRINTF2("%08x[EAX]", displacement); return M.x86.R_EAX + displacement; case 1: DECODE_PRINTF2("%08x[ECX]", displacement); return M.x86.R_ECX + displacement; case 2: DECODE_PRINTF2("%08x[EDX]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_EDX + displacement; case 3: DECODE_PRINTF2("%08x[EBX]", displacement); return M.x86.R_EBX + displacement; case 4: sib = fetch_byte_imm(); displacement = (u32)fetch_long_imm(); DECODE_PRINTF2("%08x", displacement); return decode_sib_address(sib, 2) + displacement; break; case 5: DECODE_PRINTF2("%08x[EBP]", displacement); return M.x86.R_EBP + displacement; case 6: DECODE_PRINTF2("%08x[ESI]", displacement); return M.x86.R_ESI + displacement; case 7: DECODE_PRINTF2("%08x[EDI]", displacement); return M.x86.R_EDI + displacement; } HALT_SYS(); } else { switch (rm) { case 0: DECODE_PRINTF2("%04x[BX+SI]", displacement); return M.x86.R_BX + M.x86.R_SI + displacement; case 1: DECODE_PRINTF2("%04x[BX+DI]", displacement); return M.x86.R_BX + M.x86.R_DI + displacement; case 2: DECODE_PRINTF2("%04x[BP+SI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + M.x86.R_SI + displacement; case 3: DECODE_PRINTF2("%04x[BP+DI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + M.x86.R_DI + displacement; case 4: DECODE_PRINTF2("%04x[SI]", displacement); return M.x86.R_SI + displacement; case 5: DECODE_PRINTF2("%04x[DI]", displacement); return M.x86.R_DI + displacement; case 6: DECODE_PRINTF2("%04x[BP]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; return M.x86.R_BP + displacement; case 7: DECODE_PRINTF2("%04x[BX]", displacement); return M.x86.R_BX + displacement; } HALT_SYS(); } return 0; /*NOTREACHED */ } xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/makefile0000644000000000000000000000375510410136571016462 0ustar ############################################################################# # # Realmode X86 Emulator Library # # Copyright (C) 1996-1999 SciTech Software, Inc. # # ======================================================================== # # Permission to use, copy, modify, distribute, and sell this software and # its documentation for any purpose is hereby granted without fee, # provided that the above copyright notice appear in all copies and that # both that copyright notice and this permission notice appear in # supporting documentation, and that the name of the authors not be used # in advertising or publicity pertaining to distribution of the software # without specific, written prior permission. The authors makes no # representations about the suitability of this software for any purpose. # It is provided "as is" without express or implied warranty. # # THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, # INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO # EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR # CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF # USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR # OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR # PERFORMANCE OF THIS SOFTWARE. # # ======================================================================== # # Descripton: Linux specific makefile for the x86emu library. # ############################################################################# TARGETLIB = libx86emu.a OBJS=\ debug.o \ decode.o \ fpu.o \ ops.o \ ops2.o \ prim_ops.o \ sys.o all: $(TARGETLIB) $(TARGETLIB): $(OBJS) ar rv $(TARGETLIB) $(OBJS) INCS = -I. -Ix86emu -I../../include -I../x86emu_include CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -DDEBUG .c.o: gcc -g -O -Wall -c $(CFLAGS) $(INCS) $*.c .cpp.o: gcc -c $(CFLAGS) $(INCS) $*.cpp distclean: clean clean: rm -f *.a *.o install: xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/0000755000000000000000000000000010415741443016111 5ustar xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/debug.h0000644000000000000000000001706310410136571017352 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for debug definitions. * ****************************************************************************/ #ifndef __X86EMU_DEBUG_H #define __X86EMU_DEBUG_H /*---------------------- Macros and type definitions ----------------------*/ /* checks to be enabled for "runtime" */ #define CHECK_IP_FETCH_F 0x1 #define CHECK_SP_ACCESS_F 0x2 #define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ #define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ #ifdef DEBUG # define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) # define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) # define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) # define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) #else # define CHECK_IP_FETCH() # define CHECK_SP_ACCESS() # define CHECK_MEM_ACCESS() # define CHECK_DATA_ACCESS() #endif #ifdef DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) # define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) # define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) # define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) # define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) # define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) # define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) # define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) # define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) # define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) # define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) # define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) # define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) # define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) # define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) #else # define DEBUG_INSTRUMENT() 0 # define DEBUG_DECODE() 0 # define DEBUG_TRACE() 0 # define DEBUG_STEP() 0 # define DEBUG_DISASSEMBLE() 0 # define DEBUG_BREAK() 0 # define DEBUG_SVC() 0 # define DEBUG_SAVE_IP_CS() 0 # define DEBUG_FS() 0 # define DEBUG_PROC() 0 # define DEBUG_SYSINT() 0 # define DEBUG_TRACECALL() 0 # define DEBUG_TRACECALLREGS() 0 # define DEBUG_SYS() 0 # define DEBUG_MEM_TRACE() 0 # define DEBUG_IO_TRACE() 0 # define DEBUG_DECODE_NOPRINT() 0 #endif #ifdef DEBUG # define DECODE_PRINTF(x) \ if (DEBUG_DECODE()) \ x86emu_decode_printf(x) # define DECODE_PRINTF2(x,y) \ if (DEBUG_DECODE()) \ x86emu_decode_printf2(x,y) /* * The following allow us to look at the bytes of an instruction. The * first INCR_INSTRN_LEN, is called everytime bytes are consumed in * the decoding process. The SAVE_IP_CS is called initially when the * major opcode of the instruction is accessed. */ #define INC_DECODED_INST_LEN(x) \ if (DEBUG_DECODE()) \ x86emu_inc_decoded_inst_len(x) #define SAVE_IP_CS(x,y) \ if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ M.x86.saved_cs = x; \ M.x86.saved_ip = y; \ } #else # define INC_DECODED_INST_LEN(x) # define DECODE_PRINTF(x) # define DECODE_PRINTF2(x,y) # define SAVE_IP_CS(x,y) #endif #ifdef DEBUG #define TRACE_REGS() \ if (DEBUG_DISASSEMBLE()) { \ x86emu_just_disassemble(); \ goto EndOfTheInstructionProcedure; \ } /*\ if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs()*/ #else # define TRACE_REGS() #endif #ifdef DEBUG # define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() #endif #define TRACE_AND_STEP() \ TRACE_REGS(); \ SINGLE_STEP() #ifdef DEBUG # define START_OF_INSTR() # define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); #else # define START_OF_INSTR() # define END_OF_INSTR() # define END_OF_INSTR_NO_TRACE() #endif #ifdef DEBUG # define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ x86emu_dump_regs(); \ if (DEBUG_TRACECALL()) \ printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); # define RETURN_TRACE(n,u,v) \ if (DEBUG_TRACECALLREGS()) \ x86emu_dump_regs(); \ if (DEBUG_TRACECALL()) \ printk("%04x:%04x: %s\n",u,v,n); #else # define CALL_TRACE(u,v,w,x,s) # define RETURN_TRACE(n,u,v) #endif #ifdef DEBUG #define DB(x) x #else #define DB(x) #endif /*-------------------------- Function Prototypes --------------------------*/ #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif extern void x86emu_inc_decoded_inst_len (int x); extern void x86emu_decode_printf (char *x); extern void x86emu_decode_printf2 (char *x, int y); extern void x86emu_just_disassemble (void); extern void x86emu_single_step (void); extern void x86emu_end_instr (void); extern void x86emu_dump_regs (void); extern void x86emu_dump_xregs (void); extern void x86emu_print_int_vect (u16 iv); extern void x86emu_instrument_instruction (void); extern void x86emu_check_ip_access (void); extern void x86emu_check_sp_access (void); extern void x86emu_check_mem_access (u32 p); extern void x86emu_check_data_access (uint s, uint o); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_DEBUG_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/fpu.h0000644000000000000000000000463710410136571017061 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for FPU instruction decoding. * ****************************************************************************/ #ifndef __X86EMU_FPU_H #define __X86EMU_FPU_H #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif /* these have to be defined, whether 8087 support compiled in or not. */ extern void x86emuOp_esc_coprocess_d8 (u8 op1); extern void x86emuOp_esc_coprocess_d9 (u8 op1); extern void x86emuOp_esc_coprocess_da (u8 op1); extern void x86emuOp_esc_coprocess_db (u8 op1); extern void x86emuOp_esc_coprocess_dc (u8 op1); extern void x86emuOp_esc_coprocess_dd (u8 op1); extern void x86emuOp_esc_coprocess_de (u8 op1); extern void x86emuOp_esc_coprocess_df (u8 op1); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_FPU_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/types.h0000644000000000000000000000621410410136571017424 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for x86 emulator type definitions. * ****************************************************************************/ #ifndef __X86EMU_TYPES_H #define __X86EMU_TYPES_H #ifndef IN_MODULE #include #endif /* * The following kludge is an attempt to work around typedef conflicts with * . */ #define u8 x86emuu8 #define u16 x86emuu16 #define u32 x86emuu32 #define u64 x86emuu64 #define s8 x86emus8 #define s16 x86emus16 #define s32 x86emus32 #define s64 x86emus64 #define uint x86emuuint #define sint x86emusint /*---------------------- Macros and type definitions ----------------------*/ /* Currently only for Linux/32bit */ #undef __HAS_LONG_LONG__ #if defined(__GNUC__) && !defined(NO_LONG_LONG) #define __HAS_LONG_LONG__ #endif /* Taken from Xmd.h */ #undef NUM32 #if defined (_LP64) || \ defined(__alpha) || defined(__alpha__) || \ defined(__ia64__) || defined(ia64) || \ defined(__sparc64__) || \ defined(__s390x__) || \ (defined(__hppa__) && defined(__LP64)) || \ defined(__amd64__) || defined(amd64) || \ (defined(__sgi) && (_MIPS_SZLONG == 64)) #define NUM32 int #else #define NUM32 long #endif typedef unsigned char u8; typedef unsigned short u16; typedef unsigned NUM32 u32; #ifdef __HAS_LONG_LONG__ typedef unsigned long long u64; #endif typedef char s8; typedef short s16; typedef NUM32 s32; #ifdef __HAS_LONG_LONG__ typedef long long s64; #endif typedef unsigned int uint; typedef int sint; typedef u16 X86EMU_pioAddr; #undef NUM32 #endif /* __X86EMU_TYPES_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/x86emui.h0000644000000000000000000000713110410136571017564 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for system specific functions. These functions * are always compiled and linked in the OS depedent libraries, * and never in a binary portable driver. * ****************************************************************************/ #ifndef __X86EMU_X86EMUI_H #define __X86EMU_X86EMUI_H /* If we are compiling in C++ mode, we can compile some functions as * inline to increase performance (however the code size increases quite * dramatically in this case). */ #if defined(__cplusplus) && !defined(_NO_INLINE) #define _INLINE inline #else #define _INLINE static #endif /* Get rid of unused parameters in C++ compilation mode */ #ifdef __cplusplus #define X86EMU_UNUSED(v) #else #define X86EMU_UNUSED(v) v #endif #include "x86emu.h" #include "x86emu/regs.h" #include "x86emu/debug.h" #include "x86emu/decode.h" #include "x86emu/ops.h" #include "x86emu/prim_ops.h" #include "x86emu/fpu.h" #include "x86emu/fpu_regs.h" #ifdef IN_MODULE #include #else #include #include #include #endif /*--------------------------- Inline Functions ----------------------------*/ #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif extern u8 (X86APIP sys_rdb)(u32 addr); extern u16 (X86APIP sys_rdw)(u32 addr); extern u32 (X86APIP sys_rdl)(u32 addr); extern void (X86APIP sys_wrb)(u32 addr,u8 val); extern void (X86APIP sys_wrw)(u32 addr,u16 val); extern void (X86APIP sys_wrl)(u32 addr,u32 val); extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_X86EMUI_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/regs.h0000644000000000000000000002415210410136571017221 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for x86 register definitions. * ****************************************************************************/ #ifndef __X86EMU_REGS_H #define __X86EMU_REGS_H /*---------------------- Macros and type definitions ----------------------*/ /* * General EAX, EBX, ECX, EDX type registers. Note that for * portability, and speed, the issue of byte swapping is not addressed * in the registers. All registers are stored in the default format * available on the host machine. The only critical issue is that the * registers should line up EXACTLY in the same manner as they do in * the 386. That is: * * EAX & 0xff === AL * EAX & 0xffff == AX * * etc. The result is that alot of the calculations can then be * done using the native instruction set fully. */ #ifdef __BIG_ENDIAN__ typedef struct { u32 e_reg; } I32_reg_t; typedef struct { u16 filler0, x_reg; } I16_reg_t; typedef struct { u8 filler0, filler1, h_reg, l_reg; } I8_reg_t; #else /* !__BIG_ENDIAN__ */ typedef struct { u32 e_reg; } I32_reg_t; typedef struct { u16 x_reg; } I16_reg_t; typedef struct { u8 l_reg, h_reg; } I8_reg_t; #endif /* BIG_ENDIAN */ typedef union { I32_reg_t I32_reg; I16_reg_t I16_reg; I8_reg_t I8_reg; } i386_general_register; struct i386_general_regs { i386_general_register A, B, C, D; }; typedef struct i386_general_regs Gen_reg_t; struct i386_special_regs { i386_general_register SP, BP, SI, DI, IP; u32 FLAGS; }; /* * Segment registers here represent the 16 bit quantities * CS, DS, ES, SS. */ struct i386_segment_regs { u16 CS, DS, SS, ES, FS, GS; }; /* 8 bit registers */ #define R_AH gen.A.I8_reg.h_reg #define R_AL gen.A.I8_reg.l_reg #define R_BH gen.B.I8_reg.h_reg #define R_BL gen.B.I8_reg.l_reg #define R_CH gen.C.I8_reg.h_reg #define R_CL gen.C.I8_reg.l_reg #define R_DH gen.D.I8_reg.h_reg #define R_DL gen.D.I8_reg.l_reg /* 16 bit registers */ #define R_AX gen.A.I16_reg.x_reg #define R_BX gen.B.I16_reg.x_reg #define R_CX gen.C.I16_reg.x_reg #define R_DX gen.D.I16_reg.x_reg /* 32 bit extended registers */ #define R_EAX gen.A.I32_reg.e_reg #define R_EBX gen.B.I32_reg.e_reg #define R_ECX gen.C.I32_reg.e_reg #define R_EDX gen.D.I32_reg.e_reg /* special registers */ #define R_SP spc.SP.I16_reg.x_reg #define R_BP spc.BP.I16_reg.x_reg #define R_SI spc.SI.I16_reg.x_reg #define R_DI spc.DI.I16_reg.x_reg #define R_IP spc.IP.I16_reg.x_reg #define R_FLG spc.FLAGS /* special registers */ #define R_SP spc.SP.I16_reg.x_reg #define R_BP spc.BP.I16_reg.x_reg #define R_SI spc.SI.I16_reg.x_reg #define R_DI spc.DI.I16_reg.x_reg #define R_IP spc.IP.I16_reg.x_reg #define R_FLG spc.FLAGS /* special registers */ #define R_ESP spc.SP.I32_reg.e_reg #define R_EBP spc.BP.I32_reg.e_reg #define R_ESI spc.SI.I32_reg.e_reg #define R_EDI spc.DI.I32_reg.e_reg #define R_EIP spc.IP.I32_reg.e_reg #define R_EFLG spc.FLAGS /* segment registers */ #define R_CS seg.CS #define R_DS seg.DS #define R_SS seg.SS #define R_ES seg.ES #define R_FS seg.FS #define R_GS seg.GS /* flag conditions */ #define FB_CF 0x0001 /* CARRY flag */ #define FB_PF 0x0004 /* PARITY flag */ #define FB_AF 0x0010 /* AUX flag */ #define FB_ZF 0x0040 /* ZERO flag */ #define FB_SF 0x0080 /* SIGN flag */ #define FB_TF 0x0100 /* TRAP flag */ #define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ #define FB_DF 0x0400 /* DIR flag */ #define FB_OF 0x0800 /* OVERFLOW flag */ /* 80286 and above always have bit#1 set */ #define F_ALWAYS_ON (0x0002) /* flag bits always on */ /* * Define a mask for only those flag bits we will ever pass back * (via PUSHF) */ #define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) /* following bits masked in to a 16bit quantity */ #define F_CF 0x0001 /* CARRY flag */ #define F_PF 0x0004 /* PARITY flag */ #define F_AF 0x0010 /* AUX flag */ #define F_ZF 0x0040 /* ZERO flag */ #define F_SF 0x0080 /* SIGN flag */ #define F_TF 0x0100 /* TRAP flag */ #define F_IF 0x0200 /* INTERRUPT ENABLE flag */ #define F_DF 0x0400 /* DIR flag */ #define F_OF 0x0800 /* OVERFLOW flag */ #define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) #define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) #define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) #define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) #define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) #define CONDITIONAL_SET_FLAG(COND,FLAG) \ if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) #define F_PF_CALC 0x010000 /* PARITY flag has been calced */ #define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ #define F_SF_CALC 0x040000 /* SIGN flag has been calced */ #define F_ALL_CALC 0xff0000 /* All have been calced */ /* * Emulator machine state. * Segment usage control. */ #define SYSMODE_SEG_DS_SS 0x00000001 #define SYSMODE_SEGOVR_CS 0x00000002 #define SYSMODE_SEGOVR_DS 0x00000004 #define SYSMODE_SEGOVR_ES 0x00000008 #define SYSMODE_SEGOVR_FS 0x00000010 #define SYSMODE_SEGOVR_GS 0x00000020 #define SYSMODE_SEGOVR_SS 0x00000040 #define SYSMODE_PREFIX_REPE 0x00000080 #define SYSMODE_PREFIX_REPNE 0x00000100 #define SYSMODE_PREFIX_DATA 0x00000200 #define SYSMODE_PREFIX_ADDR 0x00000400 #define SYSMODE_INTR_PENDING 0x10000000 #define SYSMODE_EXTRN_INTR 0x20000000 #define SYSMODE_HALTED 0x40000000 #define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ SYSMODE_SEGOVR_FS | \ SYSMODE_SEGOVR_GS | \ SYSMODE_SEGOVR_SS) #define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ SYSMODE_SEGOVR_FS | \ SYSMODE_SEGOVR_GS | \ SYSMODE_SEGOVR_SS | \ SYSMODE_PREFIX_DATA | \ SYSMODE_PREFIX_ADDR) #define INTR_SYNCH 0x1 #define INTR_ASYNCH 0x2 #define INTR_HALTED 0x4 typedef struct { struct i386_general_regs gen; struct i386_special_regs spc; struct i386_segment_regs seg; /* * MODE contains information on: * REPE prefix 2 bits repe,repne * SEGMENT overrides 5 bits normal,DS,SS,CS,ES * Delayed flag set 3 bits (zero, signed, parity) * reserved 6 bits * interrupt # 8 bits instruction raised interrupt * BIOS video segregs 4 bits * Interrupt Pending 1 bits * Extern interrupt 1 bits * Halted 1 bits */ u32 mode; volatile int intr; /* mask of pending interrupts */ int debug; #ifdef DEBUG int check; u16 saved_ip; u16 saved_cs; int enc_pos; int enc_str_pos; char decode_buf[32]; /* encoded byte stream */ char decoded_buf[256]; /* disassembled strings */ #endif u8 intno; u8 __pad[3]; } X86EMU_regs; /**************************************************************************** REMARKS: Structure maintaining the emulator machine state. MEMBERS: mem_base - Base real mode memory for the emulator mem_size - Size of the real mode memory block for the emulator private - private data pointer x86 - X86 registers ****************************************************************************/ typedef struct { unsigned long mem_base; unsigned long mem_size; void* private; X86EMU_regs x86; } X86EMU_sysEnv; /*----------------------------- Global Variables --------------------------*/ #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif /* Global emulator machine state. * * We keep it global to avoid pointer dereferences in the code for speed. */ extern X86EMU_sysEnv _X86EMU_env; #define M _X86EMU_env /*-------------------------- Function Prototypes --------------------------*/ /* Function to log information at runtime */ void printk(const char *fmt, ...); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_REGS_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/x86emu.h0000644000000000000000000001603510410136571017416 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for public specific functions. * Any application linking against us should only * include this header * ****************************************************************************/ #ifndef __X86EMU_X86EMU_H #define __X86EMU_X86EMU_H #ifdef SCITECH #include "scitech.h" #define X86API _ASMAPI #define X86APIP _ASMAPIP typedef int X86EMU_pioAddr; #else #include "x86emu/types.h" #define X86API #define X86APIP * #endif #include "x86emu/regs.h" /*---------------------- Macros and type definitions ----------------------*/ /* #pragma pack(1) */ /* Don't pack structs with function pointers! */ /**************************************************************************** REMARKS: Data structure containing ponters to programmed I/O functions used by the emulator. This is used so that the user program can hook all programmed I/O for the emulator to handled as necessary by the user program. By default the emulator contains simple functions that do not do access the hardware in any way. To allow the emualtor access the hardware, you will need to override the programmed I/O functions using the X86EMU_setupPioFuncs function. HEADER: x86emu.h MEMBERS: inb - Function to read a byte from an I/O port inw - Function to read a word from an I/O port inl - Function to read a dword from an I/O port outb - Function to write a byte to an I/O port outw - Function to write a word to an I/O port outl - Function to write a dword to an I/O port ****************************************************************************/ typedef struct { u8 (X86APIP inb)(X86EMU_pioAddr addr); u16 (X86APIP inw)(X86EMU_pioAddr addr); u32 (X86APIP inl)(X86EMU_pioAddr addr); void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); } X86EMU_pioFuncs; /**************************************************************************** REMARKS: Data structure containing ponters to memory access functions used by the emulator. This is used so that the user program can hook all memory access functions as necessary for the emulator. By default the emulator contains simple functions that only access the internal memory of the emulator. If you need specialised functions to handle access to different types of memory (ie: hardware framebuffer accesses and BIOS memory access etc), you will need to override this using the X86EMU_setupMemFuncs function. HEADER: x86emu.h MEMBERS: rdb - Function to read a byte from an address rdw - Function to read a word from an address rdl - Function to read a dword from an address wrb - Function to write a byte to an address wrw - Function to write a word to an address wrl - Function to write a dword to an address ****************************************************************************/ typedef struct { u8 (X86APIP rdb)(u32 addr); u16 (X86APIP rdw)(u32 addr); u32 (X86APIP rdl)(u32 addr); void (X86APIP wrb)(u32 addr, u8 val); void (X86APIP wrw)(u32 addr, u16 val); void (X86APIP wrl)(u32 addr, u32 val); } X86EMU_memFuncs; /**************************************************************************** Here are the default memory read and write function in case they are needed as fallbacks. ***************************************************************************/ extern u8 X86API rdb(u32 addr); extern u16 X86API rdw(u32 addr); extern u32 X86API rdl(u32 addr); extern void X86API wrb(u32 addr, u8 val); extern void X86API wrw(u32 addr, u16 val); extern void X86API wrl(u32 addr, u32 val); /* #pragma pack() */ /*--------------------- type definitions -----------------------------------*/ typedef void (X86APIP X86EMU_intrFuncs)(int num); extern X86EMU_intrFuncs _X86EMU_intrTab[256]; /*-------------------------- Function Prototypes --------------------------*/ #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); void X86EMU_prepareForInt(int num); /* decode.c */ void X86EMU_exec(void); void X86EMU_halt_sys(void); #ifdef DEBUG #define HALT_SYS() \ printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ X86EMU_halt_sys() #else #define HALT_SYS() X86EMU_halt_sys() #endif /* Debug options */ #define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ #define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ #define DEBUG_STEP_F 0x000004 #define DEBUG_DISASSEMBLE_F 0x000008 #define DEBUG_BREAK_F 0x000010 #define DEBUG_SVC_F 0x000020 #define DEBUG_FS_F 0x000080 #define DEBUG_PROC_F 0x000100 #define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 #define DEBUG_MEM_TRACE_F 0x001000 #define DEBUG_IO_TRACE_F 0x002000 #define DEBUG_TRACECALL_REGS_F 0x004000 #define DEBUG_DECODE_NOPRINT_F 0x008000 #define DEBUG_SAVE_IP_CS_F 0x010000 #define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) void X86EMU_trace_regs(void); void X86EMU_trace_xregs(void); void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); int X86EMU_trace_on(void); int X86EMU_trace_off(void); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_X86EMU_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/prim_asm.h0000644000000000000000000007143210410136571020073 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: Watcom C++ 10.6 or later * Environment: Any * Developer: Kendall Bennett * * Description: Inline assembler versions of the primitive operand * functions for faster performance. At the moment this is * x86 inline assembler, but these functions could be replaced * with native inline assembler for each supported processor * platform. * ****************************************************************************/ #ifndef __X86EMU_PRIM_ASM_H #define __X86EMU_PRIM_ASM_H #ifdef __WATCOMC__ #ifndef VALIDATE #define __HAVE_INLINE_ASSEMBLER__ #endif u32 get_flags_asm(void); #pragma aux get_flags_asm = \ "pushf" \ "pop eax" \ value [eax] \ modify exact [eax]; u16 aaa_word_asm(u32 *flags,u16 d); #pragma aux aaa_word_asm = \ "push [edi]" \ "popf" \ "aaa" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] \ value [ax] \ modify exact [ax]; u16 aas_word_asm(u32 *flags,u16 d); #pragma aux aas_word_asm = \ "push [edi]" \ "popf" \ "aas" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] \ value [ax] \ modify exact [ax]; u16 aad_word_asm(u32 *flags,u16 d); #pragma aux aad_word_asm = \ "push [edi]" \ "popf" \ "aad" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] \ value [ax] \ modify exact [ax]; u16 aam_word_asm(u32 *flags,u8 d); #pragma aux aam_word_asm = \ "push [edi]" \ "popf" \ "aam" \ "pushf" \ "pop [edi]" \ parm [edi] [al] \ value [ax] \ modify exact [ax]; u8 adc_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux adc_byte_asm = \ "push [edi]" \ "popf" \ "adc al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 adc_word_asm(u32 *flags,u16 d, u16 s); #pragma aux adc_word_asm = \ "push [edi]" \ "popf" \ "adc ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 adc_long_asm(u32 *flags,u32 d, u32 s); #pragma aux adc_long_asm = \ "push [edi]" \ "popf" \ "adc eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; u8 add_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux add_byte_asm = \ "push [edi]" \ "popf" \ "add al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 add_word_asm(u32 *flags,u16 d, u16 s); #pragma aux add_word_asm = \ "push [edi]" \ "popf" \ "add ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 add_long_asm(u32 *flags,u32 d, u32 s); #pragma aux add_long_asm = \ "push [edi]" \ "popf" \ "add eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; u8 and_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux and_byte_asm = \ "push [edi]" \ "popf" \ "and al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 and_word_asm(u32 *flags,u16 d, u16 s); #pragma aux and_word_asm = \ "push [edi]" \ "popf" \ "and ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 and_long_asm(u32 *flags,u32 d, u32 s); #pragma aux and_long_asm = \ "push [edi]" \ "popf" \ "and eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux cmp_byte_asm = \ "push [edi]" \ "popf" \ "cmp al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 cmp_word_asm(u32 *flags,u16 d, u16 s); #pragma aux cmp_word_asm = \ "push [edi]" \ "popf" \ "cmp ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 cmp_long_asm(u32 *flags,u32 d, u32 s); #pragma aux cmp_long_asm = \ "push [edi]" \ "popf" \ "cmp eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; u8 daa_byte_asm(u32 *flags,u8 d); #pragma aux daa_byte_asm = \ "push [edi]" \ "popf" \ "daa" \ "pushf" \ "pop [edi]" \ parm [edi] [al] \ value [al] \ modify exact [al]; u8 das_byte_asm(u32 *flags,u8 d); #pragma aux das_byte_asm = \ "push [edi]" \ "popf" \ "das" \ "pushf" \ "pop [edi]" \ parm [edi] [al] \ value [al] \ modify exact [al]; u8 dec_byte_asm(u32 *flags,u8 d); #pragma aux dec_byte_asm = \ "push [edi]" \ "popf" \ "dec al" \ "pushf" \ "pop [edi]" \ parm [edi] [al] \ value [al] \ modify exact [al]; u16 dec_word_asm(u32 *flags,u16 d); #pragma aux dec_word_asm = \ "push [edi]" \ "popf" \ "dec ax" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] \ value [ax] \ modify exact [ax]; u32 dec_long_asm(u32 *flags,u32 d); #pragma aux dec_long_asm = \ "push [edi]" \ "popf" \ "dec eax" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] \ value [eax] \ modify exact [eax]; u8 inc_byte_asm(u32 *flags,u8 d); #pragma aux inc_byte_asm = \ "push [edi]" \ "popf" \ "inc al" \ "pushf" \ "pop [edi]" \ parm [edi] [al] \ value [al] \ modify exact [al]; u16 inc_word_asm(u32 *flags,u16 d); #pragma aux inc_word_asm = \ "push [edi]" \ "popf" \ "inc ax" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] \ value [ax] \ modify exact [ax]; u32 inc_long_asm(u32 *flags,u32 d); #pragma aux inc_long_asm = \ "push [edi]" \ "popf" \ "inc eax" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] \ value [eax] \ modify exact [eax]; u8 or_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux or_byte_asm = \ "push [edi]" \ "popf" \ "or al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 or_word_asm(u32 *flags,u16 d, u16 s); #pragma aux or_word_asm = \ "push [edi]" \ "popf" \ "or ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 or_long_asm(u32 *flags,u32 d, u32 s); #pragma aux or_long_asm = \ "push [edi]" \ "popf" \ "or eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; u8 neg_byte_asm(u32 *flags,u8 d); #pragma aux neg_byte_asm = \ "push [edi]" \ "popf" \ "neg al" \ "pushf" \ "pop [edi]" \ parm [edi] [al] \ value [al] \ modify exact [al]; u16 neg_word_asm(u32 *flags,u16 d); #pragma aux neg_word_asm = \ "push [edi]" \ "popf" \ "neg ax" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] \ value [ax] \ modify exact [ax]; u32 neg_long_asm(u32 *flags,u32 d); #pragma aux neg_long_asm = \ "push [edi]" \ "popf" \ "neg eax" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] \ value [eax] \ modify exact [eax]; u8 not_byte_asm(u32 *flags,u8 d); #pragma aux not_byte_asm = \ "push [edi]" \ "popf" \ "not al" \ "pushf" \ "pop [edi]" \ parm [edi] [al] \ value [al] \ modify exact [al]; u16 not_word_asm(u32 *flags,u16 d); #pragma aux not_word_asm = \ "push [edi]" \ "popf" \ "not ax" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] \ value [ax] \ modify exact [ax]; u32 not_long_asm(u32 *flags,u32 d); #pragma aux not_long_asm = \ "push [edi]" \ "popf" \ "not eax" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] \ value [eax] \ modify exact [eax]; u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux rcl_byte_asm = \ "push [edi]" \ "popf" \ "rcl al,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [cl] \ value [al] \ modify exact [al cl]; u16 rcl_word_asm(u32 *flags,u16 d, u8 s); #pragma aux rcl_word_asm = \ "push [edi]" \ "popf" \ "rcl ax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [cl] \ value [ax] \ modify exact [ax cl]; u32 rcl_long_asm(u32 *flags,u32 d, u8 s); #pragma aux rcl_long_asm = \ "push [edi]" \ "popf" \ "rcl eax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [cl] \ value [eax] \ modify exact [eax cl]; u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux rcr_byte_asm = \ "push [edi]" \ "popf" \ "rcr al,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [cl] \ value [al] \ modify exact [al cl]; u16 rcr_word_asm(u32 *flags,u16 d, u8 s); #pragma aux rcr_word_asm = \ "push [edi]" \ "popf" \ "rcr ax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [cl] \ value [ax] \ modify exact [ax cl]; u32 rcr_long_asm(u32 *flags,u32 d, u8 s); #pragma aux rcr_long_asm = \ "push [edi]" \ "popf" \ "rcr eax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [cl] \ value [eax] \ modify exact [eax cl]; u8 rol_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux rol_byte_asm = \ "push [edi]" \ "popf" \ "rol al,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [cl] \ value [al] \ modify exact [al cl]; u16 rol_word_asm(u32 *flags,u16 d, u8 s); #pragma aux rol_word_asm = \ "push [edi]" \ "popf" \ "rol ax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [cl] \ value [ax] \ modify exact [ax cl]; u32 rol_long_asm(u32 *flags,u32 d, u8 s); #pragma aux rol_long_asm = \ "push [edi]" \ "popf" \ "rol eax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [cl] \ value [eax] \ modify exact [eax cl]; u8 ror_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux ror_byte_asm = \ "push [edi]" \ "popf" \ "ror al,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [cl] \ value [al] \ modify exact [al cl]; u16 ror_word_asm(u32 *flags,u16 d, u8 s); #pragma aux ror_word_asm = \ "push [edi]" \ "popf" \ "ror ax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [cl] \ value [ax] \ modify exact [ax cl]; u32 ror_long_asm(u32 *flags,u32 d, u8 s); #pragma aux ror_long_asm = \ "push [edi]" \ "popf" \ "ror eax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [cl] \ value [eax] \ modify exact [eax cl]; u8 shl_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux shl_byte_asm = \ "push [edi]" \ "popf" \ "shl al,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [cl] \ value [al] \ modify exact [al cl]; u16 shl_word_asm(u32 *flags,u16 d, u8 s); #pragma aux shl_word_asm = \ "push [edi]" \ "popf" \ "shl ax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [cl] \ value [ax] \ modify exact [ax cl]; u32 shl_long_asm(u32 *flags,u32 d, u8 s); #pragma aux shl_long_asm = \ "push [edi]" \ "popf" \ "shl eax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [cl] \ value [eax] \ modify exact [eax cl]; u8 shr_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux shr_byte_asm = \ "push [edi]" \ "popf" \ "shr al,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [cl] \ value [al] \ modify exact [al cl]; u16 shr_word_asm(u32 *flags,u16 d, u8 s); #pragma aux shr_word_asm = \ "push [edi]" \ "popf" \ "shr ax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [cl] \ value [ax] \ modify exact [ax cl]; u32 shr_long_asm(u32 *flags,u32 d, u8 s); #pragma aux shr_long_asm = \ "push [edi]" \ "popf" \ "shr eax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [cl] \ value [eax] \ modify exact [eax cl]; u8 sar_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux sar_byte_asm = \ "push [edi]" \ "popf" \ "sar al,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [cl] \ value [al] \ modify exact [al cl]; u16 sar_word_asm(u32 *flags,u16 d, u8 s); #pragma aux sar_word_asm = \ "push [edi]" \ "popf" \ "sar ax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [cl] \ value [ax] \ modify exact [ax cl]; u32 sar_long_asm(u32 *flags,u32 d, u8 s); #pragma aux sar_long_asm = \ "push [edi]" \ "popf" \ "sar eax,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [cl] \ value [eax] \ modify exact [eax cl]; u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s); #pragma aux shld_word_asm = \ "push [edi]" \ "popf" \ "shld ax,dx,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [dx] [cl] \ value [ax] \ modify exact [ax dx cl]; u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); #pragma aux shld_long_asm = \ "push [edi]" \ "popf" \ "shld eax,edx,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [edx] [cl] \ value [eax] \ modify exact [eax edx cl]; u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s); #pragma aux shrd_word_asm = \ "push [edi]" \ "popf" \ "shrd ax,dx,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [dx] [cl] \ value [ax] \ modify exact [ax dx cl]; u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); #pragma aux shrd_long_asm = \ "push [edi]" \ "popf" \ "shrd eax,edx,cl" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [edx] [cl] \ value [eax] \ modify exact [eax edx cl]; u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux sbb_byte_asm = \ "push [edi]" \ "popf" \ "sbb al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 sbb_word_asm(u32 *flags,u16 d, u16 s); #pragma aux sbb_word_asm = \ "push [edi]" \ "popf" \ "sbb ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 sbb_long_asm(u32 *flags,u32 d, u32 s); #pragma aux sbb_long_asm = \ "push [edi]" \ "popf" \ "sbb eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; u8 sub_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux sub_byte_asm = \ "push [edi]" \ "popf" \ "sub al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 sub_word_asm(u32 *flags,u16 d, u16 s); #pragma aux sub_word_asm = \ "push [edi]" \ "popf" \ "sub ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 sub_long_asm(u32 *flags,u32 d, u32 s); #pragma aux sub_long_asm = \ "push [edi]" \ "popf" \ "sub eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; void test_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux test_byte_asm = \ "push [edi]" \ "popf" \ "test al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ modify exact [al bl]; void test_word_asm(u32 *flags,u16 d, u16 s); #pragma aux test_word_asm = \ "push [edi]" \ "popf" \ "test ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ modify exact [ax bx]; void test_long_asm(u32 *flags,u32 d, u32 s); #pragma aux test_long_asm = \ "push [edi]" \ "popf" \ "test eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ modify exact [eax ebx]; u8 xor_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux xor_byte_asm = \ "push [edi]" \ "popf" \ "xor al,bl" \ "pushf" \ "pop [edi]" \ parm [edi] [al] [bl] \ value [al] \ modify exact [al bl]; u16 xor_word_asm(u32 *flags,u16 d, u16 s); #pragma aux xor_word_asm = \ "push [edi]" \ "popf" \ "xor ax,bx" \ "pushf" \ "pop [edi]" \ parm [edi] [ax] [bx] \ value [ax] \ modify exact [ax bx]; u32 xor_long_asm(u32 *flags,u32 d, u32 s); #pragma aux xor_long_asm = \ "push [edi]" \ "popf" \ "xor eax,ebx" \ "pushf" \ "pop [edi]" \ parm [edi] [eax] [ebx] \ value [eax] \ modify exact [eax ebx]; void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); #pragma aux imul_byte_asm = \ "push [edi]" \ "popf" \ "imul bl" \ "pushf" \ "pop [edi]" \ "mov [esi],ax" \ parm [edi] [esi] [al] [bl] \ modify exact [esi ax bl]; void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); #pragma aux imul_word_asm = \ "push [edi]" \ "popf" \ "imul bx" \ "pushf" \ "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [bx]\ modify exact [esi edi ax bx dx]; void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); #pragma aux imul_long_asm = \ "push [edi]" \ "popf" \ "imul ebx" \ "pushf" \ "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [ebx] \ modify exact [esi edi eax ebx edx]; void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); #pragma aux mul_byte_asm = \ "push [edi]" \ "popf" \ "mul bl" \ "pushf" \ "pop [edi]" \ "mov [esi],ax" \ parm [edi] [esi] [al] [bl] \ modify exact [esi ax bl]; void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); #pragma aux mul_word_asm = \ "push [edi]" \ "popf" \ "mul bx" \ "pushf" \ "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [bx]\ modify exact [esi edi ax bx dx]; void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); #pragma aux mul_long_asm = \ "push [edi]" \ "popf" \ "mul ebx" \ "pushf" \ "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [ebx] \ modify exact [esi edi eax ebx edx]; void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); #pragma aux idiv_byte_asm = \ "push [edi]" \ "popf" \ "idiv bl" \ "pushf" \ "pop [edi]" \ "mov [esi],al" \ "mov [ecx],ah" \ parm [edi] [esi] [ecx] [ax] [bl]\ modify exact [esi edi ax bl]; void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); #pragma aux idiv_word_asm = \ "push [edi]" \ "popf" \ "idiv bx" \ "pushf" \ "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [dx] [bx]\ modify exact [esi edi ax dx bx]; void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); #pragma aux idiv_long_asm = \ "push [edi]" \ "popf" \ "idiv ebx" \ "pushf" \ "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ modify exact [esi edi eax edx ebx]; void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); #pragma aux div_byte_asm = \ "push [edi]" \ "popf" \ "div bl" \ "pushf" \ "pop [edi]" \ "mov [esi],al" \ "mov [ecx],ah" \ parm [edi] [esi] [ecx] [ax] [bl]\ modify exact [esi edi ax bl]; void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); #pragma aux div_word_asm = \ "push [edi]" \ "popf" \ "div bx" \ "pushf" \ "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [dx] [bx]\ modify exact [esi edi ax dx bx]; void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); #pragma aux div_long_asm = \ "push [edi]" \ "popf" \ "div ebx" \ "pushf" \ "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ modify exact [esi edi eax edx ebx]; #endif #endif /* __X86EMU_PRIM_ASM_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/prim_ops.h0000644000000000000000000002312710410136571020112 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for primitive operation functions. * ****************************************************************************/ #ifndef __X86EMU_PRIM_OPS_H #define __X86EMU_PRIM_OPS_H #include "x86emu/prim_asm.h" #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif u16 aaa_word (u16 d); u16 aas_word (u16 d); u16 aad_word (u16 d); u16 aam_word (u8 d); u8 adc_byte (u8 d, u8 s); u16 adc_word (u16 d, u16 s); u32 adc_long (u32 d, u32 s); u8 add_byte (u8 d, u8 s); u16 add_word (u16 d, u16 s); u32 add_long (u32 d, u32 s); u8 and_byte (u8 d, u8 s); u16 and_word (u16 d, u16 s); u32 and_long (u32 d, u32 s); u8 cmp_byte (u8 d, u8 s); u16 cmp_word (u16 d, u16 s); u32 cmp_long (u32 d, u32 s); u8 daa_byte (u8 d); u8 das_byte (u8 d); u8 dec_byte (u8 d); u16 dec_word (u16 d); u32 dec_long (u32 d); u8 inc_byte (u8 d); u16 inc_word (u16 d); u32 inc_long (u32 d); u8 or_byte (u8 d, u8 s); u16 or_word (u16 d, u16 s); u32 or_long (u32 d, u32 s); u8 neg_byte (u8 s); u16 neg_word (u16 s); u32 neg_long (u32 s); u8 not_byte (u8 s); u16 not_word (u16 s); u32 not_long (u32 s); u8 rcl_byte (u8 d, u8 s); u16 rcl_word (u16 d, u8 s); u32 rcl_long (u32 d, u8 s); u8 rcr_byte (u8 d, u8 s); u16 rcr_word (u16 d, u8 s); u32 rcr_long (u32 d, u8 s); u8 rol_byte (u8 d, u8 s); u16 rol_word (u16 d, u8 s); u32 rol_long (u32 d, u8 s); u8 ror_byte (u8 d, u8 s); u16 ror_word (u16 d, u8 s); u32 ror_long (u32 d, u8 s); u8 shl_byte (u8 d, u8 s); u16 shl_word (u16 d, u8 s); u32 shl_long (u32 d, u8 s); u8 shr_byte (u8 d, u8 s); u16 shr_word (u16 d, u8 s); u32 shr_long (u32 d, u8 s); u8 sar_byte (u8 d, u8 s); u16 sar_word (u16 d, u8 s); u32 sar_long (u32 d, u8 s); u16 shld_word (u16 d, u16 fill, u8 s); u32 shld_long (u32 d, u32 fill, u8 s); u16 shrd_word (u16 d, u16 fill, u8 s); u32 shrd_long (u32 d, u32 fill, u8 s); u8 sbb_byte (u8 d, u8 s); u16 sbb_word (u16 d, u16 s); u32 sbb_long (u32 d, u32 s); u8 sub_byte (u8 d, u8 s); u16 sub_word (u16 d, u16 s); u32 sub_long (u32 d, u32 s); void test_byte (u8 d, u8 s); void test_word (u16 d, u16 s); void test_long (u32 d, u32 s); u8 xor_byte (u8 d, u8 s); u16 xor_word (u16 d, u16 s); u32 xor_long (u32 d, u32 s); void imul_byte (u8 s); void imul_word (u16 s); void imul_long (u32 s); void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); void mul_byte (u8 s); void mul_word (u16 s); void mul_long (u32 s); void idiv_byte (u8 s); void idiv_word (u16 s); void idiv_long (u32 s); void div_byte (u8 s); void div_word (u16 s); void div_long (u32 s); void ins (int size); void outs (int size); u16 mem_access_word (int addr); void push_word (u16 w); void push_long (u32 w); u16 pop_word (void); u32 pop_long (void); #if defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM) #define aaa_word(d) aaa_word_asm(&M.x86.R_EFLG,d) #define aas_word(d) aas_word_asm(&M.x86.R_EFLG,d) #define aad_word(d) aad_word_asm(&M.x86.R_EFLG,d) #define aam_word(d) aam_word_asm(&M.x86.R_EFLG,d) #define adc_byte(d,s) adc_byte_asm(&M.x86.R_EFLG,d,s) #define adc_word(d,s) adc_word_asm(&M.x86.R_EFLG,d,s) #define adc_long(d,s) adc_long_asm(&M.x86.R_EFLG,d,s) #define add_byte(d,s) add_byte_asm(&M.x86.R_EFLG,d,s) #define add_word(d,s) add_word_asm(&M.x86.R_EFLG,d,s) #define add_long(d,s) add_long_asm(&M.x86.R_EFLG,d,s) #define and_byte(d,s) and_byte_asm(&M.x86.R_EFLG,d,s) #define and_word(d,s) and_word_asm(&M.x86.R_EFLG,d,s) #define and_long(d,s) and_long_asm(&M.x86.R_EFLG,d,s) #define cmp_byte(d,s) cmp_byte_asm(&M.x86.R_EFLG,d,s) #define cmp_word(d,s) cmp_word_asm(&M.x86.R_EFLG,d,s) #define cmp_long(d,s) cmp_long_asm(&M.x86.R_EFLG,d,s) #define daa_byte(d) daa_byte_asm(&M.x86.R_EFLG,d) #define das_byte(d) das_byte_asm(&M.x86.R_EFLG,d) #define dec_byte(d) dec_byte_asm(&M.x86.R_EFLG,d) #define dec_word(d) dec_word_asm(&M.x86.R_EFLG,d) #define dec_long(d) dec_long_asm(&M.x86.R_EFLG,d) #define inc_byte(d) inc_byte_asm(&M.x86.R_EFLG,d) #define inc_word(d) inc_word_asm(&M.x86.R_EFLG,d) #define inc_long(d) inc_long_asm(&M.x86.R_EFLG,d) #define or_byte(d,s) or_byte_asm(&M.x86.R_EFLG,d,s) #define or_word(d,s) or_word_asm(&M.x86.R_EFLG,d,s) #define or_long(d,s) or_long_asm(&M.x86.R_EFLG,d,s) #define neg_byte(s) neg_byte_asm(&M.x86.R_EFLG,s) #define neg_word(s) neg_word_asm(&M.x86.R_EFLG,s) #define neg_long(s) neg_long_asm(&M.x86.R_EFLG,s) #define not_byte(s) not_byte_asm(&M.x86.R_EFLG,s) #define not_word(s) not_word_asm(&M.x86.R_EFLG,s) #define not_long(s) not_long_asm(&M.x86.R_EFLG,s) #define rcl_byte(d,s) rcl_byte_asm(&M.x86.R_EFLG,d,s) #define rcl_word(d,s) rcl_word_asm(&M.x86.R_EFLG,d,s) #define rcl_long(d,s) rcl_long_asm(&M.x86.R_EFLG,d,s) #define rcr_byte(d,s) rcr_byte_asm(&M.x86.R_EFLG,d,s) #define rcr_word(d,s) rcr_word_asm(&M.x86.R_EFLG,d,s) #define rcr_long(d,s) rcr_long_asm(&M.x86.R_EFLG,d,s) #define rol_byte(d,s) rol_byte_asm(&M.x86.R_EFLG,d,s) #define rol_word(d,s) rol_word_asm(&M.x86.R_EFLG,d,s) #define rol_long(d,s) rol_long_asm(&M.x86.R_EFLG,d,s) #define ror_byte(d,s) ror_byte_asm(&M.x86.R_EFLG,d,s) #define ror_word(d,s) ror_word_asm(&M.x86.R_EFLG,d,s) #define ror_long(d,s) ror_long_asm(&M.x86.R_EFLG,d,s) #define shl_byte(d,s) shl_byte_asm(&M.x86.R_EFLG,d,s) #define shl_word(d,s) shl_word_asm(&M.x86.R_EFLG,d,s) #define shl_long(d,s) shl_long_asm(&M.x86.R_EFLG,d,s) #define shr_byte(d,s) shr_byte_asm(&M.x86.R_EFLG,d,s) #define shr_word(d,s) shr_word_asm(&M.x86.R_EFLG,d,s) #define shr_long(d,s) shr_long_asm(&M.x86.R_EFLG,d,s) #define sar_byte(d,s) sar_byte_asm(&M.x86.R_EFLG,d,s) #define sar_word(d,s) sar_word_asm(&M.x86.R_EFLG,d,s) #define sar_long(d,s) sar_long_asm(&M.x86.R_EFLG,d,s) #define shld_word(d,fill,s) shld_word_asm(&M.x86.R_EFLG,d,fill,s) #define shld_long(d,fill,s) shld_long_asm(&M.x86.R_EFLG,d,fill,s) #define shrd_word(d,fill,s) shrd_word_asm(&M.x86.R_EFLG,d,fill,s) #define shrd_long(d,fill,s) shrd_long_asm(&M.x86.R_EFLG,d,fill,s) #define sbb_byte(d,s) sbb_byte_asm(&M.x86.R_EFLG,d,s) #define sbb_word(d,s) sbb_word_asm(&M.x86.R_EFLG,d,s) #define sbb_long(d,s) sbb_long_asm(&M.x86.R_EFLG,d,s) #define sub_byte(d,s) sub_byte_asm(&M.x86.R_EFLG,d,s) #define sub_word(d,s) sub_word_asm(&M.x86.R_EFLG,d,s) #define sub_long(d,s) sub_long_asm(&M.x86.R_EFLG,d,s) #define test_byte(d,s) test_byte_asm(&M.x86.R_EFLG,d,s) #define test_word(d,s) test_word_asm(&M.x86.R_EFLG,d,s) #define test_long(d,s) test_long_asm(&M.x86.R_EFLG,d,s) #define xor_byte(d,s) xor_byte_asm(&M.x86.R_EFLG,d,s) #define xor_word(d,s) xor_word_asm(&M.x86.R_EFLG,d,s) #define xor_long(d,s) xor_long_asm(&M.x86.R_EFLG,d,s) #define imul_byte(s) imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) #define imul_word(s) imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) #define imul_long(s) imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) #define imul_long_direct(res_lo,res_hi,d,s) imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s) #define mul_byte(s) mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) #define mul_word(s) mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) #define mul_long(s) mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) #define idiv_byte(s) idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) #define idiv_word(s) idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) #define idiv_long(s) idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) #define div_byte(s) div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) #define div_word(s) div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) #define div_long(s) div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) #endif #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_PRIM_OPS_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/ops.h0000644000000000000000000000356710410136571017071 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for operand decoding functions. * ****************************************************************************/ #ifndef __X86EMU_OPS_H #define __X86EMU_OPS_H extern void (*x86emu_optab[0x100])(u8 op1); extern void (*x86emu_optab2[0x100])(u8 op2); #endif /* __X86EMU_OPS_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/decode.h0000644000000000000000000000711710410136571017506 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for instruction decoding logic. * ****************************************************************************/ #ifndef __X86EMU_DECODE_H #define __X86EMU_DECODE_H /*---------------------- Macros and type definitions ----------------------*/ /* Instruction Decoding Stuff */ #define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) #define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) #define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) #define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) #define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK /*-------------------------- Function Prototypes --------------------------*/ #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif void x86emu_intr_raise (u8 type); void fetch_decode_modrm (int *mod,int *regh,int *regl); u8 fetch_byte_imm (void); u16 fetch_word_imm (void); u32 fetch_long_imm (void); u8 fetch_data_byte (uint offset); u8 fetch_data_byte_abs (uint segment, uint offset); u16 fetch_data_word (uint offset); u16 fetch_data_word_abs (uint segment, uint offset); u32 fetch_data_long (uint offset); u32 fetch_data_long_abs (uint segment, uint offset); void store_data_byte (uint offset, u8 val); void store_data_byte_abs (uint segment, uint offset, u8 val); void store_data_word (uint offset, u16 val); void store_data_word_abs (uint segment, uint offset, u16 val); void store_data_long (uint offset, u32 val); void store_data_long_abs (uint segment, uint offset, u32 val); u8* decode_rm_byte_register(int reg); u16* decode_rm_word_register(int reg); u32* decode_rm_long_register(int reg); u16* decode_rm_seg_register(int reg); u32 decode_rm00_address(int rm); u32 decode_rm01_address(int rm); u32 decode_rm10_address(int rm); u32 decode_sib_address(int sib, int mod); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_DECODE_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/x86emu/fpu_regs.h0000644000000000000000000000733010410136571020072 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for FPU register definitions. * ****************************************************************************/ #ifndef __X86EMU_FPU_REGS_H #define __X86EMU_FPU_REGS_H #ifdef X86_FPU_SUPPORT /* Basic 8087 register can hold any of the following values: */ union x86_fpu_reg_u { s8 tenbytes[10]; double dval; float fval; s16 sval; s32 lval; }; struct x86_fpu_reg { union x86_fpu_reg_u reg; char tag; }; /* * Since we are not going to worry about the problems of aliasing * registers, every time a register is modified, its result type is * set in the tag fields for that register. If some operation * attempts to access the type in a way inconsistent with its current * storage format, then we flag the operation. If common, we'll * attempt the conversion. */ #define X86_FPU_VALID 0x80 #define X86_FPU_REGTYP(r) ((r) & 0x7F) #define X86_FPU_WORD 0x0 #define X86_FPU_SHORT 0x1 #define X86_FPU_LONG 0x2 #define X86_FPU_FLOAT 0x3 #define X86_FPU_DOUBLE 0x4 #define X86_FPU_LDBL 0x5 #define X86_FPU_BSD 0x6 #define X86_FPU_STKTOP 0 struct x86_fpu_registers { struct x86_fpu_reg x86_fpu_stack[8]; int x86_fpu_flags; int x86_fpu_config; /* rounding modes, etc. */ short x86_fpu_tos, x86_fpu_bos; }; /* * There are two versions of the following macro. * * One version is for opcode D9, for which there are more than 32 * instructions encoded in the second byte of the opcode. * * The other version, deals with all the other 7 i87 opcodes, for * which there are only 32 strings needed to describe the * instructions. */ #endif /* X86_FPU_SUPPORT */ #ifdef DEBUG # define DECODE_PRINTINSTR32(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<3)+(rh)]); # define DECODE_PRINTINSTR256(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); #else # define DECODE_PRINTINSTR32(t,mod,rh,rl) # define DECODE_PRINTINSTR256(t,mod,rh,rl) #endif #endif /* __X86EMU_FPU_REGS_H */ xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/validate.c0000644000000000000000000012416010410136571016711 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: Watcom C 10.6 or later * Environment: 32-bit DOS * Developer: Kendall Bennett * * Description: Program to validate the x86 emulator library for * correctness. We run the emulator primitive operations * functions against the real x86 CPU, and compare the result * and flags to ensure correctness. * * We use inline assembler to compile and build this program. * ****************************************************************************/ #include #include #include #include #include "x86emu.h" #include "x86emu/prim_asm.h" /*-------------------------- Implementation -------------------------------*/ #define true 1 #define false 0 #define ALL_FLAGS (F_CF | F_PF | F_AF | F_ZF | F_SF | F_OF) #define VAL_START_BINARY(parm_type,res_type,dmax,smax,dincr,sincr) \ { \ parm_type d,s; \ res_type r,r_asm; \ ulong flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < dmax; d += dincr) { \ for (s = 0; s < smax; s += sincr) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { #define VAL_TEST_BINARY(name) \ r_asm = name##_asm(&flags,d,s); \ r = name(d,s); \ if (r != r_asm || M.x86.R_EFLG != flags) \ failed = true; \ if (failed || trace) { #define VAL_TEST_BINARY_VOID(name) \ name##_asm(&flags,d,s); \ name(d,s); \ r = r_asm = 0; \ if (M.x86.R_EFLG != flags) \ failed = true; \ if (failed || trace) { #define VAL_FAIL_BYTE_BYTE_BINARY(name) \ if (failed) \ printk("fail\n"); \ printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_FAIL_WORD_WORD_BINARY(name) \ if (failed) \ printk("fail\n"); \ printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_FAIL_LONG_LONG_BINARY(name) \ if (failed) \ printk("fail\n"); \ printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_END_BINARY() \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_BYTE_BYTE_BINARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ VAL_TEST_BINARY(name) \ VAL_FAIL_BYTE_BYTE_BINARY(name) \ VAL_END_BINARY() #define VAL_WORD_WORD_BINARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ VAL_TEST_BINARY(name) \ VAL_FAIL_WORD_WORD_BINARY(name) \ VAL_END_BINARY() #define VAL_LONG_LONG_BINARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ VAL_TEST_BINARY(name) \ VAL_FAIL_LONG_LONG_BINARY(name) \ VAL_END_BINARY() #define VAL_VOID_BYTE_BINARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ VAL_TEST_BINARY_VOID(name) \ VAL_FAIL_BYTE_BYTE_BINARY(name) \ VAL_END_BINARY() #define VAL_VOID_WORD_BINARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ VAL_TEST_BINARY_VOID(name) \ VAL_FAIL_WORD_WORD_BINARY(name) \ VAL_END_BINARY() #define VAL_VOID_LONG_BINARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ VAL_TEST_BINARY_VOID(name) \ VAL_FAIL_LONG_LONG_BINARY(name) \ VAL_END_BINARY() #define VAL_BYTE_ROTATE(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u8,u8,0xFF,8,1,1) \ VAL_TEST_BINARY(name) \ VAL_FAIL_BYTE_BYTE_BINARY(name) \ VAL_END_BINARY() #define VAL_WORD_ROTATE(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u16,u16,0xFF00,16,0x100,1) \ VAL_TEST_BINARY(name) \ VAL_FAIL_WORD_WORD_BINARY(name) \ VAL_END_BINARY() #define VAL_LONG_ROTATE(name) \ printk("Validating %s ... ", #name); \ VAL_START_BINARY(u32,u32,0xFF000000,32,0x1000000,1) \ VAL_TEST_BINARY(name) \ VAL_FAIL_LONG_LONG_BINARY(name) \ VAL_END_BINARY() #define VAL_START_TERNARY(parm_type,res_type,dmax,smax,dincr,sincr,maxshift)\ { \ parm_type d,s; \ res_type r,r_asm; \ u8 shift; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < dmax; d += dincr) { \ for (s = 0; s < smax; s += sincr) { \ for (shift = 0; shift < maxshift; shift += 1) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { #define VAL_TEST_TERNARY(name) \ r_asm = name##_asm(&flags,d,s,shift); \ r = name(d,s,shift); \ if (r != r_asm || M.x86.R_EFLG != flags) \ failed = true; \ if (failed || trace) { #define VAL_FAIL_WORD_WORD_TERNARY(name) \ if (failed) \ printk("fail\n"); \ printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_FAIL_LONG_LONG_TERNARY(name) \ if (failed) \ printk("fail\n"); \ printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_END_TERNARY() \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_WORD_ROTATE_DBL(name) \ printk("Validating %s ... ", #name); \ VAL_START_TERNARY(u16,u16,0xFF00,0xFF00,0x100,0x100,16) \ VAL_TEST_TERNARY(name) \ VAL_FAIL_WORD_WORD_TERNARY(name) \ VAL_END_TERNARY() #define VAL_LONG_ROTATE_DBL(name) \ printk("Validating %s ... ", #name); \ VAL_START_TERNARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000,32) \ VAL_TEST_TERNARY(name) \ VAL_FAIL_LONG_LONG_TERNARY(name) \ VAL_END_TERNARY() #define VAL_START_UNARY(parm_type,max,incr) \ { \ parm_type d,r,r_asm; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < max; d += incr) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { #define VAL_TEST_UNARY(name) \ r_asm = name##_asm(&flags,d); \ r = name(d); \ if (r != r_asm || M.x86.R_EFLG != flags) { \ failed = true; #define VAL_FAIL_BYTE_UNARY(name) \ printk("fail\n"); \ printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_FAIL_WORD_UNARY(name) \ printk("fail\n"); \ printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_FAIL_LONG_UNARY(name) \ printk("fail\n"); \ printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); #define VAL_END_UNARY() \ } \ M.x86.R_EFLG = inflags = flags = def_flags | ALL_FLAGS; \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_BYTE_UNARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_UNARY(u8,0xFF,0x1) \ VAL_TEST_UNARY(name) \ VAL_FAIL_BYTE_UNARY(name) \ VAL_END_UNARY() #define VAL_WORD_UNARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_UNARY(u16,0xFF00,0x100) \ VAL_TEST_UNARY(name) \ VAL_FAIL_WORD_UNARY(name) \ VAL_END_UNARY() #define VAL_WORD_BYTE_UNARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_UNARY(u16,0xFF,0x1) \ VAL_TEST_UNARY(name) \ VAL_FAIL_WORD_UNARY(name) \ VAL_END_UNARY() #define VAL_LONG_UNARY(name) \ printk("Validating %s ... ", #name); \ VAL_START_UNARY(u32,0xFF000000,0x1000000) \ VAL_TEST_UNARY(name) \ VAL_FAIL_LONG_UNARY(name) \ VAL_END_UNARY() #define VAL_BYTE_MUL(name) \ printk("Validating %s ... ", #name); \ { \ u8 d,s; \ u16 r,r_asm; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < 0xFF; d += 1) { \ for (s = 0; s < 0xFF; s += 1) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { \ name##_asm(&flags,&r_asm,d,s); \ M.x86.R_AL = d; \ name(s); \ r = M.x86.R_AX; \ if (r != r_asm || M.x86.R_EFLG != flags) \ failed = true; \ if (failed || trace) { \ if (failed) \ printk("fail\n"); \ printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_WORD_MUL(name) \ printk("Validating %s ... ", #name); \ { \ u16 d,s; \ u16 r_lo,r_asm_lo; \ u16 r_hi,r_asm_hi; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < 0xFF00; d += 0x100) { \ for (s = 0; s < 0xFF00; s += 0x100) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { \ name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ M.x86.R_AX = d; \ name(s); \ r_lo = M.x86.R_AX; \ r_hi = M.x86.R_DX; \ if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ failed = true; \ if (failed || trace) { \ if (failed) \ printk("fail\n"); \ printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_LONG_MUL(name) \ printk("Validating %s ... ", #name); \ { \ u32 d,s; \ u32 r_lo,r_asm_lo; \ u32 r_hi,r_asm_hi; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < 0xFF000000; d += 0x1000000) { \ for (s = 0; s < 0xFF000000; s += 0x1000000) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { \ name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ M.x86.R_EAX = d; \ name(s); \ r_lo = M.x86.R_EAX; \ r_hi = M.x86.R_EDX; \ if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ failed = true; \ if (failed || trace) { \ if (failed) \ printk("fail\n"); \ printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_BYTE_DIV(name) \ printk("Validating %s ... ", #name); \ { \ u16 d,s; \ u8 r_quot,r_rem,r_asm_quot,r_asm_rem; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < 0xFF00; d += 0x100) { \ for (s = 1; s < 0xFF; s += 1) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { \ M.x86.intr = 0; \ M.x86.R_AX = d; \ name(s); \ r_quot = M.x86.R_AL; \ r_rem = M.x86.R_AH; \ if (M.x86.intr & INTR_SYNCH) \ continue; \ name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,s); \ if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ failed = true; \ if (failed || trace) { \ if (failed) \ printk("fail\n"); \ printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_WORD_DIV(name) \ printk("Validating %s ... ", #name); \ { \ u32 d,s; \ u16 r_quot,r_rem,r_asm_quot,r_asm_rem; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < 0xFF000000; d += 0x1000000) { \ for (s = 0x100; s < 0xFF00; s += 0x100) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { \ M.x86.intr = 0; \ M.x86.R_AX = d & 0xFFFF; \ M.x86.R_DX = d >> 16; \ name(s); \ r_quot = M.x86.R_AX; \ r_rem = M.x86.R_DX; \ if (M.x86.intr & INTR_SYNCH) \ continue; \ name##_asm(&flags,&r_asm_quot,&r_asm_rem,d & 0xFFFF,d >> 16,s);\ if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ failed = true; \ if (failed || trace) { \ if (failed) \ printk("fail\n"); \ printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } #define VAL_LONG_DIV(name) \ printk("Validating %s ... ", #name); \ { \ u32 d,s; \ u32 r_quot,r_rem,r_asm_quot,r_asm_rem; \ u32 flags,inflags; \ int f,failed = false; \ char buf1[80],buf2[80]; \ for (d = 0; d < 0xFF000000; d += 0x1000000) { \ for (s = 0x100; s < 0xFF00; s += 0x100) { \ M.x86.R_EFLG = inflags = flags = def_flags; \ for (f = 0; f < 2; f++) { \ M.x86.intr = 0; \ M.x86.R_EAX = d; \ M.x86.R_EDX = 0; \ name(s); \ r_quot = M.x86.R_EAX; \ r_rem = M.x86.R_EDX; \ if (M.x86.intr & INTR_SYNCH) \ continue; \ name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,0,s); \ if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ failed = true; \ if (failed || trace) { \ if (failed) \ printk("fail\n"); \ printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ r_quot, r_rem, #name, 0, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ r_asm_quot, r_asm_rem, #name"_asm", 0, d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ } \ M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (failed) \ break; \ } \ if (!failed) \ printk("passed\n"); \ } void printk(const char *fmt, ...) { va_list argptr; va_start(argptr, fmt); vfprintf(stdout, fmt, argptr); fflush(stdout); va_end(argptr); } char * print_flags(char *buf,ulong flags) { char *separator = ""; buf[0] = 0; if (flags & F_CF) { strcat(buf,separator); strcat(buf,"CF"); separator = ","; } if (flags & F_PF) { strcat(buf,separator); strcat(buf,"PF"); separator = ","; } if (flags & F_AF) { strcat(buf,separator); strcat(buf,"AF"); separator = ","; } if (flags & F_ZF) { strcat(buf,separator); strcat(buf,"ZF"); separator = ","; } if (flags & F_SF) { strcat(buf,separator); strcat(buf,"SF"); separator = ","; } if (flags & F_OF) { strcat(buf,separator); strcat(buf,"OF"); separator = ","; } if (separator[0] == 0) strcpy(buf,"None"); return buf; } int main(int argc) { ulong def_flags; int trace = false; if (argc > 1) trace = true; memset(&M, 0, sizeof(M)); def_flags = get_flags_asm() & ~ALL_FLAGS; VAL_WORD_UNARY(aaa_word); VAL_WORD_UNARY(aas_word); VAL_WORD_UNARY(aad_word); VAL_WORD_UNARY(aam_word); VAL_BYTE_BYTE_BINARY(adc_byte); VAL_WORD_WORD_BINARY(adc_word); VAL_LONG_LONG_BINARY(adc_long); VAL_BYTE_BYTE_BINARY(add_byte); VAL_WORD_WORD_BINARY(add_word); VAL_LONG_LONG_BINARY(add_long); VAL_BYTE_BYTE_BINARY(and_byte); VAL_WORD_WORD_BINARY(and_word); VAL_LONG_LONG_BINARY(and_long); VAL_BYTE_BYTE_BINARY(cmp_byte); VAL_WORD_WORD_BINARY(cmp_word); VAL_LONG_LONG_BINARY(cmp_long); VAL_BYTE_UNARY(daa_byte); VAL_BYTE_UNARY(das_byte); // Fails for 0x9A (out of range anyway) VAL_BYTE_UNARY(dec_byte); VAL_WORD_UNARY(dec_word); VAL_LONG_UNARY(dec_long); VAL_BYTE_UNARY(inc_byte); VAL_WORD_UNARY(inc_word); VAL_LONG_UNARY(inc_long); VAL_BYTE_BYTE_BINARY(or_byte); VAL_WORD_WORD_BINARY(or_word); VAL_LONG_LONG_BINARY(or_long); VAL_BYTE_UNARY(neg_byte); VAL_WORD_UNARY(neg_word); VAL_LONG_UNARY(neg_long); VAL_BYTE_UNARY(not_byte); VAL_WORD_UNARY(not_word); VAL_LONG_UNARY(not_long); VAL_BYTE_ROTATE(rcl_byte); VAL_WORD_ROTATE(rcl_word); VAL_LONG_ROTATE(rcl_long); VAL_BYTE_ROTATE(rcr_byte); VAL_WORD_ROTATE(rcr_word); VAL_LONG_ROTATE(rcr_long); VAL_BYTE_ROTATE(rol_byte); VAL_WORD_ROTATE(rol_word); VAL_LONG_ROTATE(rol_long); VAL_BYTE_ROTATE(ror_byte); VAL_WORD_ROTATE(ror_word); VAL_LONG_ROTATE(ror_long); VAL_BYTE_ROTATE(shl_byte); VAL_WORD_ROTATE(shl_word); VAL_LONG_ROTATE(shl_long); VAL_BYTE_ROTATE(shr_byte); VAL_WORD_ROTATE(shr_word); VAL_LONG_ROTATE(shr_long); VAL_BYTE_ROTATE(sar_byte); VAL_WORD_ROTATE(sar_word); VAL_LONG_ROTATE(sar_long); VAL_WORD_ROTATE_DBL(shld_word); VAL_LONG_ROTATE_DBL(shld_long); VAL_WORD_ROTATE_DBL(shrd_word); VAL_LONG_ROTATE_DBL(shrd_long); VAL_BYTE_BYTE_BINARY(sbb_byte); VAL_WORD_WORD_BINARY(sbb_word); VAL_LONG_LONG_BINARY(sbb_long); VAL_BYTE_BYTE_BINARY(sub_byte); VAL_WORD_WORD_BINARY(sub_word); VAL_LONG_LONG_BINARY(sub_long); VAL_BYTE_BYTE_BINARY(xor_byte); VAL_WORD_WORD_BINARY(xor_word); VAL_LONG_LONG_BINARY(xor_long); VAL_VOID_BYTE_BINARY(test_byte); VAL_VOID_WORD_BINARY(test_word); VAL_VOID_LONG_BINARY(test_long); VAL_BYTE_MUL(imul_byte); VAL_WORD_MUL(imul_word); VAL_LONG_MUL(imul_long); VAL_BYTE_MUL(mul_byte); VAL_WORD_MUL(mul_word); VAL_LONG_MUL(mul_long); VAL_BYTE_DIV(idiv_byte); VAL_WORD_DIV(idiv_word); VAL_LONG_DIV(idiv_long); VAL_BYTE_DIV(div_byte); VAL_WORD_DIV(div_word); VAL_LONG_DIV(div_long); return 0; } xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/ops2.c0000644000000000000000000024671610410136571016017 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: This file includes subroutines to implement the decoding * and emulation of all the x86 extended two-byte processor * instructions. * ****************************************************************************/ #include "x86emu/x86emui.h" /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** PARAMETERS: op1 - Instruction op code REMARKS: Handles illegal opcodes. ****************************************************************************/ static void x86emuOp2_illegal_op( u8 op2) { START_OF_INSTR(); DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", M.x86.R_CS, M.x86.R_IP-2,op2); HALT_SYS(); END_OF_INSTR(); } #define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) /**************************************************************************** REMARKS: Handles opcode 0x0f,0x80-0x8F ****************************************************************************/ static void x86emuOp2_long_jump(u8 op2) { s32 target; char *name = 0; int cond = 0; /* conditional jump to word offset. */ START_OF_INSTR(); switch (op2) { case 0x80: name = "JO\t"; cond = ACCESS_FLAG(F_OF); break; case 0x81: name = "JNO\t"; cond = !ACCESS_FLAG(F_OF); break; case 0x82: name = "JB\t"; cond = ACCESS_FLAG(F_CF); break; case 0x83: name = "JNB\t"; cond = !ACCESS_FLAG(F_CF); break; case 0x84: name = "JZ\t"; cond = ACCESS_FLAG(F_ZF); break; case 0x85: name = "JNZ\t"; cond = !ACCESS_FLAG(F_ZF); break; case 0x86: name = "JBE\t"; cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); break; case 0x87: name = "JNBE\t"; cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); break; case 0x88: name = "JS\t"; cond = ACCESS_FLAG(F_SF); break; case 0x89: name = "JNS\t"; cond = !ACCESS_FLAG(F_SF); break; case 0x8a: name = "JP\t"; cond = ACCESS_FLAG(F_PF); break; case 0x8b: name = "JNP\t"; cond = !ACCESS_FLAG(F_PF); break; case 0x8c: name = "JL\t"; cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); break; case 0x8d: name = "JNL\t"; cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); break; case 0x8e: name = "JLE\t"; cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || ACCESS_FLAG(F_ZF)); break; case 0x8f: name = "JNLE\t"; cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || ACCESS_FLAG(F_ZF)); break; } DECODE_PRINTF(name); (void)name; target = (s16) fetch_word_imm(); target += (s16) M.x86.R_IP; DECODE_PRINTF2("%04x\n", target); TRACE_AND_STEP(); if (cond) M.x86.R_IP = (u16)target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0x90-0x9F ****************************************************************************/ static void x86emuOp2_set_byte(u8 op2) { int mod, rl, rh; uint destoffset; u8 *destreg; char *name = 0; int cond = 0; START_OF_INSTR(); switch (op2) { case 0x90: name = "SETO\t"; cond = ACCESS_FLAG(F_OF); break; case 0x91: name = "SETNO\t"; cond = !ACCESS_FLAG(F_OF); break; case 0x92: name = "SETB\t"; cond = ACCESS_FLAG(F_CF); break; case 0x93: name = "SETNB\t"; cond = !ACCESS_FLAG(F_CF); break; case 0x94: name = "SETZ\t"; cond = ACCESS_FLAG(F_ZF); break; case 0x95: name = "SETNZ\t"; cond = !ACCESS_FLAG(F_ZF); break; case 0x96: name = "SETBE\t"; cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); break; case 0x97: name = "SETNBE\t"; cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); break; case 0x98: name = "SETS\t"; cond = ACCESS_FLAG(F_SF); break; case 0x99: name = "SETNS\t"; cond = !ACCESS_FLAG(F_SF); break; case 0x9a: name = "SETP\t"; cond = ACCESS_FLAG(F_PF); break; case 0x9b: name = "SETNP\t"; cond = !ACCESS_FLAG(F_PF); break; case 0x9c: name = "SETL\t"; cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); break; case 0x9d: name = "SETNL\t"; cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); break; case 0x9e: name = "SETLE\t"; cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || ACCESS_FLAG(F_ZF)); break; case 0x9f: name = "SETNLE\t"; cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || ACCESS_FLAG(F_ZF)); break; } DECODE_PRINTF(name); (void)name; FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); TRACE_AND_STEP(); store_data_byte(destoffset, cond ? 0x01 : 0x00); break; case 1: destoffset = decode_rm01_address(rl); TRACE_AND_STEP(); store_data_byte(destoffset, cond ? 0x01 : 0x00); break; case 2: destoffset = decode_rm10_address(rl); TRACE_AND_STEP(); store_data_byte(destoffset, cond ? 0x01 : 0x00); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); TRACE_AND_STEP(); *destreg = cond ? 0x01 : 0x00; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xa0 ****************************************************************************/ static void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tFS\n"); TRACE_AND_STEP(); push_word(M.x86.R_FS); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xa1 ****************************************************************************/ static void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("POP\tFS\n"); TRACE_AND_STEP(); M.x86.R_FS = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xa3 ****************************************************************************/ static void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; int bit,disp; START_OF_INSTR(); DECODE_PRINTF("BT\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval; u32 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); } else { u16 srcval; u16 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval; u32 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); } else { u16 srcval; u16 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval; u32 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); } else { u16 srcval; u16 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg,*shiftreg; srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); } else { u16 *srcreg,*shiftreg; srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xa4 ****************************************************************************/ static void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; u8 shift; START_OF_INSTR(); DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shld_long(destval,*shiftreg,shift); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shld_word(destval,*shiftreg,shift); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shld_long(destval,*shiftreg,shift); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shld_word(destval,*shiftreg,shift); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shld_long(destval,*shiftreg,shift); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shld_word(destval,*shiftreg,shift); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*shiftreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); *destreg = shld_long(*destreg,*shiftreg,shift); } else { u16 *destreg,*shiftreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); *destreg = shld_word(*destreg,*shiftreg,shift); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xa5 ****************************************************************************/ static void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shld_long(destval,*shiftreg,M.x86.R_CL); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shld_word(destval,*shiftreg,M.x86.R_CL); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shld_long(destval,*shiftreg,M.x86.R_CL); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shld_word(destval,*shiftreg,M.x86.R_CL); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shld_long(destval,*shiftreg,M.x86.R_CL); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shld_word(destval,*shiftreg,M.x86.R_CL); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*shiftreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); } else { u16 *destreg,*shiftreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xa8 ****************************************************************************/ static void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tGS\n"); TRACE_AND_STEP(); push_word(M.x86.R_GS); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xa9 ****************************************************************************/ static void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("POP\tGS\n"); TRACE_AND_STEP(); M.x86.R_GS = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } #if 0 /**************************************************************************** REMARKS: Handles opcode 0x0f,0xaa ****************************************************************************/ static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; int bit,disp; START_OF_INSTR(); DECODE_PRINTF("BTS\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval | mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, srcval | mask); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval | mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, srcval | mask); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval | mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, srcval | mask); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg,*shiftreg; u32 mask; srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; mask = (0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); *srcreg |= mask; } else { u16 *srcreg,*shiftreg; u16 mask; srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); *srcreg |= mask; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } #endif /**************************************************************************** REMARKS: Handles opcode 0x0f,0xac ****************************************************************************/ static void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; u8 shift; START_OF_INSTR(); DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shrd_long(destval,*shiftreg,shift); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shrd_word(destval,*shiftreg,shift); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shrd_long(destval,*shiftreg,shift); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shrd_word(destval,*shiftreg,shift); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shrd_long(destval,*shiftreg,shift); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shrd_word(destval,*shiftreg,shift); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*shiftreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); *destreg = shrd_long(*destreg,*shiftreg,shift); } else { u16 *destreg,*shiftreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); shift = fetch_byte_imm(); DECODE_PRINTF2("%d\n", shift); TRACE_AND_STEP(); *destreg = shrd_word(*destreg,*shiftreg,shift); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xad ****************************************************************************/ static void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shrd_long(destval,*shiftreg,M.x86.R_CL); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shrd_word(destval,*shiftreg,M.x86.R_CL); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shrd_long(destval,*shiftreg,M.x86.R_CL); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shrd_word(destval,*shiftreg,M.x86.R_CL); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_long(destoffset); destval = shrd_long(destval,*shiftreg,M.x86.R_CL); store_data_long(destoffset, destval); } else { u16 destval; u16 *shiftreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = fetch_data_word(destoffset); destval = shrd_word(destval,*shiftreg,M.x86.R_CL); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*shiftreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); } else { u16 *destreg,*shiftreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xaf ****************************************************************************/ static void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); TRACE_AND_STEP(); res = (s16)*destreg * (s16)srcval; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); TRACE_AND_STEP(); res = (s16)*destreg * (s16)srcval; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); TRACE_AND_STEP(); res = (s16)*destreg * (s16)srcval; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg,*srcreg; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); res = (s16)*destreg * (s16)*srcreg; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xb2 ****************************************************************************/ static void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rh, rl; u16 *dstreg; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("LSS\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_SS = fetch_data_word(srcoffset + 2); break; case 1: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_SS = fetch_data_word(srcoffset + 2); break; case 2: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_SS = fetch_data_word(srcoffset + 2); break; case 3: /* register to register */ /* UNDEFINED! */ TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xb3 ****************************************************************************/ static void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; int bit,disp; START_OF_INSTR(); DECODE_PRINTF("BTR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval & ~mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval & ~mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval & ~mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg,*shiftreg; u32 mask; srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; mask = (0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); *srcreg &= ~mask; } else { u16 *srcreg,*shiftreg; u16 mask; srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); *srcreg &= ~mask; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xb4 ****************************************************************************/ static void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rh, rl; u16 *dstreg; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("LFS\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_FS = fetch_data_word(srcoffset + 2); break; case 1: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_FS = fetch_data_word(srcoffset + 2); break; case 2: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_FS = fetch_data_word(srcoffset + 2); break; case 3: /* register to register */ /* UNDEFINED! */ TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xb5 ****************************************************************************/ static void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rh, rl; u16 *dstreg; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("LGS\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_GS = fetch_data_word(srcoffset + 2); break; case 1: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_GS = fetch_data_word(srcoffset + 2); break; case 2: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_GS = fetch_data_word(srcoffset + 2); break; case 3: /* register to register */ /* UNDEFINED! */ TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xb6 ****************************************************************************/ static void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u8 *srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; } else { u16 *destreg; u8 *srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xb7 ****************************************************************************/ static void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; u32 *destreg; u32 srcval; u16 *srcreg; START_OF_INSTR(); DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 1: destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 2: destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 3: /* register to register */ destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xba ****************************************************************************/ static void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; int bit; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); switch (rh) { case 4: DECODE_PRINTF("BT\t"); break; case 5: DECODE_PRINTF("BTS\t"); break; case 6: DECODE_PRINTF("BTR\t"); break; case 7: DECODE_PRINTF("BTC\t"); break; default: DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); HALT_SYS(); } switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, mask; u8 shift; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0x1F; srcval = fetch_data_long(srcoffset); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); switch (rh) { case 5: store_data_long(srcoffset, srcval | mask); break; case 6: store_data_long(srcoffset, srcval & ~mask); break; case 7: store_data_long(srcoffset, srcval ^ mask); break; default: break; } } else { u16 srcval, mask; u8 shift; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0xF; srcval = fetch_data_word(srcoffset); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); switch (rh) { case 5: store_data_word(srcoffset, srcval | mask); break; case 6: store_data_word(srcoffset, srcval & ~mask); break; case 7: store_data_word(srcoffset, srcval ^ mask); break; default: break; } } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, mask; u8 shift; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0x1F; srcval = fetch_data_long(srcoffset); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); switch (rh) { case 5: store_data_long(srcoffset, srcval | mask); break; case 6: store_data_long(srcoffset, srcval & ~mask); break; case 7: store_data_long(srcoffset, srcval ^ mask); break; default: break; } } else { u16 srcval, mask; u8 shift; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0xF; srcval = fetch_data_word(srcoffset); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); switch (rh) { case 5: store_data_word(srcoffset, srcval | mask); break; case 6: store_data_word(srcoffset, srcval & ~mask); break; case 7: store_data_word(srcoffset, srcval ^ mask); break; default: break; } } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, mask; u8 shift; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0x1F; srcval = fetch_data_long(srcoffset); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); switch (rh) { case 5: store_data_long(srcoffset, srcval | mask); break; case 6: store_data_long(srcoffset, srcval & ~mask); break; case 7: store_data_long(srcoffset, srcval ^ mask); break; default: break; } } else { u16 srcval, mask; u8 shift; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0xF; srcval = fetch_data_word(srcoffset); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); switch (rh) { case 5: store_data_word(srcoffset, srcval | mask); break; case 6: store_data_word(srcoffset, srcval & ~mask); break; case 7: store_data_word(srcoffset, srcval ^ mask); break; default: break; } } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg; u32 mask; u8 shift; srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0x1F; mask = (0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); switch (rh) { case 5: *srcreg |= mask; break; case 6: *srcreg &= ~mask; break; case 7: *srcreg ^= mask; break; default: break; } } else { u16 *srcreg; u16 mask; u8 shift; srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shift = fetch_byte_imm(); TRACE_AND_STEP(); bit = shift & 0xF; mask = (0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); switch (rh) { case 5: *srcreg |= mask; break; case 6: *srcreg &= ~mask; break; case 7: *srcreg ^= mask; break; default: break; } } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xbb ****************************************************************************/ static void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; int bit,disp; START_OF_INSTR(); DECODE_PRINTF("BTC\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval ^ mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval ^ mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval,mask; u32 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; disp = (s16)*shiftreg >> 5; srcval = fetch_data_long(srcoffset+disp); mask = (0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_long(srcoffset+disp, srcval ^ mask); } else { u16 srcval,mask; u16 *shiftreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; disp = (s16)*shiftreg >> 4; srcval = fetch_data_word(srcoffset+disp); mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(srcval & mask,F_CF); store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg,*shiftreg; u32 mask; srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0x1F; mask = (0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); *srcreg ^= mask; } else { u16 *srcreg,*shiftreg; u16 mask; srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); shiftreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); bit = *shiftreg & 0xF; mask = (u16)(0x1 << bit); CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); *srcreg ^= mask; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xbc ****************************************************************************/ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("BSF\n"); FETCH_DECODE_MODRM(mod, rh, rl); switch(mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, *dstreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 32; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 16; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, *dstreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 32; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 16; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, *dstreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 32; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 16; (*dstreg)++) if ((srcval >> *dstreg) & 1) break; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg, *dstreg; srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); for(*dstreg = 0; *dstreg < 32; (*dstreg)++) if ((*srcreg >> *dstreg) & 1) break; } else { u16 *srcreg, *dstreg; srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); for(*dstreg = 0; *dstreg < 16; (*dstreg)++) if ((*srcreg >> *dstreg) & 1) break; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xbd ****************************************************************************/ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("BSF\n"); FETCH_DECODE_MODRM(mod, rh, rl); switch(mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, *dstreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 31; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; srcoffset = decode_rm00_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 15; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, *dstreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 31; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; srcoffset = decode_rm01_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 15; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 srcval, *dstreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_long(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 31; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } else { u16 srcval, *dstreg; srcoffset = decode_rm10_address(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); srcval = fetch_data_word(srcoffset); CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 15; *dstreg > 0; (*dstreg)--) if ((srcval >> *dstreg) & 1) break; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg, *dstreg; srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); for(*dstreg = 31; *dstreg > 0; (*dstreg)--) if ((*srcreg >> *dstreg) & 1) break; } else { u16 *srcreg, *dstreg; srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); for(*dstreg = 15; *dstreg > 0; (*dstreg)--) if ((*srcreg >> *dstreg) & 1) break; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xbe ****************************************************************************/ static void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = (s32)((s8)fetch_data_byte(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = (s16)((s8)fetch_data_byte(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = (s32)((s8)fetch_data_byte(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = (s16)((s8)fetch_data_byte(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = (s32)((s8)fetch_data_byte(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = (s16)((s8)fetch_data_byte(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u8 *srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = (s32)((s8)*srcreg); } else { u16 *destreg; u8 *srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = (s16)((s8)*srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f,0xbf ****************************************************************************/ static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; u32 *destreg; u32 srcval; u16 *srcreg; START_OF_INSTR(); DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = (s32)((s16)fetch_data_word(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 1: destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = (s32)((s16)fetch_data_word(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 2: destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = (s32)((s16)fetch_data_word(srcoffset)); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 3: /* register to register */ destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = (s32)((s16)*srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /*************************************************************************** * Double byte operation code table: **************************************************************************/ void (*x86emu_optab2[256])(u8) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ /* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ /* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ /* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ /* 0x04 */ x86emuOp2_illegal_op, /* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ /* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ /* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ /* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ /* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ /* 0x0a */ x86emuOp2_illegal_op, /* 0x0b */ x86emuOp2_illegal_op, /* 0x0c */ x86emuOp2_illegal_op, /* 0x0d */ x86emuOp2_illegal_op, /* 0x0e */ x86emuOp2_illegal_op, /* 0x0f */ x86emuOp2_illegal_op, /* 0x10 */ x86emuOp2_illegal_op, /* 0x11 */ x86emuOp2_illegal_op, /* 0x12 */ x86emuOp2_illegal_op, /* 0x13 */ x86emuOp2_illegal_op, /* 0x14 */ x86emuOp2_illegal_op, /* 0x15 */ x86emuOp2_illegal_op, /* 0x16 */ x86emuOp2_illegal_op, /* 0x17 */ x86emuOp2_illegal_op, /* 0x18 */ x86emuOp2_illegal_op, /* 0x19 */ x86emuOp2_illegal_op, /* 0x1a */ x86emuOp2_illegal_op, /* 0x1b */ x86emuOp2_illegal_op, /* 0x1c */ x86emuOp2_illegal_op, /* 0x1d */ x86emuOp2_illegal_op, /* 0x1e */ x86emuOp2_illegal_op, /* 0x1f */ x86emuOp2_illegal_op, /* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ /* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ /* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ /* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ /* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ /* 0x25 */ x86emuOp2_illegal_op, /* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ /* 0x27 */ x86emuOp2_illegal_op, /* 0x28 */ x86emuOp2_illegal_op, /* 0x29 */ x86emuOp2_illegal_op, /* 0x2a */ x86emuOp2_illegal_op, /* 0x2b */ x86emuOp2_illegal_op, /* 0x2c */ x86emuOp2_illegal_op, /* 0x2d */ x86emuOp2_illegal_op, /* 0x2e */ x86emuOp2_illegal_op, /* 0x2f */ x86emuOp2_illegal_op, /* 0x30 */ x86emuOp2_illegal_op, /* 0x31 */ x86emuOp2_illegal_op, /* 0x32 */ x86emuOp2_illegal_op, /* 0x33 */ x86emuOp2_illegal_op, /* 0x34 */ x86emuOp2_illegal_op, /* 0x35 */ x86emuOp2_illegal_op, /* 0x36 */ x86emuOp2_illegal_op, /* 0x37 */ x86emuOp2_illegal_op, /* 0x38 */ x86emuOp2_illegal_op, /* 0x39 */ x86emuOp2_illegal_op, /* 0x3a */ x86emuOp2_illegal_op, /* 0x3b */ x86emuOp2_illegal_op, /* 0x3c */ x86emuOp2_illegal_op, /* 0x3d */ x86emuOp2_illegal_op, /* 0x3e */ x86emuOp2_illegal_op, /* 0x3f */ x86emuOp2_illegal_op, /* 0x40 */ x86emuOp2_illegal_op, /* 0x41 */ x86emuOp2_illegal_op, /* 0x42 */ x86emuOp2_illegal_op, /* 0x43 */ x86emuOp2_illegal_op, /* 0x44 */ x86emuOp2_illegal_op, /* 0x45 */ x86emuOp2_illegal_op, /* 0x46 */ x86emuOp2_illegal_op, /* 0x47 */ x86emuOp2_illegal_op, /* 0x48 */ x86emuOp2_illegal_op, /* 0x49 */ x86emuOp2_illegal_op, /* 0x4a */ x86emuOp2_illegal_op, /* 0x4b */ x86emuOp2_illegal_op, /* 0x4c */ x86emuOp2_illegal_op, /* 0x4d */ x86emuOp2_illegal_op, /* 0x4e */ x86emuOp2_illegal_op, /* 0x4f */ x86emuOp2_illegal_op, /* 0x50 */ x86emuOp2_illegal_op, /* 0x51 */ x86emuOp2_illegal_op, /* 0x52 */ x86emuOp2_illegal_op, /* 0x53 */ x86emuOp2_illegal_op, /* 0x54 */ x86emuOp2_illegal_op, /* 0x55 */ x86emuOp2_illegal_op, /* 0x56 */ x86emuOp2_illegal_op, /* 0x57 */ x86emuOp2_illegal_op, /* 0x58 */ x86emuOp2_illegal_op, /* 0x59 */ x86emuOp2_illegal_op, /* 0x5a */ x86emuOp2_illegal_op, /* 0x5b */ x86emuOp2_illegal_op, /* 0x5c */ x86emuOp2_illegal_op, /* 0x5d */ x86emuOp2_illegal_op, /* 0x5e */ x86emuOp2_illegal_op, /* 0x5f */ x86emuOp2_illegal_op, /* 0x60 */ x86emuOp2_illegal_op, /* 0x61 */ x86emuOp2_illegal_op, /* 0x62 */ x86emuOp2_illegal_op, /* 0x63 */ x86emuOp2_illegal_op, /* 0x64 */ x86emuOp2_illegal_op, /* 0x65 */ x86emuOp2_illegal_op, /* 0x66 */ x86emuOp2_illegal_op, /* 0x67 */ x86emuOp2_illegal_op, /* 0x68 */ x86emuOp2_illegal_op, /* 0x69 */ x86emuOp2_illegal_op, /* 0x6a */ x86emuOp2_illegal_op, /* 0x6b */ x86emuOp2_illegal_op, /* 0x6c */ x86emuOp2_illegal_op, /* 0x6d */ x86emuOp2_illegal_op, /* 0x6e */ x86emuOp2_illegal_op, /* 0x6f */ x86emuOp2_illegal_op, /* 0x70 */ x86emuOp2_illegal_op, /* 0x71 */ x86emuOp2_illegal_op, /* 0x72 */ x86emuOp2_illegal_op, /* 0x73 */ x86emuOp2_illegal_op, /* 0x74 */ x86emuOp2_illegal_op, /* 0x75 */ x86emuOp2_illegal_op, /* 0x76 */ x86emuOp2_illegal_op, /* 0x77 */ x86emuOp2_illegal_op, /* 0x78 */ x86emuOp2_illegal_op, /* 0x79 */ x86emuOp2_illegal_op, /* 0x7a */ x86emuOp2_illegal_op, /* 0x7b */ x86emuOp2_illegal_op, /* 0x7c */ x86emuOp2_illegal_op, /* 0x7d */ x86emuOp2_illegal_op, /* 0x7e */ x86emuOp2_illegal_op, /* 0x7f */ x86emuOp2_illegal_op, /* 0x80 */ x86emuOp2_long_jump, /* 0x81 */ x86emuOp2_long_jump, /* 0x82 */ x86emuOp2_long_jump, /* 0x83 */ x86emuOp2_long_jump, /* 0x84 */ x86emuOp2_long_jump, /* 0x85 */ x86emuOp2_long_jump, /* 0x86 */ x86emuOp2_long_jump, /* 0x87 */ x86emuOp2_long_jump, /* 0x88 */ x86emuOp2_long_jump, /* 0x89 */ x86emuOp2_long_jump, /* 0x8a */ x86emuOp2_long_jump, /* 0x8b */ x86emuOp2_long_jump, /* 0x8c */ x86emuOp2_long_jump, /* 0x8d */ x86emuOp2_long_jump, /* 0x8e */ x86emuOp2_long_jump, /* 0x8f */ x86emuOp2_long_jump, /* 0x90 */ x86emuOp2_set_byte, /* 0x91 */ x86emuOp2_set_byte, /* 0x92 */ x86emuOp2_set_byte, /* 0x93 */ x86emuOp2_set_byte, /* 0x94 */ x86emuOp2_set_byte, /* 0x95 */ x86emuOp2_set_byte, /* 0x96 */ x86emuOp2_set_byte, /* 0x97 */ x86emuOp2_set_byte, /* 0x98 */ x86emuOp2_set_byte, /* 0x99 */ x86emuOp2_set_byte, /* 0x9a */ x86emuOp2_set_byte, /* 0x9b */ x86emuOp2_set_byte, /* 0x9c */ x86emuOp2_set_byte, /* 0x9d */ x86emuOp2_set_byte, /* 0x9e */ x86emuOp2_set_byte, /* 0x9f */ x86emuOp2_set_byte, /* 0xa0 */ x86emuOp2_push_FS, /* 0xa1 */ x86emuOp2_pop_FS, /* 0xa2 */ x86emuOp2_illegal_op, /* 0xa3 */ x86emuOp2_bt_R, /* 0xa4 */ x86emuOp2_shld_IMM, /* 0xa5 */ x86emuOp2_shld_CL, /* 0xa6 */ x86emuOp2_illegal_op, /* 0xa7 */ x86emuOp2_illegal_op, /* 0xa8 */ x86emuOp2_push_GS, /* 0xa9 */ x86emuOp2_pop_GS, /* 0xaa */ x86emuOp2_illegal_op, /* 0xab */ x86emuOp2_bt_R, /* 0xac */ x86emuOp2_shrd_IMM, /* 0xad */ x86emuOp2_shrd_CL, /* 0xae */ x86emuOp2_illegal_op, /* 0xaf */ x86emuOp2_imul_R_RM, /* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ /* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ /* 0xb2 */ x86emuOp2_lss_R_IMM, /* 0xb3 */ x86emuOp2_btr_R, /* 0xb4 */ x86emuOp2_lfs_R_IMM, /* 0xb5 */ x86emuOp2_lgs_R_IMM, /* 0xb6 */ x86emuOp2_movzx_byte_R_RM, /* 0xb7 */ x86emuOp2_movzx_word_R_RM, /* 0xb8 */ x86emuOp2_illegal_op, /* 0xb9 */ x86emuOp2_illegal_op, /* 0xba */ x86emuOp2_btX_I, /* 0xbb */ x86emuOp2_btc_R, /* 0xbc */ x86emuOp2_bsf, /* 0xbd */ x86emuOp2_bsr, /* 0xbe */ x86emuOp2_movsx_byte_R_RM, /* 0xbf */ x86emuOp2_movsx_word_R_RM, /* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ /* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ /* 0xc2 */ x86emuOp2_illegal_op, /* 0xc3 */ x86emuOp2_illegal_op, /* 0xc4 */ x86emuOp2_illegal_op, /* 0xc5 */ x86emuOp2_illegal_op, /* 0xc6 */ x86emuOp2_illegal_op, /* 0xc7 */ x86emuOp2_illegal_op, /* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ /* 0xd0 */ x86emuOp2_illegal_op, /* 0xd1 */ x86emuOp2_illegal_op, /* 0xd2 */ x86emuOp2_illegal_op, /* 0xd3 */ x86emuOp2_illegal_op, /* 0xd4 */ x86emuOp2_illegal_op, /* 0xd5 */ x86emuOp2_illegal_op, /* 0xd6 */ x86emuOp2_illegal_op, /* 0xd7 */ x86emuOp2_illegal_op, /* 0xd8 */ x86emuOp2_illegal_op, /* 0xd9 */ x86emuOp2_illegal_op, /* 0xda */ x86emuOp2_illegal_op, /* 0xdb */ x86emuOp2_illegal_op, /* 0xdc */ x86emuOp2_illegal_op, /* 0xdd */ x86emuOp2_illegal_op, /* 0xde */ x86emuOp2_illegal_op, /* 0xdf */ x86emuOp2_illegal_op, /* 0xe0 */ x86emuOp2_illegal_op, /* 0xe1 */ x86emuOp2_illegal_op, /* 0xe2 */ x86emuOp2_illegal_op, /* 0xe3 */ x86emuOp2_illegal_op, /* 0xe4 */ x86emuOp2_illegal_op, /* 0xe5 */ x86emuOp2_illegal_op, /* 0xe6 */ x86emuOp2_illegal_op, /* 0xe7 */ x86emuOp2_illegal_op, /* 0xe8 */ x86emuOp2_illegal_op, /* 0xe9 */ x86emuOp2_illegal_op, /* 0xea */ x86emuOp2_illegal_op, /* 0xeb */ x86emuOp2_illegal_op, /* 0xec */ x86emuOp2_illegal_op, /* 0xed */ x86emuOp2_illegal_op, /* 0xee */ x86emuOp2_illegal_op, /* 0xef */ x86emuOp2_illegal_op, /* 0xf0 */ x86emuOp2_illegal_op, /* 0xf1 */ x86emuOp2_illegal_op, /* 0xf2 */ x86emuOp2_illegal_op, /* 0xf3 */ x86emuOp2_illegal_op, /* 0xf4 */ x86emuOp2_illegal_op, /* 0xf5 */ x86emuOp2_illegal_op, /* 0xf6 */ x86emuOp2_illegal_op, /* 0xf7 */ x86emuOp2_illegal_op, /* 0xf8 */ x86emuOp2_illegal_op, /* 0xf9 */ x86emuOp2_illegal_op, /* 0xfa */ x86emuOp2_illegal_op, /* 0xfb */ x86emuOp2_illegal_op, /* 0xfc */ x86emuOp2_illegal_op, /* 0xfd */ x86emuOp2_illegal_op, /* 0xfe */ x86emuOp2_illegal_op, /* 0xff */ x86emuOp2_illegal_op, }; xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/ops.c0000644000000000000000000126140210410136571015723 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: This file includes subroutines to implement the decoding * and emulation of all the x86 processor instructions. * * There are approximately 250 subroutines in here, which correspond * to the 256 byte-"opcodes" found on the 8086. The table which * dispatches this is found in the files optab.[ch]. * * Each opcode proc has a comment preceeding it which gives it's table * address. Several opcodes are missing (undefined) in the table. * * Each proc includes information for decoding (DECODE_PRINTF and * DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc * functions (START_OF_INSTR, END_OF_INSTR). * * Many of the procedures are *VERY* similar in coding. This has * allowed for a very large amount of code to be generated in a fairly * short amount of time (i.e. cut, paste, and modify). The result is * that much of the code below could have been folded into subroutines * for a large reduction in size of this file. The downside would be * that there would be a penalty in execution speed. The file could * also have been *MUCH* larger by inlining certain functions which * were called. This could have resulted even faster execution. The * prime directive I used to decide whether to inline the code or to * modularize it, was basically: 1) no unnecessary subroutine calls, * 2) no routines more than about 200 lines in size, and 3) modularize * any code that I might not get right the first time. The fetch_* * subroutines fall into the latter category. The The decode_* fall * into the second category. The coding of the "switch(mod){ .... }" * in many of the subroutines below falls into the first category. * Especially, the coding of {add,and,or,sub,...}_{byte,word} * subroutines are an especially glaring case of the third guideline. * Since so much of the code is cloned from other modules (compare * opcode #00 to opcode #01), making the basic operations subroutine * calls is especially important; otherwise mistakes in coding an * "add" would represent a nightmare in maintenance. * ****************************************************************************/ #include "x86emu/x86emui.h" /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** PARAMETERS: op1 - Instruction op code REMARKS: Handles illegal opcodes. ****************************************************************************/ static void x86emuOp_illegal_op( u8 op1) { START_OF_INSTR(); DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", M.x86.R_CS, M.x86.R_IP-1,op1); HALT_SYS(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x00 ****************************************************************************/ static void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; u8 *destreg, *srcreg; u8 destval; START_OF_INSTR(); DECODE_PRINTF("ADD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x01 ****************************************************************************/ static void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("ADD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = add_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x02 ****************************************************************************/ static void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("ADD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x03 ****************************************************************************/ static void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("ADD\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_word(*destreg, srcval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = add_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x04 ****************************************************************************/ static void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("ADD\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); M.x86.R_AL = add_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x05 ****************************************************************************/ static void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("ADD\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("ADD\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = add_long(M.x86.R_EAX, srcval); } else { M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x06 ****************************************************************************/ static void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tES\n"); TRACE_AND_STEP(); push_word(M.x86.R_ES); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x07 ****************************************************************************/ static void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("POP\tES\n"); TRACE_AND_STEP(); M.x86.R_ES = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x08 ****************************************************************************/ static void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; START_OF_INSTR(); DECODE_PRINTF("OR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x09 ****************************************************************************/ static void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("OR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = or_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0a ****************************************************************************/ static void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("OR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0b ****************************************************************************/ static void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("OR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_word(*destreg, srcval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = or_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0c ****************************************************************************/ static void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("OR\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); M.x86.R_AL = or_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0d ****************************************************************************/ static void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("OR\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("OR\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = or_long(M.x86.R_EAX, srcval); } else { M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0e ****************************************************************************/ static void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tCS\n"); TRACE_AND_STEP(); push_word(M.x86.R_CS); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x0f. Escape for two-byte opcode (286 or better) ****************************************************************************/ static void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) { u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); (*x86emu_optab2[op2])(op2); } /**************************************************************************** REMARKS: Handles opcode 0x10 ****************************************************************************/ static void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; START_OF_INSTR(); DECODE_PRINTF("ADC\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x11 ****************************************************************************/ static void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("ADC\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = adc_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x12 ****************************************************************************/ static void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("ADC\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x13 ****************************************************************************/ static void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("ADC\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_word(*destreg, srcval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = adc_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x14 ****************************************************************************/ static void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("ADC\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); M.x86.R_AL = adc_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x15 ****************************************************************************/ static void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("ADC\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("ADC\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval); } else { M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x16 ****************************************************************************/ static void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tSS\n"); TRACE_AND_STEP(); push_word(M.x86.R_SS); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x17 ****************************************************************************/ static void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("POP\tSS\n"); TRACE_AND_STEP(); M.x86.R_SS = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x18 ****************************************************************************/ static void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; START_OF_INSTR(); DECODE_PRINTF("SBB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x19 ****************************************************************************/ static void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("SBB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sbb_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x1a ****************************************************************************/ static void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("SBB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x1b ****************************************************************************/ static void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("SBB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_word(*destreg, srcval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sbb_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x1c ****************************************************************************/ static void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("SBB\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x1d ****************************************************************************/ static void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("SBB\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("SBB\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval); } else { M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x1e ****************************************************************************/ static void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tDS\n"); TRACE_AND_STEP(); push_word(M.x86.R_DS); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x1f ****************************************************************************/ static void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("POP\tDS\n"); TRACE_AND_STEP(); M.x86.R_DS = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x20 ****************************************************************************/ static void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; START_OF_INSTR(); DECODE_PRINTF("AND\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x21 ****************************************************************************/ static void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("AND\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = and_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x22 ****************************************************************************/ static void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("AND\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x23 ****************************************************************************/ static void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("AND\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_long(*destreg, srcval); break; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_word(*destreg, srcval); break; } case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = and_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x24 ****************************************************************************/ static void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("AND\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); M.x86.R_AL = and_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x25 ****************************************************************************/ static void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("AND\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("AND\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = and_long(M.x86.R_EAX, srcval); } else { M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x26 ****************************************************************************/ static void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("ES:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_SEGOVR_ES; /* * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 * opcode subroutines we do not want to do this. */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x27 ****************************************************************************/ static void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DAA\n"); TRACE_AND_STEP(); M.x86.R_AL = daa_byte(M.x86.R_AL); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x28 ****************************************************************************/ static void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; START_OF_INSTR(); DECODE_PRINTF("SUB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x29 ****************************************************************************/ static void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("SUB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = sub_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x2a ****************************************************************************/ static void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("SUB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x2b ****************************************************************************/ static void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("SUB\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_word(*destreg, srcval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = sub_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x2c ****************************************************************************/ static void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("SUB\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); M.x86.R_AL = sub_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x2d ****************************************************************************/ static void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("SUB\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("SUB\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval); } else { M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x2e ****************************************************************************/ static void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("CS:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_SEGOVR_CS; /* note no DECODE_CLEAR_SEGOVR here. */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x2f ****************************************************************************/ static void x86emuOp_das(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DAS\n"); TRACE_AND_STEP(); M.x86.R_AL = das_byte(M.x86.R_AL); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x30 ****************************************************************************/ static void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; START_OF_INSTR(); DECODE_PRINTF("XOR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_byte(destval, *srcreg); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x31 ****************************************************************************/ static void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("XOR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_long(destval, *srcreg); store_data_long(destoffset, destval); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = xor_word(destval, *srcreg); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x32 ****************************************************************************/ static void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("XOR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x33 ****************************************************************************/ static void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("XOR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_word(*destreg, srcval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = xor_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x34 ****************************************************************************/ static void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("XOR\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); M.x86.R_AL = xor_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x35 ****************************************************************************/ static void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XOR\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("XOR\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval); } else { M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x36 ****************************************************************************/ static void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("SS:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_SEGOVR_SS; /* no DECODE_CLEAR_SEGOVR ! */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x37 ****************************************************************************/ static void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("AAA\n"); TRACE_AND_STEP(); M.x86.R_AX = aaa_word(M.x86.R_AX); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x38 ****************************************************************************/ static void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; u8 *destreg, *srcreg; u8 destval; START_OF_INSTR(); DECODE_PRINTF("CMP\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(destval, *srcreg); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(destval, *srcreg); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(destval, *srcreg); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x39 ****************************************************************************/ static void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("CMP\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(destval, *srcreg); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(destval, *srcreg); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(destval, *srcreg); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(destval, *srcreg); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(destval, *srcreg); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(destval, *srcreg); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x3a ****************************************************************************/ static void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("CMP\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(*destreg, srcval); break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(*destreg, srcval); break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(*destreg, srcval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x3b ****************************************************************************/ static void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("CMP\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(*destreg, srcval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(*destreg, srcval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(*destreg, srcval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); cmp_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x3c ****************************************************************************/ static void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 srcval; START_OF_INSTR(); DECODE_PRINTF("CMP\tAL,"); srcval = fetch_byte_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); cmp_byte(M.x86.R_AL, srcval); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x3d ****************************************************************************/ static void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("CMP\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("CMP\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { cmp_long(M.x86.R_EAX, srcval); } else { cmp_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x3e ****************************************************************************/ static void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DS:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_SEGOVR_DS; /* NO DECODE_CLEAR_SEGOVR! */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x3f ****************************************************************************/ static void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("AAS\n"); TRACE_AND_STEP(); M.x86.R_AX = aas_word(M.x86.R_AX); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x40 ****************************************************************************/ static void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tEAX\n"); } else { DECODE_PRINTF("INC\tAX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = inc_long(M.x86.R_EAX); } else { M.x86.R_AX = inc_word(M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x41 ****************************************************************************/ static void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tECX\n"); } else { DECODE_PRINTF("INC\tCX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ECX = inc_long(M.x86.R_ECX); } else { M.x86.R_CX = inc_word(M.x86.R_CX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x42 ****************************************************************************/ static void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tEDX\n"); } else { DECODE_PRINTF("INC\tDX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDX = inc_long(M.x86.R_EDX); } else { M.x86.R_DX = inc_word(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x43 ****************************************************************************/ static void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tEBX\n"); } else { DECODE_PRINTF("INC\tBX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBX = inc_long(M.x86.R_EBX); } else { M.x86.R_BX = inc_word(M.x86.R_BX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x44 ****************************************************************************/ static void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tESP\n"); } else { DECODE_PRINTF("INC\tSP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESP = inc_long(M.x86.R_ESP); } else { M.x86.R_SP = inc_word(M.x86.R_SP); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x45 ****************************************************************************/ static void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tEBP\n"); } else { DECODE_PRINTF("INC\tBP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBP = inc_long(M.x86.R_EBP); } else { M.x86.R_BP = inc_word(M.x86.R_BP); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x46 ****************************************************************************/ static void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tESI\n"); } else { DECODE_PRINTF("INC\tSI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESI = inc_long(M.x86.R_ESI); } else { M.x86.R_SI = inc_word(M.x86.R_SI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x47 ****************************************************************************/ static void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tEDI\n"); } else { DECODE_PRINTF("INC\tDI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDI = inc_long(M.x86.R_EDI); } else { M.x86.R_DI = inc_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x48 ****************************************************************************/ static void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tEAX\n"); } else { DECODE_PRINTF("DEC\tAX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = dec_long(M.x86.R_EAX); } else { M.x86.R_AX = dec_word(M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x49 ****************************************************************************/ static void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tECX\n"); } else { DECODE_PRINTF("DEC\tCX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ECX = dec_long(M.x86.R_ECX); } else { M.x86.R_CX = dec_word(M.x86.R_CX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x4a ****************************************************************************/ static void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tEDX\n"); } else { DECODE_PRINTF("DEC\tDX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDX = dec_long(M.x86.R_EDX); } else { M.x86.R_DX = dec_word(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x4b ****************************************************************************/ static void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tEBX\n"); } else { DECODE_PRINTF("DEC\tBX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBX = dec_long(M.x86.R_EBX); } else { M.x86.R_BX = dec_word(M.x86.R_BX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x4c ****************************************************************************/ static void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tESP\n"); } else { DECODE_PRINTF("DEC\tSP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESP = dec_long(M.x86.R_ESP); } else { M.x86.R_SP = dec_word(M.x86.R_SP); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x4d ****************************************************************************/ static void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tEBP\n"); } else { DECODE_PRINTF("DEC\tBP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBP = dec_long(M.x86.R_EBP); } else { M.x86.R_BP = dec_word(M.x86.R_BP); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x4e ****************************************************************************/ static void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tESI\n"); } else { DECODE_PRINTF("DEC\tSI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESI = dec_long(M.x86.R_ESI); } else { M.x86.R_SI = dec_word(M.x86.R_SI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x4f ****************************************************************************/ static void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tEDI\n"); } else { DECODE_PRINTF("DEC\tDI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDI = dec_long(M.x86.R_EDI); } else { M.x86.R_DI = dec_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x50 ****************************************************************************/ static void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tEAX\n"); } else { DECODE_PRINTF("PUSH\tAX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_EAX); } else { push_word(M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x51 ****************************************************************************/ static void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tECX\n"); } else { DECODE_PRINTF("PUSH\tCX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_ECX); } else { push_word(M.x86.R_CX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x52 ****************************************************************************/ static void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tEDX\n"); } else { DECODE_PRINTF("PUSH\tDX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_EDX); } else { push_word(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x53 ****************************************************************************/ static void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tEBX\n"); } else { DECODE_PRINTF("PUSH\tBX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_EBX); } else { push_word(M.x86.R_BX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x54 ****************************************************************************/ static void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tESP\n"); } else { DECODE_PRINTF("PUSH\tSP\n"); } TRACE_AND_STEP(); /* Always push (E)SP, since we are emulating an i386 and above * processor. This is necessary as some BIOS'es use this to check * what type of processor is in the system. */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_ESP); } else { push_word((u16)(M.x86.R_SP)); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x55 ****************************************************************************/ static void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tEBP\n"); } else { DECODE_PRINTF("PUSH\tBP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_EBP); } else { push_word(M.x86.R_BP); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x56 ****************************************************************************/ static void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tESI\n"); } else { DECODE_PRINTF("PUSH\tSI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_ESI); } else { push_word(M.x86.R_SI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x57 ****************************************************************************/ static void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSH\tEDI\n"); } else { DECODE_PRINTF("PUSH\tDI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(M.x86.R_EDI); } else { push_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x58 ****************************************************************************/ static void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tEAX\n"); } else { DECODE_PRINTF("POP\tAX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = pop_long(); } else { M.x86.R_AX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x59 ****************************************************************************/ static void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tECX\n"); } else { DECODE_PRINTF("POP\tCX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ECX = pop_long(); } else { M.x86.R_CX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x5a ****************************************************************************/ static void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tEDX\n"); } else { DECODE_PRINTF("POP\tDX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDX = pop_long(); } else { M.x86.R_DX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x5b ****************************************************************************/ static void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tEBX\n"); } else { DECODE_PRINTF("POP\tBX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBX = pop_long(); } else { M.x86.R_BX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x5c ****************************************************************************/ static void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tESP\n"); } else { DECODE_PRINTF("POP\tSP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESP = pop_long(); } else { M.x86.R_SP = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x5d ****************************************************************************/ static void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tEBP\n"); } else { DECODE_PRINTF("POP\tBP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBP = pop_long(); } else { M.x86.R_BP = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x5e ****************************************************************************/ static void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tESI\n"); } else { DECODE_PRINTF("POP\tSI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESI = pop_long(); } else { M.x86.R_SI = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x5f ****************************************************************************/ static void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POP\tEDI\n"); } else { DECODE_PRINTF("POP\tDI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDI = pop_long(); } else { M.x86.R_DI = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x60 ****************************************************************************/ static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSHAD\n"); } else { DECODE_PRINTF("PUSHA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 old_sp = M.x86.R_ESP; push_long(M.x86.R_EAX); push_long(M.x86.R_ECX); push_long(M.x86.R_EDX); push_long(M.x86.R_EBX); push_long(old_sp); push_long(M.x86.R_EBP); push_long(M.x86.R_ESI); push_long(M.x86.R_EDI); } else { u16 old_sp = M.x86.R_SP; push_word(M.x86.R_AX); push_word(M.x86.R_CX); push_word(M.x86.R_DX); push_word(M.x86.R_BX); push_word(old_sp); push_word(M.x86.R_BP); push_word(M.x86.R_SI); push_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x61 ****************************************************************************/ static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POPAD\n"); } else { DECODE_PRINTF("POPA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDI = pop_long(); M.x86.R_ESI = pop_long(); M.x86.R_EBP = pop_long(); M.x86.R_ESP += 4; /* skip ESP */ M.x86.R_EBX = pop_long(); M.x86.R_EDX = pop_long(); M.x86.R_ECX = pop_long(); M.x86.R_EAX = pop_long(); } else { M.x86.R_DI = pop_word(); M.x86.R_SI = pop_word(); M.x86.R_BP = pop_word(); M.x86.R_SP += 2; /* skip SP */ M.x86.R_BX = pop_word(); M.x86.R_DX = pop_word(); M.x86.R_CX = pop_word(); M.x86.R_AX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ /*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ /**************************************************************************** REMARKS: Handles opcode 0x64 ****************************************************************************/ static void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("FS:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_SEGOVR_FS; /* * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 * opcode subroutines we do not want to do this. */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x65 ****************************************************************************/ static void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("GS:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_SEGOVR_GS; /* * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 * opcode subroutines we do not want to do this. */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x66 - prefix for 32-bit register ****************************************************************************/ static void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DATA:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_DATA; /* note no DECODE_CLEAR_SEGOVR here. */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x67 - prefix for 32-bit address ****************************************************************************/ static void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("ADDR:\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_ADDR; /* note no DECODE_CLEAR_SEGOVR here. */ END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x68 ****************************************************************************/ static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) { u32 imm; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { imm = fetch_long_imm(); } else { imm = fetch_word_imm(); } DECODE_PRINTF2("PUSH\t%x\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(imm); } else { push_word((u16)imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x69 ****************************************************************************/ static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; s32 imm; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); imm = fetch_long_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; s16 imm; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); imm = fetch_word_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); res = (s16)srcval * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; s32 imm; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); imm = fetch_long_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; s16 imm; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); imm = fetch_word_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); res = (s16)srcval * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; s32 imm; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); imm = fetch_long_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; s16 imm; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); imm = fetch_word_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); res = (s16)srcval * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; u32 res_lo,res_hi; s32 imm; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); imm = fetch_long_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg,*srcreg; u32 res; s16 imm; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); imm = fetch_word_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); res = (s16)*srcreg * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x6a ****************************************************************************/ static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) { s16 imm; START_OF_INSTR(); imm = (s8)fetch_byte_imm(); DECODE_PRINTF2("PUSH\t%d\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long((s32)imm); } else { push_word(imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x6b ****************************************************************************/ static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; s8 imm; START_OF_INSTR(); DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); res = (s16)srcval * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); res = (s16)srcval * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg; u16 srcval; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); res = (s16)srcval * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; u32 res_lo,res_hi; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); TRACE_AND_STEP(); imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); if (res_hi != 0) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u32)res_lo; } else { u16 *destreg,*srcreg; u32 res; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); imm = fetch_byte_imm(); DECODE_PRINTF2(",%d\n", (s32)imm); res = (s16)*srcreg * (s16)imm; if (res > 0xFFFF) { SET_FLAG(F_CF); SET_FLAG(F_OF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } *destreg = (u16)res; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x6c ****************************************************************************/ static void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("INSB\n"); ins(1); TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x6d ****************************************************************************/ static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INSD\n"); ins(4); } else { DECODE_PRINTF("INSW\n"); ins(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x6e ****************************************************************************/ static void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("OUTSB\n"); outs(1); TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x6f ****************************************************************************/ static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("OUTSD\n"); outs(4); } else { DECODE_PRINTF("OUTSW\n"); outs(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x70 ****************************************************************************/ static void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if overflow flag is set */ START_OF_INSTR(); DECODE_PRINTF("JO\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (ACCESS_FLAG(F_OF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x71 ****************************************************************************/ static void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if overflow is not set */ START_OF_INSTR(); DECODE_PRINTF("JNO\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (!ACCESS_FLAG(F_OF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x72 ****************************************************************************/ static void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if carry flag is set. */ START_OF_INSTR(); DECODE_PRINTF("JB\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (ACCESS_FLAG(F_CF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x73 ****************************************************************************/ static void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if carry flag is clear. */ START_OF_INSTR(); DECODE_PRINTF("JNB\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (!ACCESS_FLAG(F_CF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x74 ****************************************************************************/ static void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if zero flag is set. */ START_OF_INSTR(); DECODE_PRINTF("JZ\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (ACCESS_FLAG(F_ZF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x75 ****************************************************************************/ static void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if zero flag is clear. */ START_OF_INSTR(); DECODE_PRINTF("JNZ\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (!ACCESS_FLAG(F_ZF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x76 ****************************************************************************/ static void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if carry flag is set or if the zero flag is set. */ START_OF_INSTR(); DECODE_PRINTF("JBE\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x77 ****************************************************************************/ static void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if carry flag is clear and if the zero flag is clear */ START_OF_INSTR(); DECODE_PRINTF("JNBE\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x78 ****************************************************************************/ static void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if sign flag is set */ START_OF_INSTR(); DECODE_PRINTF("JS\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (ACCESS_FLAG(F_SF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x79 ****************************************************************************/ static void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if sign flag is clear */ START_OF_INSTR(); DECODE_PRINTF("JNS\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (!ACCESS_FLAG(F_SF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x7a ****************************************************************************/ static void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if parity flag is set (even parity) */ START_OF_INSTR(); DECODE_PRINTF("JP\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (ACCESS_FLAG(F_PF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x7b ****************************************************************************/ static void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; /* jump to byte offset if parity flag is clear (odd parity) */ START_OF_INSTR(); DECODE_PRINTF("JNP\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (!ACCESS_FLAG(F_PF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x7c ****************************************************************************/ static void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; int sf, of; /* jump to byte offset if sign flag not equal to overflow flag. */ START_OF_INSTR(); DECODE_PRINTF("JL\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); sf = ACCESS_FLAG(F_SF) != 0; of = ACCESS_FLAG(F_OF) != 0; if (sf ^ of) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x7d ****************************************************************************/ static void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; int sf, of; /* jump to byte offset if sign flag not equal to overflow flag. */ START_OF_INSTR(); DECODE_PRINTF("JNL\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); sf = ACCESS_FLAG(F_SF) != 0; of = ACCESS_FLAG(F_OF) != 0; /* note: inverse of above, but using == instead of xor. */ if (sf == of) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x7e ****************************************************************************/ static void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; int sf, of; /* jump to byte offset if sign flag not equal to overflow flag or the zero flag is set */ START_OF_INSTR(); DECODE_PRINTF("JLE\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); sf = ACCESS_FLAG(F_SF) != 0; of = ACCESS_FLAG(F_OF) != 0; if ((sf ^ of) || ACCESS_FLAG(F_ZF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x7f ****************************************************************************/ static void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1)) { s8 offset; u16 target; int sf, of; /* jump to byte offset if sign flag equal to overflow flag. and the zero flag is clear */ START_OF_INSTR(); DECODE_PRINTF("JNLE\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + (s16)offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); sf = ACCESS_FLAG(F_SF) != 0; of = ACCESS_FLAG(F_OF) != 0; if ((sf == of) && !ACCESS_FLAG(F_ZF)) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } static u8 (*opc80_byte_operation[])(u8 d, u8 s) = { add_byte, /* 00 */ or_byte, /* 01 */ adc_byte, /* 02 */ sbb_byte, /* 03 */ and_byte, /* 04 */ sub_byte, /* 05 */ xor_byte, /* 06 */ cmp_byte, /* 07 */ }; /**************************************************************************** REMARKS: Handles opcode 0x80 ****************************************************************************/ static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; uint destoffset; u8 imm; u8 destval; /* * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ADD\t"); break; case 1: DECODE_PRINTF("OR\t"); break; case 2: DECODE_PRINTF("ADC\t"); break; case 3: DECODE_PRINTF("SBB\t"); break; case 4: DECODE_PRINTF("AND\t"); break; case 5: DECODE_PRINTF("SUB\t"); break; case 6: DECODE_PRINTF("XOR\t"); break; case 7: DECODE_PRINTF("CMP\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ switch (mod) { case 0: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc80_byte_operation[rh]) (destval, imm); if (rh != 7) store_data_byte(destoffset, destval); break; case 1: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc80_byte_operation[rh]) (destval, imm); if (rh != 7) store_data_byte(destoffset, destval); break; case 2: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc80_byte_operation[rh]) (destval, imm); if (rh != 7) store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc80_byte_operation[rh]) (*destreg, imm); if (rh != 7) *destreg = destval; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } static u16 (*opc81_word_operation[])(u16 d, u16 s) = { add_word, /*00 */ or_word, /*01 */ adc_word, /*02 */ sbb_word, /*03 */ and_word, /*04 */ sub_word, /*05 */ xor_word, /*06 */ cmp_word, /*07 */ }; static u32 (*opc81_long_operation[])(u32 d, u32 s) = { add_long, /*00 */ or_long, /*01 */ adc_long, /*02 */ sbb_long, /*03 */ and_long, /*04 */ sub_long, /*05 */ xor_long, /*06 */ cmp_long, /*07 */ }; /**************************************************************************** REMARKS: Handles opcode 0x81 ****************************************************************************/ static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; /* * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ADD\t"); break; case 1: DECODE_PRINTF("OR\t"); break; case 2: DECODE_PRINTF("ADC\t"); break; case 3: DECODE_PRINTF("SBB\t"); break; case 4: DECODE_PRINTF("AND\t"); break; case 5: DECODE_PRINTF("SUB\t"); break; case 6: DECODE_PRINTF("XOR\t"); break; case 7: DECODE_PRINTF("CMP\t"); break; } } #endif /* * Know operation, decode the mod byte to find the addressing * mode. */ switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); imm = fetch_long_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_long_operation[rh]) (destval, imm); if (rh != 7) store_data_long(destoffset, destval); } else { u16 destval,imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); imm = fetch_word_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_word_operation[rh]) (destval, imm); if (rh != 7) store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); imm = fetch_long_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_long_operation[rh]) (destval, imm); if (rh != 7) store_data_long(destoffset, destval); } else { u16 destval,imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); imm = fetch_word_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_word_operation[rh]) (destval, imm); if (rh != 7) store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); imm = fetch_long_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_long_operation[rh]) (destval, imm); if (rh != 7) store_data_long(destoffset, destval); } else { u16 destval,imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); imm = fetch_word_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_word_operation[rh]) (destval, imm); if (rh != 7) store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 destval,imm; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); imm = fetch_long_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_long_operation[rh]) (*destreg, imm); if (rh != 7) *destreg = destval; } else { u16 *destreg; u16 destval,imm; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); imm = fetch_word_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); destval = (*opc81_word_operation[rh]) (*destreg, imm); if (rh != 7) *destreg = destval; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } static u8 (*opc82_byte_operation[])(u8 s, u8 d) = { add_byte, /*00 */ or_byte, /*01 *//*YYY UNUSED ???? */ adc_byte, /*02 */ sbb_byte, /*03 */ and_byte, /*04 *//*YYY UNUSED ???? */ sub_byte, /*05 */ xor_byte, /*06 *//*YYY UNUSED ???? */ cmp_byte, /*07 */ }; /**************************************************************************** REMARKS: Handles opcode 0x82 ****************************************************************************/ static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; uint destoffset; u8 imm; u8 destval; /* * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction Similar to opcode 81, except that * the immediate byte is sign extended to a word length. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ADD\t"); break; case 1: DECODE_PRINTF("OR\t"); break; case 2: DECODE_PRINTF("ADC\t"); break; case 3: DECODE_PRINTF("SBB\t"); break; case 4: DECODE_PRINTF("AND\t"); break; case 5: DECODE_PRINTF("SUB\t"); break; case 6: DECODE_PRINTF("XOR\t"); break; case 7: DECODE_PRINTF("CMP\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ switch (mod) { case 0: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm00_address(rl); destval = fetch_data_byte(destoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc82_byte_operation[rh]) (destval, imm); if (rh != 7) store_data_byte(destoffset, destval); break; case 1: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm01_address(rl); destval = fetch_data_byte(destoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc82_byte_operation[rh]) (destval, imm); if (rh != 7) store_data_byte(destoffset, destval); break; case 2: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); destval = fetch_data_byte(destoffset); imm = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc82_byte_operation[rh]) (destval, imm); if (rh != 7) store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); imm = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc82_byte_operation[rh]) (*destreg, imm); if (rh != 7) *destreg = destval; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } static u16 (*opc83_word_operation[])(u16 s, u16 d) = { add_word, /*00 */ or_word, /*01 *//*YYY UNUSED ???? */ adc_word, /*02 */ sbb_word, /*03 */ and_word, /*04 *//*YYY UNUSED ???? */ sub_word, /*05 */ xor_word, /*06 *//*YYY UNUSED ???? */ cmp_word, /*07 */ }; static u32 (*opc83_long_operation[])(u32 s, u32 d) = { add_long, /*00 */ or_long, /*01 *//*YYY UNUSED ???? */ adc_long, /*02 */ sbb_long, /*03 */ and_long, /*04 *//*YYY UNUSED ???? */ sub_long, /*05 */ xor_long, /*06 *//*YYY UNUSED ???? */ cmp_long, /*07 */ }; /**************************************************************************** REMARKS: Handles opcode 0x83 ****************************************************************************/ static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; /* * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction Similar to opcode 81, except that * the immediate byte is sign extended to a word length. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ADD\t"); break; case 1: DECODE_PRINTF("OR\t"); break; case 2: DECODE_PRINTF("ADC\t"); break; case 3: DECODE_PRINTF("SBB\t"); break; case 4: DECODE_PRINTF("AND\t"); break; case 5: DECODE_PRINTF("SUB\t"); break; case 6: DECODE_PRINTF("XOR\t"); break; case 7: DECODE_PRINTF("CMP\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm00_address(rl); destval = fetch_data_long(destoffset); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_long_operation[rh]) (destval, imm); if (rh != 7) store_data_long(destoffset, destval); } else { u16 destval,imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm00_address(rl); destval = fetch_data_word(destoffset); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_word_operation[rh]) (destval, imm); if (rh != 7) store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm01_address(rl); destval = fetch_data_long(destoffset); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_long_operation[rh]) (destval, imm); if (rh != 7) store_data_long(destoffset, destval); } else { u16 destval,imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm01_address(rl); destval = fetch_data_word(destoffset); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_word_operation[rh]) (destval, imm); if (rh != 7) store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm10_address(rl); destval = fetch_data_long(destoffset); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_long_operation[rh]) (destval, imm); if (rh != 7) store_data_long(destoffset, destval); } else { u16 destval,imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm10_address(rl); destval = fetch_data_word(destoffset); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_word_operation[rh]) (destval, imm); if (rh != 7) store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 destval,imm; destreg = DECODE_RM_LONG_REGISTER(rl); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_long_operation[rh]) (*destreg, imm); if (rh != 7) *destreg = destval; } else { u16 *destreg; u16 destval,imm; destreg = DECODE_RM_WORD_REGISTER(rl); imm = (s8) fetch_byte_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); destval = (*opc83_word_operation[rh]) (*destreg, imm); if (rh != 7) *destreg = destval; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x84 ****************************************************************************/ static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; START_OF_INSTR(); DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_byte(destval, *srcreg); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_byte(destval, *srcreg); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_byte(destval, *srcreg); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_byte(*destreg, *srcreg); break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x85 ****************************************************************************/ static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_long(destval, *srcreg); } else { u16 destval; u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_word(destval, *srcreg); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_long(destval, *srcreg); } else { u16 destval; u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_word(destval, *srcreg); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_long(destval, *srcreg); } else { u16 destval; u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_word(destval, *srcreg); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_long(*destreg, *srcreg); } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); test_word(*destreg, *srcreg); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x86 ****************************************************************************/ static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; u8 destval; u8 tmp; START_OF_INSTR(); DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_byte(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_byte(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_byte(destoffset); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = *destreg; *destreg = tmp; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x87 ****************************************************************************/ static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg; u32 destval,tmp; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_long(destoffset, destval); } else { u16 *srcreg; u16 destval,tmp; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg; u32 destval,tmp; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_long(destoffset, destval); } else { u16 *srcreg; u16 destval,tmp; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg; u32 destval,tmp; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_long(destoffset); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_long(destoffset, destval); } else { u16 *srcreg; u16 destval,tmp; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); destval = fetch_data_word(destoffset); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = destval; destval = tmp; store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; u32 tmp; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = *destreg; *destreg = tmp; } else { u16 *destreg,*srcreg; u16 tmp; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); tmp = *srcreg; *srcreg = *destreg; *destreg = tmp; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x88 ****************************************************************************/ static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_byte(destoffset, *srcreg); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_byte(destoffset, *srcreg); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_byte(destoffset, *srcreg); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x89 ****************************************************************************/ static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u32 destoffset; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_long(destoffset, *srcreg); } else { u16 *srcreg; destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_word(destoffset, *srcreg); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_long(destoffset, *srcreg); } else { u16 *srcreg; destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_word(destoffset, *srcreg); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_long(destoffset, *srcreg); } else { u16 *srcreg; destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_word(destoffset, *srcreg); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg,*srcreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; } else { u16 *destreg,*srcreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x8a ****************************************************************************/ static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; uint srcoffset; u8 srcval; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 1: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 2: destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_byte(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x8b ****************************************************************************/ static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_long(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } else { u16 *destreg; u16 srcval; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg, *srcreg; destreg = DECODE_RM_LONG_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; } else { u16 *destreg, *srcreg; destreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x8c ****************************************************************************/ static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u16 *destreg, *srcreg; uint destoffset; u16 destval; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); srcreg = decode_rm_seg_register(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = *srcreg; store_data_word(destoffset, destval); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); srcreg = decode_rm_seg_register(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = *srcreg; store_data_word(destoffset, destval); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); srcreg = decode_rm_seg_register(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = *srcreg; store_data_word(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcreg = decode_rm_seg_register(rh); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x8d ****************************************************************************/ static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u16 *srcreg; uint destoffset; /* * TODO: Need to handle address size prefix! * * lea eax,[eax+ebx*2] ?? */ START_OF_INSTR(); DECODE_PRINTF("LEA\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *srcreg = (u16)destoffset; break; case 1: srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *srcreg = (u16)destoffset; break; case 2: srcreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *srcreg = (u16)destoffset; break; case 3: /* register to register */ /* undefined. Do nothing. */ break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x8e ****************************************************************************/ static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u16 *destreg, *srcreg; uint srcoffset; u16 srcval; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: destreg = decode_rm_seg_register(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 1: destreg = decode_rm_seg_register(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 2: destreg = decode_rm_seg_register(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); srcval = fetch_data_word(srcoffset); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = srcval; break; case 3: /* register to register */ destreg = decode_rm_seg_register(rh); DECODE_PRINTF(","); srcreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = *srcreg; break; } /* * Clean up, and reset all the R_xSP pointers to the correct * locations. This is about 3x too much overhead (doing all the * segreg ptrs when only one is needed, but this instruction * *cannot* be that common, and this isn't too much work anyway. */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x8f ****************************************************************************/ static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("POP\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); HALT_SYS(); } switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = pop_long(); store_data_long(destoffset, destval); } else { u16 destval; destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = pop_word(); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = pop_long(); store_data_long(destoffset, destval); } else { u16 destval; destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = pop_word(); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = pop_long(); store_data_long(destoffset, destval); } else { u16 destval; destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); destval = pop_word(); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = pop_long(); } else { u16 *destreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = pop_word(); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x90 ****************************************************************************/ static void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("NOP\n"); TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x91 ****************************************************************************/ static void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1)) { u32 tmp; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XCHG\tEAX,ECX\n"); } else { DECODE_PRINTF("XCHG\tAX,CX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { tmp = M.x86.R_EAX; M.x86.R_EAX = M.x86.R_ECX; M.x86.R_ECX = tmp; } else { tmp = M.x86.R_AX; M.x86.R_AX = M.x86.R_CX; M.x86.R_CX = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x92 ****************************************************************************/ static void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1)) { u32 tmp; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XCHG\tEAX,EDX\n"); } else { DECODE_PRINTF("XCHG\tAX,DX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { tmp = M.x86.R_EAX; M.x86.R_EAX = M.x86.R_EDX; M.x86.R_EDX = tmp; } else { tmp = M.x86.R_AX; M.x86.R_AX = M.x86.R_DX; M.x86.R_DX = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x93 ****************************************************************************/ static void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1)) { u32 tmp; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XCHG\tEAX,EBX\n"); } else { DECODE_PRINTF("XCHG\tAX,BX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { tmp = M.x86.R_EAX; M.x86.R_EAX = M.x86.R_EBX; M.x86.R_EBX = tmp; } else { tmp = M.x86.R_AX; M.x86.R_AX = M.x86.R_BX; M.x86.R_BX = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x94 ****************************************************************************/ static void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1)) { u32 tmp; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XCHG\tEAX,ESP\n"); } else { DECODE_PRINTF("XCHG\tAX,SP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { tmp = M.x86.R_EAX; M.x86.R_EAX = M.x86.R_ESP; M.x86.R_ESP = tmp; } else { tmp = M.x86.R_AX; M.x86.R_AX = M.x86.R_SP; M.x86.R_SP = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x95 ****************************************************************************/ static void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1)) { u32 tmp; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XCHG\tEAX,EBP\n"); } else { DECODE_PRINTF("XCHG\tAX,BP\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { tmp = M.x86.R_EAX; M.x86.R_EAX = M.x86.R_EBP; M.x86.R_EBP = tmp; } else { tmp = M.x86.R_AX; M.x86.R_AX = M.x86.R_BP; M.x86.R_BP = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x96 ****************************************************************************/ static void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1)) { u32 tmp; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XCHG\tEAX,ESI\n"); } else { DECODE_PRINTF("XCHG\tAX,SI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { tmp = M.x86.R_EAX; M.x86.R_EAX = M.x86.R_ESI; M.x86.R_ESI = tmp; } else { tmp = M.x86.R_AX; M.x86.R_AX = M.x86.R_SI; M.x86.R_SI = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x97 ****************************************************************************/ static void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1)) { u32 tmp; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("XCHG\tEAX,EDI\n"); } else { DECODE_PRINTF("XCHG\tAX,DI\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { tmp = M.x86.R_EAX; M.x86.R_EAX = M.x86.R_EDI; M.x86.R_EDI = tmp; } else { tmp = M.x86.R_AX; M.x86.R_AX = M.x86.R_DI; M.x86.R_DI = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x98 ****************************************************************************/ static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("CWDE\n"); } else { DECODE_PRINTF("CBW\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { if (M.x86.R_AX & 0x8000) { M.x86.R_EAX |= 0xffff0000; } else { M.x86.R_EAX &= 0x0000ffff; } } else { if (M.x86.R_AL & 0x80) { M.x86.R_AH = 0xff; } else { M.x86.R_AH = 0x0; } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x99 ****************************************************************************/ static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("CDQ\n"); } else { DECODE_PRINTF("CWD\n"); } DECODE_PRINTF("CWD\n"); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { if (M.x86.R_EAX & 0x80000000) { M.x86.R_EDX = 0xffffffff; } else { M.x86.R_EDX = 0x0; } } else { if (M.x86.R_AX & 0x8000) { M.x86.R_DX = 0xffff; } else { M.x86.R_DX = 0x0; } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x9a ****************************************************************************/ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) { u16 farseg, faroff; START_OF_INSTR(); DECODE_PRINTF("CALL\t"); faroff = fetch_word_imm(); farseg = fetch_word_imm(); DECODE_PRINTF2("%04x:", farseg); DECODE_PRINTF2("%04x\n", faroff); CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); /* XXX * * Hooked interrupt vectors calling into our "BIOS" will cause * problems unless all intersegment stuff is checked for BIOS * access. Check needed here. For moment, let it alone. */ TRACE_AND_STEP(); push_word(M.x86.R_CS); M.x86.R_CS = farseg; push_word(M.x86.R_IP); M.x86.R_IP = faroff; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x9b ****************************************************************************/ static void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("WAIT"); TRACE_AND_STEP(); /* NADA. */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x9c ****************************************************************************/ static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) { u32 flags; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("PUSHFD\n"); } else { DECODE_PRINTF("PUSHF\n"); } TRACE_AND_STEP(); /* clear out *all* bits not representing flags, and turn on real bits */ flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; if (M.x86.mode & SYSMODE_PREFIX_DATA) { push_long(flags); } else { push_word((u16)flags); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x9d ****************************************************************************/ static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("POPFD\n"); } else { DECODE_PRINTF("POPF\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EFLG = pop_long(); } else { M.x86.R_FLG = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x9e ****************************************************************************/ static void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("SAHF\n"); TRACE_AND_STEP(); /* clear the lower bits of the flag register */ M.x86.R_FLG &= 0xffffff00; /* or in the AH register into the flags register */ M.x86.R_FLG |= M.x86.R_AH; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0x9f ****************************************************************************/ static void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("LAHF\n"); TRACE_AND_STEP(); M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); /*undocumented TC++ behavior??? Nope. It's documented, but you have too look real hard to notice it. */ M.x86.R_AH |= 0x2; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa0 ****************************************************************************/ static void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; START_OF_INSTR(); DECODE_PRINTF("MOV\tAL,"); offset = fetch_word_imm(); DECODE_PRINTF2("[%04x]\n", offset); TRACE_AND_STEP(); M.x86.R_AL = fetch_data_byte(offset); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa1 ****************************************************************************/ static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); } else { DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = fetch_data_long(offset); } else { M.x86.R_AX = fetch_data_word(offset); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa2 ****************************************************************************/ static void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); offset = fetch_word_imm(); DECODE_PRINTF2("[%04x],AL\n", offset); TRACE_AND_STEP(); store_data_byte(offset, M.x86.R_AL); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa3 ****************************************************************************/ static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); } else { DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { store_data_long(offset, M.x86.R_EAX); } else { store_data_word(offset, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa4 ****************************************************************************/ static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) { u8 val; u32 count; int inc; START_OF_INSTR(); DECODE_PRINTF("MOVS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -1; else inc = 1; TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* move them until CX is ZERO. */ count = M.x86.R_CX; M.x86.R_CX = 0; M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { val = fetch_data_byte(M.x86.R_SI); store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); M.x86.R_SI += inc; M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa5 ****************************************************************************/ static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) { u32 val; int inc; u32 count; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOVS\tDWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -4; else inc = 4; } else { DECODE_PRINTF("MOVS\tWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -2; else inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* move them until CX is ZERO. */ count = M.x86.R_CX; M.x86.R_CX = 0; M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { if (M.x86.mode & SYSMODE_PREFIX_DATA) { val = fetch_data_long(M.x86.R_SI); store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); } else { val = fetch_data_word(M.x86.R_SI); store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); } M.x86.R_SI += inc; M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa6 ****************************************************************************/ static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) { s8 val1, val2; int inc; START_OF_INSTR(); DECODE_PRINTF("CMPS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ inc = -1; else inc = 1; if (M.x86.mode & SYSMODE_PREFIX_REPE) { /* REPE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { val1 = fetch_data_byte(M.x86.R_SI); val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); cmp_byte(val1, val2); M.x86.R_CX -= 1; M.x86.R_SI += inc; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF) == 0) break; } M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { /* REPNE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { val1 = fetch_data_byte(M.x86.R_SI); val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); cmp_byte(val1, val2); M.x86.R_CX -= 1; M.x86.R_SI += inc; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF)) break; /* zero flag set means equal */ } M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { val1 = fetch_data_byte(M.x86.R_SI); val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); cmp_byte(val1, val2); M.x86.R_SI += inc; M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa7 ****************************************************************************/ static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) { u32 val1,val2; int inc; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("CMPS\tDWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -4; else inc = 4; } else { DECODE_PRINTF("CMPS\tWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -2; else inc = 2; } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_REPE) { /* REPE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { if (M.x86.mode & SYSMODE_PREFIX_DATA) { val1 = fetch_data_long(M.x86.R_SI); val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); cmp_long(val1, val2); } else { val1 = fetch_data_word(M.x86.R_SI); val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); cmp_word((u16)val1, (u16)val2); } M.x86.R_CX -= 1; M.x86.R_SI += inc; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF) == 0) break; } M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { /* REPNE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { if (M.x86.mode & SYSMODE_PREFIX_DATA) { val1 = fetch_data_long(M.x86.R_SI); val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); cmp_long(val1, val2); } else { val1 = fetch_data_word(M.x86.R_SI); val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); cmp_word((u16)val1, (u16)val2); } M.x86.R_CX -= 1; M.x86.R_SI += inc; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF)) break; /* zero flag set means equal */ } M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { if (M.x86.mode & SYSMODE_PREFIX_DATA) { val1 = fetch_data_long(M.x86.R_SI); val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); cmp_long(val1, val2); } else { val1 = fetch_data_word(M.x86.R_SI); val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); cmp_word((u16)val1, (u16)val2); } M.x86.R_SI += inc; M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa8 ****************************************************************************/ static void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) { int imm; START_OF_INSTR(); DECODE_PRINTF("TEST\tAL,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%04x\n", imm); TRACE_AND_STEP(); test_byte(M.x86.R_AL, (u8)imm); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xa9 ****************************************************************************/ static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("TEST\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("TEST\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { test_long(M.x86.R_EAX, srcval); } else { test_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xaa ****************************************************************************/ static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) { int inc; START_OF_INSTR(); DECODE_PRINTF("STOS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -1; else inc = 1; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); M.x86.R_CX -= 1; M.x86.R_DI += inc; } M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xab ****************************************************************************/ static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) { int inc; u32 count; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("STOS\tDWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -4; else inc = 4; } else { DECODE_PRINTF("STOS\tWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -2; else inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* move them until CX is ZERO. */ count = M.x86.R_CX; M.x86.R_CX = 0; M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { if (M.x86.mode & SYSMODE_PREFIX_DATA) { store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); } else { store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); } M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xac ****************************************************************************/ static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) { int inc; START_OF_INSTR(); DECODE_PRINTF("LODS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ inc = -1; else inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { M.x86.R_AL = fetch_data_byte(M.x86.R_SI); M.x86.R_CX -= 1; M.x86.R_SI += inc; } M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { M.x86.R_AL = fetch_data_byte(M.x86.R_SI); M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xad ****************************************************************************/ static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) { int inc; u32 count; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("LODS\tDWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -4; else inc = 4; } else { DECODE_PRINTF("LODS\tWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -2; else inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* move them until CX is ZERO. */ count = M.x86.R_CX; M.x86.R_CX = 0; M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = fetch_data_long(M.x86.R_SI); } else { M.x86.R_AX = fetch_data_word(M.x86.R_SI); } M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xae ****************************************************************************/ static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) { s8 val2; int inc; START_OF_INSTR(); DECODE_PRINTF("SCAS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ inc = -1; else inc = 1; if (M.x86.mode & SYSMODE_PREFIX_REPE) { /* REPE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); cmp_byte(M.x86.R_AL, val2); M.x86.R_CX -= 1; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF) == 0) break; } M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { /* REPNE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); cmp_byte(M.x86.R_AL, val2); M.x86.R_CX -= 1; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF)) break; /* zero flag set means equal */ } M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); cmp_byte(M.x86.R_AL, val2); M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xaf ****************************************************************************/ static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) { int inc; u32 val; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("SCAS\tDWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -4; else inc = 4; } else { DECODE_PRINTF("SCAS\tWORD\n"); if (ACCESS_FLAG(F_DF)) /* down */ inc = -2; else inc = 2; } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_REPE) { /* REPE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { if (M.x86.mode & SYSMODE_PREFIX_DATA) { val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); cmp_long(M.x86.R_EAX, val); } else { val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); cmp_word(M.x86.R_AX, (u16)val); } M.x86.R_CX -= 1; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF) == 0) break; } M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { /* REPNE */ /* move them until CX is ZERO. */ while (M.x86.R_CX != 0) { if (M.x86.mode & SYSMODE_PREFIX_DATA) { val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); cmp_long(M.x86.R_EAX, val); } else { val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); cmp_word(M.x86.R_AX, (u16)val); } M.x86.R_CX -= 1; M.x86.R_DI += inc; if (ACCESS_FLAG(F_ZF)) break; /* zero flag set means equal */ } M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { if (M.x86.mode & SYSMODE_PREFIX_DATA) { val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); cmp_long(M.x86.R_EAX, val); } else { val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); cmp_word(M.x86.R_AX, (u16)val); } M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb0 ****************************************************************************/ static void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tAL,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_AL = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb1 ****************************************************************************/ static void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tCL,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_CL = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb2 ****************************************************************************/ static void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tDL,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_DL = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb3 ****************************************************************************/ static void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tBL,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_BL = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb4 ****************************************************************************/ static void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tAH,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_AH = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb5 ****************************************************************************/ static void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tCH,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_CH = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb6 ****************************************************************************/ static void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tDH,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_DH = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb7 ****************************************************************************/ static void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1)) { u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\tBH,"); imm = fetch_byte_imm(); DECODE_PRINTF2("%x\n", imm); TRACE_AND_STEP(); M.x86.R_BH = imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb8 ****************************************************************************/ static void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tEAX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tAX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = srcval; } else { M.x86.R_AX = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xb9 ****************************************************************************/ static void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tECX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tCX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ECX = srcval; } else { M.x86.R_CX = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xba ****************************************************************************/ static void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tEDX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tDX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDX = srcval; } else { M.x86.R_DX = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xbb ****************************************************************************/ static void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tEBX,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tBX,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBX = srcval; } else { M.x86.R_BX = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xbc ****************************************************************************/ static void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tESP,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tSP,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESP = srcval; } else { M.x86.R_SP = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xbd ****************************************************************************/ static void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tEBP,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tBP,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EBP = srcval; } else { M.x86.R_BP = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xbe ****************************************************************************/ static void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tESI,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tSI,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ESI = srcval; } else { M.x86.R_SI = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xbf ****************************************************************************/ static void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("MOV\tEDI,"); srcval = fetch_long_imm(); } else { DECODE_PRINTF("MOV\tDI,"); srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EDI = srcval; } else { M.x86.R_DI = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /* used by opcodes c0, d0, and d2. */ static u8(*opcD0_byte_operation[])(u8 d, u8 s) = { rol_byte, ror_byte, rcl_byte, rcr_byte, shl_byte, shr_byte, shl_byte, /* sal_byte === shl_byte by definition */ sar_byte, }; /**************************************************************************** REMARKS: Handles opcode 0xc0 ****************************************************************************/ static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; uint destoffset; u8 destval; u8 amt; /* * Yet another weirdo special case instruction format. Part of * the opcode held below in "RH". Doubly nested case would * result, except that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ROL\t"); break; case 1: DECODE_PRINTF("ROR\t"); break; case 2: DECODE_PRINTF("RCL\t"); break; case 3: DECODE_PRINTF("RCR\t"); break; case 4: DECODE_PRINTF("SHL\t"); break; case 5: DECODE_PRINTF("SHR\t"); break; case 6: DECODE_PRINTF("SAL\t"); break; case 7: DECODE_PRINTF("SAR\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ switch (mod) { case 0: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm00_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, amt); store_data_byte(destoffset, destval); break; case 1: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm01_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, amt); store_data_byte(destoffset, destval); break; case 2: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, amt); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (*destreg, amt); *destreg = destval; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /* used by opcodes c1, d1, and d3. */ static u16(*opcD1_word_operation[])(u16 s, u8 d) = { rol_word, ror_word, rcl_word, rcr_word, shl_word, shr_word, shl_word, /* sal_byte === shl_byte by definition */ sar_word, }; /* used by opcodes c1, d1, and d3. */ static u32 (*opcD1_long_operation[])(u32 s, u8 d) = { rol_long, ror_long, rcl_long, rcr_long, shl_long, shr_long, shl_long, /* sal_byte === shl_byte by definition */ sar_long, }; /**************************************************************************** REMARKS: Handles opcode 0xc1 ****************************************************************************/ static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; u8 amt; /* * Yet another weirdo special case instruction format. Part of * the opcode held below in "RH". Doubly nested case would * result, except that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ROL\t"); break; case 1: DECODE_PRINTF("ROR\t"); break; case 2: DECODE_PRINTF("RCL\t"); break; case 3: DECODE_PRINTF("RCR\t"); break; case 4: DECODE_PRINTF("SHL\t"); break; case 5: DECODE_PRINTF("SHR\t"); break; case 6: DECODE_PRINTF("SAL\t"); break; case 7: DECODE_PRINTF("SAR\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm00_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, amt); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm00_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, amt); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm01_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, amt); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm01_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, amt); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm10_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, amt); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm10_address(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, amt); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; destreg = DECODE_RM_LONG_REGISTER(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); TRACE_AND_STEP(); *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); } else { u16 *destreg; destreg = DECODE_RM_WORD_REGISTER(rl); amt = fetch_byte_imm(); DECODE_PRINTF2(",%x\n", amt); TRACE_AND_STEP(); *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc2 ****************************************************************************/ static void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) { u16 imm; START_OF_INSTR(); DECODE_PRINTF("RET\t"); imm = fetch_word_imm(); DECODE_PRINTF2("%x\n", imm); RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); M.x86.R_IP = pop_word(); M.x86.R_SP += imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc3 ****************************************************************************/ static void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("RET\n"); RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); M.x86.R_IP = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc4 ****************************************************************************/ static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; u16 *dstreg; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("LES\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_ES = fetch_data_word(srcoffset + 2); break; case 1: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_ES = fetch_data_word(srcoffset + 2); break; case 2: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_ES = fetch_data_word(srcoffset + 2); break; case 3: /* register to register */ /* UNDEFINED! */ TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc5 ****************************************************************************/ static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; u16 *dstreg; uint srcoffset; START_OF_INSTR(); DECODE_PRINTF("LDS\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_DS = fetch_data_word(srcoffset + 2); break; case 1: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_DS = fetch_data_word(srcoffset + 2); break; case 2: dstreg = DECODE_RM_WORD_REGISTER(rh); DECODE_PRINTF(","); srcoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *dstreg = fetch_data_word(srcoffset); M.x86.R_DS = fetch_data_word(srcoffset + 2); break; case 3: /* register to register */ /* UNDEFINED! */ TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc6 ****************************************************************************/ static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; uint destoffset; u8 imm; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); HALT_SYS(); } switch (mod) { case 0: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm00_address(rl); imm = fetch_byte_imm(); DECODE_PRINTF2(",%2x\n", imm); TRACE_AND_STEP(); store_data_byte(destoffset, imm); break; case 1: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm01_address(rl); imm = fetch_byte_imm(); DECODE_PRINTF2(",%2x\n", imm); TRACE_AND_STEP(); store_data_byte(destoffset, imm); break; case 2: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); imm = fetch_byte_imm(); DECODE_PRINTF2(",%2x\n", imm); TRACE_AND_STEP(); store_data_byte(destoffset, imm); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); imm = fetch_byte_imm(); DECODE_PRINTF2(",%2x\n", imm); TRACE_AND_STEP(); *destreg = imm; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc7 ****************************************************************************/ static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; START_OF_INSTR(); DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); HALT_SYS(); } switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm00_address(rl); imm = fetch_long_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); store_data_long(destoffset, imm); } else { u16 imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm00_address(rl); imm = fetch_word_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); store_data_word(destoffset, imm); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm01_address(rl); imm = fetch_long_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); store_data_long(destoffset, imm); } else { u16 imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm01_address(rl); imm = fetch_word_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); store_data_word(destoffset, imm); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 imm; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm10_address(rl); imm = fetch_long_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); store_data_long(destoffset, imm); } else { u16 imm; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm10_address(rl); imm = fetch_word_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); store_data_word(destoffset, imm); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 imm; destreg = DECODE_RM_LONG_REGISTER(rl); imm = fetch_long_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); *destreg = imm; } else { u16 *destreg; u16 imm; destreg = DECODE_RM_WORD_REGISTER(rl); imm = fetch_word_imm(); DECODE_PRINTF2(",%x\n", imm); TRACE_AND_STEP(); *destreg = imm; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc8 ****************************************************************************/ static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) { u16 local,frame_pointer; u8 nesting; int i; START_OF_INSTR(); local = fetch_word_imm(); nesting = fetch_byte_imm(); DECODE_PRINTF2("ENTER %x\n", local); DECODE_PRINTF2(",%x\n", nesting); TRACE_AND_STEP(); push_word(M.x86.R_BP); frame_pointer = M.x86.R_SP; if (nesting > 0) { for (i = 1; i < nesting; i++) { M.x86.R_BP -= 2; push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); } push_word(frame_pointer); } M.x86.R_BP = frame_pointer; M.x86.R_SP = (u16)(M.x86.R_SP - local); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xc9 ****************************************************************************/ static void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("LEAVE\n"); TRACE_AND_STEP(); M.x86.R_SP = M.x86.R_BP; M.x86.R_BP = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xca ****************************************************************************/ static void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) { u16 imm; START_OF_INSTR(); DECODE_PRINTF("RETF\t"); imm = fetch_word_imm(); DECODE_PRINTF2("%x\n", imm); RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); M.x86.R_IP = pop_word(); M.x86.R_CS = pop_word(); M.x86.R_SP += imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xcb ****************************************************************************/ static void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("RETF\n"); RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); M.x86.R_IP = pop_word(); M.x86.R_CS = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xcc ****************************************************************************/ static void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("INT 3\n"); TRACE_AND_STEP(); if (_X86EMU_intrTab[3]) { (*_X86EMU_intrTab[3])(3); } else { push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); push_word(M.x86.R_CS); M.x86.R_CS = mem_access_word(3 * 4 + 2); push_word(M.x86.R_IP); M.x86.R_IP = mem_access_word(3 * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xcd ****************************************************************************/ static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) { u8 intnum; START_OF_INSTR(); DECODE_PRINTF("INT\t"); intnum = fetch_byte_imm(); DECODE_PRINTF2("%x\n", intnum); TRACE_AND_STEP(); if (_X86EMU_intrTab[intnum]) { (*_X86EMU_intrTab[intnum])(intnum); } else { push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); push_word(M.x86.R_CS); M.x86.R_CS = mem_access_word(intnum * 4 + 2); push_word(M.x86.R_IP); M.x86.R_IP = mem_access_word(intnum * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xce ****************************************************************************/ static void x86emuOp_into(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("INTO\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_OF)) { if (_X86EMU_intrTab[4]) { (*_X86EMU_intrTab[4])(4); } else { push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); push_word(M.x86.R_CS); M.x86.R_CS = mem_access_word(4 * 4 + 2); push_word(M.x86.R_IP); M.x86.R_IP = mem_access_word(4 * 4); } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xcf ****************************************************************************/ static void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("IRET\n"); TRACE_AND_STEP(); M.x86.R_IP = pop_word(); M.x86.R_CS = pop_word(); M.x86.R_FLG = pop_word(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xd0 ****************************************************************************/ static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; uint destoffset; u8 destval; /* * Yet another weirdo special case instruction format. Part of * the opcode held below in "RH". Doubly nested case would * result, except that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ROL\t"); break; case 1: DECODE_PRINTF("ROR\t"); break; case 2: DECODE_PRINTF("RCL\t"); break; case 3: DECODE_PRINTF("RCR\t"); break; case 4: DECODE_PRINTF("SHL\t"); break; case 5: DECODE_PRINTF("SHR\t"); break; case 6: DECODE_PRINTF("SAL\t"); break; case 7: DECODE_PRINTF("SAR\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ switch (mod) { case 0: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, 1); store_data_byte(destoffset, destval); break; case 1: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, 1); store_data_byte(destoffset, destval); break; case 2: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, 1); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(",1\n"); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (*destreg, 1); *destreg = destval; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xd1 ****************************************************************************/ static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; /* * Yet another weirdo special case instruction format. Part of * the opcode held below in "RH". Doubly nested case would * result, except that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ROL\t"); break; case 1: DECODE_PRINTF("ROR\t"); break; case 2: DECODE_PRINTF("RCL\t"); break; case 3: DECODE_PRINTF("RCR\t"); break; case 4: DECODE_PRINTF("SHL\t"); break; case 5: DECODE_PRINTF("SHR\t"); break; case 6: DECODE_PRINTF("SAL\t"); break; case 7: DECODE_PRINTF("SAR\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, 1); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, 1); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, 1); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, 1); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, 1); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(",1\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, 1); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *destreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(",1\n"); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (*destreg, 1); *destreg = destval; } else { u16 destval; u16 *destreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(",1\n"); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (*destreg, 1); *destreg = destval; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xd2 ****************************************************************************/ static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; uint destoffset; u8 destval; u8 amt; /* * Yet another weirdo special case instruction format. Part of * the opcode held below in "RH". Doubly nested case would * result, except that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ROL\t"); break; case 1: DECODE_PRINTF("ROR\t"); break; case 2: DECODE_PRINTF("RCL\t"); break; case 3: DECODE_PRINTF("RCR\t"); break; case 4: DECODE_PRINTF("SHL\t"); break; case 5: DECODE_PRINTF("SHR\t"); break; case 6: DECODE_PRINTF("SAL\t"); break; case 7: DECODE_PRINTF("SAR\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; switch (mod) { case 0: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, amt); store_data_byte(destoffset, destval); break; case 1: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, amt); store_data_byte(destoffset, destval); break; case 2: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (destval, amt); store_data_byte(destoffset, destval); break; case 3: /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); destval = (*opcD0_byte_operation[rh]) (*destreg, amt); *destreg = destval; break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xd3 ****************************************************************************/ static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; u8 amt; /* * Yet another weirdo special case instruction format. Part of * the opcode held below in "RH". Doubly nested case would * result, except that the decoded instruction */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("ROL\t"); break; case 1: DECODE_PRINTF("ROR\t"); break; case 2: DECODE_PRINTF("RCL\t"); break; case 3: DECODE_PRINTF("RCR\t"); break; case 4: DECODE_PRINTF("SHL\t"); break; case 5: DECODE_PRINTF("SHR\t"); break; case 6: DECODE_PRINTF("SAL\t"); break; case 7: DECODE_PRINTF("SAR\t"); break; } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; switch (mod) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, amt); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, amt); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, amt); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, amt); store_data_word(destoffset, destval); } break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = (*opcD1_long_operation[rh]) (destval, amt); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("WORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(",CL\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = (*opcD1_word_operation[rh]) (destval, amt); store_data_word(destoffset, destval); } break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); } else { u16 *destreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(",CL\n"); TRACE_AND_STEP(); *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xd4 ****************************************************************************/ static void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) { u8 a; START_OF_INSTR(); DECODE_PRINTF("AAM\n"); a = fetch_byte_imm(); /* this is a stupid encoding. */ if (a != 10) { DECODE_PRINTF("ERROR DECODING AAM\n"); TRACE_REGS(); HALT_SYS(); } TRACE_AND_STEP(); /* note the type change here --- returning AL and AH in AX. */ M.x86.R_AX = aam_word(M.x86.R_AL); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xd5 ****************************************************************************/ static void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("AAD\n"); (void) fetch_byte_imm(); TRACE_AND_STEP(); M.x86.R_AX = aad_word(M.x86.R_AX); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /* opcode 0xd6 ILLEGAL OPCODE */ /**************************************************************************** REMARKS: Handles opcode 0xd7 ****************************************************************************/ static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) { u16 addr; START_OF_INSTR(); DECODE_PRINTF("XLAT\n"); TRACE_AND_STEP(); addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); M.x86.R_AL = fetch_data_byte(addr); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /* instuctions D8 .. DF are in i87_ops.c */ /**************************************************************************** REMARKS: Handles opcode 0xe0 ****************************************************************************/ static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) { s16 ip; START_OF_INSTR(); DECODE_PRINTF("LOOPNE\t"); ip = (s8) fetch_byte_imm(); ip += (s16) M.x86.R_IP; DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_CX -= 1; if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe1 ****************************************************************************/ static void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) { s16 ip; START_OF_INSTR(); DECODE_PRINTF("LOOPE\t"); ip = (s8) fetch_byte_imm(); ip += (s16) M.x86.R_IP; DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_CX -= 1; if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe2 ****************************************************************************/ static void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) { s16 ip; START_OF_INSTR(); DECODE_PRINTF("LOOP\t"); ip = (s8) fetch_byte_imm(); ip += (s16) M.x86.R_IP; DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_CX -= 1; if (M.x86.R_CX != 0) M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe3 ****************************************************************************/ static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) { u16 target; s8 offset; /* jump to byte offset if overflow flag is set */ START_OF_INSTR(); DECODE_PRINTF("JCXZ\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (M.x86.R_CX == 0) M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe4 ****************************************************************************/ static void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 port; START_OF_INSTR(); DECODE_PRINTF("IN\t"); port = (u8) fetch_byte_imm(); DECODE_PRINTF2("%x,AL\n", port); TRACE_AND_STEP(); M.x86.R_AL = (*sys_inb)(port); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe5 ****************************************************************************/ static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u8 port; START_OF_INSTR(); DECODE_PRINTF("IN\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF2("EAX,%x\n", port); } else { DECODE_PRINTF2("AX,%x\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = (*sys_inl)(port); } else { M.x86.R_AX = (*sys_inw)(port); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe6 ****************************************************************************/ static void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) { u8 port; START_OF_INSTR(); DECODE_PRINTF("OUT\t"); port = (u8) fetch_byte_imm(); DECODE_PRINTF2("%x,AL\n", port); TRACE_AND_STEP(); (*sys_outb)(port, M.x86.R_AL); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe7 ****************************************************************************/ static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) { u8 port; START_OF_INSTR(); DECODE_PRINTF("OUT\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF2("%x,EAX\n", port); } else { DECODE_PRINTF2("%x,AX\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { (*sys_outl)(port, M.x86.R_EAX); } else { (*sys_outw)(port, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe8 ****************************************************************************/ static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) { s16 ip; START_OF_INSTR(); DECODE_PRINTF("CALL\t"); ip = (s16) fetch_word_imm(); ip += (s16) M.x86.R_IP; /* CHECK SIGN */ DECODE_PRINTF2("%04x\n", (u16)ip); CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); TRACE_AND_STEP(); push_word(M.x86.R_IP); M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xe9 ****************************************************************************/ static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) { int ip; START_OF_INSTR(); DECODE_PRINTF("JMP\t"); ip = (s16)fetch_word_imm(); ip += (s16)M.x86.R_IP; DECODE_PRINTF2("%04x\n", (u16)ip); TRACE_AND_STEP(); M.x86.R_IP = (u16)ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xea ****************************************************************************/ static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) { u16 cs, ip; START_OF_INSTR(); DECODE_PRINTF("JMP\tFAR "); ip = fetch_word_imm(); cs = fetch_word_imm(); DECODE_PRINTF2("%04x:", cs); DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_IP = ip; M.x86.R_CS = cs; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xeb ****************************************************************************/ static void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) { u16 target; s8 offset; START_OF_INSTR(); DECODE_PRINTF("JMP\t"); offset = (s8)fetch_byte_imm(); target = (u16)(M.x86.R_IP + offset); DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xec ****************************************************************************/ static void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("IN\tAL,DX\n"); TRACE_AND_STEP(); M.x86.R_AL = (*sys_inb)(M.x86.R_DX); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xed ****************************************************************************/ static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("IN\tEAX,DX\n"); } else { DECODE_PRINTF("IN\tAX,DX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); } else { M.x86.R_AX = (*sys_inw)(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xee ****************************************************************************/ static void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("OUT\tDX,AL\n"); TRACE_AND_STEP(); (*sys_outb)(M.x86.R_DX, M.x86.R_AL); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xef ****************************************************************************/ static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("OUT\tDX,EAX\n"); } else { DECODE_PRINTF("OUT\tDX,AX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); } else { (*sys_outw)(M.x86.R_DX, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf0 ****************************************************************************/ static void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("LOCK:\n"); TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /*opcode 0xf1 ILLEGAL OPERATION */ /**************************************************************************** REMARKS: Handles opcode 0xf2 ****************************************************************************/ static void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("REPNE\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_REPNE; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf3 ****************************************************************************/ static void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("REPE\n"); TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_REPE; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf4 ****************************************************************************/ static void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("HALT\n"); TRACE_AND_STEP(); HALT_SYS(); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf5 ****************************************************************************/ static void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) { /* complement the carry flag. */ START_OF_INSTR(); DECODE_PRINTF("CMC\n"); TRACE_AND_STEP(); TOGGLE_FLAG(F_CF); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf6 ****************************************************************************/ static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; uint destoffset; u8 destval, srcval; /* long, drawn out code follows. Double switch for a total of 32 cases. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: /* mod=00 */ switch (rh) { case 0: /* test byte imm */ DECODE_PRINTF("TEST\tBYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); srcval = fetch_byte_imm(); DECODE_PRINTF2("%02x\n", srcval); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); test_byte(destval, srcval); break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: DECODE_PRINTF("NOT\tBYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = not_byte(destval); store_data_byte(destoffset, destval); break; case 3: DECODE_PRINTF("NEG\tBYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = neg_byte(destval); store_data_byte(destoffset, destval); break; case 4: DECODE_PRINTF("MUL\tBYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); mul_byte(destval); break; case 5: DECODE_PRINTF("IMUL\tBYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); imul_byte(destval); break; case 6: DECODE_PRINTF("DIV\tBYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); div_byte(destval); break; case 7: DECODE_PRINTF("IDIV\tBYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); idiv_byte(destval); break; } break; /* end mod==00 */ case 1: /* mod=01 */ switch (rh) { case 0: /* test byte imm */ DECODE_PRINTF("TEST\tBYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); srcval = fetch_byte_imm(); DECODE_PRINTF2("%02x\n", srcval); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); test_byte(destval, srcval); break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: DECODE_PRINTF("NOT\tBYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = not_byte(destval); store_data_byte(destoffset, destval); break; case 3: DECODE_PRINTF("NEG\tBYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = neg_byte(destval); store_data_byte(destoffset, destval); break; case 4: DECODE_PRINTF("MUL\tBYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); mul_byte(destval); break; case 5: DECODE_PRINTF("IMUL\tBYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); imul_byte(destval); break; case 6: DECODE_PRINTF("DIV\tBYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); div_byte(destval); break; case 7: DECODE_PRINTF("IDIV\tBYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); idiv_byte(destval); break; } break; /* end mod==01 */ case 2: /* mod=10 */ switch (rh) { case 0: /* test byte imm */ DECODE_PRINTF("TEST\tBYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); srcval = fetch_byte_imm(); DECODE_PRINTF2("%02x\n", srcval); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); test_byte(destval, srcval); break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: DECODE_PRINTF("NOT\tBYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = not_byte(destval); store_data_byte(destoffset, destval); break; case 3: DECODE_PRINTF("NEG\tBYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = neg_byte(destval); store_data_byte(destoffset, destval); break; case 4: DECODE_PRINTF("MUL\tBYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); mul_byte(destval); break; case 5: DECODE_PRINTF("IMUL\tBYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); imul_byte(destval); break; case 6: DECODE_PRINTF("DIV\tBYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); div_byte(destval); break; case 7: DECODE_PRINTF("IDIV\tBYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); idiv_byte(destval); break; } break; /* end mod==10 */ case 3: /* mod=11 */ switch (rh) { case 0: /* test byte imm */ DECODE_PRINTF("TEST\t"); destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF(","); srcval = fetch_byte_imm(); DECODE_PRINTF2("%02x\n", srcval); TRACE_AND_STEP(); test_byte(*destreg, srcval); break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: DECODE_PRINTF("NOT\t"); destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = not_byte(*destreg); break; case 3: DECODE_PRINTF("NEG\t"); destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = neg_byte(*destreg); break; case 4: DECODE_PRINTF("MUL\t"); destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); mul_byte(*destreg); /*!!! */ break; case 5: DECODE_PRINTF("IMUL\t"); destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); imul_byte(*destreg); break; case 6: DECODE_PRINTF("DIV\t"); destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); div_byte(*destreg); break; case 7: DECODE_PRINTF("IDIV\t"); destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); idiv_byte(*destreg); break; } break; /* end mod==11 */ } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf7 ****************************************************************************/ static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; /* long, drawn out code follows. Double switch for a total of 32 cases. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); switch (mod) { case 0: /* mod=00 */ switch (rh) { case 0: /* test word imm */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,srcval; DECODE_PRINTF("TEST\tDWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); srcval = fetch_long_imm(); DECODE_PRINTF2("%x\n", srcval); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); test_long(destval, srcval); } else { u16 destval,srcval; DECODE_PRINTF("TEST\tWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF(","); srcval = fetch_word_imm(); DECODE_PRINTF2("%x\n", srcval); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); test_word(destval, srcval); } break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); HALT_SYS(); break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("NOT\tDWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = not_long(destval); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("NOT\tWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = not_word(destval); store_data_word(destoffset, destval); } break; case 3: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("NEG\tDWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = neg_long(destval); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("NEG\tWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = neg_word(destval); store_data_word(destoffset, destval); } break; case 4: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("MUL\tDWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); mul_long(destval); } else { u16 destval; DECODE_PRINTF("MUL\tWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); mul_word(destval); } break; case 5: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("IMUL\tDWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); imul_long(destval); } else { u16 destval; DECODE_PRINTF("IMUL\tWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); imul_word(destval); } break; case 6: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DIV\tDWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); div_long(destval); } else { u16 destval; DECODE_PRINTF("DIV\tWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); div_word(destval); } break; case 7: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("IDIV\tDWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); idiv_long(destval); } else { u16 destval; DECODE_PRINTF("IDIV\tWORD PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); idiv_word(destval); } break; } break; /* end mod==00 */ case 1: /* mod=01 */ switch (rh) { case 0: /* test word imm */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,srcval; DECODE_PRINTF("TEST\tDWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); srcval = fetch_long_imm(); DECODE_PRINTF2("%x\n", srcval); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); test_long(destval, srcval); } else { u16 destval,srcval; DECODE_PRINTF("TEST\tWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF(","); srcval = fetch_word_imm(); DECODE_PRINTF2("%x\n", srcval); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); test_word(destval, srcval); } break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("NOT\tDWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = not_long(destval); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("NOT\tWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = not_word(destval); store_data_word(destoffset, destval); } break; case 3: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("NEG\tDWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = neg_long(destval); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("NEG\tWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = neg_word(destval); store_data_word(destoffset, destval); } break; case 4: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("MUL\tDWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); mul_long(destval); } else { u16 destval; DECODE_PRINTF("MUL\tWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); mul_word(destval); } break; case 5: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("IMUL\tDWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); imul_long(destval); } else { u16 destval; DECODE_PRINTF("IMUL\tWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); imul_word(destval); } break; case 6: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DIV\tDWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); div_long(destval); } else { u16 destval; DECODE_PRINTF("DIV\tWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); div_word(destval); } break; case 7: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("IDIV\tDWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); idiv_long(destval); } else { u16 destval; DECODE_PRINTF("IDIV\tWORD PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); idiv_word(destval); } break; } break; /* end mod==01 */ case 2: /* mod=10 */ switch (rh) { case 0: /* test word imm */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval,srcval; DECODE_PRINTF("TEST\tDWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); srcval = fetch_long_imm(); DECODE_PRINTF2("%x\n", srcval); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); test_long(destval, srcval); } else { u16 destval,srcval; DECODE_PRINTF("TEST\tWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF(","); srcval = fetch_word_imm(); DECODE_PRINTF2("%x\n", srcval); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); test_word(destval, srcval); } break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("NOT\tDWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = not_long(destval); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("NOT\tWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = not_word(destval); store_data_word(destoffset, destval); } break; case 3: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("NEG\tDWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = neg_long(destval); store_data_long(destoffset, destval); } else { u16 destval; DECODE_PRINTF("NEG\tWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = neg_word(destval); store_data_word(destoffset, destval); } break; case 4: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("MUL\tDWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); mul_long(destval); } else { u16 destval; DECODE_PRINTF("MUL\tWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); mul_word(destval); } break; case 5: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("IMUL\tDWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); imul_long(destval); } else { u16 destval; DECODE_PRINTF("IMUL\tWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); imul_word(destval); } break; case 6: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("DIV\tDWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); div_long(destval); } else { u16 destval; DECODE_PRINTF("DIV\tWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); div_word(destval); } break; case 7: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; DECODE_PRINTF("IDIV\tDWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_long(destoffset); TRACE_AND_STEP(); idiv_long(destval); } else { u16 destval; DECODE_PRINTF("IDIV\tWORD PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); destval = fetch_data_word(destoffset); TRACE_AND_STEP(); idiv_word(destval); } break; } break; /* end mod==10 */ case 3: /* mod=11 */ switch (rh) { case 0: /* test word imm */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 srcval; DECODE_PRINTF("TEST\t"); destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); srcval = fetch_long_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); test_long(*destreg, srcval); } else { u16 *destreg; u16 srcval; DECODE_PRINTF("TEST\t"); destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); srcval = fetch_word_imm(); DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); test_word(*destreg, srcval); } break; case 1: DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; DECODE_PRINTF("NOT\t"); destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = not_long(*destreg); } else { u16 *destreg; DECODE_PRINTF("NOT\t"); destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = not_word(*destreg); } break; case 3: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; DECODE_PRINTF("NEG\t"); destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = neg_long(*destreg); } else { u16 *destreg; DECODE_PRINTF("NEG\t"); destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = neg_word(*destreg); } break; case 4: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; DECODE_PRINTF("MUL\t"); destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); mul_long(*destreg); /*!!! */ } else { u16 *destreg; DECODE_PRINTF("MUL\t"); destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); mul_word(*destreg); /*!!! */ } break; case 5: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; DECODE_PRINTF("IMUL\t"); destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); imul_long(*destreg); } else { u16 *destreg; DECODE_PRINTF("IMUL\t"); destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); imul_word(*destreg); } break; case 6: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; DECODE_PRINTF("DIV\t"); destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); div_long(*destreg); } else { u16 *destreg; DECODE_PRINTF("DIV\t"); destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); div_word(*destreg); } break; case 7: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; DECODE_PRINTF("IDIV\t"); destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); idiv_long(*destreg); } else { u16 *destreg; DECODE_PRINTF("IDIV\t"); destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); idiv_word(*destreg); } break; } break; /* end mod==11 */ } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf8 ****************************************************************************/ static void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) { /* clear the carry flag. */ START_OF_INSTR(); DECODE_PRINTF("CLC\n"); TRACE_AND_STEP(); CLEAR_FLAG(F_CF); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xf9 ****************************************************************************/ static void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) { /* set the carry flag. */ START_OF_INSTR(); DECODE_PRINTF("STC\n"); TRACE_AND_STEP(); SET_FLAG(F_CF); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xfa ****************************************************************************/ static void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) { /* clear interrupts. */ START_OF_INSTR(); DECODE_PRINTF("CLI\n"); TRACE_AND_STEP(); CLEAR_FLAG(F_IF); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xfb ****************************************************************************/ static void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) { /* enable interrupts. */ START_OF_INSTR(); DECODE_PRINTF("STI\n"); TRACE_AND_STEP(); SET_FLAG(F_IF); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xfc ****************************************************************************/ static void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) { /* clear interrupts. */ START_OF_INSTR(); DECODE_PRINTF("CLD\n"); TRACE_AND_STEP(); CLEAR_FLAG(F_DF); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xfd ****************************************************************************/ static void x86emuOp_std(u8 X86EMU_UNUSED(op1)) { /* clear interrupts. */ START_OF_INSTR(); DECODE_PRINTF("STD\n"); TRACE_AND_STEP(); SET_FLAG(F_DF); DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xfe ****************************************************************************/ static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; u8 destval; uint destoffset; u8 *destreg; /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: DECODE_PRINTF("INC\t"); break; case 1: DECODE_PRINTF("DEC\t"); break; case 2: case 3: case 4: case 5: case 6: case 7: DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); HALT_SYS(); break; } } #endif switch (mod) { case 0: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); switch (rh) { case 0: /* inc word ptr ... */ destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = inc_byte(destval); store_data_byte(destoffset, destval); break; case 1: /* dec word ptr ... */ destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = dec_byte(destval); store_data_byte(destoffset, destval); break; } break; case 1: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); switch (rh) { case 0: destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = inc_byte(destval); store_data_byte(destoffset, destval); break; case 1: destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = dec_byte(destval); store_data_byte(destoffset, destval); break; } break; case 2: DECODE_PRINTF("BYTE PTR "); destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); switch (rh) { case 0: destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = inc_byte(destval); store_data_byte(destoffset, destval); break; case 1: destval = fetch_data_byte(destoffset); TRACE_AND_STEP(); destval = dec_byte(destval); store_data_byte(destoffset, destval); break; } break; case 3: destreg = DECODE_RM_BYTE_REGISTER(rl); DECODE_PRINTF("\n"); switch (rh) { case 0: TRACE_AND_STEP(); *destreg = inc_byte(*destreg); break; case 1: TRACE_AND_STEP(); *destreg = dec_byte(*destreg); break; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /**************************************************************************** REMARKS: Handles opcode 0xff ****************************************************************************/ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; uint destoffset = 0; u16 *destreg; u16 destval,destval2; /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings in the same format, even though the result is that the above test is done twice. */ switch (rh) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("INC\tDWORD PTR "); } else { DECODE_PRINTF("INC\tWORD PTR "); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { DECODE_PRINTF("DEC\tDWORD PTR "); } else { DECODE_PRINTF("DEC\tWORD PTR "); } break; case 2: DECODE_PRINTF("CALL\t"); break; case 3: DECODE_PRINTF("CALL\tFAR "); break; case 4: DECODE_PRINTF("JMP\t"); break; case 5: DECODE_PRINTF("JMP\tFAR "); break; case 6: DECODE_PRINTF("PUSH\t"); break; case 7: DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); HALT_SYS(); break; } } #endif switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); switch (rh) { case 0: /* inc word ptr ... */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = inc_long(destval); store_data_long(destoffset, destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = inc_word(destval); store_data_word(destoffset, destval); } break; case 1: /* dec word ptr ... */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = dec_long(destval); store_data_long(destoffset, destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = dec_word(destval); store_data_word(destoffset, destval); } break; case 2: /* call word ptr ... */ destval = fetch_data_word(destoffset); TRACE_AND_STEP(); push_word(M.x86.R_IP); M.x86.R_IP = destval; break; case 3: /* call far ptr ... */ destval = fetch_data_word(destoffset); destval2 = fetch_data_word(destoffset + 2); TRACE_AND_STEP(); push_word(M.x86.R_CS); M.x86.R_CS = destval2; push_word(M.x86.R_IP); M.x86.R_IP = destval; break; case 4: /* jmp word ptr ... */ destval = fetch_data_word(destoffset); TRACE_AND_STEP(); M.x86.R_IP = destval; break; case 5: /* jmp far ptr ... */ destval = fetch_data_word(destoffset); destval2 = fetch_data_word(destoffset + 2); TRACE_AND_STEP(); M.x86.R_IP = destval; M.x86.R_CS = destval2; break; case 6: /* push word ptr ... */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); push_long(destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); push_word(destval); } break; } break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); switch (rh) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = inc_long(destval); store_data_long(destoffset, destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = inc_word(destval); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = dec_long(destval); store_data_long(destoffset, destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = dec_word(destval); store_data_word(destoffset, destval); } break; case 2: /* call word ptr ... */ destval = fetch_data_word(destoffset); TRACE_AND_STEP(); push_word(M.x86.R_IP); M.x86.R_IP = destval; break; case 3: /* call far ptr ... */ destval = fetch_data_word(destoffset); destval2 = fetch_data_word(destoffset + 2); TRACE_AND_STEP(); push_word(M.x86.R_CS); M.x86.R_CS = destval2; push_word(M.x86.R_IP); M.x86.R_IP = destval; break; case 4: /* jmp word ptr ... */ destval = fetch_data_word(destoffset); TRACE_AND_STEP(); M.x86.R_IP = destval; break; case 5: /* jmp far ptr ... */ destval = fetch_data_word(destoffset); destval2 = fetch_data_word(destoffset + 2); TRACE_AND_STEP(); M.x86.R_IP = destval; M.x86.R_CS = destval2; break; case 6: /* push word ptr ... */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); push_long(destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); push_word(destval); } break; } break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); switch (rh) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = inc_long(destval); store_data_long(destoffset, destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = inc_word(destval); store_data_word(destoffset, destval); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); destval = dec_long(destval); store_data_long(destoffset, destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); destval = dec_word(destval); store_data_word(destoffset, destval); } break; case 2: /* call word ptr ... */ destval = fetch_data_word(destoffset); TRACE_AND_STEP(); push_word(M.x86.R_IP); M.x86.R_IP = destval; break; case 3: /* call far ptr ... */ destval = fetch_data_word(destoffset); destval2 = fetch_data_word(destoffset + 2); TRACE_AND_STEP(); push_word(M.x86.R_CS); M.x86.R_CS = destval2; push_word(M.x86.R_IP); M.x86.R_IP = destval; break; case 4: /* jmp word ptr ... */ destval = fetch_data_word(destoffset); TRACE_AND_STEP(); M.x86.R_IP = destval; break; case 5: /* jmp far ptr ... */ destval = fetch_data_word(destoffset); destval2 = fetch_data_word(destoffset + 2); TRACE_AND_STEP(); M.x86.R_IP = destval; M.x86.R_CS = destval2; break; case 6: /* push word ptr ... */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; destval = fetch_data_long(destoffset); TRACE_AND_STEP(); push_long(destval); } else { u16 destval; destval = fetch_data_word(destoffset); TRACE_AND_STEP(); push_word(destval); } break; } break; case 3: switch (rh) { case 0: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = inc_long(*destreg); } else { u16 *destreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = inc_word(*destreg); } break; case 1: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = dec_long(*destreg); } else { u16 *destreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = dec_word(*destreg); } break; case 2: /* call word ptr ... */ destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); push_word(M.x86.R_IP); M.x86.R_IP = *destreg; break; case 3: /* jmp far ptr ... */ DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); TRACE_AND_STEP(); HALT_SYS(); break; case 4: /* jmp ... */ destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); M.x86.R_IP = (u16) (*destreg); break; case 5: /* jmp far ptr ... */ DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); TRACE_AND_STEP(); HALT_SYS(); break; case 6: if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; destreg = DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); push_long(*destreg); } else { u16 *destreg; destreg = DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF("\n"); TRACE_AND_STEP(); push_word(*destreg); } break; } break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } /*************************************************************************** * Single byte operation code table: **************************************************************************/ void (*x86emu_optab[256])(u8) = { /* 0x00 */ x86emuOp_add_byte_RM_R, /* 0x01 */ x86emuOp_add_word_RM_R, /* 0x02 */ x86emuOp_add_byte_R_RM, /* 0x03 */ x86emuOp_add_word_R_RM, /* 0x04 */ x86emuOp_add_byte_AL_IMM, /* 0x05 */ x86emuOp_add_word_AX_IMM, /* 0x06 */ x86emuOp_push_ES, /* 0x07 */ x86emuOp_pop_ES, /* 0x08 */ x86emuOp_or_byte_RM_R, /* 0x09 */ x86emuOp_or_word_RM_R, /* 0x0a */ x86emuOp_or_byte_R_RM, /* 0x0b */ x86emuOp_or_word_R_RM, /* 0x0c */ x86emuOp_or_byte_AL_IMM, /* 0x0d */ x86emuOp_or_word_AX_IMM, /* 0x0e */ x86emuOp_push_CS, /* 0x0f */ x86emuOp_two_byte, /* 0x10 */ x86emuOp_adc_byte_RM_R, /* 0x11 */ x86emuOp_adc_word_RM_R, /* 0x12 */ x86emuOp_adc_byte_R_RM, /* 0x13 */ x86emuOp_adc_word_R_RM, /* 0x14 */ x86emuOp_adc_byte_AL_IMM, /* 0x15 */ x86emuOp_adc_word_AX_IMM, /* 0x16 */ x86emuOp_push_SS, /* 0x17 */ x86emuOp_pop_SS, /* 0x18 */ x86emuOp_sbb_byte_RM_R, /* 0x19 */ x86emuOp_sbb_word_RM_R, /* 0x1a */ x86emuOp_sbb_byte_R_RM, /* 0x1b */ x86emuOp_sbb_word_R_RM, /* 0x1c */ x86emuOp_sbb_byte_AL_IMM, /* 0x1d */ x86emuOp_sbb_word_AX_IMM, /* 0x1e */ x86emuOp_push_DS, /* 0x1f */ x86emuOp_pop_DS, /* 0x20 */ x86emuOp_and_byte_RM_R, /* 0x21 */ x86emuOp_and_word_RM_R, /* 0x22 */ x86emuOp_and_byte_R_RM, /* 0x23 */ x86emuOp_and_word_R_RM, /* 0x24 */ x86emuOp_and_byte_AL_IMM, /* 0x25 */ x86emuOp_and_word_AX_IMM, /* 0x26 */ x86emuOp_segovr_ES, /* 0x27 */ x86emuOp_daa, /* 0x28 */ x86emuOp_sub_byte_RM_R, /* 0x29 */ x86emuOp_sub_word_RM_R, /* 0x2a */ x86emuOp_sub_byte_R_RM, /* 0x2b */ x86emuOp_sub_word_R_RM, /* 0x2c */ x86emuOp_sub_byte_AL_IMM, /* 0x2d */ x86emuOp_sub_word_AX_IMM, /* 0x2e */ x86emuOp_segovr_CS, /* 0x2f */ x86emuOp_das, /* 0x30 */ x86emuOp_xor_byte_RM_R, /* 0x31 */ x86emuOp_xor_word_RM_R, /* 0x32 */ x86emuOp_xor_byte_R_RM, /* 0x33 */ x86emuOp_xor_word_R_RM, /* 0x34 */ x86emuOp_xor_byte_AL_IMM, /* 0x35 */ x86emuOp_xor_word_AX_IMM, /* 0x36 */ x86emuOp_segovr_SS, /* 0x37 */ x86emuOp_aaa, /* 0x38 */ x86emuOp_cmp_byte_RM_R, /* 0x39 */ x86emuOp_cmp_word_RM_R, /* 0x3a */ x86emuOp_cmp_byte_R_RM, /* 0x3b */ x86emuOp_cmp_word_R_RM, /* 0x3c */ x86emuOp_cmp_byte_AL_IMM, /* 0x3d */ x86emuOp_cmp_word_AX_IMM, /* 0x3e */ x86emuOp_segovr_DS, /* 0x3f */ x86emuOp_aas, /* 0x40 */ x86emuOp_inc_AX, /* 0x41 */ x86emuOp_inc_CX, /* 0x42 */ x86emuOp_inc_DX, /* 0x43 */ x86emuOp_inc_BX, /* 0x44 */ x86emuOp_inc_SP, /* 0x45 */ x86emuOp_inc_BP, /* 0x46 */ x86emuOp_inc_SI, /* 0x47 */ x86emuOp_inc_DI, /* 0x48 */ x86emuOp_dec_AX, /* 0x49 */ x86emuOp_dec_CX, /* 0x4a */ x86emuOp_dec_DX, /* 0x4b */ x86emuOp_dec_BX, /* 0x4c */ x86emuOp_dec_SP, /* 0x4d */ x86emuOp_dec_BP, /* 0x4e */ x86emuOp_dec_SI, /* 0x4f */ x86emuOp_dec_DI, /* 0x50 */ x86emuOp_push_AX, /* 0x51 */ x86emuOp_push_CX, /* 0x52 */ x86emuOp_push_DX, /* 0x53 */ x86emuOp_push_BX, /* 0x54 */ x86emuOp_push_SP, /* 0x55 */ x86emuOp_push_BP, /* 0x56 */ x86emuOp_push_SI, /* 0x57 */ x86emuOp_push_DI, /* 0x58 */ x86emuOp_pop_AX, /* 0x59 */ x86emuOp_pop_CX, /* 0x5a */ x86emuOp_pop_DX, /* 0x5b */ x86emuOp_pop_BX, /* 0x5c */ x86emuOp_pop_SP, /* 0x5d */ x86emuOp_pop_BP, /* 0x5e */ x86emuOp_pop_SI, /* 0x5f */ x86emuOp_pop_DI, /* 0x60 */ x86emuOp_push_all, /* 0x61 */ x86emuOp_pop_all, /* 0x62 */ x86emuOp_illegal_op, /* bound */ /* 0x63 */ x86emuOp_illegal_op, /* arpl */ /* 0x64 */ x86emuOp_segovr_FS, /* 0x65 */ x86emuOp_segovr_GS, /* 0x66 */ x86emuOp_prefix_data, /* 0x67 */ x86emuOp_prefix_addr, /* 0x68 */ x86emuOp_push_word_IMM, /* 0x69 */ x86emuOp_imul_word_IMM, /* 0x6a */ x86emuOp_push_byte_IMM, /* 0x6b */ x86emuOp_imul_byte_IMM, /* 0x6c */ x86emuOp_ins_byte, /* 0x6d */ x86emuOp_ins_word, /* 0x6e */ x86emuOp_outs_byte, /* 0x6f */ x86emuOp_outs_word, /* 0x70 */ x86emuOp_jump_near_O, /* 0x71 */ x86emuOp_jump_near_NO, /* 0x72 */ x86emuOp_jump_near_B, /* 0x73 */ x86emuOp_jump_near_NB, /* 0x74 */ x86emuOp_jump_near_Z, /* 0x75 */ x86emuOp_jump_near_NZ, /* 0x76 */ x86emuOp_jump_near_BE, /* 0x77 */ x86emuOp_jump_near_NBE, /* 0x78 */ x86emuOp_jump_near_S, /* 0x79 */ x86emuOp_jump_near_NS, /* 0x7a */ x86emuOp_jump_near_P, /* 0x7b */ x86emuOp_jump_near_NP, /* 0x7c */ x86emuOp_jump_near_L, /* 0x7d */ x86emuOp_jump_near_NL, /* 0x7e */ x86emuOp_jump_near_LE, /* 0x7f */ x86emuOp_jump_near_NLE, /* 0x80 */ x86emuOp_opc80_byte_RM_IMM, /* 0x81 */ x86emuOp_opc81_word_RM_IMM, /* 0x82 */ x86emuOp_opc82_byte_RM_IMM, /* 0x83 */ x86emuOp_opc83_word_RM_IMM, /* 0x84 */ x86emuOp_test_byte_RM_R, /* 0x85 */ x86emuOp_test_word_RM_R, /* 0x86 */ x86emuOp_xchg_byte_RM_R, /* 0x87 */ x86emuOp_xchg_word_RM_R, /* 0x88 */ x86emuOp_mov_byte_RM_R, /* 0x89 */ x86emuOp_mov_word_RM_R, /* 0x8a */ x86emuOp_mov_byte_R_RM, /* 0x8b */ x86emuOp_mov_word_R_RM, /* 0x8c */ x86emuOp_mov_word_RM_SR, /* 0x8d */ x86emuOp_lea_word_R_M, /* 0x8e */ x86emuOp_mov_word_SR_RM, /* 0x8f */ x86emuOp_pop_RM, /* 0x90 */ x86emuOp_nop, /* 0x91 */ x86emuOp_xchg_word_AX_CX, /* 0x92 */ x86emuOp_xchg_word_AX_DX, /* 0x93 */ x86emuOp_xchg_word_AX_BX, /* 0x94 */ x86emuOp_xchg_word_AX_SP, /* 0x95 */ x86emuOp_xchg_word_AX_BP, /* 0x96 */ x86emuOp_xchg_word_AX_SI, /* 0x97 */ x86emuOp_xchg_word_AX_DI, /* 0x98 */ x86emuOp_cbw, /* 0x99 */ x86emuOp_cwd, /* 0x9a */ x86emuOp_call_far_IMM, /* 0x9b */ x86emuOp_wait, /* 0x9c */ x86emuOp_pushf_word, /* 0x9d */ x86emuOp_popf_word, /* 0x9e */ x86emuOp_sahf, /* 0x9f */ x86emuOp_lahf, /* 0xa0 */ x86emuOp_mov_AL_M_IMM, /* 0xa1 */ x86emuOp_mov_AX_M_IMM, /* 0xa2 */ x86emuOp_mov_M_AL_IMM, /* 0xa3 */ x86emuOp_mov_M_AX_IMM, /* 0xa4 */ x86emuOp_movs_byte, /* 0xa5 */ x86emuOp_movs_word, /* 0xa6 */ x86emuOp_cmps_byte, /* 0xa7 */ x86emuOp_cmps_word, /* 0xa8 */ x86emuOp_test_AL_IMM, /* 0xa9 */ x86emuOp_test_AX_IMM, /* 0xaa */ x86emuOp_stos_byte, /* 0xab */ x86emuOp_stos_word, /* 0xac */ x86emuOp_lods_byte, /* 0xad */ x86emuOp_lods_word, /* 0xac */ x86emuOp_scas_byte, /* 0xad */ x86emuOp_scas_word, /* 0xb0 */ x86emuOp_mov_byte_AL_IMM, /* 0xb1 */ x86emuOp_mov_byte_CL_IMM, /* 0xb2 */ x86emuOp_mov_byte_DL_IMM, /* 0xb3 */ x86emuOp_mov_byte_BL_IMM, /* 0xb4 */ x86emuOp_mov_byte_AH_IMM, /* 0xb5 */ x86emuOp_mov_byte_CH_IMM, /* 0xb6 */ x86emuOp_mov_byte_DH_IMM, /* 0xb7 */ x86emuOp_mov_byte_BH_IMM, /* 0xb8 */ x86emuOp_mov_word_AX_IMM, /* 0xb9 */ x86emuOp_mov_word_CX_IMM, /* 0xba */ x86emuOp_mov_word_DX_IMM, /* 0xbb */ x86emuOp_mov_word_BX_IMM, /* 0xbc */ x86emuOp_mov_word_SP_IMM, /* 0xbd */ x86emuOp_mov_word_BP_IMM, /* 0xbe */ x86emuOp_mov_word_SI_IMM, /* 0xbf */ x86emuOp_mov_word_DI_IMM, /* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, /* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, /* 0xc2 */ x86emuOp_ret_near_IMM, /* 0xc3 */ x86emuOp_ret_near, /* 0xc4 */ x86emuOp_les_R_IMM, /* 0xc5 */ x86emuOp_lds_R_IMM, /* 0xc6 */ x86emuOp_mov_byte_RM_IMM, /* 0xc7 */ x86emuOp_mov_word_RM_IMM, /* 0xc8 */ x86emuOp_enter, /* 0xc9 */ x86emuOp_leave, /* 0xca */ x86emuOp_ret_far_IMM, /* 0xcb */ x86emuOp_ret_far, /* 0xcc */ x86emuOp_int3, /* 0xcd */ x86emuOp_int_IMM, /* 0xce */ x86emuOp_into, /* 0xcf */ x86emuOp_iret, /* 0xd0 */ x86emuOp_opcD0_byte_RM_1, /* 0xd1 */ x86emuOp_opcD1_word_RM_1, /* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, /* 0xd3 */ x86emuOp_opcD3_word_RM_CL, /* 0xd4 */ x86emuOp_aam, /* 0xd5 */ x86emuOp_aad, /* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ /* 0xd7 */ x86emuOp_xlat, /* 0xd8 */ x86emuOp_esc_coprocess_d8, /* 0xd9 */ x86emuOp_esc_coprocess_d9, /* 0xda */ x86emuOp_esc_coprocess_da, /* 0xdb */ x86emuOp_esc_coprocess_db, /* 0xdc */ x86emuOp_esc_coprocess_dc, /* 0xdd */ x86emuOp_esc_coprocess_dd, /* 0xde */ x86emuOp_esc_coprocess_de, /* 0xdf */ x86emuOp_esc_coprocess_df, /* 0xe0 */ x86emuOp_loopne, /* 0xe1 */ x86emuOp_loope, /* 0xe2 */ x86emuOp_loop, /* 0xe3 */ x86emuOp_jcxz, /* 0xe4 */ x86emuOp_in_byte_AL_IMM, /* 0xe5 */ x86emuOp_in_word_AX_IMM, /* 0xe6 */ x86emuOp_out_byte_IMM_AL, /* 0xe7 */ x86emuOp_out_word_IMM_AX, /* 0xe8 */ x86emuOp_call_near_IMM, /* 0xe9 */ x86emuOp_jump_near_IMM, /* 0xea */ x86emuOp_jump_far_IMM, /* 0xeb */ x86emuOp_jump_byte_IMM, /* 0xec */ x86emuOp_in_byte_AL_DX, /* 0xed */ x86emuOp_in_word_AX_DX, /* 0xee */ x86emuOp_out_byte_DX_AL, /* 0xef */ x86emuOp_out_word_DX_AX, /* 0xf0 */ x86emuOp_lock, /* 0xf1 */ x86emuOp_illegal_op, /* 0xf2 */ x86emuOp_repne, /* 0xf3 */ x86emuOp_repe, /* 0xf4 */ x86emuOp_halt, /* 0xf5 */ x86emuOp_cmc, /* 0xf6 */ x86emuOp_opcF6_byte_RM, /* 0xf7 */ x86emuOp_opcF7_word_RM, /* 0xf8 */ x86emuOp_clc, /* 0xf9 */ x86emuOp_stc, /* 0xfa */ x86emuOp_cli, /* 0xfb */ x86emuOp_sti, /* 0xfc */ x86emuOp_cld, /* 0xfd */ x86emuOp_std, /* 0xfe */ x86emuOp_opcFE_byte_RM, /* 0xff */ x86emuOp_opcFF_word_RM, }; xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/fpu.c0000644000000000000000000006465510410136571015726 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: This file contains the code to implement the decoding and * emulation of the FPU instructions. * ****************************************************************************/ #include "x86emu/x86emui.h" /*----------------------------- Implementation ----------------------------*/ /* opcode=0xd8 */ void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("ESC D8\n"); DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } #ifdef DEBUG static char *x86emu_fpu_op_d9_tab[] = { "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", }; static char *x86emu_fpu_op_d9_tab1[] = { "FLD\t", "FLD\t", "FLD\t", "FLD\t", "FLD\t", "FLD\t", "FLD\t", "FLD\t", "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", "FNOP", "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", "FCHS", "FABS", "ESC_D9", "ESC_D9", "FTST", "FXAM", "ESC_D9", "ESC_D9", "FLD1", "FLDL2T", "FLDL2E", "FLDPI", "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9", "F2XM1", "FYL2X", "FPTAN", "FPATAN", "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP", "FPREM", "FYL2XP1", "FSQRT", "ESC_D9", "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", }; #endif /* DEBUG */ /* opcode=0xd9 */ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset = 0; u8 stkelem = 0; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); } else { DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); } #endif switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); break; case 3: /* register to register */ stkelem = (u8)rl; if (rh < 4) { DECODE_PRINTF2("ST(%d)\n", stkelem); } else { DECODE_PRINTF("\n"); } break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: switch (rh) { case 0: x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); break; case 1: x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); break; case 2: switch (rl) { case 0: x86emu_fpu_R_nop(); break; default: x86emu_fpu_illegal(); break; } case 3: x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); break; case 4: switch (rl) { case 0: x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); break; case 1: x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); break; case 4: x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); break; case 5: x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); break; default: /* 2,3,6,7 */ x86emu_fpu_illegal(); break; } break; case 5: switch (rl) { case 0: x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); break; case 1: x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); break; case 2: x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); break; case 3: x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); break; case 4: x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); break; case 5: x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); break; case 6: x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); break; default: /* 7 */ x86emu_fpu_illegal(); break; } break; case 6: switch (rl) { case 0: x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); break; case 1: x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); break; case 2: x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); break; case 3: x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); break; case 4: x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); break; case 5: x86emu_fpu_illegal(); break; case 6: x86emu_fpu_R_decstp(); break; case 7: x86emu_fpu_R_incstp(); break; } break; case 7: switch (rl) { case 0: x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); break; case 1: x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); break; case 2: x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); break; case 3: x86emu_fpu_illegal(); break; case 4: x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); break; case 5: x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); break; case 6: case 7: default: x86emu_fpu_illegal(); break; } break; default: switch (rh) { case 0: x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); break; case 1: x86emu_fpu_illegal(); break; case 2: x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); break; case 3: x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); break; case 4: x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); break; case 5: x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); break; case 6: x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); break; case 7: x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); break; } } } #else (void)destoffset; (void)stkelem; #endif /* X86EMU_FPU_PRESENT */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } #ifdef DEBUG char *x86emu_fpu_op_da_tab[] = { "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", "FICOMP\tDWORD PTR ", "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", "FIDIVR\tDWORD PTR ", "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", "FICOMP\tDWORD PTR ", "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", "FIDIVR\tDWORD PTR ", "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", "FICOMP\tDWORD PTR ", "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", "FIDIVR\tDWORD PTR ", "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", }; #endif /* DEBUG */ /* opcode=0xda */ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset = 0; u8 stkelem = 0; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); break; case 3: /* register to register */ stkelem = (u8)rl; DECODE_PRINTF2("\tST(%d),ST\n", stkelem); break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: x86emu_fpu_illegal(); break; default: switch (rh) { case 0: x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); break; case 1: x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); break; case 2: x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); break; case 3: x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); break; case 4: x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); break; case 5: x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); break; case 6: x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); break; case 7: x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); break; } } #else (void)destoffset; (void)stkelem; #endif DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } #ifdef DEBUG char *x86emu_fpu_op_db_tab[] = { "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", }; #endif /* DEBUG */ /* opcode=0xdb */ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset = 0; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); } else if (rh == 4) { /* === 11 10 0 nnn */ switch (rl) { case 0: DECODE_PRINTF("FENI\n"); break; case 1: DECODE_PRINTF("FDISI\n"); break; case 2: DECODE_PRINTF("FCLEX\n"); break; case 3: DECODE_PRINTF("FINIT\n"); break; } } else { DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); } #endif /* DEBUG */ switch (mod) { case 0: destoffset = decode_rm00_address(rl); break; case 1: destoffset = decode_rm01_address(rl); break; case 2: destoffset = decode_rm10_address(rl); break; case 3: /* register to register */ break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: switch (rh) { case 4: switch (rl) { case 0: x86emu_fpu_R_feni(); break; case 1: x86emu_fpu_R_fdisi(); break; case 2: x86emu_fpu_R_fclex(); break; case 3: x86emu_fpu_R_finit(); break; default: x86emu_fpu_illegal(); break; } break; default: x86emu_fpu_illegal(); break; } break; default: switch (rh) { case 0: x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); break; case 1: x86emu_fpu_illegal(); break; case 2: x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); break; case 3: x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); break; case 4: x86emu_fpu_illegal(); break; case 5: x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); break; case 6: x86emu_fpu_illegal(); break; case 7: x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); break; } } #else (void)destoffset; #endif DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } #ifdef DEBUG char *x86emu_fpu_op_dc_tab[] = { "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", "FCOMP\tQWORD PTR ", "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", "FDIVR\tQWORD PTR ", "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", "FCOMP\tQWORD PTR ", "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", "FDIVR\tQWORD PTR ", "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", "FCOMP\tQWORD PTR ", "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", "FDIVR\tQWORD PTR ", "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", }; #endif /* DEBUG */ /* opcode=0xdc */ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset = 0; u8 stkelem = 0; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); break; case 3: /* register to register */ stkelem = (u8)rl; DECODE_PRINTF2("\tST(%d),ST\n", stkelem); break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: switch (rh) { case 0: x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); break; case 1: x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); break; case 2: x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); break; case 3: x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); break; case 4: x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); break; case 5: x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); break; case 6: x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); break; case 7: x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); break; } break; default: switch (rh) { case 0: x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); break; case 1: x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); break; case 2: x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); break; case 3: x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); break; case 4: x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); break; case 5: x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); break; case 6: x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); break; case 7: x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); break; } } #else (void)destoffset; (void)stkelem; #endif DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } #ifdef DEBUG static char *x86emu_fpu_op_dd_tab[] = { "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", }; #endif /* DEBUG */ /* opcode=0xdd */ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset = 0; u8 stkelem = 0; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); break; case 3: /* register to register */ stkelem = (u8)rl; DECODE_PRINTF2("\tST(%d),ST\n", stkelem); break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: switch (rh) { case 0: x86emu_fpu_R_ffree(stkelem); break; case 1: x86emu_fpu_R_fxch(stkelem); break; case 2: x86emu_fpu_R_fst(stkelem); /* register version */ break; case 3: x86emu_fpu_R_fstp(stkelem); /* register version */ break; default: x86emu_fpu_illegal(); break; } break; default: switch (rh) { case 0: x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); break; case 1: x86emu_fpu_illegal(); break; case 2: x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); break; case 3: x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); break; case 4: x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); break; case 5: x86emu_fpu_illegal(); break; case 6: x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); break; case 7: x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); break; } } #else (void)destoffset; (void)stkelem; #endif DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } #ifdef DEBUG static char *x86emu_fpu_op_de_tab[] = { "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", "FICOMP\tWORD PTR ", "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", "FIDIVR\tWORD PTR ", "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", "FICOMP\tWORD PTR ", "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", "FIDIVR\tWORD PTR ", "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", "FICOMP\tWORD PTR ", "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", "FIDIVR\tWORD PTR ", "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t", "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", }; #endif /* DEBUG */ /* opcode=0xde */ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset = 0; u8 stkelem = 0; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); break; case 3: /* register to register */ stkelem = (u8)rl; DECODE_PRINTF2("\tST(%d),ST\n", stkelem); break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: switch (rh) { case 0: x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); break; case 1: x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); break; case 2: x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); break; case 3: if (stkelem == 1) x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); else x86emu_fpu_illegal(); break; case 4: x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); break; case 5: x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); break; case 6: x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); break; case 7: x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); break; } break; default: switch (rh) { case 0: x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); break; case 1: x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); break; case 2: x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); break; case 3: x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); break; case 4: x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); break; case 5: x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); break; case 6: x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); break; case 7: x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); break; } } #else (void)destoffset; (void)stkelem; #endif DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } #ifdef DEBUG static char *x86emu_fpu_op_df_tab[] = { /* mod == 00 */ "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", "FISTP\tQWORD PTR ", /* mod == 01 */ "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", "FISTP\tQWORD PTR ", /* mod == 10 */ "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", "FISTP\tQWORD PTR ", /* mod == 11 */ "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," }; #endif /* DEBUG */ /* opcode=0xdf */ void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset = 0; u8 stkelem = 0; START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); switch (mod) { case 0: destoffset = decode_rm00_address(rl); DECODE_PRINTF("\n"); break; case 1: destoffset = decode_rm01_address(rl); DECODE_PRINTF("\n"); break; case 2: destoffset = decode_rm10_address(rl); DECODE_PRINTF("\n"); break; case 3: /* register to register */ stkelem = (u8)rl; DECODE_PRINTF2("\tST(%d)\n", stkelem); break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: switch (rh) { case 0: x86emu_fpu_R_ffree(stkelem); break; case 1: x86emu_fpu_R_fxch(stkelem); break; case 2: x86emu_fpu_R_fst(stkelem); /* register version */ break; case 3: x86emu_fpu_R_fstp(stkelem); /* register version */ break; default: x86emu_fpu_illegal(); break; } break; default: switch (rh) { case 0: x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); break; case 1: x86emu_fpu_illegal(); break; case 2: x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); break; case 3: x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); break; case 4: x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); break; case 5: x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); break; case 6: x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); break; case 7: x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); break; } } #else (void)destoffset; (void)stkelem; #endif DECODE_CLEAR_SEGOVR(); END_OF_INSTR_NO_TRACE(); } xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/prim_ops.c0000644000000000000000000023372510410136571016760 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: This file contains the code to implement the primitive * machine operations used by the emulation code in ops.c * * Carry Chain Calculation * * This represents a somewhat expensive calculation which is * apparently required to emulate the setting of the OF and AF flag. * The latter is not so important, but the former is. The overflow * flag is the XOR of the top two bits of the carry chain for an * addition (similar for subtraction). Since we do not want to * simulate the addition in a bitwise manner, we try to calculate the * carry chain given the two operands and the result. * * So, given the following table, which represents the addition of two * bits, we can derive a formula for the carry chain. * * a b cin r cout * 0 0 0 0 0 * 0 0 1 1 0 * 0 1 0 1 0 * 0 1 1 0 1 * 1 0 0 1 0 * 1 0 1 0 1 * 1 1 0 0 1 * 1 1 1 1 1 * * Construction of table for cout: * * ab * r \ 00 01 11 10 * |------------------ * 0 | 0 1 1 1 * 1 | 0 0 1 0 * * By inspection, one gets: cc = ab + r'(a + b) * * That represents alot of operations, but NO CHOICE.... * * Borrow Chain Calculation. * * The following table represents the subtraction of two bits, from * which we can derive a formula for the borrow chain. * * a b bin r bout * 0 0 0 0 0 * 0 0 1 1 1 * 0 1 0 1 1 * 0 1 1 0 1 * 1 0 0 1 0 * 1 0 1 0 0 * 1 1 0 0 0 * 1 1 1 1 1 * * Construction of table for cout: * * ab * r \ 00 01 11 10 * |------------------ * 0 | 0 1 0 0 * 1 | 1 1 1 0 * * By inspection, one gets: bc = a'b + r(a' + b) * ****************************************************************************/ #define PRIM_OPS_NO_REDEFINE_ASM #include "x86emu/x86emui.h" /*------------------------- Global Variables ------------------------------*/ #ifndef __HAVE_INLINE_ASSEMBLER__ static u32 x86emu_parity_tab[8] = { 0x96696996, 0x69969669, 0x69969669, 0x96696996, 0x69969669, 0x96696996, 0x96696996, 0x69969669, }; #endif #define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) #define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) /*----------------------------- Implementation ----------------------------*/ #ifndef __HAVE_INLINE_ASSEMBLER__ /**************************************************************************** REMARKS: Implements the AAA instruction and side effects. ****************************************************************************/ u16 aaa_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { d += 0x6; d += 0x100; SET_FLAG(F_AF); SET_FLAG(F_CF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); CLEAR_FLAG(F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); return res; } /**************************************************************************** REMARKS: Implements the AAA instruction and side effects. ****************************************************************************/ u16 aas_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { d -= 0x6; d -= 0x100; SET_FLAG(F_AF); SET_FLAG(F_CF); } else { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); CLEAR_FLAG(F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); return res; } /**************************************************************************** REMARKS: Implements the AAD instruction and side effects. ****************************************************************************/ u16 aad_word(u16 d) { u16 l; u8 hb, lb; hb = (u8)((d >> 8) & 0xff); lb = (u8)((d & 0xff)); l = (u16)((lb + 10 * hb) & 0xFF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(l & 0x80, F_SF); CONDITIONAL_SET_FLAG(l == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); return l; } /**************************************************************************** REMARKS: Implements the AAM instruction and side effects. ****************************************************************************/ u16 aam_word(u8 d) { u16 h, l; h = (u16)(d / 10); l = (u16)(d % 10); l |= (u16)(h << 8); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(l & 0x80, F_SF); CONDITIONAL_SET_FLAG(l == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); return l; } /**************************************************************************** REMARKS: Implements the ADC instruction and side effects. ****************************************************************************/ u8 adc_byte(u8 d, u8 s) { register u32 res; /* all operands in native machine order */ register u32 cc; if (ACCESS_FLAG(F_CF)) res = 1 + d + s; else res = d + s; CONDITIONAL_SET_FLAG(res & 0x100, F_CF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (s & d) | ((~res) & (s | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return (u8)res; } /**************************************************************************** REMARKS: Implements the ADC instruction and side effects. ****************************************************************************/ u16 adc_word(u16 d, u16 s) { register u32 res; /* all operands in native machine order */ register u32 cc; if (ACCESS_FLAG(F_CF)) res = 1 + d + s; else res = d + s; CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (s & d) | ((~res) & (s | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return (u16)res; } /**************************************************************************** REMARKS: Implements the ADC instruction and side effects. ****************************************************************************/ u32 adc_long(u32 d, u32 s) { register u32 lo; /* all operands in native machine order */ register u32 hi; register u32 res; register u32 cc; if (ACCESS_FLAG(F_CF)) { lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); res = 1 + d + s; } else { lo = (d & 0xFFFF) + (s & 0xFFFF); res = d + s; } hi = (lo >> 16) + (d >> 16) + (s >> 16); CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (s & d) | ((~res) & (s | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the ADD instruction and side effects. ****************************************************************************/ u8 add_byte(u8 d, u8 s) { register u32 res; /* all operands in native machine order */ register u32 cc; res = d + s; CONDITIONAL_SET_FLAG(res & 0x100, F_CF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (s & d) | ((~res) & (s | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return (u8)res; } /**************************************************************************** REMARKS: Implements the ADD instruction and side effects. ****************************************************************************/ u16 add_word(u16 d, u16 s) { register u32 res; /* all operands in native machine order */ register u32 cc; res = d + s; CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (s & d) | ((~res) & (s | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return (u16)res; } /**************************************************************************** REMARKS: Implements the ADD instruction and side effects. ****************************************************************************/ u32 add_long(u32 d, u32 s) { register u32 lo; /* all operands in native machine order */ register u32 hi; register u32 res; register u32 cc; lo = (d & 0xFFFF) + (s & 0xFFFF); res = d + s; hi = (lo >> 16) + (d >> 16) + (s >> 16); CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (s & d) | ((~res) & (s | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the AND instruction and side effects. ****************************************************************************/ u8 and_byte(u8 d, u8 s) { register u8 res; /* all operands in native machine order */ res = d & s; /* set the flags */ CLEAR_FLAG(F_OF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res), F_PF); return res; } /**************************************************************************** REMARKS: Implements the AND instruction and side effects. ****************************************************************************/ u16 and_word(u16 d, u16 s) { register u16 res; /* all operands in native machine order */ res = d & s; /* set the flags */ CLEAR_FLAG(F_OF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); return res; } /**************************************************************************** REMARKS: Implements the AND instruction and side effects. ****************************************************************************/ u32 and_long(u32 d, u32 s) { register u32 res; /* all operands in native machine order */ res = d & s; /* set the flags */ CLEAR_FLAG(F_OF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); return res; } /**************************************************************************** REMARKS: Implements the CMP instruction and side effects. ****************************************************************************/ u8 cmp_byte(u8 d, u8 s) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - s; CLEAR_FLAG(F_CF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return d; } /**************************************************************************** REMARKS: Implements the CMP instruction and side effects. ****************************************************************************/ u16 cmp_word(u16 d, u16 s) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - s; CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return d; } /**************************************************************************** REMARKS: Implements the CMP instruction and side effects. ****************************************************************************/ u32 cmp_long(u32 d, u32 s) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - s; CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return d; } /**************************************************************************** REMARKS: Implements the DAA instruction and side effects. ****************************************************************************/ u8 daa_byte(u8 d) { u32 res = d; if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { res += 6; SET_FLAG(F_AF); } if (res > 0x9F || ACCESS_FLAG(F_CF)) { res += 0x60; SET_FLAG(F_CF); } CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); return (u8)res; } /**************************************************************************** REMARKS: Implements the DAS instruction and side effects. ****************************************************************************/ u8 das_byte(u8 d) { if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { d -= 6; SET_FLAG(F_AF); } if (d > 0x9F || ACCESS_FLAG(F_CF)) { d -= 0x60; SET_FLAG(F_CF); } CONDITIONAL_SET_FLAG(d & 0x80, F_SF); CONDITIONAL_SET_FLAG(d == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); return d; } /**************************************************************************** REMARKS: Implements the DEC instruction and side effects. ****************************************************************************/ u8 dec_byte(u8 d) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - 1; CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ /* based on sub_byte, uses s==1. */ bc = (res & (~d | 1)) | (~d & 1); /* carry flag unchanged */ CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return (u8)res; } /**************************************************************************** REMARKS: Implements the DEC instruction and side effects. ****************************************************************************/ u16 dec_word(u16 d) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - 1; CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ /* based on the sub_byte routine, with s==1 */ bc = (res & (~d | 1)) | (~d & 1); /* carry flag unchanged */ CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return (u16)res; } /**************************************************************************** REMARKS: Implements the DEC instruction and side effects. ****************************************************************************/ u32 dec_long(u32 d) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - 1; CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | 1)) | (~d & 1); /* carry flag unchanged */ CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the INC instruction and side effects. ****************************************************************************/ u8 inc_byte(u8 d) { register u32 res; /* all operands in native machine order */ register u32 cc; res = d + 1; CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = ((1 & d) | (~res)) & (1 | d); CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return (u8)res; } /**************************************************************************** REMARKS: Implements the INC instruction and side effects. ****************************************************************************/ u16 inc_word(u16 d) { register u32 res; /* all operands in native machine order */ register u32 cc; res = d + 1; CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (1 & d) | ((~res) & (1 | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return (u16)res; } /**************************************************************************** REMARKS: Implements the INC instruction and side effects. ****************************************************************************/ u32 inc_long(u32 d) { register u32 res; /* all operands in native machine order */ register u32 cc; res = d + 1; CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the carry chain SEE NOTE AT TOP. */ cc = (1 & d) | ((~res) & (1 | d)); CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the OR instruction and side effects. ****************************************************************************/ u8 or_byte(u8 d, u8 s) { register u8 res; /* all operands in native machine order */ res = d | s; CLEAR_FLAG(F_OF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res), F_PF); return res; } /**************************************************************************** REMARKS: Implements the OR instruction and side effects. ****************************************************************************/ u16 or_word(u16 d, u16 s) { register u16 res; /* all operands in native machine order */ res = d | s; /* set the carry flag to be bit 8 */ CLEAR_FLAG(F_OF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); return res; } /**************************************************************************** REMARKS: Implements the OR instruction and side effects. ****************************************************************************/ u32 or_long(u32 d, u32 s) { register u32 res; /* all operands in native machine order */ res = d | s; /* set the carry flag to be bit 8 */ CLEAR_FLAG(F_OF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); return res; } /**************************************************************************** REMARKS: Implements the OR instruction and side effects. ****************************************************************************/ u8 neg_byte(u8 s) { register u8 res; register u8 bc; CONDITIONAL_SET_FLAG(s != 0, F_CF); res = (u8)-s; CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(PARITY(res), F_PF); /* calculate the borrow chain --- modified such that d=0. substitutiing d=0 into bc= res&(~d|s)|(~d&s); (the one used for sub) and simplifying, since ~d=0xff..., ~d|s == 0xffff..., and res&0xfff... == res. Similarly ~d&s == s. So the simplified result is: */ bc = res | s; CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the OR instruction and side effects. ****************************************************************************/ u16 neg_word(u16 s) { register u16 res; register u16 bc; CONDITIONAL_SET_FLAG(s != 0, F_CF); res = (u16)-s; CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain --- modified such that d=0. substitutiing d=0 into bc= res&(~d|s)|(~d&s); (the one used for sub) and simplifying, since ~d=0xff..., ~d|s == 0xffff..., and res&0xfff... == res. Similarly ~d&s == s. So the simplified result is: */ bc = res | s; CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the OR instruction and side effects. ****************************************************************************/ u32 neg_long(u32 s) { register u32 res; register u32 bc; CONDITIONAL_SET_FLAG(s != 0, F_CF); res = (u32)-s; CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain --- modified such that d=0. substitutiing d=0 into bc= res&(~d|s)|(~d&s); (the one used for sub) and simplifying, since ~d=0xff..., ~d|s == 0xffff..., and res&0xfff... == res. Similarly ~d&s == s. So the simplified result is: */ bc = res | s; CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the NOT instruction and side effects. ****************************************************************************/ u8 not_byte(u8 s) { return ~s; } /**************************************************************************** REMARKS: Implements the NOT instruction and side effects. ****************************************************************************/ u16 not_word(u16 s) { return ~s; } /**************************************************************************** REMARKS: Implements the NOT instruction and side effects. ****************************************************************************/ u32 not_long(u32 s) { return ~s; } /**************************************************************************** REMARKS: Implements the RCL instruction and side effects. ****************************************************************************/ u8 rcl_byte(u8 d, u8 s) { register unsigned int res, cnt, mask, cf; /* s is the rotate distance. It varies from 0 - 8. */ /* have CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 want to rotate through the carry by "s" bits. We could loop, but that's inefficient. So the width is 9, and we split into three parts: The new carry flag (was B_n) the stuff in B_n-1 .. B_0 the stuff in B_7 .. B_n+1 The new rotate is done mod 9, and given this, for a rotation of n bits (mod 9) the new carry flag is then located n bits from the MSB. The low part is then shifted up cnt bits, and the high part is or'd in. Using CAPS for new values, and lowercase for the original values, this can be expressed as: IF n > 0 1) CF <- b_(8-n) 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 3) B_(n-1) <- cf 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ res = d; if ((cnt = s % 9) != 0) { /* extract the new CARRY FLAG. */ /* CF <- b_(8-n) */ cf = (d >> (8 - cnt)) & 0x1; /* get the low stuff which rotated into the range B_7 .. B_cnt */ /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ /* note that the right hand side done by the mask */ res = (d << cnt) & 0xff; /* now the high stuff which rotated around into the positions B_cnt-2 .. B_0 */ /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ /* shift it downward, 7-(n-2) = 9-n positions. and mask off the result before or'ing in. */ mask = (1 << (cnt - 1)) - 1; res |= (d >> (9 - cnt)) & mask; /* if the carry flag was set, or it in. */ if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ /* B_(n-1) <- cf */ res |= 1 << (cnt - 1); } /* set the new carry flag, based on the variable "cf" */ CONDITIONAL_SET_FLAG(cf, F_CF); /* OVERFLOW is set *IFF* cnt==1, then it is the xor of CF and the most significant bit. Blecck. */ /* parenthesized this expression since it appears to be causing OF to be misset */ CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), F_OF); } return (u8)res; } /**************************************************************************** REMARKS: Implements the RCL instruction and side effects. ****************************************************************************/ u16 rcl_word(u16 d, u8 s) { register unsigned int res, cnt, mask, cf; res = d; if ((cnt = s % 17) != 0) { cf = (d >> (16 - cnt)) & 0x1; res = (d << cnt) & 0xffff; mask = (1 << (cnt - 1)) - 1; res |= (d >> (17 - cnt)) & mask; if (ACCESS_FLAG(F_CF)) { res |= 1 << (cnt - 1); } CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), F_OF); } return (u16)res; } /**************************************************************************** REMARKS: Implements the RCL instruction and side effects. ****************************************************************************/ u32 rcl_long(u32 d, u8 s) { register u32 res, cnt, mask, cf; res = d; if ((cnt = s % 33) != 0) { cf = (d >> (32 - cnt)) & 0x1; res = (d << cnt) & 0xffffffff; mask = (1 << (cnt - 1)) - 1; res |= (d >> (33 - cnt)) & mask; if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ res |= 1 << (cnt - 1); } CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), F_OF); } return res; } /**************************************************************************** REMARKS: Implements the RCR instruction and side effects. ****************************************************************************/ u8 rcr_byte(u8 d, u8 s) { u32 res, cnt; u32 mask, cf, ocf = 0; /* rotate right through carry */ /* s is the rotate distance. It varies from 0 - 8. d is the byte object rotated. have CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 The new rotate is done mod 9, and given this, for a rotation of n bits (mod 9) the new carry flag is then located n bits from the LSB. The low part is then shifted up cnt bits, and the high part is or'd in. Using CAPS for new values, and lowercase for the original values, this can be expressed as: IF n > 0 1) CF <- b_(n-1) 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) 3) B_(8-n) <- cf 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ res = d; if ((cnt = s % 9) != 0) { /* extract the new CARRY FLAG. */ /* CF <- b_(n-1) */ if (cnt == 1) { cf = d & 0x1; /* note hackery here. Access_flag(..) evaluates to either 0 if flag not set non-zero if flag is set. doing access_flag(..) != 0 casts that into either 0..1 in any representation of the flags register (i.e. packed bit array or unpacked.) */ ocf = ACCESS_FLAG(F_CF) != 0; } else cf = (d >> (cnt - 1)) & 0x1; /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ /* note that the right hand side done by the mask This is effectively done by shifting the object to the right. The result must be masked, in case the object came in and was treated as a negative number. Needed??? */ mask = (1 << (8 - cnt)) - 1; res = (d >> cnt) & mask; /* now the high stuff which rotated around into the positions B_cnt-2 .. B_0 */ /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ /* shift it downward, 7-(n-2) = 9-n positions. and mask off the result before or'ing in. */ res |= (d << (9 - cnt)); /* if the carry flag was set, or it in. */ if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ /* B_(8-n) <- cf */ res |= 1 << (8 - cnt); } /* set the new carry flag, based on the variable "cf" */ CONDITIONAL_SET_FLAG(cf, F_CF); /* OVERFLOW is set *IFF* cnt==1, then it is the xor of CF and the most significant bit. Blecck. */ /* parenthesized... */ if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), F_OF); } } return (u8)res; } /**************************************************************************** REMARKS: Implements the RCR instruction and side effects. ****************************************************************************/ u16 rcr_word(u16 d, u8 s) { u32 res, cnt; u32 mask, cf, ocf = 0; /* rotate right through carry */ res = d; if ((cnt = s % 17) != 0) { if (cnt == 1) { cf = d & 0x1; ocf = ACCESS_FLAG(F_CF) != 0; } else cf = (d >> (cnt - 1)) & 0x1; mask = (1 << (16 - cnt)) - 1; res = (d >> cnt) & mask; res |= (d << (17 - cnt)); if (ACCESS_FLAG(F_CF)) { res |= 1 << (16 - cnt); } CONDITIONAL_SET_FLAG(cf, F_CF); if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), F_OF); } } return (u16)res; } /**************************************************************************** REMARKS: Implements the RCR instruction and side effects. ****************************************************************************/ u32 rcr_long(u32 d, u8 s) { u32 res, cnt; u32 mask, cf, ocf = 0; /* rotate right through carry */ res = d; if ((cnt = s % 33) != 0) { if (cnt == 1) { cf = d & 0x1; ocf = ACCESS_FLAG(F_CF) != 0; } else cf = (d >> (cnt - 1)) & 0x1; mask = (1 << (32 - cnt)) - 1; res = (d >> cnt) & mask; if (cnt != 1) res |= (d << (33 - cnt)); if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ res |= 1 << (32 - cnt); } CONDITIONAL_SET_FLAG(cf, F_CF); if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), F_OF); } } return res; } /**************************************************************************** REMARKS: Implements the ROL instruction and side effects. ****************************************************************************/ u8 rol_byte(u8 d, u8 s) { register unsigned int res, cnt, mask; /* rotate left */ /* s is the rotate distance. It varies from 0 - 8. d is the byte object rotated. have CF B_7 ... B_0 The new rotate is done mod 8. Much simpler than the "rcl" or "rcr" operations. IF n > 0 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ res = d; if ((cnt = s % 8) != 0) { /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ res = (d << cnt); /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ mask = (1 << cnt) - 1; res |= (d >> (8 - cnt)) & mask; /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x1, F_CF); /* OVERFLOW is set *IFF* s==1, then it is the xor of CF and the most significant bit. Blecck. */ CONDITIONAL_SET_FLAG(s == 1 && XOR2((res & 0x1) + ((res >> 6) & 0x2)), F_OF); } if (s != 0) { /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u8)res; } /**************************************************************************** REMARKS: Implements the ROL instruction and side effects. ****************************************************************************/ u16 rol_word(u16 d, u8 s) { register unsigned int res, cnt, mask; res = d; if ((cnt = s % 16) != 0) { res = (d << cnt); mask = (1 << cnt) - 1; res |= (d >> (16 - cnt)) & mask; CONDITIONAL_SET_FLAG(res & 0x1, F_CF); CONDITIONAL_SET_FLAG(s == 1 && XOR2((res & 0x1) + ((res >> 14) & 0x2)), F_OF); } if (s != 0) { /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u16)res; } /**************************************************************************** REMARKS: Implements the ROL instruction and side effects. ****************************************************************************/ u32 rol_long(u32 d, u8 s) { register u32 res, cnt, mask; res = d; if ((cnt = s % 32) != 0) { res = (d << cnt); mask = (1 << cnt) - 1; res |= (d >> (32 - cnt)) & mask; CONDITIONAL_SET_FLAG(res & 0x1, F_CF); CONDITIONAL_SET_FLAG(s == 1 && XOR2((res & 0x1) + ((res >> 30) & 0x2)), F_OF); } if (s != 0) { /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return res; } /**************************************************************************** REMARKS: Implements the ROR instruction and side effects. ****************************************************************************/ u8 ror_byte(u8 d, u8 s) { register unsigned int res, cnt, mask; /* rotate right */ /* s is the rotate distance. It varies from 0 - 8. d is the byte object rotated. have B_7 ... B_0 The rotate is done mod 8. IF n > 0 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ res = d; if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ res = (d << (8 - cnt)); /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ mask = (1 << (8 - cnt)) - 1; res |= (d >> (cnt)) & mask; /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x80, F_CF); /* OVERFLOW is set *IFF* s==1, then it is the xor of the two most significant bits. Blecck. */ CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); } else if (s != 0) { /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x80, F_CF); } return (u8)res; } /**************************************************************************** REMARKS: Implements the ROR instruction and side effects. ****************************************************************************/ u16 ror_word(u16 d, u8 s) { register unsigned int res, cnt, mask; res = d; if ((cnt = s % 16) != 0) { res = (d << (16 - cnt)); mask = (1 << (16 - cnt)) - 1; res |= (d >> (cnt)) & mask; CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); } else if (s != 0) { /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); } return (u16)res; } /**************************************************************************** REMARKS: Implements the ROR instruction and side effects. ****************************************************************************/ u32 ror_long(u32 d, u8 s) { register u32 res, cnt, mask; res = d; if ((cnt = s % 32) != 0) { res = (d << (32 - cnt)); mask = (1 << (32 - cnt)) - 1; res |= (d >> (cnt)) & mask; CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); } else if (s != 0) { /* set the new carry flag, Note that it is the low order bit of the result!!! */ CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); } return res; } /**************************************************************************** REMARKS: Implements the SHL instruction and side effects. ****************************************************************************/ u8 shl_byte(u8 d, u8 s) { unsigned int cnt, res, cf; if (s < 8) { cnt = s % 8; /* last bit shifted out goes into carry flag */ if (cnt > 0) { res = d << cnt; cf = d & (1 << (8 - cnt)); CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = (u8) d; } if (cnt == 1) { /* Needs simplification. */ CONDITIONAL_SET_FLAG( (((res & 0x80) == 0x80) ^ (ACCESS_FLAG(F_CF) != 0)), /* was (M.x86.R_FLG&F_CF)==F_CF)), */ F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); CLEAR_FLAG(F_OF); CLEAR_FLAG(F_SF); SET_FLAG(F_PF); SET_FLAG(F_ZF); } return (u8)res; } /**************************************************************************** REMARKS: Implements the SHL instruction and side effects. ****************************************************************************/ u16 shl_word(u16 d, u8 s) { unsigned int cnt, res, cf; if (s < 16) { cnt = s % 16; if (cnt > 0) { res = d << cnt; cf = d & (1 << (16 - cnt)); CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = (u16) d; } if (cnt == 1) { CONDITIONAL_SET_FLAG( (((res & 0x8000) == 0x8000) ^ (ACCESS_FLAG(F_CF) != 0)), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); CLEAR_FLAG(F_OF); CLEAR_FLAG(F_SF); SET_FLAG(F_PF); SET_FLAG(F_ZF); } return (u16)res; } /**************************************************************************** REMARKS: Implements the SHL instruction and side effects. ****************************************************************************/ u32 shl_long(u32 d, u8 s) { unsigned int cnt, res, cf; if (s < 32) { cnt = s % 32; if (cnt > 0) { res = d << cnt; cf = d & (1 << (32 - cnt)); CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = d; } if (cnt == 1) { CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ (ACCESS_FLAG(F_CF) != 0)), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); CLEAR_FLAG(F_OF); CLEAR_FLAG(F_SF); SET_FLAG(F_PF); SET_FLAG(F_ZF); } return res; } /**************************************************************************** REMARKS: Implements the SHR instruction and side effects. ****************************************************************************/ u8 shr_byte(u8 d, u8 s) { unsigned int cnt, res, cf; if (s < 8) { cnt = s % 8; if (cnt > 0) { cf = d & (1 << (cnt - 1)); res = d >> cnt; CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = (u8) d; } if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); CLEAR_FLAG(F_OF); CLEAR_FLAG(F_SF); SET_FLAG(F_PF); SET_FLAG(F_ZF); } return (u8)res; } /**************************************************************************** REMARKS: Implements the SHR instruction and side effects. ****************************************************************************/ u16 shr_word(u16 d, u8 s) { unsigned int cnt, res, cf; if (s < 16) { cnt = s % 16; if (cnt > 0) { cf = d & (1 << (cnt - 1)); res = d >> cnt; CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = d; } if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); SET_FLAG(F_ZF); CLEAR_FLAG(F_SF); CLEAR_FLAG(F_PF); } return (u16)res; } /**************************************************************************** REMARKS: Implements the SHR instruction and side effects. ****************************************************************************/ u32 shr_long(u32 d, u8 s) { unsigned int cnt, res, cf; if (s < 32) { cnt = s % 32; if (cnt > 0) { cf = d & (1 << (cnt - 1)); res = d >> cnt; CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = d; } if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); SET_FLAG(F_ZF); CLEAR_FLAG(F_SF); CLEAR_FLAG(F_PF); } return res; } /**************************************************************************** REMARKS: Implements the SAR instruction and side effects. ****************************************************************************/ u8 sar_byte(u8 d, u8 s) { unsigned int cnt, res, cf, mask, sf; res = d; sf = d & 0x80; cnt = s % 8; if (cnt > 0 && cnt < 8) { mask = (1 << (8 - cnt)) - 1; cf = d & (1 << (cnt - 1)); res = (d >> cnt) & mask; CONDITIONAL_SET_FLAG(cf, F_CF); if (sf) { res |= ~mask; } CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); } else if (cnt >= 8) { if (sf) { res = 0xff; SET_FLAG(F_CF); CLEAR_FLAG(F_ZF); SET_FLAG(F_SF); SET_FLAG(F_PF); } else { res = 0; CLEAR_FLAG(F_CF); SET_FLAG(F_ZF); CLEAR_FLAG(F_SF); CLEAR_FLAG(F_PF); } } return (u8)res; } /**************************************************************************** REMARKS: Implements the SAR instruction and side effects. ****************************************************************************/ u16 sar_word(u16 d, u8 s) { unsigned int cnt, res, cf, mask, sf; sf = d & 0x8000; cnt = s % 16; res = d; if (cnt > 0 && cnt < 16) { mask = (1 << (16 - cnt)) - 1; cf = d & (1 << (cnt - 1)); res = (d >> cnt) & mask; CONDITIONAL_SET_FLAG(cf, F_CF); if (sf) { res |= ~mask; } CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else if (cnt >= 16) { if (sf) { res = 0xffff; SET_FLAG(F_CF); CLEAR_FLAG(F_ZF); SET_FLAG(F_SF); SET_FLAG(F_PF); } else { res = 0; CLEAR_FLAG(F_CF); SET_FLAG(F_ZF); CLEAR_FLAG(F_SF); CLEAR_FLAG(F_PF); } } return (u16)res; } /**************************************************************************** REMARKS: Implements the SAR instruction and side effects. ****************************************************************************/ u32 sar_long(u32 d, u8 s) { u32 cnt, res, cf, mask, sf; sf = d & 0x80000000; cnt = s % 32; res = d; if (cnt > 0 && cnt < 32) { mask = (1 << (32 - cnt)) - 1; cf = d & (1 << (cnt - 1)); res = (d >> cnt) & mask; CONDITIONAL_SET_FLAG(cf, F_CF); if (sf) { res |= ~mask; } CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else if (cnt >= 32) { if (sf) { res = 0xffffffff; SET_FLAG(F_CF); CLEAR_FLAG(F_ZF); SET_FLAG(F_SF); SET_FLAG(F_PF); } else { res = 0; CLEAR_FLAG(F_CF); SET_FLAG(F_ZF); CLEAR_FLAG(F_SF); CLEAR_FLAG(F_PF); } } return res; } /**************************************************************************** REMARKS: Implements the SHLD instruction and side effects. ****************************************************************************/ u16 shld_word (u16 d, u16 fill, u8 s) { unsigned int cnt, res, cf; if (s < 16) { cnt = s % 16; if (cnt > 0) { res = (d << cnt) | (fill >> (16-cnt)); cf = d & (1 << (16 - cnt)); CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = d; } if (cnt == 1) { CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ (ACCESS_FLAG(F_CF) != 0)), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); CLEAR_FLAG(F_OF); CLEAR_FLAG(F_SF); SET_FLAG(F_PF); SET_FLAG(F_ZF); } return (u16)res; } /**************************************************************************** REMARKS: Implements the SHLD instruction and side effects. ****************************************************************************/ u32 shld_long (u32 d, u32 fill, u8 s) { unsigned int cnt, res, cf; if (s < 32) { cnt = s % 32; if (cnt > 0) { res = (d << cnt) | (fill >> (32-cnt)); cf = d & (1 << (32 - cnt)); CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = d; } if (cnt == 1) { CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ (ACCESS_FLAG(F_CF) != 0)), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); CLEAR_FLAG(F_OF); CLEAR_FLAG(F_SF); SET_FLAG(F_PF); SET_FLAG(F_ZF); } return res; } /**************************************************************************** REMARKS: Implements the SHRD instruction and side effects. ****************************************************************************/ u16 shrd_word (u16 d, u16 fill, u8 s) { unsigned int cnt, res, cf; if (s < 16) { cnt = s % 16; if (cnt > 0) { cf = d & (1 << (cnt - 1)); res = (d >> cnt) | (fill << (16 - cnt)); CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = d; } if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); SET_FLAG(F_ZF); CLEAR_FLAG(F_SF); CLEAR_FLAG(F_PF); } return (u16)res; } /**************************************************************************** REMARKS: Implements the SHRD instruction and side effects. ****************************************************************************/ u32 shrd_long (u32 d, u32 fill, u8 s) { unsigned int cnt, res, cf; if (s < 32) { cnt = s % 32; if (cnt > 0) { cf = d & (1 << (cnt - 1)); res = (d >> cnt) | (fill << (32 - cnt)); CONDITIONAL_SET_FLAG(cf, F_CF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); } else { res = d; } if (cnt == 1) { CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); } else { CLEAR_FLAG(F_OF); } } else { res = 0; CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); SET_FLAG(F_ZF); CLEAR_FLAG(F_SF); CLEAR_FLAG(F_PF); } return res; } /**************************************************************************** REMARKS: Implements the SBB instruction and side effects. ****************************************************************************/ u8 sbb_byte(u8 d, u8 s) { register u32 res; /* all operands in native machine order */ register u32 bc; if (ACCESS_FLAG(F_CF)) res = d - s - 1; else res = d - s; CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return (u8)res; } /**************************************************************************** REMARKS: Implements the SBB instruction and side effects. ****************************************************************************/ u16 sbb_word(u16 d, u16 s) { register u32 res; /* all operands in native machine order */ register u32 bc; if (ACCESS_FLAG(F_CF)) res = d - s - 1; else res = d - s; CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return (u16)res; } /**************************************************************************** REMARKS: Implements the SBB instruction and side effects. ****************************************************************************/ u32 sbb_long(u32 d, u32 s) { register u32 res; /* all operands in native machine order */ register u32 bc; if (ACCESS_FLAG(F_CF)) res = d - s - 1; else res = d - s; CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the SUB instruction and side effects. ****************************************************************************/ u8 sub_byte(u8 d, u8 s) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - s; CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return (u8)res; } /**************************************************************************** REMARKS: Implements the SUB instruction and side effects. ****************************************************************************/ u16 sub_word(u16 d, u16 s) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - s; CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return (u16)res; } /**************************************************************************** REMARKS: Implements the SUB instruction and side effects. ****************************************************************************/ u32 sub_long(u32 d, u32 s) { register u32 res; /* all operands in native machine order */ register u32 bc; res = d - s; CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* calculate the borrow chain. See note at top */ bc = (res & (~d | s)) | (~d & s); CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); return res; } /**************************************************************************** REMARKS: Implements the TEST instruction and side effects. ****************************************************************************/ void test_byte(u8 d, u8 s) { register u32 res; /* all operands in native machine order */ res = d & s; CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* AF == dont care */ CLEAR_FLAG(F_CF); } /**************************************************************************** REMARKS: Implements the TEST instruction and side effects. ****************************************************************************/ void test_word(u16 d, u16 s) { register u32 res; /* all operands in native machine order */ res = d & s; CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* AF == dont care */ CLEAR_FLAG(F_CF); } /**************************************************************************** REMARKS: Implements the TEST instruction and side effects. ****************************************************************************/ void test_long(u32 d, u32 s) { register u32 res; /* all operands in native machine order */ res = d & s; CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); /* AF == dont care */ CLEAR_FLAG(F_CF); } /**************************************************************************** REMARKS: Implements the XOR instruction and side effects. ****************************************************************************/ u8 xor_byte(u8 d, u8 s) { register u8 res; /* all operands in native machine order */ res = d ^ s; CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(res & 0x80, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res), F_PF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); return res; } /**************************************************************************** REMARKS: Implements the XOR instruction and side effects. ****************************************************************************/ u16 xor_word(u16 d, u16 s) { register u16 res; /* all operands in native machine order */ res = d ^ s; CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); return res; } /**************************************************************************** REMARKS: Implements the XOR instruction and side effects. ****************************************************************************/ u32 xor_long(u32 d, u32 s) { register u32 res; /* all operands in native machine order */ res = d ^ s; CLEAR_FLAG(F_OF); CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); CONDITIONAL_SET_FLAG(res == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); return res; } /**************************************************************************** REMARKS: Implements the IMUL instruction and side effects. ****************************************************************************/ void imul_byte(u8 s) { s16 res = (s16)((s8)M.x86.R_AL * (s8)s); M.x86.R_AX = res; if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } else { SET_FLAG(F_CF); SET_FLAG(F_OF); } } /**************************************************************************** REMARKS: Implements the IMUL instruction and side effects. ****************************************************************************/ void imul_word(u16 s) { s32 res = (s16)M.x86.R_AX * (s16)s; M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) || ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } else { SET_FLAG(F_CF); SET_FLAG(F_OF); } } /**************************************************************************** REMARKS: Implements the IMUL instruction and side effects. ****************************************************************************/ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) { #ifdef __HAS_LONG_LONG__ s64 res = (s32)d * (s32)s; *res_lo = (u32)res; *res_hi = (u32)(res >> 32); #else u32 d_lo,d_hi,d_sign; u32 s_lo,s_hi,s_sign; u32 rlo_lo,rlo_hi,rhi_lo; if ((d_sign = d & 0x80000000) != 0) d = -d; d_lo = d & 0xFFFF; d_hi = d >> 16; if ((s_sign = s & 0x80000000) != 0) s = -s; s_lo = s & 0xFFFF; s_hi = s >> 16; rlo_lo = d_lo * s_lo; rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); rhi_lo = d_hi * s_hi + (rlo_hi >> 16); *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); *res_hi = rhi_lo; if (d_sign != s_sign) { d = ~*res_lo; s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); *res_lo = ~*res_lo+1; *res_hi = ~*res_hi+(s >> 16); } #endif } /**************************************************************************** REMARKS: Implements the IMUL instruction and side effects. ****************************************************************************/ void imul_long(u32 s) { imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) || ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } else { SET_FLAG(F_CF); SET_FLAG(F_OF); } } /**************************************************************************** REMARKS: Implements the MUL instruction and side effects. ****************************************************************************/ void mul_byte(u8 s) { u16 res = (u16)(M.x86.R_AL * s); M.x86.R_AX = res; if (M.x86.R_AH == 0) { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } else { SET_FLAG(F_CF); SET_FLAG(F_OF); } } /**************************************************************************** REMARKS: Implements the MUL instruction and side effects. ****************************************************************************/ void mul_word(u16 s) { u32 res = M.x86.R_AX * s; M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (M.x86.R_DX == 0) { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } else { SET_FLAG(F_CF); SET_FLAG(F_OF); } } /**************************************************************************** REMARKS: Implements the MUL instruction and side effects. ****************************************************************************/ void mul_long(u32 s) { #ifdef __HAS_LONG_LONG__ u64 res = (u32)M.x86.R_EAX * (u32)s; M.x86.R_EAX = (u32)res; M.x86.R_EDX = (u32)(res >> 32); #else u32 a,a_lo,a_hi; u32 s_lo,s_hi; u32 rlo_lo,rlo_hi,rhi_lo; a = M.x86.R_EAX; a_lo = a & 0xFFFF; a_hi = a >> 16; s_lo = s & 0xFFFF; s_hi = s >> 16; rlo_lo = a_lo * s_lo; rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); rhi_lo = a_hi * s_hi + (rlo_hi >> 16); M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); M.x86.R_EDX = rhi_lo; #endif if (M.x86.R_EDX == 0) { CLEAR_FLAG(F_CF); CLEAR_FLAG(F_OF); } else { SET_FLAG(F_CF); SET_FLAG(F_OF); } } /**************************************************************************** REMARKS: Implements the IDIV instruction and side effects. ****************************************************************************/ void idiv_byte(u8 s) { s32 dvd, div, mod; dvd = (s16)M.x86.R_AX; if (s == 0) { x86emu_intr_raise(0); return; } div = dvd / (s8)s; mod = dvd % (s8)s; if (abs(div) > 0x7f) { x86emu_intr_raise(0); return; } M.x86.R_AL = (s8) div; M.x86.R_AH = (s8) mod; } /**************************************************************************** REMARKS: Implements the IDIV instruction and side effects. ****************************************************************************/ void idiv_word(u16 s) { s32 dvd, div, mod; dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { x86emu_intr_raise(0); return; } div = dvd / (s16)s; mod = dvd % (s16)s; if (abs(div) > 0x7fff) { x86emu_intr_raise(0); return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); CONDITIONAL_SET_FLAG(div == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); M.x86.R_AX = (u16)div; M.x86.R_DX = (u16)mod; } /**************************************************************************** REMARKS: Implements the IDIV instruction and side effects. ****************************************************************************/ void idiv_long(u32 s) { #ifdef __HAS_LONG_LONG__ s64 dvd, div, mod; dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { x86emu_intr_raise(0); return; } div = dvd / (s32)s; mod = dvd % (s32)s; if (abs(div) > 0x7fffffff) { x86emu_intr_raise(0); return; } #else s32 div = 0, mod; s32 h_dvd = M.x86.R_EDX; u32 l_dvd = M.x86.R_EAX; u32 abs_s = s & 0x7FFFFFFF; u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; u32 h_s = abs_s >> 1; u32 l_s = abs_s << 31; int counter = 31; int carry; if (s == 0) { x86emu_intr_raise(0); return; } do { div <<= 1; carry = (l_dvd >= l_s) ? 0 : 1; if (abs_h_dvd < (h_s + carry)) { h_s >>= 1; l_s = abs_s << (--counter); continue; } else { abs_h_dvd -= (h_s + carry); l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) : (l_dvd - l_s); h_s >>= 1; l_s = abs_s << (--counter); div |= 1; continue; } } while (counter > -1); /* overflow */ if (abs_h_dvd || (l_dvd > abs_s)) { x86emu_intr_raise(0); return; } /* sign */ div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); mod = l_dvd; #endif CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CLEAR_FLAG(F_SF); SET_FLAG(F_ZF); CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); M.x86.R_EAX = (u32)div; M.x86.R_EDX = (u32)mod; } /**************************************************************************** REMARKS: Implements the DIV instruction and side effects. ****************************************************************************/ void div_byte(u8 s) { u32 dvd, div, mod; dvd = M.x86.R_AX; if (s == 0) { x86emu_intr_raise(0); return; } div = dvd / (u8)s; mod = dvd % (u8)s; if (abs(div) > 0xff) { x86emu_intr_raise(0); return; } M.x86.R_AL = (u8)div; M.x86.R_AH = (u8)mod; } /**************************************************************************** REMARKS: Implements the DIV instruction and side effects. ****************************************************************************/ void div_word(u16 s) { u32 dvd, div, mod; dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { x86emu_intr_raise(0); return; } div = dvd / (u16)s; mod = dvd % (u16)s; if (abs(div) > 0xffff) { x86emu_intr_raise(0); return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); CONDITIONAL_SET_FLAG(div == 0, F_ZF); CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); M.x86.R_AX = (u16)div; M.x86.R_DX = (u16)mod; } /**************************************************************************** REMARKS: Implements the DIV instruction and side effects. ****************************************************************************/ void div_long(u32 s) { #ifdef __HAS_LONG_LONG__ u64 dvd, div, mod; dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { x86emu_intr_raise(0); return; } div = dvd / (u32)s; mod = dvd % (u32)s; if (abs(div) > 0xffffffff) { x86emu_intr_raise(0); return; } #else s32 div = 0, mod; s32 h_dvd = M.x86.R_EDX; u32 l_dvd = M.x86.R_EAX; u32 h_s = s; u32 l_s = 0; int counter = 32; int carry; if (s == 0) { x86emu_intr_raise(0); return; } do { div <<= 1; carry = (l_dvd >= l_s) ? 0 : 1; if (h_dvd < (h_s + carry)) { h_s >>= 1; l_s = s << (--counter); continue; } else { h_dvd -= (h_s + carry); l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) : (l_dvd - l_s); h_s >>= 1; l_s = s << (--counter); div |= 1; continue; } } while (counter > -1); /* overflow */ if (h_dvd || (l_dvd > s)) { x86emu_intr_raise(0); return; } mod = l_dvd; #endif CLEAR_FLAG(F_CF); CLEAR_FLAG(F_AF); CLEAR_FLAG(F_SF); SET_FLAG(F_ZF); CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); M.x86.R_EAX = (u32)div; M.x86.R_EDX = (u32)mod; } #endif /* __HAVE_INLINE_ASSEMBLER__ */ /**************************************************************************** REMARKS: Implements the IN string instruction and side effects. ****************************************************************************/ void ins(int size) { int inc = size; if (ACCESS_FLAG(F_DF)) { inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* in until CX is ZERO. */ u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? M.x86.R_ECX : M.x86.R_CX); switch (size) { case 1: while (count--) { store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, (*sys_inb)(M.x86.R_DX)); M.x86.R_DI += inc; } break; case 2: while (count--) { store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (*sys_inw)(M.x86.R_DX)); M.x86.R_DI += inc; } break; case 4: while (count--) { store_data_long_abs(M.x86.R_ES, M.x86.R_DI, (*sys_inl)(M.x86.R_DX)); M.x86.R_DI += inc; break; } } M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ECX = 0; } M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { switch (size) { case 1: store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, (*sys_inb)(M.x86.R_DX)); break; case 2: store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (*sys_inw)(M.x86.R_DX)); break; case 4: store_data_long_abs(M.x86.R_ES, M.x86.R_DI, (*sys_inl)(M.x86.R_DX)); break; } M.x86.R_DI += inc; } } /**************************************************************************** REMARKS: Implements the OUT string instruction and side effects. ****************************************************************************/ void outs(int size) { int inc = size; if (ACCESS_FLAG(F_DF)) { inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { /* dont care whether REPE or REPNE */ /* out until CX is ZERO. */ u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? M.x86.R_ECX : M.x86.R_CX); switch (size) { case 1: while (count--) { (*sys_outb)(M.x86.R_DX, fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); M.x86.R_SI += inc; } break; case 2: while (count--) { (*sys_outw)(M.x86.R_DX, fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); M.x86.R_SI += inc; } break; case 4: while (count--) { (*sys_outl)(M.x86.R_DX, fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); M.x86.R_SI += inc; break; } } M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_PREFIX_DATA) { M.x86.R_ECX = 0; } M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { switch (size) { case 1: (*sys_outb)(M.x86.R_DX, fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); break; case 2: (*sys_outw)(M.x86.R_DX, fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); break; case 4: (*sys_outl)(M.x86.R_DX, fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); break; } M.x86.R_SI += inc; } } /**************************************************************************** PARAMETERS: addr - Address to fetch word from REMARKS: Fetches a word from emulator memory using an absolute address. ****************************************************************************/ u16 mem_access_word(int addr) { DB( if (CHECK_MEM_ACCESS()) x86emu_check_mem_access(addr);) return (*sys_rdw)(addr); } /**************************************************************************** REMARKS: Pushes a word onto the stack. NOTE: Do not inline this, as (*sys_wrX) is already inline! ****************************************************************************/ void push_word(u16 w) { DB( if (CHECK_SP_ACCESS()) x86emu_check_sp_access();) M.x86.R_SP -= 2; (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); } /**************************************************************************** REMARKS: Pushes a long onto the stack. NOTE: Do not inline this, as (*sys_wrX) is already inline! ****************************************************************************/ void push_long(u32 w) { DB( if (CHECK_SP_ACCESS()) x86emu_check_sp_access();) M.x86.R_SP -= 4; (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); } /**************************************************************************** REMARKS: Pops a word from the stack. NOTE: Do not inline this, as (*sys_rdX) is already inline! ****************************************************************************/ u16 pop_word(void) { register u16 res; DB( if (CHECK_SP_ACCESS()) x86emu_check_sp_access();) res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); M.x86.R_SP += 2; return res; } /**************************************************************************** REMARKS: Pops a long from the stack. NOTE: Do not inline this, as (*sys_rdX) is already inline! ****************************************************************************/ u32 pop_long(void) { register u32 res; DB( if (CHECK_SP_ACCESS()) x86emu_check_sp_access();) res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); M.x86.R_SP += 4; return res; } #ifdef __HAVE_INLINE_ASSEMBLER__ u16 aaa_word (u16 d) { return aaa_word_asm(&M.x86.R_EFLG,d); } u16 aas_word (u16 d) { return aas_word_asm(&M.x86.R_EFLG,d); } u16 aad_word (u16 d) { return aad_word_asm(&M.x86.R_EFLG,d); } u16 aam_word (u8 d) { return aam_word_asm(&M.x86.R_EFLG,d); } u8 adc_byte (u8 d, u8 s) { return adc_byte_asm(&M.x86.R_EFLG,d,s); } u16 adc_word (u16 d, u16 s) { return adc_word_asm(&M.x86.R_EFLG,d,s); } u32 adc_long (u32 d, u32 s) { return adc_long_asm(&M.x86.R_EFLG,d,s); } u8 add_byte (u8 d, u8 s) { return add_byte_asm(&M.x86.R_EFLG,d,s); } u16 add_word (u16 d, u16 s) { return add_word_asm(&M.x86.R_EFLG,d,s); } u32 add_long (u32 d, u32 s) { return add_long_asm(&M.x86.R_EFLG,d,s); } u8 and_byte (u8 d, u8 s) { return and_byte_asm(&M.x86.R_EFLG,d,s); } u16 and_word (u16 d, u16 s) { return and_word_asm(&M.x86.R_EFLG,d,s); } u32 and_long (u32 d, u32 s) { return and_long_asm(&M.x86.R_EFLG,d,s); } u8 cmp_byte (u8 d, u8 s) { return cmp_byte_asm(&M.x86.R_EFLG,d,s); } u16 cmp_word (u16 d, u16 s) { return cmp_word_asm(&M.x86.R_EFLG,d,s); } u32 cmp_long (u32 d, u32 s) { return cmp_long_asm(&M.x86.R_EFLG,d,s); } u8 daa_byte (u8 d) { return daa_byte_asm(&M.x86.R_EFLG,d); } u8 das_byte (u8 d) { return das_byte_asm(&M.x86.R_EFLG,d); } u8 dec_byte (u8 d) { return dec_byte_asm(&M.x86.R_EFLG,d); } u16 dec_word (u16 d) { return dec_word_asm(&M.x86.R_EFLG,d); } u32 dec_long (u32 d) { return dec_long_asm(&M.x86.R_EFLG,d); } u8 inc_byte (u8 d) { return inc_byte_asm(&M.x86.R_EFLG,d); } u16 inc_word (u16 d) { return inc_word_asm(&M.x86.R_EFLG,d); } u32 inc_long (u32 d) { return inc_long_asm(&M.x86.R_EFLG,d); } u8 or_byte (u8 d, u8 s) { return or_byte_asm(&M.x86.R_EFLG,d,s); } u16 or_word (u16 d, u16 s) { return or_word_asm(&M.x86.R_EFLG,d,s); } u32 or_long (u32 d, u32 s) { return or_long_asm(&M.x86.R_EFLG,d,s); } u8 neg_byte (u8 s) { return neg_byte_asm(&M.x86.R_EFLG,s); } u16 neg_word (u16 s) { return neg_word_asm(&M.x86.R_EFLG,s); } u32 neg_long (u32 s) { return neg_long_asm(&M.x86.R_EFLG,s); } u8 not_byte (u8 s) { return not_byte_asm(&M.x86.R_EFLG,s); } u16 not_word (u16 s) { return not_word_asm(&M.x86.R_EFLG,s); } u32 not_long (u32 s) { return not_long_asm(&M.x86.R_EFLG,s); } u8 rcl_byte (u8 d, u8 s) { return rcl_byte_asm(&M.x86.R_EFLG,d,s); } u16 rcl_word (u16 d, u8 s) { return rcl_word_asm(&M.x86.R_EFLG,d,s); } u32 rcl_long (u32 d, u8 s) { return rcl_long_asm(&M.x86.R_EFLG,d,s); } u8 rcr_byte (u8 d, u8 s) { return rcr_byte_asm(&M.x86.R_EFLG,d,s); } u16 rcr_word (u16 d, u8 s) { return rcr_word_asm(&M.x86.R_EFLG,d,s); } u32 rcr_long (u32 d, u8 s) { return rcr_long_asm(&M.x86.R_EFLG,d,s); } u8 rol_byte (u8 d, u8 s) { return rol_byte_asm(&M.x86.R_EFLG,d,s); } u16 rol_word (u16 d, u8 s) { return rol_word_asm(&M.x86.R_EFLG,d,s); } u32 rol_long (u32 d, u8 s) { return rol_long_asm(&M.x86.R_EFLG,d,s); } u8 ror_byte (u8 d, u8 s) { return ror_byte_asm(&M.x86.R_EFLG,d,s); } u16 ror_word (u16 d, u8 s) { return ror_word_asm(&M.x86.R_EFLG,d,s); } u32 ror_long (u32 d, u8 s) { return ror_long_asm(&M.x86.R_EFLG,d,s); } u8 shl_byte (u8 d, u8 s) { return shl_byte_asm(&M.x86.R_EFLG,d,s); } u16 shl_word (u16 d, u8 s) { return shl_word_asm(&M.x86.R_EFLG,d,s); } u32 shl_long (u32 d, u8 s) { return shl_long_asm(&M.x86.R_EFLG,d,s); } u8 shr_byte (u8 d, u8 s) { return shr_byte_asm(&M.x86.R_EFLG,d,s); } u16 shr_word (u16 d, u8 s) { return shr_word_asm(&M.x86.R_EFLG,d,s); } u32 shr_long (u32 d, u8 s) { return shr_long_asm(&M.x86.R_EFLG,d,s); } u8 sar_byte (u8 d, u8 s) { return sar_byte_asm(&M.x86.R_EFLG,d,s); } u16 sar_word (u16 d, u8 s) { return sar_word_asm(&M.x86.R_EFLG,d,s); } u32 sar_long (u32 d, u8 s) { return sar_long_asm(&M.x86.R_EFLG,d,s); } u16 shld_word (u16 d, u16 fill, u8 s) { return shld_word_asm(&M.x86.R_EFLG,d,fill,s); } u32 shld_long (u32 d, u32 fill, u8 s) { return shld_long_asm(&M.x86.R_EFLG,d,fill,s); } u16 shrd_word (u16 d, u16 fill, u8 s) { return shrd_word_asm(&M.x86.R_EFLG,d,fill,s); } u32 shrd_long (u32 d, u32 fill, u8 s) { return shrd_long_asm(&M.x86.R_EFLG,d,fill,s); } u8 sbb_byte (u8 d, u8 s) { return sbb_byte_asm(&M.x86.R_EFLG,d,s); } u16 sbb_word (u16 d, u16 s) { return sbb_word_asm(&M.x86.R_EFLG,d,s); } u32 sbb_long (u32 d, u32 s) { return sbb_long_asm(&M.x86.R_EFLG,d,s); } u8 sub_byte (u8 d, u8 s) { return sub_byte_asm(&M.x86.R_EFLG,d,s); } u16 sub_word (u16 d, u16 s) { return sub_word_asm(&M.x86.R_EFLG,d,s); } u32 sub_long (u32 d, u32 s) { return sub_long_asm(&M.x86.R_EFLG,d,s); } void test_byte (u8 d, u8 s) { test_byte_asm(&M.x86.R_EFLG,d,s); } void test_word (u16 d, u16 s) { test_word_asm(&M.x86.R_EFLG,d,s); } void test_long (u32 d, u32 s) { test_long_asm(&M.x86.R_EFLG,d,s); } u8 xor_byte (u8 d, u8 s) { return xor_byte_asm(&M.x86.R_EFLG,d,s); } u16 xor_word (u16 d, u16 s) { return xor_word_asm(&M.x86.R_EFLG,d,s); } u32 xor_long (u32 d, u32 s) { return xor_long_asm(&M.x86.R_EFLG,d,s); } void imul_byte (u8 s) { imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } void imul_word (u16 s) { imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } void imul_long (u32 s) { imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) { imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s); } void mul_byte (u8 s) { mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } void mul_word (u16 s) { mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } void mul_long (u32 s) { mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } void idiv_byte (u8 s) { idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } void idiv_word (u16 s) { idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } void idiv_long (u32 s) { idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } void div_byte (u8 s) { div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } void div_word (u16 s) { div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } void div_long (u32 s) { div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } #endif xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/LICENSE0000644000000000000000000000134210410136571015755 0ustar License information ------------------- The x86emu library is under a BSD style license, comaptible with the XFree86 and X licenses used by XFree86. The original x86emu libraries were under the GNU General Public License. Due to license incompatibilities between the GPL and the XFree86 license, the original authors of the code decided to allow a license change. If you have submitted code to the original x86emu project, and you don't agree with the license change, please contact us and let you know. Your code will be removed to comply with your wishes. If you have any questions about this, please send email to x86emu@linuxlabs.com or KendallB@scitechsoft.com for clarification. xresprobe-0.4.24ubuntu9/ddcprobe/x86emu/sys.c0000644000000000000000000004220010410136571015730 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: This file includes subroutines which are related to * programmed I/O and memory access. Included in this module * are default functions with limited usefulness. For real * uses these functions will most likely be overriden by the * user library. * ****************************************************************************/ #include "x86emu.h" #include "x86emu/x86emui.h" #include "x86emu/regs.h" #include "x86emu/debug.h" #include "x86emu/prim_ops.h" #ifdef IN_MODULE #include "xf86_ansic.h" #else #include #endif /*------------------------- Global Variables ------------------------------*/ X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ X86EMU_intrFuncs _X86EMU_intrTab[256]; /*----------------------------- Implementation ----------------------------*/ #if defined(__alpha__) || defined(__alpha) /* to cope with broken egcs-1.1.2 :-(((( */ /* * inline functions to do unaligned accesses * from linux/include/asm-alpha/unaligned.h */ /* * EGCS 1.1 knows about arbitrary unaligned loads. Define some * packed structures to talk about such things with. */ #if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) struct __una_u64 { unsigned long x __attribute__((packed)); }; struct __una_u32 { unsigned int x __attribute__((packed)); }; struct __una_u16 { unsigned short x __attribute__((packed)); }; #endif static __inline__ unsigned long ldq_u(unsigned long * r11) { #if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) const struct __una_u64 *ptr = (const struct __una_u64 *) r11; return ptr->x; #else unsigned long r1,r2; __asm__("ldq_u %0,%3\n\t" "ldq_u %1,%4\n\t" "extql %0,%2,%0\n\t" "extqh %1,%2,%1" :"=&r" (r1), "=&r" (r2) :"r" (r11), "m" (*r11), "m" (*(const unsigned long *)(7+(char *) r11))); return r1 | r2; #endif } static __inline__ unsigned long ldl_u(unsigned int * r11) { #if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) const struct __una_u32 *ptr = (const struct __una_u32 *) r11; return ptr->x; #else unsigned long r1,r2; __asm__("ldq_u %0,%3\n\t" "ldq_u %1,%4\n\t" "extll %0,%2,%0\n\t" "extlh %1,%2,%1" :"=&r" (r1), "=&r" (r2) :"r" (r11), "m" (*r11), "m" (*(const unsigned long *)(3+(char *) r11))); return r1 | r2; #endif } static __inline__ unsigned long ldw_u(unsigned short * r11) { #if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) const struct __una_u16 *ptr = (const struct __una_u16 *) r11; return ptr->x; #else unsigned long r1,r2; __asm__("ldq_u %0,%3\n\t" "ldq_u %1,%4\n\t" "extwl %0,%2,%0\n\t" "extwh %1,%2,%1" :"=&r" (r1), "=&r" (r2) :"r" (r11), "m" (*r11), "m" (*(const unsigned long *)(1+(char *) r11))); return r1 | r2; #endif } /* * Elemental unaligned stores */ static __inline__ void stq_u(unsigned long r5, unsigned long * r11) { #if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) struct __una_u64 *ptr = (struct __una_u64 *) r11; ptr->x = r5; #else unsigned long r1,r2,r3,r4; __asm__("ldq_u %3,%1\n\t" "ldq_u %2,%0\n\t" "insqh %6,%7,%5\n\t" "insql %6,%7,%4\n\t" "mskqh %3,%7,%3\n\t" "mskql %2,%7,%2\n\t" "bis %3,%5,%3\n\t" "bis %2,%4,%2\n\t" "stq_u %3,%1\n\t" "stq_u %2,%0" :"=m" (*r11), "=m" (*(unsigned long *)(7+(char *) r11)), "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) :"r" (r5), "r" (r11)); #endif } static __inline__ void stl_u(unsigned long r5, unsigned int * r11) { #if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) struct __una_u32 *ptr = (struct __una_u32 *) r11; ptr->x = r5; #else unsigned long r1,r2,r3,r4; __asm__("ldq_u %3,%1\n\t" "ldq_u %2,%0\n\t" "inslh %6,%7,%5\n\t" "insll %6,%7,%4\n\t" "msklh %3,%7,%3\n\t" "mskll %2,%7,%2\n\t" "bis %3,%5,%3\n\t" "bis %2,%4,%2\n\t" "stq_u %3,%1\n\t" "stq_u %2,%0" :"=m" (*r11), "=m" (*(unsigned long *)(3+(char *) r11)), "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) :"r" (r5), "r" (r11)); #endif } static __inline__ void stw_u(unsigned long r5, unsigned short * r11) { #if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) struct __una_u16 *ptr = (struct __una_u16 *) r11; ptr->x = r5; #else unsigned long r1,r2,r3,r4; __asm__("ldq_u %3,%1\n\t" "ldq_u %2,%0\n\t" "inswh %6,%7,%5\n\t" "inswl %6,%7,%4\n\t" "mskwh %3,%7,%3\n\t" "mskwl %2,%7,%2\n\t" "bis %3,%5,%3\n\t" "bis %2,%4,%2\n\t" "stq_u %3,%1\n\t" "stq_u %2,%0" :"=m" (*r11), "=m" (*(unsigned long *)(1+(char *) r11)), "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) :"r" (r5), "r" (r11)); #endif } #endif /**************************************************************************** PARAMETERS: addr - Emulator memory address to read RETURNS: Byte value read from emulator memory. REMARKS: Reads a byte value from the emulator memory. ****************************************************************************/ u8 X86API rdb( u32 addr) { u8 val; if (addr > M.mem_size - 1) { DB(printk("mem_read: address %#lx out of range!\n", addr);) HALT_SYS(); } val = *(u8*)(M.mem_base + addr); DB( if (DEBUG_MEM_TRACE()) printk("%#08x 1 -> %#x\n", addr, val);) return val; } /**************************************************************************** PARAMETERS: addr - Emulator memory address to read RETURNS: Word value read from emulator memory. REMARKS: Reads a word value from the emulator memory. ****************************************************************************/ u16 X86API rdw( u32 addr) { u16 val = 0; if (addr > M.mem_size - 2) { DB(printk("mem_read: address %#lx out of range!\n", addr);) HALT_SYS(); } #ifdef __BIG_ENDIAN__ if (addr & 0x1) { val = (*(u8*)(M.mem_base + addr) | (*(u8*)(M.mem_base + addr + 1) << 8)); } else #endif #if defined(__alpha__) || defined(__alpha) val = ldw_u((u16*)(M.mem_base + addr)); #else val = *(u16*)(M.mem_base + addr); #endif DB( if (DEBUG_MEM_TRACE()) printk("%#08x 2 -> %#x\n", addr, val);) return val; } /**************************************************************************** PARAMETERS: addr - Emulator memory address to read RETURNS: Long value read from emulator memory. REMARKS: Reads a long value from the emulator memory. ****************************************************************************/ u32 X86API rdl( u32 addr) { u32 val = 0; if (addr > M.mem_size - 4) { DB(printk("mem_read: address %#lx out of range!\n", addr);) HALT_SYS(); } #ifdef __BIG_ENDIAN__ if (addr & 0x3) { val = (*(u8*)(M.mem_base + addr + 0) | (*(u8*)(M.mem_base + addr + 1) << 8) | (*(u8*)(M.mem_base + addr + 2) << 16) | (*(u8*)(M.mem_base + addr + 3) << 24)); } else #endif #if defined(__alpha__) || defined(__alpha) val = ldl_u((u32*)(M.mem_base + addr)); #else val = *(u32*)(M.mem_base + addr); #endif DB( if (DEBUG_MEM_TRACE()) printk("%#08x 4 -> %#x\n", addr, val);) return val; } /**************************************************************************** PARAMETERS: addr - Emulator memory address to read val - Value to store REMARKS: Writes a byte value to emulator memory. ****************************************************************************/ void X86API wrb( u32 addr, u8 val) { DB( if (DEBUG_MEM_TRACE()) printk("%#08x 1 <- %#x\n", addr, val);) if (addr > M.mem_size - 1) { DB(printk("mem_write: address %#lx out of range!\n", addr);) HALT_SYS(); } *(u8*)(M.mem_base + addr) = val; } /**************************************************************************** PARAMETERS: addr - Emulator memory address to read val - Value to store REMARKS: Writes a word value to emulator memory. ****************************************************************************/ void X86API wrw( u32 addr, u16 val) { DB( if (DEBUG_MEM_TRACE()) printk("%#08x 2 <- %#x\n", addr, val);) if (addr > M.mem_size - 2) { DB(printk("mem_write: address %#lx out of range!\n", addr);) HALT_SYS(); } #ifdef __BIG_ENDIAN__ if (addr & 0x1) { *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; } else #endif #if defined(__alpha__) || defined(__alpha) stw_u(val,(u16*)(M.mem_base + addr)); #else *(u16*)(M.mem_base + addr) = val; #endif } /**************************************************************************** PARAMETERS: addr - Emulator memory address to read val - Value to store REMARKS: Writes a long value to emulator memory. ****************************************************************************/ void X86API wrl( u32 addr, u32 val) { DB( if (DEBUG_MEM_TRACE()) printk("%#08x 4 <- %#x\n", addr, val);) if (addr > M.mem_size - 4) { DB(printk("mem_write: address %#lx out of range!\n", addr);) HALT_SYS(); } #ifdef __BIG_ENDIAN__ if (addr & 0x1) { *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; } else #endif #if defined(__alpha__) || defined(__alpha) stl_u(val,(u32*)(M.mem_base + addr)); #else *(u32*)(M.mem_base + addr) = val; #endif } /**************************************************************************** PARAMETERS: addr - PIO address to read RETURN: 0 REMARKS: Default PIO byte read function. Doesn't perform real inb. ****************************************************************************/ static u8 X86API p_inb( X86EMU_pioAddr addr) { printf("No real inb\n"); DB( if (DEBUG_IO_TRACE()) printk("inb %#04x \n", addr);) return 0; } /**************************************************************************** PARAMETERS: addr - PIO address to read RETURN: 0 REMARKS: Default PIO word read function. Doesn't perform real inw. ****************************************************************************/ static u16 X86API p_inw( X86EMU_pioAddr addr) { printf("No real inw\n"); DB( if (DEBUG_IO_TRACE()) printk("inw %#04x \n", addr);) return 0; } /**************************************************************************** PARAMETERS: addr - PIO address to read RETURN: 0 REMARKS: Default PIO long read function. Doesn't perform real inl. ****************************************************************************/ static u32 X86API p_inl( X86EMU_pioAddr addr) { printf("No real inl\n"); DB( if (DEBUG_IO_TRACE()) printk("inl %#04x \n", addr);) return 0; } /**************************************************************************** PARAMETERS: addr - PIO address to write val - Value to store REMARKS: Default PIO byte write function. Doesn't perform real outb. ****************************************************************************/ static void X86API p_outb( X86EMU_pioAddr addr, u8 val) { printf("No real outb\n"); DB( if (DEBUG_IO_TRACE()) printk("outb %#02x -> %#04x \n", val, addr);) return; } /**************************************************************************** PARAMETERS: addr - PIO address to write val - Value to store REMARKS: Default PIO word write function. Doesn't perform real outw. ****************************************************************************/ static void X86API p_outw( X86EMU_pioAddr addr, u16 val) { printf("No real outw\n"); DB( if (DEBUG_IO_TRACE()) printk("outw %#04x -> %#04x \n", val, addr);) return; } /**************************************************************************** PARAMETERS: addr - PIO address to write val - Value to store REMARKS: Default PIO ;ong write function. Doesn't perform real outl. ****************************************************************************/ static void X86API p_outl( X86EMU_pioAddr addr, u32 val) { printf("No real outl\n"); DB( if (DEBUG_IO_TRACE()) printk("outl %#08x -> %#04x \n", val, addr);) return; } /*------------------------- Global Variables ------------------------------*/ u8 (X86APIP sys_rdb)(u32 addr) = rdb; u16 (X86APIP sys_rdw)(u32 addr) = rdw; u32 (X86APIP sys_rdl)(u32 addr) = rdl; void (X86APIP sys_wrb)(u32 addr,u8 val) = wrb; void (X86APIP sys_wrw)(u32 addr,u16 val) = wrw; void (X86APIP sys_wrl)(u32 addr,u32 val) = wrl; u8 (X86APIP sys_inb)(X86EMU_pioAddr addr) = p_inb; u16 (X86APIP sys_inw)(X86EMU_pioAddr addr) = p_inw; u32 (X86APIP sys_inl)(X86EMU_pioAddr addr) = p_inl; void (X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) = p_outb; void (X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val) = p_outw; void (X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val) = p_outl; /*----------------------------- Setup -------------------------------------*/ /**************************************************************************** PARAMETERS: funcs - New memory function pointers to make active REMARKS: This function is used to set the pointers to functions which access memory space, allowing the user application to override these functions and hook them out as necessary for their application. ****************************************************************************/ void X86EMU_setupMemFuncs( X86EMU_memFuncs *funcs) { sys_rdb = funcs->rdb; sys_rdw = funcs->rdw; sys_rdl = funcs->rdl; sys_wrb = funcs->wrb; sys_wrw = funcs->wrw; sys_wrl = funcs->wrl; } /**************************************************************************** PARAMETERS: funcs - New programmed I/O function pointers to make active REMARKS: This function is used to set the pointers to functions which access I/O space, allowing the user application to override these functions and hook them out as necessary for their application. ****************************************************************************/ void X86EMU_setupPioFuncs( X86EMU_pioFuncs *funcs) { sys_inb = funcs->inb; sys_inw = funcs->inw; sys_inl = funcs->inl; sys_outb = funcs->outb; sys_outw = funcs->outw; sys_outl = funcs->outl; } /**************************************************************************** PARAMETERS: funcs - New interrupt vector table to make active REMARKS: This function is used to set the pointers to functions which handle interrupt processing in the emulator, allowing the user application to hook interrupts as necessary for their application. Any interrupts that are not hooked by the user application, and reflected and handled internally in the emulator via the interrupt vector table. This allows the application to get control when the code being emulated executes specific software interrupts. ****************************************************************************/ void X86EMU_setupIntrFuncs( X86EMU_intrFuncs funcs[]) { int i; for (i=0; i < 256; i++) _X86EMU_intrTab[i] = NULL; if (funcs) { for (i = 0; i < 256; i++) _X86EMU_intrTab[i] = funcs[i]; } } /**************************************************************************** PARAMETERS: int - New software interrupt to prepare for REMARKS: This function is used to set up the emulator state to exceute a software interrupt. This can be used by the user application code to allow an interrupt to be hooked, examined and then reflected back to the emulator so that the code in the emulator will continue processing the software interrupt as per normal. This essentially allows system code to actively hook and handle certain software interrupts as necessary. ****************************************************************************/ void X86EMU_prepareForInt( int num) { push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); push_word(M.x86.R_CS); M.x86.R_CS = mem_access_word(num * 4 + 2); push_word(M.x86.R_IP); M.x86.R_IP = mem_access_word(num * 4); M.x86.intr = 0; } xresprobe-0.4.24ubuntu9/ddcprobe/x86-common.c0000644000000000000000000001123510410136571015675 0ustar /* Linux Real Mode Interface - A library of DPMI-like functions for Linux. Copyright (C) 1998 by Josh Vanderhoof Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL JOSH VANDERHOOF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include "include/lrmi.h" /*#define REAL_MEM_BASE ((void *)0x1000) #define REAL_MEM_SIZE 0xa0000 #define REAL_MEM_BLOCKS 0x280*/ #define REAL_MEM_BASE ((void *)0x1000) #define REAL_MEM_SIZE 0x80000 #define REAL_MEM_BLOCKS (REAL_MEM_SIZE/1024) struct mem_block { unsigned int size : 20; unsigned int free : 1; }; static struct { int ready; int count; struct mem_block blocks[REAL_MEM_BLOCKS]; } mem_info = { .ready = 0 }; static int real_mem_init(void) { void *m; int fd_zero; if (mem_info.ready) return 1; fd_zero = open("/dev/zero", O_RDWR); if (fd_zero == -1) { perror("open /dev/zero"); return 0; } m = mmap((void *)REAL_MEM_BASE, REAL_MEM_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_SHARED, fd_zero, 0); if (m == (void *)-1) { perror("mmap /dev/zero"); close(fd_zero); return 0; } close(fd_zero); mem_info.ready = 1; mem_info.count = 1; mem_info.blocks[0].size = REAL_MEM_SIZE; mem_info.blocks[0].free = 1; return 1; } static void real_mem_deinit(void) { if (mem_info.ready) { munmap((void *)REAL_MEM_BASE, REAL_MEM_SIZE); mem_info.ready = 0; } } static void insert_block(int i) { memmove( mem_info.blocks + i + 1, mem_info.blocks + i, (mem_info.count - i) * sizeof(struct mem_block)); mem_info.count++; } static void delete_block(int i) { mem_info.count--; memmove( mem_info.blocks + i, mem_info.blocks + i + 1, (mem_info.count - i) * sizeof(struct mem_block)); } void * LRMI_alloc_real(int size) { int i; char *r = (char *)REAL_MEM_BASE; if (!mem_info.ready) return NULL; if (mem_info.count == REAL_MEM_BLOCKS) return NULL; size = (size + 15) & ~15; for (i = 0; i < mem_info.count; i++) { if (mem_info.blocks[i].free && size < mem_info.blocks[i].size) { insert_block(i); mem_info.blocks[i].size = size; mem_info.blocks[i].free = 0; mem_info.blocks[i + 1].size -= size; return (void *)r; } r += mem_info.blocks[i].size; } return NULL; } void LRMI_free_real(void *m) { int i; char *r = (char *)REAL_MEM_BASE; if (!mem_info.ready) return; i = 0; while (m != (void *)r) { r += mem_info.blocks[i].size; i++; if (i == mem_info.count) return; } mem_info.blocks[i].free = 1; if (i + 1 < mem_info.count && mem_info.blocks[i + 1].free) { mem_info.blocks[i].size += mem_info.blocks[i + 1].size; delete_block(i + 1); } if (i - 1 >= 0 && mem_info.blocks[i - 1].free) { mem_info.blocks[i - 1].size += mem_info.blocks[i].size; delete_block(i); } } #define DEFAULT_STACK_SIZE 0x1000 static inline void set_bit(unsigned int bit, void *array) { unsigned char *a = array; a[bit / 8] |= (1 << (bit % 8)); } int LRMI_common_init(void) { void *m; int fd_mem; if (!real_mem_init()) return 0; /* Map the Interrupt Vectors (0x0 - 0x400) + BIOS data (0x400 - 0x502) and the ROM (0xa0000 - 0x100000) */ fd_mem = open("/dev/mem", O_RDWR); if (fd_mem == -1) { real_mem_deinit(); perror("open /dev/mem"); return 0; } m = mmap((void *)0, 0x502, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_SHARED, fd_mem, 0); if (m == (void *)-1) { close(fd_mem); real_mem_deinit(); perror("mmap /dev/mem"); return 0; } m = mmap((void *)0xa0000, 0x100000 - 0xa0000, PROT_READ | PROT_WRITE, MAP_FIXED | MAP_SHARED, fd_mem, 0xa0000); if (m == (void *)-1) { munmap((void *)0, 0x502); close(fd_mem); real_mem_deinit(); perror("mmap /dev/mem"); return 0; } close(fd_mem); return 1; } xresprobe-0.4.24ubuntu9/ddcprobe/lrmi.c0000644000000000000000000004377311261766110014744 0ustar /* Linux Real Mode Interface - A library of DPMI-like functions for Linux. Copyright (C) 1998 by Josh Vanderhoof Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL JOSH VANDERHOOF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #if defined(__linux__) && defined(__i386__) #include #ifdef USE_LIBC_VM86 #include #endif #elif defined(__NetBSD__) || defined(__FreeBSD__) #include #include #include #include #include #include #endif /* __NetBSD__ || __FreeBSD__ */ #include #include #include #include #include #include "include/lrmi.h" #include "x86-common.h" #if defined(__linux__) && !defined(TF_MASK) #define TF_MASK X86_EFLAGS_TF #define IF_MASK X86_EFLAGS_IF #define VIF_MASK X86_EFLAGS_VIF #define IOPL_MASK X86_EFLAGS_IOPL #endif #if defined(__linux__) #define DEFAULT_VM86_FLAGS (IF_MASK | IOPL_MASK) #elif defined(__NetBSD__) || defined(__FreeBSD__) #define DEFAULT_VM86_FLAGS (PSL_I | PSL_IOPL) #define TF_MASK PSL_T #define VIF_MASK PSL_VIF #endif #define DEFAULT_STACK_SIZE 0x1000 #define RETURN_TO_32_INT 255 #if defined(__linux__) #define CONTEXT_REGS context.vm.regs #define REG(x) x #elif defined(__NetBSD__) #define CONTEXT_REGS context.vm.substr.regs #define REG(x) vmsc.sc_ ## x #elif defined(__FreeBSD__) #define CONTEXT_REGS context.vm.uc #define REG(x) uc_mcontext.mc_ ## x #endif static struct { int ready; unsigned short ret_seg, ret_off; unsigned short stack_seg, stack_off; #if defined(__linux__) || defined(__NetBSD__) struct vm86_struct vm; #elif defined(__FreeBSD__) struct { struct vm86_init_args init; ucontext_t uc; } vm; #endif #if defined(__NetBSD__) || defined(__FreeBSD__) int success; jmp_buf env; void *old_sighandler; int vret; #endif } context = { 0 }; static inline void set_bit(unsigned int bit, void *array) { unsigned char *a = array; a[bit / 8] |= (1 << (bit % 8)); } static inline unsigned int get_int_seg(int i) { return *(unsigned short *)(i * 4 + 2); } static inline unsigned int get_int_off(int i) { return *(unsigned short *)(i * 4); } static inline void pushw(unsigned short i) { CONTEXT_REGS.REG(esp) -= 2; *(unsigned short *)(((unsigned int)CONTEXT_REGS.REG(ss) << 4) + CONTEXT_REGS.REG(esp)) = i; } int LRMI_init(void) { void *m; if (context.ready) return 1; if (!LRMI_common_init()) return 0; /* Allocate a stack */ m = LRMI_alloc_real(DEFAULT_STACK_SIZE); context.stack_seg = (unsigned int)m >> 4; context.stack_off = DEFAULT_STACK_SIZE; /* Allocate the return to 32 bit routine */ m = LRMI_alloc_real(2); context.ret_seg = (unsigned int)m >> 4; context.ret_off = (unsigned int)m & 0xf; ((unsigned char *)m)[0] = 0xcd; /* int opcode */ ((unsigned char *)m)[1] = RETURN_TO_32_INT; memset(&context.vm, 0, sizeof(context.vm)); /* Enable kernel emulation of all ints except RETURN_TO_32_INT */ #if defined(__linux__) memset(&context.vm.int_revectored, 0, sizeof(context.vm.int_revectored)); set_bit(RETURN_TO_32_INT, &context.vm.int_revectored); #elif defined(__NetBSD__) set_bit(RETURN_TO_32_INT, &context.vm.int_byuser); #elif defined(__FreeBSD__) set_bit(RETURN_TO_32_INT, &context.vm.init.int_map); #endif context.ready = 1; return 1; } static void set_regs(struct LRMI_regs *r) { CONTEXT_REGS.REG(edi) = r->edi; CONTEXT_REGS.REG(esi) = r->esi; CONTEXT_REGS.REG(ebp) = r->ebp; CONTEXT_REGS.REG(ebx) = r->ebx; CONTEXT_REGS.REG(edx) = r->edx; CONTEXT_REGS.REG(ecx) = r->ecx; CONTEXT_REGS.REG(eax) = r->eax; CONTEXT_REGS.REG(eflags) = DEFAULT_VM86_FLAGS; CONTEXT_REGS.REG(es) = r->es; CONTEXT_REGS.REG(ds) = r->ds; CONTEXT_REGS.REG(fs) = r->fs; CONTEXT_REGS.REG(gs) = r->gs; } static void get_regs(struct LRMI_regs *r) { r->edi = CONTEXT_REGS.REG(edi); r->esi = CONTEXT_REGS.REG(esi); r->ebp = CONTEXT_REGS.REG(ebp); r->ebx = CONTEXT_REGS.REG(ebx); r->edx = CONTEXT_REGS.REG(edx); r->ecx = CONTEXT_REGS.REG(ecx); r->eax = CONTEXT_REGS.REG(eax); r->flags = CONTEXT_REGS.REG(eflags); r->es = CONTEXT_REGS.REG(es); r->ds = CONTEXT_REGS.REG(ds); r->fs = CONTEXT_REGS.REG(fs); r->gs = CONTEXT_REGS.REG(gs); } #define DIRECTION_FLAG (1 << 10) enum { CSEG = 0x2e, SSEG = 0x36, DSEG = 0x3e, ESEG = 0x26, FSEG = 0x64, GSEG = 0x65 }; static void em_ins(int size) { unsigned int edx, edi; edx = CONTEXT_REGS.REG(edx) & 0xffff; edi = CONTEXT_REGS.REG(edi) & 0xffff; edi += (unsigned int)CONTEXT_REGS.REG(es) << 4; if (CONTEXT_REGS.REG(eflags) & DIRECTION_FLAG) { if (size == 4) asm volatile ("std; insl; cld" : "=D" (edi) : "d" (edx), "0" (edi)); else if (size == 2) asm volatile ("std; insw; cld" : "=D" (edi) : "d" (edx), "0" (edi)); else asm volatile ("std; insb; cld" : "=D" (edi) : "d" (edx), "0" (edi)); } else { if (size == 4) asm volatile ("cld; insl" : "=D" (edi) : "d" (edx), "0" (edi)); else if (size == 2) asm volatile ("cld; insw" : "=D" (edi) : "d" (edx), "0" (edi)); else asm volatile ("cld; insb" : "=D" (edi) : "d" (edx), "0" (edi)); } edi -= (unsigned int)CONTEXT_REGS.REG(es) << 4; CONTEXT_REGS.REG(edi) &= 0xffff0000; CONTEXT_REGS.REG(edi) |= edi & 0xffff; } static void em_rep_ins(int size) { unsigned int cx; cx = CONTEXT_REGS.REG(ecx) & 0xffff; while (cx--) em_ins(size); CONTEXT_REGS.REG(ecx) &= 0xffff0000; } static void em_outs(int size, int seg) { unsigned int edx, esi, base; edx = CONTEXT_REGS.REG(edx) & 0xffff; esi = CONTEXT_REGS.REG(esi) & 0xffff; switch (seg) { case CSEG: base = CONTEXT_REGS.REG(cs); break; case SSEG: base = CONTEXT_REGS.REG(ss); break; case ESEG: base = CONTEXT_REGS.REG(es); break; case FSEG: base = CONTEXT_REGS.REG(fs); break; case GSEG: base = CONTEXT_REGS.REG(gs); break; default: case DSEG: base = CONTEXT_REGS.REG(ds); break; } esi += base << 4; if (CONTEXT_REGS.REG(eflags) & DIRECTION_FLAG) { if (size == 4) asm volatile ("std; outsl; cld" : "=S" (esi) : "d" (edx), "0" (esi)); else if (size == 2) asm volatile ("std; outsw; cld" : "=S" (esi) : "d" (edx), "0" (esi)); else asm volatile ("std; outsb; cld" : "=S" (esi) : "d" (edx), "0" (esi)); } else { if (size == 4) asm volatile ("cld; outsl" : "=S" (esi) : "d" (edx), "0" (esi)); else if (size == 2) asm volatile ("cld; outsw" : "=S" (esi) : "d" (edx), "0" (esi)); else asm volatile ("cld; outsb" : "=S" (esi) : "d" (edx), "0" (esi)); } esi -= base << 4; CONTEXT_REGS.REG(esi) &= 0xffff0000; CONTEXT_REGS.REG(esi) |= esi & 0xffff; } static void em_rep_outs(int size, int seg) { unsigned int cx; cx = CONTEXT_REGS.REG(ecx) & 0xffff; while (cx--) em_outs(size, seg); CONTEXT_REGS.REG(ecx) &= 0xffff0000; } static void em_inbl(unsigned char literal) { asm volatile ("inb %w1, %b0" : "=a" (CONTEXT_REGS.REG(eax)) : "d" (literal), "0" (CONTEXT_REGS.REG(eax))); } static void em_inb(void) { asm volatile ("inb %w1, %b0" : "=a" (CONTEXT_REGS.REG(eax)) : "d" (CONTEXT_REGS.REG(edx)), "0" (CONTEXT_REGS.REG(eax))); } static void em_inw(void) { asm volatile ("inw %w1, %w0" : "=a" (CONTEXT_REGS.REG(eax)) : "d" (CONTEXT_REGS.REG(edx)), "0" (CONTEXT_REGS.REG(eax))); } static void em_inl(void) { asm volatile ("inl %w1, %0" : "=a" (CONTEXT_REGS.REG(eax)) : "d" (CONTEXT_REGS.REG(edx))); } static void em_outbl(unsigned char literal) { asm volatile ("outb %b0, %w1" : : "a" (CONTEXT_REGS.REG(eax)), "d" (literal)); } static void em_outb(void) { asm volatile ("outb %b0, %w1" : : "a" (CONTEXT_REGS.REG(eax)), "d" (CONTEXT_REGS.REG(edx))); } static void em_outw(void) { asm volatile ("outw %w0, %w1" : : "a" (CONTEXT_REGS.REG(eax)), "d" (CONTEXT_REGS.REG(edx))); } static void em_outl(void) { asm volatile ("outl %0, %w1" : : "a" (CONTEXT_REGS.REG(eax)), "d" (CONTEXT_REGS.REG(edx))); } static int emulate(void) { unsigned char *insn; struct { unsigned char seg; unsigned int size : 1; unsigned int rep : 1; } prefix = { DSEG, 0, 0 }; int i = 0; insn = (unsigned char *)((unsigned int)CONTEXT_REGS.REG(cs) << 4); insn += CONTEXT_REGS.REG(eip); while (1) { if (insn[i] == 0x66) { prefix.size = 1 - prefix.size; i++; } else if (insn[i] == 0xf3) { prefix.rep = 1; i++; } else if (insn[i] == CSEG || insn[i] == SSEG || insn[i] == DSEG || insn[i] == ESEG || insn[i] == FSEG || insn[i] == GSEG) { prefix.seg = insn[i]; i++; } else if (insn[i] == 0xf0 || insn[i] == 0xf2 || insn[i] == 0x67) { /* these prefixes are just ignored */ i++; } else if (insn[i] == 0x6c) { if (prefix.rep) em_rep_ins(1); else em_ins(1); i++; break; } else if (insn[i] == 0x6d) { if (prefix.rep) { if (prefix.size) em_rep_ins(4); else em_rep_ins(2); } else { if (prefix.size) em_ins(4); else em_ins(2); } i++; break; } else if (insn[i] == 0x6e) { if (prefix.rep) em_rep_outs(1, prefix.seg); else em_outs(1, prefix.seg); i++; break; } else if (insn[i] == 0x6f) { if (prefix.rep) { if (prefix.size) em_rep_outs(4, prefix.seg); else em_rep_outs(2, prefix.seg); } else { if (prefix.size) em_outs(4, prefix.seg); else em_outs(2, prefix.seg); } i++; break; } else if (insn[i] == 0xe4) { em_inbl(insn[i + 1]); i += 2; break; } else if (insn[i] == 0xec) { em_inb(); i++; break; } else if (insn[i] == 0xed) { if (prefix.size) em_inl(); else em_inw(); i++; break; } else if (insn[i] == 0xe6) { em_outbl(insn[i + 1]); i += 2; break; } else if (insn[i] == 0xee) { em_outb(); i++; break; } else if (insn[i] == 0xef) { if (prefix.size) em_outl(); else em_outw(); i++; break; } else return 0; } CONTEXT_REGS.REG(eip) += i; return 1; } #if defined(__linux__) /* I don't know how to make sure I get the right vm86() from libc. The one I want is syscall # 113 (vm86old() in libc 5, vm86() in glibc) which should be declared as "int vm86(struct vm86_struct *);" in . This just does syscall 113 with inline asm, which should work for both libc's (I hope). */ #if !defined(USE_LIBC_VM86) static int lrmi_vm86(struct vm86_struct *vm) { int r; #ifdef __PIC__ asm volatile ( "pushl %%ebx\n\t" "movl %2, %%ebx\n\t" "int $0x80\n\t" "popl %%ebx" : "=a" (r) : "0" (113), "r" (vm)); #else asm volatile ( "int $0x80" : "=a" (r) : "0" (113), "b" (vm)); #endif return r; } #else #define lrmi_vm86 vm86 #endif #endif /* __linux__ */ static void debug_info(int vret) { #ifdef LRMI_DEBUG int i; unsigned char *p; fputs("vm86() failed\n", stderr); fprintf(stderr, "return = 0x%x\n", vret); fprintf(stderr, "eax = 0x%08x\n", CONTEXT_REGS.REG(eax)); fprintf(stderr, "ebx = 0x%08x\n", CONTEXT_REGS.REG(ebx)); fprintf(stderr, "ecx = 0x%08x\n", CONTEXT_REGS.REG(ecx)); fprintf(stderr, "edx = 0x%08x\n", CONTEXT_REGS.REG(edx)); fprintf(stderr, "esi = 0x%08x\n", CONTEXT_REGS.REG(esi)); fprintf(stderr, "edi = 0x%08x\n", CONTEXT_REGS.REG(edi)); fprintf(stderr, "ebp = 0x%08x\n", CONTEXT_REGS.REG(ebp)); fprintf(stderr, "eip = 0x%08x\n", CONTEXT_REGS.REG(eip)); fprintf(stderr, "cs = 0x%04x\n", CONTEXT_REGS.REG(cs)); fprintf(stderr, "esp = 0x%08x\n", CONTEXT_REGS.REG(esp)); fprintf(stderr, "ss = 0x%04x\n", CONTEXT_REGS.REG(ss)); fprintf(stderr, "ds = 0x%04x\n", CONTEXT_REGS.REG(ds)); fprintf(stderr, "es = 0x%04x\n", CONTEXT_REGS.REG(es)); fprintf(stderr, "fs = 0x%04x\n", CONTEXT_REGS.REG(fs)); fprintf(stderr, "gs = 0x%04x\n", CONTEXT_REGS.REG(gs)); fprintf(stderr, "eflags = 0x%08x\n", CONTEXT_REGS.REG(eflags)); fputs("cs:ip = [ ", stderr); p = (unsigned char *)((CONTEXT_REGS.REG(cs) << 4) + (CONTEXT_REGS.REG(eip) & 0xffff)); for (i = 0; i < 16; ++i) fprintf(stderr, "%02x ", (unsigned int)p[i]); fputs("]\n", stderr); #endif } #if defined(__linux__) static int run_vm86(void) { unsigned int vret; while (1) { vret = lrmi_vm86(&context.vm); if (VM86_TYPE(vret) == VM86_INTx) { unsigned int v = VM86_ARG(vret); if (v == RETURN_TO_32_INT) return 1; fprintf(stderr, "Calling INT 0x%X (%04X:%04X)\n", v, get_int_seg(v), get_int_off(v)); fprintf(stderr, " EAX is 0x%lX\n", CONTEXT_REGS.REG(eax)); pushw(CONTEXT_REGS.REG(eflags)); pushw(CONTEXT_REGS.REG(cs)); pushw(CONTEXT_REGS.REG(eip)); CONTEXT_REGS.REG(cs) = get_int_seg(v); CONTEXT_REGS.REG(eip) = get_int_off(v); CONTEXT_REGS.REG(eflags) &= ~(VIF_MASK | TF_MASK); continue; } if (VM86_TYPE(vret) != VM86_UNKNOWN) break; if (!emulate()) break; } debug_info(vret); return 0; } #elif defined(__NetBSD__) || defined(__FreeBSD__) #if defined(__NetBSD__) static void vm86_callback(int sig, int code, struct sigcontext *sc) { /* Sync our context with what the kernel develivered to us. */ memcpy(&CONTEXT_REGS, sc, sizeof(*sc)); switch (VM86_TYPE(code)) { case VM86_INTx: { unsigned int v = VM86_ARG(code); if (v == RETURN_TO_32_INT) { context.success = 1; longjmp(context.env, 1); } pushw(CONTEXT_REGS.REG(eflags)); pushw(CONTEXT_REGS.REG(cs)); pushw(CONTEXT_REGS.REG(eip)); CONTEXT_REGS.REG(cs) = get_int_seg(v); CONTEXT_REGS.REG(eip) = get_int_off(v); CONTEXT_REGS.REG(eflags) &= ~(VIF_MASK | TF_MASK); break; } case VM86_UNKNOWN: if (emulate() == 0) { context.success = 0; context.vret = code; longjmp(context.env, 1); } break; default: context.success = 0; context.vret = code; longjmp(context.env, 1); return; } /* ...and sync our context back to the kernel. */ memcpy(sc, &CONTEXT_REGS, sizeof(*sc)); } #elif defined(__FreeBSD__) static void vm86_callback(int sig, int code, struct sigcontext *sc) { unsigned char *addr; /* Sync our context with what the kernel develivered to us. */ memcpy(&CONTEXT_REGS, sc, sizeof(*sc)); if (code) { /* XXX probably need to call original signal handler here */ context.success = 0; context.vret = code; longjmp(context.env, 1); } addr = (unsigned char *)((CONTEXT_REGS.REG(cs) << 4) + CONTEXT_REGS.REG(eip)); if (addr[0] == 0xcd) { /* int opcode */ if (addr[1] == RETURN_TO_32_INT) { context.success = 1; longjmp(context.env, 1); } pushw(CONTEXT_REGS.REG(eflags)); pushw(CONTEXT_REGS.REG(cs)); pushw(CONTEXT_REGS.REG(eip)); CONTEXT_REGS.REG(cs) = get_int_seg(addr[1]); CONTEXT_REGS.REG(eip) = get_int_off(addr[1]); CONTEXT_REGS.REG(eflags) &= ~(VIF_MASK | TF_MASK); } else { if (emulate() == 0) { context.success = 0; longjmp(context.env, 1); } } /* ...and sync our context back to the kernel. */ memcpy(sc, &CONTEXT_REGS, sizeof(*sc)); } #endif /* __FreeBSD__ */ static int run_vm86(void) { if (context.old_sighandler) { #ifdef LRMI_DEBUG fprintf(stderr, "run_vm86: callback already installed\n"); #endif return (0); } #if defined(__NetBSD__) context.old_sighandler = signal(SIGURG, (void (*)(int))vm86_callback); #elif defined(__FreeBSD__) context.old_sighandler = signal(SIGBUS, (void (*)(int))vm86_callback); #endif if (context.old_sighandler == (void *)-1) { context.old_sighandler = NULL; #ifdef LRMI_DEBUG fprintf(stderr, "run_vm86: cannot install callback\n"); #endif return (0); } if (setjmp(context.env)) { #if defined(__NetBSD__) (void) signal(SIGURG, context.old_sighandler); #elif defined(__FreeBSD__) (void) signal(SIGBUS, context.old_sighandler); #endif context.old_sighandler = NULL; if (context.success) return (1); debug_info(context.vret); return (0); } #if defined(__NetBSD__) if (i386_vm86(&context.vm) == -1) return (0); #elif defined(__FreeBSD__) if (i386_vm86(VM86_INIT, &context.vm.init)) return 0; CONTEXT_REGS.REG(eflags) |= PSL_VM | PSL_VIF; sigreturn(&context.vm.uc); #endif /* __FreeBSD__ */ /* NOTREACHED */ return (0); } #endif /* __NetBSD__ || __FreeBSD__ */ int LRMI_call(struct LRMI_regs *r) { unsigned int vret; memset(&CONTEXT_REGS, 0, sizeof(CONTEXT_REGS)); set_regs(r); CONTEXT_REGS.REG(cs) = r->cs; CONTEXT_REGS.REG(eip) = r->ip; if (r->ss == 0 && r->sp == 0) { CONTEXT_REGS.REG(ss) = context.stack_seg; CONTEXT_REGS.REG(esp) = context.stack_off; } else { CONTEXT_REGS.REG(ss) = r->ss; CONTEXT_REGS.REG(esp) = r->sp; } pushw(context.ret_seg); pushw(context.ret_off); vret = run_vm86(); get_regs(r); return vret; } int LRMI_int(int i, struct LRMI_regs *r) { unsigned int vret; unsigned int seg, off; seg = get_int_seg(i); off = get_int_off(i); /* If the interrupt is in regular memory, it's probably still pointing at a dos TSR (which is now gone). */ if (seg < 0xa000 || (seg << 4) + off >= 0x100000) { #ifdef LRMI_DEBUG fprintf(stderr, "Int 0x%x is not in rom (%04x:%04x)\n", i, seg, off); #endif return 0; } memset(&CONTEXT_REGS, 0, sizeof(CONTEXT_REGS)); set_regs(r); CONTEXT_REGS.REG(cs) = seg; CONTEXT_REGS.REG(eip) = off; if (r->ss == 0 && r->sp == 0) { CONTEXT_REGS.REG(ss) = context.stack_seg; CONTEXT_REGS.REG(esp) = context.stack_off; } else { CONTEXT_REGS.REG(ss) = r->ss; CONTEXT_REGS.REG(esp) = r->sp; } pushw(DEFAULT_VM86_FLAGS); pushw(context.ret_seg); pushw(context.ret_off); vret = run_vm86(); get_regs(r); return vret; } size_t LRMI_base_addr(void) { return 0; } xresprobe-0.4.24ubuntu9/ddcprobe/x86-common.h0000644000000000000000000000300710410136571015700 0ustar /* Common routines for x86emu/lrmi interfaces. Taken from lrmi.c. Copyright (C) 1998 by Josh Vanderhoof Copyright (C) 2005 by Jonathan McDowell Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL JOSH VANDERHOOF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include "include/lrmi.h" #define REAL_MEM_BASE ((void *)0x10000) #define REAL_MEM_SIZE 0x40000 #define REAL_MEM_BLOCKS 0x100 void *LRMI_alloc_real(int size); void LRMI_free_real(void *m); int LRMI_common_init(void); xresprobe-0.4.24ubuntu9/ddcprobe/vbe.h0000644000000000000000000000474610214367723014563 0ustar #ifndef VBE_H #define VBE_H #ident "$Id: vbe.h,v 1.3 2003/02/11 15:33:03 notting Exp $" #include "common.h" #include /* Stuff returned by int 0x10, function 0x4f, subfunction 0x01. */ struct vbe_mode_info { /* required for all VESA versions */ struct { /* VBE 1.0+ */ u_int16_t supported: 1; u_int16_t optional_info_available: 1; u_int16_t bios_output_supported: 1; u_int16_t color: 1; u_int16_t graphics: 1; /* VBE 2.0+ */ u_int16_t not_vga_compatible: 1; u_int16_t not_bank_switched: 1; u_int16_t lfb: 1; /* VBE 1.0+ */ u_int16_t unknown: 1; u_int16_t must_enable_directaccess_in_10: 1; } mode_attributes; struct { unsigned char exists: 1; unsigned char readable: 1; unsigned char writeable: 1; unsigned char reserved: 5; } windowa_attributes, windowb_attributes; u_int16_t window_granularity; u_int16_t window_size; u_int16_t windowa_start_segment, windowb_start_segment; u_int16_t window_positioning_seg, window_positioning_ofs; u_int16_t bytes_per_scanline; /* optional for VESA 1.0/1.1, required for OEM modes */ u_int16_t w, h; unsigned char cell_width, cell_height; unsigned char memory_planes; unsigned char bpp; unsigned char banks; enum { memory_model_text = 0, memory_model_cga = 1, memory_model_hgc = 2, memory_model_ega16 = 3, memory_model_packed_pixel = 4, memory_model_sequ256 = 5, memory_model_direct_color = 6, memory_model_yuv = 7, } memory_model: 8; unsigned char bank_size; unsigned char image_pages; unsigned char reserved1; /* required for VESA 1.2+ */ unsigned char red_mask, red_field; unsigned char green_mask, green_field; unsigned char blue_mask, blue_field; unsigned char reserved_mask, reserved_field; unsigned char direct_color_mode_info; /* VESA 2.0+ */ u_int32_t linear_buffer_address; u_int32_t offscreen_memory_address; u_int16_t offscreen_memory_size; unsigned char reserved2[206]; } __attribute__ ((packed)); #define VBE_LINEAR_FRAMEBUFFER 0x4000 /* Get information about a particular video mode, bitwise or with VBE_LINEAR_FRAMEBUFFER to check if LFB version is supported. */ struct vbe_mode_info *vbe_get_mode_info(u_int16_t mode); /* Get the current video mode, -1 on error. */ int32_t vbe_get_mode(); /* Set a new video mode, bitwise or with VBE_LINEAR_FRAMEBUFFER. */ void vbe_set_mode(u_int16_t mode); /* Save/restore the SVGA state. Call free() on the state record when done. */ const void *vbe_save_svga_state(); void vbe_restore_svga_state(const void *state); #endif /* VBE_H */ xresprobe-0.4.24ubuntu9/ddcprobe/thunk.c0000644000000000000000000001147110410136571015115 0ustar #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define SHMERRORPTR (pointer)(-1) #define _INT10_PRIVATE #include "include/xf86int10.h" #include "include/x86emu.h" #include "include/xf86x86emu.h" #include "include/lrmi.h" #include "x86-common.h" #define DEBUG #define ALLOC_ENTRIES(x) (V_RAM - 1) #define TRUE 1 #define FALSE 0 #define __BUILDIO(bwl,bw,type) \ static inline void out##bwl##_local(unsigned long port, unsigned type value) { __asm__ __volatile__("out" #bwl " %" #bw "0, %w1" : : "a"(value), "Nd"(port)); \ }\ static inline unsigned type in##bwl##_local(unsigned long port) { \ unsigned type value; \ __asm__ __volatile__("in" #bwl " %w1, %" #bw "0" : "=a"(value) : "Nd"(port)); \ return value; \ }\ __BUILDIO(b,b,char) __BUILDIO(w,w,short) __BUILDIO(l,,int) char *mmap_addr = SHMERRORPTR; void *stack; struct LRMI_regs *regs; void printk(const char *fmt, ...) { va_list argptr; va_start(argptr, fmt); printf(fmt, argptr); va_end(argptr); } u8 read_b(int addr) { return *((char *)mmap_addr + addr); } CARD8 x_inb(CARD16 port) { CARD8 val; val = inb_local(port); return val; } CARD16 x_inw(CARD16 port) { CARD16 val; val = inw_local(port); return val; } CARD32 x_inl(CARD16 port) { CARD32 val; val = inl_local(port); return val; } void x_outb(CARD16 port, CARD8 val) { outb_local(port, val); } void x_outw(CARD16 port, CARD16 val) { outw_local(port, val); } void x_outl(CARD16 port, CARD32 val) { outl_local(port, val); } void pushw(u16 val) { X86_ESP -= 2; MEM_WW(((u32) X86_SS << 4) + X86_SP, val); } static void x86emu_do_int(int num) { u32 eflags; fprintf(stderr, "Calling INT 0x%X (%04X:%04X)\n", num, (read_b((num << 2) + 3) << 8) + read_b((num << 2) + 2), (read_b((num << 2) + 1) << 8) + read_b((num << 2))); fprintf(stderr, " EAX is %X\n", (int) X86_EAX); eflags = X86_EFLAGS; eflags = eflags | X86_IF_MASK; pushw(eflags); pushw(X86_CS); pushw(X86_IP); X86_EFLAGS = X86_EFLAGS & ~(X86_VIF_MASK | X86_TF_MASK); X86_CS = (read_b((num << 2) + 3) << 8) + read_b((num << 2) + 2); X86_IP = (read_b((num << 2) + 1) << 8) + read_b((num << 2)); fprintf(stderr, "Leaving interrupt call.\n"); } int LRMI_init() { int i; static int inited = 0; X86EMU_intrFuncs intFuncs[256]; if (inited == 1) return 1; inited = 1; if (!LRMI_common_init()) return 0; mmap_addr = 0; X86EMU_pioFuncs pioFuncs = { (&x_inb), (&x_inw), (&x_inl), (&x_outb), (&x_outw), (&x_outl) }; X86EMU_setupPioFuncs(&pioFuncs); for (i=0;i<256;i++) intFuncs[i] = x86emu_do_int; X86EMU_setupIntrFuncs(intFuncs); X86_EFLAGS = X86_IF_MASK | X86_IOPL_MASK; /* * Allocate a 64k stack. */ stack = LRMI_alloc_real(64 * 1024); X86_SS = (unsigned int) (stack) >> 4; X86_ESP = 0xFFFE; //X86_EIP = 0x0600; X86_CS = 0x0; /* address of 'hlt' */ //X86_DS = 0x40; /* standard pc ds */ M.mem_size = 1024*1024; M.mem_base = 0; /* M.x86.debug |= DEBUG_MEM_TRACE_F | DEBUG_TRACECALL_F;*/ return 1; } int real_call(struct LRMI_regs *registers) { regs = registers; X86_EAX = registers->eax; X86_EBX = registers->ebx; X86_ECX = registers->ecx; X86_EDX = registers->edx; X86_ESI = registers->esi; X86_EDI = registers->edi; X86_EBP = registers->ebp; X86_EIP = registers->ip; X86_ES = registers->es; X86_FS = registers->fs; X86_GS = registers->gs; X86_CS = registers->cs; if (registers->ss != 0) { X86_SS = registers->ss; } if (registers->ds != 0) { X86_DS = registers->ds; } if (registers->sp != 0) { X86_ESP = registers->sp; } X86EMU_exec(); registers->eax = X86_EAX; registers->ebx = X86_EBX; registers->ecx = X86_ECX; registers->edx = X86_EDX; registers->esi = X86_ESI; registers->edi = X86_EDI; registers->ebp = X86_EBP; registers->es = X86_ES; return 1; } int LRMI_int(int num, struct LRMI_regs *registers) { u32 eflags; eflags = X86_EFLAGS; eflags = eflags | X86_IF_MASK; X86_EFLAGS = X86_EFLAGS & ~(X86_VIF_MASK | X86_TF_MASK | X86_IF_MASK | X86_NT_MASK); X86_SS = (unsigned int) (stack) >> 4; X86_ESP = 0xFFFE; registers->cs = (read_b((num << 2) + 3) << 8) + read_b((num << 2) + 2); registers->ip = (read_b((num << 2) + 1) << 8) + read_b((num << 2)); regs = registers; return real_call(registers); } int LRMI_call(struct LRMI_regs *registers) { // pushw(X86_CS); // pushw(X86_IP); return real_call(registers); } size_t LRMI_base_addr(void) { return (size_t)mmap_addr; } xresprobe-0.4.24ubuntu9/ddcprobe/common.c0000644000000000000000000001556510220413313015253 0ustar #include #include #include #include #include #include #include #include #include #include "vesamode.h" #include "common.h" /* Just read ranges from the EDID. */ void get_edid_ranges(unsigned char *hmin, unsigned char *hmax, unsigned char *vmin, unsigned char *vmax) { struct edid1_info *edid; struct edid_monitor_descriptor *monitor; int i; *hmin = *hmax = *vmin = *vmax = 0; if((edid = get_edid_info()) == NULL) { return; } for(i = 0; i < 4; i++) { monitor = &edid->monitor_details.monitor_descriptor[i]; if(monitor->type == edid_monitor_descriptor_range) { *hmin = monitor->data.range_data.horizontal_min; *hmax = monitor->data.range_data.horizontal_max; *vmin = monitor->data.range_data.vertical_min; *vmax = monitor->data.range_data.vertical_max; } } } static int compare_modelines(const void *m1, const void *m2) { const struct modeline *M1 = (const struct modeline*) m1; const struct modeline *M2 = (const struct modeline*) m2; if(M1->width < M2->width) return -1; if(M1->width > M2->width) return 1; return 0; } struct modeline *get_edid_modelines() { struct edid1_info *edid; struct modeline *ret; char buf[LINE_MAX]; int modeline_count = 0, j; unsigned int i; if((edid = get_edid_info()) == NULL) { return NULL; } memcpy(buf, &edid->established_timings, sizeof(edid->established_timings)); for(i = 0; i < (8 * sizeof(edid->established_timings)); i++) { if(buf[i / 8] & (1 << (i % 8))) { modeline_count++; } } /* Count the number of standard timings. */ for(i = 0; i < 8; i++) { int x, v; x = edid->standard_timing[i].xresolution; v = edid->standard_timing[i].vfreq; if(((edid->standard_timing[i].xresolution & 0x01) != x) && ((edid->standard_timing[i].vfreq & 0x01) != v)) { modeline_count++; } } ret = malloc(sizeof(struct modeline) * (modeline_count + 1)); if(ret == NULL) { return NULL; } memset(ret, 0, sizeof(struct modeline) * (modeline_count + 1)); modeline_count = 0; /* Fill out established timings. */ if(edid->established_timings.timing_720x400_70) { ret[modeline_count].width = 720; ret[modeline_count].height = 400; ret[modeline_count].refresh = 70; modeline_count++; } if(edid->established_timings.timing_720x400_88) { ret[modeline_count].width = 720; ret[modeline_count].height = 400; ret[modeline_count].refresh = 88; modeline_count++; } if(edid->established_timings.timing_640x480_60) { ret[modeline_count].width = 640; ret[modeline_count].height = 480; ret[modeline_count].refresh = 60; modeline_count++; } if(edid->established_timings.timing_640x480_67) { ret[modeline_count].width = 640; ret[modeline_count].height = 480; ret[modeline_count].refresh = 67; modeline_count++; } if(edid->established_timings.timing_640x480_72) { ret[modeline_count].width = 640; ret[modeline_count].height = 480; ret[modeline_count].refresh = 72; modeline_count++; } if(edid->established_timings.timing_640x480_75) { ret[modeline_count].width = 640; ret[modeline_count].height = 480; ret[modeline_count].refresh = 75; modeline_count++; } if(edid->established_timings.timing_800x600_56) { ret[modeline_count].width = 800; ret[modeline_count].height = 600; ret[modeline_count].refresh = 56; modeline_count++; } if(edid->established_timings.timing_800x600_60) { ret[modeline_count].width = 800; ret[modeline_count].height = 600; ret[modeline_count].refresh = 60; modeline_count++; } if(edid->established_timings.timing_800x600_72) { ret[modeline_count].width = 800; ret[modeline_count].height = 600; ret[modeline_count].refresh = 72; modeline_count++; } if(edid->established_timings.timing_800x600_75) { ret[modeline_count].width = 800; ret[modeline_count].height = 600; ret[modeline_count].refresh = 75; modeline_count++; } if(edid->established_timings.timing_832x624_75) { ret[modeline_count].width = 832; ret[modeline_count].height = 624; ret[modeline_count].refresh = 75; modeline_count++; } if(edid->established_timings.timing_1024x768_87i) { ret[modeline_count].width = 1024; ret[modeline_count].height = 768; ret[modeline_count].refresh = 87; ret[modeline_count].interlaced = 1; modeline_count++; } if(edid->established_timings.timing_1024x768_60){ ret[modeline_count].width = 1024; ret[modeline_count].height = 768; ret[modeline_count].refresh = 60; modeline_count++; } if(edid->established_timings.timing_1024x768_70){ ret[modeline_count].width = 1024; ret[modeline_count].height = 768; ret[modeline_count].refresh = 70; modeline_count++; } if(edid->established_timings.timing_1024x768_75){ ret[modeline_count].width = 1024; ret[modeline_count].height = 768; ret[modeline_count].refresh = 75; modeline_count++; } if(edid->established_timings.timing_1280x1024_75) { ret[modeline_count].width = 1280; ret[modeline_count].height = 1024; ret[modeline_count].refresh = 75; modeline_count++; } /* Add in standard timings. */ for(i = 0; i < 8; i++) { float aspect = 1; int x, v; x = edid->standard_timing[i].xresolution; v = edid->standard_timing[i].vfreq; if(((edid->standard_timing[i].xresolution & 0x01) != x) && ((edid->standard_timing[i].vfreq & 0x01) != v)) { switch(edid->standard_timing[i].aspect) { case aspect_75: aspect = 0.7500; break; case aspect_8: aspect = 0.8000; break; case aspect_5625: aspect = 0.5625; break; default: aspect = 1; break; } x = (edid->standard_timing[i].xresolution + 31) * 8; ret[modeline_count].width = x; ret[modeline_count].height = x * aspect; ret[modeline_count].refresh = edid->standard_timing[i].vfreq + 60; modeline_count++; } } /* Now tack on any matching modelines. */ for(i = 0; ret[i].refresh != 0; i++) { struct vesa_timing_t *t = NULL; for(j = 0; known_vesa_timings[j].refresh != 0; j++) { t = &known_vesa_timings[j]; if(ret[i].width == t->x) if(ret[i].height == t->y) if(ret[i].refresh == t->refresh) { snprintf(buf, sizeof(buf), "ModeLine \"%dx%d\"\t%6.2f " "%4d %4d %4d %4d %4d %4d %4d %4d %s %s" , t->x, t->y, t->dotclock, t->timings[0], t->timings[0] + t->timings[1], t->timings[0] + t->timings[1] + t->timings[2], t->timings[0] + t->timings[1] + t->timings[2] + t->timings[3], t->timings[4], t->timings[4] + t->timings[5], t->timings[4] + t->timings[5] + t->timings[6], t->timings[4] + t->timings[5] + t->timings[6] + t->timings[7], t->hsync == hsync_pos ? "+hsync" : "-hsync", t->vsync == vsync_pos ? "+vsync" : "-vsync"); ret[i].modeline = strdup(buf); ret[i].hfreq = t->hfreq; ret[i].vfreq = t->vfreq; } } } modeline_count = 0; for(i = 0; ret[i].refresh != 0; i++) { modeline_count++; } qsort(ret, modeline_count, sizeof(ret[0]), compare_modelines); return ret; } xresprobe-0.4.24ubuntu9/ddcprobe/minifind.h0000644000000000000000000000163410214367723015575 0ustar /* minifind.h * * Copyright (c) 2002 Terra Soft Solutions, Inc. * Written by Dan Burcaw * * This software may be freely redistributed under the terms of the GNU * library public license. * * You should have received a copy of the GNU Library Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * */ #ifndef MINIFIND_H #define MINIFIND_H #include #include #include #include #include #include #include struct pathNode { char *path; struct pathNode *next; }; struct findNode { struct pathNode *result; struct pathNode *exclude; }; void insert_node(struct pathNode *n, char *path); char *stripLastChar(char *in); char *minifind(char *dir, char *search, struct findNode *list); #endif /* MINIFIND_H */ xresprobe-0.4.24ubuntu9/ddcprobe/common.h0000644000000000000000000001644010410136571015262 0ustar #ifndef COMMON_H #define COMMON_H #include /* This is in common, because PPC uses it for video memory info */ /* Record returned by int 0x10, function 0x4f, subfunction 0x00. */ struct vbe_info { unsigned char signature[4]; unsigned char version[2]; struct { u_int16_t ofs; u_int16_t seg; } oem_name_addr; u_int32_t capabilities; struct { u_int16_t ofs; u_int16_t seg; } mode_list_addr; u_int16_t memory_size; /* VESA 3.0+ */ u_int16_t vbe_revision; struct { u_int16_t ofs; u_int16_t seg; } vendor_name_addr; struct { u_int16_t ofs; u_int16_t seg; } product_name_addr; struct { u_int16_t ofs; u_int16_t seg; } product_revision_addr; char reserved1[222]; char reserved2[256]; } __attribute__ ((packed)); struct vbe_parent_info { struct vbe_info vbe; const char *oem_name_string; u_int16_t *mode_list_list; const char *vendor_name_string; const char *product_name_string; const char *product_revision_string; }; /* Modeline information used by XFree86. */ struct modeline { u_int16_t width, height; unsigned char interlaced; float refresh; char *modeline; float hfreq, vfreq, pixel_clock; }; /* Aspect ratios used in EDID info. */ enum edid_aspect { aspect_unknown = 0, aspect_75, aspect_8, aspect_5625, }; /* Detailed timing information used in EDID v1.x */ struct edid_detailed_timing { u_int16_t pixel_clock; #define EDID_DETAILED_TIMING_PIXEL_CLOCK(_x) \ ((_x).pixel_clock * 10000) unsigned char horizontal_active; unsigned char horizontal_blanking; unsigned char horizontal_active_hi: 4; unsigned char horizontal_blanking_hi: 4; #define EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(_x) \ (((_x).horizontal_active_hi << 8) + (_x).horizontal_active) #define EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(_x) \ (((_x).horizontal_blanking_hi << 8) + (_x).horizontal_blanking) unsigned char vertical_active; unsigned char vertical_blanking; unsigned char vertical_active_hi: 4; unsigned char vertical_blanking_hi: 4; #define EDID_DETAILED_TIMING_VERTICAL_ACTIVE(_x) \ (((_x).vertical_active_hi << 8) + (_x).vertical_active) #define EDID_DETAILED_TIMING_VERTICAL_BLANKING(_x) \ (((_x).vertical_blanking_hi << 8) + (_x).vertical_blanking) unsigned char hsync_offset; unsigned char hsync_pulse_width; unsigned char vsync_offset: 4; unsigned char vsync_pulse_width: 4; unsigned char hsync_offset_hi: 2; unsigned char hsync_pulse_width_hi: 2; unsigned char vsync_offset_hi: 2; unsigned char vsync_pulse_width_hi: 2; #define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \ (((_x).hsync_offset_hi << 8) + (_x).hsync_offset) #define EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(_x) \ (((_x).hsync_pulse_width_hi << 8) + (_x).hsync_pulse_width) #define EDID_DETAILED_TIMING_VSYNC_OFFSET(_x) \ (((_x).vsync_offset_hi << 4) + (_x).vsync_offset) #define EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(_x) \ (((_x).vsync_pulse_width_hi << 4) + (_x).vsync_pulse_width) unsigned char himage_size; unsigned char vimage_size; unsigned char himage_size_hi: 4; unsigned char vimage_size_hi: 4; #define EDID_DETAILED_TIMING_HIMAGE_SIZE(_x) \ (((_x).himage_size_hi << 8) + (_x).himage_size) #define EDID_DETAILED_TIMING_VIMAGE_SIZE(_x) \ (((_x).vimage_size_hi << 8) + (_x).vimage_size) unsigned char hborder; unsigned char vborder; struct { unsigned char interlaced: 1; unsigned char stereo: 2; unsigned char digital_composite: 2; unsigned char variant: 2; unsigned char zero: 1; } flags __attribute__ ((packed)); } __attribute__ ((packed)); enum { edid_monitor_descriptor_serial = 0xff, edid_monitor_descriptor_ascii = 0xfe, edid_monitor_descriptor_range = 0xfd, edid_monitor_descriptor_name = 0xfc, } edid_monitor_descriptor_types; struct edid_monitor_descriptor { u_int16_t zero_flag_1; unsigned char zero_flag_2; unsigned char type; unsigned char zero_flag_3; union { char string[13]; struct { unsigned char vertical_min; unsigned char vertical_max; unsigned char horizontal_min; unsigned char horizontal_max; unsigned char pixel_clock_max; unsigned char gtf_data[8]; } range_data; } data; } __attribute__ ((packed)); struct edid1_info { unsigned char header[8]; struct { #if __BYTE_ORDER == __LITTLE_ENDIAN u_int16_t char3: 5; u_int16_t char2: 5; u_int16_t char1: 5; u_int16_t zero: 1; #else /* __BIG_ENDIAN */ u_int16_t zero: 1; u_int16_t char1: 5; u_int16_t char2: 5; u_int16_t char3: 5; #endif } manufacturer_name __attribute__ ((packed)); u_int16_t product_code; u_int32_t serial_number; unsigned char week; unsigned char year; unsigned char version; unsigned char revision; struct { unsigned char digital: 1; unsigned char separate_sync: 1; unsigned char composite_sync: 1; unsigned char sync_on_green: 1; unsigned char unused: 2; unsigned char voltage_level: 2; } video_input_definition __attribute__ ((packed)); unsigned char max_size_horizontal; unsigned char max_size_vertical; unsigned char gamma; struct { unsigned char unused1: 3; unsigned char rgb: 1; unsigned char unused2: 1; unsigned char active_off: 1; unsigned char suspend: 1; unsigned char standby: 1; } feature_support __attribute__ ((packed)); unsigned char color_characteristics[10]; struct { unsigned char timing_720x400_70: 1; unsigned char timing_720x400_88: 1; unsigned char timing_640x480_60: 1; unsigned char timing_640x480_67: 1; unsigned char timing_640x480_72: 1; unsigned char timing_640x480_75: 1; unsigned char timing_800x600_56: 1; unsigned char timing_800x600_60: 1; unsigned char timing_800x600_72: 1; unsigned char timing_800x600_75: 1; unsigned char timing_832x624_75: 1; unsigned char timing_1024x768_87i: 1; unsigned char timing_1024x768_60: 1; unsigned char timing_1024x768_70: 1; unsigned char timing_1024x768_75: 1; unsigned char timing_1280x1024_75: 1; } established_timings __attribute__ ((packed)); struct { unsigned char timing_1152x870_75: 1; unsigned char reserved: 7; } manufacturer_timings __attribute__ ((packed)); struct { #if __BYTE_ORDER == __LITTLE_ENDIAN u_int16_t xresolution: 8; u_int16_t vfreq: 6; u_int16_t aspect: 2; #else /* __BIG_ENDIAN */ u_int16_t aspect: 2; u_int16_t vfreq: 6; u_int16_t xresolution: 8; #endif } standard_timing[8] __attribute__ ((packed)); union { unsigned char detailed_timing[72]; #if 0 struct edid_detailed_timing detailed_timing[4]; #endif struct edid_monitor_descriptor monitor_descriptor[4]; } monitor_details __attribute__ ((packed)); unsigned char extension_flag; unsigned char checksum; unsigned char padding[128]; } __attribute__ ((packed)); /* Check if EDID reads are supported, and do them. */ int get_edid_supported(); struct edid1_info *get_edid_info(); /* Get the ranges of values suitable for the attached monitor. */ void get_edid_ranges(unsigned char *hmin, unsigned char *hmax, unsigned char *vmin, unsigned char *vmax); /* Get a list of modelines that will work with this monitor. */ struct modeline *get_edid_modelines(); /* Get VESA information. */ struct vbe_parent_info *vbe_get_vbe_info(); #endif /* COMMON_H */ xresprobe-0.4.24ubuntu9/ddcprobe/vesamode.c0000644000000000000000000001323510220413313015556 0ustar #include "vesamode.h" #ident "$Id: vesamode.c,v 1.3 1999/07/22 04:53:06 nalin Exp $" /* Known standard VESA modes. */ struct vesa_mode_t known_vesa_modes[] = { /* VESA 1.0/1.1 ? */ {0x100, 640, 400, 256, "640x400x256", 0}, {0x101, 640, 480, 256, "640x480x256", 0}, {0x102, 800, 600, 16, "800x600x16", 0}, {0x103, 800, 600, 256, "800x600x256", 0}, {0x104, 1024, 768, 16, "1024x768x16", 0}, {0x105, 1024, 768, 256, "1024x768x256", 0}, {0x106, 1280, 1024, 16, "1280x1024x16", 0}, {0x107, 1280, 1024, 256,"1280x1024x256", 0}, {0x108, 80, 60, 16, "80x60 (text)", 0}, {0x109, 132, 25, 16, "132x25 (text)", 0}, {0x10a, 132, 43, 16, "132x43 (text)", 0}, {0x10b, 132, 50, 16, "132x50 (text)", 0}, {0x10c, 132, 60, 16, "132x60 (text)", 0}, /* VESA 1.2+ */ {0x10d, 320, 200, 32768, "320x200x32k", 0}, {0x10e, 320, 200, 65536, "320x200x64k", 0}, {0x10f, 320, 200, 16777216, "320x200x16m", 0}, {0x110, 640, 480, 32768, "640x480x32k", 0}, {0x111, 640, 480, 65536, "640x480x64k", 0}, {0x112, 640, 480, 16777216, "640x480x16m", 0}, {0x113, 800, 600, 32768, "800x600x32k", 0}, {0x114, 800, 600, 65536, "800x600x64k", 0}, {0x115, 800, 600, 16777216, "800x600x16m", 0}, {0x116, 1024, 768, 32768, "1024x768x32k", 0}, {0x117, 1024, 768, 65536, "1024x768x64k", 0}, {0x118, 1024, 768, 16777216, "1024x768x16m", 0}, {0x119, 1280, 1024, 32768, "1280x1024x32k", 0}, {0x11a, 1280, 1024, 65536, "1280x1024x64k", 0}, {0x11b, 1280, 1024, 16777216, "1280x1024x16m", 0}, /* VESA 2.0+ */ {0x120, 1600, 1200, 256, "1600x1200x256", 0}, {0x121, 1600, 1200, 32768, "1600x1200x32k", 0}, {0x122, 1600, 1200, 65536, "1600x1200x64k", 0}, { 0, 0, 0, 0, "", 0}, }; struct vesa_timing_t known_vesa_timings[] = { /* Source: VESA Monitor Timing Specifications 1.0 rev 0.8 */ { 640, 350, 85, 31.500, { 640, 32, 64, 96, 350,32, 3, 60}, hsync_pos, vsync_neg, 37.861, 85.080}, { 640, 400, 85, 31.500, { 640, 32, 64, 96, 400, 1, 3, 41}, hsync_neg, vsync_pos, 37.861, 85.080}, { 720, 400, 85, 35.500, { 720, 36, 72, 108, 400, 1, 3, 42}, hsync_neg, vsync_pos, 37.861, 85.080}, { 640, 480, 60, 25.175, { 640, 8, 96, 40, 480, 2, 2, 25}, hsync_neg, vsync_neg, 31.469, 59.940}, { 640, 480, 72, 31.500, { 640, 16, 40, 120, 480, 1, 3, 20}, hsync_neg, vsync_neg, 37.861, 72.809}, { 640, 480, 75, 31.500, { 640, 16, 64, 120, 480, 1, 3, 16}, hsync_neg, vsync_neg, 37.500, 75.000}, { 640, 480, 85, 36.000, { 640, 56, 56, 80, 480, 1, 3, 25}, hsync_neg, vsync_neg, 43.269, 85.008}, { 800, 600, 56, 36.000, { 800, 24, 72, 128, 600, 1, 2, 22}, hsync_pos, vsync_pos, 35.156, 56.250}, { 800, 600, 60, 40.000, { 800, 40, 128, 88, 600, 1, 4, 23}, hsync_pos, vsync_pos, 37.879, 60.317}, { 800, 600, 72, 50.000, { 800, 56, 120, 64, 600,37, 6, 23}, hsync_pos, vsync_pos, 48.077, 72.188}, { 800, 600, 75, 49.500, { 800, 16, 80, 160, 600, 1, 3, 21}, hsync_pos, vsync_pos, 46.875, 75.000}, { 800, 600, 85, 56.250, { 800, 32, 64, 152, 600, 1, 3, 27}, hsync_pos, vsync_pos, 53.674, 85.061}, {1024, 768, 43, 44.900, {1024, 8, 176, 56, 768, 0, 4, 20}, hsync_pos, vsync_pos, 35.522, 86.957}, {1024, 768, 60, 65.000, {1024, 24, 136, 160, 768, 3, 6, 29}, hsync_neg, vsync_neg, 48.363, 60.004}, {1024, 768, 70, 75.000, {1024, 24, 136, 144, 768, 3, 6, 29}, hsync_neg, vsync_neg, 56.476, 70.069}, {1024, 768, 75, 78.750, {1024, 16, 96, 176, 768, 1, 3, 28}, hsync_pos, vsync_pos, 60.023, 75.029}, {1024, 768, 85, 94.500, {1024, 48, 96, 208, 768, 1, 3, 36}, hsync_pos, vsync_pos, 68.677, 84.997}, {1152, 864, 70, 94.200, {1152, 32, 96, 192, 864, 1, 3, 46}, hsync_pos, vsync_pos, 0.000, 0.000}, {1152, 864, 75, 108.000, {1152, 64, 128, 256, 864, 1, 3, 32}, hsync_pos, vsync_pos, 67.500, 75.000}, {1152, 864, 85, 121.500, {1152, 64, 128, 224, 864, 1, 3, 43}, hsync_pos, vsync_pos, 0.000, 0.000}, {1280, 960, 60, 108.000, {1280, 96, 112, 312, 960, 1, 3, 36}, hsync_pos, vsync_pos, 60.000, 60.000}, {1280, 960, 85, 148.500, {1280, 64, 160, 224, 960, 1, 3, 47}, hsync_pos, vsync_pos, 85.398, 85.002}, {1280, 1024, 60, 108.000, {1280, 48, 112, 248, 1024, 1, 3, 38}, hsync_pos, vsync_pos, 63.981, 60.020}, {1280, 1024, 75, 135.000, {1280, 16, 144, 248, 1024, 1, 3, 38}, hsync_pos, vsync_pos, 79.976, 75.025}, {1280, 1024, 85, 157.500, {1280, 64, 160, 224, 1024, 1, 3, 44}, hsync_pos, vsync_pos, 91.146, 85.024}, {1600, 1200, 60, 162.000, {1600, 64, 192, 304, 1200, 1, 3, 46}, hsync_pos, vsync_pos, 75.000, 60.000}, {1600, 1200, 65, 175.500, {1600, 64, 192, 304, 1200, 1, 3, 46}, hsync_pos, vsync_pos, 81.250, 65.000}, {1600, 1200, 70, 189.000, {1600, 64, 192, 304, 1200, 1, 3, 46}, hsync_pos, vsync_pos, 87.500, 70.000}, {1600, 1200, 75, 202.500, {1600, 64, 192, 304, 1200, 1, 3, 46}, hsync_pos, vsync_pos, 93.750, 75.000}, {1600, 1200, 85, 229.500, {1600, 64, 192, 304, 1200, 1, 3, 46}, hsync_pos, vsync_pos, 106.250, 85.000}, {1792, 1344, 60, 204.750, {1792,128, 200, 328, 1344, 1, 3, 46}, hsync_neg, vsync_pos, 83.640, 60.000}, {1792, 1344, 75, 261.000, {1792, 96, 216, 352, 1344, 1, 3, 69}, hsync_neg, vsync_pos, 106.270, 74.997}, {1856, 1392, 60, 218.250, {1856, 96, 224, 352, 1392, 1, 3, 43}, hsync_neg, vsync_pos, 86.333, 59.995}, {1856, 1392, 75, 288.000, {1856,128, 224, 352, 1392, 1, 3,104}, hsync_neg, vsync_pos, 112.500, 75.000}, {1920, 1440, 60, 234.000, {1920,128, 208, 344, 1440, 1, 3, 56}, hsync_neg, vsync_pos, 90.000, 60.000}, {1920, 1440, 75, 297.000, {1920,144, 224, 352, 1440, 1, 3, 56}, hsync_neg, vsync_pos, 112.500, 75.000}, { 0, 0, 0, 0.000, { 0, 0, 0, 0, 0, 0, 0, 0}, 000000000, 000000000, 0.000, 0.000}, }; xresprobe-0.4.24ubuntu9/ddcprobe/foo0000644000000000000000000000005710410136571014324 0ustar 1280x1200 1280x1000 1280x800 1000x800 1000x600 xresprobe-0.4.24ubuntu9/ddcprobe/bioscall.h0000644000000000000000000000163010214367723015564 0ustar #ifndef bioscall_h #define bioscall_h /* Print some of the interesting parts of a vm86_regs structure. */ void dump_regs(struct vm86_regs *regs); /* Call vm86 using the given memory block, stopping if we break at a given address. */ void do_vm86(struct vm86_struct *vm, char *memory, unsigned stop_eip); /* Memory-map a megabyte at address 0, and copy the kernel's low megabyte into the memory block, returning the result. */ unsigned char *vm86_ram_alloc(); void vm86_ram_free(unsigned char *ram); /* Handle everything, using the memory mapped at address 0. The code that makes the actual code to the bios is stored at segment BIOSCALL_START_SEG, offset BIOSCALL_START_OFS, so expect that area to be destroyed if you use it. */ #define BIOSCALL_START_SEG 0x8000 #define BIOSCALL_START_OFS 0x0000 void bioscall(unsigned char int_no, struct vm86_regs *regs, unsigned char *mem); #endif /* bioscall_h */ xresprobe-0.4.24ubuntu9/ddcprobe/README0000644000000000000000000000060710214367723014506 0ustar This is some VBE/DDC stuff. It makes calls to the VESA extensions in the BIOS using a slightly modified version of Josh Vanderhoof's LRMI 0.6, and generally requires a 2.2 or newer kernel. The idea for reading EDID data from the BIOS came from Matt Wilson , as well as several ideas about better ways to lay out data structure declarations. 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You can do so by permitting redistribution under these terms (or, alternatively, under the terms of the ordinary General Public License). To apply these terms, attach the following notices to the library. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This library is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with this library; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Also add information on how to contact you by electronic and paper mail. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the library, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the library `Frob' (a library for tweaking knobs) written by James Random Hacker. , 1 April 1990 Ty Coon, President of Vice That's all there is to it! xresprobe-0.4.24ubuntu9/ddcprobe/include/0000755000000000000000000000000010415741443015244 5ustar xresprobe-0.4.24ubuntu9/ddcprobe/include/xf86int10.h0000644000000000000000000001473110410136571017065 0ustar /* $XFree86: xc/programs/Xserver/hw/xfree86/int10/xf86int10.h,v 1.23 2002/04/04 14:05:51 eich Exp $ */ /* * XFree86 int10 module * execute BIOS int 10h calls in x86 real mode environment * Copyright 1999 Egbert Eich */ #ifndef _XF86INT10_H #define _XF86INT10_H #define SEG_ADDR(x) (((x) >> 4) & 0x00F000) #define SEG_OFF(x) ((x) & 0x0FFFF) #define SET_BIOS_SCRATCH 0x1 #define RESTORE_BIOS_SCRATCH 0x2 #define CARD8 unsigned char #define CARD16 unsigned short #define CARD32 unsigned long #define pointer void * #define IOADDRESS void * #define Bool int #define X86_TF_MASK 0x00000100 #define X86_IF_MASK 0x00000200 #define X86_IOPL_MASK 0x00003000 #define X86_NT_MASK 0x00004000 #define X86_VM_MASK 0x00020000 #define X86_AC_MASK 0x00040000 #define X86_VIF_MASK 0x00080000 /* virtual interrupt flag */ #define X86_VIP_MASK 0x00100000 /* virtual interrupt pending */ #define X86_ID_MASK 0x00200000 /* int10 info structure */ typedef struct { int entityIndex; int scrnIndex; pointer cpuRegs; CARD16 BIOSseg; CARD16 inb40time; char * BIOSScratch; int Flags; pointer private; struct _int10Mem* mem; int num; int ax; int bx; int cx; int dx; int si; int di; int es; int bp; int flags; int stackseg; //PCITAG Tag; IOADDRESS ioBase; } xf86Int10InfoRec, *xf86Int10InfoPtr; typedef struct _int10Mem { CARD8(*rb)(xf86Int10InfoPtr, int); CARD16(*rw)(xf86Int10InfoPtr, int); CARD32(*rl)(xf86Int10InfoPtr, int); void(*wb)(xf86Int10InfoPtr, int, CARD8); void(*ww)(xf86Int10InfoPtr, int, CARD16); void(*wl)(xf86Int10InfoPtr, int, CARD32); } int10MemRec, *int10MemPtr; typedef struct { CARD8 save_msr; CARD8 save_pos102; CARD8 save_vse; CARD8 save_46e8; } legacyVGARec, *legacyVGAPtr; //typedef struct { //BusType bus; //union { //struct { //int bus; //int dev; //int func; ////} pci; //int legacy; //} location; ////} xf86int10BiosLocation, *xf86int10BiosLocationPtr; /* OS dependent functions */ xf86Int10InfoPtr xf86InitInt10(int entityIndex); xf86Int10InfoPtr xf86ExtendedInitInt10(int entityIndex, int Flags); void xf86FreeInt10(xf86Int10InfoPtr pInt); void *xf86Int10AllocPages(xf86Int10InfoPtr pInt, int num, int *off); void xf86Int10FreePages(xf86Int10InfoPtr pInt, void *pbase, int num); pointer xf86int10Addr(xf86Int10InfoPtr pInt, CARD32 addr); /* x86 executor related functions */ void xf86ExecX86int10(xf86Int10InfoPtr pInt); #ifdef _INT10_PRIVATE #define I_S_DEFAULT_INT_VECT 0xFF065 #define SYS_SIZE 0x100000 #define SYS_BIOS 0xF0000 #if 1 #define BIOS_SIZE 0x10000 #else /* a bug in DGUX requires this - let's try it */ #define BIOS_SIZE (0x10000 - 1) #endif #define LOW_PAGE_SIZE 0x600 #define V_RAM 0xA0000 #define VRAM_SIZE 0x20000 #define V_BIOS_SIZE 0x10000 #define V_BIOS 0xC0000 #define BIOS_SCRATCH_OFF 0x449 #define BIOS_SCRATCH_END 0x466 #define BIOS_SCRATCH_LEN (BIOS_SCRATCH_END - BIOS_SCRATCH_OFF + 1) #define HIGH_MEM V_BIOS #define HIGH_MEM_SIZE (SYS_BIOS - HIGH_MEM) #define SEG_ADR(type, seg, reg) type((seg << 4) + (X86_##reg)) #define SEG_EADR(type, seg, reg) type((seg << 4) + (X86_E##reg)) #define X86_TF_MASK 0x00000100 #define X86_IF_MASK 0x00000200 #define X86_IOPL_MASK 0x00003000 #define X86_NT_MASK 0x00004000 #define X86_VM_MASK 0x00020000 #define X86_AC_MASK 0x00040000 #define X86_VIF_MASK 0x00080000 /* virtual interrupt flag */ #define X86_VIP_MASK 0x00100000 /* virtual interrupt pending */ #define X86_ID_MASK 0x00200000 #define MEM_RB(name, addr) (*name->mem->rb)(name, addr) #define MEM_RW(name, addr) (*name->mem->rw)(name, addr) #define MEM_RL(name, addr) (*name->mem->rl)(name, addr) #define MEM_WB(name, addr, val) (*name->mem->wb)(name, addr, val) #define MEM_WW(addr, val) wrw(addr, val) #define MEM_WL(name, addr, val) (*name->mem->wl)(name, addr, val) /* OS dependent functions */ Bool MapCurrentInt10(xf86Int10InfoPtr pInt); /* x86 executor related functions */ Bool xf86Int10ExecSetup(xf86Int10InfoPtr pInt); /* int.c */ extern xf86Int10InfoPtr Int10Current; int int_handler(xf86Int10InfoPtr pInt); /* helper_exec.c */ int setup_int(xf86Int10InfoPtr pInt); void finish_int(xf86Int10InfoPtr, int sig); CARD32 getIntVect(xf86Int10InfoPtr pInt, int num); void pushw(CARD16 val); int run_bios_int(int num, xf86Int10InfoPtr pInt); void dump_code(xf86Int10InfoPtr pInt); void dump_registers(xf86Int10InfoPtr pInt); void stack_trace(xf86Int10InfoPtr pInt); xf86Int10InfoPtr getInt10Rec(int entityIndex); CARD8 bios_checksum(CARD8 *start, int size); void LockLegacyVGA(xf86Int10InfoPtr pInt, legacyVGAPtr vga); void UnlockLegacyVGA(xf86Int10InfoPtr pInt, legacyVGAPtr vga); #if defined (_PC) void xf86Int10SaveRestoreBIOSVars(xf86Int10InfoPtr pInt, Bool save); #endif int port_rep_inb(xf86Int10InfoPtr pInt, CARD16 port, CARD32 base, int d_f, CARD32 count); int port_rep_inw(xf86Int10InfoPtr pInt, CARD16 port, CARD32 base, int d_f, CARD32 count); int port_rep_inl(xf86Int10InfoPtr pInt, CARD16 port, CARD32 base, int d_f, CARD32 count); int port_rep_outb(xf86Int10InfoPtr pInt, CARD16 port, CARD32 base, int d_f, CARD32 count); int port_rep_outw(xf86Int10InfoPtr pInt, CARD16 port, CARD32 base, int d_f, CARD32 count); int port_rep_outl(xf86Int10InfoPtr pInt, CARD16 port, CARD32 base, int d_f, CARD32 count); CARD8 x_inb(CARD16 port); CARD16 x_inw(CARD16 port); void x_outb(CARD16 port, CARD8 val); void x_outw(CARD16 port, CARD16 val); CARD32 x_inl(CARD16 port); void x_outl(CARD16 port, CARD32 val); CARD8 Mem_rb(CARD32 addr); CARD16 Mem_rw(CARD32 addr); CARD32 Mem_rl(CARD32 addr); void Mem_wb(CARD32 addr, CARD8 val); void Mem_ww(CARD32 addr, CARD16 val); void Mem_wl(CARD32 addr, CARD32 val); /* helper_mem.c */ void setup_int_vect(xf86Int10InfoPtr pInt); int setup_system_bios(void *base_addr); void reset_int_vect(xf86Int10InfoPtr pInt); void set_return_trap(xf86Int10InfoPtr pInt); //void * xf86HandleInt10Options(ScrnInfoPtr pScrn, int entityIndex); Bool int10skip(void* options); Bool int10_check_bios(int scrnIndex, int codeSeg, unsigned char* vbiosMem); Bool initPrimary(void* options); //void xf86int10ParseBiosLocation(void* options, //xf86int10BiosLocationPtr bios); #ifdef DEBUG void dprint(unsigned long start, unsigned long size); #endif /* pci.c */ int mapPciRom(char *filename, unsigned char *address); #endif /* _INT10_PRIVATE */ #endif /* _XF86INT10_H */ xresprobe-0.4.24ubuntu9/ddcprobe/include/xf86x86emu.h0000644000000000000000000000236710410136571017270 0ustar /* $XFree86: xc/programs/Xserver/hw/xfree86/int10/xf86x86emu.h,v 1.1 2000/01/23 04:44:35 dawes Exp $ */ /* * XFree86 int10 module * execute BIOS int 10h calls in x86 real mode environment * Copyright 1999 Egbert Eich */ #ifndef XF86X86EMU_H_ #define XF86X86EMU_H_ #include "x86emu.h" #define M _X86EMU_env #define X86_EAX M.x86.R_EAX #define X86_EBX M.x86.R_EBX #define X86_ECX M.x86.R_ECX #define X86_EDX M.x86.R_EDX #define X86_ESI M.x86.R_ESI #define X86_EDI M.x86.R_EDI #define X86_EBP M.x86.R_EBP #define X86_EIP M.x86.R_EIP #define X86_ESP M.x86.R_ESP #define X86_EFLAGS M.x86.R_EFLG #define X86_FLAGS M.x86.R_FLG #define X86_AX M.x86.R_AX #define X86_BX M.x86.R_BX #define X86_CX M.x86.R_CX #define X86_DX M.x86.R_DX #define X86_SI M.x86.R_SI #define X86_DI M.x86.R_DI #define X86_BP M.x86.R_BP #define X86_IP M.x86.R_IP #define X86_SP M.x86.R_SP #define X86_CS M.x86.R_CS #define X86_DS M.x86.R_DS #define X86_ES M.x86.R_ES #define X86_SS M.x86.R_SS #define X86_FS M.x86.R_FS #define X86_GS M.x86.R_GS #define X86_AL M.x86.R_AL #define X86_BL M.x86.R_BL #define X86_CL M.x86.R_CL #define X86_DL M.x86.R_DL #define X86_AH M.x86.R_AH #define X86_BH M.x86.R_BH #define X86_CH M.x86.R_CH #define X86_DH M.x86.R_DH #endif xresprobe-0.4.24ubuntu9/ddcprobe/include/lrmi.h0000644000000000000000000000477510410136571016370 0ustar /* Linux Real Mode Interface - A library of DPMI-like functions for Linux. Copyright (C) 1998 by Josh Vanderhoof Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL JOSH VANDERHOOF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef LRMI_H #define LRMI_H struct LRMI_regs { unsigned int edi; unsigned int esi; unsigned int ebp; unsigned int reserved; unsigned int ebx; unsigned int edx; unsigned int ecx; unsigned int eax; unsigned short int flags; unsigned short int es; unsigned short int ds; unsigned short int fs; unsigned short int gs; unsigned short int ip; unsigned short int cs; unsigned short int sp; unsigned short int ss; }; #ifndef LRMI_PREFIX #define LRMI_PREFIX LRMI_ #endif #define LRMI_CONCAT2(a, b) a ## b #define LRMI_CONCAT(a, b) LRMI_CONCAT2(a, b) #define LRMI_MAKENAME(a) LRMI_CONCAT(LRMI_PREFIX, a) /* Initialize returns 1 if sucessful, 0 for failure */ #define LRMI_init LRMI_MAKENAME(init) int LRMI_init(void); /* Simulate a 16 bit far call returns 1 if sucessful, 0 for failure */ #define LRMI_call LRMI_MAKENAME(call) int LRMI_call(struct LRMI_regs *r); /* Simulate a 16 bit interrupt returns 1 if sucessful, 0 for failure */ #define LRMI_int LRMI_MAKENAME(int) int LRMI_int(int interrupt, struct LRMI_regs *r); /* Allocate real mode memory The returned block is paragraph (16 byte) aligned */ #define LRMI_alloc_real LRMI_MAKENAME(alloc_real) void * LRMI_alloc_real(int size); /* Free real mode memory */ #define LRMI_free_real LRMI_MAKENAME(free_real) void LRMI_free_real(void *m); /* * Get the base address of the real memory address space block. */ size_t LRMI_base_addr(void); #endif xresprobe-0.4.24ubuntu9/ddcprobe/include/types.h0000644000000000000000000000635110410136571016561 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for x86 emulator type definitions. * ****************************************************************************/ /* $XFree86: xc/extras/x86emu/include/x86emu/types.h,v 1.6 2003/06/12 14:12:26 eich Exp $ */ #ifndef __X86EMU_TYPES_H #define __X86EMU_TYPES_H #ifndef IN_MODULE #include #endif /* * The following kludge is an attempt to work around typedef conflicts with * . */ #define u8 x86emuu8 #define u16 x86emuu16 #define u32 x86emuu32 #define u64 x86emuu64 #define s8 x86emus8 #define s16 x86emus16 #define s32 x86emus32 #define s64 x86emus64 #define uint x86emuuint #define sint x86emusint /*---------------------- Macros and type definitions ----------------------*/ /* Currently only for Linux/32bit */ #undef __HAS_LONG_LONG__ #if defined(__GNUC__) && !defined(NO_LONG_LONG) #define __HAS_LONG_LONG__ #endif /* Taken from Xmd.h */ #undef NUM32 #if defined (_LP64) || \ defined(__alpha) || defined(__alpha__) || \ defined(__ia64__) || defined(ia64) || \ defined(__sparc64__) || \ defined(__s390x__) || \ (defined(__hppa__) && defined(__LP64)) || \ defined(__amd64__) || defined(amd64) || \ (defined(__sgi) && (_MIPS_SZLONG == 64)) #define NUM32 int #else #define NUM32 long #endif typedef unsigned char u8; typedef unsigned short u16; typedef unsigned NUM32 u32; #ifdef __HAS_LONG_LONG__ typedef unsigned long long u64; #endif typedef char s8; typedef short s16; typedef NUM32 s32; #ifdef __HAS_LONG_LONG__ typedef long long s64; #endif typedef unsigned int uint; typedef int sint; typedef u16 X86EMU_pioAddr; #undef NUM32 #endif /* __X86EMU_TYPES_H */ xresprobe-0.4.24ubuntu9/ddcprobe/include/regs.h0000644000000000000000000002430510410136571016354 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for x86 register definitions. * ****************************************************************************/ /* $XFree86: xc/extras/x86emu/include/x86emu/regs.h,v 1.5 2003/10/22 20:03:05 tsi Exp $ */ #ifndef __X86EMU_REGS_H #define __X86EMU_REGS_H /*---------------------- Macros and type definitions ----------------------*/ /* * General EAX, EBX, ECX, EDX type registers. Note that for * portability, and speed, the issue of byte swapping is not addressed * in the registers. All registers are stored in the default format * available on the host machine. The only critical issue is that the * registers should line up EXACTLY in the same manner as they do in * the 386. That is: * * EAX & 0xff === AL * EAX & 0xffff == AX * * etc. The result is that alot of the calculations can then be * done using the native instruction set fully. */ #ifdef __BIG_ENDIAN__ typedef struct { u32 e_reg; } I32_reg_t; typedef struct { u16 filler0, x_reg; } I16_reg_t; typedef struct { u8 filler0, filler1, h_reg, l_reg; } I8_reg_t; #else /* !__BIG_ENDIAN__ */ typedef struct { u32 e_reg; } I32_reg_t; typedef struct { u16 x_reg; } I16_reg_t; typedef struct { u8 l_reg, h_reg; } I8_reg_t; #endif /* BIG_ENDIAN */ typedef union { I32_reg_t I32_reg; I16_reg_t I16_reg; I8_reg_t I8_reg; } i386_general_register; struct i386_general_regs { i386_general_register A, B, C, D; }; typedef struct i386_general_regs Gen_reg_t; struct i386_special_regs { i386_general_register SP, BP, SI, DI, IP; u32 FLAGS; }; /* * Segment registers here represent the 16 bit quantities * CS, DS, ES, SS. */ struct i386_segment_regs { u16 CS, DS, SS, ES, FS, GS; }; /* 8 bit registers */ #define R_AH gen.A.I8_reg.h_reg #define R_AL gen.A.I8_reg.l_reg #define R_BH gen.B.I8_reg.h_reg #define R_BL gen.B.I8_reg.l_reg #define R_CH gen.C.I8_reg.h_reg #define R_CL gen.C.I8_reg.l_reg #define R_DH gen.D.I8_reg.h_reg #define R_DL gen.D.I8_reg.l_reg /* 16 bit registers */ #define R_AX gen.A.I16_reg.x_reg #define R_BX gen.B.I16_reg.x_reg #define R_CX gen.C.I16_reg.x_reg #define R_DX gen.D.I16_reg.x_reg /* 32 bit extended registers */ #define R_EAX gen.A.I32_reg.e_reg #define R_EBX gen.B.I32_reg.e_reg #define R_ECX gen.C.I32_reg.e_reg #define R_EDX gen.D.I32_reg.e_reg /* special registers */ #define R_SP spc.SP.I16_reg.x_reg #define R_BP spc.BP.I16_reg.x_reg #define R_SI spc.SI.I16_reg.x_reg #define R_DI spc.DI.I16_reg.x_reg #define R_IP spc.IP.I16_reg.x_reg #define R_FLG spc.FLAGS /* special registers */ #define R_SP spc.SP.I16_reg.x_reg #define R_BP spc.BP.I16_reg.x_reg #define R_SI spc.SI.I16_reg.x_reg #define R_DI spc.DI.I16_reg.x_reg #define R_IP spc.IP.I16_reg.x_reg #define R_FLG spc.FLAGS /* special registers */ #define R_ESP spc.SP.I32_reg.e_reg #define R_EBP spc.BP.I32_reg.e_reg #define R_ESI spc.SI.I32_reg.e_reg #define R_EDI spc.DI.I32_reg.e_reg #define R_EIP spc.IP.I32_reg.e_reg #define R_EFLG spc.FLAGS /* segment registers */ #define R_CS seg.CS #define R_DS seg.DS #define R_SS seg.SS #define R_ES seg.ES #define R_FS seg.FS #define R_GS seg.GS /* flag conditions */ #define FB_CF 0x0001 /* CARRY flag */ #define FB_PF 0x0004 /* PARITY flag */ #define FB_AF 0x0010 /* AUX flag */ #define FB_ZF 0x0040 /* ZERO flag */ #define FB_SF 0x0080 /* SIGN flag */ #define FB_TF 0x0100 /* TRAP flag */ #define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ #define FB_DF 0x0400 /* DIR flag */ #define FB_OF 0x0800 /* OVERFLOW flag */ /* 80286 and above always have bit#1 set */ #define F_ALWAYS_ON (0x0002) /* flag bits always on */ /* * Define a mask for only those flag bits we will ever pass back * (via PUSHF) */ #define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) /* following bits masked in to a 16bit quantity */ #define F_CF 0x0001 /* CARRY flag */ #define F_PF 0x0004 /* PARITY flag */ #define F_AF 0x0010 /* AUX flag */ #define F_ZF 0x0040 /* ZERO flag */ #define F_SF 0x0080 /* SIGN flag */ #define F_TF 0x0100 /* TRAP flag */ #define F_IF 0x0200 /* INTERRUPT ENABLE flag */ #define F_DF 0x0400 /* DIR flag */ #define F_OF 0x0800 /* OVERFLOW flag */ #define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) #define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) #define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) #define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) #define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) #define CONDITIONAL_SET_FLAG(COND,FLAG) \ if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) #define F_PF_CALC 0x010000 /* PARITY flag has been calced */ #define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ #define F_SF_CALC 0x040000 /* SIGN flag has been calced */ #define F_ALL_CALC 0xff0000 /* All have been calced */ /* * Emulator machine state. * Segment usage control. */ #define SYSMODE_SEG_DS_SS 0x00000001 #define SYSMODE_SEGOVR_CS 0x00000002 #define SYSMODE_SEGOVR_DS 0x00000004 #define SYSMODE_SEGOVR_ES 0x00000008 #define SYSMODE_SEGOVR_FS 0x00000010 #define SYSMODE_SEGOVR_GS 0x00000020 #define SYSMODE_SEGOVR_SS 0x00000040 #define SYSMODE_PREFIX_REPE 0x00000080 #define SYSMODE_PREFIX_REPNE 0x00000100 #define SYSMODE_PREFIX_DATA 0x00000200 #define SYSMODE_PREFIX_ADDR 0x00000400 #define SYSMODE_INTR_PENDING 0x10000000 #define SYSMODE_EXTRN_INTR 0x20000000 #define SYSMODE_HALTED 0x40000000 #define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ SYSMODE_SEGOVR_FS | \ SYSMODE_SEGOVR_GS | \ SYSMODE_SEGOVR_SS) #define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ SYSMODE_SEGOVR_FS | \ SYSMODE_SEGOVR_GS | \ SYSMODE_SEGOVR_SS | \ SYSMODE_PREFIX_DATA | \ SYSMODE_PREFIX_ADDR) #define INTR_SYNCH 0x1 #define INTR_ASYNCH 0x2 #define INTR_HALTED 0x4 typedef struct { struct i386_general_regs gen; struct i386_special_regs spc; struct i386_segment_regs seg; /* * MODE contains information on: * REPE prefix 2 bits repe,repne * SEGMENT overrides 5 bits normal,DS,SS,CS,ES * Delayed flag set 3 bits (zero, signed, parity) * reserved 6 bits * interrupt # 8 bits instruction raised interrupt * BIOS video segregs 4 bits * Interrupt Pending 1 bits * Extern interrupt 1 bits * Halted 1 bits */ u32 mode; volatile int intr; /* mask of pending interrupts */ int debug; #ifdef DEBUG int check; u16 saved_ip; u16 saved_cs; int enc_pos; int enc_str_pos; char decode_buf[32]; /* encoded byte stream */ char decoded_buf[256]; /* disassembled strings */ #endif u8 intno; u8 __pad[3]; } X86EMU_regs; /**************************************************************************** REMARKS: Structure maintaining the emulator machine state. MEMBERS: mem_base - Base real mode memory for the emulator mem_size - Size of the real mode memory block for the emulator private - private data pointer x86 - X86 registers ****************************************************************************/ typedef struct { unsigned long mem_base; unsigned long mem_size; void* private; X86EMU_regs x86; } X86EMU_sysEnv; /*----------------------------- Global Variables --------------------------*/ #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif /* Global emulator machine state. * * We keep it global to avoid pointer dereferences in the code for speed. */ extern X86EMU_sysEnv _X86EMU_env; #define M _X86EMU_env /*-------------------------- Function Prototypes --------------------------*/ /* Function to log information at runtime */ void printk(const char *fmt, ...); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_REGS_H */ xresprobe-0.4.24ubuntu9/ddcprobe/include/x86emu.h0000644000000000000000000001603710410136571016553 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for public specific functions. * Any application linking against us should only * include this header * ****************************************************************************/ /* $XFree86$ */ #ifndef __X86EMU_X86EMU_H #define __X86EMU_X86EMU_H #ifdef SCITECH #include "scitech.h" #define X86API _ASMAPI #define X86APIP _ASMAPIP typedef int X86EMU_pioAddr; #else #include "types.h" #define X86API #define X86APIP * #endif #include "regs.h" /*---------------------- Macros and type definitions ----------------------*/ /* #pragma pack(1) */ /* Don't pack structs with function pointers! */ /**************************************************************************** REMARKS: Data structure containing ponters to programmed I/O functions used by the emulator. This is used so that the user program can hook all programmed I/O for the emulator to handled as necessary by the user program. By default the emulator contains simple functions that do not do access the hardware in any way. To allow the emualtor access the hardware, you will need to override the programmed I/O functions using the X86EMU_setupPioFuncs function. HEADER: x86emu.h MEMBERS: inb - Function to read a byte from an I/O port inw - Function to read a word from an I/O port inl - Function to read a dword from an I/O port outb - Function to write a byte to an I/O port outw - Function to write a word to an I/O port outl - Function to write a dword to an I/O port ****************************************************************************/ typedef struct { u8 (X86APIP inb)(X86EMU_pioAddr addr); u16 (X86APIP inw)(X86EMU_pioAddr addr); u32 (X86APIP inl)(X86EMU_pioAddr addr); void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); } X86EMU_pioFuncs; /**************************************************************************** REMARKS: Data structure containing ponters to memory access functions used by the emulator. This is used so that the user program can hook all memory access functions as necessary for the emulator. By default the emulator contains simple functions that only access the internal memory of the emulator. If you need specialised functions to handle access to different types of memory (ie: hardware framebuffer accesses and BIOS memory access etc), you will need to override this using the X86EMU_setupMemFuncs function. HEADER: x86emu.h MEMBERS: rdb - Function to read a byte from an address rdw - Function to read a word from an address rdl - Function to read a dword from an address wrb - Function to write a byte to an address wrw - Function to write a word to an address wrl - Function to write a dword to an address ****************************************************************************/ typedef struct { u8 (X86APIP rdb)(u32 addr); u16 (X86APIP rdw)(u32 addr); u32 (X86APIP rdl)(u32 addr); void (X86APIP wrb)(u32 addr, u8 val); void (X86APIP wrw)(u32 addr, u16 val); void (X86APIP wrl)(u32 addr, u32 val); } X86EMU_memFuncs; /**************************************************************************** Here are the default memory read and write function in case they are needed as fallbacks. ***************************************************************************/ extern u8 X86API rdb(u32 addr); extern u16 X86API rdw(u32 addr); extern u32 X86API rdl(u32 addr); extern void X86API wrb(u32 addr, u8 val); extern void X86API wrw(u32 addr, u16 val); extern void X86API wrl(u32 addr, u32 val); /* #pragma pack() */ /*--------------------- type definitions -----------------------------------*/ typedef void (X86APIP X86EMU_intrFuncs)(int num); extern X86EMU_intrFuncs _X86EMU_intrTab[256]; /*-------------------------- Function Prototypes --------------------------*/ #ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); void X86EMU_prepareForInt(int num); /* decode.c */ void X86EMU_exec(void); void X86EMU_halt_sys(void); #ifdef DEBUG #define HALT_SYS() \ printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ X86EMU_halt_sys() #else #define HALT_SYS() X86EMU_halt_sys() #endif /* Debug options */ #define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ #define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ #define DEBUG_STEP_F 0x000004 #define DEBUG_DISASSEMBLE_F 0x000008 #define DEBUG_BREAK_F 0x000010 #define DEBUG_SVC_F 0x000020 #define DEBUG_FS_F 0x000080 #define DEBUG_PROC_F 0x000100 #define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 #define DEBUG_MEM_TRACE_F 0x001000 #define DEBUG_IO_TRACE_F 0x002000 #define DEBUG_TRACECALL_REGS_F 0x004000 #define DEBUG_DECODE_NOPRINT_F 0x008000 #define DEBUG_SAVE_IP_CS_F 0x010000 #define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) void X86EMU_trace_regs(void); void X86EMU_trace_xregs(void); void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); int X86EMU_trace_on(void); int X86EMU_trace_off(void); #ifdef __cplusplus } /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_X86EMU_H */ xresprobe-0.4.24ubuntu9/ddcprobe/include/fpu_regs.h0000644000000000000000000000746710410136571017240 0ustar /**************************************************************************** * * Realmode X86 Emulator Library * * Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * * ======================================================================== * * Permission to use, copy, modify, distribute, and sell this software and * its documentation for any purpose is hereby granted without fee, * provided that the above copyright notice appear in all copies and that * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software * without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * ======================================================================== * * Language: ANSI C * Environment: Any * Developer: Kendall Bennett * * Description: Header file for FPU register definitions. * ****************************************************************************/ /* $XFree86: xc/extras/x86emu/include/x86emu/fpu_regs.h,v 1.2 2003/10/22 20:03:05 tsi Exp $ */ #ifndef __X86EMU_FPU_REGS_H #define __X86EMU_FPU_REGS_H #ifdef X86_FPU_SUPPORT /* Basic 8087 register can hold any of the following values: */ union x86_fpu_reg_u { s8 tenbytes[10]; double dval; float fval; s16 sval; s32 lval; }; struct x86_fpu_reg { union x86_fpu_reg_u reg; char tag; }; /* * Since we are not going to worry about the problems of aliasing * registers, every time a register is modified, its result type is * set in the tag fields for that register. If some operation * attempts to access the type in a way inconsistent with its current * storage format, then we flag the operation. If common, we'll * attempt the conversion. */ #define X86_FPU_VALID 0x80 #define X86_FPU_REGTYP(r) ((r) & 0x7F) #define X86_FPU_WORD 0x0 #define X86_FPU_SHORT 0x1 #define X86_FPU_LONG 0x2 #define X86_FPU_FLOAT 0x3 #define X86_FPU_DOUBLE 0x4 #define X86_FPU_LDBL 0x5 #define X86_FPU_BSD 0x6 #define X86_FPU_STKTOP 0 struct x86_fpu_registers { struct x86_fpu_reg x86_fpu_stack[8]; int x86_fpu_flags; int x86_fpu_config; /* rounding modes, etc. */ short x86_fpu_tos, x86_fpu_bos; }; /* * There are two versions of the following macro. * * One version is for opcode D9, for which there are more than 32 * instructions encoded in the second byte of the opcode. * * The other version, deals with all the other 7 i87 opcodes, for * which there are only 32 strings needed to describe the * instructions. */ #endif /* X86_FPU_SUPPORT */ #ifdef DEBUG # define DECODE_PRINTINSTR32(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<3)+(rh)]); # define DECODE_PRINTINSTR256(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); #else # define DECODE_PRINTINSTR32(t,mod,rh,rl) # define DECODE_PRINTINSTR256(t,mod,rh,rl) #endif #endif /* __X86EMU_FPU_REGS_H */ xresprobe-0.4.24ubuntu9/ddcprobe/modetest.c0000644000000000000000000000637410214367723015625 0ustar #include #include #include #include #include #include #include #include #include #include #include #include "vbe.h" #ident "$Id: modetest.c,v 1.3 1999/08/24 01:08:47 nalin Exp $" #define VESA_MODE 0x112 int main(int argc, char **argv) { const void *start_state; u_int16_t start_mode; struct vbe_info *info; struct vbe_mode_info *mode_info; char fontdata[32 * 512]; struct consolefontdesc font = {512, 32, fontdata}; int fd, tty_fd; long tty_mode; char *lfb; int i, j; /* Make sure we have VESA on this machine. */ info = vbe_get_vbe_info(); if(info == NULL) { fprintf(stderr, "VESA BIOS Extensions not detected.\n"); exit(1); } fprintf(stderr, "Detected %c%c%c%c %d.%d\n", info->signature[0], info->signature[1], info->signature[2], info->signature[3], info->version[1], info->version[0]); /* Open the current tty. We'll need this for setting fonts. */ tty_fd = open("/dev/tty", O_RDWR); if(tty_fd == -1) { perror("opening tty"); exit(1); } /* Save the current VESA state and mode. */ start_state = vbe_save_svga_state(); start_mode = vbe_get_mode(); /* Make sure we don't have garbage values for these. */ assert(start_state); assert(start_mode); printf("Started in mode 0x%04x.\n", start_mode); /* Make sure the desired mode is available. */ mode_info = vbe_get_mode_info(VBE_LINEAR_FRAMEBUFFER | VESA_MODE); assert(mode_info != NULL); assert(mode_info->linear_buffer_address != 0); /* Memory-map the framebuffer for direct access (whee!) */ fd = open("/dev/mem", O_RDWR); if(fd == -1) { perror("opening framebuffer"); exit(1); } lfb = mmap(NULL, mode_info->bytes_per_scanline * mode_info->h, PROT_WRITE, MAP_SHARED, fd, mode_info->linear_buffer_address); if(lfb == MAP_FAILED) { perror("memory-mapping framebuffer"); exit(1); } /* Get the console's current mode and font for restoring when we're finished messing with it. */ if(ioctl(tty_fd, KDGETMODE, &tty_mode) != 0) { perror("getting console mode"); exit(1); } if(ioctl(tty_fd, GIO_FONTX, &font) != 0) { perror("saving console font"); exit(1); } /* Tell the console we're going into graphics mode. */ if(ioctl(tty_fd, KDSETMODE, KD_GRAPHICS) != 0) { perror("preparing for graphics"); exit(1); } /* Do the switch. */ fprintf(stderr, "Switching to mode 0x%04x: %dx%d, %d-bit...\n", VBE_LINEAR_FRAMEBUFFER | VESA_MODE, mode_info->w, mode_info->h, mode_info->bpp); vbe_set_mode(VBE_LINEAR_FRAMEBUFFER | VESA_MODE); /* Test pattern time! */ for(i = 0; i < mode_info->h; i++) for(j = 0; j < mode_info->w; j++) { lfb[3 * (i * mode_info->w + j) + 0] = j % 256; lfb[3 * (i * mode_info->w + j) + 1] = j % 128; lfb[3 * (i * mode_info->w + j) + 2] = j % 64; } /* Pause to admire the display. */ sleep(10); /* Restore the original video mode, hardware settings, VT mode and font. */ vbe_set_mode(start_mode); vbe_restore_svga_state(start_state); fprintf(stderr, "Back to normal.\n"); if(ioctl(tty_fd, KDSETMODE, tty_mode) != 0) { perror("switching vt back to normal mode"); } if(ioctl(tty_fd, PIO_FONTX, &font) != 0) { perror("restoring console font"); system("setfont"); } return 0; } xresprobe-0.4.24ubuntu9/ddcprobe/ddcprobe.c0000644000000000000000000002345710410136571015555 0ustar #define _GNU_SOURCE #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined (__i386__) #include #include #endif #if defined (__i386__) || defined (__x86_64__) #include "vbe.h" #include "include/lrmi.h" #endif #include #include "common.h" #include "vesamode.h" char *snip(char *string) { int i; /* This is always a 13 character buffer */ /* and it's not always terminated. */ string[12] = '\0'; while(((i = strlen(string)) > 0) && (isspace(string[i - 1]) || (string[i - 1] == '\n') || (string[i - 1] == '\r'))) { string[i - 1] = '\0'; } return string; } int main(int argc, char **argv) { struct edid1_info *edid_info = NULL; char manufacturer[4]; int i; struct vbe_parent_info *vbe_parent_info = NULL; struct vbe_info *vbe_info = NULL; #if defined (__i386__) || defined (__x86_64__) u_int16_t *mode_list = NULL; #endif /* __i386__ */ unsigned char *timings; struct edid_monitor_descriptor *monitor; unsigned char *timing; #if defined (__i386__) || defined (__powerpc__) || defined (__x86_64__) assert(sizeof(struct edid1_info) == 256); assert(sizeof(struct edid_detailed_timing) == 18); assert(sizeof(struct edid_monitor_descriptor) == 18); assert(sizeof(struct vbe_info) == 512); #endif vbe_parent_info = vbe_get_vbe_info(); vbe_info = &vbe_parent_info->vbe; if(vbe_info == NULL) { fprintf(stderr, "VESA BIOS Extensions not detected.\n"); exit(1); } else { #ifdef __powerpc__ printf("oem: %s\n", vbe_parent_info->oem_name_string); printf("memory: %dkb\n", vbe_info->memory_size); } #elif defined (__i386__) || defined (__x86_64__) /* Signature. */ printf("vbe: %c%c%c%c %d.%d detected.\n", vbe_info->signature[0], vbe_info->signature[1], vbe_info->signature[2], vbe_info->signature[3], vbe_info->version[1], vbe_info->version[0]); /* OEM Strings. */ printf("oem: %s\n", vbe_parent_info->oem_name_string); if(vbe_info->version[1] >= 3) { printf("vendor: %s\n", vbe_parent_info->vendor_name_string); printf("product: %s %s\n", vbe_parent_info->product_name_string, vbe_parent_info->product_revision_string); } if (strcasestr(vbe_parent_info->oem_name_string, "intel") && strstr(vbe_parent_info->oem_name_string, "810")) { printf("memory: %dkb\n", vbe_info->memory_size * 64); printf("memory: 4096kb\n"); } else printf("memory: %dkb\n", vbe_info->memory_size * 64); /* List supported standard modes. */ mode_list = vbe_parent_info->mode_list_list; for(;*mode_list != 0xffff; mode_list++) { int i; for(i = 0; known_vesa_modes[i].x != 0; i++) { if(known_vesa_modes[i].number == *mode_list) { printf("mode: %s\n", known_vesa_modes[i].text); } } } } #else fprintf(stderr, "Sorry, unsupported architecture\n"); exit(1); } #endif if(!get_edid_supported()) { printf("noedid\n"); exit(0); } edid_info = get_edid_info(); printf("edid: %s\n", edid_info); /* Interpret results. */ if((edid_info == NULL) || (edid_info->version == 0)) { printf("edidfail\n"); exit(0); } if ((edid_info->version == 0xff && edid_info->revision == 0xff) || (edid_info->version == 0 && edid_info->revision == 0)) { printf("edidfail\n"); exit(0); } printf("edid: %d %d\n", edid_info->version, edid_info->revision); manufacturer[0] = edid_info->manufacturer_name.char1 + 'A' - 1; manufacturer[1] = edid_info->manufacturer_name.char2 + 'A' - 1; manufacturer[2] = edid_info->manufacturer_name.char3 + 'A' - 1; manufacturer[3] = '\0'; printf("id: %04x\n", edid_info->product_code); printf("eisa: %s%04x\n", manufacturer, edid_info->product_code); if(edid_info->serial_number != 0xffffffff) { if(strcmp(manufacturer, "MAG") == 0) { edid_info->serial_number -= 0x7000000; } if(strcmp(manufacturer, "OQI") == 0) { edid_info->serial_number -= 456150000; } if(strcmp(manufacturer, "VSC") == 0) { edid_info->serial_number -= 640000000; } } printf("serial: %08x\n", edid_info->serial_number); printf("manufacture: %d %d\n", edid_info->week, edid_info->year + 1990); printf("input: %s%s%s%s.\n", edid_info->video_input_definition.separate_sync ? "separate sync, " : "", edid_info->video_input_definition.composite_sync ? "composite sync, " : "", edid_info->video_input_definition.sync_on_green ? "sync on green, " : "", edid_info->video_input_definition.digital ? "digital signal" : "analog signal"); printf("screensize: %d %d\n", edid_info->max_size_horizontal, edid_info->max_size_vertical); printf("gamma: %f\n", edid_info->gamma / 100.0 + 1); printf("dpms: %s, %s%s, %s%s, %s%s\n", edid_info->feature_support.rgb ? "RGB" : "non-RGB", edid_info->feature_support.active_off ? "" : "no ", "active off", edid_info->feature_support.suspend ? "" : "no ", "suspend", edid_info->feature_support.standby ? "" : "no ", "standby"); if(edid_info->established_timings.timing_720x400_70) printf("timing: 720x400@70 Hz (VGA 640x400, IBM)\n"); if(edid_info->established_timings.timing_720x400_88) printf("timing: 720x400@88 Hz (XGA2)\n"); if(edid_info->established_timings.timing_640x480_60) printf("timing: 640x480@60 Hz (VGA)\n"); if(edid_info->established_timings.timing_640x480_67) printf("timing: 640x480@67 Hz (Mac II, Apple)\n"); if(edid_info->established_timings.timing_640x480_72) printf("timing: 640x480@72 Hz (VESA)\n"); if(edid_info->established_timings.timing_640x480_75) printf("timing: 640x480@75 Hz (VESA)\n"); if(edid_info->established_timings.timing_800x600_56) printf("timing: 800x600@56 Hz (VESA)\n"); if(edid_info->established_timings.timing_800x600_60) printf("timing: 800x600@60 Hz (VESA)\n"); if(edid_info->established_timings.timing_800x600_72) printf("timing: 800x600@72 Hz (VESA)\n"); if(edid_info->established_timings.timing_800x600_75) printf("timing: 800x600@75 Hz (VESA)\n"); if(edid_info->established_timings.timing_832x624_75) printf("timing: 832x624@75 Hz (Mac II)\n"); if(edid_info->established_timings.timing_1024x768_87i) printf("timing: 1024x768@87 Hz Interlaced (8514A)\n"); if(edid_info->established_timings.timing_1024x768_60) printf("timing: 1024x768@60 Hz (VESA)\n"); if(edid_info->established_timings.timing_1024x768_70) printf("timing: 1024x768@70 Hz (VESA)\n"); if(edid_info->established_timings.timing_1024x768_75) printf("timing: 1024x768@75 Hz (VESA)\n"); if(edid_info->established_timings.timing_1280x1024_75) printf("timing: 1280x1024@75 (VESA)\n"); /* Standard timings. */ for(i = 0; i < 8; i++) { double aspect = 1; unsigned int x, y; unsigned char xres, vfreq; xres = edid_info->standard_timing[i].xresolution; vfreq = edid_info->standard_timing[i].vfreq; if((xres != vfreq) || ((xres != 0) && (xres != 1)) || ((vfreq != 0) && (vfreq != 1))) { switch(edid_info->standard_timing[i].aspect) { case 0: aspect = 1; break; /*undefined*/ case 1: aspect = 0.750; break; case 2: aspect = 0.800; break; case 3: aspect = 0.625; break; } x = (xres + 31) * 8; y = x * aspect; printf("ctiming: %dx%d@%d\n", x, y, (vfreq & 0x3f) + 60); } } /* Detailed timing information. */ /* The original dtiming code didn't actually work at all, so I've * removed it and replaced it with my own dtiming code, which is derived * from the VESA spec and parse-edid.c. How well it works on monitors * with multiple dtimings is unknown, since I don't have one. -daniels */ timings = (unsigned char *)&edid_info->monitor_details.detailed_timing; monitor = NULL; for(i = 0; i < 4; i++) { timing = &(timings[i*18]); if (timing[0] == 0 && timing[1] == 0) { monitor = &edid_info->monitor_details.monitor_descriptor[i]; if (monitor->type == edid_monitor_descriptor_serial) printf("monitorserial: %s\n", snip(monitor->data.string)); else if (monitor->type == edid_monitor_descriptor_ascii) printf("monitorid: %s\n", snip(monitor->data.string)); else if (monitor->type == edid_monitor_descriptor_name) printf("monitorname: %s\n", snip(monitor->data.string)); else if (monitor->type == edid_monitor_descriptor_range) printf("monitorrange: %d-%d, %d-%d\n", monitor->data.range_data.horizontal_min, monitor->data.range_data.horizontal_max, monitor->data.range_data.vertical_min, monitor->data.range_data.vertical_max); } else { int h_active_high, h_active_low, h_active; int h_blanking_high, h_blanking_low, h_blanking; int v_active_high, v_active_low, v_active; int v_blanking_high, v_blanking_low, v_blanking; int pixclock_high, pixclock_low, pixclock; int h_total, v_total, vfreq; pixclock_low = timing[0]; pixclock_high = timing[1]; pixclock = ((pixclock_high << 8) | pixclock_low) * 10000; h_blanking_high = ((1|2|4|8) & (timing[4])) >> 4; h_blanking_low = timing[3]; h_blanking = ((h_blanking_high) << 8) | h_blanking_low; h_active_high = ((128|64|32|16) & (timing[4])) >> 4; h_active_low = timing[2]; h_active = ((h_active_high) << 8) | h_active_low; h_total = h_active + h_blanking; v_blanking_high = ((1|2|4|8) & (timing[7])) >> 4; v_blanking_low = timing[6]; v_blanking = ((v_blanking_high) << 8) | v_blanking_low; v_active_high = ((128|64|32|16) & (timing[7])) >> 4; v_active_low = timing[5]; v_active = ((v_active_high) << 8) | v_active_low; v_total = v_active + v_blanking; vfreq = (double)pixclock/((double)v_total*(double)h_total); printf("dtiming: %dx%d@%d\n", h_active, v_active, vfreq); } } return 0; } xresprobe-0.4.24ubuntu9/ddcprobe/stub.c0000644000000000000000000000047310415737362014753 0ustar #include #include "common.h" struct vbe_parent_info *vbe_get_vbe_info() { struct vbe_info *ret = NULL; return ret; } int get_edid_supported() { int ret = 0; return ret; } struct edid1_info *get_edid_info() { struct edid1_info *ret = NULL; return ret; } xresprobe-0.4.24ubuntu9/ddcprobe/svgamodes.c0000644000000000000000000001225310410136571015753 0ustar #if defined (__i386__) #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "vbe.h" #include "vesamode.h" #include "include/lrmi.h" #ident "$Id: svgamodes.c,v 1.6 2003/02/11 14:47:38 notting Exp $" /* Callback for qsort(). */ static int compare_16(const void *i1, const void *i2) { const u_int16_t *I1, *I2; I1 = (const u_int16_t*) i1; I2 = (const u_int16_t*) i2; if(*I1 < *I2) return -1; if(*I1 > *I2) return 1; return 0; } int main(int argc, char **argv) { struct vbe_parent_info *vbe_parent_info = NULL; struct vbe_info *vbe_info = NULL; struct vbe_mode_info *mode_info = NULL; u_int16_t *mode_list = NULL; int mode_count = 0; float vesa_version; /* Get basic information. */ vbe_parent_info = vbe_get_vbe_info(); if(vbe_info == NULL) { printf("VESA BIOS Extensions not detected.\n"); exit(0); } vbe_info = &vbe_parent_info->vbe; /* Print the signature, should be "VESA .". */ printf("%c%c%c%c %d.%d detected.\n", vbe_info->signature[0], vbe_info->signature[1], vbe_info->signature[2], vbe_info->signature[3], vbe_info->version[1], vbe_info->version[0]); vesa_version = (vbe_info->version[1]) + (vbe_info->version[0]) / 10.0; /* List supported standard modes. */ mode_list = vbe_parent_info->mode_list_list; if(*mode_list != 0xffff) { printf("Supported modes:\n"); } /* Count the number of modes. */ for(;*mode_list != 0xffff; mode_list++) { mode_count++; } /* Sort the mode list, because my ATI doesn't. Grrr... */ mode_list = vbe_parent_info->mode_list_list; if(*mode_list != 0xffff) { qsort(mode_list, mode_count, sizeof(u_int16_t), compare_16); } /* Dump info about the video mode. */ for(;*mode_list != 0xffff; mode_list++) { int j; /* Mode number. */ printf("0x%03x\t", *mode_list); for(j = 0; known_vesa_modes[j].x != 0; j++) { /* If it's a standard mode, print info about it. */ if(known_vesa_modes[j].number == *mode_list) { printf("Specs list this as %dx%d, %d colors.", known_vesa_modes[j].x, known_vesa_modes[j].y, known_vesa_modes[j].colors); }} printf("\n"); /* Get mode information from the BIOS. Should never fail. */ mode_info = vbe_get_mode_info(*mode_list); if(mode_info == NULL) { printf("Get mode information not supported by BIOS.\n"); exit(0); } /* Report what the BIOS says about the mode, should agree with VESA on standard modes. */ if(mode_info->w && mode_info->h && mode_info->bpp) { printf("\tBIOS reports this as %dx%d, %d bpp", mode_info->w, mode_info->h, mode_info->bpp); } if(mode_info->bytes_per_scanline) { printf(", %d bytes per scanline.", mode_info->bytes_per_scanline); } printf("\n"); /* Check the 'supported' bit. Should be set, because this is in the main supported modes list. */ printf("\t%s, ", mode_info->mode_attributes.supported ? "Supported" : "Not supported"); /* Color? Graphics? */ printf("%s ", mode_info->mode_attributes.color ? "Color" : "Monochrome"); printf("%s.\n", mode_info->mode_attributes.graphics ? "Graphics" : "Text"); /* Check for LFB stuff. Ralf's list says that you need to query with bit 14 set to check if an LFB version of the mode is available, but the ATI always returns true. */ if(vesa_version >= 2.0) { /* Regular info about the current mode. */ struct vbe_mode_info *info = NULL; printf("\t%sVGA compatible.\n", mode_info->mode_attributes.not_vga_compatible ? "Not " : ""); printf("\tThis is %san LFB mode.\n", mode_info->mode_attributes.lfb ? "" : "not "); /* Info about the LFB variant mode (bit 14 set). */ info = vbe_get_mode_info(*mode_list | VBE_LINEAR_FRAMEBUFFER); if(info) { if(info->mode_attributes.lfb) { printf("\tLFB variant available.\n"); } free(info); } if((mode_info->mode_attributes.lfb) || (info && (info->mode_attributes.lfb))) { printf("\tLFB at address 0x%8x.\n", mode_info->linear_buffer_address); } } /* Memory model: EGA = icky bit planes, packed-pixel = palette, direct color = LFB compatible but needs bank switches. */ printf("\tMemory model: "); switch(mode_info->memory_model) { case memory_model_text: { printf("text.\n"); break; } case memory_model_cga: { printf("CGA.\n"); break; } case memory_model_hgc: { printf("Hercules.\n"); break; } case memory_model_ega16: { printf("EGA.\n"); break; } case memory_model_packed_pixel: { printf("packed-pixel.\n"); break; } case memory_model_sequ256: { printf("sequential 256.\n"); break; } case memory_model_direct_color: { printf("direct color.\n"); break; } case memory_model_yuv: { printf("YUV.\n"); break; } default : { printf("unknown/OEM.\n"); } } } return 0; } #endif /* __i386__ */ xresprobe-0.4.24ubuntu9/UNDETECTABLE0000644000000000000000000000042010214367723013617 0ustar * r4xx: this is a bit weird -- (WW) RADEON(0): LVDS Info:\nXRes: %d, YRes: %d need contextual egrep and friends -- eep! only occurs on ATI ATOM BIOSes (r4xx) AFAICT -d * anything on amd64: need to port our int10 stuff to amd64; currently digging up ASM books. xresprobe-0.4.24ubuntu9/xresprobe0000755000000000000000000001067410704625164014010 0ustar #!/bin/sh # Usage: xresprobe driver [screentype] # Copyright (C) 2004 Canonical Ltd # Author: Daniel Stone # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License with # the Debian GNU/Linux distribution in file /usr/share/common-licenses/GPL-2; # if not, write to the Free Software Foundation, Inc., 59 Temple Place, # Suite 330, Boston, MA 02111-1307 USA # # On Debian systems, the complete text of the GNU General Public # License, version 2, can be found in /usr/share/common-licenses/GPL-2. DATADIR="/usr/share/xresprobe" DRIVER="$1" SCREENTYPE="$2" RETCODE=0 if [ -z "$DRIVER" ]; then echo "Driver must be specified." exit 1 fi if [ -n "$SCREENTYPE" ]; then if [ "$SCREENTYPE" = "laptop" ]; then LAPTOP="yes" elif [ "$SCREENTYPE" = "crt" ]; then DDC="yes" elif [ "$SCREENTYPE" = "lcd" ]; then DDC="yes" fi else if which laptop-detect >/dev/null 2>&1; then if laptop-detect >/dev/null 2>&1; then LAPTOP="yes" else DDC="yes" fi else echo "laptop-detect must be installed for xresprobe to work properly. If" echo "you really want to continue without it, call xresprobe like:" echo "$0 drivername [laptop|crt|lcd]" echo echo "Note that laptop LCDs are different from standard desktop LCDs, so" echo "be careful how you call it." fi fi if [ -n "$XRESPROBE_DEBUG" ]; then echo "laptop: $LAPTOP; ddc: $DDC" >&2 fi if [ -n "$XRESPROBE_RIG" ]; then if [ -n "$XRESPROBE_DEBUG" ]; then echo "xresprobe: rigging results for $XRESPROBE_RIG" >&2 fi exec "$DATADIR/rigprobe.sh" $DRIVER $SCREENTYPE $LAPTOP fi doddc() { if [ -n "$XRESPROBE_DEBUG" ]; then echo "attempting DDC detection" >&2 fi DDCOUT="$("$DATADIR/ddcprobe.sh")" RETCODE="$?" RES="$(echo "$DDCOUT" | grep "^res:" | sed -e 's/^res: *//;')" IDENTIFIER="$(echo "$DDCOUT" | grep "^name:" | sed -e 's/^name: *//;')" FREQ="$(echo "$DDCOUT" | grep "^freq:" | sed -e 's/^freq: *//;')" DISPTYPE="$(echo "$DDCOUT" | grep "^disptype:" | sed -e 's/^disptype: *//;')" # well, not necessarily, but it's a pretty good guess if [ -n "$DISPTYPE" ] && [ "$DISPTYPE" = "lcd" ]; then DISPTYPE="lcd/tmds" fi } forkx() { if [ -z "$FORKEDX" ]; then if [ -n "$XRESPROBE_DEBUG" ]; then echo "forking Xorg" >&2 fi XPROBEDIR="$("$DATADIR/xprobe.sh" "$DRIVER")" RETCODE="$?" LOGFILE="$XPROBEDIR/xorg.log" FORKEDX="yes" else if [ -n "$XRESPROBE_DEBUG" ]; then echo "X has already been forked; not reforking" >&2 fi fi } cleanx() { if [ -n "$FORKEDX" ]; then if [ -n "$XRESPROBE_DEBUG" ]; then echo "not removing temporary xprobe directory $XPROBEDIR; please do this \ by hand" >&2 else rm -rf "$XPROBEDIR" fi FORKEDX="" else if [ -n "$XRESPROBE_DEBUG" ]; then echo "not cleaning up after Xorg; not forked" >&2 fi fi } doprobe() { if [ -n "$XRESPROBE_DEBUG" ]; then echo "attempting an X probe" >&2 fi forkx RES="$("$DATADIR/lcdsize.sh" $DRIVER $LOGFILE)" } dodepthcheck() { if [ -n "$XRESPROBE_DEBUG" ]; then echo "checking for broken i8xx BIOS with no 24bpp modes" >&2 fi forkx FORCEDEPTH="$("$DATADIR/bitdepth.sh" $DRIVER $LOGFILE)" } if [ "$DRIVER" = "i810" ]; then dodepthcheck fi if [ "x$LAPTOP" = "xyes" ]; then # Allow use of ddc on intel; doprobe can result in screen corruption (LP: #127008) if [ "$(uname -m)" = "ppc" ] || [ "$(uname -m)" = "ppc64" ] || [ "x$DRIVER" = "xintel" ]; then doddc fi if [ -z "$RES" ] && [ ! "x$DRIVER" = "xintel" ]; then doprobe fi DISPTYPE="lcd/lvds" elif [ "x$DDC" = "xyes" ]; then doddc fi if [ -n "$XRESPROBE_DEBUG" ]; then echo "id: $IDENTIFIER" >&2 echo "res: $RES" >&2 echo "freq: $FREQ" >&2 echo "disptype: $DISPTYPE" >&2 if [ -n "$FORCEDEPTH" ]; then echo "depth: $FORCEDEPTH" >&2 fi fi echo "id: $IDENTIFIER" echo "res: $RES" echo "freq: $FREQ" echo "disptype: $DISPTYPE" if [ -n "$FORCEDEPTH" ]; then echo "depth: $FORCEDEPTH" fi cleanx exit $RETCODE xresprobe-0.4.24ubuntu9/COPYING0000644000000000000000000000166710220410053013064 0ustar Copyright (C) 2004-2005 Canonical Ltd, written by Daniel Stone , and Fabio M. Di Nitto Copyright: This package is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; version 2 dated June, 1991. This package is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this package; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. On Debian systems, the complete text of the GNU General Public License can be found in `/usr/share/common-licenses/GPLv2'. xresprobe-0.4.24ubuntu9/debian/0000755000000000000000000000000011261766254013270 5ustar xresprobe-0.4.24ubuntu9/debian/copyright0000644000000000000000000000157610214367723015227 0ustar Copyright (C) 2004 Canonical Software, written by Daniel Stone . Copyright: This package is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; version 2 dated June, 1991. This package is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this package; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. On Debian systems, the complete text of the GNU General Public License can be found in `/usr/share/common-licenses/GPL'. xresprobe-0.4.24ubuntu9/debian/compat0000644000000000000000000000000210214367723014461 0ustar 4 xresprobe-0.4.24ubuntu9/debian/changelog0000644000000000000000000001257111261766253015147 0ustar xresprobe (0.4.24ubuntu9) karmic; urgency=low * ddcprobe/lrmi.c: - Define *_MASK to fix FTBFS on newer kernels. -- Chris Coulson Sun, 04 Oct 2009 01:29:02 +0100 xresprobe (0.4.24ubuntu8) gutsy; urgency=low * Fix typo in previous upload -- Bryce Harrington Mon, 15 Oct 2007 01:53:14 -0700 xresprobe (0.4.24ubuntu7) gutsy; urgency=low * Expanding the previous xprobe.sh fix, to prevent calling xprobe.sh for -intel even if the ddcprobe failed. (Re-closes LP: #127008) -- Bryce Harrington Mon, 15 Oct 2007 00:18:33 -0700 xresprobe (0.4.24ubuntu6) gutsy; urgency=low [Tormod Volden] * lcdsize.sh: fix vesa sed regexp so that resolutions are returned correctly without trailing text. -- Timo Aaltonen Wed, 10 Oct 2007 18:21:05 +0300 xresprobe (0.4.24ubuntu5) gutsy; urgency=low * xorg.conf: Fix xprobe.sh failure caused by missing type1 module; this was dropped by Debian for xserver 1.3 since it's obsolete and has some security issues. (Addresses portion of fix for 127008) * xresprobe: Fix issue in alternate installation for Intel gfx laptops resulting in screen to be replaced by flashing colored blocks, by making xresprobe use ddcprobe instead of xprobe for laptops using the -intel driver. (Closes LP: #127008 and many, many duplicates) * ddcprobe.sh: Fix resolution detection error where LCD's would get configured to use one resolution less than their maximum because ddcprobe cannot tell the difference between an analog attached LCD and a CRT. (Closes LP: #27667) -- Bryce Harrington Thu, 27 Sep 2007 17:57:22 -0700 xresprobe (0.4.24ubuntu4) gutsy; urgency=low * Add support for the Intel driver -- Matthew Garrett Fri, 10 Aug 2007 21:15:44 +0100 xresprobe (0.4.24ubuntu3) feisty; urgency=low * xprobe.sh: use autoprobing only if the driver is vesa. -- Timo Aaltonen Thu, 8 Mar 2007 12:14:54 +0200 xresprobe (0.4.24ubuntu2) feisty; urgency=low * lcdsize.sh: add a missing 'getres'. -- Timo Aaltonen Wed, 7 Mar 2007 20:34:43 +0200 xresprobe (0.4.24ubuntu1) feisty; urgency=low * lcdsize.sh: - Add support for vesa. * xprobe.sh: - Don't use the bare-bones config, instead rely on the new xserver to be clever. * debian/control: - Change the Maintainer address. -- Timo Aaltonen Wed, 7 Mar 2007 15:57:51 +0200 xresprobe (0.4.24) edgy; urgency=low * Fix bashism in ddcprobe.sh. -- Colin Watson Mon, 17 Jul 2006 21:20:13 +0100 xresprobe (0.4.23debian1) unstable; urgency=low * New release based in 0.4.23 release of Ubuntu. - Fixed FTBFS bug (closes: #358334) * Fix bashism on xresprobe script (closes: #318215) * Stop to install Ubuntu changelog since we're using the same changelog file right now. -- Otavio Salvador Sat, 8 Apr 2006 11:00:30 -0300 xresprobe (0.4.23) dapper; urgency=low * Fix vbe_get_vbe_info in stub.c to match the declaration. -- LaMont Jones Wed, 22 Mar 2006 16:11:56 -0700 xresprobe (0.4.22-1) unstable; urgency=low * New upstream release * Add myself to uploaders, since octavio didn't grab this after a month -- David Nusinow Tue, 21 Mar 2006 22:03:54 -0500 xresprobe (0.4.22) dapper; urgency=low * More AMD64 support. Reset the stack pointer on each call to LRMI_int (unless overridden in regs). Without this, the second call to LRMI_int will always fail due to the stack size being too small. -- Tollef Fog Heen Mon, 20 Feb 2006 13:55:47 +0100 xresprobe (0.4.21) dapper; urgency=low * Add support for amd64. Take the thunking/x86emu parts from vbetool and reuse them here. Great and many thanks go to both Matthew Garrett and the people who wrote x86emu. -- Tollef Fog Heen Mon, 13 Feb 2006 14:42:03 +0100 xresprobe (0.4.20) dapper; urgency=low * Call Xorg explicitly, instead of guessing through the symlink. * ddcprobe: Dump the EDID for debugging purposes. -- Daniel Stone Tue, 25 Oct 2005 19:27:17 +1000 xresprobe (0.4.19) breezy; urgency=low * Apply Debian patch to fix CRT/LCD regexp in ddcprobe.sh (closes: #328551). * Remap 1408x1050 to 1400x1050 by force on savages. Yes, I know this is a horror freak show (closes: Ubuntu#15231). -- Daniel Stone Fri, 16 Sep 2005 17:36:42 +1000 xresprobe (0.4.18-1) unstable; urgency=low * New upstream release. - FTBFS: missing stubs on several architectures. Closes: #309491; -- Otavio Salvador Wed, 18 May 2005 00:43:19 -0300 xresprobe (0.4.16-1) unstable; urgency=low * Initial version for Debian. * Replace kudzu-vesa and then allow upgrades from woody. * Use simple-patch support of CDBS build system to apply patches in build time to fix issues while these patches weren't include by upstream. * debian/patches/10_gcc_2.95_fixes.diff: Added, while we were working on 0.4.14, to fix some compilation issues Petter Reinholdtsen for the patch. * debian/patches/10_gcc_2.95_fixes.diff: Droped since was merged on 0.4.16 upstream release. -- Otavio Salvador Mon, 4 Apr 2005 11:15:24 -0300 xresprobe-0.4.24ubuntu9/debian/rules0000755000000000000000000000035310415741376014347 0ustar #!/usr/bin/make -f include /usr/share/cdbs/1/rules/debhelper.mk include /usr/share/cdbs/1/class/makefile.mk include /usr/share/cdbs/1/rules/simple-patchsys.mk common-install-impl:: $(MAKE) install DESTDIR=$(CURDIR)/debian/xresprobe xresprobe-0.4.24ubuntu9/debian/control0000644000000000000000000000170610573542275014677 0ustar Source: xresprobe Section: x11 Priority: optional Maintainer: Ubuntu Core Developers XSBC-Original-Maintainer: Debian X Strike Force Uploaders: Otavio Salvador , David Nusinow Build-Depends: debhelper (>= 4.0.0), cdbs Standards-Version: 3.6.1.0 Package: xresprobe Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} Recommends: laptop-detect Replaces: kudzu-vesa Conflicts: kudzu-vesa Provides: kudzu-vesa Description: X Resolution Probe xresprobe is a package that probes both laptop and DDC-compliant screens for their standard resolutions, and returns a specifically-formatted, easy-to-parse output. . It contains the 'ddcprobe' package, which performs a DDC probe to the monitor; however, ddcprobe only works on i386 and powerpc. The laptop detection routines are, however, sufficiently generic to to be useful to other architectures. xresprobe-0.4.24ubuntu9/xprobe.sh0000755000000000000000000000310610573761031013675 0ustar #!/bin/sh # usage: xprobe.sh driver # Copyright (C) 2004 Canonical Ltd. # Author: Daniel Stone # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License with # the Debian GNU/Linux distribution in file /usr/share/common-licenses/GPL-2; # if not, write to the Free Software Foundation, Inc., 59 Temple Place, # Suite 330, Boston, MA 02111-1307 USA # # On Debian systems, the complete text of the GNU General Public # License, version 2, can be found in /usr/share/common-licenses/GPL-2. DATAPATH="/usr/share/xresprobe" DRIVER="$1" if [ -z "$DRIVER" ]; then echo "Driver name must be specified on the command line." exit 1 fi set -e if [ -z "$TMPDIR" ]; then TMPDIR="/tmp" fi XDIR="$TMPDIR/xprobe.$$" TMPCONF="$XDIR/xorg.conf" TMPLOG="$XDIR/xorg.log" TMPOUT="$XDIR/xorg-stdout.log" mkdir -m700 "$XDIR" sed -e "s/::DRIVER::/$DRIVER/;" < "$DATAPATH/xorg.conf" > "$TMPCONF" set +e if [ "$DRIVER" = "vesa" ]; then /usr/bin/Xorg :67 -ac -probeonly -logfile "$TMPLOG" > "$TMPOUT" 2>&1 else /usr/bin/Xorg :67 -ac -probeonly -logfile "$TMPLOG" -config "$TMPCONF" > "$TMPOUT" 2>&1 fi echo "$XDIR" exit 0 xresprobe-0.4.24ubuntu9/rigprobe.sh0000755000000000000000000000604210220413313014173 0ustar #!/bin/sh # Usage: rigprobe.sh driver screentype laptop # Copyright (C) 2005 Canonical Ltd # Author: Daniel Stone # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License with # the Debian GNU/Linux distribution in file /usr/share/common-licenses/GPL-2; # if not, write to the Free Software Foundation, Inc., 59 Temple Place, # Suite 330, Boston, MA 02111-1307 USA # # On Debian systems, the complete text of the GNU General Public # License, version 2, can be found in /usr/share/common-licenses/GPL-2. DATADIR="/usr/share/xresprobe" if [ -n "$XRESPROBE_DRIVER" ]; then DRIVER="$XRESPROBE_DRIVER" else DRIVER="$1" fi if [ -n "$XRESPROBE_DEBUG" ]; then echo "rigprobe: assuming $DRIVER as driver" >&2 fi SCREENTYPE="$2" LAPTOP="$3" rignoddc() { if [ -n "$XRESPROBE_DEBUG" ]; then echo "rigprobe: returning failed DDC" >&2 fi if [ -n "$LAPTOP" ]; then DISPTYPE="lcd/lvds" fi } rigddc() { if [ -n "$XRESPROBE_DEBUG" ]; then echo "rigprobe: returning DDC from $XRESPROBE_RIG_DDC" >&2 fi DDCOUT="$("$DATADIR/ddcprobe.sh" "$XRESPROBE_RIG_DDC")" RETCODE="$?" RES="$(echo "$DDCOUT" | grep "^res:" | sed -e 's/^res: *//;')" IDENTIFIER="$(echo "$DDCOUT" | grep "^name:" | sed -e 's/^name: *//;')" FREQ="$(echo "$DDCOUT" | grep "^freq:" | sed -e 's/^freq: *//;')" DISPTYPE="$(echo "$DDCOUT" | grep "^disptype:" | sed -e 's/^disptype: *//;')" # well, not necessarily, but it's a pretty good guess if [ -n "$DISPTYPE" ] && [ "$DISPTYPE" = "lcd" ]; then DISPTYPE="lcd/tmds" fi } rigprobe() { if [ -n "$XRESPROBE_DEBUG" ]; then echo "rigprobe: returning LCD size from $XRESPROBE_RIG_LOG" >&2 fi RES="$("$DATADIR/lcdsize.sh" $DRIVER $XRESPROBE_RIG_LOG)" } rigdepth() { if [ -n "$XRESPROBE_DEBUG" ]; then echo "rigprobe: checking for broken i8xx BIOS with no 24bpp modes" >&2 echo " from $XRESPROBE_RIG_LOG" >&2 fi FORCEDEPTH="$("$DATADIR/bitdepth.sh" $DRIVER $XRESPROBE_RIG_LOG)" } if [ "$XRESPROBE_RIG" = "noddc" ]; then rignoddc elif [ "$XRESPROBE_RIG" = "ddc" ]; then rigddc elif [ "$XRESPROBE_RIG" = "probe" ]; then rigprobe fi if [ "$DRIVER" = "i810" ] && [ -n "$XRESPROBE_RIG_LOG" ] && \ [ -e "$XRESPROBE_RIG_LOG" ]; then rigdepth fi if [ -n "$XRESPROBE_DEBUG" ]; then echo "id: $IDENTIFIER" >&2 echo "res: $RES" >&2 echo "freq: $FREQ" >&2 echo "disptype: $DISPTYPE" >&2 if [ -n "$FORCEDEPTH" ]; then echo "depth: $FORCEDEPTH" >&2 fi fi echo "id: $IDENTIFIER" echo "res: $RES" echo "freq: $FREQ" echo "disptype: $DISPTYPE" if [ -n "$FORCEDEPTH" ]; then echo "depth: $FORCEDEPTH" fi exit 0